As a remedy for such situations, the kernel configuration item
CONFIG_DRM_LOAD_EDID_FIRMWARE was introduced. It allows to provide an
individually prepared or corrected EDID data set in the /lib/firmware
-directory from where it is loaded via the firmware interface. The code
-(see drivers/gpu/drm/drm_edid_load.c) contains built-in data sets for
-commonly used screen resolutions (800x600, 1024x768, 1280x1024, 1600x1200,
-1680x1050, 1920x1080) as binary blobs, but the kernel source tree does
-not contain code to create these data. In order to elucidate the origin
-of the built-in binary EDID blobs and to facilitate the creation of
-individual data for a specific misbehaving monitor, commented sources
-and a Makefile environment are given here.
-
-To create binary EDID and C source code files from the existing data
-material, simply type "make" in tools/edid/.
-
-If you want to create your own EDID file, copy the file 1024x768.S,
-replace the settings with your own data and add a new target to the
-Makefile. Please note that the EDID data structure expects the timing
-values in a different way as compared to the standard X11 format.
-
-X11:
- HTimings:
- hdisp hsyncstart hsyncend htotal
- VTimings:
- vdisp vsyncstart vsyncend vtotal
-
-EDID::
-
- #define XPIX hdisp
- #define XBLANK htotal-hdisp
- #define XOFFSET hsyncstart-hdisp
- #define XPULSE hsyncend-hsyncstart
-
- #define YPIX vdisp
- #define YBLANK vtotal-vdisp
- #define YOFFSET vsyncstart-vdisp
- #define YPULSE vsyncend-vsyncstart
+directory from where it is loaded via the firmware interface.
panels may send no or incorrect EDID data sets.
This parameter allows to specify an EDID data sets
in the /lib/firmware directory that are used instead.
- Generic built-in EDID data sets are used, if one of
- edid/1024x768.bin, edid/1280x1024.bin,
- edid/1680x1050.bin, or edid/1920x1080.bin is given
- and no file with the same name exists. Details and
- instructions how to build your own EDID data are
- available in Documentation/admin-guide/edid.rst. An EDID
- data set will only be used for a particular connector,
- if its name and a colon are prepended to the EDID
- name. Each connector may use a unique EDID data
- set by separating the files with a comma. An EDID
+ An EDID data set will only be used for a particular
+ connector, if its name and a colon are prepended to
+ the EDID name. Each connector may use a unique EDID
+ data set by separating the files with a comma. An EDID
data set with no connector name will be used for
any connectors not explicitly specified.
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
- qcom,msm8974-dsi-ctrl
+ - qcom,msm8976-dsi-ctrl
- qcom,msm8996-dsi-ctrl
- qcom,msm8998-dsi-ctrl
- qcom,qcm2290-dsi-ctrl
contains:
enum:
- qcom,msm8953-dsi-ctrl
+ - qcom,msm8976-dsi-ctrl
then:
properties:
clocks:
enum:
- qcom,adreno-gmu-730.1
- qcom,adreno-gmu-740.1
+ - qcom,adreno-gmu-750.1
then:
properties:
reg:
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
items:
- - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
+ - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Imageon to
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
then:
properties:
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-8226
- qcom,dsi-phy-28nm-hpm
+ - qcom,dsi-phy-28nm-hpm-fam-b
- qcom,dsi-phy-28nm-lp
- qcom,hdmi-phy-8084
- qcom,hdmi-phy-8660
properties:
compatible:
- const: qcom,sm8650-dpu
+ enum:
+ - qcom,sm8650-dpu
+ - qcom,x1e80100-dpu
reg:
items:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dp
"^dsi@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
items:
"^phy@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dsi-phy-4nm
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 Display MDSS
+
+maintainers:
+ - Abel Vesa <abel.vesa@linaro.org>
+
+description:
+ X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DP interfaces, etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,x1e80100-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dp
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dp-phy
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,x1e80100-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
+ <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
+
+ resets = <&dispcc_core_bcr>;
+
+ power-domains = <&dispcc_gdsc>;
+
+ clocks = <&dispcc_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdp_clk>;
+ clock-names = "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,x1e80100-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_axi_clk>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_mdp_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ displayport-controller@ae90000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&dispcc_dptx0_aux_clk>,
+ <&dispcc_dptx0_link_clk>,
+ <&dispcc_dptx0_link_intf_clk>,
+ <&dispcc_dptx0_pixel0_clk>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
+ <&dispcc_mdss_dptx0_pixel0_clk_src>;
+ assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp0_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&mdss_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+...
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
- if:
properties:
compatible:
- const: qcom,sm8450-smmu-500
+ items:
+ - const: qcom,sm8450-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+
then:
properties:
clock-names:
- if:
properties:
compatible:
- const: qcom,sm8550-smmu-500
+ items:
+ - enum:
+ - qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
then:
properties:
clock-names:
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- - qcom,sm8650-smmu-500
- qcom,x1e80100-smmu-500
then:
properties:
M: David Airlie <airlied@redhat.com>
L: dri-devel@lists.freedesktop.org
S: Maintained
-T: git git://anongit.freedesktop.org/drm/drm
+T: git https://gitlab.freedesktop.org/drm/kernel.git
F: drivers/char/agp/
F: include/linux/agp*
F: include/uapi/linux/agp*
S: Maintained
B: https://gitlab.freedesktop.org/drm
C: irc://irc.oftc.net/dri-devel
-T: git git://anongit.freedesktop.org/drm/drm
+T: git https://gitlab.freedesktop.org/drm/kernel.git
F: Documentation/devicetree/bindings/display/
F: Documentation/devicetree/bindings/gpu/
F: Documentation/gpu/
module_param(mhi_timeout_ms, uint, 0600);
MODULE_PARM_DESC(mhi_timeout_ms, "MHI controller timeout value");
-static struct mhi_channel_config aic100_channels[] = {
+static const struct mhi_channel_config aic100_channels[] = {
{
.name = "QAIC_LOOPBACK",
.num = 0,
help
DRM display helpers for DisplayPort.
+config DRM_DISPLAY_DP_TUNNEL
+ bool
+ select DRM_DISPLAY_DP_HELPER
+ help
+ Enable support for DisplayPort tunnels. This allows drivers to use
+ DP tunnel features like the Bandwidth Allocation mode to maximize the
+ BW utilization for display streams on Thunderbolt links.
+
+config DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+ bool "Enable debugging the DP tunnel state"
+ depends on REF_TRACKER
+ depends on DRM_DISPLAY_DP_TUNNEL
+ depends on DEBUG_KERNEL
+ depends on EXPERT
+ help
+ Enables debugging the DP tunnel manager's state, including the
+ consistency of all managed tunnels' reference counting and the state of
+ streams contained in tunnels.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_HDCP_HELPER
bool
depends on DRM_DISPLAY_HELPER
drm_dp_helper.o \
drm_dp_mst_topology.o \
drm_dsc_helper.o
+drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TUNNEL) += \
+ drm_dp_tunnel.o
drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o
drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \
drm_hdmi_helper.o \
mutex_lock(&aux->hw_mutex);
+ /*
+ * If the device attached to the aux bus is powered down then there's
+ * no reason to attempt a transfer. Error out immediately.
+ */
+ if (aux->powered_down) {
+ ret = -EBUSY;
+ goto unlock;
+ }
+
/*
* The specification doesn't give any recommendation on how often to
* retry native transactions. We used to retry 7 times like for
}
EXPORT_SYMBOL(drm_dp_dpcd_probe);
+/**
+ * drm_dp_dpcd_set_powered() - Set whether the DP device is powered
+ * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here
+ * and the function will be a no-op.
+ * @powered: true if powered; false if not
+ *
+ * If the endpoint device on the DP AUX bus is known to be powered down
+ * then this function can be called to make future transfers fail immediately
+ * instead of needing to time out.
+ *
+ * If this function is never called then a device defaults to being powered.
+ */
+void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
+{
+ if (!aux)
+ return;
+
+ mutex_lock(&aux->hw_mutex);
+ aux->powered_down = !powered;
+ mutex_unlock(&aux->hw_mutex);
+}
+EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
+
/**
* drm_dp_dpcd_read() - read a series of bytes from the DPCD
* @aux: DisplayPort AUX channel (SST or MST)
struct drm_dp_aux_msg msg;
int err = 0;
+ if (aux->powered_down)
+ return -EBUSY;
+
dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
memset(&msg, 0, sizeof(msg));
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+/**
+ * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if vsc sdp is supported, else returns false
+ */
+bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 rx_feature;
+
+ if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+ return false;
+
+ if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) != 1) {
+ drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
+ return false;
+ }
+
+ return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
+
+/**
+ * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
+ * @vsc: vsc sdp initialized according to its purpose as defined in
+ * table 2-118 - table 2-120 in DP 1.4a specification
+ * @sdp: valid handle to the generic dp_sdp which will be packed
+ *
+ * Returns length of sdp on success and error code on failure
+ */
+ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+ struct dp_sdp *sdp)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ memset(sdp, 0, sizeof(struct dp_sdp));
+
+ /*
+ * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+ * VSC SDP Header Bytes
+ */
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ if (vsc->revision == 0x6) {
+ sdp->db[0] = 1;
+ sdp->db[3] = 1;
+ }
+
+ /*
+ * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
+ * Format as per DP 1.4a spec and DP 2.0 respectively.
+ */
+ if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
+ goto out;
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 6:
+ /* 6bpc: 0x0 */
+ break;
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ WARN(1, "Missing case %d\n", vsc->bpc);
+ return -EINVAL;
+ }
+
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+out:
+ return length;
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_pack);
+
/**
* drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
* @dpcd: DisplayPort configuration data
return 800000;
}
EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
+
+/**
+ * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
+ * @max_link_rate: max DPRX link rate in 10kbps units
+ * @max_lanes: max DPRX lane count
+ *
+ * Given a link rate and lanes, get the data bandwidth.
+ *
+ * Data bandwidth is the actual payload rate, which depends on the data
+ * bandwidth efficiency and the link rate.
+ *
+ * Note that protocol layers above the DPRX link level considered here can
+ * further limit the maximum data rate. Such layers are the MST topology (with
+ * limits on the link between the source and first branch device as well as on
+ * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
+ * which in turn can encapsulate an MST link with its own limit - with each
+ * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
+ *
+ * Returns the maximum data rate in kBps units.
+ */
+int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
+{
+ int ch_coding_efficiency =
+ drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
+
+ return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
+ ch_coding_efficiency),
+ 1000000 * 8);
+}
+EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
--- /dev/null
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/ref_tracker.h>
+#include <linux/types.h>
+
+#include <drm/drm_atomic_state_helper.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+#include <drm/display/drm_dp.h>
+#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_dp_tunnel.h>
+
+#define to_group(__private_obj) \
+ container_of(__private_obj, struct drm_dp_tunnel_group, base)
+
+#define to_group_state(__private_state) \
+ container_of(__private_state, struct drm_dp_tunnel_group_state, base)
+
+#define is_dp_tunnel_private_obj(__obj) \
+ ((__obj)->funcs == &tunnel_group_funcs)
+
+#define for_each_new_group_in_state(__state, __new_group_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_private_objs; \
+ (__i)++) \
+ for_each_if ((__state)->private_objs[__i].ptr && \
+ is_dp_tunnel_private_obj((__state)->private_objs[__i].ptr) && \
+ ((__new_group_state) = \
+ to_group_state((__state)->private_objs[__i].new_state), 1))
+
+#define for_each_old_group_in_state(__state, __old_group_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->num_private_objs; \
+ (__i)++) \
+ for_each_if ((__state)->private_objs[__i].ptr && \
+ is_dp_tunnel_private_obj((__state)->private_objs[__i].ptr) && \
+ ((__old_group_state) = \
+ to_group_state((__state)->private_objs[__i].old_state), 1))
+
+#define for_each_tunnel_in_group(__group, __tunnel) \
+ list_for_each_entry(__tunnel, &(__group)->tunnels, node)
+
+#define for_each_tunnel_state(__group_state, __tunnel_state) \
+ list_for_each_entry(__tunnel_state, &(__group_state)->tunnel_states, node)
+
+#define for_each_tunnel_state_safe(__group_state, __tunnel_state, __tunnel_state_tmp) \
+ list_for_each_entry_safe(__tunnel_state, __tunnel_state_tmp, \
+ &(__group_state)->tunnel_states, node)
+
+#define kbytes_to_mbits(__kbytes) \
+ DIV_ROUND_UP((__kbytes) * 8, 1000)
+
+#define DPTUN_BW_ARG(__bw) ((__bw) < 0 ? (__bw) : kbytes_to_mbits(__bw))
+
+#define __tun_prn(__tunnel, __level, __type, __fmt, ...) \
+ drm_##__level##__type((__tunnel)->group->mgr->dev, \
+ "[DPTUN %s][%s] " __fmt, \
+ drm_dp_tunnel_name(__tunnel), \
+ (__tunnel)->aux->name, ## \
+ __VA_ARGS__)
+
+#define tun_dbg(__tunnel, __fmt, ...) \
+ __tun_prn(__tunnel, dbg, _kms, __fmt, ## __VA_ARGS__)
+
+#define tun_dbg_stat(__tunnel, __err, __fmt, ...) do { \
+ if (__err) \
+ __tun_prn(__tunnel, dbg, _kms, __fmt " (Failed, err: %pe)\n", \
+ ## __VA_ARGS__, ERR_PTR(__err)); \
+ else \
+ __tun_prn(__tunnel, dbg, _kms, __fmt " (Ok)\n", \
+ ## __VA_ARGS__); \
+} while (0)
+
+#define tun_dbg_atomic(__tunnel, __fmt, ...) \
+ __tun_prn(__tunnel, dbg, _atomic, __fmt, ## __VA_ARGS__)
+
+#define tun_grp_dbg(__group, __fmt, ...) \
+ drm_dbg_kms((__group)->mgr->dev, \
+ "[DPTUN %s] " __fmt, \
+ drm_dp_tunnel_group_name(__group), ## \
+ __VA_ARGS__)
+
+#define DP_TUNNELING_BASE DP_TUNNELING_OUI
+
+#define __DPTUN_REG_RANGE(__start, __size) \
+ GENMASK_ULL((__start) + (__size) - 1, (__start))
+
+#define DPTUN_REG_RANGE(__addr, __size) \
+ __DPTUN_REG_RANGE((__addr) - DP_TUNNELING_BASE, (__size))
+
+#define DPTUN_REG(__addr) DPTUN_REG_RANGE(__addr, 1)
+
+#define DPTUN_INFO_REG_MASK ( \
+ DPTUN_REG_RANGE(DP_TUNNELING_OUI, DP_TUNNELING_OUI_BYTES) | \
+ DPTUN_REG_RANGE(DP_TUNNELING_DEV_ID, DP_TUNNELING_DEV_ID_BYTES) | \
+ DPTUN_REG(DP_TUNNELING_HW_REV) | \
+ DPTUN_REG(DP_TUNNELING_SW_REV_MAJOR) | \
+ DPTUN_REG(DP_TUNNELING_SW_REV_MINOR) | \
+ DPTUN_REG(DP_TUNNELING_CAPABILITIES) | \
+ DPTUN_REG(DP_IN_ADAPTER_INFO) | \
+ DPTUN_REG(DP_USB4_DRIVER_ID) | \
+ DPTUN_REG(DP_USB4_DRIVER_BW_CAPABILITY) | \
+ DPTUN_REG(DP_IN_ADAPTER_TUNNEL_INFORMATION) | \
+ DPTUN_REG(DP_BW_GRANULARITY) | \
+ DPTUN_REG(DP_ESTIMATED_BW) | \
+ DPTUN_REG(DP_ALLOCATED_BW) | \
+ DPTUN_REG(DP_TUNNELING_MAX_LINK_RATE) | \
+ DPTUN_REG(DP_TUNNELING_MAX_LANE_COUNT) | \
+ DPTUN_REG(DP_DPTX_BW_ALLOCATION_MODE_CONTROL))
+
+static const DECLARE_BITMAP(dptun_info_regs, 64) = {
+ DPTUN_INFO_REG_MASK & -1UL,
+#if BITS_PER_LONG == 32
+ DPTUN_INFO_REG_MASK >> 32,
+#endif
+};
+
+struct drm_dp_tunnel_regs {
+ u8 buf[HWEIGHT64(DPTUN_INFO_REG_MASK)];
+};
+
+struct drm_dp_tunnel_group;
+
+struct drm_dp_tunnel {
+ struct drm_dp_tunnel_group *group;
+
+ struct list_head node;
+
+ struct kref kref;
+ struct ref_tracker *tracker;
+ struct drm_dp_aux *aux;
+ char name[8];
+
+ int bw_granularity;
+ int estimated_bw;
+ int allocated_bw;
+
+ int max_dprx_rate;
+ u8 max_dprx_lane_count;
+
+ u8 adapter_id;
+
+ bool bw_alloc_supported:1;
+ bool bw_alloc_enabled:1;
+ bool has_io_error:1;
+ bool destroyed:1;
+};
+
+struct drm_dp_tunnel_group_state;
+
+struct drm_dp_tunnel_state {
+ struct drm_dp_tunnel_group_state *group_state;
+
+ struct drm_dp_tunnel_ref tunnel_ref;
+
+ struct list_head node;
+
+ u32 stream_mask;
+ int *stream_bw;
+};
+
+struct drm_dp_tunnel_group_state {
+ struct drm_private_state base;
+
+ struct list_head tunnel_states;
+};
+
+struct drm_dp_tunnel_group {
+ struct drm_private_obj base;
+ struct drm_dp_tunnel_mgr *mgr;
+
+ struct list_head tunnels;
+
+ /* available BW including the allocated_bw of all tunnels in the group */
+ int available_bw;
+
+ u8 drv_group_id;
+ char name[8];
+
+ bool active:1;
+};
+
+struct drm_dp_tunnel_mgr {
+ struct drm_device *dev;
+
+ int group_count;
+ struct drm_dp_tunnel_group *groups;
+ wait_queue_head_t bw_req_queue;
+
+#ifdef CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+ struct ref_tracker_dir ref_tracker;
+#endif
+};
+
+/*
+ * The following helpers provide a way to read out the tunneling DPCD
+ * registers with a minimal amount of AUX transfers (1 transfer per contiguous
+ * range, as permitted by the 16 byte per transfer AUX limit), not accessing
+ * other registers to avoid any read side-effects.
+ */
+static int next_reg_area(int *offset)
+{
+ *offset = find_next_bit(dptun_info_regs, 64, *offset);
+
+ return find_next_zero_bit(dptun_info_regs, 64, *offset + 1) - *offset;
+}
+
+#define tunnel_reg_ptr(__regs, __address) ({ \
+ WARN_ON(!test_bit((__address) - DP_TUNNELING_BASE, dptun_info_regs)); \
+ &(__regs)->buf[bitmap_weight(dptun_info_regs, (__address) - DP_TUNNELING_BASE)]; \
+})
+
+static int read_tunnel_regs(struct drm_dp_aux *aux, struct drm_dp_tunnel_regs *regs)
+{
+ int offset = 0;
+ int len;
+
+ while ((len = next_reg_area(&offset))) {
+ int address = DP_TUNNELING_BASE + offset;
+
+ if (drm_dp_dpcd_read(aux, address, tunnel_reg_ptr(regs, address), len) < 0)
+ return -EIO;
+
+ offset += len;
+ }
+
+ return 0;
+}
+
+static u8 tunnel_reg(const struct drm_dp_tunnel_regs *regs, int address)
+{
+ return *tunnel_reg_ptr(regs, address);
+}
+
+static u8 tunnel_reg_drv_group_id(const struct drm_dp_tunnel_regs *regs)
+{
+ u8 drv_id = tunnel_reg(regs, DP_USB4_DRIVER_ID) & DP_USB4_DRIVER_ID_MASK;
+ u8 group_id = tunnel_reg(regs, DP_IN_ADAPTER_TUNNEL_INFORMATION) & DP_GROUP_ID_MASK;
+
+ if (!group_id)
+ return 0;
+
+ return (drv_id << DP_GROUP_ID_BITS) | group_id;
+}
+
+/* Return granularity in kB/s units */
+static int tunnel_reg_bw_granularity(const struct drm_dp_tunnel_regs *regs)
+{
+ int gr = tunnel_reg(regs, DP_BW_GRANULARITY) & DP_BW_GRANULARITY_MASK;
+
+ if (gr > 2)
+ return -1;
+
+ return (250000 << gr) / 8;
+}
+
+static int tunnel_reg_max_dprx_rate(const struct drm_dp_tunnel_regs *regs)
+{
+ u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);
+
+ return drm_dp_bw_code_to_link_rate(bw_code);
+}
+
+static int tunnel_reg_max_dprx_lane_count(const struct drm_dp_tunnel_regs *regs)
+{
+ return tunnel_reg(regs, DP_TUNNELING_MAX_LANE_COUNT) &
+ DP_TUNNELING_MAX_LANE_COUNT_MASK;
+}
+
+static bool tunnel_reg_bw_alloc_supported(const struct drm_dp_tunnel_regs *regs)
+{
+ u8 cap_mask = DP_TUNNELING_SUPPORT | DP_IN_BW_ALLOCATION_MODE_SUPPORT;
+
+ if ((tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) & cap_mask) != cap_mask)
+ return false;
+
+ return tunnel_reg(regs, DP_USB4_DRIVER_BW_CAPABILITY) &
+ DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT;
+}
+
+static bool tunnel_reg_bw_alloc_enabled(const struct drm_dp_tunnel_regs *regs)
+{
+ return tunnel_reg(regs, DP_DPTX_BW_ALLOCATION_MODE_CONTROL) &
+ DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE;
+}
+
+static u8 tunnel_group_drv_id(u8 drv_group_id)
+{
+ return drv_group_id >> DP_GROUP_ID_BITS;
+}
+
+static u8 tunnel_group_id(u8 drv_group_id)
+{
+ return drv_group_id & DP_GROUP_ID_MASK;
+}
+
+const char *drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->name;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_name);
+
+static const char *drm_dp_tunnel_group_name(const struct drm_dp_tunnel_group *group)
+{
+ return group->name;
+}
+
+static struct drm_dp_tunnel_group *
+lookup_or_alloc_group(struct drm_dp_tunnel_mgr *mgr, u8 drv_group_id)
+{
+ struct drm_dp_tunnel_group *group = NULL;
+ int i;
+
+ for (i = 0; i < mgr->group_count; i++) {
+ /*
+ * A tunnel group with 0 group ID shouldn't have more than one
+ * tunnels.
+ */
+ if (tunnel_group_id(drv_group_id) &&
+ mgr->groups[i].drv_group_id == drv_group_id)
+ return &mgr->groups[i];
+
+ if (!group && !mgr->groups[i].active)
+ group = &mgr->groups[i];
+ }
+
+ if (!group) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: Can't allocate more tunnel groups\n");
+ return NULL;
+ }
+
+ group->drv_group_id = drv_group_id;
+ group->active = true;
+
+ /*
+ * The group name format here and elsewhere: Driver-ID:Group-ID:*
+ * (* standing for all DP-Adapters/tunnels in the group).
+ */
+ snprintf(group->name, sizeof(group->name), "%d:%d:*",
+ tunnel_group_drv_id(drv_group_id) & ((1 << DP_GROUP_ID_BITS) - 1),
+ tunnel_group_id(drv_group_id) & ((1 << DP_USB4_DRIVER_ID_BITS) - 1));
+
+ return group;
+}
+
+static void free_group(struct drm_dp_tunnel_group *group)
+{
+ struct drm_dp_tunnel_mgr *mgr = group->mgr;
+
+ if (drm_WARN_ON(mgr->dev, !list_empty(&group->tunnels)))
+ return;
+
+ group->drv_group_id = 0;
+ group->available_bw = -1;
+ group->active = false;
+}
+
+static struct drm_dp_tunnel *
+tunnel_get(struct drm_dp_tunnel *tunnel)
+{
+ kref_get(&tunnel->kref);
+
+ return tunnel;
+}
+
+static void free_tunnel(struct kref *kref)
+{
+ struct drm_dp_tunnel *tunnel = container_of(kref, typeof(*tunnel), kref);
+ struct drm_dp_tunnel_group *group = tunnel->group;
+
+ list_del(&tunnel->node);
+ if (list_empty(&group->tunnels))
+ free_group(group);
+
+ kfree(tunnel);
+}
+
+static void tunnel_put(struct drm_dp_tunnel *tunnel)
+{
+ kref_put(&tunnel->kref, free_tunnel);
+}
+
+#ifdef CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+static void track_tunnel_ref(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+ ref_tracker_alloc(&tunnel->group->mgr->ref_tracker,
+ tracker, GFP_KERNEL);
+}
+
+static void untrack_tunnel_ref(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+ ref_tracker_free(&tunnel->group->mgr->ref_tracker,
+ tracker);
+}
+#else
+static void track_tunnel_ref(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+}
+
+static void untrack_tunnel_ref(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+}
+#endif
+
+/**
+ * drm_dp_tunnel_get - Get a reference for a DP tunnel
+ * @tunnel: Tunnel object
+ * @tracker: Debug tracker for the reference
+ *
+ * Get a reference for @tunnel, along with a debug tracker to help locating
+ * the source of a reference leak/double reference put etc. issue.
+ *
+ * The reference must be dropped after use calling drm_dp_tunnel_put()
+ * passing @tunnel and *@tracker returned from here.
+ *
+ * Returns @tunnel - as a convenience - along with *@tracker.
+ */
+struct drm_dp_tunnel *
+drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+ track_tunnel_ref(tunnel, tracker);
+
+ return tunnel_get(tunnel);
+}
+EXPORT_SYMBOL(drm_dp_tunnel_get);
+
+/**
+ * drm_dp_tunnel_put - Put a reference for a DP tunnel
+ * @tunnel - Tunnel object
+ * @tracker - Debug tracker for the reference
+ *
+ * Put a reference for @tunnel along with its debug *@tracker, which
+ * was obtained with drm_dp_tunnel_get().
+ */
+void drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel,
+ struct ref_tracker **tracker)
+{
+ untrack_tunnel_ref(tunnel, tracker);
+
+ tunnel_put(tunnel);
+}
+EXPORT_SYMBOL(drm_dp_tunnel_put);
+
+static bool add_tunnel_to_group(struct drm_dp_tunnel_mgr *mgr,
+ u8 drv_group_id,
+ struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_group *group;
+
+ group = lookup_or_alloc_group(mgr, drv_group_id);
+ if (!group)
+ return false;
+
+ tunnel->group = group;
+ list_add(&tunnel->node, &group->tunnels);
+
+ return true;
+}
+
+static struct drm_dp_tunnel *
+create_tunnel(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux,
+ const struct drm_dp_tunnel_regs *regs)
+{
+ u8 drv_group_id = tunnel_reg_drv_group_id(regs);
+ struct drm_dp_tunnel *tunnel;
+
+ tunnel = kzalloc(sizeof(*tunnel), GFP_KERNEL);
+ if (!tunnel)
+ return NULL;
+
+ INIT_LIST_HEAD(&tunnel->node);
+
+ kref_init(&tunnel->kref);
+
+ tunnel->aux = aux;
+
+ tunnel->adapter_id = tunnel_reg(regs, DP_IN_ADAPTER_INFO) & DP_IN_ADAPTER_NUMBER_MASK;
+
+ snprintf(tunnel->name, sizeof(tunnel->name), "%d:%d:%d",
+ tunnel_group_drv_id(drv_group_id) & ((1 << DP_GROUP_ID_BITS) - 1),
+ tunnel_group_id(drv_group_id) & ((1 << DP_USB4_DRIVER_ID_BITS) - 1),
+ tunnel->adapter_id & ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1));
+
+ tunnel->bw_granularity = tunnel_reg_bw_granularity(regs);
+ tunnel->allocated_bw = tunnel_reg(regs, DP_ALLOCATED_BW) *
+ tunnel->bw_granularity;
+ /*
+ * An initial allocated BW of 0 indicates an undefined state: the
+ * actual allocation is determined by the TBT CM, usually following a
+ * legacy allocation policy (based on the max DPRX caps). From the
+ * driver's POV the state becomes defined only after the first
+ * allocation request.
+ */
+ if (!tunnel->allocated_bw)
+ tunnel->allocated_bw = -1;
+
+ tunnel->bw_alloc_supported = tunnel_reg_bw_alloc_supported(regs);
+ tunnel->bw_alloc_enabled = tunnel_reg_bw_alloc_enabled(regs);
+
+ if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) {
+ kfree(tunnel);
+
+ return NULL;
+ }
+
+ track_tunnel_ref(tunnel, &tunnel->tracker);
+
+ return tunnel;
+}
+
+static void destroy_tunnel(struct drm_dp_tunnel *tunnel)
+{
+ untrack_tunnel_ref(tunnel, &tunnel->tracker);
+ tunnel_put(tunnel);
+}
+
+/**
+ * drm_dp_tunnel_set_io_error - Set the IO error flag for a DP tunnel
+ * @tunnel: Tunnel object
+ *
+ * Set the IO error flag for @tunnel. Drivers can call this function upon
+ * detecting a failure that affects the tunnel functionality, for instance
+ * after a DP AUX transfer failure on the port @tunnel is connected to.
+ *
+ * This disables further management of @tunnel, including any related
+ * AUX accesses for tunneling DPCD registers, returning error to the
+ * initiators of these. The driver is supposed to drop this tunnel and -
+ * optionally - recreate it.
+ */
+void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel)
+{
+ tunnel->has_io_error = true;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_set_io_error);
+
+#define SKIP_DPRX_CAPS_CHECK BIT(0)
+#define ALLOW_ALLOCATED_BW_CHANGE BIT(1)
+static bool tunnel_regs_are_valid(struct drm_dp_tunnel_mgr *mgr,
+ const struct drm_dp_tunnel_regs *regs,
+ unsigned int flags)
+{
+ u8 drv_group_id = tunnel_reg_drv_group_id(regs);
+ bool check_dprx = !(flags & SKIP_DPRX_CAPS_CHECK);
+ bool ret = true;
+
+ if (!tunnel_reg_bw_alloc_supported(regs)) {
+ if (tunnel_group_id(drv_group_id)) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: A non-zero group ID is only allowed with BWA support\n");
+ ret = false;
+ }
+
+ if (tunnel_reg(regs, DP_ALLOCATED_BW)) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: BW is allocated without BWA support\n");
+ ret = false;
+ }
+
+ return ret;
+ }
+
+ if (!tunnel_group_id(drv_group_id)) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: BWA support requires a non-zero group ID\n");
+ ret = false;
+ }
+
+ if (check_dprx && hweight8(tunnel_reg_max_dprx_lane_count(regs)) != 1) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: Invalid DPRX lane count: %d\n",
+ tunnel_reg_max_dprx_lane_count(regs));
+
+ ret = false;
+ }
+
+ if (check_dprx && !tunnel_reg_max_dprx_rate(regs)) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: DPRX rate is 0\n");
+
+ ret = false;
+ }
+
+ if (tunnel_reg_bw_granularity(regs) < 0) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: Invalid BW granularity\n");
+
+ ret = false;
+ }
+
+ if (tunnel_reg(regs, DP_ALLOCATED_BW) > tunnel_reg(regs, DP_ESTIMATED_BW)) {
+ drm_dbg_kms(mgr->dev,
+ "DPTUN: Allocated BW %d > estimated BW %d Mb/s\n",
+ DPTUN_BW_ARG(tunnel_reg(regs, DP_ALLOCATED_BW) *
+ tunnel_reg_bw_granularity(regs)),
+ DPTUN_BW_ARG(tunnel_reg(regs, DP_ESTIMATED_BW) *
+ tunnel_reg_bw_granularity(regs)));
+
+ ret = false;
+ }
+
+ return ret;
+}
+
+static int tunnel_allocated_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return max(tunnel->allocated_bw, 0);
+}
+
+static bool tunnel_info_changes_are_valid(struct drm_dp_tunnel *tunnel,
+ const struct drm_dp_tunnel_regs *regs,
+ unsigned int flags)
+{
+ u8 new_drv_group_id = tunnel_reg_drv_group_id(regs);
+ bool ret = true;
+
+ if (tunnel->bw_alloc_supported != tunnel_reg_bw_alloc_supported(regs)) {
+ tun_dbg(tunnel,
+ "BW alloc support has changed %s -> %s\n",
+ str_yes_no(tunnel->bw_alloc_supported),
+ str_yes_no(tunnel_reg_bw_alloc_supported(regs)));
+
+ ret = false;
+ }
+
+ if (tunnel->group->drv_group_id != new_drv_group_id) {
+ tun_dbg(tunnel,
+ "Driver/group ID has changed %d:%d:* -> %d:%d:*\n",
+ tunnel_group_drv_id(tunnel->group->drv_group_id),
+ tunnel_group_id(tunnel->group->drv_group_id),
+ tunnel_group_drv_id(new_drv_group_id),
+ tunnel_group_id(new_drv_group_id));
+
+ ret = false;
+ }
+
+ if (!tunnel->bw_alloc_supported)
+ return ret;
+
+ if (tunnel->bw_granularity != tunnel_reg_bw_granularity(regs)) {
+ tun_dbg(tunnel,
+ "BW granularity has changed: %d -> %d Mb/s\n",
+ DPTUN_BW_ARG(tunnel->bw_granularity),
+ DPTUN_BW_ARG(tunnel_reg_bw_granularity(regs)));
+
+ ret = false;
+ }
+
+ /*
+ * On some devices at least the BW alloc mode enabled status is always
+ * reported as 0, so skip checking that here.
+ */
+
+ if (!(flags & ALLOW_ALLOCATED_BW_CHANGE) &&
+ tunnel_allocated_bw(tunnel) !=
+ tunnel_reg(regs, DP_ALLOCATED_BW) * tunnel->bw_granularity) {
+ tun_dbg(tunnel,
+ "Allocated BW has changed: %d -> %d Mb/s\n",
+ DPTUN_BW_ARG(tunnel->allocated_bw),
+ DPTUN_BW_ARG(tunnel_reg(regs, DP_ALLOCATED_BW) * tunnel->bw_granularity));
+
+ ret = false;
+ }
+
+ return ret;
+}
+
+static int
+read_and_verify_tunnel_regs(struct drm_dp_tunnel *tunnel,
+ struct drm_dp_tunnel_regs *regs,
+ unsigned int flags)
+{
+ int err;
+
+ err = read_tunnel_regs(tunnel->aux, regs);
+ if (err < 0) {
+ drm_dp_tunnel_set_io_error(tunnel);
+
+ return err;
+ }
+
+ if (!tunnel_regs_are_valid(tunnel->group->mgr, regs, flags))
+ return -EINVAL;
+
+ if (!tunnel_info_changes_are_valid(tunnel, regs, flags))
+ return -EINVAL;
+
+ return 0;
+}
+
+static bool update_dprx_caps(struct drm_dp_tunnel *tunnel, const struct drm_dp_tunnel_regs *regs)
+{
+ bool changed = false;
+
+ if (tunnel_reg_max_dprx_rate(regs) != tunnel->max_dprx_rate) {
+ tunnel->max_dprx_rate = tunnel_reg_max_dprx_rate(regs);
+ changed = true;
+ }
+
+ if (tunnel_reg_max_dprx_lane_count(regs) != tunnel->max_dprx_lane_count) {
+ tunnel->max_dprx_lane_count = tunnel_reg_max_dprx_lane_count(regs);
+ changed = true;
+ }
+
+ return changed;
+}
+
+static int dev_id_len(const u8 *dev_id, int max_len)
+{
+ while (max_len && dev_id[max_len - 1] == '\0')
+ max_len--;
+
+ return max_len;
+}
+
+static int get_max_dprx_bw(const struct drm_dp_tunnel *tunnel)
+{
+ int max_dprx_bw = drm_dp_max_dprx_data_rate(tunnel->max_dprx_rate,
+ tunnel->max_dprx_lane_count);
+
+ /*
+ * A BW request of roundup(max_dprx_bw, tunnel->bw_granularity) results in
+ * an allocation of max_dprx_bw. A BW request above this rounded-up
+ * value will fail.
+ */
+ return min(roundup(max_dprx_bw, tunnel->bw_granularity),
+ MAX_DP_REQUEST_BW * tunnel->bw_granularity);
+}
+
+static int get_max_tunnel_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return min(get_max_dprx_bw(tunnel), tunnel->group->available_bw);
+}
+
+/**
+ * drm_dp_tunnel_detect - Detect DP tunnel on the link
+ * @mgr: Tunnel manager
+ * @aux: DP AUX on which the tunnel will be detected
+ *
+ * Detect if there is any DP tunnel on the link and add it to the tunnel
+ * group's tunnel list.
+ *
+ * Returns a pointer to a tunnel on success, or an ERR_PTR() error on
+ * failure.
+ */
+struct drm_dp_tunnel *
+drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux)
+{
+ struct drm_dp_tunnel_regs regs;
+ struct drm_dp_tunnel *tunnel;
+ int err;
+
+ err = read_tunnel_regs(aux, ®s);
+ if (err)
+ return ERR_PTR(err);
+
+ if (!(tunnel_reg(®s, DP_TUNNELING_CAPABILITIES) &
+ DP_TUNNELING_SUPPORT))
+ return ERR_PTR(-ENODEV);
+
+ /* The DPRX caps are valid only after enabling BW alloc mode. */
+ if (!tunnel_regs_are_valid(mgr, ®s, SKIP_DPRX_CAPS_CHECK))
+ return ERR_PTR(-EINVAL);
+
+ tunnel = create_tunnel(mgr, aux, ®s);
+ if (!tunnel)
+ return ERR_PTR(-ENOMEM);
+
+ tun_dbg(tunnel,
+ "OUI:%*phD DevID:%*pE Rev-HW:%d.%d SW:%d.%d PR-Sup:%s BWA-Sup:%s BWA-En:%s\n",
+ DP_TUNNELING_OUI_BYTES,
+ tunnel_reg_ptr(®s, DP_TUNNELING_OUI),
+ dev_id_len(tunnel_reg_ptr(®s, DP_TUNNELING_DEV_ID), DP_TUNNELING_DEV_ID_BYTES),
+ tunnel_reg_ptr(®s, DP_TUNNELING_DEV_ID),
+ (tunnel_reg(®s, DP_TUNNELING_HW_REV) & DP_TUNNELING_HW_REV_MAJOR_MASK) >>
+ DP_TUNNELING_HW_REV_MAJOR_SHIFT,
+ (tunnel_reg(®s, DP_TUNNELING_HW_REV) & DP_TUNNELING_HW_REV_MINOR_MASK) >>
+ DP_TUNNELING_HW_REV_MINOR_SHIFT,
+ tunnel_reg(®s, DP_TUNNELING_SW_REV_MAJOR),
+ tunnel_reg(®s, DP_TUNNELING_SW_REV_MINOR),
+ str_yes_no(tunnel_reg(®s, DP_TUNNELING_CAPABILITIES) &
+ DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT),
+ str_yes_no(tunnel->bw_alloc_supported),
+ str_yes_no(tunnel->bw_alloc_enabled));
+
+ return tunnel;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_detect);
+
+/**
+ * drm_dp_tunnel_destroy - Destroy tunnel object
+ * @tunnel: Tunnel object
+ *
+ * Remove the tunnel from the tunnel topology and destroy it.
+ *
+ * Returns 0 on success, -ENODEV if the tunnel has been destroyed already.
+ */
+int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel)
+{
+ if (!tunnel)
+ return 0;
+
+ if (drm_WARN_ON(tunnel->group->mgr->dev, tunnel->destroyed))
+ return -ENODEV;
+
+ tun_dbg(tunnel, "destroying\n");
+
+ tunnel->destroyed = true;
+ destroy_tunnel(tunnel);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_destroy);
+
+static int check_tunnel(const struct drm_dp_tunnel *tunnel)
+{
+ if (tunnel->destroyed)
+ return -ENODEV;
+
+ if (tunnel->has_io_error)
+ return -EIO;
+
+ return 0;
+}
+
+static int group_allocated_bw(struct drm_dp_tunnel_group *group)
+{
+ struct drm_dp_tunnel *tunnel;
+ int group_allocated_bw = 0;
+
+ for_each_tunnel_in_group(group, tunnel) {
+ if (check_tunnel(tunnel) == 0 &&
+ tunnel->bw_alloc_enabled)
+ group_allocated_bw += tunnel_allocated_bw(tunnel);
+ }
+
+ return group_allocated_bw;
+}
+
+/*
+ * The estimated BW reported by the TBT Connection Manager for each tunnel in
+ * a group includes the BW already allocated for the given tunnel and the
+ * unallocated BW which is free to be used by any tunnel in the group.
+ */
+static int group_free_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->estimated_bw - tunnel_allocated_bw(tunnel);
+}
+
+static int calc_group_available_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return group_allocated_bw(tunnel->group) +
+ group_free_bw(tunnel);
+}
+
+static int update_group_available_bw(struct drm_dp_tunnel *tunnel,
+ const struct drm_dp_tunnel_regs *regs)
+{
+ struct drm_dp_tunnel *tunnel_iter;
+ int group_available_bw;
+ bool changed;
+
+ tunnel->estimated_bw = tunnel_reg(regs, DP_ESTIMATED_BW) * tunnel->bw_granularity;
+
+ if (calc_group_available_bw(tunnel) == tunnel->group->available_bw)
+ return 0;
+
+ for_each_tunnel_in_group(tunnel->group, tunnel_iter) {
+ int err;
+
+ if (tunnel_iter == tunnel)
+ continue;
+
+ if (check_tunnel(tunnel_iter) != 0 ||
+ !tunnel_iter->bw_alloc_enabled)
+ continue;
+
+ err = drm_dp_dpcd_probe(tunnel_iter->aux, DP_DPCD_REV);
+ if (err) {
+ tun_dbg(tunnel_iter,
+ "Probe failed, assume disconnected (err %pe)\n",
+ ERR_PTR(err));
+ drm_dp_tunnel_set_io_error(tunnel_iter);
+ }
+ }
+
+ group_available_bw = calc_group_available_bw(tunnel);
+
+ tun_dbg(tunnel, "Updated group available BW: %d->%d\n",
+ DPTUN_BW_ARG(tunnel->group->available_bw),
+ DPTUN_BW_ARG(group_available_bw));
+
+ changed = tunnel->group->available_bw != group_available_bw;
+
+ tunnel->group->available_bw = group_available_bw;
+
+ return changed ? 1 : 0;
+}
+
+static int set_bw_alloc_mode(struct drm_dp_tunnel *tunnel, bool enable)
+{
+ u8 mask = DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE | DP_UNMASK_BW_ALLOCATION_IRQ;
+ u8 val;
+
+ if (drm_dp_dpcd_readb(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, &val) < 0)
+ goto out_err;
+
+ if (enable)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ if (drm_dp_dpcd_writeb(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, val) < 0)
+ goto out_err;
+
+ tunnel->bw_alloc_enabled = enable;
+
+ return 0;
+
+out_err:
+ drm_dp_tunnel_set_io_error(tunnel);
+
+ return -EIO;
+}
+
+/**
+ * drm_dp_tunnel_enable_bw_alloc - Enable DP tunnel BW allocation mode
+ * @tunnel: Tunnel object
+ *
+ * Enable the DP tunnel BW allocation mode on @tunnel if it supports it.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_regs regs;
+ int err;
+
+ err = check_tunnel(tunnel);
+ if (err)
+ return err;
+
+ if (!tunnel->bw_alloc_supported)
+ return -EOPNOTSUPP;
+
+ if (!tunnel_group_id(tunnel->group->drv_group_id))
+ return -EINVAL;
+
+ err = set_bw_alloc_mode(tunnel, true);
+ if (err)
+ goto out;
+
+ /*
+ * After a BWA disable/re-enable sequence the allocated BW can either
+ * stay at its last requested value or, for instance after system
+ * suspend/resume, TBT CM can reset back the allocation to the amount
+ * allocated in the legacy/non-BWA mode. Accordingly allow for the
+ * allocation to change wrt. the last SW state.
+ */
+ err = read_and_verify_tunnel_regs(tunnel, ®s,
+ ALLOW_ALLOCATED_BW_CHANGE);
+ if (err) {
+ set_bw_alloc_mode(tunnel, false);
+
+ goto out;
+ }
+
+ if (!tunnel->max_dprx_rate)
+ update_dprx_caps(tunnel, ®s);
+
+ if (tunnel->group->available_bw == -1) {
+ err = update_group_available_bw(tunnel, ®s);
+ if (err > 0)
+ err = 0;
+ }
+out:
+ tun_dbg_stat(tunnel, err,
+ "Enabling BW alloc mode: DPRX:%dx%d Group alloc:%d/%d Mb/s",
+ tunnel->max_dprx_rate / 100, tunnel->max_dprx_lane_count,
+ DPTUN_BW_ARG(group_allocated_bw(tunnel->group)),
+ DPTUN_BW_ARG(tunnel->group->available_bw));
+
+ return err;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_enable_bw_alloc);
+
+/**
+ * drm_dp_tunnel_disable_bw_alloc - Disable DP tunnel BW allocation mode
+ * @tunnel: Tunnel object
+ *
+ * Disable the DP tunnel BW allocation mode on @tunnel.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel)
+{
+ int err;
+
+ err = check_tunnel(tunnel);
+ if (err)
+ return err;
+
+ tunnel->allocated_bw = -1;
+
+ err = set_bw_alloc_mode(tunnel, false);
+
+ tun_dbg_stat(tunnel, err, "Disabling BW alloc mode");
+
+ return err;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_disable_bw_alloc);
+
+/**
+ * drm_dp_tunnel_bw_alloc_is_enabled - Query the BW allocation mode enabled state
+ * @tunnel: Tunnel object
+ *
+ * Query if the BW allocation mode is enabled for @tunnel.
+ *
+ * Returns %true if the BW allocation mode is enabled for @tunnel.
+ */
+bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel && tunnel->bw_alloc_enabled;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled);
+
+static int clear_bw_req_state(struct drm_dp_aux *aux)
+{
+ u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;
+
+ if (drm_dp_dpcd_writeb(aux, DP_TUNNELING_STATUS, bw_req_mask) < 0)
+ return -EIO;
+
+ return 0;
+}
+
+static int bw_req_complete(struct drm_dp_aux *aux, bool *status_changed)
+{
+ u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;
+ u8 status_change_mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;
+ u8 val;
+ int err;
+
+ if (drm_dp_dpcd_readb(aux, DP_TUNNELING_STATUS, &val) < 0)
+ return -EIO;
+
+ *status_changed = val & status_change_mask;
+
+ val &= bw_req_mask;
+
+ if (!val)
+ return -EAGAIN;
+
+ err = clear_bw_req_state(aux);
+ if (err < 0)
+ return err;
+
+ return val == DP_BW_REQUEST_SUCCEEDED ? 0 : -ENOSPC;
+}
+
+static int allocate_tunnel_bw(struct drm_dp_tunnel *tunnel, int bw)
+{
+ struct drm_dp_tunnel_mgr *mgr = tunnel->group->mgr;
+ int request_bw = DIV_ROUND_UP(bw, tunnel->bw_granularity);
+ DEFINE_WAIT_FUNC(wait, woken_wake_function);
+ long timeout;
+ int err;
+
+ if (bw < 0) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (request_bw * tunnel->bw_granularity == tunnel->allocated_bw)
+ return 0;
+
+ /* Atomic check should prevent the following. */
+ if (drm_WARN_ON(mgr->dev, request_bw > MAX_DP_REQUEST_BW)) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ err = clear_bw_req_state(tunnel->aux);
+ if (err)
+ goto out;
+
+ if (drm_dp_dpcd_writeb(tunnel->aux, DP_REQUEST_BW, request_bw) < 0) {
+ err = -EIO;
+ goto out;
+ }
+
+ timeout = msecs_to_jiffies(3000);
+ add_wait_queue(&mgr->bw_req_queue, &wait);
+
+ for (;;) {
+ bool status_changed;
+
+ err = bw_req_complete(tunnel->aux, &status_changed);
+ if (err != -EAGAIN)
+ break;
+
+ if (status_changed) {
+ struct drm_dp_tunnel_regs regs;
+
+ err = read_and_verify_tunnel_regs(tunnel, ®s,
+ ALLOW_ALLOCATED_BW_CHANGE);
+ if (err)
+ break;
+ }
+
+ if (!timeout) {
+ err = -ETIMEDOUT;
+ break;
+ }
+
+ timeout = wait_woken(&wait, TASK_UNINTERRUPTIBLE, timeout);
+ };
+
+ remove_wait_queue(&mgr->bw_req_queue, &wait);
+
+ if (err)
+ goto out;
+
+ tunnel->allocated_bw = request_bw * tunnel->bw_granularity;
+
+out:
+ tun_dbg_stat(tunnel, err, "Allocating %d/%d Mb/s for tunnel: Group alloc:%d/%d Mb/s",
+ DPTUN_BW_ARG(request_bw * tunnel->bw_granularity),
+ DPTUN_BW_ARG(get_max_tunnel_bw(tunnel)),
+ DPTUN_BW_ARG(group_allocated_bw(tunnel->group)),
+ DPTUN_BW_ARG(tunnel->group->available_bw));
+
+ if (err == -EIO)
+ drm_dp_tunnel_set_io_error(tunnel);
+
+ return err;
+}
+
+/**
+ * drm_dp_tunnel_alloc_bw - Allocate BW for a DP tunnel
+ * @tunnel: Tunnel object
+ * @bw: BW in kB/s units
+ *
+ * Allocate @bw kB/s for @tunnel. The allocated BW must be freed after use by
+ * calling this function for the same tunnel setting @bw to 0.
+ *
+ * Returns 0 in case of success, a negative error code otherwise.
+ */
+int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
+{
+ int err;
+
+ err = check_tunnel(tunnel);
+ if (err)
+ return err;
+
+ return allocate_tunnel_bw(tunnel, bw);
+}
+EXPORT_SYMBOL(drm_dp_tunnel_alloc_bw);
+
+/**
+ * drm_dp_tunnel_atomic_get_allocated_bw - Get the BW allocated for a DP tunnel
+ * @tunnel: Tunnel object
+ *
+ * Get the current BW allocated for @tunnel. After the tunnel is created /
+ * resumed and the BW allocation mode is enabled for it, the allocation
+ * becomes determined only after the first allocation request by the driver
+ * calling drm_dp_tunnel_alloc_bw().
+ *
+ * Return the BW allocated for the tunnel, or -1 if the allocation is
+ * undetermined.
+ */
+int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->allocated_bw;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_get_allocated_bw);
+
+/*
+ * Return 0 if the status hasn't changed, 1 if the status has changed, a
+ * negative error code in case of an I/O failure.
+ */
+static int check_and_clear_status_change(struct drm_dp_tunnel *tunnel)
+{
+ u8 mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;
+ u8 val;
+
+ if (drm_dp_dpcd_readb(tunnel->aux, DP_TUNNELING_STATUS, &val) < 0)
+ goto out_err;
+
+ val &= mask;
+
+ if (val) {
+ if (drm_dp_dpcd_writeb(tunnel->aux, DP_TUNNELING_STATUS, val) < 0)
+ goto out_err;
+
+ return 1;
+ }
+
+ if (!drm_dp_tunnel_bw_alloc_is_enabled(tunnel))
+ return 0;
+
+ /*
+ * Check for estimated BW changes explicitly to account for lost
+ * BW change notifications.
+ */
+ if (drm_dp_dpcd_readb(tunnel->aux, DP_ESTIMATED_BW, &val) < 0)
+ goto out_err;
+
+ if (val * tunnel->bw_granularity != tunnel->estimated_bw)
+ return 1;
+
+ return 0;
+
+out_err:
+ drm_dp_tunnel_set_io_error(tunnel);
+
+ return -EIO;
+}
+
+/**
+ * drm_dp_tunnel_update_state - Update DP tunnel SW state with the HW state
+ * @tunnel: Tunnel object
+ *
+ * Update the SW state of @tunnel with the HW state.
+ *
+ * Returns 0 if the state has not changed, 1 if it has changed and got updated
+ * successfully and a negative error code otherwise.
+ */
+int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_regs regs;
+ bool changed = false;
+ int ret;
+
+ ret = check_tunnel(tunnel);
+ if (ret < 0)
+ return ret;
+
+ ret = check_and_clear_status_change(tunnel);
+ if (ret < 0)
+ goto out;
+
+ if (!ret)
+ return 0;
+
+ ret = read_and_verify_tunnel_regs(tunnel, ®s, 0);
+ if (ret)
+ goto out;
+
+ if (update_dprx_caps(tunnel, ®s))
+ changed = true;
+
+ ret = update_group_available_bw(tunnel, ®s);
+ if (ret == 1)
+ changed = true;
+
+out:
+ tun_dbg_stat(tunnel, ret < 0 ? ret : 0,
+ "State update: Changed:%s DPRX:%dx%d Tunnel alloc:%d/%d Group alloc:%d/%d Mb/s",
+ str_yes_no(changed),
+ tunnel->max_dprx_rate / 100, tunnel->max_dprx_lane_count,
+ DPTUN_BW_ARG(tunnel->allocated_bw),
+ DPTUN_BW_ARG(get_max_tunnel_bw(tunnel)),
+ DPTUN_BW_ARG(group_allocated_bw(tunnel->group)),
+ DPTUN_BW_ARG(tunnel->group->available_bw));
+
+ if (ret < 0)
+ return ret;
+
+ if (changed)
+ return 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_update_state);
+
+/*
+ * drm_dp_tunnel_handle_irq - Handle DP tunnel IRQs
+ *
+ * Handle any pending DP tunnel IRQs, waking up waiters for a completion
+ * event.
+ *
+ * Returns 1 if the state of the tunnel has changed which requires calling
+ * drm_dp_tunnel_update_state(), a negative error code in case of a failure,
+ * 0 otherwise.
+ */
+int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_aux *aux)
+{
+ u8 val;
+
+ if (drm_dp_dpcd_readb(aux, DP_TUNNELING_STATUS, &val) < 0)
+ return -EIO;
+
+ if (val & (DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED))
+ wake_up_all(&mgr->bw_req_queue);
+
+ if (val & (DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED))
+ return 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_handle_irq);
+
+/**
+ * drm_dp_tunnel_max_dprx_rate - Query the maximum rate of the tunnel's DPRX
+ * @tunnel: Tunnel object
+ *
+ * The function is used to query the maximum link rate of the DPRX connected
+ * to @tunnel. Note that this rate will not be limited by the BW limit of the
+ * tunnel, as opposed to the standard and extended DP_MAX_LINK_RATE DPCD
+ * registers.
+ *
+ * Returns the maximum link rate in 10 kbit/s units.
+ */
+int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->max_dprx_rate;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_max_dprx_rate);
+
+/**
+ * drm_dp_tunnel_max_dprx_lane_count - Query the maximum lane count of the tunnel's DPRX
+ * @tunnel: Tunnel object
+ *
+ * The function is used to query the maximum lane count of the DPRX connected
+ * to @tunnel. Note that this lane count will not be limited by the BW limit of
+ * the tunnel, as opposed to the standard and extended DP_MAX_LANE_COUNT DPCD
+ * registers.
+ *
+ * Returns the maximum lane count.
+ */
+int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->max_dprx_lane_count;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_max_dprx_lane_count);
+
+/**
+ * drm_dp_tunnel_available_bw - Query the estimated total available BW of the tunnel
+ * @tunnel: Tunnel object
+ *
+ * This function is used to query the estimated total available BW of the
+ * tunnel. This includes the currently allocated and free BW for all the
+ * tunnels in @tunnel's group. The available BW is valid only after the BW
+ * allocation mode has been enabled for the tunnel and its state got updated
+ * calling drm_dp_tunnel_update_state().
+ *
+ * Returns the @tunnel group's estimated total available bandwidth in kB/s
+ * units, or -1 if the available BW isn't valid (the BW allocation mode is
+ * not enabled or the tunnel's state hasn't been updated).
+ */
+int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return tunnel->group->available_bw;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_available_bw);
+
+static struct drm_dp_tunnel_group_state *
+drm_dp_tunnel_atomic_get_group_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel)
+{
+ return (struct drm_dp_tunnel_group_state *)
+ drm_atomic_get_private_obj_state(state,
+ &tunnel->group->base);
+}
+
+static struct drm_dp_tunnel_state *
+add_tunnel_state(struct drm_dp_tunnel_group_state *group_state,
+ struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ tun_dbg_atomic(tunnel,
+ "Adding state for tunnel %p to group state %p\n",
+ tunnel, group_state);
+
+ tunnel_state = kzalloc(sizeof(*tunnel_state), GFP_KERNEL);
+ if (!tunnel_state)
+ return NULL;
+
+ tunnel_state->group_state = group_state;
+
+ drm_dp_tunnel_ref_get(tunnel, &tunnel_state->tunnel_ref);
+
+ INIT_LIST_HEAD(&tunnel_state->node);
+ list_add(&tunnel_state->node, &group_state->tunnel_states);
+
+ return tunnel_state;
+}
+
+static void free_tunnel_state(struct drm_dp_tunnel_state *tunnel_state)
+{
+ tun_dbg_atomic(tunnel_state->tunnel_ref.tunnel,
+ "Freeing state for tunnel %p\n",
+ tunnel_state->tunnel_ref.tunnel);
+
+ list_del(&tunnel_state->node);
+
+ kfree(tunnel_state->stream_bw);
+ drm_dp_tunnel_ref_put(&tunnel_state->tunnel_ref);
+
+ kfree(tunnel_state);
+}
+
+static void free_group_state(struct drm_dp_tunnel_group_state *group_state)
+{
+ struct drm_dp_tunnel_state *tunnel_state;
+ struct drm_dp_tunnel_state *tunnel_state_tmp;
+
+ for_each_tunnel_state_safe(group_state, tunnel_state, tunnel_state_tmp)
+ free_tunnel_state(tunnel_state);
+
+ kfree(group_state);
+}
+
+static struct drm_dp_tunnel_state *
+get_tunnel_state(struct drm_dp_tunnel_group_state *group_state,
+ const struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ for_each_tunnel_state(group_state, tunnel_state)
+ if (tunnel_state->tunnel_ref.tunnel == tunnel)
+ return tunnel_state;
+
+ return NULL;
+}
+
+static struct drm_dp_tunnel_state *
+get_or_add_tunnel_state(struct drm_dp_tunnel_group_state *group_state,
+ struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ tunnel_state = get_tunnel_state(group_state, tunnel);
+ if (tunnel_state)
+ return tunnel_state;
+
+ return add_tunnel_state(group_state, tunnel);
+}
+
+static struct drm_private_state *
+tunnel_group_duplicate_state(struct drm_private_obj *obj)
+{
+ struct drm_dp_tunnel_group_state *group_state;
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ group_state = kzalloc(sizeof(*group_state), GFP_KERNEL);
+ if (!group_state)
+ return NULL;
+
+ INIT_LIST_HEAD(&group_state->tunnel_states);
+
+ __drm_atomic_helper_private_obj_duplicate_state(obj, &group_state->base);
+
+ for_each_tunnel_state(to_group_state(obj->state), tunnel_state) {
+ struct drm_dp_tunnel_state *new_tunnel_state;
+
+ new_tunnel_state = get_or_add_tunnel_state(group_state,
+ tunnel_state->tunnel_ref.tunnel);
+ if (!new_tunnel_state)
+ goto out_free_state;
+
+ new_tunnel_state->stream_mask = tunnel_state->stream_mask;
+ new_tunnel_state->stream_bw = kmemdup(tunnel_state->stream_bw,
+ sizeof(*tunnel_state->stream_bw) *
+ hweight32(tunnel_state->stream_mask),
+ GFP_KERNEL);
+
+ if (!new_tunnel_state->stream_bw)
+ goto out_free_state;
+ }
+
+ return &group_state->base;
+
+out_free_state:
+ free_group_state(group_state);
+
+ return NULL;
+}
+
+static void tunnel_group_destroy_state(struct drm_private_obj *obj, struct drm_private_state *state)
+{
+ free_group_state(to_group_state(state));
+}
+
+static const struct drm_private_state_funcs tunnel_group_funcs = {
+ .atomic_duplicate_state = tunnel_group_duplicate_state,
+ .atomic_destroy_state = tunnel_group_destroy_state,
+};
+
+/**
+ * drm_dp_tunnel_atomic_get_state - get/allocate the new atomic state for a tunnel
+ * @state: Atomic state
+ * @tunnel: Tunnel to get the state for
+ *
+ * Get the new atomic state for @tunnel, duplicating it from the old tunnel
+ * state if not yet allocated.
+ *
+ * Return the state or an ERR_PTR() error on failure.
+ */
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_group_state *group_state;
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ group_state = drm_dp_tunnel_atomic_get_group_state(state, tunnel);
+ if (IS_ERR(group_state))
+ return ERR_CAST(group_state);
+
+ tunnel_state = get_or_add_tunnel_state(group_state, tunnel);
+ if (!tunnel_state)
+ return ERR_PTR(-ENOMEM);
+
+ return tunnel_state;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_state);
+
+/**
+ * drm_dp_tunnel_atomic_get_old_state - get the old atomic state for a tunnel
+ * @state: Atomic state
+ * @tunnel: Tunnel to get the state for
+ *
+ * Get the old atomic state for @tunnel.
+ *
+ * Return the old state or NULL if the tunnel's atomic state is not in @state.
+ */
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_group_state *old_group_state;
+ int i;
+
+ for_each_old_group_in_state(state, old_group_state, i)
+ if (to_group(old_group_state->base.obj) == tunnel->group)
+ return get_tunnel_state(old_group_state, tunnel);
+
+ return NULL;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_old_state);
+
+/**
+ * drm_dp_tunnel_atomic_get_new_state - get the new atomic state for a tunnel
+ * @state: Atomic state
+ * @tunnel: Tunnel to get the state for
+ *
+ * Get the new atomic state for @tunnel.
+ *
+ * Return the new state or NULL if the tunnel's atomic state is not in @state.
+ */
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel)
+{
+ struct drm_dp_tunnel_group_state *new_group_state;
+ int i;
+
+ for_each_new_group_in_state(state, new_group_state, i)
+ if (to_group(new_group_state->base.obj) == tunnel->group)
+ return get_tunnel_state(new_group_state, tunnel);
+
+ return NULL;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_new_state);
+
+static bool init_group(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_tunnel_group *group)
+{
+ struct drm_dp_tunnel_group_state *group_state;
+
+ group_state = kzalloc(sizeof(*group_state), GFP_KERNEL);
+ if (!group_state)
+ return false;
+
+ INIT_LIST_HEAD(&group_state->tunnel_states);
+
+ group->mgr = mgr;
+ group->available_bw = -1;
+ INIT_LIST_HEAD(&group->tunnels);
+
+ drm_atomic_private_obj_init(mgr->dev, &group->base, &group_state->base,
+ &tunnel_group_funcs);
+
+ return true;
+}
+
+static void cleanup_group(struct drm_dp_tunnel_group *group)
+{
+ drm_atomic_private_obj_fini(&group->base);
+}
+
+#ifdef CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+static void check_unique_stream_ids(const struct drm_dp_tunnel_group_state *group_state)
+{
+ const struct drm_dp_tunnel_state *tunnel_state;
+ u32 stream_mask = 0;
+
+ for_each_tunnel_state(group_state, tunnel_state) {
+ drm_WARN(to_group(group_state->base.obj)->mgr->dev,
+ tunnel_state->stream_mask & stream_mask,
+ "[DPTUN %s]: conflicting stream IDs %x (IDs in other tunnels %x)\n",
+ tunnel_state->tunnel_ref.tunnel->name,
+ tunnel_state->stream_mask,
+ stream_mask);
+
+ stream_mask |= tunnel_state->stream_mask;
+ }
+}
+#else
+static void check_unique_stream_ids(const struct drm_dp_tunnel_group_state *group_state)
+{
+}
+#endif
+
+static int stream_id_to_idx(u32 stream_mask, u8 stream_id)
+{
+ return hweight32(stream_mask & (BIT(stream_id) - 1));
+}
+
+static int resize_bw_array(struct drm_dp_tunnel_state *tunnel_state,
+ unsigned long old_mask, unsigned long new_mask)
+{
+ unsigned long move_mask = old_mask & new_mask;
+ int *new_bws = NULL;
+ int id;
+
+ WARN_ON(!new_mask);
+
+ if (old_mask == new_mask)
+ return 0;
+
+ new_bws = kcalloc(hweight32(new_mask), sizeof(*new_bws), GFP_KERNEL);
+ if (!new_bws)
+ return -ENOMEM;
+
+ for_each_set_bit(id, &move_mask, BITS_PER_TYPE(move_mask))
+ new_bws[stream_id_to_idx(new_mask, id)] =
+ tunnel_state->stream_bw[stream_id_to_idx(old_mask, id)];
+
+ kfree(tunnel_state->stream_bw);
+ tunnel_state->stream_bw = new_bws;
+ tunnel_state->stream_mask = new_mask;
+
+ return 0;
+}
+
+static int set_stream_bw(struct drm_dp_tunnel_state *tunnel_state,
+ u8 stream_id, int bw)
+{
+ int err;
+
+ err = resize_bw_array(tunnel_state,
+ tunnel_state->stream_mask,
+ tunnel_state->stream_mask | BIT(stream_id));
+ if (err)
+ return err;
+
+ tunnel_state->stream_bw[stream_id_to_idx(tunnel_state->stream_mask, stream_id)] = bw;
+
+ return 0;
+}
+
+static int clear_stream_bw(struct drm_dp_tunnel_state *tunnel_state,
+ u8 stream_id)
+{
+ if (!(tunnel_state->stream_mask & ~BIT(stream_id))) {
+ free_tunnel_state(tunnel_state);
+ return 0;
+ }
+
+ return resize_bw_array(tunnel_state,
+ tunnel_state->stream_mask,
+ tunnel_state->stream_mask & ~BIT(stream_id));
+}
+
+/**
+ * drm_dp_tunnel_atomic_set_stream_bw - Set the BW for a DP tunnel stream
+ * @state: Atomic state
+ * @tunnel: DP tunnel containing the stream
+ * @stream_id: Stream ID
+ * @bw: BW of the stream
+ *
+ * Set a DP tunnel stream's required BW in the atomic state.
+ *
+ * Returns 0 in case of success, a negative error code otherwise.
+ */
+int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel,
+ u8 stream_id, int bw)
+{
+ struct drm_dp_tunnel_group_state *new_group_state;
+ struct drm_dp_tunnel_state *tunnel_state;
+ int err;
+
+ if (drm_WARN_ON(tunnel->group->mgr->dev,
+ stream_id > BITS_PER_TYPE(tunnel_state->stream_mask)))
+ return -EINVAL;
+
+ tun_dbg(tunnel,
+ "Setting %d Mb/s for stream %d\n",
+ DPTUN_BW_ARG(bw), stream_id);
+
+ new_group_state = drm_dp_tunnel_atomic_get_group_state(state, tunnel);
+ if (IS_ERR(new_group_state))
+ return PTR_ERR(new_group_state);
+
+ if (bw == 0) {
+ tunnel_state = get_tunnel_state(new_group_state, tunnel);
+ if (!tunnel_state)
+ return 0;
+
+ return clear_stream_bw(tunnel_state, stream_id);
+ }
+
+ tunnel_state = get_or_add_tunnel_state(new_group_state, tunnel);
+ if (drm_WARN_ON(state->dev, !tunnel_state))
+ return -EINVAL;
+
+ err = set_stream_bw(tunnel_state, stream_id, bw);
+ if (err)
+ return err;
+
+ check_unique_stream_ids(new_group_state);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_set_stream_bw);
+
+/**
+ * drm_dp_tunnel_atomic_get_required_bw - Get the BW required by a DP tunnel
+ * @tunnel_state: Atomic state of the queried tunnel
+ *
+ * Calculate the BW required by a tunnel adding up the required BW of all
+ * the streams in the tunnel.
+ *
+ * Return the total BW required by the tunnel.
+ */
+int drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state)
+{
+ int tunnel_bw = 0;
+ int i;
+
+ if (!tunnel_state || !tunnel_state->stream_mask)
+ return 0;
+
+ for (i = 0; i < hweight32(tunnel_state->stream_mask); i++)
+ tunnel_bw += tunnel_state->stream_bw[i];
+
+ return tunnel_bw;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_required_bw);
+
+/**
+ * drm_dp_tunnel_atomic_get_group_streams_in_state - Get mask of stream IDs in a group
+ * @state: Atomic state
+ * @tunnel: Tunnel object
+ * @stream_mask: Mask of streams in @tunnel's group
+ *
+ * Get the mask of all the stream IDs in the tunnel group of @tunnel.
+ *
+ * Return 0 in case of success - with the stream IDs in @stream_mask - or a
+ * negative error code in case of failure.
+ */
+int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel,
+ u32 *stream_mask)
+{
+ struct drm_dp_tunnel_group_state *group_state;
+ struct drm_dp_tunnel_state *tunnel_state;
+
+ group_state = drm_dp_tunnel_atomic_get_group_state(state, tunnel);
+ if (IS_ERR(group_state))
+ return PTR_ERR(group_state);
+
+ *stream_mask = 0;
+ for_each_tunnel_state(group_state, tunnel_state)
+ *stream_mask |= tunnel_state->stream_mask;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_get_group_streams_in_state);
+
+static int
+drm_dp_tunnel_atomic_check_group_bw(struct drm_dp_tunnel_group_state *new_group_state,
+ u32 *failed_stream_mask)
+{
+ struct drm_dp_tunnel_group *group = to_group(new_group_state->base.obj);
+ struct drm_dp_tunnel_state *new_tunnel_state;
+ u32 group_stream_mask = 0;
+ int group_bw = 0;
+
+ for_each_tunnel_state(new_group_state, new_tunnel_state) {
+ struct drm_dp_tunnel *tunnel = new_tunnel_state->tunnel_ref.tunnel;
+ int max_dprx_bw = get_max_dprx_bw(tunnel);
+ int tunnel_bw = drm_dp_tunnel_atomic_get_required_bw(new_tunnel_state);
+
+ tun_dbg(tunnel,
+ "%sRequired %d/%d Mb/s total for tunnel.\n",
+ tunnel_bw > max_dprx_bw ? "Not enough BW: " : "",
+ DPTUN_BW_ARG(tunnel_bw),
+ DPTUN_BW_ARG(max_dprx_bw));
+
+ if (tunnel_bw > max_dprx_bw) {
+ *failed_stream_mask = new_tunnel_state->stream_mask;
+ return -ENOSPC;
+ }
+
+ group_bw += min(roundup(tunnel_bw, tunnel->bw_granularity),
+ max_dprx_bw);
+ group_stream_mask |= new_tunnel_state->stream_mask;
+ }
+
+ tun_grp_dbg(group,
+ "%sRequired %d/%d Mb/s total for tunnel group.\n",
+ group_bw > group->available_bw ? "Not enough BW: " : "",
+ DPTUN_BW_ARG(group_bw),
+ DPTUN_BW_ARG(group->available_bw));
+
+ if (group_bw > group->available_bw) {
+ *failed_stream_mask = group_stream_mask;
+ return -ENOSPC;
+ }
+
+ return 0;
+}
+
+/**
+ * drm_dp_tunnel_atomic_check_stream_bws - Check BW limit for all streams in state
+ * @state: Atomic state
+ * @failed_stream_mask: Mask of stream IDs with a BW limit failure
+ *
+ * Check the required BW of each DP tunnel in @state against both the DPRX BW
+ * limit of the tunnel and the BW limit of the tunnel group. Return a mask of
+ * stream IDs in @failed_stream_mask once a check fails. The mask will contain
+ * either all the streams in a tunnel (in case a DPRX BW limit check failed) or
+ * all the streams in a tunnel group (in case a group BW limit check failed).
+ *
+ * Return 0 if all the BW limit checks passed, -ENOSPC in case a BW limit
+ * check failed - with @failed_stream_mask containing the streams failing the
+ * check - or a negative error code otherwise.
+ */
+int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state,
+ u32 *failed_stream_mask)
+{
+ struct drm_dp_tunnel_group_state *new_group_state;
+ int i;
+
+ for_each_new_group_in_state(state, new_group_state, i) {
+ int ret;
+
+ ret = drm_dp_tunnel_atomic_check_group_bw(new_group_state,
+ failed_stream_mask);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_atomic_check_stream_bws);
+
+static void destroy_mgr(struct drm_dp_tunnel_mgr *mgr)
+{
+ int i;
+
+ for (i = 0; i < mgr->group_count; i++) {
+ cleanup_group(&mgr->groups[i]);
+ drm_WARN_ON(mgr->dev, !list_empty(&mgr->groups[i].tunnels));
+ }
+
+#ifdef CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+ ref_tracker_dir_exit(&mgr->ref_tracker);
+#endif
+
+ kfree(mgr->groups);
+ kfree(mgr);
+}
+
+/**
+ * drm_dp_tunnel_mgr_create - Create a DP tunnel manager
+ * @dev: DRM device object
+ *
+ * Creates a DP tunnel manager for @dev.
+ *
+ * Returns a pointer to the tunnel manager if created successfully or NULL in
+ * case of an error.
+ */
+struct drm_dp_tunnel_mgr *
+drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count)
+{
+ struct drm_dp_tunnel_mgr *mgr;
+ int i;
+
+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
+ if (!mgr)
+ return NULL;
+
+ mgr->dev = dev;
+ init_waitqueue_head(&mgr->bw_req_queue);
+
+ mgr->groups = kcalloc(max_group_count, sizeof(*mgr->groups), GFP_KERNEL);
+ if (!mgr->groups) {
+ kfree(mgr);
+
+ return NULL;
+ }
+
+#ifdef CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE
+ ref_tracker_dir_init(&mgr->ref_tracker, 16, "dptun");
+#endif
+
+ for (i = 0; i < max_group_count; i++) {
+ if (!init_group(mgr, &mgr->groups[i])) {
+ destroy_mgr(mgr);
+
+ return NULL;
+ }
+
+ mgr->group_count++;
+ }
+
+ return mgr;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_mgr_create);
+
+/**
+ * drm_dp_tunnel_mgr_destroy - Destroy DP tunnel manager
+ * @mgr: Tunnel manager object
+ *
+ * Destroy the tunnel manager.
+ */
+void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr)
+{
+ destroy_mgr(mgr);
+}
+EXPORT_SYMBOL(drm_dp_tunnel_mgr_destroy);
return drm_mode_set_config_internal(&set);
}
-static unsigned int drm_num_crtcs(struct drm_device *dev)
-{
- unsigned int num = 0;
- struct drm_crtc *tmp;
-
- drm_for_each_crtc(tmp, dev) {
- num++;
- }
-
- return num;
-}
-
int drm_crtc_register_all(struct drm_device *dev)
{
struct drm_crtc *crtc;
if (name) {
crtc->name = kvasprintf(GFP_KERNEL, name, ap);
} else {
- crtc->name = kasprintf(GFP_KERNEL, "crtc-%d",
- drm_num_crtcs(dev));
+ crtc->name = kasprintf(GFP_KERNEL, "crtc-%d", config->num_crtc);
}
if (!crtc->name) {
drm_mode_object_unregister(dev, &crtc->base);
static char edid_firmware[PATH_MAX];
module_param_string(edid_firmware, edid_firmware, sizeof(edid_firmware), 0644);
-MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob "
- "from built-in data or /lib/firmware instead. ");
-
-#define GENERIC_EDIDS 6
-static const char * const generic_edid_name[GENERIC_EDIDS] = {
- "edid/800x600.bin",
- "edid/1024x768.bin",
- "edid/1280x1024.bin",
- "edid/1600x1200.bin",
- "edid/1680x1050.bin",
- "edid/1920x1080.bin",
-};
-
-static const u8 generic_edid[GENERIC_EDIDS][128] = {
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x1b, 0x14, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x01, 0x00, 0x00, 0x45, 0x40,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xa0, 0x0f,
- 0x20, 0x00, 0x31, 0x58, 0x1c, 0x20, 0x28, 0x80,
- 0x14, 0x00, 0x15, 0xd0, 0x10, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x24, 0x26, 0x05, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x53,
- 0x56, 0x47, 0x41, 0x0a, 0x20, 0x20, 0x00, 0xc2,
- },
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x23, 0x1a, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x08, 0x00, 0x61, 0x40,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x19,
- 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x08, 0x90,
- 0x36, 0x00, 0x63, 0x0a, 0x11, 0x00, 0x00, 0x18,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x2f, 0x31, 0x07, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x58,
- 0x47, 0x41, 0x0a, 0x20, 0x20, 0x20, 0x00, 0x55,
- },
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x2c, 0x23, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0x81, 0x80,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x30, 0x2a,
- 0x00, 0x98, 0x51, 0x00, 0x2a, 0x40, 0x30, 0x70,
- 0x13, 0x00, 0xbc, 0x63, 0x11, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x3e, 0x40, 0x0b, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x53,
- 0x58, 0x47, 0x41, 0x0a, 0x20, 0x20, 0x00, 0xa0,
- },
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x37, 0x29, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0xa9, 0x40,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x48, 0x3f,
- 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40, 0xc0,
- 0x13, 0x00, 0x2b, 0xa0, 0x21, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x4a, 0x4c, 0x11, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x55,
- 0x58, 0x47, 0x41, 0x0a, 0x20, 0x20, 0x00, 0x9d,
- },
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x2b, 0x1b, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0xb3, 0x00,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x21, 0x39,
- 0x90, 0x30, 0x62, 0x1a, 0x27, 0x40, 0x68, 0xb0,
- 0x36, 0x00, 0xb5, 0x11, 0x11, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x40, 0x42, 0x0f, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x57,
- 0x53, 0x58, 0x47, 0x41, 0x0a, 0x20, 0x00, 0x26,
- },
- {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x32, 0x1c, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0xd1, 0xc0,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
- 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
- 0x45, 0x00, 0xf4, 0x19, 0x11, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x42, 0x44, 0x0f, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x46,
- 0x48, 0x44, 0x0a, 0x20, 0x20, 0x20, 0x00, 0x05,
- },
-};
+MODULE_PARM_DESC(edid_firmware,
+ "Do not probe monitor, use specified EDID blob from /lib/firmware instead.");
static const struct drm_edid *edid_load(struct drm_connector *connector, const char *name)
{
const struct firmware *fw = NULL;
- const u8 *fwdata;
const struct drm_edid *drm_edid;
- int fwsize, builtin;
-
- builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
- if (builtin >= 0) {
- fwdata = generic_edid[builtin];
- fwsize = sizeof(generic_edid[builtin]);
- } else {
- int err;
-
- err = request_firmware(&fw, name, connector->dev->dev);
- if (err) {
- drm_err(connector->dev,
- "[CONNECTOR:%d:%s] Requesting EDID firmware \"%s\" failed (err=%d)\n",
- connector->base.id, connector->name,
- name, err);
- return ERR_PTR(err);
- }
-
- fwdata = fw->data;
- fwsize = fw->size;
+ int err;
+
+ err = request_firmware(&fw, name, connector->dev->dev);
+ if (err) {
+ drm_err(connector->dev,
+ "[CONNECTOR:%d:%s] Requesting EDID firmware \"%s\" failed (err=%d)\n",
+ connector->base.id, connector->name,
+ name, err);
+ return ERR_PTR(err);
}
- drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Loaded %s firmware EDID \"%s\"\n",
- connector->base.id, connector->name,
- builtin >= 0 ? "built-in" : "external", name);
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Loaded external firmware EDID \"%s\"\n",
+ connector->base.id, connector->name, name);
- drm_edid = drm_edid_alloc(fwdata, fwsize);
+ drm_edid = drm_edid_alloc(fw->data, fw->size);
if (!drm_edid_valid(drm_edid)) {
drm_err(connector->dev, "Invalid firmware EDID \"%s\"\n", name);
drm_edid_free(drm_edid);
if (!dev)
return 0;
+ /*
+ * Don't disable polling if it was never initialized
+ */
+ if (dev->mode_config.poll_enabled)
+ drm_kms_helper_poll_disable(dev);
- drm_kms_helper_poll_disable(dev);
drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 1);
state = drm_atomic_helper_suspend(dev);
if (IS_ERR(state)) {
drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
- drm_kms_helper_poll_enable(dev);
+ /*
+ * Don't enable polling if it was never initialized
+ */
+ if (dev->mode_config.poll_enabled)
+ drm_kms_helper_poll_enable(dev);
+
return PTR_ERR(state);
}
dev->mode_config.suspend_state = NULL;
drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
- drm_kms_helper_poll_enable(dev);
+ /*
+ * Don't enable polling if it is not initialized
+ */
+ if (dev->mode_config.poll_enabled)
+ drm_kms_helper_poll_enable(dev);
return ret;
}
* Drivers can call this helper from their device resume implementation. It is
* not an error to call this even when output polling isn't enabled.
*
+ * If device polling was never initialized before, this call will trigger a
+ * warning and return.
+ *
* Note that calls to enable and disable polling must be strictly ordered, which
* is automatically the case when they're only call from suspend/resume
* callbacks.
*/
void drm_kms_helper_poll_enable(struct drm_device *dev)
{
- if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll ||
- dev->mode_config.poll_running)
+ if (drm_WARN_ON_ONCE(dev, !dev->mode_config.poll_enabled) ||
+ !drm_kms_helper_poll || dev->mode_config.poll_running)
return;
if (drm_kms_helper_enable_hpd(dev) ||
0);
}
- /* Re-enable polling in case the global poll config changed. */
- drm_kms_helper_poll_enable(dev);
+ /*
+ * Re-enable polling in case the global poll config changed but polling
+ * is still initialized.
+ */
+ if (dev->mode_config.poll_enabled)
+ drm_kms_helper_poll_enable(dev);
if (connector->status == connector_status_disconnected) {
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n",
* not an error to call this even when output polling isn't enabled or already
* disabled. Polling is re-enabled by calling drm_kms_helper_poll_enable().
*
+ * If however, the polling was never initialized, this call will trigger a
+ * warning and return
+ *
* Note that calls to enable and disable polling must be strictly ordered, which
* is automatically the case when they're only call from suspend/resume
* callbacks.
*/
void drm_kms_helper_poll_disable(struct drm_device *dev)
{
+ if (drm_WARN_ON(dev, !dev->mode_config.poll_enabled))
+ return;
+
if (dev->mode_config.poll_running)
drm_kms_helper_disable_hpd(dev);
protected session and manage the status of the alive software session,
as well as its life cycle.
+config DRM_I915_DP_TUNNEL
+ bool "Enable DP tunnel support"
+ depends on DRM_I915
+ depends on USB4
+ select DRM_DISPLAY_DP_TUNNEL
+ default y
+ help
+ Choose this option to detect DP tunnels and enable the Bandwidth
+ Allocation mode for such tunnels. This allows using the maximum
+ resolution allowed by the link BW on all displays sharing the
+ link BW, for instance on a Thunderbolt link.
+
+ If in doubt, say "Y".
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
select STACKDEPOT
select STACKTRACE
select DRM_DP_AUX_CHARDEV
+ select DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE if DRM_I915_DP_TUNNEL
select X86_MSR # used by igt/pm_rpm
select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
select DRM_DEBUG_MM if DRM=y
display/vlv_dsi.o \
display/vlv_dsi_pll.o
+i915-$(CONFIG_DRM_I915_DP_TUNNEL) += \
+ display/intel_dp_tunnel.o
+
i915-y += \
i915_perf.o
const char *str;
u8 val;
- priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return false;
u8 vendor, device;
char *name, *devid;
- ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
+ ch7xxx = kzalloc(sizeof(*ch7xxx), GFP_KERNEL);
if (ch7xxx == NULL)
return false;
u16 temp;
int i;
- priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return false;
struct ns2501_priv *ns;
unsigned char ch;
- ns = kzalloc(sizeof(struct ns2501_priv), GFP_KERNEL);
+ ns = kzalloc(sizeof(*ns), GFP_KERNEL);
if (ns == NULL)
return false;
const struct drm_display_mode *adjusted_mode)
{
const struct ns2501_configuration *conf;
- struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
+ struct ns2501_priv *ns = dvo->dev_priv;
int mode_idx, i;
DRM_DEBUG_KMS
/* set the NS2501 power state */
static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
{
- struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
+ struct ns2501_priv *ns = dvo->dev_priv;
DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
struct sil164_priv *sil;
unsigned char ch;
- sil = kzalloc(sizeof(struct sil164_priv), GFP_KERNEL);
+ sil = kzalloc(sizeof(*sil), GFP_KERNEL);
if (sil == NULL)
return false;
struct tfp410_priv *tfp;
int id;
- tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
+ tfp = kzalloc(sizeof(*tfp), GFP_KERNEL);
if (tfp == NULL)
return false;
{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
};
-static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
- bool is_ddr3,
- int fsb,
- int mem)
+static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915)
{
- const struct cxsr_latency *latency;
int i;
- if (fsb == 0 || mem == 0)
+ if (i915->fsb_freq == 0 || i915->mem_freq == 0)
return NULL;
for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
- latency = &cxsr_latency_table[i];
+ const struct cxsr_latency *latency = &cxsr_latency_table[i];
+ bool is_desktop = !IS_MOBILE(i915);
+
if (is_desktop == latency->is_desktop &&
- is_ddr3 == latency->is_ddr3 &&
- fsb == latency->fsb_freq && mem == latency->mem_freq)
+ i915->is_ddr3 == latency->is_ddr3 &&
+ i915->fsb_freq == latency->fsb_freq &&
+ i915->mem_freq == latency->mem_freq)
return latency;
}
- DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
+ drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n");
return NULL;
}
/**
* intel_calculate_wm - calculate watermark level
+ * @i915: the device
* @pixel_rate: pixel clock
* @wm: chip FIFO params
* @fifo_size: size of the FIFO buffer
* past the watermark point. If the FIFO drains completely, a FIFO underrun
* will occur, and a display engine hang could result.
*/
-static unsigned int intel_calculate_wm(int pixel_rate,
+static unsigned int intel_calculate_wm(struct drm_i915_private *i915,
+ int pixel_rate,
const struct intel_watermark_params *wm,
int fifo_size, int cpp,
unsigned int latency_ns)
latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
wm->guard_size;
- DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
+ drm_dbg_kms(&i915->drm, "FIFO entries required for mode: %d\n", entries);
wm_size = fifo_size - entries;
- DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
+ drm_dbg_kms(&i915->drm, "FIFO watermark level: %d\n", wm_size);
/* Don't promote wm_size to unsigned... */
if (wm_size > wm->max_wm)
u32 reg;
unsigned int wm;
- latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
- dev_priv->is_ddr3,
- dev_priv->fsb_freq,
- dev_priv->mem_freq);
+ latency = intel_get_cxsr_latency(dev_priv);
if (!latency) {
drm_dbg_kms(&dev_priv->drm,
"Unknown FSB/MEM found, disable CxSR\n");
int cpp = fb->format->cpp[0];
/* Display SR */
- wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
+ wm = intel_calculate_wm(dev_priv, pixel_rate,
+ &pnv_display_wm,
pnv_display_wm.fifo_size,
cpp, latency->display_sr);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */
- wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
+ wm = intel_calculate_wm(dev_priv, pixel_rate,
+ &pnv_cursor_wm,
pnv_display_wm.fifo_size,
4, latency->cursor_sr);
intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK,
FW_WM(wm, CURSOR_SR));
/* Display HPLL off SR */
- wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
+ wm = intel_calculate_wm(dev_priv, pixel_rate,
+ &pnv_display_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
cpp, latency->display_hpll_disable);
intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
/* cursor HPLL off SR */
- wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
+ wm = intel_calculate_wm(dev_priv, pixel_rate,
+ &pnv_cursor_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
4, latency->cursor_hpll_disable);
reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
else
cpp = fb->format->cpp[0];
- planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
+ planea_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
} else {
else
cpp = fb->format->cpp[0];
- planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
+ planeb_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
} else {
if (crtc == NULL)
return;
- planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
+ planea_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
&i845_wm_info,
i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
max->fbc = ilk_fbc_wm_reg_max(dev_priv);
}
-static bool ilk_validate_wm_level(int level,
+static bool ilk_validate_wm_level(struct drm_i915_private *i915,
+ int level,
const struct ilk_wm_maximums *max,
struct intel_wm_level *result)
{
*/
if (level == 0 && !result->enable) {
if (result->pri_val > max->pri)
- DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
- level, result->pri_val, max->pri);
+ drm_dbg_kms(&i915->drm,
+ "Primary WM%d too large %u (max %u)\n",
+ level, result->pri_val, max->pri);
if (result->spr_val > max->spr)
- DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
- level, result->spr_val, max->spr);
+ drm_dbg_kms(&i915->drm,
+ "Sprite WM%d too large %u (max %u)\n",
+ level, result->spr_val, max->spr);
if (result->cur_val > max->cur)
- DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
- level, result->cur_val, max->cur);
+ drm_dbg_kms(&i915->drm,
+ "Cursor WM%d too large %u (max %u)\n",
+ level, result->cur_val, max->cur);
result->pri_val = min_t(u32, result->pri_val, max->pri);
result->spr_val = min_t(u32, result->spr_val, max->spr);
}
}
-static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
+static bool ilk_validate_pipe_wm(struct drm_i915_private *dev_priv,
struct intel_pipe_wm *pipe_wm)
{
/* LP0 watermark maximums depend on this pipe alone */
ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
/* At least LP0 must be valid */
- if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
+ if (!ilk_validate_wm_level(dev_priv, 0, &max, &pipe_wm->wm[0])) {
drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
return false;
}
* register maximums since such watermarks are
* always invalid.
*/
- if (!ilk_validate_wm_level(level, &max, wm)) {
+ if (!ilk_validate_wm_level(dev_priv, level, &max, wm)) {
memset(wm, 0, sizeof(*wm));
break;
}
if (level > last_enabled_level)
wm->enable = false;
- else if (!ilk_validate_wm_level(level, max, wm))
+ else if (!ilk_validate_wm_level(dev_priv, level, max, wm))
/* make sure all following levels get disabled */
last_enabled_level = level - 1;
g4x_setup_wm_latency(dev_priv);
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
- if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
- dev_priv->is_ddr3,
- dev_priv->fsb_freq,
- dev_priv->mem_freq)) {
+ if (!intel_get_cxsr_latency(dev_priv)) {
drm_info(&dev_priv->drm,
"failed to find known CxSR latency "
"(found ddr%s fsb freq %d, mem freq %d), "
* See intel_atomic_plane.c for the plane-specific atomic functionality.
*/
+#include <drm/display/drm_dp_tunnel.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fourcc.h>
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_dp_tunnel.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
if (crtc_state->post_csc_lut)
drm_property_blob_get(crtc_state->post_csc_lut);
+ if (crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_get(crtc_state->dp_tunnel_ref.tunnel,
+ &crtc_state->dp_tunnel_ref);
+
crtc_state->update_pipe = false;
crtc_state->update_m_n = false;
crtc_state->update_lrr = false;
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
intel_crtc_free_hw_state(crtc_state);
+ if (crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);
kfree(crtc_state);
}
/* state->internal not reset on purpose */
state->dpll_set = state->modeset = false;
+
+ intel_dp_tunnel_atomic_cleanup_inherited_state(state);
}
struct intel_crtc_state *
/* Find the sequence block and size for the given panel. */
static const u8 *
-find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
+find_panel_sequence_block(struct drm_i915_private *i915,
+ const struct bdb_mipi_sequence *sequence,
u16 panel_id, u32 *seq_size)
{
u32 total = get_blocksize(sequence);
for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
if (index + header_size > total) {
- DRM_ERROR("Invalid sequence block (header)\n");
+ drm_err(&i915->drm, "Invalid sequence block (header)\n");
return NULL;
}
index += header_size;
if (index + current_size > total) {
- DRM_ERROR("Invalid sequence block\n");
+ drm_err(&i915->drm, "Invalid sequence block\n");
return NULL;
}
index += current_size;
}
- DRM_ERROR("Sequence block detected but no valid configuration\n");
+ drm_err(&i915->drm, "Sequence block detected but no valid configuration\n");
return NULL;
}
-static int goto_next_sequence(const u8 *data, int index, int total)
+static int goto_next_sequence(struct drm_i915_private *i915,
+ const u8 *data, int index, int total)
{
u16 len;
len = *(data + index + 6) + 7;
break;
default:
- DRM_ERROR("Unknown operation byte\n");
+ drm_err(&i915->drm, "Unknown operation byte\n");
return 0;
}
}
return 0;
}
-static int goto_next_sequence_v3(const u8 *data, int index, int total)
+static int goto_next_sequence_v3(struct drm_i915_private *i915,
+ const u8 *data, int index, int total)
{
int seq_end;
u16 len;
* checking on the structure.
*/
if (total < 5) {
- DRM_ERROR("Too small sequence size\n");
+ drm_err(&i915->drm, "Too small sequence size\n");
return 0;
}
seq_end = index + size_of_sequence;
if (seq_end > total) {
- DRM_ERROR("Invalid sequence size\n");
+ drm_err(&i915->drm, "Invalid sequence size\n");
return 0;
}
if (operation_byte == MIPI_SEQ_ELEM_END) {
if (index != seq_end) {
- DRM_ERROR("Invalid element structure\n");
+ drm_err(&i915->drm, "Invalid element structure\n");
return 0;
}
return index;
case MIPI_SEQ_ELEM_PMIC:
break;
default:
- DRM_ERROR("Unknown operation byte %u\n",
- operation_byte);
+ drm_err(&i915->drm, "Unknown operation byte %u\n",
+ operation_byte);
break;
}
}
drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n",
sequence->version);
- seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
+ seq_data = find_panel_sequence_block(i915, sequence, panel_type, &seq_size);
if (!seq_data)
return;
panel->vbt.dsi.sequence[seq_id] = data + index;
if (sequence->version >= 3)
- index = goto_next_sequence_v3(data, index, seq_size);
+ index = goto_next_sequence_v3(i915, data, index, seq_size);
else
- index = goto_next_sequence(data, index, seq_size);
+ index = goto_next_sequence(i915, data, index, seq_size);
if (!index) {
drm_err(&i915->drm, "Invalid sequence %u\n",
seq_id);
}
}
-static u8 translate_iboost(u8 val)
+static u8 translate_iboost(struct drm_i915_private *i915, u8 val)
{
static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
if (val >= ARRAY_SIZE(mapping)) {
- DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
+ drm_dbg_kms(&i915->drm,
+ "Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
return 0;
}
return mapping[val];
/**
* intel_bios_is_valid_vbt - does the given buffer contain a valid VBT
+ * @i915: the device
* @buf: pointer to a buffer to validate
* @size: size of the buffer
*
* Returns true on valid VBT.
*/
-bool intel_bios_is_valid_vbt(const void *buf, size_t size)
+bool intel_bios_is_valid_vbt(struct drm_i915_private *i915,
+ const void *buf, size_t size)
{
const struct vbt_header *vbt = buf;
const struct bdb_header *bdb;
return false;
if (sizeof(struct vbt_header) > size) {
- DRM_DEBUG_DRIVER("VBT header incomplete\n");
+ drm_dbg_kms(&i915->drm, "VBT header incomplete\n");
return false;
}
if (memcmp(vbt->signature, "$VBT", 4)) {
- DRM_DEBUG_DRIVER("VBT invalid signature\n");
+ drm_dbg_kms(&i915->drm, "VBT invalid signature\n");
return false;
}
if (vbt->vbt_size > size) {
- DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n");
+ drm_dbg_kms(&i915->drm, "VBT incomplete (vbt_size overflows)\n");
return false;
}
vbt->bdb_offset,
sizeof(struct bdb_header),
size)) {
- DRM_DEBUG_DRIVER("BDB header incomplete\n");
+ drm_dbg_kms(&i915->drm, "BDB header incomplete\n");
return false;
}
bdb = get_bdb_header(vbt);
if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
- DRM_DEBUG_DRIVER("BDB incomplete\n");
+ drm_dbg_kms(&i915->drm, "BDB incomplete\n");
return false;
}
for (count = 0; count < vbt_size; count += 4)
*(vbt + store++) = intel_spi_read(&i915->uncore, found + count);
- if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size))
goto err_free_vbt;
drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
memcpy_fromio(vbt, p, vbt_size);
- if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size))
goto err_free_vbt;
pci_unmap_rom(pdev, oprom);
struct dsc_compression_parameters_entry *dsc,
int dsc_max_bpc)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
int bpc = 8;
else if (dsc->support_8bpc && dsc_max_bpc >= 8)
bpc = 8;
else
- DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
- dsc_max_bpc);
+ drm_dbg_kms(&i915->drm, "VBT: Unsupported BPC %d for DCS\n",
+ dsc_max_bpc);
crtc_state->pipe_bpp = bpc * 3;
} else {
/* FIXME */
if (!(dsc->slices_per_line & BIT(0)))
- DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
+ drm_dbg_kms(&i915->drm, "VBT: Unsupported DSC slice count for DSI\n");
crtc_state->dsc.slice_count = 1;
}
if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
crtc_state->dsc.slice_count != 0)
- DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n",
- crtc_state->hw.adjusted_mode.crtc_hdisplay,
- crtc_state->dsc.slice_count);
+ drm_dbg_kms(&i915->drm, "VBT: DSC hdisplay %d not divisible by slice count %d\n",
+ crtc_state->hw.adjusted_mode.crtc_hdisplay,
+ crtc_state->dsc.slice_count);
/*
* The VBT rc_buffer_block_size and rc_buffer_size definitions
if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
- return translate_iboost(devdata->child.dp_iboost_level);
+ return translate_iboost(devdata->i915, devdata->child.dp_iboost_level);
}
int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata)
if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
- return translate_iboost(devdata->child.hdmi_iboost_level);
+ return translate_iboost(devdata->i915, devdata->child.hdmi_iboost_level);
}
int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
const struct drm_edid *drm_edid);
void intel_bios_fini_panel(struct intel_panel *panel);
void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
-bool intel_bios_is_valid_vbt(const void *buf, size_t size);
+bool intel_bios_is_valid_vbt(struct drm_i915_private *i915,
+ const void *buf, size_t size);
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
* DMC will not change the active CDCLK frequency however, so that part
* will still be performed by the driver directly.
*
+ * Several methods exist to change the CDCLK frequency, which ones are
+ * supported depends on the platform:
+ *
+ * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
+ * - CD2X divider update. Single pipe can be active as the divider update
+ * can be synchronized with the pipe's start of vblank.
+ * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
+ * - Squash waveform update. Pipes can be active.
+ * - Crawl and squash can also be done back to back. Pipes can be active.
+ *
* RAWCLK is a fixed frequency clock, often used by various auxiliary
* blocks such as AUX CH or backlight PWM. Hence the only thing we
* really need to know about RAWCLK is its frequency so that various
{}
};
+static const int cdclk_squash_len = 16;
+
+static int cdclk_squash_divider(u16 waveform)
+{
+ return hweight16(waveform ?: 0xffff);
+}
+
+static int cdclk_divider(int cdclk, int vco, u16 waveform)
+{
+ /* 2 * cd2x divider */
+ return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
+ cdclk * cdclk_squash_len);
+}
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
}
static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
- int cdclk, int vco)
+ int cdclk, int vco, u16 waveform)
{
/* cdclk = vco / 2 / div{1,1.5,2,4} */
- switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
+ switch (cdclk_divider(cdclk, vco, waveform)) {
default:
drm_WARN_ON(&dev_priv->drm,
cdclk != dev_priv->display.cdclk.hw.bypass);
}
}
-static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
+static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
int cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
return vco == ~0;
}
-static const int cdclk_squash_len = 16;
-
-static int cdclk_squash_divider(u16 waveform)
-{
- return hweight16(waveform ?: 0xffff);
-}
-
static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
const struct intel_cdclk_config *old_cdclk_config,
const struct intel_cdclk_config *new_cdclk_config,
struct intel_cdclk_config *mid_cdclk_config)
{
u16 old_waveform, new_waveform, mid_waveform;
- int div = 2;
+ int old_div, new_div, mid_div;
/* Return if PLL is in an unknown state, force a complete disable and re-enable. */
if (cdclk_pll_is_unknown(old_cdclk_config->vco))
old_waveform == new_waveform)
return false;
+ old_div = cdclk_divider(old_cdclk_config->cdclk,
+ old_cdclk_config->vco, old_waveform);
+ new_div = cdclk_divider(new_cdclk_config->cdclk,
+ new_cdclk_config->vco, new_waveform);
+
+ /*
+ * Should not happen currently. We might need more midpoint
+ * transitions if we need to also change the cd2x divider.
+ */
+ if (drm_WARN_ON(&i915->drm, old_div != new_div))
+ return false;
+
*mid_cdclk_config = *new_cdclk_config;
/*
if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
mid_cdclk_config->vco = old_cdclk_config->vco;
+ mid_div = old_div;
mid_waveform = new_waveform;
} else {
mid_cdclk_config->vco = new_cdclk_config->vco;
+ mid_div = new_div;
mid_waveform = old_waveform;
}
mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
mid_cdclk_config->vco,
- cdclk_squash_len * div);
+ cdclk_squash_len * mid_div);
/* make sure the mid clock came out sane */
{
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
- int unsquashed_cdclk;
u16 waveform;
u32 val;
waveform = cdclk_squash_waveform(i915, cdclk);
- unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,
- cdclk_squash_divider(waveform));
-
- val = bxt_cdclk_cd2x_div_sel(i915, unsquashed_cdclk, vco) |
+ val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
bxt_cdclk_cd2x_pipe(i915, pipe);
/*
return DISPLAY_INFO(i915)->color.degamma_lut_size;
}
-static int check_lut_size(const struct drm_property_blob *lut, int expected)
+static int check_lut_size(struct drm_i915_private *i915,
+ const struct drm_property_blob *lut, int expected)
{
int len;
len = drm_color_lut_size(lut);
if (len != expected) {
- DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
- len, expected);
+ drm_dbg_kms(&i915->drm, "Invalid LUT size; got %d, expected %d\n",
+ len, expected);
return -EINVAL;
}
degamma_length = intel_degamma_lut_size(crtc_state);
gamma_length = intel_gamma_lut_size(crtc_state);
- if (check_lut_size(degamma_lut, degamma_length) ||
- check_lut_size(gamma_lut, gamma_length))
+ if (check_lut_size(i915, degamma_lut, degamma_length) ||
+ check_lut_size(i915, gamma_lut, gamma_length))
return -EINVAL;
if (drm_color_lut_check(degamma_lut, degamma_tests) ||
struct i2c_adapter *ddc;
int ret;
+ if (!intel_display_driver_check_access(dev_priv))
+ return drm_edid_connector_add_modes(connector);
+
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
.clock = 1000000, /* 10 Gbps */
.tx = { 0xbe21, /* tx cfg0 */
- 0x4800, /* tx cfg1 */
+ 0xe800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
- .cmn = {0x0500, /* cmn cfg0*/
+ .cmn = {0x0700, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
.clock = 3000000,
.tx = { 0xbe98, /* tx cfg0 */
- 0x9800, /* tx cfg1 */
+ 0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = { 0x0500, /* cmn cfg0*/
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
- .mpllb = { 0x209c, /* mpllb cfg0 */
- 0x7d10, /* mpllb cfg1 */
+ .mpllb = { 0x309c, /* mpllb cfg0 */
+ 0x2110, /* mpllb cfg1 */
0xca06, /* mpllb cfg2 */
0xbe40, /* mpllb cfg3 */
0x0000, /* mpllb cfg4 */
static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
.clock = 6000000,
.tx = { 0xbe98, /* tx cfg0 */
- 0x9800, /* tx cfg1 */
+ 0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = { 0x0500, /* cmn cfg0*/
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
- .mpllb = { 0x009c, /* mpllb cfg0 */
- 0x7d08, /* mpllb cfg1 */
+ .mpllb = { 0x109c, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
0xca06, /* mpllb cfg2 */
0xbe40, /* mpllb cfg3 */
0x0000, /* mpllb cfg4 */
static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
.clock = 8000000,
.tx = { 0xbe98, /* tx cfg0 */
- 0x9800, /* tx cfg1 */
+ 0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = { 0x0500, /* cmn cfg0*/
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
- .mpllb = { 0x00d0, /* mpllb cfg0 */
- 0x7d08, /* mpllb cfg1 */
+ .mpllb = { 0x10d0, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
0x4a06, /* mpllb cfg2 */
0xbe40, /* mpllb cfg3 */
0x0000, /* mpllb cfg4 */
static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
.clock = 10000000,
.tx = { 0xbe98, /* tx cfg0 */
- 0x9800, /* tx cfg1 */
+ 0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = { 0x0500, /* cmn cfg0*/
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x1104, /* mpllb cfg0 */
- 0x7d08, /* mpllb cfg1 */
+ 0x2108, /* mpllb cfg1 */
0x0a06, /* mpllb cfg2 */
0xbe40, /* mpllb cfg3 */
0x0000, /* mpllb cfg4 */
static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
.clock = 12000000,
.tx = { 0xbe98, /* tx cfg0 */
- 0x9800, /* tx cfg1 */
+ 0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = { 0x0500, /* cmn cfg0*/
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
- .mpllb = { 0x0138, /* mpllb cfg0 */
- 0x7d08, /* mpllb cfg1 */
+ .mpllb = { 0x1138, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
0x5486, /* mpllb cfg2 */
0xfe40, /* mpllb cfg3 */
0x0000, /* mpllb cfg4 */
#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
#include "intel_dpio_phy.h"
#include "intel_dsi.h"
#include "intel_fdi.h"
intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
crtc_state);
- if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
+ if (intel_encoder_is_dp(encoder))
intel_dp_sync_state(encoder, crtc_state);
}
#include <linux/string_helpers.h>
#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_dp_tunnel.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_atomic_uapi.h>
#include "intel_dp.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
#include "intel_dpt.h"
u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
bw_overhead);
- u32 data_n = intel_dp_max_data_rate(link_clock, nlanes);
+ u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
/*
* Windows/BIOS uses fixed M/N values always. Follow suit.
saved_state->crc_enabled = slave_crtc_state->crc_enabled;
intel_crtc_free_hw_state(slave_crtc_state);
+ if (slave_crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_put(&slave_crtc_state->dp_tunnel_ref);
memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
kfree(saved_state);
&master_crtc_state->hw.adjusted_mode);
slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
+ if (master_crtc_state->dp_tunnel_ref.tunnel)
+ drm_dp_tunnel_ref_get(master_crtc_state->dp_tunnel_ref.tunnel,
+ &slave_crtc_state->dp_tunnel_ref);
+
copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
/* free the old crtc_state->hw members */
intel_crtc_free_hw_state(crtc_state);
+ intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
+
/* FIXME: before the switch to atomic started, a new pipe_config was
* kzalloc'd. Code that depends on any field being zero should be
* fixed, so that the crtc_state can be safely duplicated. For now,
}
static void
-pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
- bool fastset, const char *name,
+pipe_config_buffer_mismatch(bool fastset, const struct intel_crtc *crtc,
+ const char *name,
const u8 *a, const u8 *b, size_t len)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
if (fastset) {
if (!drm_debug_enabled(DRM_UT_KMS))
return;
len = memcmp_diff_len(a, b, len);
drm_dbg_kms(&dev_priv->drm,
- "fastset requirement not met in %s buffer\n", name);
+ "[CRTC:%d:%s] fastset requirement not met in %s buffer\n",
+ crtc->base.base.id, crtc->base.name, name);
print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
16, 0, a, len, false);
print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
/* only dump up to the last difference */
len = memcmp_diff_len(a, b, len);
- drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
+ drm_err(&dev_priv->drm, "[CRTC:%d:%s] mismatch in %s buffer\n",
+ crtc->base.base.id, crtc->base.name, name);
print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
16, 0, a, len, false);
print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
va_end(args);
}
-static bool fastboot_enabled(struct drm_i915_private *dev_priv)
+static void
+pipe_config_pll_mismatch(bool fastset,
+ const struct intel_crtc *crtc,
+ const char *name,
+ const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
{
- /* Enable fastboot by default on Skylake and newer */
- if (DISPLAY_VER(dev_priv) >= 9)
- return true;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- /* Enable fastboot by default on VLV and CHV */
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- return true;
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
- /* Disabled by default on all others */
- return false;
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] fastset requirement not met in %s\n",
+ crtc->base.base.id, crtc->base.name, name);
+ drm_dbg_kms(&i915->drm, "expected:\n");
+ intel_dpll_dump_hw_state(i915, a);
+ drm_dbg_kms(&i915->drm, "found:\n");
+ intel_dpll_dump_hw_state(i915, b);
+ } else {
+ drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s buffer\n",
+ crtc->base.base.id, crtc->base.name, name);
+ drm_err(&i915->drm, "expected:\n");
+ intel_dpll_dump_hw_state(i915, a);
+ drm_err(&i915->drm, "found:\n");
+ intel_dpll_dump_hw_state(i915, b);
+ }
}
bool
struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
bool ret = true;
- bool fixup_inherited = fastset &&
- current_config->inherited && !pipe_config->inherited;
-
- if (fixup_inherited && !fastboot_enabled(dev_priv)) {
- drm_dbg_kms(&dev_priv->drm,
- "initial modeset and fastboot not set\n");
- ret = false;
- }
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
} \
} while (0)
-#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+#define PIPE_CONF_CHECK_PLL(name) do { \
+ if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
+ &pipe_config->name)) { \
+ pipe_config_pll_mismatch(fastset, crtc, __stringify(name), \
+ ¤t_config->name, \
+ &pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
PIPE_CONF_CHECK_I(name.crtc_htotal); \
PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
- pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
+ pipe_config_buffer_mismatch(fastset, crtc, __stringify(name), \
current_config->name, \
pipe_config->name, \
(len)); \
PIPE_CONF_CHECK_BOOL(double_wide);
- if (dev_priv->display.dpll.mgr) {
+ if (dev_priv->display.dpll.mgr)
PIPE_CONF_CHECK_P(shared_dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.spll);
- PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
- PIPE_CONF_CHECK_X(dpll_hw_state.div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
- PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
- }
+ /* FIXME convert everything over the dpll_mgr */
+ if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
+ PIPE_CONF_CHECK_PLL(dpll_hw_state);
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
if (ret)
return ret;
+ ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
+ if (ret)
+ return ret;
+
ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
if (ret)
return ret;
static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_link_bw_limits new_limits;
struct intel_link_bw_limits old_limits;
int ret;
- intel_link_bw_init_limits(i915, &new_limits);
+ intel_link_bw_init_limits(state, &new_limits);
old_limits = new_limits;
while (true) {
intel_commit_modeset_disables(state);
+ intel_dp_tunnel_atomic_alloc_bw(state);
+
/* FIXME: Eventually get rid of our crtc->config pointer */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
/* Kill all the work that may have been queued by hpd. */
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
- if (connector->modeset_retry_work.func)
- cancel_work_sync(&connector->modeset_retry_work);
+ if (connector->modeset_retry_work.func &&
+ cancel_work_sync(&connector->modeset_retry_work))
+ drm_connector_put(&connector->base);
if (connector->hdcp.shim) {
cancel_delayed_work_sync(&connector->hdcp.check_work);
cancel_work_sync(&connector->hdcp.prop_work);
} wq;
/* Grouping using named structs. Keep sorted. */
+ struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
struct intel_audio audio;
struct intel_dpll dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
}
static void intel_hdcp_info(struct seq_file *m,
- struct intel_connector *intel_connector)
+ struct intel_connector *intel_connector,
+ bool remote_req)
{
bool hdcp_cap, hdcp2_cap;
goto out;
}
- hdcp_cap = intel_hdcp_capable(intel_connector);
- hdcp2_cap = intel_hdcp2_capable(intel_connector);
+ if (remote_req) {
+ intel_hdcp_get_remote_capability(intel_connector,
+ &hdcp_cap,
+ &hdcp2_cap);
+ } else {
+ hdcp_cap = intel_hdcp_get_capability(intel_connector);
+ hdcp2_cap = intel_hdcp2_get_capability(intel_connector);
+ }
if (hdcp_cap)
seq_puts(m, "HDCP1.4 ");
}
seq_puts(m, "\tHDCP version: ");
- intel_hdcp_info(m, intel_connector);
+ if (intel_encoder_is_mst(encoder)) {
+ intel_hdcp_info(m, intel_connector, true);
+ seq_puts(m, "\tMST Hub HDCP version: ");
+ }
+ intel_hdcp_info(m, intel_connector, false);
seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
seq_printf(m, "%s:%d HDCP version: ", connector->base.name,
connector->base.base.id);
- intel_hdcp_info(m, connector);
+ intel_hdcp_info(m, connector, false);
out:
drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
return ret;
}
+static int i915_bigjoiner_enable_show(struct seq_file *m, void *data)
+{
+ struct intel_connector *connector = m->private;
+ struct drm_crtc *crtc;
+
+ crtc = connector->base.state->crtc;
+ if (connector->base.status != connector_status_connected || !crtc)
+ return -ENODEV;
+
+ seq_printf(m, "Bigjoiner enable: %d\n", connector->force_bigjoiner_enable);
+
+ return 0;
+}
+
static ssize_t i915_dsc_output_format_write(struct file *file,
const char __user *ubuf,
size_t len, loff_t *offp)
return len;
}
+static ssize_t i915_bigjoiner_enable_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct intel_connector *connector = m->private;
+ struct drm_crtc *crtc;
+ bool bigjoiner_en = 0;
+ int ret;
+
+ crtc = connector->base.state->crtc;
+ if (connector->base.status != connector_status_connected || !crtc)
+ return -ENODEV;
+
+ ret = kstrtobool_from_user(ubuf, len, &bigjoiner_en);
+ if (ret < 0)
+ return ret;
+
+ connector->force_bigjoiner_enable = bigjoiner_en;
+ *offp += len;
+
+ return len;
+}
+
static int i915_dsc_output_format_open(struct inode *inode,
struct file *file)
{
.write = i915_dsc_fractional_bpp_write
};
+DEFINE_SHOW_STORE_ATTRIBUTE(i915_bigjoiner_enable);
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
connector, &i915_dsc_fractional_bpp_fops);
}
+ if (DISPLAY_VER(i915) >= 11 &&
+ (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+ connector_type == DRM_MODE_CONNECTOR_eDP)) {
+ debugfs_create_file("i915_bigjoiner_force_enable", 0644, root,
+ connector, &i915_bigjoiner_enable_fops);
+ }
+
if (connector_type == DRM_MODE_CONNECTOR_DSI ||
connector_type == DRM_MODE_CONNECTOR_eDP ||
connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
#include "intel_dkl_phy.h"
#include "intel_dmc.h"
#include "intel_dp.h"
+#include "intel_dp_tunnel.h"
#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
#include "intel_fb.h"
for_each_pipe(i915, pipe) {
ret = intel_crtc_init(i915, pipe);
- if (ret) {
- intel_mode_config_cleanup(i915);
- return ret;
- }
+ if (ret)
+ goto err_mode_config;
}
intel_plane_possible_crtcs_init(i915);
intel_vga_disable(i915);
intel_setup_outputs(i915);
+ ret = intel_dp_tunnel_mgr_init(i915);
+ if (ret)
+ goto err_hdcp;
+
intel_display_driver_disable_user_access(i915);
drm_modeset_lock_all(dev);
ilk_wm_sanitize(i915);
return 0;
+
+err_hdcp:
+ intel_hdcp_component_fini(i915);
+err_mode_config:
+ intel_mode_config_cleanup(i915);
+
+ return ret;
}
/* part #3: call after gem init */
intel_mode_config_cleanup(i915);
+ intel_dp_tunnel_mgr_cleanup(i915);
+
intel_overlay_cleanup(i915);
intel_gmbus_teardown(i915);
#include <drm/display/drm_dp_dual_mode_helper.h>
#include <drm/display/drm_dp_mst_helper.h>
+#include <drm/display/drm_dp_tunnel.h>
#include <drm/display/drm_dsc.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc.h>
struct edp_power_seq pps;
u8 drrs_msa_timing_delay;
bool low_vswing;
- bool initialized;
bool hobl;
} edp;
struct intel_connector *connector);
/* Detects panel's hdcp capability. This is optional for HDMI. */
- int (*hdcp_capable)(struct intel_digital_port *dig_port,
- bool *hdcp_capable);
+ int (*hdcp_get_capability)(struct intel_digital_port *dig_port,
+ bool *hdcp_capable);
/* HDCP adaptation(DP/HDMI) required on the port */
enum hdcp_wired_protocol protocol;
/* Detects whether sink is HDCP2.2 capable */
- int (*hdcp_2_2_capable)(struct intel_connector *connector,
- bool *capable);
+ int (*hdcp_2_2_get_capability)(struct intel_connector *connector,
+ bool *capable);
/* Write HDCP2.2 messages */
int (*write_2_2_msg)(struct intel_connector *connector,
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
+
+ /* HDCP remote sink cap */
+ int (*get_remote_hdcp_capability)(struct intel_connector *connector,
+ bool *hdcp_capable, bool *hdcp2_capable);
};
struct intel_hdcp {
struct intel_dp *mst_port;
+ bool force_bigjoiner_enable;
+
struct {
struct drm_dp_aux *dsc_decompression_aux;
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
+ struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
+
/*
* Current watermarks can't be trusted during hardware readout, so
* don't bother calculating intermediate watermarks.
struct drm_dsc_config config;
} dsc;
+ /* DP tunnel used for BW allocation. */
+ struct drm_dp_tunnel_ref dp_tunnel_ref;
+
/* HSW+ linetime watermarks */
u16 linetime;
u16 ips_linetime;
/* connector directly attached - won't be use for modeset in mst world */
struct intel_connector *attached_connector;
+ struct drm_dp_tunnel *tunnel;
+ bool tunnel_suspended:1;
+
/* mst connector list */
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
struct drm_dp_mst_topology_mgr mst_mgr;
#include <asm/byteorder.h>
#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_dp_tunnel.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/display/drm_hdmi_helper.h>
#include <drm/drm_atomic_helper.h>
#include "intel_dp_hdcp.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_fifo_underrun.h"
return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
}
+static int max_dprx_rate(struct intel_dp *intel_dp)
+{
+ if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
+
+ return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+}
+
+static int max_dprx_lane_count(struct intel_dp *intel_dp)
+{
+ if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
+
+ return drm_dp_max_lane_count(intel_dp->dpcd);
+}
+
static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
{
intel_dp->sink_rates[0] = 162000;
/*
* Sink rates for 8b/10b.
*/
- max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+ max_rate = max_dprx_rate(intel_dp);
max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
if (max_lttpr_rate)
max_rate = min(max_rate, max_lttpr_rate);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &intel_dig_port->base;
- intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
switch (intel_dp->max_sink_lane_count) {
case 1:
}
/* Theoretical max between source and sink */
-static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
+int intel_dp_max_common_rate(struct intel_dp *intel_dp)
{
return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
}
}
/* Theoretical max between source and sink */
-static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
+int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
int source_max = intel_dp_max_source_lane_count(dig_port);
1000000 * 16 * 8);
}
-/*
- * Given a link rate and lanes, get the data bandwidth.
- *
- * Data bandwidth is the actual payload rate, which depends on the data
- * bandwidth efficiency and the link rate.
+/**
+ * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
+ * @intel_dp: Intel DP object
+ * @max_dprx_rate: Maximum data rate of the DPRX
+ * @max_dprx_lanes: Maximum lane count of the DPRX
*
- * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
- * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
- * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
- * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
- * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
- * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
+ * Calculate the maximum data rate for the provided link parameters taking into
+ * account any BW limitations by a DP tunnel attached to @intel_dp.
*
- * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
- * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
- * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
- * does not match the symbol clock, the port clock (not even if you think in
- * terms of a byte clock), nor the data bandwidth. It only matches the link bit
- * rate in units of 10000 bps.
+ * Returns the maximum data rate in kBps units.
*/
-int
-intel_dp_max_data_rate(int max_link_rate, int max_lanes)
+int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
+ int max_dprx_rate, int max_dprx_lanes)
{
- int ch_coding_efficiency =
- drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
- int max_link_rate_kbps = max_link_rate * 10;
+ int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
- /*
- * UHBR rates always use 128b/132b channel encoding, and have
- * 97.71% data bandwidth efficiency. Consider max_link_rate the
- * link bit rate in units of 10000 bps.
- */
- /*
- * Lower than UHBR rates always use 8b/10b channel encoding, and have
- * 80% data bandwidth efficiency for SST non-FEC. However, this turns
- * out to be a nop by coincidence:
- *
- * int max_link_rate_kbps = max_link_rate * 10;
- * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10);
- * max_link_rate = max_link_rate_kbps / 8;
- */
- return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
- ch_coding_efficiency),
- 1000000 * 8);
+ if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ max_rate = min(max_rate,
+ drm_dp_tunnel_available_bw(intel_dp->tunnel));
+
+ return max_rate;
}
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
int mode_rate, max_rate;
mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
- max_rate = intel_dp_max_data_rate(link_rate, lane_count);
+ max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
if (mode_rate > max_rate)
return false;
int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector = intel_dp->attached_connector;
if (!intel_dp_can_bigjoiner(intel_dp))
return false;
- return clock > i915->max_dotclk_freq || hdisplay > 5120;
+ return clock > i915->max_dotclk_freq || hdisplay > 5120 ||
+ connector->force_bigjoiner_enable;
}
static enum drm_mode_status
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
- max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
+ max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
+
mode_rate = intel_dp_link_required(target_clock,
intel_dp_mode_min_output_bpp(connector, mode));
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- link_avail = intel_dp_max_data_rate(link_rate,
- lane_count);
+ link_avail = intel_dp_max_link_data_rate(intel_dp,
+ link_rate,
+ lane_count);
+
if (mode_rate <= link_avail) {
pipe_config->lane_count = lane_count;
limits);
}
+int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int bpp = crtc_state->dsc.compression_enable ?
+ to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
+ crtc_state->pipe_bpp;
+
+ return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
+}
+
static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
return ret;
}
- if (pipe_config->dsc.compression_enable) {
- drm_dbg_kms(&i915->drm,
- "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
- pipe_config->lane_count, pipe_config->port_clock,
- pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
-
- drm_dbg_kms(&i915->drm,
- "DP link rate required %i available %i\n",
- intel_dp_link_required(adjusted_mode->crtc_clock,
- to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
- intel_dp_max_data_rate(pipe_config->port_clock,
- pipe_config->lane_count));
- } else {
- drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
- pipe_config->lane_count, pipe_config->port_clock,
- pipe_config->pipe_bpp);
+ drm_dbg_kms(&i915->drm,
+ "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
+ pipe_config->lane_count, pipe_config->port_clock,
+ pipe_config->pipe_bpp,
+ BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
+ intel_dp_config_required_rate(pipe_config),
+ intel_dp_max_link_data_rate(intel_dp,
+ pipe_config->port_clock,
+ pipe_config->lane_count));
- drm_dbg_kms(&i915->drm,
- "DP link rate required %i available %i\n",
- intel_dp_link_required(adjusted_mode->crtc_clock,
- pipe_config->pipe_bpp),
- intel_dp_max_data_rate(pipe_config->port_clock,
- pipe_config->lane_count));
- }
return 0;
}
intel_dp_is_uhbr(pipe_config);
}
+void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+ drm_connector_get(&connector->base);
+ if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
+ drm_connector_put(&connector->base);
+}
+
+void
+intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_connector *connector;
+ struct intel_digital_connector_state *conn_state;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ int i;
+
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+ intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
+
+ return;
+ }
+
+ for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
+ if (!conn_state->base.crtc)
+ continue;
+
+ if (connector->mst_port == intel_dp)
+ intel_dp_queue_modeset_retry_work(connector);
+ }
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
- return 0;
+ return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
+ pipe_config);
}
void intel_dp_set_link_params(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- if (!crtc_state)
- return;
+ bool dpcd_updated = false;
/*
* Don't clobber DPCD if it's been already read out during output
* setup (eDP) or detect.
*/
- if (intel_dp->dpcd[DP_DPCD_REV] == 0)
+ if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
intel_dp_get_dpcd(intel_dp);
+ dpcd_updated = true;
+ }
- intel_dp_reset_max_link_params(intel_dp);
+ intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
+
+ if (crtc_state)
+ intel_dp_reset_max_link_params(intel_dp);
}
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
&intel_dp->desc);
}
+void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
+{
+ intel_dp_set_sink_rates(intel_dp);
+ intel_dp_set_max_sink_lane_count(intel_dp);
+ intel_dp_set_common_rates(intel_dp);
+}
+
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
{
drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
drm_dp_is_branch(intel_dp->dpcd));
- intel_dp_set_sink_rates(intel_dp);
- intel_dp_set_max_sink_lane_count(intel_dp);
- intel_dp_set_common_rates(intel_dp);
+ intel_dp_update_sink_caps(intel_dp);
}
if (intel_dp_has_sink_count(intel_dp)) {
return false;
}
-static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
- struct dp_sdp *sdp, size_t size)
-{
- size_t length = sizeof(struct dp_sdp);
-
- if (size < length)
- return -ENOSPC;
-
- memset(sdp, 0, size);
-
- /*
- * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
- * VSC SDP Header Bytes
- */
- sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
- sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
- sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
- sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
-
- if (vsc->revision == 0x6) {
- sdp->db[0] = 1;
- sdp->db[3] = 1;
- }
-
- /*
- * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
- * Format as per DP 1.4a spec and DP 2.0 respectively.
- */
- if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
- goto out;
-
- /* VSC SDP Payload for DB16 through DB18 */
- /* Pixel Encoding and Colorimetry Formats */
- sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
- sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
-
- switch (vsc->bpc) {
- case 6:
- /* 6bpc: 0x0 */
- break;
- case 8:
- sdp->db[17] = 0x1; /* DB17[3:0] */
- break;
- case 10:
- sdp->db[17] = 0x2;
- break;
- case 12:
- sdp->db[17] = 0x3;
- break;
- case 16:
- sdp->db[17] = 0x4;
- break;
- default:
- MISSING_CASE(vsc->bpc);
- break;
- }
- /* Dynamic Range and Component Bit Depth */
- if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
- sdp->db[17] |= 0x80; /* DB17[7] */
-
- /* Content Type */
- sdp->db[18] = vsc->content_type & 0x7;
-
-out:
- return length;
-}
-
static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
const struct hdmi_drm_infoframe *drm_infoframe,
switch (type) {
case DP_SDP_VSC:
- len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
- sizeof(sdp));
+ len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
break;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
* - %true if pending interrupts were serviced (or no interrupts were
* pending) w/o detecting an error condition.
* - %false if an error condition - like AUX failure or a loss of link - is
- * detected, which needs servicing from the hotplug work.
+ * detected, or another condition - like a DP tunnel BW state change - needs
+ * servicing from the hotplug work.
*/
static bool
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
bool link_ok = true;
+ bool reprobe_needed = false;
drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
intel_dp_mst_hpd_irq(intel_dp, esi, ack);
+ if (esi[3] & DP_TUNNELING_IRQ) {
+ if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
+ &intel_dp->aux))
+ reprobe_needed = true;
+ ack[3] |= DP_TUNNELING_IRQ;
+ }
+
if (!memchr_inv(ack, 0, sizeof(ack)))
break;
drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
}
- return link_ok;
+ return link_ok && !reprobe_needed;
}
static void
if (!crtc_state->hw.active)
continue;
- if (conn_state->commit &&
- !try_wait_for_completion(&conn_state->commit->hw_done))
- continue;
+ if (conn_state->commit)
+ drm_WARN_ON(&i915->drm,
+ !wait_for_completion_timeout(&conn_state->commit->hw_done,
+ msecs_to_jiffies(5000)));
*pipe_mask |= BIT(crtc->pipe);
}
drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
}
-static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
+static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool reprobe_needed = false;
u8 val;
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
- return;
+ return false;
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
- return;
+ return false;
+
+ if ((val & DP_TUNNELING_IRQ) &&
+ drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
+ &intel_dp->aux))
+ reprobe_needed = true;
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
- return;
+ return reprobe_needed;
if (val & HDMI_LINK_STATUS_CHANGED)
intel_dp_handle_hdmi_link_status_change(intel_dp);
+
+ return reprobe_needed;
}
/*
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 old_sink_count = intel_dp->sink_count;
+ bool reprobe_needed = false;
bool ret;
/*
}
intel_dp_check_device_service_irq(intel_dp);
- intel_dp_check_link_service_irq(intel_dp);
+ reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
/* Handle CEC interrupts, if any */
drm_dp_cec_irq(&intel_dp->aux);
* FIXME get rid of the ad-hoc phy test modeset code
* and properly incorporate it into the normal modeset.
*/
- return false;
+ reprobe_needed = true;
}
- return true;
+ return !reprobe_needed;
}
/* XXX this is probably wrong for multiple downstream ports */
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
enum drm_connector_status status;
+ int ret;
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
connector->base.id, connector->name);
intel_dp->is_mst);
}
+ intel_dp_tunnel_disconnect(intel_dp);
+
goto out;
}
+ ret = intel_dp_tunnel_detect(intel_dp, ctx);
+ if (ret == -EDEADLK)
+ return ret;
+
+ if (ret == 1)
+ intel_connector->base.epoch_counter++;
+
intel_dp_detect_dsc_caps(intel_dp, intel_connector);
intel_dp_configure_mst(intel_dp);
* with an IRQ_HPD, so force a link status check.
*/
if (!intel_dp_is_edp(intel_dp)) {
- int ret;
-
ret = intel_dp_retrain_link(encoder, ctx);
if (ret)
return ret;
intel_dp_mst_encoder_cleanup(dig_port);
+ intel_dp_tunnel_destroy(intel_dp);
+
intel_pps_vdd_off_sync(intel_dp);
/*
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
intel_pps_vdd_off_sync(intel_dp);
+
+ intel_dp_tunnel_suspend(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
return ret;
}
+ if (!intel_connector_needs_modeset(state, conn))
+ return 0;
+
+ ret = intel_dp_tunnel_atomic_check_state(state,
+ intel_dp,
+ intel_conn);
+ if (ret)
+ return ret;
+
/*
* We don't enable port sync on BDW due to missing w/as and
* due to not having adjusted the modeset sequence appropriately.
if (DISPLAY_VER(dev_priv) < 9)
return 0;
- if (!intel_connector_needs_modeset(state, conn))
- return 0;
-
if (conn->has_tile) {
ret = intel_modeset_tile_group(state, conn->tile_group->id);
if (ret)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_dp *intel_dp = &dig_port->dp;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
(long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
dig_port->base.base.name,
long_hpd ? "long" : "short");
+ /*
+ * TBT DP tunnels require the GFX driver to read out the DPRX caps in
+ * response to long HPD pulses. The DP hotplug handler does that,
+ * however the hotplug handler may be blocked by another
+ * connector's/encoder's hotplug handler. Since the TBT CM may not
+ * complete the DP tunnel BW request for the latter connector/encoder
+ * waiting for this encoder's DPRX read, perform a dummy read here.
+ */
+ if (long_hpd)
+ intel_dp_read_dprx_caps(intel_dp, dpcd);
+
if (long_hpd) {
intel_dp->reset_link_params = true;
return IRQ_NONE;
mutex_unlock(&connector->dev->mode_config.mutex);
/* Send Hotplug uevent so userspace can reprobe */
drm_kms_helper_connector_hotplug_event(connector);
+
+ drm_connector_put(connector);
+}
+
+void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
+{
+ INIT_WORK(&connector->modeset_retry_work,
+ intel_dp_modeset_retry_work_fn);
}
bool
int type;
/* Initialize the work for modeset in case of link train failure */
- INIT_WORK(&intel_connector->modeset_retry_work,
- intel_dp_modeset_retry_work_fn);
+ intel_dp_init_modeset_retry_work(intel_connector);
if (drm_WARN(dev, dig_port->max_lanes < 1,
"Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
int intel_dp_min_bpp(enum intel_output_format output_format);
+void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
+void intel_dp_queue_modeset_retry_work(struct intel_connector *connector);
+void
+intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
bool intel_dp_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector);
void intel_dp_set_link_params(struct intel_dp *intel_dp,
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
+int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
+int intel_dp_max_common_rate(struct intel_dp *intel_dp);
+int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
+void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
int bw_overhead);
-int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
+int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
+ int max_dprx_rate, int max_dprx_lanes);
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
}
}
-static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
+static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector,
+ int timeout)
{
+ struct intel_hdcp *hdcp = &connector->hdcp;
long ret;
#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
msecs_to_jiffies(timeout));
if (!ret)
- DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
+ drm_dbg_kms(connector->base.dev,
+ "Timedout at waiting for CP_IRQ\n");
}
static
}
static
-int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
+int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
+ struct drm_i915_private *i915,
u8 *bcaps)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
ssize_t ret;
- ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
+ ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
bcaps, 1);
if (ret != 1) {
drm_dbg_kms(&i915->drm,
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
bool *repeater_present)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
if (ret)
return ret;
}
static
-int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
- bool *hdcp_capable)
+int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
+ bool *hdcp_capable)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
if (ret)
return ret;
0, 0 },
};
-static struct drm_dp_aux *
-intel_dp_hdcp_get_aux(struct intel_connector *connector)
-{
- struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
-
- if (intel_encoder_is_mst(connector->encoder))
- return &connector->port->aux;
- else
- return &dig_port->dp.aux;
-}
-
static int
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
u8 *rx_status)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = &dig_port->dp.aux;
ssize_t ret;
ret = drm_dp_dpcd_read(aux,
*msg_ready = true;
break;
default:
- DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
+ drm_err(connector->base.dev,
+ "Unidentified msg_id: %d\n", msg_id);
return -EINVAL;
}
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_hdcp *hdcp = &connector->hdcp;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
u8 msg_id = hdcp2_msg_data->msg_id;
int ret, timeout;
bool msg_ready = false;
* As we want to check the msg availability at timeout, Ignoring
* the timeout at wait for CP_IRQ.
*/
- intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
+ intel_dp_hdcp_wait_for_cp_irq(connector, timeout);
ret = hdcp2_detect_msg_availability(connector, msg_id,
&msg_ready);
if (!msg_ready)
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_write, len;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = &dig_port->dp.aux;
const struct hdcp2_dp_msg_data *hdcp2_msg_data;
- struct drm_dp_aux *aux;
hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
if (!hdcp2_msg_data)
offset = hdcp2_msg_data->offset;
- aux = intel_dp_hdcp_get_aux(connector);
-
/* No msg_id in DP HDCP2.2 msgs */
bytes_to_write = size - 1;
byte++;
ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector,
u32 *dev_cnt, u8 *byte)
{
- struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = &dig_port->dp.aux;
ssize_t ret;
u8 *rx_info = byte;
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_hdcp *hdcp = &connector->hdcp;
- struct drm_dp_aux *aux;
+ struct drm_dp_aux *aux = &dig_port->dp.aux;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
return -EINVAL;
offset = hdcp2_msg_data->offset;
- aux = intel_dp_hdcp_get_aux(connector);
-
ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data);
if (ret < 0)
return ret;
/* Entire msg read timeout since initiate of msg read */
if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) {
- if (intel_encoder_is_mst(connector->encoder))
- msg_end = ktime_add_ms(ktime_get_raw(),
- hdcp2_msg_data->msg_read_timeout *
- connector->port->parent->num_ports);
- else
- msg_end = ktime_add_ms(ktime_get_raw(),
- hdcp2_msg_data->msg_read_timeout);
+ msg_end = ktime_add_ms(ktime_get_raw(),
+ hdcp2_msg_data->msg_read_timeout);
}
ret = drm_dp_dpcd_read(aux, offset,
}
static
-int intel_dp_hdcp2_capable(struct intel_connector *connector,
- bool *capable)
+int _intel_dp_hdcp2_get_capability(struct drm_dp_aux *aux,
+ bool *capable)
{
- struct drm_dp_aux *aux;
u8 rx_caps[3];
+ int ret, i;
+
+ *capable = false;
+
+ /*
+ * Some HDCP monitors act really shady by not giving the correct hdcp
+ * capability on the first rx_caps read and usually take an extra read
+ * to give the capability. We read rx_caps three times before we
+ * declare a monitor not capable of HDCP 2.2.
+ */
+ for (i = 0; i < 3; i++) {
+ ret = drm_dp_dpcd_read(aux,
+ DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
+ rx_caps, HDCP_2_2_RXCAPS_LEN);
+ if (ret != HDCP_2_2_RXCAPS_LEN)
+ return ret >= 0 ? -EIO : ret;
+
+ if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
+ HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) {
+ *capable = true;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static
+int intel_dp_hdcp2_get_capability(struct intel_connector *connector,
+ bool *capable)
+{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = &dig_port->dp.aux;
+
+ return _intel_dp_hdcp2_get_capability(aux, capable);
+}
+
+static
+int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
+ bool *hdcp_capable,
+ bool *hdcp2_capable)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_dp_aux *aux = &connector->port->aux;
+ u8 bcaps;
int ret;
- aux = intel_dp_hdcp_get_aux(connector);
+ if (!intel_encoder_is_mst(connector->encoder))
+ return -EINVAL;
- *capable = false;
- ret = drm_dp_dpcd_read(aux,
- DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
- rx_caps, HDCP_2_2_RXCAPS_LEN);
- if (ret != HDCP_2_2_RXCAPS_LEN)
- return ret >= 0 ? -EIO : ret;
+ ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
+ if (ret)
+ return ret;
+
+ ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
+ if (ret)
+ return ret;
- if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
- HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
- *capable = true;
+ *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
return 0;
}
.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
.toggle_signalling = intel_dp_hdcp_toggle_signalling,
.check_link = intel_dp_hdcp_check_link,
- .hdcp_capable = intel_dp_hdcp_capable,
+ .hdcp_get_capability = intel_dp_hdcp_get_capability,
.write_2_2_msg = intel_dp_hdcp2_write_msg,
.read_2_2_msg = intel_dp_hdcp2_read_msg,
.config_stream_type = intel_dp_hdcp2_config_stream_type,
.check_2_2_link = intel_dp_hdcp2_check_link,
- .hdcp_2_2_capable = intel_dp_hdcp2_capable,
+ .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability,
.protocol = HDCP_PROTOCOL_DP,
};
.toggle_signalling = intel_dp_hdcp_toggle_signalling,
.stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_hdcp_check_link,
- .hdcp_capable = intel_dp_hdcp_capable,
+ .hdcp_get_capability = intel_dp_hdcp_get_capability,
.write_2_2_msg = intel_dp_hdcp2_write_msg,
.read_2_2_msg = intel_dp_hdcp2_read_msg,
.config_stream_type = intel_dp_hdcp2_config_stream_type,
.stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
.check_2_2_link = intel_dp_mst_hdcp2_check_link,
- .hdcp_2_2_capable = intel_dp_hdcp2_capable,
+ .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability,
+ .get_remote_hdcp_capability = intel_dp_hdcp_get_remote_capability,
.protocol = HDCP_PROTOCOL_DP,
};
return lttpr_count;
}
+int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (intel_dp_is_edp(intel_dp))
+ return 0;
+
+ /*
+ * Detecting LTTPRs must be avoided on platforms with an AUX timeout
+ * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
+ */
+ if (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))
+ if (drm_dp_dpcd_probe(&intel_dp->aux,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
+ return -EIO;
+
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ return 0;
+}
+
/**
* intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
* @intel_dp: Intel DP struct
if (!intel_dp_is_edp(intel_dp) &&
(DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) {
u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ int err = intel_dp_read_dprx_caps(intel_dp, dpcd);
- if (drm_dp_dpcd_probe(&intel_dp->aux, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
- return -EIO;
-
- if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
- return -EIO;
+ if (err != 0)
+ return err;
lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
}
const struct intel_crtc_state *crtc_state)
{
struct intel_connector *intel_connector = intel_dp->attached_connector;
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
}
/* Schedule a Hotplug Uevent to userspace to start modeset */
- queue_work(i915->unordered_wq, &intel_connector->modeset_retry_work);
+ intel_dp_queue_modeset_retry_work(intel_connector);
}
/* Perform the link training on all LTTPRs and the DPRX on a link. */
struct intel_crtc_state;
struct intel_dp;
+int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
#include "intel_dp.h"
#include "intel_dp_hdcp.h"
#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
const struct intel_connector *connector =
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- return 0;
+ return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
+ pipe_config);
}
/*
if (ret)
return ret;
+ if (intel_connector_needs_modeset(state, connector)) {
+ ret = intel_dp_tunnel_atomic_check_state(state,
+ intel_connector->mst_port,
+ intel_connector);
+ if (ret)
+ return ret;
+ }
+
return drm_dp_atomic_release_time_slots(&state->base,
&intel_connector->mst_port->mst_mgr,
intel_connector->port);
static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
struct intel_dp *intel_dp = intel_connector->mst_port;
const struct drm_edid *drm_edid;
int ret;
if (drm_connector_is_unregistered(connector))
return intel_connector_update_modes(connector, NULL);
+ if (!intel_display_driver_check_access(i915))
+ return drm_edid_connector_add_modes(connector);
+
drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
ret = intel_connector_update_modes(connector, drm_edid);
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
- max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
+ max_rate = intel_dp_max_link_data_rate(intel_dp,
+ max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(mode->clock, min_bpp);
ret = drm_modeset_lock(&mgr->base.lock, ctx);
intel_connector->port = port;
drm_dp_mst_get_port_malloc(port);
+ intel_dp_init_modeset_retry_work(intel_connector);
+
intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
intel_connector->dp.dsc_hblank_expansion_quirk =
--- /dev/null
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include <drm/display/drm_dp_tunnel.h>
+
+#include "intel_atomic.h"
+#include "intel_display_limits.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
+#include "intel_link_bw.h"
+
+struct intel_dp_tunnel_inherited_state {
+ struct drm_dp_tunnel_ref ref[I915_MAX_PIPES];
+};
+
+/**
+ * intel_dp_tunnel_disconnect - Disconnect a DP tunnel from a port
+ * @intel_dp: DP port object the tunnel is connected to
+ *
+ * Disconnect a DP tunnel from @intel_dp, destroying any related state. This
+ * should be called after detecting a sink-disconnect event from the port.
+ */
+void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp)
+{
+ drm_dp_tunnel_destroy(intel_dp->tunnel);
+ intel_dp->tunnel = NULL;
+}
+
+/**
+ * intel_dp_tunnel_destroy - Destroy a DP tunnel
+ * @intel_dp: DP port object the tunnel is connected to
+ *
+ * Destroy a DP tunnel connected to @intel_dp, after disabling the BW
+ * allocation mode on the tunnel. This should be called while destroying the
+ * port.
+ */
+void intel_dp_tunnel_destroy(struct intel_dp *intel_dp)
+{
+ if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);
+
+ intel_dp_tunnel_disconnect(intel_dp);
+}
+
+static int kbytes_to_mbits(int kbytes)
+{
+ return DIV_ROUND_UP(kbytes * 8, 1000);
+}
+
+static int get_current_link_bw(struct intel_dp *intel_dp,
+ bool *below_dprx_bw)
+{
+ int rate = intel_dp_max_common_rate(intel_dp);
+ int lane_count = intel_dp_max_common_lane_count(intel_dp);
+ int bw;
+
+ bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
+ *below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate, lane_count);
+
+ return bw;
+}
+
+static int update_tunnel_state(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ bool old_bw_below_dprx;
+ bool new_bw_below_dprx;
+ int old_bw;
+ int new_bw;
+ int ret;
+
+ old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);
+
+ ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
+ if (ret < 0) {
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s] State update failed (err %pe)\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ encoder->base.base.id, encoder->base.name,
+ ERR_PTR(ret));
+
+ return ret;
+ }
+
+ if (ret == 0 ||
+ !drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel))
+ return 0;
+
+ intel_dp_update_sink_caps(intel_dp);
+
+ new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);
+
+ /* Suppress the notification if the mode list can't change due to bw. */
+ if (old_bw_below_dprx == new_bw_below_dprx &&
+ !new_bw_below_dprx)
+ return 0;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s] Notify users about BW change: %d -> %d\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ encoder->base.base.id, encoder->base.name,
+ kbytes_to_mbits(old_bw), kbytes_to_mbits(new_bw));
+
+ return 1;
+}
+
+/*
+ * Allocate the BW for a tunnel on a DP connector/port if the connector/port
+ * was already active when detecting the tunnel. The allocated BW must be
+ * freed by the next atomic modeset, storing the BW in the
+ * intel_atomic_state::inherited_dp_tunnels, and calling
+ * intel_dp_tunnel_atomic_free_bw().
+ */
+static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pipe_mask)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct intel_crtc *crtc;
+ int tunnel_bw = 0;
+ int err;
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
+ const struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+ int stream_bw = intel_dp_config_required_rate(crtc_state);
+
+ tunnel_bw += stream_bw;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s][CRTC:%d:%s] Initial BW for stream %d: %d/%d Mb/s\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ crtc->pipe,
+ kbytes_to_mbits(stream_bw), kbytes_to_mbits(tunnel_bw));
+ }
+
+ err = drm_dp_tunnel_alloc_bw(intel_dp->tunnel, tunnel_bw);
+ if (err) {
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s] Initial BW allocation failed (err %pe)\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ encoder->base.base.id, encoder->base.name,
+ ERR_PTR(err));
+
+ return err;
+ }
+
+ return update_tunnel_state(intel_dp);
+}
+
+static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ u8 pipe_mask;
+ int err;
+
+ err = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
+ if (err)
+ return err;
+
+ return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);
+}
+
+static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_dp_tunnel *tunnel;
+ int ret;
+
+ tunnel = drm_dp_tunnel_detect(i915->display.dp_tunnel_mgr,
+ &intel_dp->aux);
+ if (IS_ERR(tunnel))
+ return PTR_ERR(tunnel);
+
+ intel_dp->tunnel = tunnel;
+
+ ret = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);
+ if (ret) {
+ if (ret == -EOPNOTSUPP)
+ return 0;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s] Failed to enable BW allocation mode (ret %pe)\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ encoder->base.base.id, encoder->base.name,
+ ERR_PTR(ret));
+
+ /* Keep the tunnel with BWA disabled */
+ return 0;
+ }
+
+ ret = allocate_initial_tunnel_bw(intel_dp, ctx);
+ if (ret < 0)
+ intel_dp_tunnel_destroy(intel_dp);
+
+ return ret;
+}
+
+/**
+ * intel_dp_tunnel_detect - Detect a DP tunnel on a port
+ * @intel_dp: DP port object
+ * @ctx: lock context acquired by the connector detection handler
+ *
+ * Detect a DP tunnel on the @intel_dp port, enabling the BW allocation mode
+ * on it if supported and allocating the BW required on an already active port.
+ * The BW allocated this way must be freed by the next atomic modeset calling
+ * intel_dp_tunnel_atomic_free_bw().
+ *
+ * If @intel_dp has already a tunnel detected on it, update the tunnel's state
+ * wrt. its support for BW allocation mode and the available BW via the
+ * tunnel. If the tunnel's state change requires this - for instance the
+ * tunnel's group ID has changed - the tunnel will be dropped and recreated.
+ *
+ * Return 0 in case of success - after any tunnel detected and added to
+ * @intel_dp - 1 in case the BW on an already existing tunnel has changed in a
+ * way that requires notifying user space.
+ */
+int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)
+{
+ int ret;
+
+ if (intel_dp_is_edp(intel_dp))
+ return 0;
+
+ if (intel_dp->tunnel) {
+ ret = update_tunnel_state(intel_dp);
+ if (ret >= 0)
+ return ret;
+
+ /* Try to recreate the tunnel after an update error. */
+ intel_dp_tunnel_destroy(intel_dp);
+ }
+
+ return detect_new_tunnel(intel_dp, ctx);
+}
+
+/**
+ * intel_dp_tunnel_bw_alloc_is_enabled - Query the BW allocation support on a tunnel
+ * @intel_dp: DP port object
+ *
+ * Query whether a DP tunnel is connected on @intel_dp and the tunnel supports
+ * the BW allocation mode.
+ *
+ * Returns %true if the BW allocation mode is supported on @intel_dp.
+ */
+bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
+{
+ return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);
+}
+
+/**
+ * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port
+ * @intel_dp: DP port object
+ *
+ * Suspend a DP tunnel on @intel_dp with BW allocation mode enabled on it.
+ */
+void intel_dp_tunnel_suspend(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+
+ if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ return;
+
+ drm_dbg_kms(&i915->drm, "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Suspend\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name);
+
+ drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);
+
+ intel_dp->tunnel_suspended = true;
+}
+
+/**
+ * intel_dp_tunnel_resume - Resume a DP tunnel connected on a port
+ * @intel_dp: DP port object
+ * @crtc_state: CRTC state
+ * @dpcd_updated: the DPCD DPRX capabilities got updated during resume
+ *
+ * Resume a DP tunnel on @intel_dp with BW allocation mode enabled on it.
+ */
+void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dpcd_updated)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ u8 pipe_mask;
+ int err = 0;
+
+ if (!intel_dp->tunnel_suspended)
+ return;
+
+ intel_dp->tunnel_suspended = false;
+
+ drm_dbg_kms(&i915->drm, "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Resume\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name);
+
+ /*
+ * The TBT Connection Manager requires the GFX driver to read out
+ * the sink's DPRX caps to be able to service any BW requests later.
+ * During resume overriding the caps in @intel_dp cached before
+ * suspend must be avoided, so do here only a dummy read, unless the
+ * capabilities were updated already during resume.
+ */
+ if (!dpcd_updated) {
+ err = intel_dp_read_dprx_caps(intel_dp, dpcd);
+
+ if (err) {
+ drm_dp_tunnel_set_io_error(intel_dp->tunnel);
+ goto out_err;
+ }
+ }
+
+ err = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);
+ if (err)
+ goto out_err;
+
+ pipe_mask = 0;
+ if (crtc_state) {
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ /* TODO: Add support for MST */
+ pipe_mask |= BIT(crtc->pipe);
+ }
+
+ err = allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);
+ if (err < 0)
+ goto out_err;
+
+ return;
+
+out_err:
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s] Tunnel can't be resumed, will drop and redect it (err %pe)\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name,
+ ERR_PTR(err));
+}
+
+static struct drm_dp_tunnel *
+get_inherited_tunnel(struct intel_atomic_state *state, struct intel_crtc *crtc)
+{
+ if (!state->inherited_dp_tunnels)
+ return NULL;
+
+ return state->inherited_dp_tunnels->ref[crtc->pipe].tunnel;
+}
+
+static int
+add_inherited_tunnel(struct intel_atomic_state *state,
+ struct drm_dp_tunnel *tunnel,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct drm_dp_tunnel *old_tunnel;
+
+ old_tunnel = get_inherited_tunnel(state, crtc);
+ if (old_tunnel) {
+ drm_WARN_ON(&i915->drm, old_tunnel != tunnel);
+ return 0;
+ }
+
+ if (!state->inherited_dp_tunnels) {
+ state->inherited_dp_tunnels = kzalloc(sizeof(*state->inherited_dp_tunnels),
+ GFP_KERNEL);
+ if (!state->inherited_dp_tunnels)
+ return -ENOMEM;
+ }
+
+ drm_dp_tunnel_ref_get(tunnel, &state->inherited_dp_tunnels->ref[crtc->pipe]);
+
+ return 0;
+}
+
+static int check_inherited_tunnel_state(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ const struct intel_digital_connector_state *old_conn_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct intel_connector *connector =
+ to_intel_connector(old_conn_state->base.connector);
+ struct intel_crtc *old_crtc;
+ const struct intel_crtc_state *old_crtc_state;
+
+ /*
+ * If a BWA tunnel gets detected only after the corresponding
+ * connector got enabled already without a BWA tunnel, or a different
+ * BWA tunnel (which was removed meanwhile) the old CRTC state won't
+ * contain the state of the current tunnel. This tunnel still has a
+ * reserved BW, which needs to be released, add the state for such
+ * inherited tunnels separately only to this atomic state.
+ */
+ if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ return 0;
+
+ if (!old_conn_state->base.crtc)
+ return 0;
+
+ old_crtc = to_intel_crtc(old_conn_state->base.crtc);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, old_crtc);
+
+ if (!old_crtc_state->hw.active ||
+ old_crtc_state->dp_tunnel_ref.tunnel == intel_dp->tunnel)
+ return 0;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s][CRTC:%d:%s] Adding state for inherited tunnel %p\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name,
+ old_crtc->base.base.id, old_crtc->base.name,
+ intel_dp->tunnel);
+
+ return add_inherited_tunnel(state, intel_dp->tunnel, old_crtc);
+}
+
+/**
+ * intel_dp_tunnel_atomic_cleanup_inherited_state - Free any inherited DP tunnel state
+ * @state: Atomic state
+ *
+ * Free the inherited DP tunnel state in @state.
+ */
+void intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state)
+{
+ enum pipe pipe;
+
+ if (!state->inherited_dp_tunnels)
+ return;
+
+ for_each_pipe(to_i915(state->base.dev), pipe)
+ if (state->inherited_dp_tunnels->ref[pipe].tunnel)
+ drm_dp_tunnel_ref_put(&state->inherited_dp_tunnels->ref[pipe]);
+
+ kfree(state->inherited_dp_tunnels);
+ state->inherited_dp_tunnels = NULL;
+}
+
+static int intel_dp_tunnel_atomic_add_group_state(struct intel_atomic_state *state,
+ struct drm_dp_tunnel *tunnel)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ u32 pipe_mask;
+ int err;
+
+ err = drm_dp_tunnel_atomic_get_group_streams_in_state(&state->base,
+ tunnel, &pipe_mask);
+ if (err)
+ return err;
+
+ drm_WARN_ON(&i915->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));
+
+ return intel_modeset_pipes_in_mask_early(state, "DPTUN", pipe_mask);
+}
+
+/**
+ * intel_dp_tunnel_atomic_add_state_for_crtc - Add CRTC specific DP tunnel state
+ * @state: Atomic state
+ * @crtc: CRTC to add the tunnel state for
+ *
+ * Add the DP tunnel state for @crtc if the CRTC (aka DP tunnel stream) is enabled
+ * via a DP tunnel.
+ *
+ * Return 0 in case of success, a negative error code otherwise.
+ */
+int intel_dp_tunnel_atomic_add_state_for_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_dp_tunnel_state *tunnel_state;
+ struct drm_dp_tunnel *tunnel = new_crtc_state->dp_tunnel_ref.tunnel;
+
+ if (!tunnel)
+ return 0;
+
+ tunnel_state = drm_dp_tunnel_atomic_get_state(&state->base, tunnel);
+ if (IS_ERR(tunnel_state))
+ return PTR_ERR(tunnel_state);
+
+ return 0;
+}
+
+static int check_group_state(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ struct intel_connector *connector,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!crtc_state->dp_tunnel_ref.tunnel)
+ return 0;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s][CRTC:%d:%s] Adding group state for tunnel %p\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ crtc_state->dp_tunnel_ref.tunnel);
+
+ return intel_dp_tunnel_atomic_add_group_state(state, crtc_state->dp_tunnel_ref.tunnel);
+}
+
+/**
+ * intel_dp_tunnel_atomic_check_state - Check a connector's DP tunnel specific state
+ * @state: Atomic state
+ * @intel_dp: DP port object
+ * @connector: connector using @intel_dp
+ *
+ * Check and add the DP tunnel atomic state for @intel_dp/@connector to
+ * @state, if there is a DP tunnel detected on @intel_dp with BW allocation
+ * mode enabled on it, or if @intel_dp/@connector was previously enabled via a
+ * DP tunnel.
+ *
+ * Returns 0 in case of success, or a negative error code otherwise.
+ */
+int intel_dp_tunnel_atomic_check_state(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ struct intel_connector *connector)
+{
+ const struct intel_digital_connector_state *old_conn_state =
+ intel_atomic_get_old_connector_state(state, connector);
+ const struct intel_digital_connector_state *new_conn_state =
+ intel_atomic_get_new_connector_state(state, connector);
+ int err;
+
+ if (old_conn_state->base.crtc) {
+ err = check_group_state(state, intel_dp, connector,
+ to_intel_crtc(old_conn_state->base.crtc));
+ if (err)
+ return err;
+ }
+
+ if (new_conn_state->base.crtc &&
+ new_conn_state->base.crtc != old_conn_state->base.crtc) {
+ err = check_group_state(state, intel_dp, connector,
+ to_intel_crtc(new_conn_state->base.crtc));
+ if (err)
+ return err;
+ }
+
+ return check_inherited_tunnel_state(state, intel_dp, old_conn_state);
+}
+
+/**
+ * intel_dp_tunnel_atomic_compute_stream_bw - Compute the BW required by a DP tunnel stream
+ * @state: Atomic state
+ * @intel_dp: DP object
+ * @connector: connector using @intel_dp
+ * @crtc_state: state of CRTC of the given DP tunnel stream
+ *
+ * Compute the required BW of CRTC (aka DP tunnel stream), storing this BW to
+ * the DP tunnel state containing the stream in @state. Before re-calculating a
+ * BW requirement in the crtc_state state the old BW requirement computed by this
+ * function must be cleared by calling intel_dp_tunnel_atomic_clear_stream_bw().
+ *
+ * Returns 0 in case of success, a negative error code otherwise.
+ */
+int intel_dp_tunnel_atomic_compute_stream_bw(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ int required_rate = intel_dp_config_required_rate(crtc_state);
+ int ret;
+
+ if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+ return 0;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][CONNECTOR:%d:%s][ENCODER:%d:%s][CRTC:%d:%s] Stream %d required BW %d Mb/s\n",
+ drm_dp_tunnel_name(intel_dp->tunnel),
+ connector->base.base.id, connector->base.name,
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ crtc->pipe,
+ kbytes_to_mbits(required_rate));
+
+ ret = drm_dp_tunnel_atomic_set_stream_bw(&state->base, intel_dp->tunnel,
+ crtc->pipe, required_rate);
+ if (ret < 0)
+ return ret;
+
+ drm_dp_tunnel_ref_get(intel_dp->tunnel,
+ &crtc_state->dp_tunnel_ref);
+
+ return 0;
+}
+
+/**
+ * intel_dp_tunnel_atomic_clear_stream_bw - Clear any DP tunnel stream BW requirement
+ * @state: Atomic state
+ * @crtc_state: state of CRTC of the given DP tunnel stream
+ *
+ * Clear any DP tunnel stream BW requirement set by
+ * intel_dp_tunnel_atomic_compute_stream_bw().
+ */
+void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (!crtc_state->dp_tunnel_ref.tunnel)
+ return;
+
+ drm_dp_tunnel_atomic_set_stream_bw(&state->base,
+ crtc_state->dp_tunnel_ref.tunnel,
+ crtc->pipe, 0);
+ drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);
+}
+
+/**
+ * intel_dp_tunnel_atomic_check_link - Check the DP tunnel atomic state
+ * @state: intel atomic state
+ * @limits: link BW limits
+ *
+ * Check the link configuration for all DP tunnels in @state. If the
+ * configuration is invalid @limits will be updated if possible to
+ * reduce the total BW, after which the configuration for all CRTCs in
+ * @state must be recomputed with the updated @limits.
+ *
+ * Returns:
+ * - 0 if the confugration is valid
+ * - %-EAGAIN, if the configuration is invalid and @limits got updated
+ * with fallback values with which the configuration of all CRTCs in
+ * @state must be recomputed
+ * - Other negative error, if the configuration is invalid without a
+ * fallback possibility, or the check failed for another reason
+ */
+int intel_dp_tunnel_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ u32 failed_stream_mask;
+ int err;
+
+ err = drm_dp_tunnel_atomic_check_stream_bws(&state->base,
+ &failed_stream_mask);
+ if (err != -ENOSPC)
+ return err;
+
+ err = intel_link_bw_reduce_bpp(state, limits,
+ failed_stream_mask, "DP tunnel link BW");
+
+ return err ? : -EAGAIN;
+}
+
+static void atomic_decrease_bw(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ const struct intel_crtc_state *old_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
+ int i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ const struct drm_dp_tunnel_state *new_tunnel_state;
+ struct drm_dp_tunnel *tunnel;
+ int old_bw;
+ int new_bw;
+
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ continue;
+
+ tunnel = get_inherited_tunnel(state, crtc);
+ if (!tunnel)
+ tunnel = old_crtc_state->dp_tunnel_ref.tunnel;
+
+ if (!tunnel)
+ continue;
+
+ old_bw = drm_dp_tunnel_get_allocated_bw(tunnel);
+
+ new_tunnel_state = drm_dp_tunnel_atomic_get_new_state(&state->base, tunnel);
+ new_bw = drm_dp_tunnel_atomic_get_required_bw(new_tunnel_state);
+
+ if (new_bw >= old_bw)
+ continue;
+
+ drm_dp_tunnel_alloc_bw(tunnel, new_bw);
+ }
+}
+
+static void queue_retry_work(struct intel_atomic_state *state,
+ struct drm_dp_tunnel *tunnel,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_encoder *encoder;
+
+ encoder = intel_get_crtc_new_encoder(state, crtc_state);
+
+ if (!intel_digital_port_connected(encoder))
+ return;
+
+ drm_dbg_kms(&i915->drm,
+ "[DPTUN %s][ENCODER:%d:%s] BW allocation failed on a connected sink\n",
+ drm_dp_tunnel_name(tunnel),
+ encoder->base.base.id,
+ encoder->base.name);
+
+ intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
+}
+
+static void atomic_increase_bw(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ const struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ struct drm_dp_tunnel_state *tunnel_state;
+ struct drm_dp_tunnel *tunnel = crtc_state->dp_tunnel_ref.tunnel;
+ int bw;
+
+ if (!intel_crtc_needs_modeset(crtc_state))
+ continue;
+
+ if (!tunnel)
+ continue;
+
+ tunnel_state = drm_dp_tunnel_atomic_get_new_state(&state->base, tunnel);
+
+ bw = drm_dp_tunnel_atomic_get_required_bw(tunnel_state);
+
+ if (drm_dp_tunnel_alloc_bw(tunnel, bw) != 0)
+ queue_retry_work(state, tunnel, crtc_state);
+ }
+}
+
+/**
+ * intel_dp_tunnel_atomic_alloc_bw - Allocate the BW for all modeset tunnels
+ * @state: Atomic state
+ *
+ * Allocate the required BW for all tunnels in @state.
+ */
+void intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state)
+{
+ atomic_decrease_bw(state);
+ atomic_increase_bw(state);
+}
+
+/**
+ * intel_dp_tunnel_mgr_init - Initialize the DP tunnel manager
+ * @i915: i915 device object
+ *
+ * Initialize the DP tunnel manager. The tunnel manager will support the
+ * detection/management of DP tunnels on all DP connectors, so the function
+ * must be called after all these connectors have been registered already.
+ *
+ * Return 0 in case of success, a negative error code otherwise.
+ */
+int intel_dp_tunnel_mgr_init(struct drm_i915_private *i915)
+{
+ struct drm_dp_tunnel_mgr *tunnel_mgr;
+ struct drm_connector_list_iter connector_list_iter;
+ struct intel_connector *connector;
+ int dp_connectors = 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &connector_list_iter);
+ for_each_intel_connector_iter(connector, &connector_list_iter) {
+ if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ dp_connectors++;
+ }
+ drm_connector_list_iter_end(&connector_list_iter);
+
+ tunnel_mgr = drm_dp_tunnel_mgr_create(&i915->drm, dp_connectors);
+ if (IS_ERR(tunnel_mgr))
+ return PTR_ERR(tunnel_mgr);
+
+ i915->display.dp_tunnel_mgr = tunnel_mgr;
+
+ return 0;
+}
+
+/**
+ * intel_dp_tunnel_mgr_cleanup - Clean up the DP tunnel manager state
+ * @i915: i915 device object
+ *
+ * Clean up the DP tunnel manager state.
+ */
+void intel_dp_tunnel_mgr_cleanup(struct drm_i915_private *i915)
+{
+ drm_dp_tunnel_mgr_destroy(i915->display.dp_tunnel_mgr);
+ i915->display.dp_tunnel_mgr = NULL;
+}
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DP_TUNNEL_H__
+#define __INTEL_DP_TUNNEL_H__
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct drm_connector_state;
+struct drm_modeset_acquire_ctx;
+
+struct intel_atomic_state;
+struct intel_connector;
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_dp;
+struct intel_encoder;
+struct intel_link_bw_limits;
+
+#if defined(CONFIG_DRM_I915_DP_TUNNEL) && defined(I915)
+
+int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx);
+void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp);
+void intel_dp_tunnel_destroy(struct intel_dp *intel_dp);
+void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dpcd_updated);
+void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
+
+bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
+
+void
+intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state);
+
+int intel_dp_tunnel_atomic_compute_stream_bw(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ struct intel_crtc_state *crtc_state);
+void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state);
+
+int intel_dp_tunnel_atomic_add_state_for_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+int intel_dp_tunnel_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
+int intel_dp_tunnel_atomic_check_state(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ struct intel_connector *connector);
+
+void intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state);
+
+int intel_dp_tunnel_mgr_init(struct drm_i915_private *i915);
+void intel_dp_tunnel_mgr_cleanup(struct drm_i915_private *i915);
+
+#else
+
+static inline int
+intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp) {}
+static inline void intel_dp_tunnel_destroy(struct intel_dp *intel_dp) {}
+static inline void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dpcd_updated) {}
+static inline void intel_dp_tunnel_suspend(struct intel_dp *intel_dp) {}
+
+static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
+{
+ return false;
+}
+
+static inline void
+intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state) {}
+
+static inline int
+intel_dp_tunnel_atomic_compute_stream_bw(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
+ struct intel_crtc_state *crtc_state)
+{
+ return 0;
+}
+
+static inline void
+intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state) {}
+
+static inline int
+intel_dp_tunnel_atomic_add_state_for_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ return 0;
+}
+
+static inline int
+intel_dp_tunnel_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ return 0;
+}
+
+static inline int
+intel_dp_tunnel_atomic_check_state(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
+ struct intel_connector *connector)
+{
+ return 0;
+}
+
+static inline int
+intel_dp_tunnel_atomic_alloc_bw(struct intel_atomic_state *state)
+{
+ return 0;
+}
+
+static inline int
+intel_dp_tunnel_mgr_init(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static inline void intel_dp_tunnel_mgr_cleanup(struct drm_i915_private *i915) {}
+
+#endif /* CONFIG_DRM_I915_DP_TUNNEL */
+
+#endif /* __INTEL_DP_TUNNEL_H__ */
void (*update_ref_clks)(struct drm_i915_private *i915);
void (*dump_hw_state)(struct drm_i915_private *i915,
const struct intel_dpll_hw_state *hw_state);
+ bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b);
};
static void
hw_state->fp1);
}
+static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ return a->dpll == b->dpll &&
+ a->dpll_md == b->dpll_md &&
+ a->fp0 == b->fp0 &&
+ a->fp1 == b->fp1;
+}
+
static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_dplls = ibx_get_dpll,
.put_dplls = intel_put_dpll,
.dump_hw_state = ibx_dump_hw_state,
+ .compare_hw_state = ibx_compare_hw_state,
};
static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
hw_state->wrpll, hw_state->spll);
}
+static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ return a->wrpll == b->wrpll &&
+ a->spll == b->spll;
+}
+
static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.put_dplls = intel_put_dpll,
.update_ref_clks = hsw_update_dpll_ref_clks,
.dump_hw_state = hsw_dump_hw_state,
+ .compare_hw_state = hsw_compare_hw_state,
};
struct skl_dpll_regs {
hw_state->cfgcr2);
}
+static bool skl_compare_hw_state(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ return a->ctrl1 == b->ctrl1 &&
+ a->cfgcr1 == b->cfgcr1 &&
+ a->cfgcr2 == b->cfgcr2;
+}
+
static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.put_dplls = intel_put_dpll,
.update_ref_clks = skl_update_dpll_ref_clks,
.dump_hw_state = skl_dump_hw_state,
+ .compare_hw_state = skl_compare_hw_state,
};
static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
hw_state->pcsdw12);
}
+static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ return a->ebb0 == b->ebb0 &&
+ a->ebb4 == b->ebb4 &&
+ a->pll0 == b->pll0 &&
+ a->pll1 == b->pll1 &&
+ a->pll2 == b->pll2 &&
+ a->pll3 == b->pll3 &&
+ a->pll6 == b->pll6 &&
+ a->pll8 == b->pll8 &&
+ a->pll10 == b->pll10 &&
+ a->pcsdw12 == b->pcsdw12;
+}
+
static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.put_dplls = intel_put_dpll,
.update_ref_clks = bxt_update_dpll_ref_clks,
.dump_hw_state = bxt_dump_hw_state,
+ .compare_hw_state = bxt_compare_hw_state,
};
static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
hw_state->mg_pll_tdc_coldst_bias);
}
+static bool icl_compare_hw_state(const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ /* FIXME split combo vs. mg more thoroughly */
+ return a->cfgcr0 == b->cfgcr0 &&
+ a->cfgcr1 == b->cfgcr1 &&
+ a->div0 == b->div0 &&
+ a->mg_refclkin_ctl == b->mg_refclkin_ctl &&
+ a->mg_clktop2_coreclkctl1 == b->mg_clktop2_coreclkctl1 &&
+ a->mg_clktop2_hsclkctl == b->mg_clktop2_hsclkctl &&
+ a->mg_pll_div0 == b->mg_pll_div0 &&
+ a->mg_pll_div1 == b->mg_pll_div1 &&
+ a->mg_pll_lf == b->mg_pll_lf &&
+ a->mg_pll_frac_lock == b->mg_pll_frac_lock &&
+ a->mg_pll_ssc == b->mg_pll_ssc &&
+ a->mg_pll_bias == b->mg_pll_bias &&
+ a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
+}
+
static const struct intel_shared_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.update_active_dpll = icl_update_active_dpll,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct dpll_info ehl_plls[] = {
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
.update_active_dpll = icl_update_active_dpll,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct dpll_info rkl_plls[] = {
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct dpll_info dg1_plls[] = {
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct dpll_info adls_plls[] = {
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
static const struct dpll_info adlp_plls[] = {
.update_active_dpll = icl_update_active_dpll,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
+ .compare_hw_state = icl_compare_hw_state,
};
/**
/* fallback for platforms that don't use the shared dpll
* infrastructure
*/
- drm_dbg_kms(&i915->drm,
- "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
- "fp0: 0x%x, fp1: 0x%x\n",
- hw_state->dpll,
- hw_state->dpll_md,
- hw_state->fp0,
- hw_state->fp1);
+ ibx_dump_hw_state(i915, hw_state);
+ }
+}
+
+/**
+ * intel_dpll_compare_hw_state - compare the two states
+ * @i915: i915 drm device
+ * @a: first DPLL hw state
+ * @b: second DPLL hw state
+ *
+ * Compare DPLL hw states @a and @b.
+ *
+ * Returns: true if the states are equal, false if the differ
+ */
+bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+ const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b)
+{
+ if (i915->display.dpll.mgr) {
+ return i915->display.dpll.mgr->compare_hw_state(a, b);
+ } else {
+ /* fallback for platforms that don't use the shared dpll
+ * infrastructure
+ */
+ return ibx_compare_hw_state(a, b);
}
}
void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_dpll_hw_state *hw_state);
+bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+ const struct intel_dpll_hw_state *a,
+ const struct intel_dpll_hw_state *b);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
static int intel_drrs_debugfs_status_show(struct seq_file *m, void *unused)
{
struct intel_crtc *crtc = m->private;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
const struct intel_crtc_state *crtc_state;
int ret;
mutex_lock(&crtc->drrs.mutex);
+ seq_printf(m, "DRRS capable: %s\n",
+ str_yes_no(crtc_state->has_drrs ||
+ HAS_DOUBLE_BUFFERED_M_N(i915) ||
+ intel_cpu_transcoder_has_m2_n2(i915, crtc_state->cpu_transcoder)));
+
seq_printf(m, "DRRS enabled: %s\n",
str_yes_no(crtc_state->has_drrs));
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- unsigned int latency = skl_watermark_max_latency(i915);
+ unsigned int latency = skl_watermark_max_latency(i915, 0);
int vblank_start;
if (crtc_state->vrr.enable) {
u16 phys; /* ICL DSI */
};
- /* if true, use HS mode, otherwise LP */
- bool hs;
-
/* virtual channel */
int channel;
bool bgr_enabled;
u8 pixel_overlap;
- u32 port_bits;
u32 bw_timer;
u32 dphy_reg;
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
#include "i915_drv.h"
#include "i915_reg.h"
static int intel_dvo_get_modes(struct drm_connector *_connector)
{
struct intel_connector *connector = to_intel_connector(_connector);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
int num_modes;
+ if (!intel_display_driver_check_access(i915))
+ return drm_edid_connector_add_modes(&connector->base);
+
/*
* We should probably have an i2c driver get_modes function for those
* devices which will have a fixed set of modes determined by the chip
bool (*init)(struct intel_dvo_device *dvo,
struct i2c_adapter *i2cbus);
- /*
- * Called to allow the output a chance to create properties after the
- * RandR objects have been created.
- */
- void (*create_resources)(struct intel_dvo_device *dvo);
-
/*
* Turn on/off output.
*
enum drm_mode_status (*mode_valid)(struct intel_dvo_device *dvo,
struct drm_display_mode *mode);
- /*
- * Callback for preparing mode changes on an output
- */
- void (*prepare)(struct intel_dvo_device *dvo);
-
- /*
- * Callback for committing mode changes on an output
- */
- void (*commit)(struct intel_dvo_device *dvo);
-
/*
* Callback for setting up a video mode after fixups have been made.
*
*/
bool (*get_hw_state)(struct intel_dvo_device *dev);
- /**
- * Query the device for the modes it provides.
- *
- * This function may also update MonInfo, mm_width, and mm_height.
- *
- * \return singly-linked list of modes or NULL if no modes found.
- */
- struct drm_display_mode *(*get_modes)(struct intel_dvo_device *dvo);
-
/**
* Clean up driver-specific bits of the output
*/
fb->modifier, rotation);
if (stride > max_stride) {
- DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
- fb->base.id, stride,
- plane->base.base.id, plane->base.name, max_stride);
+ drm_dbg_kms(plane->base.dev,
+ "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
+ fb->base.id, stride,
+ plane->base.base.id, plane->base.name, max_stride);
return -EINVAL;
}
(__i)++) \
for_each_if(obj)
-#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \
+#define for_each_old_global_obj_in_state(__state, obj, old_obj_state, __i) \
for ((__i) = 0; \
(__i) < (__state)->num_global_objs && \
((obj) = (__state)->global_objs[__i].ptr, \
- (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \
+ (old_obj_state) = (__state)->global_objs[__i].old_state, 1); \
(__i)++) \
for_each_if(obj)
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
-static int intel_conn_to_vcpi(struct drm_atomic_state *state,
+static int intel_conn_to_vcpi(struct intel_atomic_state *state,
struct intel_connector *connector)
{
struct drm_dp_mst_topology_mgr *mgr;
return 0;
mgr = connector->port->mgr;
- drm_modeset_lock(&mgr->base.lock, state->acquire_ctx);
+ drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx);
mst_state = to_drm_dp_mst_topology_state(mgr->base.state);
payload = drm_atomic_get_mst_payload_state(mst_state, connector->port);
if (drm_WARN_ON(mgr->dev, !payload))
* DP MST topology. Though it is not compulsory, security fw should change its
* policy to mark different content_types for different streams.
*/
-static void
-intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+static int
+intel_hdcp_required_content_stream(struct intel_atomic_state *state,
+ struct intel_digital_port *dig_port)
{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
bool enforce_type0 = false;
int k;
if (dig_port->hdcp_auth_status)
- return;
+ return 0;
+
+ data->k = 0;
if (!dig_port->hdcp_mst_type1_capable)
enforce_type0 = true;
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ data->streams[data->k].stream_id =
+ intel_conn_to_vcpi(state, connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
+ return -EINVAL;
+
/*
* Apply common protection level across all streams in DP MST Topology.
* Use highest supported content type for all streams in DP MST Topology.
for (k = 0; k < data->k; k++)
data->streams[k].stream_type =
enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
}
-static void intel_hdcp_prepare_streams(struct intel_connector *connector)
+static int intel_hdcp_prepare_streams(struct intel_atomic_state *state,
+ struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
- if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
- data->streams[0].stream_type = hdcp->content_type;
- } else {
- intel_hdcp_required_content_stream(dig_port);
- }
+ if (intel_encoder_is_mst(intel_attached_encoder(connector)))
+ return intel_hdcp_required_content_stream(state, dig_port);
+
+ data->k = 1;
+ data->streams[0].stream_id = 0;
+ data->streams[0].stream_type = hdcp->content_type;
+
+ return 0;
}
static
}
/* Is HDCP1.4 capable on Platform and Sink */
-bool intel_hdcp_capable(struct intel_connector *connector)
+bool intel_hdcp_get_capability(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
const struct intel_hdcp_shim *shim = connector->hdcp.shim;
if (!shim)
return capable;
- if (shim->hdcp_capable) {
- shim->hdcp_capable(dig_port, &capable);
+ if (shim->hdcp_get_capability) {
+ shim->hdcp_get_capability(dig_port, &capable);
} else {
if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv))
capable = true;
return capable;
}
-/* Is HDCP2.2 capable on Platform and Sink */
-bool intel_hdcp2_capable(struct intel_connector *connector)
+/*
+ * Check if the source has all the building blocks ready to make
+ * HDCP 2.2 work
+ */
+static bool intel_hdcp2_prerequisite(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
- bool capable = false;
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
}
mutex_unlock(&i915->display.hdcp.hdcp_mutex);
+ return true;
+}
+
+/* Is HDCP2.2 capable on Platform and Sink */
+bool intel_hdcp2_get_capability(struct intel_connector *connector)
+{
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ bool capable = false;
+
+ if (!intel_hdcp2_prerequisite(connector))
+ return false;
+
/* Sink's capability for HDCP2.2 */
- hdcp->shim->hdcp_2_2_capable(connector, &capable);
+ hdcp->shim->hdcp_2_2_get_capability(connector, &capable);
return capable;
}
+void intel_hdcp_get_remote_capability(struct intel_connector *connector,
+ bool *hdcp_capable,
+ bool *hdcp2_capable)
+{
+ struct intel_hdcp *hdcp = &connector->hdcp;
+
+ if (!hdcp->shim->get_remote_hdcp_capability)
+ return;
+
+ hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable,
+ hdcp2_capable);
+
+ if (!intel_hdcp2_prerequisite(connector))
+ *hdcp2_capable = false;
+}
+
static bool intel_hdcp_in_use(struct drm_i915_private *i915,
enum transcoder cpu_transcoder, enum port port)
{
* whether the display supports HDCP before we write An. For HDMI
* displays, this is not necessary.
*/
- if (shim->hdcp_capable) {
- ret = shim->hdcp_capable(dig_port, &hdcp_capable);
+ if (shim->hdcp_get_capability) {
+ ret = shim->hdcp_get_capability(dig_port, &hdcp_capable);
if (ret)
return ret;
if (!hdcp_capable) {
goto out;
}
- ret = intel_hdcp1_enable(connector);
- if (ret) {
- drm_err(&i915->drm, "Failed to enable hdcp (%d)\n", ret);
- intel_hdcp_update_value(connector,
- DRM_MODE_CONTENT_PROTECTION_DESIRED,
- true);
- goto out;
- }
-
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED,
+ true);
out:
mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
-static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
+static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state,
+ struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) {
ret = hdcp2_authenticate_sink(connector);
if (!ret) {
- intel_hdcp_prepare_streams(connector);
+ ret = intel_hdcp_prepare_streams(state, connector);
+ if (ret) {
+ drm_dbg_kms(&i915->drm,
+ "Prepare stream failed.(%d)\n",
+ ret);
+ break;
+ }
ret = hdcp2_propagate_stream_management_info(connector);
if (ret) {
return ret;
}
-static int _intel_hdcp2_enable(struct intel_connector *connector)
+static int _intel_hdcp2_enable(struct intel_atomic_state *state,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
connector->base.base.id, connector->base.name,
hdcp->content_type);
- ret = hdcp2_authenticate_and_encrypt(connector);
+ ret = hdcp2_authenticate_and_encrypt(state, connector);
if (ret) {
drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
hdcp->content_type, ret);
drm_dbg_kms(&i915->drm,
"HDCP2.2 Downstream topology change\n");
- ret = hdcp2_authenticate_repeater_topology(connector);
- if (!ret) {
- intel_hdcp_update_value(connector,
- DRM_MODE_CONTENT_PROTECTION_ENABLED,
- true);
- goto out;
- }
- drm_dbg_kms(&i915->drm,
- "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n",
- connector->base.base.id, connector->base.name,
- ret);
} else {
drm_dbg_kms(&i915->drm,
"[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n",
goto out;
}
- ret = _intel_hdcp2_enable(connector);
- if (ret) {
- drm_dbg_kms(&i915->drm,
- "[CONNECTOR:%d:%s] Failed to enable hdcp2.2 (%d)\n",
- connector->base.base.id, connector->base.name,
- ret);
- intel_hdcp_update_value(connector,
- DRM_MODE_CONTENT_PROTECTION_DESIRED,
- true);
- goto out;
- }
-
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED, true);
out:
mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return 0;
}
-static int
-intel_hdcp_set_streams(struct intel_digital_port *dig_port,
- struct intel_atomic_state *state)
-{
- struct drm_connector_list_iter conn_iter;
- struct intel_digital_port *conn_dig_port;
- struct intel_connector *connector;
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct hdcp_port_data *data = &dig_port->hdcp_port_data;
-
- if (!intel_encoder_is_mst(&dig_port->base)) {
- data->k = 1;
- data->streams[0].stream_id = 0;
- return 0;
- }
-
- data->k = 0;
-
- drm_connector_list_iter_begin(&i915->drm, &conn_iter);
- for_each_intel_connector_iter(connector, &conn_iter) {
- if (connector->base.status == connector_status_disconnected)
- continue;
-
- if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
- continue;
-
- conn_dig_port = intel_attached_dig_port(connector);
- if (conn_dig_port != dig_port)
- continue;
-
- data->streams[data->k].stream_id =
- intel_conn_to_vcpi(&state->base, connector);
- data->k++;
-
- /* if there is only one active stream */
- if (dig_port->dp.active_mst_links <= 1)
- break;
- }
- drm_connector_list_iter_end(&conn_iter);
-
- if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
- return -EINVAL;
-
- return 0;
-}
-
static int _intel_hdcp_enable(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
* is capable of HDCP2.2, it is preferred to use HDCP2.2.
*/
- if (intel_hdcp2_capable(connector)) {
- ret = intel_hdcp_set_streams(dig_port, state);
- if (!ret) {
- ret = _intel_hdcp2_enable(connector);
- if (!ret)
- check_link_interval =
- DRM_HDCP2_CHECK_PERIOD_MS;
- } else {
- drm_dbg_kms(&i915->drm,
- "Set content streams failed: (%d)\n",
- ret);
- }
+ if (intel_hdcp2_get_capability(connector)) {
+ ret = _intel_hdcp2_enable(state, connector);
+ if (!ret)
+ check_link_interval =
+ DRM_HDCP2_CHECK_PERIOD_MS;
}
/*
* When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will
* be attempted.
*/
- if (ret && intel_hdcp_capable(connector) &&
+ if (ret && intel_hdcp_get_capability(connector) &&
hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) {
ret = intel_hdcp1_enable(connector);
}
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool is_hdcp_supported(struct drm_i915_private *i915, enum port port);
-bool intel_hdcp_capable(struct intel_connector *connector);
-bool intel_hdcp2_capable(struct intel_connector *connector);
+bool intel_hdcp_get_capability(struct intel_connector *connector);
+bool intel_hdcp2_get_capability(struct intel_connector *connector);
+void intel_hdcp_get_remote_capability(struct intel_connector *connector,
+ bool *hdcp_capable,
+ bool *hdcp2_capable);
void intel_hdcp_component_init(struct drm_i915_private *i915);
void intel_hdcp_component_fini(struct drm_i915_private *i915);
void intel_hdcp_cleanup(struct intel_connector *connector);
}
static
-int intel_hdmi_hdcp2_capable(struct intel_connector *connector,
- bool *capable)
+int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector,
+ bool *capable)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
u8 hdcp2_version;
.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
.check_2_2_link = intel_hdmi_hdcp2_check_link,
- .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
+ .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability,
.protocol = HDCP_PROTOCOL_HDMI,
};
#include "i915_drv.h"
#include "intel_atomic.h"
+#include "intel_crtc.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
+#include "intel_dp_tunnel.h"
#include "intel_fdi.h"
#include "intel_link_bw.h"
/**
* intel_link_bw_init_limits - initialize BW limits
- * @i915: device instance
+ * @state: Atomic state
* @limits: link BW limits
*
* Initialize @limits.
*/
-void intel_link_bw_init_limits(struct drm_i915_private *i915, struct intel_link_bw_limits *limits)
+void intel_link_bw_init_limits(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
enum pipe pipe;
limits->force_fec_pipes = 0;
limits->bpp_limit_reached_pipes = 0;
- for_each_pipe(i915, pipe)
- limits->max_bpp_x16[pipe] = INT_MAX;
+ for_each_pipe(i915, pipe) {
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+ intel_crtc_for_pipe(i915, pipe));
+
+ if (state->base.duplicated && crtc_state) {
+ limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;
+ if (crtc_state->fec_enable)
+ limits->force_fec_pipes |= BIT(pipe);
+ } else {
+ limits->max_bpp_x16[pipe] = INT_MAX;
+ }
+ }
}
/**
if (ret)
return ret;
+ ret = intel_dp_tunnel_atomic_check_link(state, limits);
+ if (ret)
+ return ret;
+
ret = intel_fdi_atomic_check_link(state, limits);
if (ret)
return ret;
int max_bpp_x16[I915_MAX_PIPES];
};
-void intel_link_bw_init_limits(struct drm_i915_private *i915,
+void intel_link_bw_init_limits(struct intel_atomic_state *state,
struct intel_link_bw_limits *limits);
int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
struct intel_link_bw_limits *limits,
return ret;
}
- if (intel_bios_is_valid_vbt(fw->data, fw->size)) {
+ if (intel_bios_is_valid_vbt(dev_priv, fw->data, fw->size)) {
opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL);
if (opregion->vbt_firmware) {
drm_dbg_kms(&dev_priv->drm,
vbt = opregion->rvda;
vbt_size = opregion->asle->rvds;
- if (intel_bios_is_valid_vbt(vbt, vbt_size)) {
+ if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) {
drm_dbg_kms(&dev_priv->drm,
"Found valid VBT in ACPI OpRegion (RVDA)\n");
opregion->vbt = vbt;
vbt_size = (mboxes & MBOX_ASLE_EXT) ?
OPREGION_ASLE_EXT_OFFSET : OPREGION_SIZE;
vbt_size -= OPREGION_VBT_OFFSET;
- if (intel_bios_is_valid_vbt(vbt, vbt_size)) {
+ if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) {
drm_dbg_kms(&dev_priv->drm,
"Found valid VBT in ACPI OpRegion (Mailbox #4)\n");
opregion->vbt = vbt;
static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct i2c_msg msgs[] = {
{
.addr = intel_sdvo->slave_addr,
if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
return true;
- DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
+ drm_dbg_kms(&i915->drm, "i2c transfer returned %d\n", ret);
return false;
}
drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
#undef BUF_PRINT
- DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
+ drm_dbg_kms(&dev_priv->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),
+ cmd, buffer);
}
static const char * const cmd_status_names[] = {
const void *args, int args_len,
bool unlocked)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
u8 *buf, status;
struct i2c_msg *msgs;
int i, ret = true;
else
ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
if (ret < 0) {
- DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
+ drm_dbg_kms(&i915->drm, "I2c transfer returned %d\n", ret);
ret = false;
goto out;
}
if (ret != i+3) {
/* failure in I2C transfer */
- DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
+ drm_dbg_kms(&i915->drm, "I2c transfer returned %d/%d\n", ret, i+3);
ret = false;
}
drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
#undef BUF_PRINT
- DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
+ drm_dbg_kms(&dev_priv->drm, "%s: R: %s\n",
+ SDVO_NAME(intel_sdvo), buffer);
return true;
log_fail:
- DRM_DEBUG_KMS("%s: R: ... failed %s\n",
- SDVO_NAME(intel_sdvo), buffer);
+ drm_dbg_kms(&dev_priv->drm, "%s: R: ... failed %s\n",
+ SDVO_NAME(intel_sdvo), buffer);
return false;
}
}
static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
- struct intel_sdvo_dtd *dtd)
+ struct intel_sdvo_dtd *dtd)
{
return intel_sdvo_set_timing(intel_sdvo,
SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
BUILD_BUG_ON(sizeof(encode) != 2);
return intel_sdvo_get_value(intel_sdvo,
- SDVO_CMD_GET_SUPP_ENCODE,
- &encode, sizeof(encode));
+ SDVO_CMD_GET_SUPP_ENCODE,
+ &encode, sizeof(encode));
}
static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
unsigned int if_index, u8 tx_rate,
const u8 *data, unsigned int length)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
u8 set_buf_index[2] = { if_index, 0 };
u8 hbuf_size, tmp[8];
int i;
if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
return false;
- DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
- if_index, length, hbuf_size);
+ drm_dbg_kms(&i915->drm,
+ "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
+ if_index, length, hbuf_size);
if (hbuf_size < length)
return false;
unsigned int if_index,
u8 *data, unsigned int length)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
u8 set_buf_index[2] = { if_index, 0 };
u8 hbuf_size, tx_rate, av_split;
int i;
if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
return false;
- DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
- if_index, length, hbuf_size);
+ drm_dbg_kms(&i915->drm,
+ "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
+ if_index, length, hbuf_size);
hbuf_size = min_t(unsigned int, length, hbuf_size);
static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
ssize_t len;
len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
sdvo_data, sizeof(sdvo_data));
if (len < 0) {
- DRM_DEBUG_KMS("failed to read AVI infoframe\n");
+ drm_dbg_kms(&i915->drm, "failed to read AVI infoframe\n");
return;
} else if (len == 0) {
return;
ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
if (ret) {
- DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
+ drm_dbg_kms(&i915->drm, "Failed to unpack AVI infoframe\n");
return;
}
if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
- DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
- frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
+ drm_dbg_kms(&i915->drm,
+ "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
+ frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
}
static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(conn_state->connector);
return -EINVAL;
}
- DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
+ drm_dbg_kms(&i915->drm, "forcing bpc to 8 for SDVO\n");
/* FIXME: Don't increase pipe_bpp */
pipe_config->pipe_bpp = 8*3;
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
pipe_config, conn_state)) {
- DRM_DEBUG_KMS("bad AVI infoframe\n");
+ drm_dbg_kms(&i915->drm, "bad AVI infoframe\n");
return -EINVAL;
}
*/
if (success && !input1) {
drm_dbg_kms(&dev_priv->drm,
- "First %s output reported failure to "
- "sync\n", SDVO_NAME(intel_sdvo));
+ "First %s output reported failure to sync\n",
+ SDVO_NAME(intel_sdvo));
}
if (0)
static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
BUILD_BUG_ON(sizeof(*caps) != 8);
if (!intel_sdvo_get_value(intel_sdvo,
SDVO_CMD_GET_DEVICE_CAPS,
caps, sizeof(*caps)))
return false;
- DRM_DEBUG_KMS("SDVO capabilities:\n"
- " vendor_id: %d\n"
- " device_id: %d\n"
- " device_rev_id: %d\n"
- " sdvo_version_major: %d\n"
- " sdvo_version_minor: %d\n"
- " sdvo_num_inputs: %d\n"
- " smooth_scaling: %d\n"
- " sharp_scaling: %d\n"
- " up_scaling: %d\n"
- " down_scaling: %d\n"
- " stall_support: %d\n"
- " output_flags: %d\n",
- caps->vendor_id,
- caps->device_id,
- caps->device_rev_id,
- caps->sdvo_version_major,
- caps->sdvo_version_minor,
- caps->sdvo_num_inputs,
- caps->smooth_scaling,
- caps->sharp_scaling,
- caps->up_scaling,
- caps->down_scaling,
- caps->stall_support,
- caps->output_flags);
+ drm_dbg_kms(&i915->drm, "SDVO capabilities:\n"
+ " vendor_id: %d\n"
+ " device_id: %d\n"
+ " device_rev_id: %d\n"
+ " sdvo_version_major: %d\n"
+ " sdvo_version_minor: %d\n"
+ " sdvo_num_inputs: %d\n"
+ " smooth_scaling: %d\n"
+ " sharp_scaling: %d\n"
+ " up_scaling: %d\n"
+ " down_scaling: %d\n"
+ " stall_support: %d\n"
+ " output_flags: %d\n",
+ caps->vendor_id,
+ caps->device_id,
+ caps->device_rev_id,
+ caps->sdvo_version_major,
+ caps->sdvo_version_minor,
+ caps->sdvo_num_inputs,
+ caps->smooth_scaling,
+ caps->sharp_scaling,
+ caps->up_scaling,
+ caps->down_scaling,
+ caps->stall_support,
+ caps->output_flags);
return true;
}
return 0;
if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
- &hotplug, sizeof(hotplug)))
+ &hotplug, sizeof(hotplug)))
return 0;
return hotplug;
bool monitor_is_digital = drm_edid_is_digital(drm_edid);
bool connector_is_digital = !!IS_DIGITAL(sdvo);
- DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
- connector_is_digital, monitor_is_digital);
+ drm_dbg_kms(sdvo->base.base.dev,
+ "connector_is_digital? %d, monitor_is_digital? %d\n",
+ connector_is_digital, monitor_is_digital);
return connector_is_digital == monitor_is_digital;
}
enum drm_connector_status ret;
u16 response;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
+ drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
if (!intel_display_device_enabled(i915))
return connector_status_disconnected;
&response, 2))
return connector_status_unknown;
- DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
- response & 0xff, response >> 8,
- intel_sdvo_connector->output_flag);
+ drm_dbg_kms(&i915->drm, "SDVO response %d %d [%x]\n",
+ response & 0xff, response >> 8,
+ intel_sdvo_connector->output_flag);
if (response == 0)
return connector_status_disconnected;
static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
{
+ struct drm_i915_private *i915 = to_i915(connector->dev);
int num_modes = 0;
const struct drm_edid *drm_edid;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
+
+ if (!intel_display_driver_check_access(i915))
+ return drm_edid_connector_add_modes(connector);
/* set the bus switch and get the modes */
drm_edid = intel_sdvo_get_edid(connector);
static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
{
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(connector);
const struct drm_connector_state *conn_state = connector->state;
int num_modes = 0;
int i;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
+ drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
+
+ if (!intel_display_driver_check_access(i915))
+ return 0;
/*
* Read the list of supported input resolutions for the selected TV
struct drm_encoder *encoder = &intel_sdvo->base.base;
struct drm_connector *connector;
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
+ struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
struct intel_connector *intel_connector;
struct intel_sdvo_connector *intel_sdvo_connector;
- DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type);
+ drm_dbg_kms(&i915->drm, "initialising DVI type 0x%x\n", type);
intel_sdvo_connector = intel_sdvo_connector_alloc();
if (!intel_sdvo_connector)
intel_connector = &intel_sdvo_connector->base;
connector = &intel_connector->base;
if (intel_sdvo_get_hotplug_support(intel_sdvo) &
- intel_sdvo_connector->output_flag) {
+ intel_sdvo_connector->output_flag) {
intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
/*
* Some SDVO devices have one-shot hotplug interrupts.
static bool
intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct drm_encoder *encoder = &intel_sdvo->base.base;
struct drm_connector *connector;
struct intel_connector *intel_connector;
struct intel_sdvo_connector *intel_sdvo_connector;
- DRM_DEBUG_KMS("initialising TV type 0x%x\n", type);
+ drm_dbg_kms(&i915->drm, "initialising TV type 0x%x\n", type);
intel_sdvo_connector = intel_sdvo_connector_alloc();
if (!intel_sdvo_connector)
static bool
intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct drm_encoder *encoder = &intel_sdvo->base.base;
struct drm_connector *connector;
struct intel_connector *intel_connector;
struct intel_sdvo_connector *intel_sdvo_connector;
- DRM_DEBUG_KMS("initialising analog type 0x%x\n", type);
+ drm_dbg_kms(&i915->drm, "initialising analog type 0x%x\n", type);
intel_sdvo_connector = intel_sdvo_connector_alloc();
if (!intel_sdvo_connector)
struct intel_connector *intel_connector;
struct intel_sdvo_connector *intel_sdvo_connector;
- DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type);
+ drm_dbg_kms(&i915->drm, "initialising LVDS type 0x%x\n", type);
intel_sdvo_connector = intel_sdvo_connector_alloc();
if (!intel_sdvo_connector)
static bool
intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
static const u16 probe_order[] = {
SDVO_OUTPUT_TMDS0,
SDVO_OUTPUT_TMDS1,
flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
if (flags == 0) {
- DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n",
- SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
+ drm_dbg_kms(&i915->drm,
+ "%s: Unknown SDVO output type (0x%04x)\n",
+ SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
return false;
}
intel_sdvo_connector->tv_format =
- drm_property_create(dev, DRM_MODE_PROP_ENUM,
- "mode", intel_sdvo_connector->format_supported_num);
+ drm_property_create(dev, DRM_MODE_PROP_ENUM,
+ "mode", intel_sdvo_connector->format_supported_num);
if (!intel_sdvo_connector->tv_format)
return false;
state_assignment = response; \
drm_object_attach_property(&connector->base, \
intel_sdvo_connector->name, 0); \
- DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
- data_value[0], data_value[1], response); \
+ drm_dbg_kms(dev, #name ": max %d, default %d, current %d\n", \
+ data_value[0], data_value[1], response); \
} \
} while (0)
struct intel_sdvo_connector *intel_sdvo_connector,
struct intel_sdvo_enhancements_reply enhancements)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct drm_device *dev = intel_sdvo->base.base.dev;
struct drm_connector *connector = &intel_sdvo_connector->base.base;
struct drm_connector_state *conn_state = connector->state;
return false;
drm_object_attach_property(&connector->base,
- intel_sdvo_connector->right, 0);
- DRM_DEBUG_KMS("h_overscan: max %d, "
- "default %d, current %d\n",
- data_value[0], data_value[1], response);
+ intel_sdvo_connector->right, 0);
+ drm_dbg_kms(&i915->drm, "h_overscan: max %d, default %d, current %d\n",
+ data_value[0], data_value[1], response);
}
if (enhancements.overscan_v) {
intel_sdvo_connector->max_vscan = data_value[0];
intel_sdvo_connector->top =
drm_property_create_range(dev, 0,
- "top_margin", 0, data_value[0]);
+ "top_margin", 0, data_value[0]);
if (!intel_sdvo_connector->top)
return false;
intel_sdvo_connector->bottom =
drm_property_create_range(dev, 0,
- "bottom_margin", 0, data_value[0]);
+ "bottom_margin", 0, data_value[0]);
if (!intel_sdvo_connector->bottom)
return false;
drm_object_attach_property(&connector->base,
- intel_sdvo_connector->bottom, 0);
- DRM_DEBUG_KMS("v_overscan: max %d, "
- "default %d, current %d\n",
- data_value[0], data_value[1], response);
+ intel_sdvo_connector->bottom, 0);
+ drm_dbg_kms(&i915->drm, "v_overscan: max %d, default %d, current %d\n",
+ data_value[0], data_value[1], response);
}
ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
drm_object_attach_property(&connector->base,
intel_sdvo_connector->dot_crawl, 0);
- DRM_DEBUG_KMS("dot crawl: current %d\n", response);
+ drm_dbg_kms(&i915->drm, "dot crawl: current %d\n", response);
}
return true;
static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
struct intel_sdvo_connector *intel_sdvo_connector)
{
+ struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
union {
struct intel_sdvo_enhancements_reply reply;
u16 response;
SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
&enhancements, sizeof(enhancements)) ||
enhancements.response == 0) {
- DRM_DEBUG_KMS("No enhancement is supported\n");
+ drm_dbg_kms(&i915->drm, "No enhancement is supported\n");
return true;
}
goto err_output;
drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
- "clock range %dMHz - %dMHz, "
- "num inputs: %d, "
- "output 1: %c, output 2: %c\n",
- SDVO_NAME(intel_sdvo),
- intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
- intel_sdvo->caps.device_rev_id,
- intel_sdvo->pixel_clock_min / 1000,
- intel_sdvo->pixel_clock_max / 1000,
- intel_sdvo->caps.sdvo_num_inputs,
- /* check currently supported outputs */
- intel_sdvo->caps.output_flags &
- (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
- SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
- SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
- intel_sdvo->caps.output_flags &
- (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
- SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
+ "clock range %dMHz - %dMHz, "
+ "num inputs: %d, "
+ "output 1: %c, output 2: %c\n",
+ SDVO_NAME(intel_sdvo),
+ intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
+ intel_sdvo->caps.device_rev_id,
+ intel_sdvo->pixel_clock_min / 1000,
+ intel_sdvo->pixel_clock_max / 1000,
+ intel_sdvo->caps.sdvo_num_inputs,
+ /* check currently supported outputs */
+ intel_sdvo->caps.output_flags &
+ (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
+ SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
+ SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
+ intel_sdvo->caps.output_flags &
+ (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
+ SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
return true;
err_output:
if (DISPLAY_VER(dev_priv) == 13)
plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
+ if (GRAPHICS_VER(dev_priv) >= 20 &&
+ fb->modifier == I915_FORMAT_MOD_4_TILED) {
+ plane_ctl |= PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ }
+
return plane_ctl;
}
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
+/*It is expected that DSB can do posted writes to every register in
+ * the pipe and planes within 100us. For flip queue use case, the
+ * recommended DSB execution time is 100us + one SAGV block time.
+ */
+#define DSB_EXE_TIME 100
+
static void skl_sagv_disable(struct drm_i915_private *i915);
/* Stores plane specific WM parameters */
return 0;
}
+/*
+ * If Fixed Refresh Rate:
+ * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
+ * watermark level1 and up and above. If watermark level 1 is
+ * invalid program it with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = DSB execution time
+ * If Variable Refresh Rate:
+ * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
+ * Program PKG_C_LATENCY Added Wake Time = 0
+ */
+static void
+skl_program_dpkgc_latency(struct drm_i915_private *i915, bool vrr_enabled)
+{
+ u32 max_latency = 0;
+ u32 clear = 0, val = 0;
+ u32 added_wake_time = 0;
+
+ if (DISPLAY_VER(i915) < 20)
+ return;
+
+ if (vrr_enabled) {
+ max_latency = LNL_PKG_C_LATENCY_MASK;
+ added_wake_time = 0;
+ } else {
+ max_latency = skl_watermark_max_latency(i915, 1);
+ if (max_latency == 0)
+ max_latency = LNL_PKG_C_LATENCY_MASK;
+ added_wake_time = DSB_EXE_TIME +
+ i915->display.sagv.block_time_us;
+ }
+
+ clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
+ val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
+ val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
+
+ intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_crtc_state __maybe_unused *new_crtc_state;
int ret, i;
+ bool vrr_enabled = false;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
ret = skl_build_pipe_wm(state, crtc);
ret = skl_wm_add_affected_planes(state, crtc);
if (ret)
return ret;
+
+ if (new_crtc_state->vrr.enable)
+ vrr_enabled = true;
}
+ skl_program_dpkgc_latency(to_i915(state->base.dev), vrr_enabled);
+
skl_print_wm_changes(state);
return 0;
&intel_sagv_status_fops);
}
-unsigned int skl_watermark_max_latency(struct drm_i915_private *i915)
+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, int initial_wm_level)
{
int level;
- for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
+ for (level = i915->display.wm.num_levels - 1; level >= initial_wm_level; level--) {
unsigned int latency = skl_wm_latency(i915, level, NULL);
if (latency)
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
void skl_watermark_debugfs_register(struct drm_i915_private *i915);
-unsigned int skl_watermark_max_latency(struct drm_i915_private *i915);
-
+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
+ int initial_wm_level);
void skl_wm_init(struct drm_i915_private *i915);
struct intel_dbuf_state {
#define MTL_LATENCY_SAGV _MMIO(0x4578c)
#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
+#define LNL_PKG_C_LATENCY _MMIO(0x46460)
+#define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16)
+#define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0)
+
#endif /* __SKL_WATERMARK_REGS_H__ */
{
GEM_WARN_ON(obj->userptr.page_ref);
+ if (!obj->userptr.notifier.mm)
+ return;
+
mmu_interval_notifier_remove(&obj->userptr.notifier);
obj->userptr.notifier.mm = NULL;
}
u32 ads_golden_ctxt_size;
/** @ads_capture_size: size of register lists in the ADS used for error capture */
u32 ads_capture_size;
- /** @ads_engine_usage_size: size of engine usage in the ADS */
- u32 ads_engine_usage_size;
/** @lrc_desc_pool_v69: object allocated to hold the GuC LRC descriptor pool */
struct i915_vma *lrc_desc_pool_v69;
u32 y_hot; /* in pixels */
};
-struct intel_vgpu_pipe_format {
- struct intel_vgpu_primary_plane_format primary;
- struct intel_vgpu_sprite_plane_format sprite;
- struct intel_vgpu_cursor_plane_format cursor;
- enum DDI_PORT ddi_port; /* the DDI port that pipe is connected to */
-};
-
-struct intel_vgpu_fb_format {
- struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
-};
-
int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
struct intel_vgpu_primary_plane_format *plane);
int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
struct intel_gvt_gtt {
const struct intel_gvt_gtt_pte_ops *pte_ops;
const struct intel_gvt_gtt_gma_ops *gma_ops;
- int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
- void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
struct list_head oos_page_use_list_head;
struct list_head oos_page_free_list_head;
struct mutex ppgtt_mm_lock;
struct intel_vgpu_gtt {
struct intel_vgpu_mm *ggtt_mm;
- unsigned long active_ppgtt_mm_bitmap;
struct list_head ppgtt_mm_list_head;
struct radix_tree_root spt_tree;
struct list_head oos_page_list_head;
/* Fences owned by a vGPU */
struct intel_vgpu_fence {
struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
- u32 base;
u32 size;
};
};
struct intel_vgpu_opregion {
- bool mapped;
void *va;
u32 gfn[INTEL_GVT_OPREGION_PAGES];
};
struct vfio_region *region;
int num_regions;
- struct eventfd_ctx *intx_trigger;
struct eventfd_ctx *msi_trigger;
/*
/* Special MMIO blocks. */
struct gvt_mmio_block {
- unsigned int device;
i915_reg_t offset;
unsigned int size;
gvt_mmio_func read;
#define vgpu_hidden_gmadr_end(vgpu) \
(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
-#define vgpu_fence_base(vgpu) (vgpu->fence.base)
#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
/* ring context size i.e. the first 0x50 dwords*/
char *name;
i915_reg_t reg_base;
enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
- unsigned long warned;
int group;
DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
bool has_upstream_irq;
/* per-event information */
struct intel_gvt_event_info {
int bit; /* map to register bit */
- int policy; /* forwarding policy */
struct intel_gvt_irq_info *info; /* register info */
gvt_event_virt_handler_t v_handler; /* for v_event */
};
struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
- DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
struct intel_gvt_irq_map *irq_map;
};
struct intel_gvt_mmio_info {
u32 offset;
u64 ro_mask;
- u32 device;
gvt_mmio_func read;
gvt_mmio_func write;
- u32 addr_range;
struct hlist_node node;
};
/* execlist context information */
struct execlist_ctx_descriptor_format ctx_desc;
- struct execlist_ring_context *ring_context;
unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
unsigned long guest_rb_head;
- bool restore_inhibit;
struct intel_vgpu_elsp_dwords elsp_dwords;
bool emulate_schedule_in;
atomic_t shadow_ctx_active;
struct i915_drm_client {
struct kref kref;
- unsigned int id;
-
spinlock_t ctx_lock; /* For add/remove from ctx_list. */
struct list_head ctx_list; /* List of contexts belonging to client. */
struct i915_vma *vma;
u8 *vaddr;
u32 last_ctx_id;
- int size_exponent;
/**
* @oa_buffer.ptr_lock: Locks reads and writes to all
struct execute_cb {
struct irq_work work;
struct i915_sw_fence *fence;
- struct i915_request *signal;
};
static struct kmem_cache *slab_requests;
struct list_head obj_link; /* Link in the object's VMA list */
struct rb_node obj_node;
- struct hlist_node obj_hash;
/** This vma's place in the eviction list */
struct list_head evict_link;
for_each_if((mr) = (i915)->mm.regions[id])
struct intel_memory_region_ops {
- unsigned int flags;
-
int (*init)(struct intel_memory_region *mem);
int (*release)(struct intel_memory_region *mem);
struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+enum drm_mode_status mtk_merge_mode_valid(struct device *dev,
+ const struct drm_display_mode *mode);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev);
const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
+enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
+ const struct drm_display_mode *mode);
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
clk_disable_unprepare(priv->clk);
}
+enum drm_mode_status mtk_merge_mode_valid(struct device *dev,
+ const struct drm_display_mode *mode)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned long rate;
+
+ rate = clk_get_rate(priv->clk);
+
+ /* Convert to KHz and round the number */
+ rate = (rate + 500) / 1000;
+
+ if (rate && mode->clock > rate) {
+ dev_dbg(dev, "invalid clock: %d (>%lu)\n", mode->clock, rate);
+ return MODE_CLOCK_HIGH;
+ }
+
+ /*
+ * Measure the bandwidth requirement of hardware prefetch (per frame)
+ *
+ * let N = prefetch buffer size in lines
+ * (ex. N=3, then prefetch buffer size = 3 lines)
+ *
+ * prefetch size = htotal * N (pixels)
+ * time per line = 1 / fps / vtotal (seconds)
+ * duration = vbp * time per line
+ * = vbp / fps / vtotal
+ *
+ * data rate = prefetch size / duration
+ * = htotal * N / (vbp / fps / vtotal)
+ * = htotal * vtotal * fps * N / vbp
+ * = clk * N / vbp (pixels per second)
+ *
+ * Say 4K60 (CEA-861) is the maximum mode supported by the SoC
+ * data rate = 594000K * N / 72 = 8250 (standard)
+ * (remove K * N due to the same unit)
+ *
+ * For 2560x1440@144 (clk=583600K, vbp=17):
+ * data rate = 583600 / 17 ~= 34329 > 8250 (NG)
+ *
+ * For 2560x1440@120 (clk=497760K, vbp=77):
+ * data rate = 497760 / 77 ~= 6464 < 8250 (OK)
+ *
+ * A non-standard 4K60 timing (clk=521280K, vbp=54)
+ * data rate = 521280 / 54 ~= 9653 > 8250 (NG)
+ *
+ * Bandwidth requirement of hardware prefetch increases significantly
+ * when the VBP decreases (more than 4x in this example).
+ *
+ * The proposed formula is only one way to estimate whether our SoC
+ * supports the mode setting. The basic idea behind it is just to check
+ * if the data rate requirement is too high (directly proportional to
+ * pixel clock, inversely proportional to vbp). Please adjust the
+ * function if it doesn't fit your situation in the future.
+ */
+ rate = mode->clock / (mode->vtotal - mode->vsync_end);
+
+ if (rate > 8250) {
+ dev_dbg(dev, "invalid rate: %lu (>8250): " DRM_MODE_FMT "\n",
+ rate, DRM_MODE_ARG(mode));
+ return MODE_BAD;
+ }
+
+ return MODE_OK;
+}
+
static int mtk_disp_merge_bind(struct device *dev, struct device *master,
void *data)
{
OVL_ADAPTOR_TYPE_ETHDR,
OVL_ADAPTOR_TYPE_MDP_RDMA,
OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_PADDING,
OVL_ADAPTOR_TYPE_NUM,
};
OVL_ADAPTOR_MERGE1,
OVL_ADAPTOR_MERGE2,
OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_PADDING0,
+ OVL_ADAPTOR_PADDING1,
+ OVL_ADAPTOR_PADDING2,
+ OVL_ADAPTOR_PADDING3,
+ OVL_ADAPTOR_PADDING4,
+ OVL_ADAPTOR_PADDING5,
+ OVL_ADAPTOR_PADDING6,
+ OVL_ADAPTOR_PADDING7,
OVL_ADAPTOR_ID_MAX
};
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
[OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_PADDING] = "padding",
};
static const struct mtk_ddp_comp_funcs ethdr = {
static const struct mtk_ddp_comp_funcs merge = {
.clk_enable = mtk_merge_clk_enable,
.clk_disable = mtk_merge_clk_disable,
+ .mode_valid = mtk_merge_mode_valid,
+};
+
+static const struct mtk_ddp_comp_funcs padding = {
+ .clk_enable = mtk_padding_clk_enable,
+ .clk_disable = mtk_padding_clk_disable,
+ .start = mtk_padding_start,
+ .stop = mtk_padding_stop,
};
static const struct mtk_ddp_comp_funcs rdma = {
[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &merge },
[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &merge },
[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &merge },
+ [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0, &padding },
+ [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1, &padding },
+ [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2, &padding },
+ [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3, &padding },
+ [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4, &padding },
+ [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5, &padding },
+ [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6, &padding },
+ [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7, &padding },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
}
}
+enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
+ const struct drm_display_mode *mode)
+
+{
+ int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev || !comp_matches[i].funcs->mode_valid)
+ continue;
+ return comp_matches[i].funcs->mode_valid(dev, mode);
+ }
+ return MODE_OK;
+}
+
unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
{
return MTK_OVL_ADAPTOR_LAYER_NUM;
}
static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ { .compatible = "mediatek,mt8188-disp-padding", .data = (void *)OVL_ADAPTOR_TYPE_PADDING },
{ .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
{ .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
{ .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
struct drm_crtc *crtc = &mtk_crtc->base;
unsigned long flags;
- spin_lock_irqsave(&crtc->dev->event_lock, flags);
- drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
- drm_crtc_vblank_put(crtc);
- mtk_crtc->event = NULL;
- spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+ if (mtk_crtc->event) {
+ spin_lock_irqsave(&crtc->dev->event_lock, flags);
+ drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
+ drm_crtc_vblank_put(crtc);
+ mtk_crtc->event = NULL;
+ spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+ }
}
static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
kfree(to_mtk_crtc_state(state));
}
+static enum drm_mode_status
+mtk_drm_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ enum drm_mode_status status = MODE_OK;
+ int i;
+
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
+ if (status != MODE_OK)
+ break;
+ }
+ return status;
+}
+
static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
.mode_fixup = mtk_drm_crtc_mode_fixup,
.mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
+ .mode_valid = mtk_drm_crtc_mode_valid,
.atomic_begin = mtk_drm_crtc_atomic_begin,
.atomic_flush = mtk_drm_crtc_atomic_flush,
.atomic_enable = mtk_drm_crtc_atomic_enable,
.remove = mtk_ovl_adaptor_remove_comp,
.get_formats = mtk_ovl_adaptor_get_formats,
.get_num_formats = mtk_ovl_adaptor_get_num_formats,
+ .mode_valid = mtk_ovl_adaptor_mode_valid,
};
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <drm/drm_modes.h>
+
struct device;
struct device_node;
struct drm_crtc;
void (*add)(struct device *dev, struct mtk_mutex *mutex);
void (*remove)(struct device *dev, struct mtk_mutex *mutex);
unsigned int (*encoder_index)(struct device *dev);
+ enum drm_mode_status (*mode_valid)(struct device *dev, const struct drm_display_mode *mode);
};
struct mtk_ddp_comp {
comp->funcs->clk_disable(comp->dev);
}
+static inline
+enum drm_mode_status mtk_ddp_comp_mode_valid(struct mtk_ddp_comp *comp,
+ const struct drm_display_mode *mode)
+{
+ if (comp && comp->funcs && comp->funcs->mode_valid)
+ return comp->funcs->mode_valid(comp->dev, mode);
+ return MODE_OK;
+}
+
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
unsigned int w, unsigned int h,
unsigned int vrefresh, unsigned int bpc,
.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
.conn_routes = mt8188_mtk_ddp_main_routes,
.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
- .mmsys_dev_num = 1,
+ .mmsys_dev_num = 2,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.data = &mt8186_mmsys_driver_data},
{ .compatible = "mediatek,mt8188-vdosys0",
.data = &mt8188_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8188-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-mmsys",
* Copyright (c) 2015 MediaTek Inc.
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/iopoll.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include <linux/units.h>
#include <video/mipi_display.h>
#include <video/videomode.h>
#define DSI_TXRX_CTRL 0x18
#define VC_NUM BIT(1)
-#define LANE_NUM (0xf << 2)
+#define LANE_NUM GENMASK(5, 2)
#define DIS_EOT BIT(6)
#define NULL_EN BIT(7)
#define TE_FREERUN BIT(8)
#define EXT_TE_EN BIT(9)
#define EXT_TE_EDGE BIT(10)
-#define MAX_RTN_SIZE (0xf << 12)
+#define MAX_RTN_SIZE GENMASK(15, 12)
#define HSTX_CKLP_EN BIT(16)
#define DSI_PSCTRL 0x1c
-#define DSI_PS_WC 0x3fff
-#define DSI_PS_SEL (3 << 16)
-#define PACKED_PS_16BIT_RGB565 (0 << 16)
-#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
-#define PACKED_PS_18BIT_RGB666 (2 << 16)
-#define PACKED_PS_24BIT_RGB888 (3 << 16)
+#define DSI_PS_WC GENMASK(13, 0)
+#define DSI_PS_SEL GENMASK(17, 16)
+#define PACKED_PS_16BIT_RGB565 0
+#define PACKED_PS_18BIT_RGB666 1
+#define LOOSELY_PS_24BIT_RGB666 2
+#define PACKED_PS_24BIT_RGB888 3
#define DSI_VSA_NL 0x20
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL 0x2C
+#define VACT_NL GENMASK(14, 0)
#define DSI_SIZE_CON 0x38
+#define DSI_HEIGHT GENMASK(30, 16)
+#define DSI_WIDTH GENMASK(14, 0)
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
#define LD0_WAKEUP_EN BIT(2)
#define DSI_PHY_TIMECON0 0x110
-#define LPX (0xff << 0)
-#define HS_PREP (0xff << 8)
-#define HS_ZERO (0xff << 16)
-#define HS_TRAIL (0xff << 24)
+#define LPX GENMASK(7, 0)
+#define HS_PREP GENMASK(15, 8)
+#define HS_ZERO GENMASK(23, 16)
+#define HS_TRAIL GENMASK(31, 24)
#define DSI_PHY_TIMECON1 0x114
-#define TA_GO (0xff << 0)
-#define TA_SURE (0xff << 8)
-#define TA_GET (0xff << 16)
-#define DA_HS_EXIT (0xff << 24)
+#define TA_GO GENMASK(7, 0)
+#define TA_SURE GENMASK(15, 8)
+#define TA_GET GENMASK(23, 16)
+#define DA_HS_EXIT GENMASK(31, 24)
#define DSI_PHY_TIMECON2 0x118
-#define CONT_DET (0xff << 0)
-#define CLK_ZERO (0xff << 16)
-#define CLK_TRAIL (0xff << 24)
+#define CONT_DET GENMASK(7, 0)
+#define DA_HS_SYNC GENMASK(15, 8)
+#define CLK_ZERO GENMASK(23, 16)
+#define CLK_TRAIL GENMASK(31, 24)
#define DSI_PHY_TIMECON3 0x11c
-#define CLK_HS_PREP (0xff << 0)
-#define CLK_HS_POST (0xff << 8)
-#define CLK_HS_EXIT (0xff << 16)
+#define CLK_HS_PREP GENMASK(7, 0)
+#define CLK_HS_POST GENMASK(15, 8)
+#define CLK_HS_EXIT GENMASK(23, 16)
#define DSI_VM_CMD_CON 0x130
#define VM_CMD_EN BIT(0)
#define FORCE_COMMIT BIT(0)
#define BYPASS_SHADOW BIT(1)
-#define CONFIG (0xff << 0)
+/* CMDQ related bits */
+#define CONFIG GENMASK(7, 0)
#define SHORT_PACKET 0
#define LONG_PACKET 2
#define BTA BIT(2)
-#define DATA_ID (0xff << 8)
-#define DATA_0 (0xff << 16)
-#define DATA_1 (0xff << 24)
+#define DATA_ID GENMASK(15, 8)
+#define DATA_0 GENMASK(23, 16)
+#define DATA_1 GENMASK(31, 24)
#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
- u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
+ u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
struct mtk_phy_timing *timing = &dsi->phy_timing;
timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
timing->clk_hs_zero = timing->clk_hs_trail * 4;
timing->clk_hs_exit = 2 * timing->clk_hs_trail;
- timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
- timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
- timcon1 = timing->ta_go | timing->ta_sure << 8 |
- timing->ta_get << 16 | timing->da_hs_exit << 24;
- timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
- timing->clk_hs_trail << 24;
- timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
- timing->clk_hs_exit << 16;
+ timcon0 = FIELD_PREP(LPX, timing->lpx) |
+ FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
+ FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
+ FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
+
+ timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
+ FIELD_PREP(TA_SURE, timing->ta_sure) |
+ FIELD_PREP(TA_GET, timing->ta_get) |
+ FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
+
+ timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
+ FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
+ FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
+
+ timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
+ FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
+ FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
}
-static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
-{
- struct videomode *vm = &dsi->vm;
- u32 dsi_buf_bpp, ps_wc;
- u32 ps_bpp_mode;
-
- if (dsi->format == MIPI_DSI_FMT_RGB565)
- dsi_buf_bpp = 2;
- else
- dsi_buf_bpp = 3;
-
- ps_wc = vm->hactive * dsi_buf_bpp;
- ps_bpp_mode = ps_wc;
-
- switch (dsi->format) {
- case MIPI_DSI_FMT_RGB888:
- ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
- break;
- case MIPI_DSI_FMT_RGB666:
- ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
- break;
- case MIPI_DSI_FMT_RGB666_PACKED:
- ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
- break;
- case MIPI_DSI_FMT_RGB565:
- ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
- break;
- }
-
- writel(vm->vactive, dsi->regs + DSI_VACT_NL);
- writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
- writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
-}
-
static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
{
- u32 tmp_reg;
+ u32 regval, tmp_reg = 0;
+ u8 i;
- switch (dsi->lanes) {
- case 1:
- tmp_reg = 1 << 2;
- break;
- case 2:
- tmp_reg = 3 << 2;
- break;
- case 3:
- tmp_reg = 7 << 2;
- break;
- case 4:
- tmp_reg = 0xf << 2;
- break;
- default:
- tmp_reg = 0xf << 2;
- break;
- }
+ /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
+ for (i = 0; i < dsi->lanes; i++)
+ tmp_reg |= BIT(i);
+
+ regval = FIELD_PREP(LANE_NUM, tmp_reg);
if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
- tmp_reg |= HSTX_CKLP_EN;
+ regval |= HSTX_CKLP_EN;
if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
- tmp_reg |= DIS_EOT;
+ regval |= DIS_EOT;
- writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
+ writel(regval, dsi->regs + DSI_TXRX_CTRL);
}
-static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
+static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
{
- u32 dsi_tmp_buf_bpp;
- u32 tmp_reg;
+ u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
+
+ if (dsi->format == MIPI_DSI_FMT_RGB565)
+ dsi_buf_bpp = 2;
+ else
+ dsi_buf_bpp = 3;
+
+ /* Word count */
+ ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
+ ps_val = ps_wc;
+ /* Pixel Stream type */
switch (dsi->format) {
+ default:
+ fallthrough;
case MIPI_DSI_FMT_RGB888:
- tmp_reg = PACKED_PS_24BIT_RGB888;
- dsi_tmp_buf_bpp = 3;
+ ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
break;
case MIPI_DSI_FMT_RGB666:
- tmp_reg = LOOSELY_PS_18BIT_RGB666;
- dsi_tmp_buf_bpp = 3;
+ ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
break;
case MIPI_DSI_FMT_RGB666_PACKED:
- tmp_reg = PACKED_PS_18BIT_RGB666;
- dsi_tmp_buf_bpp = 3;
+ ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
break;
case MIPI_DSI_FMT_RGB565:
- tmp_reg = PACKED_PS_16BIT_RGB565;
- dsi_tmp_buf_bpp = 2;
- break;
- default:
- tmp_reg = PACKED_PS_24BIT_RGB888;
- dsi_tmp_buf_bpp = 3;
+ ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
break;
}
- tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
- writel(tmp_reg, dsi->regs + DSI_PSCTRL);
+ if (config_vact) {
+ vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
+ writel(vact_nl, dsi->regs + DSI_VACT_NL);
+ writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
+ }
+ writel(ps_val, dsi->regs + DSI_PSCTRL);
}
static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
if (dsi->driver_data->has_size_ctl)
- writel(vm->vactive << 16 | vm->hactive,
+ writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
+ FIELD_PREP(DSI_WIDTH, vm->hactive),
dsi->regs + DSI_SIZE_CON);
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
- mtk_dsi_ps_control(dsi);
+ mtk_dsi_ps_control(dsi, false);
}
static void mtk_dsi_start(struct mtk_dsi *dsi)
if (++dsi->refcount != 1)
return 0;
- switch (dsi->format) {
- case MIPI_DSI_FMT_RGB565:
- bit_per_pixel = 16;
- break;
- case MIPI_DSI_FMT_RGB666_PACKED:
- bit_per_pixel = 18;
- break;
- case MIPI_DSI_FMT_RGB666:
- case MIPI_DSI_FMT_RGB888:
- default:
- bit_per_pixel = 24;
- break;
+ ret = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ if (ret < 0) {
+ dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
+ return ret;
}
+ bit_per_pixel = ret;
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
dsi->lanes);
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
- mtk_dsi_ps_control_vact(dsi);
+ mtk_dsi_ps_control(dsi, true);
mtk_dsi_set_vm_cmd(dsi);
mtk_dsi_config_vdo_timing(dsi);
mtk_dsi_set_interrupt_enable(dsi);
const struct drm_display_mode *mode)
{
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
- u32 bpp;
+ int bpp;
- if (dsi->format == MIPI_DSI_FMT_RGB565)
- bpp = 16;
- else
- bpp = 24;
+ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ if (bpp < 0)
+ return MODE_ERROR;
if (mode->clock * bpp / dsi->lanes > 1500000)
return MODE_CLOCK_HIGH;
if (!dsi)
return -ENOMEM;
- dsi->host.ops = &mtk_dsi_ops;
- dsi->host.dev = dev;
- ret = mipi_dsi_host_register(&dsi->host);
- if (ret < 0) {
- dev_err(dev, "failed to register DSI host: %d\n", ret);
- return ret;
- }
-
dsi->driver_data = of_device_get_match_data(dev);
dsi->engine_clk = devm_clk_get(dev, "engine");
- if (IS_ERR(dsi->engine_clk)) {
- ret = PTR_ERR(dsi->engine_clk);
+ if (IS_ERR(dsi->engine_clk))
+ return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),
+ "Failed to get engine clock\n");
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get engine clock: %d\n", ret);
- goto err_unregister_host;
- }
dsi->digital_clk = devm_clk_get(dev, "digital");
- if (IS_ERR(dsi->digital_clk)) {
- ret = PTR_ERR(dsi->digital_clk);
-
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get digital clock: %d\n", ret);
- goto err_unregister_host;
- }
+ if (IS_ERR(dsi->digital_clk))
+ return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),
+ "Failed to get digital clock\n");
dsi->hs_clk = devm_clk_get(dev, "hs");
- if (IS_ERR(dsi->hs_clk)) {
- ret = PTR_ERR(dsi->hs_clk);
- dev_err(dev, "Failed to get hs clock: %d\n", ret);
- goto err_unregister_host;
- }
+ if (IS_ERR(dsi->hs_clk))
+ return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dsi->regs = devm_ioremap_resource(dev, regs);
- if (IS_ERR(dsi->regs)) {
- ret = PTR_ERR(dsi->regs);
- dev_err(dev, "Failed to ioremap memory: %d\n", ret);
- goto err_unregister_host;
- }
+ if (IS_ERR(dsi->regs))
+ return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");
dsi->phy = devm_phy_get(dev, "dphy");
- if (IS_ERR(dsi->phy)) {
- ret = PTR_ERR(dsi->phy);
- dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
- goto err_unregister_host;
- }
+ if (IS_ERR(dsi->phy))
+ return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");
irq_num = platform_get_irq(pdev, 0);
- if (irq_num < 0) {
- ret = irq_num;
- goto err_unregister_host;
- }
+ if (irq_num < 0)
+ return irq_num;
+
+ dsi->host.ops = &mtk_dsi_ops;
+ dsi->host.dev = dev;
+ ret = mipi_dsi_host_register(&dsi->host);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to register DSI host\n");
ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
if (ret) {
- dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
- goto err_unregister_host;
+ mipi_dsi_host_unregister(&dsi->host);
+ return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");
}
init_waitqueue_head(&dsi->irq_wait_queue);
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
return 0;
-
-err_unregister_host:
- mipi_dsi_host_unregister(&dsi->host);
- return ret;
}
static void mtk_dsi_remove(struct platform_device *pdev)
};
static const struct of_device_id mtk_dsi_of_match[] = {
- { .compatible = "mediatek,mt2701-dsi",
- .data = &mt2701_dsi_driver_data },
- { .compatible = "mediatek,mt8173-dsi",
- .data = &mt8173_dsi_driver_data },
- { .compatible = "mediatek,mt8183-dsi",
- .data = &mt8183_dsi_driver_data },
- { .compatible = "mediatek,mt8186-dsi",
- .data = &mt8186_dsi_driver_data },
- { .compatible = "mediatek,mt8188-dsi",
- .data = &mt8188_dsi_driver_data },
- { },
+ { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
+ { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
+ { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
+ { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
+ { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
MGA G200 desktop chips and the server variants. It requires 0.3.0
of the modesetting userspace driver, and a version of mga driver
that will fail on KMS enabled devices.
+
+config DRM_MGAG200_IOBURST_WORKAROUND
+ bool "Disable buffer caching"
+ depends on DRM_MGAG200 && PREEMPT_RT && X86
+ help
+ Enable a workaround to avoid I/O bursts within the mgag200 driver at
+ the expense of overall display performance.
+ It restores the <v5.10 behavior, by mapping the framebuffer in system
+ RAM as Write-Combining, and flushing the cache after each write.
+ This is only useful on x86_64 if you want to run processes with
+ deterministic latency.
+ If unsure, say N.
return offset - 65536;
}
+#if defined(CONFIG_DRM_MGAG200_IOBURST_WORKAROUND)
+static struct drm_gem_object *mgag200_create_object(struct drm_device *dev, size_t size)
+{
+ struct drm_gem_shmem_object *shmem;
+
+ shmem = kzalloc(sizeof(*shmem), GFP_KERNEL);
+ if (!shmem)
+ return NULL;
+
+ shmem->map_wc = true;
+ return &shmem->base;
+}
+#endif
+
/*
* DRM driver
*/
.major = DRIVER_MAJOR,
.minor = DRIVER_MINOR,
.patchlevel = DRIVER_PATCHLEVEL,
+#if defined(CONFIG_DRM_MGAG200_IOBURST_WORKAROUND)
+ .gem_create_object = mgag200_create_object,
+#endif
DRM_GEM_SHMEM_DRIVER_OPS,
};
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_cache.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_format_helper.h>
iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
+
+ /* Flushing the cache greatly improves latency on x86_64 */
+#if defined(CONFIG_DRM_MGAG200_IOBURST_WORKAROUND)
+ if (!vmap->is_iomem)
+ drm_clflush_virt_range(vmap->vaddr + clip->y1 * fb->pitches[0],
+ drm_rect_height(clip) * fb->pitches[0]);
+#endif
}
/*
dp/dp_drm.o \
dp/dp_link.o \
dp/dp_panel.o \
- dp/dp_parser.o \
- dp/dp_power.o \
dp/dp_audio.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum a2xx_rb_dither_type {
DITHER_PIXEL = 0,
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
- return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
}
-static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
{
- return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
}
#define REG_A2XX_RB_DEPTH_INFO 0x00002002
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
- return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
}
#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
#define A2XX_RB_COPY_DEST_PITCH__SHIFT 0
static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
{
- return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
}
#define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b
#define A2XX_SQ_TEX_0_PITCH__SHIFT 22
static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
{
- return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
}
#define A2XX_SQ_TEX_0_TILED 0x80000000
#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12
static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
{
- return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
}
#define REG_A2XX_SQ_TEX_2 0x00000002
#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12
static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
{
- return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
}
+#ifdef __cplusplus
+#endif
#endif /* A2XX_XML */
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84323 bytes, from Wed Aug 23 10:39:39 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum a3xx_tile_mode {
LINEAR = 0,
#define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
#define A3XX_INT0_MISC_HANG_DETECT 0x01000000
#define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
+
#define REG_A3XX_RBBM_HW_VERSION 0x00000000
#define REG_A3XX_RBBM_HW_RELEASE 0x00000001
#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
-
#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
-
#define REG_A3XX_RBBM_INT_0_MASK 0x00000063
-
#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
-
#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
#define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
-static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
+#define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0))
static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
{
- return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
}
#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
}
-static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
+#define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0))
static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
{
- return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
}
static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
{
- return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
}
static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
{
- return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
+ assert(!(val & 0x3fff));
+ return (((val >> 14)) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
}
#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
{
- return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
}
#define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
{
- return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
}
#define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
- return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
}
#define REG_A3XX_RB_DEPTH_PITCH 0x00002103
#define A3XX_RB_DEPTH_PITCH__SHIFT 0
static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
{
- return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
+ assert(!(val & 0x7));
+ return (((val >> 3)) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
}
#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
{
- return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
}
#define REG_A3XX_RB_STENCIL_PITCH 0x00002107
#define A3XX_RB_STENCIL_PITCH__SHIFT 0
static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
{
- return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
+ assert(!(val & 0x7));
+ return (((val >> 3)) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
}
#define REG_A3XX_RB_STENCILREFMASK 0x00002108
return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
}
-static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
+#define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) (0x0000220b + 0x2*(i0))
static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
-static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) (0x00002215 + 0x1*(i0))
static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
-static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
+#define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0))
static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
-static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
+#define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0))
static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
}
-static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
+#define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0))
static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003
return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
}
-static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+#define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0))
static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
}
-static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+#define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
+#define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0))
static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
{
- return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x7f));
+ return (((val >> 7)) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
}
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
- return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}
#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
- return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}
#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
}
-static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
+#define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0))
static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
#define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
#define A3XX_SP_FS_MRT_REG_SINT 0x00000400
#define A3XX_SP_FS_MRT_REG_UINT 0x00000800
-static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
+#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0))
static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
- return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
-static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+#define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
#define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
-static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+#define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0))
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
{
- return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
}
#define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000
#define A3XX_TEX_CONST_3_DEPTH__SHIFT 17
#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
{
- return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
}
+#ifdef __cplusplus
+#endif
#endif /* A3XX_XML */
/* Set up AOOO: */
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
+ } else if (adreno_is_a305b(adreno_gpu)) {
+ gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
+ gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);
+ gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);
+ gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
} else if (adreno_is_a306(adreno_gpu)) {
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
/* Enable Clock gating: */
- if (adreno_is_a306(adreno_gpu))
+ if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
- } else if (adreno_is_a330(adreno_gpu)) {
+ } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
/* NOTE: this (value take from downstream android driver)
* includes some bits outside of the known bitfields. But
* A330 has this "MERCIU queue" thing too, which might
goto fail;
/* if needed, allocate gmem: */
- if (adreno_is_a330(adreno_gpu)) {
+ if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
adreno_gpu, &a3xx_gpu->ocmem);
if (ret)
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum a4xx_color_fmt {
RB4_A8_UNORM = 1,
{
return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
}
+
#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
#define A4XX_INT0_MISC_HANG_DETECT 0x01000000
#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
+
#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
}
#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
}
#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
#define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
-static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
+#define REG_A4XX_RB_MRT(i0) (0x000020a4 + 0x5*(i0))
static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
{
- return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
}
static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
{
- return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
}
#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
{
- return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
+ assert(!(val & 0x3fff));
+ return (((val >> 14)) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
}
#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
}
#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
}
#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
- return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
}
#define REG_A4XX_RB_DEPTH_PITCH 0x00002104
#define A4XX_RB_DEPTH_PITCH__SHIFT 0
static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
}
#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
#define A4XX_RB_DEPTH_PITCH2__SHIFT 0
static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
}
#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
{
- return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
}
#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
#define A4XX_RB_STENCIL_PITCH__SHIFT 0
static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
{
- return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
}
#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
}
-static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
+#define REG_A4XX_RB_VPORT_Z_CLAMP(i0) (0x00002120 + 0x2*(i0))
static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL_TP(i0) (0x00000004 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL2_TP(i0) (0x00000008 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_HYST_TP(i0) (0x0000000c + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_DELAY_TP(i0) (0x00000010 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL_SP(i0) (0x00000068 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL2_SP(i0) (0x0000006c + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_HYST_SP(i0) (0x00000070 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_DELAY_SP(i0) (0x00000074 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL_RB(i0) (0x00000078 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL2_RB(i0) (0x0000007c + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i0) (0x00000082 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i0) (0x00000086 + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
+#define REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i0) (0x0000008e + 0x1*(i0))
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
-static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
+#define REG_A4XX_CP_PROTECT(i0) (0x00000240 + 0x1*(i0))
static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
{
return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
-#define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
-#define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
-static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
-{
- return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
-}
-#define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
-#define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
-static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
-{
- return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK;
-}
+#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
+#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
-static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
+#define REG_A4XX_CP_SCRATCH(i0) (0x00000578 + 0x1*(i0))
static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
}
-static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+#define REG_A4XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
+#define REG_A4XX_SP_VS_VPC_DST(i0) (0x000022d8 + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
}
-static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
+#define REG_A4XX_SP_FS_MRT(i0) (0x000022f1 + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
}
-static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
+#define REG_A4XX_SP_DS_OUT(i0) (0x0000231b + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
+#define REG_A4XX_SP_DS_VPC_DST(i0) (0x0000232c + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
}
-static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
+#define REG_A4XX_SP_GS_OUT(i0) (0x00002342 + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
+#define REG_A4XX_SP_GS_VPC_DST(i0) (0x00002353 + 0x1*(i0))
static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
}
-static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
+#define REG_A4XX_VPC_VARYING_INTERP(i0) (0x00002142 + 0x1*(i0))
static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
-static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
+#define REG_A4XX_VPC_VARYING_PS_REPL(i0) (0x0000214a + 0x1*(i0))
static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
- return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
-static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
+#define REG_A4XX_VSC_PIPE_CONFIG(i0) (0x00000c08 + 0x1*(i0))
static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
}
-static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
+#define REG_A4XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c10 + 0x1*(i0))
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
-static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
+#define REG_A4XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c18 + 0x1*(i0))
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
-static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
+#define REG_A4XX_VFD_FETCH(i0) (0x0000220a + 0x4*(i0))
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
}
-static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
+#define REG_A4XX_VFD_DECODE(i0) (0x0000228a + 0x1*(i0))
static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
{
- return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
}
#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
{
- return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
}
#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
#define A4XX_TEX_CONST_4_BASE__SHIFT 5
static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
{
- return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
}
#define REG_A4XX_TEX_CONST_5 0x00000005
#define A4XX_SSBO_0_0_BASE__SHIFT 5
static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
{
- return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
}
#define REG_A4XX_SSBO_0_1 0x00000001
#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
}
#define REG_A4XX_SSBO_0_3 0x00000003
return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
}
+#ifdef __cplusplus
+#endif
#endif /* A4XX_XML */
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 151693 bytes, from Wed Aug 23 10:39:39 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum a5xx_color_fmt {
RB5_A8_UNORM = 2,
#define A5XX_INT0_GPMU_FIRMWARE 0x20000000
#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
+
#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
+
#define REG_A5XX_CP_RB_BASE 0x00000800
#define REG_A5XX_CP_RB_BASE_HI 0x00000801
#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
-static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
+#define REG_A5XX_CP_SCRATCH(i0) (0x00000b78 + 0x1*(i0))
static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
-static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
+#define REG_A5XX_CP_PROTECT(i0) (0x00000880 + 0x1*(i0))
static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
{
return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
-#define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
-#define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
-static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
-{
- return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
-}
-#define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
-#define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
-static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
-{
- return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
-}
+#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
+#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
#define REG_A5XX_RBBM_STATUS 0x000004f5
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31
-static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
-}
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30
-static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
-}
-#define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000
-#define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29
-static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000
-#define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28
-static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000
-#define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27
-static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000
-#define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26
-static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000
-#define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25
-static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000
-#define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24
-static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000
-#define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23
-static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000
-#define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22
-static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000
-#define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21
-static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000
-#define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20
-static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000
-#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19
-static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000
-#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18
-static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000
-#define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17
-static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000
-#define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16
-static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000
-#define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15
-static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
-}
-#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000
-#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14
-static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000
-#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13
-static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000
-#define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12
-static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800
-#define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11
-static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400
-#define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10
-static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200
-#define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9
-static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8
-static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080
-#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7
-static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040
-#define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6
-static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020
-#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5
-static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010
-#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4
-static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008
-#define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3
-static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004
-#define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2
-static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
-}
-#define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002
-#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
-static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
-{
- return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
-}
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
+#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
+#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
+#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
+#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
+#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
+#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
+#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
+#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
+#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
+#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
+#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
+#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
+#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
+#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
+#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
+#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
+#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
+#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
+#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
+#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
+#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
+#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
+#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
+#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
+#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
+#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
+#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
+#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
+#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
#define REG_A5XX_RBBM_STATUS3 0x00000530
#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
- return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
-static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
+#define REG_A5XX_VSC_PIPE_CONFIG(i0) (0x00000bd0 + 0x1*(i0))
static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
}
-static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
+#define REG_A5XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000be0 + 0x2*(i0))
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
-static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
+#define REG_A5XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c00 + 0x1*(i0))
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
-#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
-
-#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
-
-#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
-
-#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
-#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
-
-#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
-#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
-
-#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
-
-#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
-
-#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
-
-#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
-
-#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
-
-#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
-
-#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
-
-#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
-
-#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
-
#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
+#define REG_A5XX_GPMU_GPMU_SP_CLOCK_CONTROL 0x0000a880
+
+#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
+
+#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
+
+#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
+
+#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
+#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
+
+#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
+#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
+
+#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
+
+#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
+
+#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
+
+#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
+
#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
+#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
+
+#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
+
+#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
+
+#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
+
+#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
+
#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
}
#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
#define A5XX_RB_CNTL_WIDTH__SHIFT 0
static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
{
- return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
}
#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
#define A5XX_RB_CNTL_HEIGHT__SHIFT 9
static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
{
- return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
}
#define A5XX_RB_CNTL_BYPASS 0x00020000
return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
}
-static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
+#define REG_A5XX_RB_MRT(i0) (0x0000e150 + 0x7*(i0))
static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
#define A5XX_RB_MRT_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
}
static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
}
static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
}
#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
#define A5XX_RB_STENCIL_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
}
#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
}
#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
-static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
+#define REG_A5XX_RB_MRT_FLAG_BUFFER(i0) (0x0000e243 + 0x4*(i0))
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
}
static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
}
#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
}
#define A5XX_VPC_CNTL_0_VARYING 0x00000800
-static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
+#define REG_A5XX_VPC_VARYING_INTERP(i0) (0x0000e282 + 0x1*(i0))
static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
-static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
+#define REG_A5XX_VPC_VARYING_PS_REPL(i0) (0x0000e28a + 0x1*(i0))
static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
#define REG_A5XX_UNKNOWN_E293 0x0000e293
-static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
+#define REG_A5XX_VPC_VAR(i0) (0x0000e294 + 0x1*(i0))
static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
{
- return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
}
#define A5XX_VPC_SO_PROG_A_EN 0x00000800
#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
{
- return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
}
#define A5XX_VPC_SO_PROG_B_EN 0x00800000
-static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
+#define REG_A5XX_VPC_SO(i0) (0x0000e2a7 + 0x7*(i0))
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
-static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
+#define REG_A5XX_VFD_FETCH(i0) (0x0000e40a + 0x4*(i0))
static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
-static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
+#define REG_A5XX_VFD_DECODE(i0) (0x0000e48a + 0x2*(i0))
static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
-static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
+#define REG_A5XX_VFD_DEST_CNTL(i0) (0x0000e4ca + 0x1*(i0))
static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
}
-static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
+#define REG_A5XX_SP_VS_OUT(i0) (0x0000e593 + 0x1*(i0))
static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
+#define REG_A5XX_SP_VS_VPC_DST(i0) (0x0000e5a3 + 0x1*(i0))
static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
+#define REG_A5XX_SP_VS_PVT_MEM_PARAM 0x0000e5ae
+#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_VS_PVT_MEM_ADDR 0x0000e5af
+
+#define REG_A5XX_SP_VS_PVT_MEM_SIZE 0x0000e5b1
+#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
#define A5XX_SP_FS_CTRL_REG0_BUFFER 0x00000004
#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
+#define REG_A5XX_SP_FS_PVT_MEM_PARAM 0x0000e5c5
+#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_FS_PVT_MEM_ADDR 0x0000e5c6
+
+#define REG_A5XX_SP_FS_PVT_MEM_SIZE 0x0000e5c8
+#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
}
-static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
+#define REG_A5XX_SP_FS_OUTPUT(i0) (0x0000e5cb + 0x1*(i0))
static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
}
#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
-static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
+#define REG_A5XX_SP_FS_MRT(i0) (0x0000e5d3 + 0x1*(i0))
static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
+#define REG_A5XX_SP_CS_PVT_MEM_PARAM 0x0000e5f5
+#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_CS_PVT_MEM_ADDR 0x0000e5f6
+
+#define REG_A5XX_SP_CS_PVT_MEM_SIZE 0x0000e5f8
+#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
#define A5XX_SP_HS_CTRL_REG0_BUFFER 0x00000004
#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
+#define REG_A5XX_SP_HS_PVT_MEM_PARAM 0x0000e605
+#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_HS_PVT_MEM_ADDR 0x0000e606
+
+#define REG_A5XX_SP_HS_PVT_MEM_SIZE 0x0000e608
+#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
#define A5XX_SP_DS_CTRL_REG0_BUFFER 0x00000004
#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
+#define REG_A5XX_SP_DS_PVT_MEM_PARAM 0x0000e62e
+#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_DS_PVT_MEM_ADDR 0x0000e62f
+
+#define REG_A5XX_SP_DS_PVT_MEM_SIZE 0x0000e631
+#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
#define A5XX_SP_GS_CTRL_REG0_BUFFER 0x00000004
#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
+#define REG_A5XX_SP_GS_PVT_MEM_PARAM 0x0000e65e
+#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
+#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
+static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
+{
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+}
+#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
+#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
+static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
+{
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
+}
+#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
+#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
+static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
+{
+ return ((val) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
+}
+
+#define REG_A5XX_SP_GS_PVT_MEM_ADDR 0x0000e65f
+
+#define REG_A5XX_SP_GS_PVT_MEM_SIZE 0x0000e661
+#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
+#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
+static inline uint32_t A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+}
+
#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
}
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_2D_DST_INFO 0x00002110
#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
}
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
}
#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
{
- return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
}
#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
}
#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
{
- return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
}
#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
#define A5XX_TEX_CONST_3_FLAG 0x10000000
#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
{
- return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
}
#define REG_A5XX_TEX_CONST_5 0x00000005
#define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
{
- return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
}
#define REG_A5XX_SSBO_0_1 0x00000001
#define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
}
#define REG_A5XX_SSBO_0_3 0x00000003
return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
}
+#ifdef __cplusplus
+#endif
#endif /* A5XX_XML */
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 243381 bytes, from Sat Feb 24 09:06:40 2024)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum a6xx_tile_mode {
TILE6_LINEAR = 0,
A6XX_HLSQ_INST_RAM_1 = 115,
};
+enum a7xx_statetype_id {
+ A7XX_TP0_NCTX_REG = 0,
+ A7XX_TP0_CTX0_3D_CVS_REG = 1,
+ A7XX_TP0_CTX0_3D_CPS_REG = 2,
+ A7XX_TP0_CTX1_3D_CVS_REG = 3,
+ A7XX_TP0_CTX1_3D_CPS_REG = 4,
+ A7XX_TP0_CTX2_3D_CPS_REG = 5,
+ A7XX_TP0_CTX3_3D_CPS_REG = 6,
+ A7XX_TP0_TMO_DATA = 9,
+ A7XX_TP0_SMO_DATA = 10,
+ A7XX_TP0_MIPMAP_BASE_DATA = 11,
+ A7XX_SP_NCTX_REG = 32,
+ A7XX_SP_CTX0_3D_CVS_REG = 33,
+ A7XX_SP_CTX0_3D_CPS_REG = 34,
+ A7XX_SP_CTX1_3D_CVS_REG = 35,
+ A7XX_SP_CTX1_3D_CPS_REG = 36,
+ A7XX_SP_CTX2_3D_CPS_REG = 37,
+ A7XX_SP_CTX3_3D_CPS_REG = 38,
+ A7XX_SP_INST_DATA = 39,
+ A7XX_SP_INST_DATA_1 = 40,
+ A7XX_SP_LB_0_DATA = 41,
+ A7XX_SP_LB_1_DATA = 42,
+ A7XX_SP_LB_2_DATA = 43,
+ A7XX_SP_LB_3_DATA = 44,
+ A7XX_SP_LB_4_DATA = 45,
+ A7XX_SP_LB_5_DATA = 46,
+ A7XX_SP_LB_6_DATA = 47,
+ A7XX_SP_LB_7_DATA = 48,
+ A7XX_SP_CB_RAM = 49,
+ A7XX_SP_LB_13_DATA = 50,
+ A7XX_SP_LB_14_DATA = 51,
+ A7XX_SP_INST_TAG = 52,
+ A7XX_SP_INST_DATA_2 = 53,
+ A7XX_SP_TMO_TAG = 54,
+ A7XX_SP_SMO_TAG = 55,
+ A7XX_SP_STATE_DATA = 56,
+ A7XX_SP_HWAVE_RAM = 57,
+ A7XX_SP_L0_INST_BUF = 58,
+ A7XX_SP_LB_8_DATA = 59,
+ A7XX_SP_LB_9_DATA = 60,
+ A7XX_SP_LB_10_DATA = 61,
+ A7XX_SP_LB_11_DATA = 62,
+ A7XX_SP_LB_12_DATA = 63,
+ A7XX_HLSQ_DATAPATH_DSTR_META = 64,
+ A7XX_HLSQ_L2STC_TAG_RAM = 67,
+ A7XX_HLSQ_L2STC_INFO_CMD = 68,
+ A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69,
+ A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70,
+ A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71,
+ A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72,
+ A7XX_HLSQ_CHUNK_CVS_RAM = 73,
+ A7XX_HLSQ_CHUNK_CPS_RAM = 74,
+ A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
+ A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
+ A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
+ A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
+ A7XX_HLSQ_CVS_MISC_RAM = 79,
+ A7XX_HLSQ_CPS_MISC_RAM = 80,
+ A7XX_HLSQ_CPS_MISC_RAM_1 = 81,
+ A7XX_HLSQ_INST_RAM = 82,
+ A7XX_HLSQ_GFX_CVS_CONST_RAM = 83,
+ A7XX_HLSQ_GFX_CPS_CONST_RAM = 84,
+ A7XX_HLSQ_CVS_MISC_RAM_TAG = 85,
+ A7XX_HLSQ_CPS_MISC_RAM_TAG = 86,
+ A7XX_HLSQ_INST_RAM_TAG = 87,
+ A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
+ A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
+ A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90,
+ A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91,
+ A7XX_HLSQ_INST_RAM_1 = 92,
+ A7XX_HLSQ_STPROC_META = 93,
+ A7XX_HLSQ_BV_BE_META = 94,
+ A7XX_HLSQ_INST_RAM_2 = 95,
+ A7XX_HLSQ_DATAPATH_META = 96,
+ A7XX_HLSQ_FRONTEND_META = 97,
+ A7XX_HLSQ_INDIRECT_META = 98,
+ A7XX_HLSQ_BACKEND_META = 99,
+};
+
enum a6xx_debugbus_id {
A6XX_DBGBUS_CP = 1,
A6XX_DBGBUS_RBBM = 2,
A6XX_DBGBUS_SPTP_5 = 93,
};
+enum a7xx_state_location {
+ A7XX_HLSQ_STATE = 0,
+ A7XX_HLSQ_DP = 1,
+ A7XX_SP_TOP = 2,
+ A7XX_USPTP = 3,
+};
+
+enum a7xx_pipe {
+ A7XX_PIPE_NONE = 0,
+ A7XX_PIPE_BR = 1,
+ A7XX_PIPE_BV = 2,
+ A7XX_PIPE_LPAC = 3,
+};
+
+enum a7xx_cluster {
+ A7XX_CLUSTER_NONE = 0,
+ A7XX_CLUSTER_FE = 1,
+ A7XX_CLUSTER_SP_VS = 2,
+ A7XX_CLUSTER_PC_VS = 3,
+ A7XX_CLUSTER_GRAS = 4,
+ A7XX_CLUSTER_SP_PS = 5,
+ A7XX_CLUSTER_VPC_PS = 6,
+ A7XX_CLUSTER_PS = 7,
+};
+
+enum a7xx_debugbus_id {
+ A7XX_DBGBUS_CP_0_0 = 1,
+ A7XX_DBGBUS_CP_0_1 = 2,
+ A7XX_DBGBUS_RBBM = 3,
+ A7XX_DBGBUS_GBIF_GX = 5,
+ A7XX_DBGBUS_GBIF_CX = 6,
+ A7XX_DBGBUS_HLSQ = 7,
+ A7XX_DBGBUS_UCHE_0 = 9,
+ A7XX_DBGBUS_UCHE_1 = 10,
+ A7XX_DBGBUS_TESS_BR = 13,
+ A7XX_DBGBUS_TESS_BV = 14,
+ A7XX_DBGBUS_PC_BR = 17,
+ A7XX_DBGBUS_PC_BV = 18,
+ A7XX_DBGBUS_VFDP_BR = 21,
+ A7XX_DBGBUS_VFDP_BV = 22,
+ A7XX_DBGBUS_VPC_BR = 25,
+ A7XX_DBGBUS_VPC_BV = 26,
+ A7XX_DBGBUS_TSE_BR = 29,
+ A7XX_DBGBUS_TSE_BV = 30,
+ A7XX_DBGBUS_RAS_BR = 33,
+ A7XX_DBGBUS_RAS_BV = 34,
+ A7XX_DBGBUS_VSC = 37,
+ A7XX_DBGBUS_COM_0 = 39,
+ A7XX_DBGBUS_LRZ_BR = 43,
+ A7XX_DBGBUS_LRZ_BV = 44,
+ A7XX_DBGBUS_UFC_0 = 47,
+ A7XX_DBGBUS_UFC_1 = 48,
+ A7XX_DBGBUS_GMU_GX = 55,
+ A7XX_DBGBUS_DBGC = 59,
+ A7XX_DBGBUS_CX = 60,
+ A7XX_DBGBUS_GMU_CX = 61,
+ A7XX_DBGBUS_GPC_BR = 62,
+ A7XX_DBGBUS_GPC_BV = 63,
+ A7XX_DBGBUS_LARC = 66,
+ A7XX_DBGBUS_HLSQ_SPTP = 68,
+ A7XX_DBGBUS_RB_0 = 70,
+ A7XX_DBGBUS_RB_1 = 71,
+ A7XX_DBGBUS_RB_2 = 72,
+ A7XX_DBGBUS_RB_3 = 73,
+ A7XX_DBGBUS_RB_4 = 74,
+ A7XX_DBGBUS_RB_5 = 75,
+ A7XX_DBGBUS_UCHE_WRAPPER = 102,
+ A7XX_DBGBUS_CCU_0 = 106,
+ A7XX_DBGBUS_CCU_1 = 107,
+ A7XX_DBGBUS_CCU_2 = 108,
+ A7XX_DBGBUS_CCU_3 = 109,
+ A7XX_DBGBUS_CCU_4 = 110,
+ A7XX_DBGBUS_CCU_5 = 111,
+ A7XX_DBGBUS_VFD_BR_0 = 138,
+ A7XX_DBGBUS_VFD_BR_1 = 139,
+ A7XX_DBGBUS_VFD_BR_2 = 140,
+ A7XX_DBGBUS_VFD_BR_3 = 141,
+ A7XX_DBGBUS_VFD_BR_4 = 142,
+ A7XX_DBGBUS_VFD_BR_5 = 143,
+ A7XX_DBGBUS_VFD_BR_6 = 144,
+ A7XX_DBGBUS_VFD_BR_7 = 145,
+ A7XX_DBGBUS_VFD_BV_0 = 202,
+ A7XX_DBGBUS_VFD_BV_1 = 203,
+ A7XX_DBGBUS_VFD_BV_2 = 204,
+ A7XX_DBGBUS_VFD_BV_3 = 205,
+ A7XX_DBGBUS_USP_0 = 234,
+ A7XX_DBGBUS_USP_1 = 235,
+ A7XX_DBGBUS_USP_2 = 236,
+ A7XX_DBGBUS_USP_3 = 237,
+ A7XX_DBGBUS_USP_4 = 238,
+ A7XX_DBGBUS_USP_5 = 239,
+ A7XX_DBGBUS_TP_0 = 266,
+ A7XX_DBGBUS_TP_1 = 267,
+ A7XX_DBGBUS_TP_2 = 268,
+ A7XX_DBGBUS_TP_3 = 269,
+ A7XX_DBGBUS_TP_4 = 270,
+ A7XX_DBGBUS_TP_5 = 271,
+ A7XX_DBGBUS_TP_6 = 272,
+ A7XX_DBGBUS_TP_7 = 273,
+ A7XX_DBGBUS_TP_8 = 274,
+ A7XX_DBGBUS_TP_9 = 275,
+ A7XX_DBGBUS_TP_10 = 276,
+ A7XX_DBGBUS_TP_11 = 277,
+ A7XX_DBGBUS_USPTP_0 = 330,
+ A7XX_DBGBUS_USPTP_1 = 331,
+ A7XX_DBGBUS_USPTP_2 = 332,
+ A7XX_DBGBUS_USPTP_3 = 333,
+ A7XX_DBGBUS_USPTP_4 = 334,
+ A7XX_DBGBUS_USPTP_5 = 335,
+ A7XX_DBGBUS_USPTP_6 = 336,
+ A7XX_DBGBUS_USPTP_7 = 337,
+ A7XX_DBGBUS_USPTP_8 = 338,
+ A7XX_DBGBUS_USPTP_9 = 339,
+ A7XX_DBGBUS_USPTP_10 = 340,
+ A7XX_DBGBUS_USPTP_11 = 341,
+ A7XX_DBGBUS_CCHE_0 = 396,
+ A7XX_DBGBUS_CCHE_1 = 397,
+ A7XX_DBGBUS_CCHE_2 = 398,
+ A7XX_DBGBUS_VPC_DSTR_0 = 408,
+ A7XX_DBGBUS_VPC_DSTR_1 = 409,
+ A7XX_DBGBUS_VPC_DSTR_2 = 410,
+ A7XX_DBGBUS_HLSQ_DP_STR_0 = 411,
+ A7XX_DBGBUS_HLSQ_DP_STR_1 = 412,
+ A7XX_DBGBUS_HLSQ_DP_STR_2 = 413,
+ A7XX_DBGBUS_HLSQ_DP_STR_3 = 414,
+ A7XX_DBGBUS_HLSQ_DP_STR_4 = 415,
+ A7XX_DBGBUS_HLSQ_DP_STR_5 = 416,
+ A7XX_DBGBUS_UFC_DSTR_0 = 443,
+ A7XX_DBGBUS_UFC_DSTR_1 = 444,
+ A7XX_DBGBUS_UFC_DSTR_2 = 445,
+ A7XX_DBGBUS_CGC_SUBCORE = 446,
+ A7XX_DBGBUS_CGC_CORE = 447,
+};
+
enum a6xx_cp_perfcounter_select {
PERF_CP_ALWAYS_COUNT = 0,
PERF_CP_BUSY_GFX_CORE_IDLE = 1,
A6XX_INVALID_ZTEST = 3,
};
+enum a6xx_tess_spacing {
+ TESS_EQUAL = 0,
+ TESS_FRACTIONAL_ODD = 2,
+ TESS_FRACTIONAL_EVEN = 3,
+};
+
+enum a6xx_tess_output {
+ TESS_POINTS = 0,
+ TESS_LINES = 1,
+ TESS_CW_TRIS = 2,
+ TESS_CCW_TRIS = 3,
+};
+
enum a6xx_sequenced_thread_dist {
DIST_SCREEN_COORD = 0,
DIST_ALL_TO_RB0 = 1,
ROTATE_VFLIP = 5,
};
-enum a6xx_tess_spacing {
- TESS_EQUAL = 0,
- TESS_FRACTIONAL_ODD = 2,
- TESS_FRACTIONAL_EVEN = 3,
+enum a6xx_ccu_cache_size {
+ CCU_CACHE_SIZE_FULL = 0,
+ CCU_CACHE_SIZE_HALF = 1,
+ CCU_CACHE_SIZE_QUARTER = 2,
+ CCU_CACHE_SIZE_EIGHTH = 3,
};
-enum a6xx_tess_output {
- TESS_POINTS = 0,
- TESS_LINES = 1,
- TESS_CW_TRIS = 2,
- TESS_CCW_TRIS = 3,
+enum a6xx_varying_interp_mode {
+ INTERP_SMOOTH = 0,
+ INTERP_FLAT = 1,
+ INTERP_ZERO = 2,
+ INTERP_ONE = 3,
+};
+
+enum a6xx_varying_ps_repl_mode {
+ PS_REPL_NONE = 0,
+ PS_REPL_S = 1,
+ PS_REPL_T = 2,
+ PS_REPL_ONE_MINUS_T = 3,
};
enum a6xx_threadsize {
};
enum a6xx_isam_mode {
+ ISAMMODE_CL = 1,
ISAMMODE_GL = 2,
};
+enum a7xx_cs_yalign {
+ CS_YALIGN_1 = 8,
+ CS_YALIGN_2 = 4,
+ CS_YALIGN_4 = 2,
+ CS_YALIGN_8 = 1,
+};
+
enum a6xx_tex_filter {
A6XX_TEX_NEAREST = 0,
A6XX_TEX_LINEAR = 1,
#define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000
#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
+
#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
#define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000
#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000
#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000
+
#define REG_A6XX_CP_RB_BASE 0x00000800
#define REG_A6XX_CP_RB_CNTL 0x00000802
#define REG_A6XX_CP_HW_FAULT 0x00000821
#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
-
#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
#define REG_A6XX_CP_STATUS_1 0x00000825
#define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00
#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
}
#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
{
- return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
}
#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002
#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001
-static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
+#define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0))
static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
-static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
+#define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0))
static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
#define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab
-static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
+#define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0))
-static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; }
+#define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*(i0))
#define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900
#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
+#define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00
+#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000
+#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12
+static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK;
+}
+#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700
+#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8
+static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK;
+}
+#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030
+#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4
+static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK;
+}
+
#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
+#define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03
+#define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000
+#define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12
+static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK;
+}
+#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700
+#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8
+static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK;
+}
+#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030
+#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4
+static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val)
+{
+ return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK;
+}
+
#define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61
#define REG_A7XX_CP_BV_HW_FAULT 0x00000a64
#define REG_A6XX_RBBM_GPR0_CNTL 0x00000018
#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
-
#define REG_A6XX_RBBM_STATUS 0x00000210
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
#define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*(i0))
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
+#define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*(i0))
-static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; }
+#define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*(i0))
#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
-static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
+#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*(i0))
#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
-
#define REG_A6XX_RBBM_INT_0_MASK 0x00000038
-
#define REG_A7XX_RBBM_INT_2_MASK 0x0000003a
#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
+#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad
+
#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
+#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e
+
+#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f
+
#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
+#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122
+#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001
+
+#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123
+
+#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124
+
+#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125
+
+#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126
+
+#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127
+
+#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128
+
+#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129
+
+#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a
+
+#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b
+
#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f
#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
-static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
+#define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*(i0))
+
+#define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8
+#define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001
#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
}
-static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
+#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*(i0))
#define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
- return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
- return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
}
-static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
+#define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*(i0))
static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
-static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
+#define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*(i0))
static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
-static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
+#define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*(i0))
static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
-static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
+#define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*(i0))
static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
+#define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10
+
+#define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11
+
#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
#define REG_A6XX_GRAS_CL_CNTL 0x00008000
{
return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
}
+#define A6XX_GRAS_CNTL_UNK10 0x00000400
+#define A6XX_GRAS_CNTL_UNK11 0x00000800
#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
}
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
+#define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007
+
+#define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008
+
+#define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009
+
+#define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a
+
+#define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b
+
+#define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c
+
+#define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*(i0))
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
}
-static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
+#define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*(i0))
static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
}
#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
-#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
-#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
-static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
-}
+#define A6XX_GRAS_SU_CNTL_UNK12 0x00001000
#define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
#define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
{
return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
}
-#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
-#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
-#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
-#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
-static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
+#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000
+#define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000
+#define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000
+#define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000
+#define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20
+static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val)
{
- return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
+ return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK;
}
#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
{
return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
}
-#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
-#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
-static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
-}
+#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008
#define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099
#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
{
- return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
{
- return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18
{
return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
}
-#define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000
-#define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
-{
- return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK;
-}
+#define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000
#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
{
return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
}
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
-static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
-{
- return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
-}
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
-static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
-{
- return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
-}
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004
+#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008
#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}
+#define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7
+
#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
-static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
+#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*(i0))
static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
}
-static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
+#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*(i0))
static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
}
+#define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4
+
+#define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5
+
+#define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6
+
+#define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8
+
+#define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9
+
+#define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa
+
#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
}
#define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100
#define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200
+#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800
+#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11
+static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val)
+{
+ return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK;
+}
#define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101
#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001
}
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
-#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
-}
#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
{
- return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
}
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
-#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
-}
#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK;
}
+#define REG_A7XX_GRAS_UNKNOWN_810B 0x0000810b
+
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
+#define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111
+#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff
+#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0
+static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val)
+{
+ return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK;
+}
+
+#define REG_A7XX_GRAS_UNKNOWN_8113 0x00008113
+
+#define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120
+
+#define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121
+
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
}
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
+#define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00
+#define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8
+static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val)
+{
+ return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK;
+}
#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
+#define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00
+#define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8
+static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val)
+{
+ return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK;
+}
#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
+#define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00
+#define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8
+static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val)
+{
+ return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK;
+}
#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
+#define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00
+#define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8
+static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val)
+{
+ return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK;
+}
#define REG_A6XX_GRAS_2D_DST_TL 0x00008405
#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
#define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602
-static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
+#define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*(i0))
-static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
+#define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*(i0))
-static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
+#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*(i0))
#define REG_A6XX_RB_BIN_CONTROL 0x00008800
#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
{
- return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
{
- return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
}
#define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
#define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
}
+#define REG_A7XX_RB_BIN_CONTROL 0x00008800
+#define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
+#define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0
+static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val)
+{
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK;
+}
+#define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
+#define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8
+static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val)
+{
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK;
+}
+#define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
+#define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
+static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
+{
+ return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
+}
+#define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
+#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
+#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
+static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
+{
+ return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
+}
+
#define REG_A6XX_RB_RENDER_CNTL 0x00008801
#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038
#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3
return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
}
+#define REG_A7XX_RB_RENDER_CNTL 0x00008801
+#define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
+#define A7XX_RB_RENDER_CNTL_BINNING 0x00000080
+#define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
+#define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
+static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
+{
+ return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
+}
+#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
+#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
+static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
+{
+ return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
+}
+#define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
+#define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
+
+#define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116
+#define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080
+
#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
{
return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
}
-#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
-#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
-static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
-{
- return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
-}
-#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
-#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
-static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
-{
- return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
-}
+#define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004
+#define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008
#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
+#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
{
#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
+#define REG_A7XX_RB_UNKNOWN_8812 0x00008812
+
#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
-static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
+#define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*(i0))
static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
{
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
}
-#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400
-#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10
-static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
-{
- return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
-}
+#define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
}
+static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
+#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
+#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
+static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
+{
+ return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
+}
+#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
+#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
+static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
+{
+ return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
+}
+#define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400
+#define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800
+#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
+#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
+static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
+{
+ return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
+}
+
static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
-#define A6XX_RB_MRT_PITCH__MASK 0x0000ffff
+#define A6XX_RB_MRT_PITCH__MASK 0xffffffff
#define A6XX_RB_MRT_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
}
static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
-#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
+#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
}
static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
-#define A6XX_RB_MRT_BASE__MASK 0xffffffff
-#define A6XX_RB_MRT_BASE__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
-{
- return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
-}
static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
-#define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000
-#define A6XX_RB_MRT_BASE_GMEM__SHIFT 12
-static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
-{
- return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
-}
#define REG_A6XX_RB_BLEND_RED_F32 0x00008860
#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
#define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
+#define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114
+#define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
+
#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
}
+#define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872
+#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
+#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
+static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
+{
+ return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
+}
+#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
+#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
+static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
+{
+ return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
+}
+#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060
+#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5
+static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val)
+{
+ return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK;
+}
+#define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080
+
#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
}
#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
-#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
-}
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
-#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000
-#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
-{
- return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
-}
#define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
#define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
}
+#define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115
+#define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001
+
#define REG_A6XX_RB_STENCIL_INFO 0x00008881
#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
#define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
+#define REG_A7XX_RB_STENCIL_INFO 0x00008881
+#define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
+#define A7XX_RB_STENCIL_INFO_UNK1 0x00000002
+#define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c
+#define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2
+static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val)
+{
+ return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK;
+}
+
#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
}
#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
-#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
-}
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
-#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000
-#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12
-static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
-{
- return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
-}
#define REG_A6XX_RB_STENCILREF 0x00008887
#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
#define REG_A6XX_RB_LRZ_CNTL 0x00008898
#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
+#define REG_A7XX_RB_UNKNOWN_8899 0x00008899
+
#define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
#define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
#define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
{
- return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
{
- return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
}
#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
}
#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
-#define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000
-#define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12
-static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
-{
- return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
-}
#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
#define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
#define REG_A6XX_RB_BLIT_DST 0x000088d8
-#define A6XX_RB_BLIT_DST__MASK 0xffffffff
-#define A6XX_RB_BLIT_DST__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
-}
#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
}
#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
-#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
-#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
-}
#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
}
#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
+ assert(!(val & 0x7f));
+ return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK;
}
-#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
+#define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4
+#define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001
-#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
-#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
+#define REG_A7XX_RB_CCU_CNTL2 0x000088e5
+#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001
+#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0
+static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val)
+{
+ return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK;
+}
+#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004
+#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2
+static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val)
+{
+ return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK;
+}
+#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00
+#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10
+static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val)
+{
+ return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK;
+}
+#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000
+#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12
+static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val)
+{
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK;
+}
+#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000
+#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21
+static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val)
+{
+ return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK;
+}
+#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000
+#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23
+static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val)
{
- return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK;
}
+#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
+
+#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
+
#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
+ assert(!(val & 0x7f));
+ return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
+#define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5
+
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
-#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
-}
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
+ assert(!(val & 0x7f));
+ return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}
-static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
+#define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*(i0))
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
-#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
-#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
-{
- return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
-}
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
+ assert(!(val & 0x7f));
+ return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
-#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
-#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
-static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
-{
- return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
-}
#define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00
{
return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
}
+#define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000
#define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
#define REG_A6XX_RB_2D_DST 0x00008c18
-#define A6XX_RB_2D_DST__MASK 0xffffffff
-#define A6XX_RB_2D_DST__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
-}
#define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
#define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
#define A6XX_RB_2D_DST_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
}
#define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
-#define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff
-#define A6XX_RB_2D_DST_PLANE1__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
-}
#define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
#define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
}
#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
-#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
-#define A6XX_RB_2D_DST_PLANE2__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
-}
#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
-#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
-#define A6XX_RB_2D_DST_FLAGS__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
-}
#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
}
#define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
-#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff
-#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
-}
#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
}
#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
+#define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06
+
#define REG_A6XX_RB_CCU_CNTL 0x00008e07
+#define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001
#define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004
#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080
#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7
{
return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK;
}
+#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00
+#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10
+static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val)
+{
+ return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK;
+}
#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000
#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12
static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
{
- return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
+}
+#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000
+#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21
+static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val)
+{
+ return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK;
}
-#define A6XX_RB_CCU_CNTL_GMEM 0x00400000
#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000
#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23
static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
{
- return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
}
+#define REG_A7XX_RB_CCU_CNTL 0x00008e07
+#define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001
+#define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004
+
#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
#define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
}
-static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
+#define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09
+
+#define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*(i0))
-static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
+#define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*(i0))
#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
-static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
+#define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*(i0))
-static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; }
+#define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*(i0))
#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
-#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff
-#define A6XX_RB_UNKNOWN_8E51__SHIFT 0
-static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
-{
- return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
-}
+
+#define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79
#define REG_A6XX_VPC_GS_PARAM 0x00009100
#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff
return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
}
+#define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK;
+}
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
+}
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
+#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
+static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
+}
+
+#define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK;
+}
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
+}
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
+#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
+static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
+}
+
+#define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK;
+}
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
+}
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
+#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
+static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
+}
+
#define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
{
return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
}
+#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK;
+}
#define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
{
return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
}
+#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK;
+}
#define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
{
return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
}
+#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK;
+}
-#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
-#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
-#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
-
-#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
-#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
+#define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314
+#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
+#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK;
+}
+#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
+#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK;
+}
+#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
+}
+
+#define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315
+#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
+#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK;
+}
+#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
+#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK;
+}
+#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
+}
+
+#define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316
+#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
+#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK;
+}
+#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
+#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK;
+}
+#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
+#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
+}
+
+#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
+#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
+#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
+
+#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
+#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
{
return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
}
-static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
+#define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109
+#define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
+#define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
+#define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004
+#define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008
+
+#define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
+static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
+{
+ return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
+}
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
+static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
+{
+ return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
+}
+#define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
+#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
+static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
+{
+ return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
+}
+#define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000
+
+#define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b
+
+#define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c
+#define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001
+#define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
+#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
+#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
+static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
+{
+ return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK;
+}
+
+#define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*(i0))
static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
-static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
+#define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*(i0))
static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
-static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
+#define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*(i0))
static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
{
- return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
}
#define A6XX_VPC_SO_PROG_A_EN 0x00000800
#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
{
- return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
}
#define A6XX_VPC_SO_PROG_B_EN 0x00800000
#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
-#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
-#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
-}
-static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
+#define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*(i0))
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
-#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
-#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
-}
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
-#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
-#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
-static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
-{
- return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
-}
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; }
-#define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff
-#define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val)
-{
- return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK;
-}
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
-#define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc
-#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2
-static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
-{
- return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
-}
static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
-#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
-#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
-}
#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
#define REG_A6XX_VPC_SO_DISABLE 0x00009306
#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
+#define REG_A7XX_VPC_POLYGON_MODE2 0x00009307
+#define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003
+#define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0
+static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val)
+{
+ return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK;
+}
+
+#define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308
+#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff
+#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0
+static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val)
+{
+ return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK;
+}
+
+#define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309
+#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff
+#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0
+static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val)
+{
+ return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK;
+}
+
+#define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09
+#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff
+#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0
+static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val)
+{
+ return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK;
+}
+
#define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600
#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
-static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
+#define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*(i0))
-static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; }
+#define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*(i0))
#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
{
return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
}
-#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
-#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
-static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
-{
- return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
-}
+#define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000
#define REG_A6XX_PC_TESS_CNTL 0x00009802
#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
#define REG_A6XX_PC_POWER_CNTL 0x00009805
-#define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
+#define REG_A6XX_PC_PS_CNTL 0x00009806
+#define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001
#define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808
#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
}
+#define REG_A7XX_PC_POLYGON_MODE 0x00009809
+#define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
+#define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0
+static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
+{
+ return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK;
+}
+
#define REG_A6XX_PC_RASTER_CNTL 0x00009980
#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
}
#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
+#define REG_A7XX_PC_RASTER_CNTL 0x00009107
+#define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
+#define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0
+static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val)
+{
+ return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK;
+}
+#define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004
+
+#define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317
+#define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003
+#define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0
+static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val)
+{
+ return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK;
+}
+#define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004
+
#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
-#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
+#define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004
#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
{
return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
}
+#define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000
#define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
{
return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
}
+#define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000
#define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03
#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
{
return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
}
+#define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000
#define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
{
return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
}
+#define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000
#define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
{
return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
}
-#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000
-#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
-{
- return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
-}
+#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000
#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
-#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
-#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
-static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
-{
- return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
-}
+
+#define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810
#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
}
#define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
-#define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff
-#define A6XX_PC_BIN_PRIM_STRM__SHIFT 0
-static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
-{
- return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
-}
#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
-#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
-#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
-static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
-{
- return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
-}
#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
-static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
+#define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24
+
+#define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*(i0))
-static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; }
+#define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*(i0))
#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
}
#define REG_A6XX_VFD_CONTROL_6 0x0000a006
-#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
+#define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001
#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
#define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007
#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
-static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
+#define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*(i0))
static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
-#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
-#define A6XX_VFD_FETCH_BASE__SHIFT 0
-static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
-{
- return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
-}
static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
-static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
+#define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*(i0))
static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
-static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
+#define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*(i0))
static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
#define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8
+#define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600
+
#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
-static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
+#define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0))
-static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
+#define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0))
#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
-#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
-#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000
#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
+#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000
#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
}
-static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
+#define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
+#define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
-#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_VS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
-#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
+#define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d
+
#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
-#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
-#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_HS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
-#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
+#define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f
+
#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
-#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
}
-static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
+#define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
+#define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
-#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_DS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
-#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
+#define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868
+
#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
-#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000
#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
}
-static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
+#define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
#define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
}
-static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
+#define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
-#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_GS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
-#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
+#define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899
+
#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
-#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
-}
#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
-#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
-}
#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
-#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
-}
#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
-#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
-}
#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
-#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_VS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
-}
#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
-#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_HS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
-}
#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
-#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_DS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
-}
#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
-#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_GS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
-}
#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
-#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
-#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
-#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
-#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
-#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
-#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
-#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000
-#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000
-#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
+#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
+static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
+{
+ return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
+#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
+#define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000
+#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
+#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
+#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
+#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000
+#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000
+#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
-#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_FS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
-#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
}
-static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
+#define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
}
#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
-static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
+#define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
}
#define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008
-#define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010
+#define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010
#define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020
-#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0
-#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6
-static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val)
+#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0
+#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6
+static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val)
+{
+ return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK;
+}
+#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000
+#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16
+static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val)
{
- return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK;
+ return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK;
}
-static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
+#define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
}
-static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
+#define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0))
+
+static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
+#define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
+#define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK;
+}
+#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380
+#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
+}
+#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00
+#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
+}
+#define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000
+#define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK;
+}
+#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000
+#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
+}
+#define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000
+#define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000
+#define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000
+#define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26
+static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)
+{
+ return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK;
+}
+
+#define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*(i0))
static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
-#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
-#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
-#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000
-#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
}
+#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
+#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
+static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
+{
+ return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
+#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
+#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000
+#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
-#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
-#define A6XX_SP_CS_OBJ_START__SHIFT 0
-static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
-}
#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
{
- return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
+ assert(!(val & 0x1ff));
+ return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
}
#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
}
#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
-#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
-#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
-}
#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
{
- return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
}
#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+ assert(!(val & 0x7ff));
+ return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
+#define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be
+
+#define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5
+
#define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2
#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0
}
#define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
-#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
-#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
+#define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3
+#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
+#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
+static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
{
- return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
+ return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
}
-
-#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
-#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
-#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
-static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
+#define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100
+#define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8
+static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
{
- return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
+ return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK;
}
+#define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200
+#define A7XX_SP_CS_CNTL_1_UNK15 0x00008000
+
+#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
+
+#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
-#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_FS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
-}
#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
-#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
-#define A6XX_SP_CS_TEX_CONST__SHIFT 0
-static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
-}
-static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
+#define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0))
static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
{
return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
-#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
+#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
+static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
{
- return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
}
-#define REG_A6XX_SP_CS_IBO 0x0000a9f2
-#define A6XX_SP_CS_IBO__MASK 0xffffffff
-#define A6XX_SP_CS_IBO__SHIFT 0
-static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
+#define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0))
+
+static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
+#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
+#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
+static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
{
- return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
+ return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
+#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
+#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
+static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+}
+
+#define REG_A6XX_SP_CS_IBO 0x0000a9f2
#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
+#define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01
+
+#define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02
+#define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001
+
+#define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK;
+}
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000
+#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28
+static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK;
+}
+
+#define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2
+
#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
#define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006
}
#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
+#define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01
+
+#define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02
+
#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
-static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
+#define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*(i0))
static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
{
return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
-#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
+#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
+static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
{
- return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
}
-#define REG_A6XX_SP_IBO 0x0000ab1a
-#define A6XX_SP_IBO__MASK 0xffffffff
-#define A6XX_SP_IBO__SHIFT 0
-static inline uint32_t A6XX_SP_IBO(uint32_t val)
+#define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*(i0))
+
+static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab0a + 0x2*i0; }
+#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
+#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
+static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
{
- return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
+ return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
+#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
+#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
+static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+}
+
+#define REG_A6XX_SP_IBO 0x0000ab1a
#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
+#define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22
+
#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
}
-#define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00
-
-#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
+#define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf
+#define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001
+#define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002
+#define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004
+#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
+#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
+static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
+{
+ return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
+}
+#define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800
+#define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
+#define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
+static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
+{
+ return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK;
+}
+
+#define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00
+
+#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
+#define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06
+
+#define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08
+
+#define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09
+
+#define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a
+
#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
-static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
+#define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*(i0))
+
+#define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*(i0))
+
+#define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a
-static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; }
+#define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b
+
+#define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c
#define REG_A7XX_SP_READ_SEL 0x0000ae6d
+#define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000
+#define A7XX_SP_READ_SEL_LOCATION__SHIFT 18
+static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val)
+{
+ return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK;
+}
+#define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000
+#define A7XX_SP_READ_SEL_PIPE__SHIFT 16
+static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val)
+{
+ return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK;
+}
+#define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00
+#define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8
+static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val)
+{
+ return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK;
+}
+#define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0
+#define A7XX_SP_READ_SEL_USPTP__SHIFT 4
+static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val)
+{
+ return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK;
+}
+#define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f
+#define A7XX_SP_READ_SEL_SPTP__SHIFT 0
+static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val)
+{
+ return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK;
+}
+
+#define REG_A7XX_SP_DBG_CNTL 0x0000ae71
-static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; }
+#define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73
+
+#define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*(i0))
#define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
-#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
-#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
-}
#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
-#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
-#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
-static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
-{
- return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
-}
#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
- return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
+ return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
}
+#define REG_A7XX_SP_UNKNOWN_B310 0x0000b310
+
#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
}
#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
-#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
-#define A6XX_SP_PS_2D_SRC__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
-}
#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
}
-#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
-#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
-#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
+#define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0
+#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
+#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
+#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
+static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
+#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
+static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
+#define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
+#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
+#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
+static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
{
- return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
+ return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
}
+#define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
+#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
+#define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
+static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
+
+#define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1
+#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
+#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
+#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
+static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
+}
+
+#define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2
+
+#define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4
+#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
+#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
+}
+#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
+#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
+static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
+}
+
+#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
}
#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
-#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
-#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
+
+#define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5
+
+#define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7
+#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
+#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
{
- return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
}
+#define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8
+
#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
-#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
-#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
-}
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
+}
+
+#define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca
+
+#define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc
+#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
+#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
}
#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
}
+#define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd
+
+#define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce
+
+#define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf
+
+#define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0
+
+#define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1
+#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff
+#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0
+static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK;
+}
+#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000
+#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16
+static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val)
+{
+ return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK;
+}
+
+#define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2
+
+#define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21
+#define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
+#define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0
+static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val)
+{
+ return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK;
+}
+#define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
+#define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16
+static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val)
+{
+ return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK;
+}
+
#define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600
#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
-static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
+#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
+
+#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
+
+#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
+
+#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
+
+#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
+
+#define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*(i0))
#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
+#define REG_A7XX_HLSQ_VS_CNTL 0x0000a827
+#define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
+}
+#define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
-#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
-#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
-static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
+#define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f
+#define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
}
+#define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_DS_CNTL 0x0000a867
+#define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
+}
+#define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_GS_CNTL 0x0000a898
+#define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
+}
+#define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa
+#define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001
+
+#define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac
+
+#define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad
+
+#define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae
+#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff
+#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0
+static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK;
+}
+#define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100
+#define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200
+
+#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
+
+#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
-
-#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7
+#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007
+#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
+}
#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
}
-#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8
-#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
-#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
-}
-
#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
}
-#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
-}
-
#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
}
+#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
+#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
+#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
+}
+#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
+#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
+}
+
+#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
+}
+#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6
+#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
+#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
+static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
+{
+ return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
+}
+#define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
+#define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
+#define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
+static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK;
+}
+
+#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7
+#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007
+#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
+}
+
+#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8
+#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
+#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
+}
+#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
+#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
+static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
+}
+#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
+#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
+static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
+}
+#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
+#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
+static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
+}
+
+#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
+}
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
+static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
+}
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
+static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
+}
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
+#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
+static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
+}
+
#define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca
#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
}
-#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
-#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
-}
-
#define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb
#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
}
-#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
-#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
+#define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd
+#define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
}
-#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
-#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
+#define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4
+#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
+#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
+}
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
+}
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
+}
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
+#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
+}
-#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
-#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
-#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
-static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
+#define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5
+#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6
+#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
{
- return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
}
+#define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7
+#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8
+#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9
+#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da
+#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
+#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc
+
+#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd
+
+#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de
+
+#define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db
+#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
+#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
+static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
+}
+#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
+#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
+static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
+{
+ return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
+}
+#define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800
+#define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000
+#define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000
+#define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000
+#define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27
+static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val)
+{
+ return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK;
+}
+
+#define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2
+static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK;
+}
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12
+static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK;
+}
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000
+#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22
+static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK;
+}
+
+#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
+
+#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
+
#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
-static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
+#define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*(i0))
static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
{
return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
-#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
+#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
+static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
{
- return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
}
#define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0
return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
}
+#define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f
+#define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
+#define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
+#define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
+#define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
+#define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
+#define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
+#define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
+#define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
+#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00
+#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
+static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
+}
+#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000
+#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17
+static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
+{
+ return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
+}
+
#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
{
- return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
+#define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03
+#define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
+#define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
+static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
+{
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
+}
+#define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100
+#define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
+
+#define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*(i0))
#define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
#define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
-static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
+#define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*(i0))
static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
{
return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
}
-#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
+#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
+static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
{
- return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
}
#define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
-static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
+#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*(i0))
#define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
#define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000
+#define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2
+
+#define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4
+
+#define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6
+
#define REG_A6XX_CP_EVENT_START 0x0000d600
#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
}
#define REG_A6XX_TEX_CONST_3 0x00000003
-#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
+#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff
#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
}
#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
{
- return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
+ assert(!(val & 0xfff));
+ return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
}
#define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
#define A6XX_TEX_CONST_3_FLAG 0x10000000
#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
{
- return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
}
#define REG_A6XX_TEX_CONST_5 0x00000005
#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
{
- return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
+ assert(!(val & 0x1f));
+ return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
}
#define REG_A6XX_TEX_CONST_8 0x00000008
#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
{
- return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
+ assert(!(val & 0xf));
+ return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A6XX_TEX_CONST_10 0x0000000a
#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
{
- return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
+ assert(!(val & 0x3f));
+ return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
}
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039
+#ifdef __cplusplus
+template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {};
+template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {};
+template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = {
+ 0xc03,
+ 0xc04,
+ 0xc30,
+ 0xc31,
+ 0xc32,
+ 0xc33,
+ 0xc34,
+ 0xc35,
+ 0xc36,
+ 0xc37,
+ 0xe12,
+ 0xe17,
+ 0xe19,
+ 0x8099,
+ 0x80af,
+ 0x810a,
+ 0x8110,
+ 0x8600,
+ 0x880e,
+ 0x8811,
+ 0x8818,
+ 0x8819,
+ 0x881a,
+ 0x881b,
+ 0x881c,
+ 0x881d,
+ 0x881e,
+ 0x8864,
+ 0x8891,
+ 0x88f0,
+ 0x8927,
+ 0x8928,
+ 0x8e01,
+ 0x8e04,
+ 0x8e07,
+ 0x9210,
+ 0x9211,
+ 0x9218,
+ 0x9219,
+ 0x921a,
+ 0x921b,
+ 0x921c,
+ 0x921d,
+ 0x921e,
+ 0x921f,
+ 0x9220,
+ 0x9221,
+ 0x9222,
+ 0x9223,
+ 0x9224,
+ 0x9225,
+ 0x9226,
+ 0x9227,
+ 0x9228,
+ 0x9229,
+ 0x922a,
+ 0x922b,
+ 0x922c,
+ 0x922d,
+ 0x922e,
+ 0x922f,
+ 0x9230,
+ 0x9231,
+ 0x9232,
+ 0x9233,
+ 0x9234,
+ 0x9235,
+ 0x9236,
+ 0x9300,
+ 0x9600,
+ 0x9601,
+ 0x9602,
+ 0x9e08,
+ 0x9e09,
+ 0x9e72,
+ 0xa007,
+ 0xa009,
+ 0xa8a0,
+ 0xa8a1,
+ 0xa8a2,
+ 0xa8a3,
+ 0xa8a4,
+ 0xa8a5,
+ 0xa8a6,
+ 0xa8a7,
+ 0xa8a8,
+ 0xa8a9,
+ 0xa8aa,
+ 0xa8ab,
+ 0xa8ac,
+ 0xa8ad,
+ 0xa8ae,
+ 0xa8af,
+ 0xa9a8,
+ 0xa9b0,
+ 0xa9b1,
+ 0xa9b2,
+ 0xa9b3,
+ 0xa9b4,
+ 0xa9b5,
+ 0xa9b6,
+ 0xa9b7,
+ 0xa9b8,
+ 0xa9b9,
+ 0xa9ba,
+ 0xa9bb,
+ 0xa9bc,
+ 0xa9bd,
+ 0xa9c2,
+ 0xa9c3,
+ 0xa9e2,
+ 0xa9e3,
+ 0xa9e6,
+ 0xa9e7,
+ 0xa9e8,
+ 0xa9e9,
+ 0xa9ea,
+ 0xa9eb,
+ 0xa9ec,
+ 0xa9ed,
+ 0xa9ee,
+ 0xa9ef,
+ 0xa9f0,
+ 0xa9f1,
+ 0xaaf2,
+ 0xab1a,
+ 0xab1b,
+ 0xab20,
+ 0xae00,
+ 0xae03,
+ 0xae04,
+ 0xae0f,
+ 0xb180,
+ 0xb181,
+ 0xb182,
+ 0xb183,
+ 0xb302,
+ 0xb303,
+ 0xb309,
+ 0xb600,
+ 0xb602,
+ 0xb605,
+ 0xb987,
+ 0xb9d0,
+ 0xbb08,
+ 0xbb11,
+ 0xbb20,
+ 0xbb21,
+ 0xbb22,
+ 0xbb23,
+ 0xbb24,
+ 0xbb25,
+ 0xbb26,
+ 0xbb27,
+ 0xbb28,
+ 0xbb29,
+ 0xbe00,
+ 0xbe01,
+ 0xbe04,
+};
+template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = {
+ 0xc03,
+ 0xc04,
+ 0xc30,
+ 0xc31,
+ 0xc32,
+ 0xc33,
+ 0xc34,
+ 0xc35,
+ 0xc36,
+ 0xc37,
+ 0xce2,
+ 0xce3,
+ 0xce4,
+ 0xce5,
+ 0xce6,
+ 0xce7,
+ 0xe10,
+ 0xe11,
+ 0xe12,
+ 0xe17,
+ 0xe19,
+ 0x8008,
+ 0x8009,
+ 0x800a,
+ 0x800b,
+ 0x800c,
+ 0x8099,
+ 0x80a7,
+ 0x80af,
+ 0x80f4,
+ 0x80f5,
+ 0x80f5,
+ 0x80f6,
+ 0x80f6,
+ 0x80f7,
+ 0x80f8,
+ 0x80f9,
+ 0x80f9,
+ 0x80fa,
+ 0x80fa,
+ 0x80fb,
+ 0x810a,
+ 0x810b,
+ 0x8110,
+ 0x8120,
+ 0x8121,
+ 0x8600,
+ 0x880e,
+ 0x8811,
+ 0x8818,
+ 0x8819,
+ 0x881a,
+ 0x881b,
+ 0x881c,
+ 0x881d,
+ 0x881e,
+ 0x8864,
+ 0x8891,
+ 0x8899,
+ 0x88e5,
+ 0x88f0,
+ 0x8927,
+ 0x8928,
+ 0x8e01,
+ 0x8e04,
+ 0x8e06,
+ 0x8e07,
+ 0x8e09,
+ 0x8e79,
+ 0x9218,
+ 0x9219,
+ 0x921a,
+ 0x921b,
+ 0x921c,
+ 0x921d,
+ 0x921e,
+ 0x921f,
+ 0x9220,
+ 0x9221,
+ 0x9222,
+ 0x9223,
+ 0x9224,
+ 0x9225,
+ 0x9226,
+ 0x9227,
+ 0x9228,
+ 0x9229,
+ 0x922a,
+ 0x922b,
+ 0x922c,
+ 0x922d,
+ 0x922e,
+ 0x922f,
+ 0x9230,
+ 0x9231,
+ 0x9232,
+ 0x9233,
+ 0x9234,
+ 0x9235,
+ 0x9236,
+ 0x9300,
+ 0x9600,
+ 0x9601,
+ 0x9602,
+ 0x9810,
+ 0x9811,
+ 0x9e24,
+ 0x9e72,
+ 0xa007,
+ 0xa009,
+ 0xa600,
+ 0xa82d,
+ 0xa82f,
+ 0xa868,
+ 0xa899,
+ 0xa8a0,
+ 0xa8a1,
+ 0xa8a2,
+ 0xa8a3,
+ 0xa8a4,
+ 0xa8a5,
+ 0xa8a6,
+ 0xa8a7,
+ 0xa8a8,
+ 0xa8a9,
+ 0xa8aa,
+ 0xa8ab,
+ 0xa8ac,
+ 0xa8ad,
+ 0xa8ae,
+ 0xa8af,
+ 0xa9a8,
+ 0xa9ac,
+ 0xa9ad,
+ 0xa9b0,
+ 0xa9b1,
+ 0xa9b2,
+ 0xa9b3,
+ 0xa9b4,
+ 0xa9b5,
+ 0xa9b6,
+ 0xa9b7,
+ 0xa9b8,
+ 0xa9b9,
+ 0xa9ba,
+ 0xa9bb,
+ 0xa9bc,
+ 0xa9bd,
+ 0xa9be,
+ 0xa9c2,
+ 0xa9c3,
+ 0xa9c5,
+ 0xa9cd,
+ 0xa9df,
+ 0xa9e2,
+ 0xa9e3,
+ 0xa9e6,
+ 0xa9e7,
+ 0xa9e8,
+ 0xa9e9,
+ 0xa9ea,
+ 0xa9eb,
+ 0xa9ec,
+ 0xa9ed,
+ 0xa9ee,
+ 0xa9ef,
+ 0xa9f0,
+ 0xa9f1,
+ 0xa9f2,
+ 0xa9f3,
+ 0xa9f4,
+ 0xa9f5,
+ 0xa9f6,
+ 0xa9f7,
+ 0xaa01,
+ 0xaa02,
+ 0xaa03,
+ 0xaaf2,
+ 0xab01,
+ 0xab02,
+ 0xab1a,
+ 0xab1b,
+ 0xab1f,
+ 0xab20,
+ 0xab22,
+ 0xae00,
+ 0xae03,
+ 0xae04,
+ 0xae06,
+ 0xae08,
+ 0xae09,
+ 0xae0a,
+ 0xae0f,
+ 0xae6a,
+ 0xae6b,
+ 0xae6c,
+ 0xae73,
+ 0xb180,
+ 0xb181,
+ 0xb182,
+ 0xb183,
+ 0xb302,
+ 0xb303,
+ 0xb309,
+ 0xb310,
+ 0xb600,
+ 0xb602,
+ 0xb608,
+ 0xb609,
+ 0xb60a,
+ 0xb60b,
+ 0xb60c,
+};
+template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = {
+ 0xc02,
+ 0xc06,
+ 0xc10,
+ 0xc11,
+ 0xc12,
+ 0xc13,
+ 0xc14,
+ 0xc15,
+ 0xc16,
+ 0xc17,
+ 0xc18,
+ 0xc19,
+ 0xc1a,
+ 0xc1b,
+ 0xc1c,
+ 0xc1d,
+ 0xc1e,
+ 0xc1f,
+ 0xc20,
+ 0xc21,
+ 0xc22,
+ 0xc23,
+ 0xc24,
+ 0xc25,
+ 0xc26,
+ 0xc27,
+ 0xc28,
+ 0xc29,
+ 0xc2a,
+ 0xc2b,
+ 0xc2c,
+ 0xc2d,
+ 0xc2e,
+ 0xc2f,
+ 0xc38,
+ 0xc39,
+ 0xc3a,
+ 0xc3b,
+ 0xc3c,
+ 0xc3d,
+ 0xc3e,
+ 0xc3f,
+ 0xc40,
+ 0xc41,
+ 0xc42,
+ 0xc43,
+ 0xc44,
+ 0xc45,
+ 0xc46,
+ 0xc47,
+ 0xc48,
+ 0xc49,
+ 0xc4a,
+ 0xc4b,
+ 0xc4c,
+ 0xc4d,
+ 0xc4e,
+ 0xc4f,
+ 0xc50,
+ 0xc51,
+ 0xc52,
+ 0xc53,
+ 0xc54,
+ 0xc55,
+ 0xc56,
+ 0xc57,
+ 0xc58,
+ 0xc59,
+ 0xc5a,
+ 0xc5b,
+ 0xc5c,
+ 0xc5d,
+ 0xc5e,
+ 0xc5f,
+ 0xc60,
+ 0xc61,
+ 0xc62,
+ 0xc63,
+ 0xc64,
+ 0xc65,
+ 0xc66,
+ 0xc67,
+ 0xc68,
+ 0xc69,
+ 0xc6a,
+ 0xc6b,
+ 0xc6c,
+ 0xc6d,
+ 0xc6e,
+ 0xc6f,
+ 0xc70,
+ 0xc71,
+ 0xc72,
+ 0xc73,
+ 0xc74,
+ 0xc75,
+ 0xc76,
+ 0xc77,
+ 0xc78,
+ 0xc79,
+ 0xc7a,
+ 0xc7b,
+ 0xc7c,
+ 0xc7d,
+ 0xc7e,
+ 0xc7f,
+ 0xc80,
+ 0xc81,
+ 0xc82,
+ 0xc83,
+ 0xc84,
+ 0xc85,
+ 0xc86,
+ 0xc87,
+ 0xc88,
+ 0xc89,
+ 0xc8a,
+ 0xc8b,
+ 0xc8c,
+ 0xc8d,
+ 0xc8e,
+ 0xc8f,
+ 0xc90,
+ 0xc91,
+ 0xc92,
+ 0xc93,
+ 0xc94,
+ 0xc95,
+ 0xc96,
+ 0xc97,
+ 0x8000,
+ 0x8001,
+ 0x8002,
+ 0x8003,
+ 0x8004,
+ 0x8005,
+ 0x8006,
+ 0x8010,
+ 0x8011,
+ 0x8012,
+ 0x8013,
+ 0x8014,
+ 0x8015,
+ 0x8016,
+ 0x8017,
+ 0x8018,
+ 0x8019,
+ 0x801a,
+ 0x801b,
+ 0x801c,
+ 0x801d,
+ 0x801e,
+ 0x801f,
+ 0x8020,
+ 0x8021,
+ 0x8022,
+ 0x8023,
+ 0x8024,
+ 0x8025,
+ 0x8026,
+ 0x8027,
+ 0x8028,
+ 0x8029,
+ 0x802a,
+ 0x802b,
+ 0x802c,
+ 0x802d,
+ 0x802e,
+ 0x802f,
+ 0x8030,
+ 0x8031,
+ 0x8032,
+ 0x8033,
+ 0x8034,
+ 0x8035,
+ 0x8036,
+ 0x8037,
+ 0x8038,
+ 0x8039,
+ 0x803a,
+ 0x803b,
+ 0x803c,
+ 0x803d,
+ 0x803e,
+ 0x803f,
+ 0x8040,
+ 0x8041,
+ 0x8042,
+ 0x8043,
+ 0x8044,
+ 0x8045,
+ 0x8046,
+ 0x8047,
+ 0x8048,
+ 0x8049,
+ 0x804a,
+ 0x804b,
+ 0x804c,
+ 0x804d,
+ 0x804e,
+ 0x804f,
+ 0x8050,
+ 0x8051,
+ 0x8052,
+ 0x8053,
+ 0x8054,
+ 0x8055,
+ 0x8056,
+ 0x8057,
+ 0x8058,
+ 0x8059,
+ 0x805a,
+ 0x805b,
+ 0x805c,
+ 0x805d,
+ 0x805e,
+ 0x805f,
+ 0x8060,
+ 0x8061,
+ 0x8062,
+ 0x8063,
+ 0x8064,
+ 0x8065,
+ 0x8066,
+ 0x8067,
+ 0x8068,
+ 0x8069,
+ 0x806a,
+ 0x806b,
+ 0x806c,
+ 0x806d,
+ 0x806e,
+ 0x806f,
+ 0x8070,
+ 0x8071,
+ 0x8072,
+ 0x8073,
+ 0x8074,
+ 0x8075,
+ 0x8076,
+ 0x8077,
+ 0x8078,
+ 0x8079,
+ 0x807a,
+ 0x807b,
+ 0x807c,
+ 0x807d,
+ 0x807e,
+ 0x807f,
+ 0x8080,
+ 0x8081,
+ 0x8082,
+ 0x8083,
+ 0x8084,
+ 0x8085,
+ 0x8086,
+ 0x8087,
+ 0x8088,
+ 0x8089,
+ 0x808a,
+ 0x808b,
+ 0x808c,
+ 0x808d,
+ 0x808e,
+ 0x808f,
+ 0x8090,
+ 0x8091,
+ 0x8092,
+ 0x8094,
+ 0x8095,
+ 0x8096,
+ 0x8097,
+ 0x8098,
+ 0x809b,
+ 0x809c,
+ 0x809d,
+ 0x80a0,
+ 0x80a1,
+ 0x80a2,
+ 0x80a3,
+ 0x80a4,
+ 0x80a5,
+ 0x80a6,
+ 0x80b0,
+ 0x80b1,
+ 0x80b2,
+ 0x80b3,
+ 0x80b4,
+ 0x80b5,
+ 0x80b6,
+ 0x80b7,
+ 0x80b8,
+ 0x80b9,
+ 0x80ba,
+ 0x80bb,
+ 0x80bc,
+ 0x80bd,
+ 0x80be,
+ 0x80bf,
+ 0x80c0,
+ 0x80c1,
+ 0x80c2,
+ 0x80c3,
+ 0x80c4,
+ 0x80c5,
+ 0x80c6,
+ 0x80c7,
+ 0x80c8,
+ 0x80c9,
+ 0x80ca,
+ 0x80cb,
+ 0x80cc,
+ 0x80cd,
+ 0x80ce,
+ 0x80cf,
+ 0x80d0,
+ 0x80d1,
+ 0x80d2,
+ 0x80d3,
+ 0x80d4,
+ 0x80d5,
+ 0x80d6,
+ 0x80d7,
+ 0x80d8,
+ 0x80d9,
+ 0x80da,
+ 0x80db,
+ 0x80dc,
+ 0x80dd,
+ 0x80de,
+ 0x80df,
+ 0x80e0,
+ 0x80e1,
+ 0x80e2,
+ 0x80e3,
+ 0x80e4,
+ 0x80e5,
+ 0x80e6,
+ 0x80e7,
+ 0x80e8,
+ 0x80e9,
+ 0x80ea,
+ 0x80eb,
+ 0x80ec,
+ 0x80ed,
+ 0x80ee,
+ 0x80ef,
+ 0x80f0,
+ 0x80f1,
+ 0x8100,
+ 0x8101,
+ 0x8102,
+ 0x8103,
+ 0x8104,
+ 0x8105,
+ 0x8106,
+ 0x8107,
+ 0x8109,
+ 0x8114,
+ 0x8115,
+ 0x8400,
+ 0x8401,
+ 0x8402,
+ 0x8403,
+ 0x8404,
+ 0x8405,
+ 0x8406,
+ 0x840a,
+ 0x840b,
+ 0x8800,
+ 0x8801,
+ 0x8802,
+ 0x8803,
+ 0x8804,
+ 0x8805,
+ 0x8806,
+ 0x8809,
+ 0x880a,
+ 0x880b,
+ 0x880c,
+ 0x880d,
+ 0x880f,
+ 0x8810,
+ 0x8820,
+ 0x8821,
+ 0x8822,
+ 0x8823,
+ 0x8824,
+ 0x8825,
+ 0x8826,
+ 0x8827,
+ 0x8828,
+ 0x8829,
+ 0x882a,
+ 0x882b,
+ 0x882c,
+ 0x882d,
+ 0x882e,
+ 0x882f,
+ 0x8830,
+ 0x8831,
+ 0x8832,
+ 0x8833,
+ 0x8834,
+ 0x8835,
+ 0x8836,
+ 0x8837,
+ 0x8838,
+ 0x8839,
+ 0x883a,
+ 0x883b,
+ 0x883c,
+ 0x883d,
+ 0x883e,
+ 0x883f,
+ 0x8840,
+ 0x8841,
+ 0x8842,
+ 0x8843,
+ 0x8844,
+ 0x8845,
+ 0x8846,
+ 0x8847,
+ 0x8848,
+ 0x8849,
+ 0x884a,
+ 0x884b,
+ 0x884c,
+ 0x884d,
+ 0x884e,
+ 0x884f,
+ 0x8850,
+ 0x8851,
+ 0x8852,
+ 0x8853,
+ 0x8854,
+ 0x8855,
+ 0x8856,
+ 0x8857,
+ 0x8858,
+ 0x8859,
+ 0x885a,
+ 0x885b,
+ 0x885c,
+ 0x885d,
+ 0x885e,
+ 0x885f,
+ 0x8860,
+ 0x8861,
+ 0x8862,
+ 0x8863,
+ 0x8865,
+ 0x8870,
+ 0x8871,
+ 0x8872,
+ 0x8873,
+ 0x8874,
+ 0x8875,
+ 0x8876,
+ 0x8877,
+ 0x8878,
+ 0x8879,
+ 0x8880,
+ 0x8881,
+ 0x8882,
+ 0x8883,
+ 0x8884,
+ 0x8885,
+ 0x8886,
+ 0x8887,
+ 0x8888,
+ 0x8889,
+ 0x8890,
+ 0x8898,
+ 0x88c0,
+ 0x88c1,
+ 0x88d0,
+ 0x88d1,
+ 0x88d2,
+ 0x88d3,
+ 0x88d4,
+ 0x88d5,
+ 0x88d6,
+ 0x88d7,
+ 0x88d8,
+ 0x88d9,
+ 0x88da,
+ 0x88db,
+ 0x88dc,
+ 0x88dd,
+ 0x88de,
+ 0x88df,
+ 0x88e0,
+ 0x88e1,
+ 0x88e2,
+ 0x88e3,
+ 0x8900,
+ 0x8901,
+ 0x8902,
+ 0x8903,
+ 0x8904,
+ 0x8905,
+ 0x8906,
+ 0x8907,
+ 0x8908,
+ 0x8909,
+ 0x890a,
+ 0x890b,
+ 0x890c,
+ 0x890d,
+ 0x890e,
+ 0x890f,
+ 0x8910,
+ 0x8911,
+ 0x8912,
+ 0x8913,
+ 0x8914,
+ 0x8915,
+ 0x8916,
+ 0x8917,
+ 0x8918,
+ 0x8919,
+ 0x891a,
+ 0x8a00,
+ 0x8a10,
+ 0x8a20,
+ 0x8a30,
+ 0x8c00,
+ 0x8c01,
+ 0x8c17,
+ 0x8c18,
+ 0x8c19,
+ 0x8c1a,
+ 0x8c1b,
+ 0x8c1c,
+ 0x8c1d,
+ 0x8c1e,
+ 0x8c1f,
+ 0x8c20,
+ 0x8c21,
+ 0x8c22,
+ 0x8c23,
+ 0x8c24,
+ 0x8c25,
+ 0x8c2c,
+ 0x8c2d,
+ 0x8c2e,
+ 0x8c2f,
+ 0x9100,
+ 0x9101,
+ 0x9102,
+ 0x9103,
+ 0x9104,
+ 0x9105,
+ 0x9106,
+ 0x9107,
+ 0x9108,
+ 0x9200,
+ 0x9201,
+ 0x9202,
+ 0x9203,
+ 0x9204,
+ 0x9205,
+ 0x9206,
+ 0x9207,
+ 0x9208,
+ 0x9209,
+ 0x920a,
+ 0x920b,
+ 0x920c,
+ 0x920d,
+ 0x920e,
+ 0x920f,
+ 0x9212,
+ 0x9213,
+ 0x9214,
+ 0x9215,
+ 0x9216,
+ 0x9217,
+ 0x9301,
+ 0x9302,
+ 0x9303,
+ 0x9304,
+ 0x9305,
+ 0x9306,
+ 0x9311,
+ 0x9312,
+ 0x9313,
+ 0x9314,
+ 0x9315,
+ 0x9316,
+ 0x9800,
+ 0x9801,
+ 0x9802,
+ 0x9803,
+ 0x9804,
+ 0x9805,
+ 0x9806,
+ 0x9808,
+ 0x9980,
+ 0x9981,
+ 0x9b00,
+ 0x9b01,
+ 0x9b02,
+ 0x9b03,
+ 0x9b04,
+ 0x9b05,
+ 0x9b06,
+ 0x9b07,
+ 0x9b08,
+ 0xa000,
+ 0xa001,
+ 0xa002,
+ 0xa003,
+ 0xa004,
+ 0xa005,
+ 0xa006,
+ 0xa008,
+ 0xa00e,
+ 0xa00f,
+ 0xa010,
+ 0xa011,
+ 0xa012,
+ 0xa013,
+ 0xa014,
+ 0xa015,
+ 0xa016,
+ 0xa017,
+ 0xa018,
+ 0xa019,
+ 0xa01a,
+ 0xa01b,
+ 0xa01c,
+ 0xa01d,
+ 0xa01e,
+ 0xa01f,
+ 0xa020,
+ 0xa021,
+ 0xa022,
+ 0xa023,
+ 0xa024,
+ 0xa025,
+ 0xa026,
+ 0xa027,
+ 0xa028,
+ 0xa029,
+ 0xa02a,
+ 0xa02b,
+ 0xa02c,
+ 0xa02d,
+ 0xa02e,
+ 0xa02f,
+ 0xa030,
+ 0xa031,
+ 0xa032,
+ 0xa033,
+ 0xa034,
+ 0xa035,
+ 0xa036,
+ 0xa037,
+ 0xa038,
+ 0xa039,
+ 0xa03a,
+ 0xa03b,
+ 0xa03c,
+ 0xa03d,
+ 0xa03e,
+ 0xa03f,
+ 0xa040,
+ 0xa041,
+ 0xa042,
+ 0xa043,
+ 0xa044,
+ 0xa045,
+ 0xa046,
+ 0xa047,
+ 0xa048,
+ 0xa049,
+ 0xa04a,
+ 0xa04b,
+ 0xa04c,
+ 0xa04d,
+ 0xa04e,
+ 0xa04f,
+ 0xa050,
+ 0xa051,
+ 0xa052,
+ 0xa053,
+ 0xa054,
+ 0xa055,
+ 0xa056,
+ 0xa057,
+ 0xa058,
+ 0xa059,
+ 0xa05a,
+ 0xa05b,
+ 0xa05c,
+ 0xa05d,
+ 0xa05e,
+ 0xa05f,
+ 0xa060,
+ 0xa061,
+ 0xa062,
+ 0xa063,
+ 0xa064,
+ 0xa065,
+ 0xa066,
+ 0xa067,
+ 0xa068,
+ 0xa069,
+ 0xa06a,
+ 0xa06b,
+ 0xa06c,
+ 0xa06d,
+ 0xa06e,
+ 0xa06f,
+ 0xa070,
+ 0xa071,
+ 0xa072,
+ 0xa073,
+ 0xa074,
+ 0xa075,
+ 0xa076,
+ 0xa077,
+ 0xa078,
+ 0xa079,
+ 0xa07a,
+ 0xa07b,
+ 0xa07c,
+ 0xa07d,
+ 0xa07e,
+ 0xa07f,
+ 0xa080,
+ 0xa081,
+ 0xa082,
+ 0xa083,
+ 0xa084,
+ 0xa085,
+ 0xa086,
+ 0xa087,
+ 0xa088,
+ 0xa089,
+ 0xa08a,
+ 0xa08b,
+ 0xa08c,
+ 0xa08d,
+ 0xa08e,
+ 0xa08f,
+ 0xa090,
+ 0xa091,
+ 0xa092,
+ 0xa093,
+ 0xa094,
+ 0xa095,
+ 0xa096,
+ 0xa097,
+ 0xa098,
+ 0xa099,
+ 0xa09a,
+ 0xa09b,
+ 0xa09c,
+ 0xa09d,
+ 0xa09e,
+ 0xa09f,
+ 0xa0a0,
+ 0xa0a1,
+ 0xa0a2,
+ 0xa0a3,
+ 0xa0a4,
+ 0xa0a5,
+ 0xa0a6,
+ 0xa0a7,
+ 0xa0a8,
+ 0xa0a9,
+ 0xa0aa,
+ 0xa0ab,
+ 0xa0ac,
+ 0xa0ad,
+ 0xa0ae,
+ 0xa0af,
+ 0xa0b0,
+ 0xa0b1,
+ 0xa0b2,
+ 0xa0b3,
+ 0xa0b4,
+ 0xa0b5,
+ 0xa0b6,
+ 0xa0b7,
+ 0xa0b8,
+ 0xa0b9,
+ 0xa0ba,
+ 0xa0bb,
+ 0xa0bc,
+ 0xa0bd,
+ 0xa0be,
+ 0xa0bf,
+ 0xa0c0,
+ 0xa0c1,
+ 0xa0c2,
+ 0xa0c3,
+ 0xa0c4,
+ 0xa0c5,
+ 0xa0c6,
+ 0xa0c7,
+ 0xa0c8,
+ 0xa0c9,
+ 0xa0ca,
+ 0xa0cb,
+ 0xa0cc,
+ 0xa0cd,
+ 0xa0ce,
+ 0xa0cf,
+ 0xa0d0,
+ 0xa0d1,
+ 0xa0d2,
+ 0xa0d3,
+ 0xa0d4,
+ 0xa0d5,
+ 0xa0d6,
+ 0xa0d7,
+ 0xa0d8,
+ 0xa0d9,
+ 0xa0da,
+ 0xa0db,
+ 0xa0dc,
+ 0xa0dd,
+ 0xa0de,
+ 0xa0df,
+ 0xa0e0,
+ 0xa0e1,
+ 0xa0e2,
+ 0xa0e3,
+ 0xa0e4,
+ 0xa0e5,
+ 0xa0e6,
+ 0xa0e7,
+ 0xa0e8,
+ 0xa0e9,
+ 0xa0ea,
+ 0xa0eb,
+ 0xa0ec,
+ 0xa0ed,
+ 0xa0ee,
+ 0xa0ef,
+ 0xa0f8,
+ 0xa800,
+ 0xa802,
+ 0xa803,
+ 0xa804,
+ 0xa805,
+ 0xa806,
+ 0xa807,
+ 0xa808,
+ 0xa809,
+ 0xa80a,
+ 0xa80b,
+ 0xa80c,
+ 0xa80d,
+ 0xa80e,
+ 0xa80f,
+ 0xa810,
+ 0xa811,
+ 0xa812,
+ 0xa813,
+ 0xa814,
+ 0xa815,
+ 0xa816,
+ 0xa817,
+ 0xa818,
+ 0xa819,
+ 0xa81a,
+ 0xa81b,
+ 0xa81c,
+ 0xa81d,
+ 0xa81e,
+ 0xa81f,
+ 0xa820,
+ 0xa821,
+ 0xa822,
+ 0xa823,
+ 0xa824,
+ 0xa825,
+ 0xa830,
+ 0xa831,
+ 0xa832,
+ 0xa833,
+ 0xa834,
+ 0xa835,
+ 0xa836,
+ 0xa837,
+ 0xa838,
+ 0xa839,
+ 0xa83a,
+ 0xa83b,
+ 0xa83c,
+ 0xa83d,
+ 0xa840,
+ 0xa842,
+ 0xa843,
+ 0xa844,
+ 0xa845,
+ 0xa846,
+ 0xa847,
+ 0xa848,
+ 0xa849,
+ 0xa84a,
+ 0xa84b,
+ 0xa84c,
+ 0xa84d,
+ 0xa84e,
+ 0xa84f,
+ 0xa850,
+ 0xa851,
+ 0xa852,
+ 0xa853,
+ 0xa854,
+ 0xa855,
+ 0xa856,
+ 0xa857,
+ 0xa858,
+ 0xa859,
+ 0xa85a,
+ 0xa85b,
+ 0xa85c,
+ 0xa85d,
+ 0xa85e,
+ 0xa85f,
+ 0xa860,
+ 0xa861,
+ 0xa862,
+ 0xa863,
+ 0xa864,
+ 0xa865,
+ 0xa870,
+ 0xa871,
+ 0xa872,
+ 0xa873,
+ 0xa874,
+ 0xa875,
+ 0xa876,
+ 0xa877,
+ 0xa878,
+ 0xa879,
+ 0xa87a,
+ 0xa87b,
+ 0xa87c,
+ 0xa87d,
+ 0xa87e,
+ 0xa87f,
+ 0xa880,
+ 0xa881,
+ 0xa882,
+ 0xa883,
+ 0xa884,
+ 0xa885,
+ 0xa886,
+ 0xa887,
+ 0xa888,
+ 0xa889,
+ 0xa88a,
+ 0xa88b,
+ 0xa88c,
+ 0xa88d,
+ 0xa88e,
+ 0xa88f,
+ 0xa890,
+ 0xa891,
+ 0xa892,
+ 0xa893,
+ 0xa894,
+ 0xa895,
+ 0xa896,
+ 0xa980,
+ 0xa982,
+ 0xa983,
+ 0xa984,
+ 0xa985,
+ 0xa986,
+ 0xa987,
+ 0xa988,
+ 0xa989,
+ 0xa98a,
+ 0xa98b,
+ 0xa98c,
+ 0xa98d,
+ 0xa98e,
+ 0xa98f,
+ 0xa990,
+ 0xa991,
+ 0xa992,
+ 0xa993,
+ 0xa994,
+ 0xa995,
+ 0xa996,
+ 0xa997,
+ 0xa998,
+ 0xa999,
+ 0xa99a,
+ 0xa99b,
+ 0xa99c,
+ 0xa99d,
+ 0xa99e,
+ 0xa99f,
+ 0xa9a0,
+ 0xa9a1,
+ 0xa9a2,
+ 0xa9a3,
+ 0xa9a4,
+ 0xa9a5,
+ 0xa9a6,
+ 0xa9a7,
+ 0xa9a9,
+ 0xa9e0,
+ 0xa9e1,
+ 0xa9e4,
+ 0xa9e5,
+ 0xab00,
+ 0xab04,
+ 0xab05,
+ 0xab10,
+ 0xab11,
+ 0xab12,
+ 0xab13,
+ 0xab14,
+ 0xab15,
+ 0xab16,
+ 0xab17,
+ 0xab18,
+ 0xab19,
+ 0xacc0,
+ 0xb300,
+ 0xb301,
+ 0xb304,
+ 0xb305,
+ 0xb306,
+ 0xb307,
+ 0xb4c0,
+ 0xb4c1,
+ 0xb4c2,
+ 0xb4c3,
+ 0xb4c4,
+ 0xb4ca,
+ 0xb4cb,
+ 0xb4cc,
+ 0xb4d1,
+ 0xb800,
+ 0xb801,
+ 0xb802,
+ 0xb803,
+ 0xb980,
+ 0xb982,
+ 0xb983,
+ 0xb984,
+ 0xb985,
+ 0xb986,
+ 0xb990,
+ 0xb991,
+ 0xb992,
+ 0xb993,
+ 0xb994,
+ 0xb995,
+ 0xb996,
+ 0xb997,
+ 0xb998,
+ 0xb999,
+ 0xb99a,
+ 0xb99b,
+ 0xb9c0,
+ 0xb9c1,
+ 0xb9c2,
+ 0xb9c3,
+ 0xb9c4,
+ 0xb9c5,
+ 0xb9c6,
+ 0xb9c7,
+ 0xb9c8,
+ 0xb9c9,
+ 0xbb10,
+};
+template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = {
+ 0xc02,
+ 0xc06,
+ 0xc10,
+ 0xc11,
+ 0xc12,
+ 0xc13,
+ 0xc14,
+ 0xc15,
+ 0xc16,
+ 0xc17,
+ 0xc18,
+ 0xc19,
+ 0xc1a,
+ 0xc1b,
+ 0xc1c,
+ 0xc1d,
+ 0xc1e,
+ 0xc1f,
+ 0xc20,
+ 0xc21,
+ 0xc22,
+ 0xc23,
+ 0xc24,
+ 0xc25,
+ 0xc26,
+ 0xc27,
+ 0xc28,
+ 0xc29,
+ 0xc2a,
+ 0xc2b,
+ 0xc2c,
+ 0xc2d,
+ 0xc2e,
+ 0xc2f,
+ 0xc38,
+ 0xc39,
+ 0xc3a,
+ 0xc3b,
+ 0xc3c,
+ 0xc3d,
+ 0xc3e,
+ 0xc3f,
+ 0xc40,
+ 0xc41,
+ 0xc42,
+ 0xc43,
+ 0xc44,
+ 0xc45,
+ 0xc46,
+ 0xc47,
+ 0xc48,
+ 0xc49,
+ 0xc4a,
+ 0xc4b,
+ 0xc4c,
+ 0xc4d,
+ 0xc4e,
+ 0xc4f,
+ 0xc50,
+ 0xc51,
+ 0xc52,
+ 0xc53,
+ 0xc54,
+ 0xc55,
+ 0xc56,
+ 0xc57,
+ 0x8000,
+ 0x8001,
+ 0x8002,
+ 0x8003,
+ 0x8004,
+ 0x8005,
+ 0x8006,
+ 0x8007,
+ 0x8010,
+ 0x8011,
+ 0x8012,
+ 0x8013,
+ 0x8014,
+ 0x8015,
+ 0x8016,
+ 0x8017,
+ 0x8018,
+ 0x8019,
+ 0x801a,
+ 0x801b,
+ 0x801c,
+ 0x801d,
+ 0x801e,
+ 0x801f,
+ 0x8020,
+ 0x8021,
+ 0x8022,
+ 0x8023,
+ 0x8024,
+ 0x8025,
+ 0x8026,
+ 0x8027,
+ 0x8028,
+ 0x8029,
+ 0x802a,
+ 0x802b,
+ 0x802c,
+ 0x802d,
+ 0x802e,
+ 0x802f,
+ 0x8030,
+ 0x8031,
+ 0x8032,
+ 0x8033,
+ 0x8034,
+ 0x8035,
+ 0x8036,
+ 0x8037,
+ 0x8038,
+ 0x8039,
+ 0x803a,
+ 0x803b,
+ 0x803c,
+ 0x803d,
+ 0x803e,
+ 0x803f,
+ 0x8040,
+ 0x8041,
+ 0x8042,
+ 0x8043,
+ 0x8044,
+ 0x8045,
+ 0x8046,
+ 0x8047,
+ 0x8048,
+ 0x8049,
+ 0x804a,
+ 0x804b,
+ 0x804c,
+ 0x804d,
+ 0x804e,
+ 0x804f,
+ 0x8050,
+ 0x8051,
+ 0x8052,
+ 0x8053,
+ 0x8054,
+ 0x8055,
+ 0x8056,
+ 0x8057,
+ 0x8058,
+ 0x8059,
+ 0x805a,
+ 0x805b,
+ 0x805c,
+ 0x805d,
+ 0x805e,
+ 0x805f,
+ 0x8060,
+ 0x8061,
+ 0x8062,
+ 0x8063,
+ 0x8064,
+ 0x8065,
+ 0x8066,
+ 0x8067,
+ 0x8068,
+ 0x8069,
+ 0x806a,
+ 0x806b,
+ 0x806c,
+ 0x806d,
+ 0x806e,
+ 0x806f,
+ 0x8070,
+ 0x8071,
+ 0x8072,
+ 0x8073,
+ 0x8074,
+ 0x8075,
+ 0x8076,
+ 0x8077,
+ 0x8078,
+ 0x8079,
+ 0x807a,
+ 0x807b,
+ 0x807c,
+ 0x807d,
+ 0x807e,
+ 0x807f,
+ 0x8080,
+ 0x8081,
+ 0x8082,
+ 0x8083,
+ 0x8084,
+ 0x8085,
+ 0x8086,
+ 0x8087,
+ 0x8088,
+ 0x8089,
+ 0x808a,
+ 0x808b,
+ 0x808c,
+ 0x808d,
+ 0x808e,
+ 0x808f,
+ 0x8090,
+ 0x8091,
+ 0x8092,
+ 0x8094,
+ 0x8095,
+ 0x8096,
+ 0x8097,
+ 0x8098,
+ 0x809b,
+ 0x809c,
+ 0x809d,
+ 0x80a0,
+ 0x80a1,
+ 0x80a2,
+ 0x80a3,
+ 0x80a4,
+ 0x80a5,
+ 0x80a6,
+ 0x80b0,
+ 0x80b1,
+ 0x80b2,
+ 0x80b3,
+ 0x80b4,
+ 0x80b5,
+ 0x80b6,
+ 0x80b7,
+ 0x80b8,
+ 0x80b9,
+ 0x80ba,
+ 0x80bb,
+ 0x80bc,
+ 0x80bd,
+ 0x80be,
+ 0x80bf,
+ 0x80c0,
+ 0x80c1,
+ 0x80c2,
+ 0x80c3,
+ 0x80c4,
+ 0x80c5,
+ 0x80c6,
+ 0x80c7,
+ 0x80c8,
+ 0x80c9,
+ 0x80ca,
+ 0x80cb,
+ 0x80cc,
+ 0x80cd,
+ 0x80ce,
+ 0x80cf,
+ 0x80d0,
+ 0x80d1,
+ 0x80d2,
+ 0x80d3,
+ 0x80d4,
+ 0x80d5,
+ 0x80d6,
+ 0x80d7,
+ 0x80d8,
+ 0x80d9,
+ 0x80da,
+ 0x80db,
+ 0x80dc,
+ 0x80dd,
+ 0x80de,
+ 0x80df,
+ 0x80e0,
+ 0x80e1,
+ 0x80e2,
+ 0x80e3,
+ 0x80e4,
+ 0x80e5,
+ 0x80e6,
+ 0x80e7,
+ 0x80e8,
+ 0x80e9,
+ 0x80ea,
+ 0x80eb,
+ 0x80ec,
+ 0x80ed,
+ 0x80ee,
+ 0x80ef,
+ 0x80f0,
+ 0x80f1,
+ 0x8100,
+ 0x8101,
+ 0x8102,
+ 0x8103,
+ 0x8104,
+ 0x8105,
+ 0x8106,
+ 0x8107,
+ 0x8109,
+ 0x8113,
+ 0x8114,
+ 0x8115,
+ 0x8116,
+ 0x8400,
+ 0x8401,
+ 0x8402,
+ 0x8403,
+ 0x8404,
+ 0x8405,
+ 0x8406,
+ 0x840a,
+ 0x840b,
+ 0x8800,
+ 0x8801,
+ 0x8802,
+ 0x8803,
+ 0x8804,
+ 0x8805,
+ 0x8806,
+ 0x8809,
+ 0x880a,
+ 0x880b,
+ 0x880c,
+ 0x880d,
+ 0x880f,
+ 0x8810,
+ 0x8812,
+ 0x8820,
+ 0x8821,
+ 0x8822,
+ 0x8823,
+ 0x8824,
+ 0x8825,
+ 0x8826,
+ 0x8827,
+ 0x8828,
+ 0x8829,
+ 0x882a,
+ 0x882b,
+ 0x882c,
+ 0x882d,
+ 0x882e,
+ 0x882f,
+ 0x8830,
+ 0x8831,
+ 0x8832,
+ 0x8833,
+ 0x8834,
+ 0x8835,
+ 0x8836,
+ 0x8837,
+ 0x8838,
+ 0x8839,
+ 0x883a,
+ 0x883b,
+ 0x883c,
+ 0x883d,
+ 0x883e,
+ 0x883f,
+ 0x8840,
+ 0x8841,
+ 0x8842,
+ 0x8843,
+ 0x8844,
+ 0x8845,
+ 0x8846,
+ 0x8847,
+ 0x8848,
+ 0x8849,
+ 0x884a,
+ 0x884b,
+ 0x884c,
+ 0x884d,
+ 0x884e,
+ 0x884f,
+ 0x8850,
+ 0x8851,
+ 0x8852,
+ 0x8853,
+ 0x8854,
+ 0x8855,
+ 0x8856,
+ 0x8857,
+ 0x8858,
+ 0x8859,
+ 0x885a,
+ 0x885b,
+ 0x885c,
+ 0x885d,
+ 0x885e,
+ 0x885f,
+ 0x8860,
+ 0x8861,
+ 0x8862,
+ 0x8863,
+ 0x8865,
+ 0x8870,
+ 0x8871,
+ 0x8872,
+ 0x8873,
+ 0x8874,
+ 0x8875,
+ 0x8876,
+ 0x8877,
+ 0x8878,
+ 0x8879,
+ 0x8880,
+ 0x8881,
+ 0x8882,
+ 0x8883,
+ 0x8884,
+ 0x8885,
+ 0x8886,
+ 0x8887,
+ 0x8888,
+ 0x8889,
+ 0x8890,
+ 0x8898,
+ 0x88c0,
+ 0x88c1,
+ 0x88d0,
+ 0x88d1,
+ 0x88d2,
+ 0x88d3,
+ 0x88d4,
+ 0x88d5,
+ 0x88d6,
+ 0x88d7,
+ 0x88d8,
+ 0x88d9,
+ 0x88da,
+ 0x88db,
+ 0x88dc,
+ 0x88dd,
+ 0x88de,
+ 0x88df,
+ 0x88e0,
+ 0x88e1,
+ 0x88e2,
+ 0x88e3,
+ 0x8900,
+ 0x8901,
+ 0x8902,
+ 0x8903,
+ 0x8904,
+ 0x8905,
+ 0x8906,
+ 0x8907,
+ 0x8908,
+ 0x8909,
+ 0x890a,
+ 0x890b,
+ 0x890c,
+ 0x890d,
+ 0x890e,
+ 0x890f,
+ 0x8910,
+ 0x8911,
+ 0x8912,
+ 0x8913,
+ 0x8914,
+ 0x8915,
+ 0x8916,
+ 0x8917,
+ 0x8918,
+ 0x8919,
+ 0x891a,
+ 0x8c00,
+ 0x8c01,
+ 0x8c17,
+ 0x8c18,
+ 0x8c19,
+ 0x8c1a,
+ 0x8c1b,
+ 0x8c1c,
+ 0x8c1d,
+ 0x8c1e,
+ 0x8c1f,
+ 0x8c20,
+ 0x8c21,
+ 0x8c22,
+ 0x8c23,
+ 0x8c24,
+ 0x8c25,
+ 0x8c2c,
+ 0x8c2d,
+ 0x8c2e,
+ 0x8c2f,
+ 0x9101,
+ 0x9102,
+ 0x9103,
+ 0x9104,
+ 0x9105,
+ 0x9106,
+ 0x9107,
+ 0x9108,
+ 0x9109,
+ 0x910a,
+ 0x910b,
+ 0x910c,
+ 0x9200,
+ 0x9201,
+ 0x9202,
+ 0x9203,
+ 0x9204,
+ 0x9205,
+ 0x9206,
+ 0x9207,
+ 0x9208,
+ 0x9209,
+ 0x920a,
+ 0x920b,
+ 0x920c,
+ 0x920d,
+ 0x920e,
+ 0x920f,
+ 0x9212,
+ 0x9213,
+ 0x9214,
+ 0x9215,
+ 0x9216,
+ 0x9217,
+ 0x9301,
+ 0x9302,
+ 0x9303,
+ 0x9304,
+ 0x9305,
+ 0x9306,
+ 0x9307,
+ 0x9308,
+ 0x9309,
+ 0x9311,
+ 0x9312,
+ 0x9313,
+ 0x9314,
+ 0x9315,
+ 0x9316,
+ 0x9317,
+ 0x9800,
+ 0x9801,
+ 0x9802,
+ 0x9803,
+ 0x9804,
+ 0x9805,
+ 0x9806,
+ 0x9808,
+ 0x9809,
+ 0x9b00,
+ 0x9b01,
+ 0x9b02,
+ 0x9b03,
+ 0x9b04,
+ 0x9b05,
+ 0x9b07,
+ 0x9b08,
+ 0x9b09,
+ 0xa000,
+ 0xa001,
+ 0xa002,
+ 0xa003,
+ 0xa004,
+ 0xa005,
+ 0xa006,
+ 0xa008,
+ 0xa00e,
+ 0xa00f,
+ 0xa010,
+ 0xa011,
+ 0xa012,
+ 0xa013,
+ 0xa014,
+ 0xa015,
+ 0xa016,
+ 0xa017,
+ 0xa018,
+ 0xa019,
+ 0xa01a,
+ 0xa01b,
+ 0xa01c,
+ 0xa01d,
+ 0xa01e,
+ 0xa01f,
+ 0xa020,
+ 0xa021,
+ 0xa022,
+ 0xa023,
+ 0xa024,
+ 0xa025,
+ 0xa026,
+ 0xa027,
+ 0xa028,
+ 0xa029,
+ 0xa02a,
+ 0xa02b,
+ 0xa02c,
+ 0xa02d,
+ 0xa02e,
+ 0xa02f,
+ 0xa030,
+ 0xa031,
+ 0xa032,
+ 0xa033,
+ 0xa034,
+ 0xa035,
+ 0xa036,
+ 0xa037,
+ 0xa038,
+ 0xa039,
+ 0xa03a,
+ 0xa03b,
+ 0xa03c,
+ 0xa03d,
+ 0xa03e,
+ 0xa03f,
+ 0xa040,
+ 0xa041,
+ 0xa042,
+ 0xa043,
+ 0xa044,
+ 0xa045,
+ 0xa046,
+ 0xa047,
+ 0xa048,
+ 0xa049,
+ 0xa04a,
+ 0xa04b,
+ 0xa04c,
+ 0xa04d,
+ 0xa04e,
+ 0xa04f,
+ 0xa050,
+ 0xa051,
+ 0xa052,
+ 0xa053,
+ 0xa054,
+ 0xa055,
+ 0xa056,
+ 0xa057,
+ 0xa058,
+ 0xa059,
+ 0xa05a,
+ 0xa05b,
+ 0xa05c,
+ 0xa05d,
+ 0xa05e,
+ 0xa05f,
+ 0xa060,
+ 0xa061,
+ 0xa062,
+ 0xa063,
+ 0xa064,
+ 0xa065,
+ 0xa066,
+ 0xa067,
+ 0xa068,
+ 0xa069,
+ 0xa06a,
+ 0xa06b,
+ 0xa06c,
+ 0xa06d,
+ 0xa06e,
+ 0xa06f,
+ 0xa070,
+ 0xa071,
+ 0xa072,
+ 0xa073,
+ 0xa074,
+ 0xa075,
+ 0xa076,
+ 0xa077,
+ 0xa078,
+ 0xa079,
+ 0xa07a,
+ 0xa07b,
+ 0xa07c,
+ 0xa07d,
+ 0xa07e,
+ 0xa07f,
+ 0xa080,
+ 0xa081,
+ 0xa082,
+ 0xa083,
+ 0xa084,
+ 0xa085,
+ 0xa086,
+ 0xa087,
+ 0xa088,
+ 0xa089,
+ 0xa08a,
+ 0xa08b,
+ 0xa08c,
+ 0xa08d,
+ 0xa08e,
+ 0xa08f,
+ 0xa090,
+ 0xa091,
+ 0xa092,
+ 0xa093,
+ 0xa094,
+ 0xa095,
+ 0xa096,
+ 0xa097,
+ 0xa098,
+ 0xa099,
+ 0xa09a,
+ 0xa09b,
+ 0xa09c,
+ 0xa09d,
+ 0xa09e,
+ 0xa09f,
+ 0xa0a0,
+ 0xa0a1,
+ 0xa0a2,
+ 0xa0a3,
+ 0xa0a4,
+ 0xa0a5,
+ 0xa0a6,
+ 0xa0a7,
+ 0xa0a8,
+ 0xa0a9,
+ 0xa0aa,
+ 0xa0ab,
+ 0xa0ac,
+ 0xa0ad,
+ 0xa0ae,
+ 0xa0af,
+ 0xa0b0,
+ 0xa0b1,
+ 0xa0b2,
+ 0xa0b3,
+ 0xa0b4,
+ 0xa0b5,
+ 0xa0b6,
+ 0xa0b7,
+ 0xa0b8,
+ 0xa0b9,
+ 0xa0ba,
+ 0xa0bb,
+ 0xa0bc,
+ 0xa0bd,
+ 0xa0be,
+ 0xa0bf,
+ 0xa0c0,
+ 0xa0c1,
+ 0xa0c2,
+ 0xa0c3,
+ 0xa0c4,
+ 0xa0c5,
+ 0xa0c6,
+ 0xa0c7,
+ 0xa0c8,
+ 0xa0c9,
+ 0xa0ca,
+ 0xa0cb,
+ 0xa0cc,
+ 0xa0cd,
+ 0xa0ce,
+ 0xa0cf,
+ 0xa0d0,
+ 0xa0d1,
+ 0xa0d2,
+ 0xa0d3,
+ 0xa0d4,
+ 0xa0d5,
+ 0xa0d6,
+ 0xa0d7,
+ 0xa0d8,
+ 0xa0d9,
+ 0xa0da,
+ 0xa0db,
+ 0xa0dc,
+ 0xa0dd,
+ 0xa0de,
+ 0xa0df,
+ 0xa0e0,
+ 0xa0e1,
+ 0xa0e2,
+ 0xa0e3,
+ 0xa0e4,
+ 0xa0e5,
+ 0xa0e6,
+ 0xa0e7,
+ 0xa0e8,
+ 0xa0e9,
+ 0xa0ea,
+ 0xa0eb,
+ 0xa0ec,
+ 0xa0ed,
+ 0xa0ee,
+ 0xa0ef,
+ 0xa0f8,
+ 0xa800,
+ 0xa802,
+ 0xa803,
+ 0xa804,
+ 0xa805,
+ 0xa806,
+ 0xa807,
+ 0xa808,
+ 0xa809,
+ 0xa80a,
+ 0xa80b,
+ 0xa80c,
+ 0xa80d,
+ 0xa80e,
+ 0xa80f,
+ 0xa810,
+ 0xa811,
+ 0xa812,
+ 0xa813,
+ 0xa814,
+ 0xa815,
+ 0xa816,
+ 0xa817,
+ 0xa818,
+ 0xa819,
+ 0xa81a,
+ 0xa81b,
+ 0xa81c,
+ 0xa81d,
+ 0xa81e,
+ 0xa81f,
+ 0xa820,
+ 0xa821,
+ 0xa822,
+ 0xa823,
+ 0xa824,
+ 0xa825,
+ 0xa827,
+ 0xa830,
+ 0xa831,
+ 0xa832,
+ 0xa833,
+ 0xa834,
+ 0xa835,
+ 0xa836,
+ 0xa837,
+ 0xa838,
+ 0xa839,
+ 0xa83a,
+ 0xa83b,
+ 0xa83c,
+ 0xa83d,
+ 0xa83f,
+ 0xa840,
+ 0xa842,
+ 0xa843,
+ 0xa844,
+ 0xa845,
+ 0xa846,
+ 0xa847,
+ 0xa848,
+ 0xa849,
+ 0xa84a,
+ 0xa84b,
+ 0xa84c,
+ 0xa84d,
+ 0xa84e,
+ 0xa84f,
+ 0xa850,
+ 0xa851,
+ 0xa852,
+ 0xa853,
+ 0xa854,
+ 0xa855,
+ 0xa856,
+ 0xa857,
+ 0xa858,
+ 0xa859,
+ 0xa85a,
+ 0xa85b,
+ 0xa85c,
+ 0xa85d,
+ 0xa85e,
+ 0xa85f,
+ 0xa860,
+ 0xa861,
+ 0xa862,
+ 0xa863,
+ 0xa864,
+ 0xa865,
+ 0xa867,
+ 0xa870,
+ 0xa871,
+ 0xa872,
+ 0xa873,
+ 0xa874,
+ 0xa875,
+ 0xa876,
+ 0xa877,
+ 0xa878,
+ 0xa879,
+ 0xa87a,
+ 0xa87b,
+ 0xa87c,
+ 0xa87d,
+ 0xa87e,
+ 0xa87f,
+ 0xa880,
+ 0xa881,
+ 0xa882,
+ 0xa883,
+ 0xa884,
+ 0xa885,
+ 0xa886,
+ 0xa887,
+ 0xa888,
+ 0xa889,
+ 0xa88a,
+ 0xa88b,
+ 0xa88c,
+ 0xa88d,
+ 0xa88e,
+ 0xa88f,
+ 0xa890,
+ 0xa891,
+ 0xa892,
+ 0xa893,
+ 0xa894,
+ 0xa895,
+ 0xa896,
+ 0xa898,
+ 0xa980,
+ 0xa982,
+ 0xa983,
+ 0xa984,
+ 0xa985,
+ 0xa986,
+ 0xa987,
+ 0xa988,
+ 0xa989,
+ 0xa98a,
+ 0xa98b,
+ 0xa98c,
+ 0xa98d,
+ 0xa98e,
+ 0xa98f,
+ 0xa990,
+ 0xa991,
+ 0xa992,
+ 0xa993,
+ 0xa994,
+ 0xa995,
+ 0xa996,
+ 0xa997,
+ 0xa998,
+ 0xa999,
+ 0xa99a,
+ 0xa99b,
+ 0xa99c,
+ 0xa99d,
+ 0xa99e,
+ 0xa99f,
+ 0xa9a0,
+ 0xa9a1,
+ 0xa9a2,
+ 0xa9a3,
+ 0xa9a4,
+ 0xa9a5,
+ 0xa9a6,
+ 0xa9a7,
+ 0xa9a9,
+ 0xa9aa,
+ 0xa9ae,
+ 0xa9bf,
+ 0xa9c6,
+ 0xa9c7,
+ 0xa9c8,
+ 0xa9c9,
+ 0xa9ca,
+ 0xa9cb,
+ 0xa9d4,
+ 0xa9d5,
+ 0xa9d6,
+ 0xa9d7,
+ 0xa9d8,
+ 0xa9d9,
+ 0xa9da,
+ 0xa9db,
+ 0xa9dc,
+ 0xa9dd,
+ 0xa9de,
+ 0xa9e0,
+ 0xa9e1,
+ 0xa9e4,
+ 0xa9e5,
+ 0xab00,
+ 0xab03,
+ 0xab04,
+ 0xab05,
+ 0xab0a,
+ 0xab0b,
+ 0xab0c,
+ 0xab0d,
+ 0xab0e,
+ 0xab0f,
+ 0xab10,
+ 0xab11,
+ 0xab12,
+ 0xab13,
+ 0xab14,
+ 0xab15,
+ 0xab16,
+ 0xab17,
+ 0xab18,
+ 0xab19,
+ 0xab21,
+ 0xb2c0,
+ 0xb2c2,
+ 0xb2c3,
+ 0xb2ca,
+ 0xb2cb,
+ 0xb2cc,
+ 0xb2d2,
+ 0xb300,
+ 0xb301,
+ 0xb304,
+ 0xb305,
+ 0xb306,
+ 0xb307,
+};
+#endif
+
#endif /* A6XX_XML */
* note: downstream saves the value in poweroff and restores it here
*/
if (adreno_is_a7xx(adreno_gpu))
- gmu_write(gmu, REG_A6XX_GMU_GENERAL_9, 0);
+ gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0);
else
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
*/
if (adreno_is_a740(adreno_gpu))
chipid_min = 2;
+ else if (adreno_is_a750(adreno_gpu))
+ chipid_min = 9;
else
return -EINVAL;
}
if (adreno_is_a7xx(adreno_gpu)) {
- gmu_write(gmu, REG_A6XX_GMU_GENERAL_10, chipid);
- gmu_write(gmu, REG_A6XX_GMU_GENERAL_8,
+ gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid);
+ gmu_write(gmu, REG_A7XX_GMU_GENERAL_8,
(gmu->log.iova & GENMASK(31, 12)) |
((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));
} else {
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
+
+Copyright (C) 2013-2024 by the following authors:
+- Rob Clark <robdclark@gmail.com> Rob Clark
+- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
+
+#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
+#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
+
+#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
+#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
+#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
+#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
+#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
+#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
+#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
+#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
+#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
+#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
+#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
-#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK 0x00800000
-#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT 23
-static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)
-{
- return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK;
-}
-#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK 0x40000000
-#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT 30
-static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)
-{
- return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK;
-}
-#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK 0x00400000
-#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT 22
-static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK;
-}
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK 0x40000000
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT 30
-static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK;
-}
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK 0x40000000
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT 30
-static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK;
-}
-#define A6XX_GMU_OOB_DCVS_SET_MASK__MASK 0x00800000
-#define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT 23
-static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK;
-}
-#define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK 0x80000000
-#define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT 31
-static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK;
-}
-#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK 0x80000000
-#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT 31
-static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK;
-}
-#define A6XX_GMU_OOB_GPU_SET_MASK__MASK 0x00040000
-#define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT 18
-static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK;
-}
-#define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK 0x04000000
-#define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT 26
-static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK;
-}
-#define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK 0x04000000
-#define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT 26
-static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK;
-}
-#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK 0x00020000
-#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT 17
-static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK;
-}
-#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK 0x02000000
-#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT 25
-static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK;
-}
-#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK 0x02000000
-#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT 25
-static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK;
-}
#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
-#define A6XX_HFI_IRQ_DSGQ_MASK__MASK 0x00000002
-#define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT 1
-static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)
-{
- return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK;
-}
-#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK 0x00000004
-#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT 2
-static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)
-{
- return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK;
-}
-#define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK 0x00800000
-#define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT 23
-static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)
-{
- return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK;
-}
+#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
+#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
+#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
}
+
#define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
+
#define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
#define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
+#define REG_A6XX_GMU_GENERAL_0 0x000051c5
+
#define REG_A6XX_GMU_GENERAL_1 0x000051c6
+#define REG_A6XX_GMU_GENERAL_6 0x000051cb
+
#define REG_A6XX_GMU_GENERAL_7 0x000051cc
-#define REG_A6XX_GMU_GENERAL_8 0x000051cd
+#define REG_A7XX_GMU_GENERAL_8 0x000051cd
-#define REG_A6XX_GMU_GENERAL_9 0x000051ce
+#define REG_A7XX_GMU_GENERAL_9 0x000051ce
-#define REG_A6XX_GMU_GENERAL_10 0x000051cf
+#define REG_A7XX_GMU_GENERAL_10 0x000051cf
#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e
+#ifdef __cplusplus
+#endif
#endif /* A6XX_GMU_XML */
{}
};
+const struct adreno_reglist a702_hwcg[] = {
+ { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
+ { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+ { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
+ { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+ { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
+ { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+ { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
+ {}
+};
+
const struct adreno_reglist a730_hwcg[] = {
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
unsigned int i;
u32 val, clock_cntl_on, cgc_mode;
- if (!adreno_gpu->info->hwcg)
+ if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu)))
return;
if (adreno_is_a630(adreno_gpu))
clock_cntl_on = 0x8aa8aa02;
else if (adreno_is_a610(adreno_gpu))
clock_cntl_on = 0xaaa8aa82;
+ else if (adreno_is_a702(adreno_gpu))
+ clock_cntl_on = 0xaaaaaa82;
else
clock_cntl_on = 0x8aa8aa82;
state ? 0x5555 : 0);
}
+ if (!adreno_gpu->info->hwcg) {
+ gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
+ gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0);
+
+ if (state) {
+ gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1);
+
+ if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val,
+ val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) {
+ dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n");
+ return;
+ }
+
+ gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0);
+ }
+
+ return;
+ }
+
val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
/* Don't re-program the registers if they are already correct */
return;
/* Disable SP clock before programming HWCG registers */
- if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
+ if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
gpu_write(gpu, reg->offset, state ? reg->value : 0);
/* Enable SP clock */
- if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
+ if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
const u32 *regs = a6xx_protect;
unsigned i, count, count_max;
- if (adreno_is_a650(adreno_gpu)) {
+ if (adreno_is_a650(adreno_gpu) || adreno_is_a702(adreno_gpu)) {
regs = a650_protect;
count = ARRAY_SIZE(a650_protect);
count_max = 48;
count = ARRAY_SIZE(a660_protect);
count_max = 48;
BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
- } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) {
+ } else if (adreno_is_a730(adreno_gpu) ||
+ adreno_is_a740(adreno_gpu) ||
+ adreno_is_a750(adreno_gpu)) {
regs = a730_protect;
count = ARRAY_SIZE(a730_protect);
count_max = 48;
gpu->ubwc_config.ubwc_mode = 1;
}
- /* a618 is using the hw default values */
if (adreno_is_a618(gpu))
- return;
+ gpu->ubwc_config.highest_bank_bit = 14;
if (adreno_is_a619_holi(gpu))
gpu->ubwc_config.highest_bank_bit = 13;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
}
+
+ if (adreno_is_a702(gpu)) {
+ gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.min_acc_len = 1;
+ gpu->ubwc_config.ubwc_mode = 2;
+ }
}
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
return false;
/* A7xx is safe! */
- if (adreno_is_a7xx(adreno_gpu))
+ if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu))
return true;
/*
a6xx_set_hwcg(gpu, true);
/* VBIF/GBIF start*/
- if (adreno_is_a610(adreno_gpu) ||
+ if (adreno_is_a610_family(adreno_gpu) ||
adreno_is_a640_family(adreno_gpu) ||
adreno_is_a650_family(adreno_gpu) ||
adreno_is_a7xx(adreno_gpu)) {
}
if (!(adreno_is_a650_family(adreno_gpu) ||
+ adreno_is_a702(adreno_gpu) ||
adreno_is_a730(adreno_gpu))) {
gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M;
if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
- } else if (adreno_is_a610(adreno_gpu)) {
+ } else if (adreno_is_a610_family(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);
} else if (!adreno_is_a7xx(adreno_gpu)) {
if (adreno_is_a610(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
+ } else if (adreno_is_a702(adreno_gpu)) {
+ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64);
+ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63);
} else if (!adreno_is_a7xx(adreno_gpu))
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
/* Setting the primFifo thresholds default values,
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
*/
- if (adreno_is_a690(adreno_gpu))
+ if (adreno_is_a702(adreno_gpu))
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);
+ else if (adreno_is_a690(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
else if (adreno_is_a619(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
- else if (adreno_is_a610(adreno_gpu))
+ else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
else
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
else
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
+ } else if (adreno_is_a702(adreno_gpu)) {
+ /* Something to do with the HLSQ cluster */
+ gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24));
}
if (adreno_is_a690(adreno_gpu))
static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
static const char *uche_clients[7] = {
"VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
};
u32 val;
- if (mid < 1 || mid > 3)
- return "UNKNOWN";
+ if (adreno_is_a7xx(adreno_gpu)) {
+ if (mid != 1 && mid != 2 && mid != 3 && mid != 8)
+ return "UNKNOWN";
+ } else {
+ if (mid < 1 || mid > 3)
+ return "UNKNOWN";
+ }
/*
* The source of the data depends on the mid ID read from FSYNR1.
*/
val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
- /* mid = 3 is most precise and refers to only one block per client */
- if (mid == 3)
- return uche_clients[val & 7];
+ if (adreno_is_a7xx(adreno_gpu)) {
+ /* Bit 3 for mid=3 indicates BR or BV */
+ static const char *uche_clients_a7xx[16] = {
+ "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC",
+ "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP",
+ "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC",
+ "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP",
+ };
+
+ /* LPAC has the same clients as BR and BV, but because it is
+ * compute-only some of them do not exist and there are holes
+ * in the array.
+ */
+ static const char *uche_clients_lpac_a7xx[8] = {
+ "-", "LPAC_SP", "-", "-",
+ "LPAC_HLSQ", "-", "-", "LPAC_TP",
+ };
+
+ val &= GENMASK(6, 0);
+
+ /* mid=3 refers to BR or BV */
+ if (mid == 3) {
+ if (val < ARRAY_SIZE(uche_clients_a7xx))
+ return uche_clients_a7xx[val];
+ else
+ return "UCHE";
+ }
+
+ /* mid=8 refers to LPAC */
+ if (mid == 8) {
+ if (val < ARRAY_SIZE(uche_clients_lpac_a7xx))
+ return uche_clients_lpac_a7xx[val];
+ else
+ return "UCHE_LPAC";
+ }
+
+ /* mid=2 is a catchall for everything else in LPAC */
+ if (mid == 2)
+ return "UCHE_LPAC";
+
+ /* mid=1 is a catchall for everything else in BR/BV */
+ return "UCHE";
+ } else if (adreno_is_a660_family(adreno_gpu)) {
+ static const char *uche_clients_a660[8] = {
+ "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP",
+ };
- /* For mid=2 the source is TP or VFD except when the client id is 0 */
- if (mid == 2)
- return ((val & 7) == 0) ? "TP" : "TP|VFD";
+ static const char *uche_clients_a660_not[8] = {
+ "not VFD", "not SP", "not VSC", "not VPC",
+ "not HLSQ", "not PC", "not LRZ", "not TP",
+ };
- /* For mid=1 just return "UCHE" as a catchall for everything else */
- return "UCHE";
+ val &= GENMASK(6, 0);
+
+ if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660))
+ return uche_clients_a660[val];
+
+ if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not))
+ return uche_clients_a660_not[val];
+
+ return "UCHE";
+ } else {
+ /* mid = 3 is most precise and refers to only one block per client */
+ if (mid == 3)
+ return uche_clients[val & 7];
+
+ /* For mid=2 the source is TP or VFD except when the client id is 0 */
+ if (mid == 2)
+ return ((val & 7) == 0) ? "TP" : "TP|VFD";
+
+ /* For mid=1 just return "UCHE" as a catchall for everything else */
+ return "UCHE";
+ }
}
static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+
if (id == 0)
return "CP";
else if (id == 4)
return "CCU";
else if (id == 6)
return "CDP Prefetch";
+ else if (id == 7)
+ return "GMU";
+ else if (id == 5 && adreno_is_a7xx(adreno_gpu))
+ return "Flag cache";
return a6xx_uche_fault_block(gpu, id);
}
msm_devfreq_resume(gpu);
- adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate : a6xx_llc_activate(a6xx_gpu);
+ adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu);
return ret;
}
/* gpu->info only gets assigned in adreno_gpu_init() */
is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||
- config->info->family == ADRENO_7XX_GEN2;
+ config->info->family == ADRENO_7XX_GEN2 ||
+ config->info->family == ADRENO_7XX_GEN3;
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
#include "a6xx_gpu_state.h"
#include "a6xx_gmu.xml.h"
+/* Ignore diagnostics about register tables that we aren't using yet. We don't
+ * want to modify these headers too much from their original source.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-variable"
+
+#include "adreno_gen7_0_0_snapshot.h"
+#include "adreno_gen7_2_0_snapshot.h"
+
+#pragma GCC diagnostic pop
+
struct a6xx_gpu_state_obj {
const void *handle;
u32 *data;
ptr += cx_debugbus_read(cxdbg, block->id, i, ptr);
}
+static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ int nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
+ (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
+
+ if (adreno_is_a650_family(to_adreno_gpu(gpu)))
+ nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks);
+
+ a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
+ sizeof(*a6xx_state->debugbus));
+
+ if (a6xx_state->debugbus) {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
+ a6xx_get_debugbus_block(gpu,
+ a6xx_state,
+ &a6xx_debugbus_blocks[i],
+ &a6xx_state->debugbus[i]);
+
+ a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
+
+ /*
+ * GBIF has same debugbus as of other GPU blocks, fall back to
+ * default path if GPU uses GBIF, also GBIF uses exactly same
+ * ID as of VBIF.
+ */
+ if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
+ a6xx_get_debugbus_block(gpu, a6xx_state,
+ &a6xx_gbif_debugbus_block,
+ &a6xx_state->debugbus[i]);
+
+ a6xx_state->nr_debugbus += 1;
+ }
+
+
+ if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
+ for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++)
+ a6xx_get_debugbus_block(gpu,
+ a6xx_state,
+ &a650_debugbus_blocks[i],
+ &a6xx_state->debugbus[i]);
+ }
+ }
+}
+
+static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ int debugbus_blocks_count, total_debugbus_blocks;
+ const u32 *debugbus_blocks;
+ int i;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ debugbus_blocks = gen7_0_0_debugbus_blocks;
+ debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks);
+ } else {
+ BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ debugbus_blocks = gen7_2_0_debugbus_blocks;
+ debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks);
+ }
+
+ total_debugbus_blocks = debugbus_blocks_count +
+ ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
+
+ a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks,
+ sizeof(*a6xx_state->debugbus));
+
+ if (a6xx_state->debugbus) {
+ for (i = 0; i < debugbus_blocks_count; i++) {
+ a6xx_get_debugbus_block(gpu,
+ a6xx_state, &a7xx_debugbus_blocks[debugbus_blocks[i]],
+ &a6xx_state->debugbus[i]);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) {
+ a6xx_get_debugbus_block(gpu,
+ a6xx_state, &a7xx_gbif_debugbus_blocks[i],
+ &a6xx_state->debugbus[i + debugbus_blocks_count]);
+ }
+ }
+
+}
+
static void a6xx_get_debugbus(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct resource *res;
void __iomem *cxdbg = NULL;
- int nr_debugbus_blocks;
/* Set up the GX debug bus */
cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
}
- nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
- (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
-
- if (adreno_is_a650_family(to_adreno_gpu(gpu)))
- nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks);
-
- a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
- sizeof(*a6xx_state->debugbus));
-
- if (a6xx_state->debugbus) {
- int i;
-
- for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
- a6xx_get_debugbus_block(gpu,
- a6xx_state,
- &a6xx_debugbus_blocks[i],
- &a6xx_state->debugbus[i]);
-
- a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
-
- /*
- * GBIF has same debugbus as of other GPU blocks, fall back to
- * default path if GPU uses GBIF, also GBIF uses exactly same
- * ID as of VBIF.
- */
- if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
- a6xx_get_debugbus_block(gpu, a6xx_state,
- &a6xx_gbif_debugbus_block,
- &a6xx_state->debugbus[i]);
-
- a6xx_state->nr_debugbus += 1;
- }
-
-
- if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
- for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++)
- a6xx_get_debugbus_block(gpu,
- a6xx_state,
- &a650_debugbus_blocks[i],
- &a6xx_state->debugbus[i]);
- }
+ if (adreno_is_a7xx(adreno_gpu)) {
+ a7xx_get_debugbus_blocks(gpu, a6xx_state);
+ } else {
+ a6xx_get_debugbus_blocks(gpu, a6xx_state);
}
/* Dump the VBIF debugbus on applicable targets */
- if (!a6xx_has_gbif(to_adreno_gpu(gpu))) {
+ if (!a6xx_has_gbif(adreno_gpu)) {
a6xx_state->vbif_debugbus =
state_kcalloc(a6xx_state, 1,
sizeof(*a6xx_state->vbif_debugbus));
}
if (cxdbg) {
+ unsigned nr_cx_debugbus_blocks;
+ const struct a6xx_debugbus_block *cx_debugbus_blocks;
+
+ if (adreno_is_a7xx(adreno_gpu)) {
+ BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
+ cx_debugbus_blocks = a7xx_cx_debugbus_blocks;
+ nr_cx_debugbus_blocks = ARRAY_SIZE(a7xx_cx_debugbus_blocks);
+ } else {
+ cx_debugbus_blocks = a6xx_cx_debugbus_blocks;
+ nr_cx_debugbus_blocks = ARRAY_SIZE(a6xx_cx_debugbus_blocks);
+ }
+
a6xx_state->cx_debugbus =
state_kcalloc(a6xx_state,
- ARRAY_SIZE(a6xx_cx_debugbus_blocks),
+ nr_cx_debugbus_blocks,
sizeof(*a6xx_state->cx_debugbus));
if (a6xx_state->cx_debugbus) {
int i;
- for (i = 0; i < ARRAY_SIZE(a6xx_cx_debugbus_blocks); i++)
+ for (i = 0; i < nr_cx_debugbus_blocks; i++)
a6xx_get_cx_debugbus_block(cxdbg,
a6xx_state,
- &a6xx_cx_debugbus_blocks[i],
+ &cx_debugbus_blocks[i],
&a6xx_state->cx_debugbus[i]);
a6xx_state->nr_cx_debugbus =
- ARRAY_SIZE(a6xx_cx_debugbus_blocks);
+ nr_cx_debugbus_blocks;
}
iounmap(cxdbg);
datasize);
}
+static void a7xx_get_dbgahb_cluster(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const struct gen7_sptp_cluster_registers *dbgahb,
+ struct a6xx_gpu_state_obj *obj,
+ struct a6xx_crashdumper *dumper)
+{
+ u64 *in = dumper->ptr;
+ u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
+ size_t datasize;
+ int i, regcount = 0;
+
+ in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL,
+ A7XX_SP_READ_SEL_LOCATION(dbgahb->location_id) |
+ A7XX_SP_READ_SEL_PIPE(dbgahb->pipe_id) |
+ A7XX_SP_READ_SEL_STATETYPE(dbgahb->statetype));
+
+ for (i = 0; dbgahb->regs[i] != UINT_MAX; i += 2) {
+ int count = RANGE(dbgahb->regs, i);
+ u32 offset = REG_A7XX_SP_AHB_READ_APERTURE +
+ dbgahb->regs[i] - dbgahb->regbase;
+
+ in += CRASHDUMP_READ(in, offset, count, out);
+
+ out += count * sizeof(u32);
+ regcount += count;
+ }
+
+ CRASHDUMP_FINI(in);
+
+ datasize = regcount * sizeof(u32);
+
+ if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
+ return;
+
+ if (a6xx_crashdumper_run(gpu, dumper))
+ return;
+
+ obj->handle = dbgahb;
+ obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
+ datasize);
+}
+
static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
&a6xx_state->dbgahb_clusters[i], dumper);
}
+static void a7xx_get_dbgahb_clusters(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_crashdumper *dumper)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ int i;
+ const struct gen7_sptp_cluster_registers *dbgahb_clusters;
+ unsigned dbgahb_clusters_size;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ dbgahb_clusters = gen7_0_0_sptp_clusters;
+ dbgahb_clusters_size = ARRAY_SIZE(gen7_0_0_sptp_clusters);
+ } else {
+ BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ dbgahb_clusters = gen7_2_0_sptp_clusters;
+ dbgahb_clusters_size = ARRAY_SIZE(gen7_2_0_sptp_clusters);
+ }
+
+ a6xx_state->dbgahb_clusters = state_kcalloc(a6xx_state,
+ dbgahb_clusters_size,
+ sizeof(*a6xx_state->dbgahb_clusters));
+
+ if (!a6xx_state->dbgahb_clusters)
+ return;
+
+ a6xx_state->nr_dbgahb_clusters = dbgahb_clusters_size;
+
+ for (i = 0; i < dbgahb_clusters_size; i++)
+ a7xx_get_dbgahb_cluster(gpu, a6xx_state,
+ &dbgahb_clusters[i],
+ &a6xx_state->dbgahb_clusters[i], dumper);
+}
+
/* Read a data cluster from the CP aperture with the crashdumper */
static void a6xx_get_cluster(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
datasize);
}
+static void a7xx_get_cluster(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const struct gen7_cluster_registers *cluster,
+ struct a6xx_gpu_state_obj *obj,
+ struct a6xx_crashdumper *dumper)
+{
+ u64 *in = dumper->ptr;
+ u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
+ size_t datasize;
+ int i, regcount = 0;
+
+ /* Some clusters need a selector register to be programmed too */
+ if (cluster->sel)
+ in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
+
+ in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD,
+ A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) |
+ A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) |
+ A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id));
+
+ for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) {
+ int count = RANGE(cluster->regs, i);
+
+ in += CRASHDUMP_READ(in, cluster->regs[i],
+ count, out);
+
+ out += count * sizeof(u32);
+ regcount += count;
+ }
+
+ CRASHDUMP_FINI(in);
+
+ datasize = regcount * sizeof(u32);
+
+ if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
+ return;
+
+ if (a6xx_crashdumper_run(gpu, dumper))
+ return;
+
+ obj->handle = cluster;
+ obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
+ datasize);
+}
+
static void a6xx_get_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
&a6xx_state->clusters[i], dumper);
}
+static void a7xx_get_clusters(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_crashdumper *dumper)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ int i;
+ const struct gen7_cluster_registers *clusters;
+ unsigned clusters_size;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ clusters = gen7_0_0_clusters;
+ clusters_size = ARRAY_SIZE(gen7_0_0_clusters);
+ } else {
+ BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ clusters = gen7_2_0_clusters;
+ clusters_size = ARRAY_SIZE(gen7_2_0_clusters);
+ }
+
+ a6xx_state->clusters = state_kcalloc(a6xx_state,
+ clusters_size, sizeof(*a6xx_state->clusters));
+
+ if (!a6xx_state->clusters)
+ return;
+
+ a6xx_state->nr_clusters = clusters_size;
+
+ for (i = 0; i < clusters_size; i++)
+ a7xx_get_cluster(gpu, a6xx_state, &clusters[i],
+ &a6xx_state->clusters[i], dumper);
+}
+
/* Read a shader / debug block from the HLSQ aperture with the crashdumper */
static void a6xx_get_shader_block(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
u64 *in = dumper->ptr;
+ u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
size_t datasize = block->size * A6XX_NUM_SHADER_BANKS * sizeof(u32);
int i;
in += CRASHDUMP_READ(in, REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE,
block->size, dumper->iova + A6XX_CD_DATA_OFFSET);
+
+ out += block->size * sizeof(u32);
}
CRASHDUMP_FINI(in);
datasize);
}
+static void a7xx_get_shader_block(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const struct gen7_shader_block *block,
+ struct a6xx_gpu_state_obj *obj,
+ struct a6xx_crashdumper *dumper)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ u64 *in = dumper->ptr;
+ u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
+ size_t datasize = block->size * block->num_sps * block->num_usptps * sizeof(u32);
+ int i, j;
+
+ if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
+ return;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3);
+ }
+
+ for (i = 0; i < block->num_sps; i++) {
+ for (j = 0; j < block->num_usptps; j++) {
+ in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL,
+ A7XX_SP_READ_SEL_LOCATION(block->location) |
+ A7XX_SP_READ_SEL_PIPE(block->pipeid) |
+ A7XX_SP_READ_SEL_STATETYPE(block->statetype) |
+ A7XX_SP_READ_SEL_USPTP(j) |
+ A7XX_SP_READ_SEL_SPTP(i));
+
+ in += CRASHDUMP_READ(in, REG_A7XX_SP_AHB_READ_APERTURE,
+ block->size, out);
+
+ out += block->size * sizeof(u32);
+ }
+ }
+
+ CRASHDUMP_FINI(in);
+
+ if (a6xx_crashdumper_run(gpu, dumper))
+ goto out;
+
+ obj->handle = block;
+ obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
+ datasize);
+
+out:
+ if (adreno_is_a730(adreno_gpu)) {
+ gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0);
+ }
+}
+
static void a6xx_get_shaders(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
&a6xx_state->shaders[i], dumper);
}
+static void a7xx_get_shaders(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_crashdumper *dumper)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ const struct gen7_shader_block *shader_blocks;
+ unsigned num_shader_blocks;
+ int i;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ shader_blocks = gen7_0_0_shader_blocks;
+ num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks);
+ } else {
+ BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ shader_blocks = gen7_2_0_shader_blocks;
+ num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks);
+ }
+
+ a6xx_state->shaders = state_kcalloc(a6xx_state,
+ num_shader_blocks, sizeof(*a6xx_state->shaders));
+
+ if (!a6xx_state->shaders)
+ return;
+
+ a6xx_state->nr_shaders = num_shader_blocks;
+
+ for (i = 0; i < num_shader_blocks; i++)
+ a7xx_get_shader_block(gpu, a6xx_state, &shader_blocks[i],
+ &a6xx_state->shaders[i], dumper);
+}
+
/* Read registers from behind the HLSQ aperture with the crashdumper */
static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
regcount * sizeof(u32));
}
+static void a7xx_get_crashdumper_registers(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const struct gen7_reg_list *regs,
+ struct a6xx_gpu_state_obj *obj,
+ struct a6xx_crashdumper *dumper)
+
+{
+ u64 *in = dumper->ptr;
+ u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
+ int i, regcount = 0;
+
+ /* Some blocks might need to program a selector register first */
+ if (regs->sel)
+ in += CRASHDUMP_WRITE(in, regs->sel->cd_reg, regs->sel->val);
+
+ for (i = 0; regs->regs[i] != UINT_MAX; i += 2) {
+ u32 count = RANGE(regs->regs, i);
+
+ in += CRASHDUMP_READ(in, regs->regs[i], count, out);
+
+ out += count * sizeof(u32);
+ regcount += count;
+ }
+
+ CRASHDUMP_FINI(in);
+
+ if (WARN_ON((regcount * sizeof(u32)) > A6XX_CD_DATA_SIZE))
+ return;
+
+ if (a6xx_crashdumper_run(gpu, dumper))
+ return;
+
+ obj->handle = regs->regs;
+ obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
+ regcount * sizeof(u32));
+}
+
+
/* Read a block of registers via AHB */
static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
}
}
+static void a7xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const u32 *regs,
+ struct a6xx_gpu_state_obj *obj)
+{
+ int i, regcount = 0, index = 0;
+
+ for (i = 0; regs[i] != UINT_MAX; i += 2)
+ regcount += RANGE(regs, i);
+
+ obj->handle = (const void *) regs;
+ obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32));
+ if (!obj->data)
+ return;
+
+ for (i = 0; regs[i] != UINT_MAX; i += 2) {
+ u32 count = RANGE(regs, i);
+ int j;
+
+ for (j = 0; j < count; j++)
+ obj->data[index++] = gpu_read(gpu, regs[i] + j);
+ }
+}
+
+static void a7xx_get_ahb_gpu_reglist(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ const struct gen7_reg_list *regs,
+ struct a6xx_gpu_state_obj *obj)
+{
+ if (regs->sel)
+ gpu_write(gpu, regs->sel->host_reg, regs->sel->val);
+
+ a7xx_get_ahb_gpu_registers(gpu, a6xx_state, regs->regs, obj);
+}
+
/* Read a block of GMU registers */
static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
a6xx_state->nr_registers = count;
- if (adreno_is_a7xx(adreno_gpu))
- a6xx_get_ahb_gpu_registers(gpu,
- a6xx_state, &a7xx_ahb_reglist,
- &a6xx_state->registers[index++]);
- else
- a6xx_get_ahb_gpu_registers(gpu,
- a6xx_state, &a6xx_ahb_reglist,
- &a6xx_state->registers[index++]);
+ a6xx_get_ahb_gpu_registers(gpu,
+ a6xx_state, &a6xx_ahb_reglist,
+ &a6xx_state->registers[index++]);
- if (adreno_is_a7xx(adreno_gpu))
- a6xx_get_ahb_gpu_registers(gpu,
- a6xx_state, &a7xx_gbif_reglist,
- &a6xx_state->registers[index++]);
- else if (a6xx_has_gbif(adreno_gpu))
+ if (a6xx_has_gbif(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_gbif_reglist,
&a6xx_state->registers[index++]);
dumper);
}
+#define A7XX_PRE_CRASHDUMPER_SIZE 1
+#define A7XX_POST_CRASHDUMPER_SIZE 1
+static void a7xx_get_registers(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_crashdumper *dumper)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ int i, count;
+ int index = 0;
+ const u32 *pre_crashdumper_regs;
+ const struct gen7_reg_list *reglist;
+
+ if (adreno_is_a730(adreno_gpu)) {
+ reglist = gen7_0_0_reg_list;
+ pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
+ } else {
+ BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ reglist = gen7_2_0_reg_list;
+ pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
+ }
+
+ count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE;
+
+ /* The downstream reglist contains registers in other memory regions
+ * (cx_misc/cx_mem and cx_dbgc) and we need to plumb through their
+ * offsets and map them to read them on the CPU. For now only read the
+ * first region which is the main one.
+ */
+ if (dumper) {
+ for (i = 0; reglist[i].regs; i++)
+ count++;
+ } else {
+ count++;
+ }
+
+ a6xx_state->registers = state_kcalloc(a6xx_state,
+ count, sizeof(*a6xx_state->registers));
+
+ if (!a6xx_state->registers)
+ return;
+
+ a6xx_state->nr_registers = count;
+
+ a7xx_get_ahb_gpu_registers(gpu, a6xx_state, pre_crashdumper_regs,
+ &a6xx_state->registers[index++]);
+
+ if (!dumper) {
+ a7xx_get_ahb_gpu_reglist(gpu,
+ a6xx_state, ®list[0],
+ &a6xx_state->registers[index++]);
+ return;
+ }
+
+ for (i = 0; reglist[i].regs; i++)
+ a7xx_get_crashdumper_registers(gpu,
+ a6xx_state, ®list[i],
+ &a6xx_state->registers[index++],
+ dumper);
+}
+
+static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ const u32 *regs;
+
+ BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
+ regs = gen7_0_0_post_crashdumper_registers;
+
+ a7xx_get_ahb_gpu_registers(gpu,
+ a6xx_state, regs,
+ &a6xx_state->registers[a6xx_state->nr_registers - 1]);
+}
+
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
{
/* The value at [16:31] is in 4dword units. Convert it to dwords */
static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i, indexed_count, mempool_count;
+ BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
/* Get the contents of the CP_BV mempool */
for (i = 0; i < mempool_count; i++)
- a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed,
- &a6xx_state->indexed_regs[indexed_count - 1 + i]);
+ a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_cp_bv_mempool_indexed[i],
+ &a6xx_state->indexed_regs[indexed_count + i]);
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
return &a6xx_state->base;
/* Get the banks of indexed registers */
- if (adreno_is_a7xx(adreno_gpu)) {
+ if (adreno_is_a7xx(adreno_gpu))
a7xx_get_indexed_registers(gpu, a6xx_state);
- /* Further codeflow is untested on A7xx. */
- return &a6xx_state->base;
- }
-
- a6xx_get_indexed_registers(gpu, a6xx_state);
+ else
+ a6xx_get_indexed_registers(gpu, a6xx_state);
/*
* Try to initialize the crashdumper, if we are not dumping state
dumper = &_dumper;
}
- a6xx_get_registers(gpu, a6xx_state, dumper);
+ if (adreno_is_a7xx(adreno_gpu)) {
+ a7xx_get_registers(gpu, a6xx_state, dumper);
- if (dumper) {
- a6xx_get_shaders(gpu, a6xx_state, dumper);
- a6xx_get_clusters(gpu, a6xx_state, dumper);
- a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
+ if (dumper) {
+ a7xx_get_shaders(gpu, a6xx_state, dumper);
+ a7xx_get_clusters(gpu, a6xx_state, dumper);
+ a7xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
+
+ msm_gem_kernel_put(dumper->bo, gpu->aspace);
+ }
+
+ a7xx_get_post_crashdumper_registers(gpu, a6xx_state);
+ } else {
+ a6xx_get_registers(gpu, a6xx_state, dumper);
- msm_gem_kernel_put(dumper->bo, gpu->aspace);
+ if (dumper) {
+ a6xx_get_shaders(gpu, a6xx_state, dumper);
+ a6xx_get_clusters(gpu, a6xx_state, dumper);
+ a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
+
+ msm_gem_kernel_put(dumper->bo, gpu->aspace);
+ }
}
if (snapshot_debugbus)
}
}
+static void a7xx_show_registers_indented(const u32 *registers, u32 *data,
+ struct drm_printer *p, unsigned indent)
+{
+ int i, index = 0;
+
+ for (i = 0; registers[i] != UINT_MAX; i += 2) {
+ u32 count = RANGE(registers, i);
+ u32 offset = registers[i];
+ int j;
+
+ for (j = 0; j < count; index++, offset++, j++) {
+ int k;
+
+ if (data[index] == 0xdeafbead)
+ continue;
+
+ for (k = 0; k < indent; k++)
+ drm_printf(p, " ");
+ drm_printf(p, "- { offset: 0x%06x, value: 0x%08x }\n",
+ offset << 2, data[index]);
+ }
+ }
+}
+
+static void a7xx_show_registers(const u32 *registers, u32 *data, struct drm_printer *p)
+{
+ a7xx_show_registers_indented(registers, data, p, 1);
+}
+
static void print_ascii85(struct drm_printer *p, size_t len, u32 *data)
{
char out[ASCII85_BUFSZ];
}
}
+static void a7xx_show_shader(struct a6xx_gpu_state_obj *obj,
+ struct drm_printer *p)
+{
+ const struct gen7_shader_block *block = obj->handle;
+ int i, j;
+ u32 *data = obj->data;
+
+ if (!obj->handle)
+ return;
+
+ print_name(p, " - type: ", a7xx_statetype_names[block->statetype]);
+ print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]);
+
+ for (i = 0; i < block->num_sps; i++) {
+ drm_printf(p, " - sp: %d\n", i);
+
+ for (j = 0; j < block->num_usptps; j++) {
+ drm_printf(p, " - usptp: %d\n", j);
+ drm_printf(p, " size: %d\n", block->size);
+
+ if (!obj->data)
+ continue;
+
+ print_ascii85(p, block->size << 2, data);
+
+ data += block->size;
+ }
+ }
+}
+
static void a6xx_show_cluster_data(const u32 *registers, int size, u32 *data,
struct drm_printer *p)
{
}
}
+static void a7xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj,
+ struct drm_printer *p)
+{
+ const struct gen7_sptp_cluster_registers *dbgahb = obj->handle;
+
+ if (dbgahb) {
+ print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]);
+ print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]);
+ drm_printf(p, " - context: %d\n", dbgahb->context_id);
+ a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4);
+ }
+}
+
+static void a7xx_show_cluster(struct a6xx_gpu_state_obj *obj,
+ struct drm_printer *p)
+{
+ const struct gen7_cluster_registers *cluster = obj->handle;
+
+ if (cluster) {
+ int context = (cluster->context_id == STATE_FORCE_CTXT_1) ? 1 : 0;
+
+ print_name(p, " - pipe: ", a7xx_pipe_names[cluster->pipe_id]);
+ print_name(p, " - cluster-name: ", a7xx_cluster_names[cluster->cluster_id]);
+ drm_printf(p, " - context: %d\n", context);
+ a7xx_show_registers_indented(cluster->regs, obj->data, p, 4);
+ }
+}
+
static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj,
struct drm_printer *p)
{
void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
struct drm_printer *p)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu_state *a6xx_state = container_of(state,
struct a6xx_gpu_state, base);
int i;
drm_puts(p, "registers:\n");
for (i = 0; i < a6xx_state->nr_registers; i++) {
struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i];
- const struct a6xx_registers *regs = obj->handle;
if (!obj->handle)
continue;
- a6xx_show_registers(regs->registers, obj->data, regs->count, p);
+ if (adreno_is_a7xx(adreno_gpu)) {
+ a7xx_show_registers(obj->handle, obj->data, p);
+ } else {
+ const struct a6xx_registers *regs = obj->handle;
+
+ a6xx_show_registers(regs->registers, obj->data, regs->count, p);
+ }
}
drm_puts(p, "registers-gmu:\n");
a6xx_show_indexed_regs(&a6xx_state->indexed_regs[i], p);
drm_puts(p, "shader-blocks:\n");
- for (i = 0; i < a6xx_state->nr_shaders; i++)
- a6xx_show_shader(&a6xx_state->shaders[i], p);
+ for (i = 0; i < a6xx_state->nr_shaders; i++) {
+ if (adreno_is_a7xx(adreno_gpu))
+ a7xx_show_shader(&a6xx_state->shaders[i], p);
+ else
+ a6xx_show_shader(&a6xx_state->shaders[i], p);
+ }
drm_puts(p, "clusters:\n");
- for (i = 0; i < a6xx_state->nr_clusters; i++)
- a6xx_show_cluster(&a6xx_state->clusters[i], p);
+ for (i = 0; i < a6xx_state->nr_clusters; i++) {
+ if (adreno_is_a7xx(adreno_gpu))
+ a7xx_show_cluster(&a6xx_state->clusters[i], p);
+ else
+ a6xx_show_cluster(&a6xx_state->clusters[i], p);
+ }
- for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++)
- a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
+ for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) {
+ if (adreno_is_a7xx(adreno_gpu))
+ a7xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
+ else
+ a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
+ }
drm_puts(p, "debugbus:\n");
a6xx_show_debugbus(a6xx_state, p);
// SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
#ifndef _A6XX_CRASH_DUMP_H_
#define _A6XX_CRASH_DUMP_H_
#define CLUSTER_SP_PS 4
#define CLUSTER_PS 5
#define CLUSTER_VPC_PS 6
+#define CLUSTER_NONE 7
#define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
{ .id = _id, .name = #_id,\
static const struct a6xx_registers a6xx_gbif_reglist =
REGS(a6xx_gbif_registers, 0, 0);
-static const u32 a7xx_ahb_registers[] = {
- /* RBBM_STATUS */
- 0x210, 0x210,
- /* RBBM_STATUS2-3 */
- 0x212, 0x213,
-};
-
-static const u32 a7xx_gbif_registers[] = {
- 0x3c00, 0x3c0b,
- 0x3c40, 0x3c42,
- 0x3c45, 0x3c47,
- 0x3c49, 0x3c4a,
- 0x3cc0, 0x3cd1,
-};
-
-static const struct a6xx_registers a7xx_ahb_reglist=
- REGS(a7xx_ahb_registers, 0, 0);
-
-static const struct a6xx_registers a7xx_gbif_reglist =
- REGS(a7xx_gbif_registers, 0, 0);
-
static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
};
+static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = {
+ DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
+ DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100),
+};
+
+static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {
+ DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100),
+ DEBUGBUS(A7XX_DBGBUS_CX, 0x100),
+ DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
+};
+
+#define STATE_NON_CONTEXT 0
+#define STATE_TOGGLE_CTXT 1
+#define STATE_FORCE_CTXT_0 2
+#define STATE_FORCE_CTXT_1 3
+
+struct gen7_sel_reg {
+ unsigned int host_reg;
+ unsigned int cd_reg;
+ unsigned int val;
+};
+
+struct gen7_cluster_registers {
+ /* cluster_id: Cluster identifier */
+ int cluster_id;
+ /* pipe_id: Pipe Identifier */
+ int pipe_id;
+ /* context_id: one of STATE_ that identifies the context to dump */
+ int context_id;
+ /* regs: Pointer to an array of register pairs */
+ const u32 *regs;
+ /* sel: Pointer to a selector register to write before reading */
+ const struct gen7_sel_reg *sel;
+};
+
+struct gen7_sptp_cluster_registers {
+ /* cluster_id: Cluster identifier */
+ enum a7xx_cluster cluster_id;
+ /* statetype: SP block state type for the cluster */
+ enum a7xx_statetype_id statetype;
+ /* pipe_id: Pipe identifier */
+ enum a7xx_pipe pipe_id;
+ /* context_id: Context identifier */
+ int context_id;
+ /* location_id: Location identifier */
+ enum a7xx_state_location location_id;
+ /* regs: Pointer to the list of register pairs to read */
+ const u32 *regs;
+ /* regbase: Dword offset of the register block in the GPu register space */
+ unsigned int regbase;
+};
+
+struct gen7_shader_block {
+ /* statetype: Type identifer for the block */
+ u32 statetype;
+ /* size: Size of the block (in dwords) */
+ u32 size;
+ /* num_sps: The SP id to dump */
+ u32 num_sps;
+ /* num_usptps: The number of USPTPs to dump */;
+ u32 num_usptps;
+ /* pipe_id: Pipe identifier for the block data */
+ u32 pipeid;
+ /* location: Location identifer for the block data */
+ u32 location;
+};
+
+struct gen7_reg_list {
+ const u32 *regs;
+ const struct gen7_sel_reg *sel;
+};
+
+/* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the
+ * list of debugbus blocks is global on a7xx.
+ */
+
+#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count },
+static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = {
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100)
+ A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100)
+};
+
+#define A7XX_NAME(enumval) [enumval] = #enumval
+static const char *a7xx_statetype_names[] = {
+ A7XX_NAME(A7XX_TP0_NCTX_REG),
+ A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG),
+ A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG),
+ A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG),
+ A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG),
+ A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG),
+ A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG),
+ A7XX_NAME(A7XX_TP0_TMO_DATA),
+ A7XX_NAME(A7XX_TP0_SMO_DATA),
+ A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA),
+ A7XX_NAME(A7XX_SP_NCTX_REG),
+ A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG),
+ A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG),
+ A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG),
+ A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG),
+ A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG),
+ A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG),
+ A7XX_NAME(A7XX_SP_INST_DATA),
+ A7XX_NAME(A7XX_SP_INST_DATA_1),
+ A7XX_NAME(A7XX_SP_LB_0_DATA),
+ A7XX_NAME(A7XX_SP_LB_1_DATA),
+ A7XX_NAME(A7XX_SP_LB_2_DATA),
+ A7XX_NAME(A7XX_SP_LB_3_DATA),
+ A7XX_NAME(A7XX_SP_LB_4_DATA),
+ A7XX_NAME(A7XX_SP_LB_5_DATA),
+ A7XX_NAME(A7XX_SP_LB_6_DATA),
+ A7XX_NAME(A7XX_SP_LB_7_DATA),
+ A7XX_NAME(A7XX_SP_CB_RAM),
+ A7XX_NAME(A7XX_SP_LB_13_DATA),
+ A7XX_NAME(A7XX_SP_LB_14_DATA),
+ A7XX_NAME(A7XX_SP_INST_TAG),
+ A7XX_NAME(A7XX_SP_INST_DATA_2),
+ A7XX_NAME(A7XX_SP_TMO_TAG),
+ A7XX_NAME(A7XX_SP_SMO_TAG),
+ A7XX_NAME(A7XX_SP_STATE_DATA),
+ A7XX_NAME(A7XX_SP_HWAVE_RAM),
+ A7XX_NAME(A7XX_SP_L0_INST_BUF),
+ A7XX_NAME(A7XX_SP_LB_8_DATA),
+ A7XX_NAME(A7XX_SP_LB_9_DATA),
+ A7XX_NAME(A7XX_SP_LB_10_DATA),
+ A7XX_NAME(A7XX_SP_LB_11_DATA),
+ A7XX_NAME(A7XX_SP_LB_12_DATA),
+ A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META),
+ A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM),
+ A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD),
+ A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM),
+ A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM),
+ A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM),
+ A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM),
+ A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG),
+ A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG),
+ A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM),
+ A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM),
+ A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1),
+ A7XX_NAME(A7XX_HLSQ_INST_RAM),
+ A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM),
+ A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM),
+ A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM),
+ A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG),
+ A7XX_NAME(A7XX_HLSQ_INST_RAM_1),
+ A7XX_NAME(A7XX_HLSQ_STPROC_META),
+ A7XX_NAME(A7XX_HLSQ_BV_BE_META),
+ A7XX_NAME(A7XX_HLSQ_INST_RAM_2),
+ A7XX_NAME(A7XX_HLSQ_DATAPATH_META),
+ A7XX_NAME(A7XX_HLSQ_FRONTEND_META),
+ A7XX_NAME(A7XX_HLSQ_INDIRECT_META),
+ A7XX_NAME(A7XX_HLSQ_BACKEND_META),
+};
+
+static const char *a7xx_pipe_names[] = {
+ A7XX_NAME(A7XX_PIPE_NONE),
+ A7XX_NAME(A7XX_PIPE_BR),
+ A7XX_NAME(A7XX_PIPE_BV),
+ A7XX_NAME(A7XX_PIPE_LPAC),
+};
+
+static const char *a7xx_cluster_names[] = {
+ A7XX_NAME(A7XX_CLUSTER_NONE),
+ A7XX_NAME(A7XX_CLUSTER_FE),
+ A7XX_NAME(A7XX_CLUSTER_SP_VS),
+ A7XX_NAME(A7XX_CLUSTER_PC_VS),
+ A7XX_NAME(A7XX_CLUSTER_GRAS),
+ A7XX_NAME(A7XX_CLUSTER_SP_PS),
+ A7XX_NAME(A7XX_CLUSTER_VPC_PS),
+ A7XX_NAME(A7XX_CLUSTER_PS),
+};
+
#endif
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum chip {
A2XX = 2,
ROP_COPY_INVERTED = 3,
ROP_AND_REVERSE = 4,
ROP_INVERT = 5,
+ ROP_XOR = 6,
ROP_NAND = 7,
ROP_AND = 8,
ROP_EQUIV = 9,
ROP_NOOP = 10,
ROP_OR_INVERTED = 11,
+ ROP_COPY = 12,
ROP_OR_REVERSE = 13,
ROP_OR = 14,
ROP_SET = 15,
#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
{
- return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
}
#define REG_AXXX_CP_RB_RPTR 0x000001c4
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
#define REG_AXXX_CP_STAT 0x0000047f
-#define AXXX_CP_STAT_CP_BUSY__MASK 0x80000000
-#define AXXX_CP_STAT_CP_BUSY__SHIFT 31
-static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK 0x40000000
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT 30
-static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK 0x20000000
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT 29
-static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK 0x10000000
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT 28
-static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK 0x08000000
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT 27
-static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_ME_BUSY__MASK 0x04000000
-#define AXXX_CP_STAT_ME_BUSY__SHIFT 26
-static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK 0x02000000
-#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT 25
-static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CP_3D_BUSY__MASK 0x00800000
-#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT 23
-static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CP_NRT_BUSY__MASK 0x00400000
-#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT 22
-static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK 0x00200000
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT 21
-static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK 0x00100000
-#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT 20
-static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK 0x00080000
-#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT 19
-static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK 0x00040000
-#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT 18
-static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK;
-}
-#define AXXX_CP_STAT_PFP_BUSY__MASK 0x00020000
-#define AXXX_CP_STAT_PFP_BUSY__SHIFT 17
-static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK 0x00010000
-#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT 16
-static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK 0x00002000
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT 13
-static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK 0x00001000
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT 12
-static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK 0x00000800
-#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT 11
-static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_BUSY__MASK 0x00000400
-#define AXXX_CP_STAT_CSF_BUSY__SHIFT 10
-static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_ST_BUSY__MASK 0x00000200
-#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT 9
-static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK;
-}
-#define AXXX_CP_STAT_EVENT_BUSY__MASK 0x00000100
-#define AXXX_CP_STAT_EVENT_BUSY__SHIFT 8
-static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK 0x00000080
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT 7
-static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK 0x00000040
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT 6
-static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_RING_BUSY__MASK 0x00000020
-#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT 5
-static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_BUSY__MASK 0x00000010
-#define AXXX_CP_STAT_RCIU_BUSY__SHIFT 4
-static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RBIU_BUSY__MASK 0x00000008
-#define AXXX_CP_STAT_RBIU_BUSY__SHIFT 3
-static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK 0x00000004
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT 2
-static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK 0x00000002
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT 1
-static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
-{
- return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK;
-}
+#define AXXX_CP_STAT_CP_BUSY 0x80000000
+#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
+#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
+#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
+#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
+#define AXXX_CP_STAT_ME_BUSY 0x04000000
+#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
+#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
+#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
+#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
+#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
+#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
+#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
+#define AXXX_CP_STAT_PFP_BUSY 0x00020000
+#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
+#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
+#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
+#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
+#define AXXX_CP_STAT_CSF_BUSY 0x00000400
+#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
+#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
+#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
+#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
+#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
+#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
+#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
+#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
+#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
+#ifdef __cplusplus
+#endif
#endif /* ADRENO_COMMON_XML */
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03000512,
- 0x03000520
- ),
+ .chip_ids = ADRENO_CHIP_IDS(0x03000512),
+ .family = ADRENO_3XX,
+ .fw = {
+ [ADRENO_FW_PM4] = "a330_pm4.fw",
+ [ADRENO_FW_PFP] = "a330_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000520),
.family = ADRENO_3XX,
.revn = 305,
.fw = {
{ 157, 3 },
{ 127, 4 },
),
+ }, {
+ .machine = "qcom,sm7150",
+ .chip_ids = ADRENO_CHIP_IDS(0x06010800),
+ .family = ADRENO_6XX_GEN1,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a630_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mbn",
+ .hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 128, 1 },
+ { 146, 2 },
+ { 167, 3 },
+ { 172, 4 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06010800),
.family = ADRENO_6XX_GEN1,
.zapfw = "a690_zap.mdt",
.hwcg = a690_hwcg,
.address_space_size = SZ_16G,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x07000200),
+ .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
+ .fw = {
+ [ADRENO_FW_SQE] = "a702_sqe.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a702_zap.mbn",
+ .hwcg = a702_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 236, 1 },
+ { 178, 2 },
+ { 142, 3 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
.family = ADRENO_7XX_GEN1,
.zapfw = "a740_zap.mdt",
.hwcg = a740_hwcg,
.address_space_size = SZ_16G,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
+ .family = ADRENO_7XX_GEN3,
+ .fw = {
+ [ADRENO_FW_SQE] = "gen70900_sqe.fw",
+ [ADRENO_FW_GMU] = "gmu_gen70900.bin",
+ },
+ .gmem = 3 * SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "gen70900_zap.mbn",
+ .address_space_size = SZ_16G,
},
};
MODULE_FIRMWARE("qcom/a530_zap.b01");
MODULE_FIRMWARE("qcom/a530_zap.b02");
MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
+MODULE_FIRMWARE("qcom/a615_zap.mbn");
MODULE_FIRMWARE("qcom/a619_gmu.bin");
MODULE_FIRMWARE("qcom/a630_sqe.fw");
MODULE_FIRMWARE("qcom/a630_gmu.bin");
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef __ADRENO_GEN7_0_0_SNAPSHOT_H
+#define __ADRENO_GEN7_0_0_SNAPSHOT_H
+
+#include "a6xx_gpu_state.h"
+
+static const u32 gen7_0_0_debugbus_blocks[] = {
+ A7XX_DBGBUS_CP_0_0,
+ A7XX_DBGBUS_CP_0_1,
+ A7XX_DBGBUS_RBBM,
+ A7XX_DBGBUS_HLSQ,
+ A7XX_DBGBUS_UCHE_0,
+ A7XX_DBGBUS_TESS_BR,
+ A7XX_DBGBUS_TESS_BV,
+ A7XX_DBGBUS_PC_BR,
+ A7XX_DBGBUS_PC_BV,
+ A7XX_DBGBUS_VFDP_BR,
+ A7XX_DBGBUS_VFDP_BV,
+ A7XX_DBGBUS_VPC_BR,
+ A7XX_DBGBUS_VPC_BV,
+ A7XX_DBGBUS_TSE_BR,
+ A7XX_DBGBUS_TSE_BV,
+ A7XX_DBGBUS_RAS_BR,
+ A7XX_DBGBUS_RAS_BV,
+ A7XX_DBGBUS_VSC,
+ A7XX_DBGBUS_COM_0,
+ A7XX_DBGBUS_LRZ_BR,
+ A7XX_DBGBUS_LRZ_BV,
+ A7XX_DBGBUS_UFC_0,
+ A7XX_DBGBUS_UFC_1,
+ A7XX_DBGBUS_GMU_GX,
+ A7XX_DBGBUS_DBGC,
+ A7XX_DBGBUS_GPC_BR,
+ A7XX_DBGBUS_GPC_BV,
+ A7XX_DBGBUS_LARC,
+ A7XX_DBGBUS_HLSQ_SPTP,
+ A7XX_DBGBUS_RB_0,
+ A7XX_DBGBUS_RB_1,
+ A7XX_DBGBUS_RB_2,
+ A7XX_DBGBUS_RB_3,
+ A7XX_DBGBUS_UCHE_WRAPPER,
+ A7XX_DBGBUS_CCU_0,
+ A7XX_DBGBUS_CCU_1,
+ A7XX_DBGBUS_CCU_2,
+ A7XX_DBGBUS_CCU_3,
+ A7XX_DBGBUS_VFD_BR_0,
+ A7XX_DBGBUS_VFD_BR_1,
+ A7XX_DBGBUS_VFD_BR_2,
+ A7XX_DBGBUS_VFD_BR_3,
+ A7XX_DBGBUS_VFD_BR_4,
+ A7XX_DBGBUS_VFD_BR_5,
+ A7XX_DBGBUS_VFD_BR_6,
+ A7XX_DBGBUS_VFD_BR_7,
+ A7XX_DBGBUS_VFD_BV_0,
+ A7XX_DBGBUS_VFD_BV_1,
+ A7XX_DBGBUS_VFD_BV_2,
+ A7XX_DBGBUS_VFD_BV_3,
+ A7XX_DBGBUS_USP_0,
+ A7XX_DBGBUS_USP_1,
+ A7XX_DBGBUS_USP_2,
+ A7XX_DBGBUS_USP_3,
+ A7XX_DBGBUS_TP_0,
+ A7XX_DBGBUS_TP_1,
+ A7XX_DBGBUS_TP_2,
+ A7XX_DBGBUS_TP_3,
+ A7XX_DBGBUS_TP_4,
+ A7XX_DBGBUS_TP_5,
+ A7XX_DBGBUS_TP_6,
+ A7XX_DBGBUS_TP_7,
+ A7XX_DBGBUS_USPTP_0,
+ A7XX_DBGBUS_USPTP_1,
+ A7XX_DBGBUS_USPTP_2,
+ A7XX_DBGBUS_USPTP_3,
+ A7XX_DBGBUS_USPTP_4,
+ A7XX_DBGBUS_USPTP_5,
+ A7XX_DBGBUS_USPTP_6,
+ A7XX_DBGBUS_USPTP_7,
+};
+
+static struct gen7_shader_block gen7_0_0_shader_blocks[] = {
+ {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_5_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_6_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_7_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_CB_RAM, 0x390, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_TAG, 0x90, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA_2, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_TMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_SMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_STATE_DATA, 0x40, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_HWAVE_RAM, 0x100, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_L0_INST_BUF, 0x50, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_8_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_9_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_10_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_11_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_12_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+};
+
+static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] = {
+ 0x00210, 0x00210, 0x00212, 0x00213, 0x03c00, 0x03c0b, 0x03c40, 0x03c42,
+ 0x03c45, 0x03c47, 0x03c49, 0x03c4a, 0x03cc0, 0x03cd1,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_pre_crashdumper_gpu_registers), 8));
+
+static const u32 gen7_0_0_post_crashdumper_registers[] = {
+ 0x00535, 0x00535, 0x0f400, 0x0f400, 0x0f800, 0x0f803, 0x0fc00, 0x0fc01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_post_crashdumper_registers), 8));
+
+static const u32 gen7_0_0_gpu_registers[] = {
+ 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b,
+ 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044,
+ 0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050,
+ 0x00056, 0x00056, 0x00073, 0x00075, 0x000ad, 0x000ae, 0x000b0, 0x000b0,
+ 0x000b4, 0x000b4, 0x000b8, 0x000b8, 0x000bc, 0x000bc, 0x000c0, 0x000c0,
+ 0x000c4, 0x000c4, 0x000c8, 0x000c8, 0x000cc, 0x000cc, 0x000d0, 0x000d0,
+ 0x000d4, 0x000d4, 0x000d8, 0x000d8, 0x000dc, 0x000dc, 0x000e0, 0x000e0,
+ 0x000e4, 0x000e4, 0x000e8, 0x000e8, 0x000ec, 0x000ec, 0x000f0, 0x000f0,
+ 0x000f4, 0x000f4, 0x000f8, 0x000f8, 0x00100, 0x00100, 0x00104, 0x0010b,
+ 0x0010f, 0x0011d, 0x0012f, 0x0012f, 0x00200, 0x0020d, 0x00211, 0x00211,
+ 0x00215, 0x00243, 0x00260, 0x00268, 0x00272, 0x00274, 0x00281, 0x0028d,
+ 0x00300, 0x00401, 0x00410, 0x00451, 0x00460, 0x004a3, 0x004c0, 0x004d1,
+ 0x00500, 0x00500, 0x00507, 0x0050b, 0x0050f, 0x0050f, 0x00511, 0x00511,
+ 0x00533, 0x00534, 0x00536, 0x00536, 0x00540, 0x00555, 0x00564, 0x00567,
+ 0x00574, 0x00577, 0x005fb, 0x005ff, 0x00800, 0x00808, 0x00810, 0x00813,
+ 0x00820, 0x00821, 0x00823, 0x00827, 0x00830, 0x00834, 0x0083f, 0x00841,
+ 0x00843, 0x00847, 0x0084f, 0x00886, 0x008a0, 0x008ab, 0x008c0, 0x008c0,
+ 0x008c4, 0x008c5, 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3,
+ 0x00900, 0x00903, 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d,
+ 0x00980, 0x00984, 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9,
+ 0x009ce, 0x009d7, 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03,
+ 0x00a10, 0x00a4f, 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31,
+ 0x00b35, 0x00b3c, 0x00b40, 0x00b40, 0x00c00, 0x00c00, 0x00c02, 0x00c04,
+ 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 0x00ce0, 0x00d0c, 0x00df0, 0x00df4,
+ 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 0x00e10, 0x00e13, 0x00e17, 0x00e19,
+ 0x00e1b, 0x00e2b, 0x00e30, 0x00e32, 0x00e38, 0x00e3c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpu_registers), 8));
+
+static const u32 gen7_0_0_gmu_registers[] = {
+ 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
+ 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
+ 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
+ 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
+ 0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
+ 0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
+ 0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
+ 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
+ 0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2,
+ 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
+ 0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f914, 0x1f920, 0x1f921,
+ 0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
+ 0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f958, 0x1f95a,
+ 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f96b, 0x1f970, 0x1f979,
+ 0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e,
+ 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa,
+ 0x1fa00, 0x1fa03, 0x20000, 0x20005, 0x20008, 0x2000c, 0x20010, 0x20012,
+ 0x20018, 0x20018, 0x20020, 0x20023, 0x20030, 0x20031, 0x23801, 0x23801,
+ 0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809,
+ 0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811,
+ 0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819,
+ 0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822,
+ 0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a,
+ 0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832,
+ 0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a,
+ 0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01,
+ 0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16,
+ 0x23b20, 0x23b20, 0x23b28, 0x23b28, 0x23b30, 0x23b30,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmu_registers), 8));
+
+static const u32 gen7_0_0_gmugx_registers[] = {
+ 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df,
+ 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df,
+ 0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789, 0x1a78b, 0x1a78d,
+ 0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799, 0x1a79b, 0x1a79b,
+ 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd,
+ 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd,
+ 0x1a800, 0x1a802, 0x1a804, 0x1a804, 0x1a816, 0x1a816, 0x1a81e, 0x1a81e,
+ 0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836, 0x1a83e, 0x1a83e,
+ 0x1a846, 0x1a846, 0x1a860, 0x1a862, 0x1a864, 0x1a867, 0x1a870, 0x1a870,
+ 0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2, 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3,
+ 0x1a900, 0x1a92b, 0x1a940, 0x1a940,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmugx_registers), 8));
+
+static const u32 gen7_0_0_noncontext_pipe_br_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b,
+ 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640,
+ 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a,
+ 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16,
+ 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31,
+ 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79,
+ 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f,
+ 0x0a630, 0x0a631, 0x0a638, 0x0a638,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_br_registers), 8));
+
+static const u32 gen7_0_0_noncontext_pipe_bv_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b,
+ 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640,
+ 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a,
+ 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16,
+ 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31,
+ 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79,
+ 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f,
+ 0x0a630, 0x0a631, 0x0a638, 0x0a638,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_bv_registers), 8));
+
+static const u32 gen7_0_0_noncontext_pipe_lpac_registers[] = {
+ 0x00887, 0x0088c, 0x00f80, 0x00f80,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_lpac_registers), 8));
+
+static const u32 gen7_0_0_noncontext_rb_rac_pipe_br_registers[] = {
+ 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rac_pipe_br_registers), 8));
+
+static const u32 gen7_0_0_noncontext_rb_rbp_pipe_br_registers[] = {
+ 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c,
+ 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e3f, 0x08e50, 0x08e50,
+ 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e65,
+ 0x08e68, 0x08e68, 0x08e70, 0x08e79, 0x08e80, 0x08e8f,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rbp_pipe_br_registers), 8));
+
+/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = {
+ 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08110, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_br_registers), 8));
+
+/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = {
+ 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08110, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_bv_registers), 8));
+
+/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = {
+ 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
+ 0x09b00, 0x09b08,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_br_registers), 8));
+
+/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = {
+ 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
+ 0x09b00, 0x09b08,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_bv_registers), 8));
+
+/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = {
+ 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811,
+ 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829,
+ 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839,
+ 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849,
+ 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859,
+ 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876,
+ 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891,
+ 0x08898, 0x08898, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5,
+ 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35,
+ 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rac_cluster_ps_pipe_br_registers), 8));
+
+/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = {
+ 0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812,
+ 0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a,
+ 0x0882f, 0x08830, 0x08832, 0x08832, 0x08837, 0x08838, 0x0883a, 0x0883a,
+ 0x0883f, 0x08840, 0x08842, 0x08842, 0x08847, 0x08848, 0x0884a, 0x0884a,
+ 0x0884f, 0x08850, 0x08852, 0x08852, 0x08857, 0x08858, 0x0885a, 0x0885a,
+ 0x0885f, 0x0885f, 0x08865, 0x08865, 0x08871, 0x08872, 0x08877, 0x08877,
+ 0x08880, 0x08881, 0x08886, 0x08886, 0x08890, 0x08890, 0x088d0, 0x088e4,
+ 0x088e8, 0x088ea, 0x088f0, 0x088f0, 0x08900, 0x0891a, 0x08927, 0x08928,
+ 0x08c17, 0x08c17, 0x08c20, 0x08c25,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = {
+ 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7,
+ 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba,
+ 0x0a9bc, 0x0a9bc, 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc,
+ 0x0aa00, 0x0aa00, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab03,
+ 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = {
+ 0x0a9b0, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
+ 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc,
+ 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] = {
+ 0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = {
+ 0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = {
+ 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8,
+ 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5,
+ 0x0a9ba, 0x0a9bc, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00,
+ 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = {
+ 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9e2, 0x0a9e3,
+ 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: uSPTP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = {
+ 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae,
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3,
+ 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf,
+ 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = {
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3,
+ 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a840, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a88c, 0x0a88e,
+ 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 0x0a89a, 0x0a89d,
+ 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a840, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a88c, 0x0a88e,
+ 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 0x0a89a, 0x0a89d,
+ 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b,
+ 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
+ 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
+ 0x0a862, 0x0a864, 0x0a870, 0x0a871, 0x0a88d, 0x0a88e, 0x0a893, 0x0a895,
+ 0x0a8a0, 0x0a8af, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
+ 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
+ 0x0a862, 0x0a864, 0x0a870, 0x0a871, 0x0a88d, 0x0a88e, 0x0a893, 0x0a895,
+ 0x0a8a0, 0x0a8af, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b,
+ 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: uSPTP */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
+ 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
+ 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a898, 0x0a8c0, 0x0a8c3,
+ 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: uSPTP */
+static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
+ 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
+ 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a898, 0x0a8c0, 0x0a8c3,
+ 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8));
+
+/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = {
+ 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307,
+ 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = {
+ 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] = {
+ 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers), 8));
+
+/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: uSPTP */
+static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] = {
+ 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers), 8));
+
+/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] = {
+ 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers), 8));
+
+/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */
+static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = {
+ 0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309,
+ 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers), 8));
+
+/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] = {
+ 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers), 8));
+
+/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] = {
+ 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers), 8));
+
+/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] = {
+ 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_br_registers), 8));
+
+/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] = {
+ 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_bv_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] = {
+ 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_br_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] = {
+ 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_bv_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] = {
+ 0x09101, 0x0910c, 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] = {
+ 0x09101, 0x0910c, 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] = {
+ 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers), 8));
+
+/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */
+static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] = {
+ 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] = {
+ 0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae73,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */
+static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = {
+ 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
+ 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f,
+ 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_sp_top_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */
+static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = {
+ 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
+ 0x0ae0f, 0x0ae0f, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3b,
+ 0x0ae3e, 0x0ae3f, 0x0ae50, 0x0ae52,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_usptp_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
+static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
+ 0x0af88, 0x0af8a,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
+static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] = {
+ 0x0af80, 0x0af84,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers), 8));
+
+/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
+static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = {
+ 0x0af80, 0x0af84, 0x0af90, 0x0af92,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));
+
+/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */
+static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
+ 0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,
+ 0x0b60f, 0x0b621, 0x0b630, 0x0b633,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));
+
+/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */
+static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
+ 0x0b780, 0x0b780,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));
+
+static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0x0,
+};
+
+static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0x9,
+};
+
+static struct gen7_cluster_registers gen7_0_0_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_pipe_br_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_pipe_bv_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_pipe_lpac_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_rb_rac_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_rb_rbp_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_gras_cluster_gras_pipe_br_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_gras_cluster_gras_pipe_br_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_pc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_pc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
+};
+
+static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
+};
+
+static const u32 gen7_0_0_rscc_registers[] = {
+ 0x14000, 0x14036, 0x14040, 0x14042, 0x14080, 0x14084, 0x14089, 0x1408c,
+ 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac,
+ 0x14100, 0x14102, 0x14114, 0x14119, 0x14124, 0x1412e, 0x14140, 0x14143,
+ 0x14180, 0x14197, 0x14340, 0x14342, 0x14344, 0x14347, 0x1434c, 0x14373,
+ 0x143ec, 0x143ef, 0x143f4, 0x1441b, 0x14494, 0x14497, 0x1449c, 0x144c3,
+ 0x1453c, 0x1453f, 0x14544, 0x1456b, 0x145e4, 0x145e7, 0x145ec, 0x14613,
+ 0x1468c, 0x1468f, 0x14694, 0x146bb, 0x14734, 0x14737, 0x1473c, 0x14763,
+ 0x147dc, 0x147df, 0x147e4, 0x1480b, 0x14884, 0x14887, 0x1488c, 0x148b3,
+ 0x1492c, 0x1492f, 0x14934, 0x1495b, 0x14f51, 0x14f54,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_rscc_registers), 8));
+
+static const u32 gen7_0_0_cpr_registers[] = {
+ 0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c,
+ 0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850,
+ 0x26880, 0x26898, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee,
+ 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f,
+ 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274ac,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_cpr_registers), 8));
+
+static const u32 gen7_0_0_gpucc_registers[] = {
+ 0x24000, 0x2400e, 0x24400, 0x2440e, 0x24800, 0x24805, 0x24c00, 0x24cff,
+ 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, 0x26400, 0x26405,
+ 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26432, 0x26441, 0x26455,
+ 0x26466, 0x26468, 0x26478, 0x2647a, 0x26489, 0x2648a, 0x2649c, 0x2649e,
+ 0x264a0, 0x264a3, 0x264b3, 0x264b5, 0x264c5, 0x264c7, 0x264d6, 0x264d8,
+ 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2650b, 0x2650c, 0x2651c, 0x2651e,
+ 0x26540, 0x26570, 0x26600, 0x26616, 0x26620, 0x2662d,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpucc_registers), 8));
+
+static const u32 gen7_0_0_cx_misc_registers[] = {
+ 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27832, 0x27857,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_cx_misc_registers), 8));
+
+static const u32 gen7_0_0_dpm_registers[] = {
+ 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12,
+ 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8));
+
+static struct gen7_reg_list gen7_0_0_reg_list[] = {
+ { gen7_0_0_gpu_registers, NULL },
+ { gen7_0_0_cx_misc_registers, NULL },
+ { gen7_0_0_dpm_registers, NULL },
+ { NULL, NULL },
+};
+
+static const u32 *gen7_0_0_external_core_regs[] = {
+ gen7_0_0_gpucc_registers,
+ gen7_0_0_cpr_registers,
+};
+#endif /*_ADRENO_GEN7_0_0_SNAPSHOT_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef __ADRENO_GEN7_2_0_SNAPSHOT_H
+#define __ADRENO_GEN7_2_0_SNAPSHOT_H
+
+#include "a6xx_gpu_state.h"
+
+static const u32 gen7_2_0_debugbus_blocks[] = {
+ A7XX_DBGBUS_CP_0_0,
+ A7XX_DBGBUS_CP_0_1,
+ A7XX_DBGBUS_RBBM,
+ A7XX_DBGBUS_HLSQ,
+ A7XX_DBGBUS_UCHE_0,
+ A7XX_DBGBUS_UCHE_1,
+ A7XX_DBGBUS_TESS_BR,
+ A7XX_DBGBUS_TESS_BV,
+ A7XX_DBGBUS_PC_BR,
+ A7XX_DBGBUS_PC_BV,
+ A7XX_DBGBUS_VFDP_BR,
+ A7XX_DBGBUS_VFDP_BV,
+ A7XX_DBGBUS_VPC_BR,
+ A7XX_DBGBUS_VPC_BV,
+ A7XX_DBGBUS_TSE_BR,
+ A7XX_DBGBUS_TSE_BV,
+ A7XX_DBGBUS_RAS_BR,
+ A7XX_DBGBUS_RAS_BV,
+ A7XX_DBGBUS_VSC,
+ A7XX_DBGBUS_COM_0,
+ A7XX_DBGBUS_LRZ_BR,
+ A7XX_DBGBUS_LRZ_BV,
+ A7XX_DBGBUS_UFC_0,
+ A7XX_DBGBUS_UFC_1,
+ A7XX_DBGBUS_GMU_GX,
+ A7XX_DBGBUS_DBGC,
+ A7XX_DBGBUS_GPC_BR,
+ A7XX_DBGBUS_GPC_BV,
+ A7XX_DBGBUS_LARC,
+ A7XX_DBGBUS_HLSQ_SPTP,
+ A7XX_DBGBUS_RB_0,
+ A7XX_DBGBUS_RB_1,
+ A7XX_DBGBUS_RB_2,
+ A7XX_DBGBUS_RB_3,
+ A7XX_DBGBUS_RB_4,
+ A7XX_DBGBUS_RB_5,
+ A7XX_DBGBUS_UCHE_WRAPPER,
+ A7XX_DBGBUS_CCU_0,
+ A7XX_DBGBUS_CCU_1,
+ A7XX_DBGBUS_CCU_2,
+ A7XX_DBGBUS_CCU_3,
+ A7XX_DBGBUS_CCU_4,
+ A7XX_DBGBUS_CCU_5,
+ A7XX_DBGBUS_VFD_BR_0,
+ A7XX_DBGBUS_VFD_BR_1,
+ A7XX_DBGBUS_VFD_BR_2,
+ A7XX_DBGBUS_VFD_BR_3,
+ A7XX_DBGBUS_VFD_BR_4,
+ A7XX_DBGBUS_VFD_BR_5,
+ A7XX_DBGBUS_VFD_BV_0,
+ A7XX_DBGBUS_VFD_BV_1,
+ A7XX_DBGBUS_USP_0,
+ A7XX_DBGBUS_USP_1,
+ A7XX_DBGBUS_USP_2,
+ A7XX_DBGBUS_USP_3,
+ A7XX_DBGBUS_USP_4,
+ A7XX_DBGBUS_USP_5,
+ A7XX_DBGBUS_TP_0,
+ A7XX_DBGBUS_TP_1,
+ A7XX_DBGBUS_TP_2,
+ A7XX_DBGBUS_TP_3,
+ A7XX_DBGBUS_TP_4,
+ A7XX_DBGBUS_TP_5,
+ A7XX_DBGBUS_TP_6,
+ A7XX_DBGBUS_TP_7,
+ A7XX_DBGBUS_TP_8,
+ A7XX_DBGBUS_TP_9,
+ A7XX_DBGBUS_TP_10,
+ A7XX_DBGBUS_TP_11,
+ A7XX_DBGBUS_USPTP_0,
+ A7XX_DBGBUS_USPTP_1,
+ A7XX_DBGBUS_USPTP_2,
+ A7XX_DBGBUS_USPTP_3,
+ A7XX_DBGBUS_USPTP_4,
+ A7XX_DBGBUS_USPTP_5,
+ A7XX_DBGBUS_USPTP_6,
+ A7XX_DBGBUS_USPTP_7,
+ A7XX_DBGBUS_USPTP_8,
+ A7XX_DBGBUS_USPTP_9,
+ A7XX_DBGBUS_USPTP_10,
+ A7XX_DBGBUS_USPTP_11,
+ A7XX_DBGBUS_CCHE_0,
+ A7XX_DBGBUS_CCHE_1,
+ A7XX_DBGBUS_CCHE_2,
+};
+
+static struct gen7_shader_block gen7_2_0_shader_blocks[] = {
+ {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_5_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_6_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_7_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_CB_RAM, 0x390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_13_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_14_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_TAG, 0xc0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_INST_DATA_2, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_TMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_SMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_STATE_DATA, 0x40, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_HWAVE_RAM, 0x100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_L0_INST_BUF, 0x50, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_8_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_9_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_10_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_11_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_SP_LB_12_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
+ {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
+ {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
+};
+
+static const u32 gen7_2_0_gpu_registers[] = {
+ 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b,
+ 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044,
+ 0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050,
+ 0x00056, 0x00056, 0x00073, 0x0007d, 0x000ad, 0x000ae, 0x000b0, 0x000b0,
+ 0x000b4, 0x000b4, 0x000b8, 0x000b8, 0x000bc, 0x000bc, 0x000c0, 0x000c0,
+ 0x000c4, 0x000c4, 0x000c8, 0x000c8, 0x000cc, 0x000cc, 0x000d0, 0x000d0,
+ 0x000d4, 0x000d4, 0x000d8, 0x000d8, 0x000dc, 0x000dc, 0x000e0, 0x000e0,
+ 0x000e4, 0x000e4, 0x000e8, 0x000e8, 0x000ec, 0x000ec, 0x000f0, 0x000f0,
+ 0x000f4, 0x000f4, 0x000f8, 0x000f8, 0x00100, 0x00100, 0x00104, 0x0010c,
+ 0x0010f, 0x0011d, 0x0012f, 0x0012f, 0x00200, 0x0020d, 0x00211, 0x00211,
+ 0x00215, 0x00253, 0x00260, 0x00270, 0x00272, 0x00274, 0x00281, 0x0028d,
+ 0x00300, 0x00401, 0x00410, 0x00451, 0x00460, 0x004a3, 0x004c0, 0x004d1,
+ 0x00500, 0x00500, 0x00507, 0x0050b, 0x0050f, 0x0050f, 0x00511, 0x00511,
+ 0x00533, 0x00536, 0x00540, 0x00555, 0x00564, 0x00567, 0x00574, 0x00577,
+ 0x00584, 0x0059b, 0x005fb, 0x005ff, 0x00800, 0x00808, 0x00810, 0x00813,
+ 0x00820, 0x00821, 0x00823, 0x00827, 0x00830, 0x00834, 0x0083f, 0x00841,
+ 0x00843, 0x00847, 0x0084f, 0x00886, 0x008a0, 0x008ab, 0x008c0, 0x008c0,
+ 0x008c4, 0x008c6, 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3,
+ 0x00900, 0x00903, 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d,
+ 0x00980, 0x00984, 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9,
+ 0x009ce, 0x009d7, 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03,
+ 0x00a10, 0x00a4f, 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31,
+ 0x00b35, 0x00b3c, 0x00b40, 0x00b40, 0x00c00, 0x00c00, 0x00c02, 0x00c04,
+ 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 0x00ce0, 0x00d0c, 0x00df0, 0x00df4,
+ 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 0x00e10, 0x00e13, 0x00e17, 0x00e19,
+ 0x00e1b, 0x00e2b, 0x00e30, 0x00e32, 0x00e38, 0x00e3c, 0x00e40, 0x00e4b,
+ 0x0ec00, 0x0ec01, 0x0ec05, 0x0ec05, 0x0ec07, 0x0ec07, 0x0ec0a, 0x0ec0a,
+ 0x0ec12, 0x0ec12, 0x0ec26, 0x0ec28, 0x0ec2b, 0x0ec2d, 0x0ec2f, 0x0ec2f,
+ 0x0ec40, 0x0ec41, 0x0ec45, 0x0ec45, 0x0ec47, 0x0ec47, 0x0ec4a, 0x0ec4a,
+ 0x0ec52, 0x0ec52, 0x0ec66, 0x0ec68, 0x0ec6b, 0x0ec6d, 0x0ec6f, 0x0ec6f,
+ 0x0ec80, 0x0ec81, 0x0ec85, 0x0ec85, 0x0ec87, 0x0ec87, 0x0ec8a, 0x0ec8a,
+ 0x0ec92, 0x0ec92, 0x0eca6, 0x0eca8, 0x0ecab, 0x0ecad, 0x0ecaf, 0x0ecaf,
+ 0x0ecc0, 0x0ecc1, 0x0ecc5, 0x0ecc5, 0x0ecc7, 0x0ecc7, 0x0ecca, 0x0ecca,
+ 0x0ecd2, 0x0ecd2, 0x0ece6, 0x0ece8, 0x0eceb, 0x0eced, 0x0ecef, 0x0ecef,
+ 0x0ed00, 0x0ed01, 0x0ed05, 0x0ed05, 0x0ed07, 0x0ed07, 0x0ed0a, 0x0ed0a,
+ 0x0ed12, 0x0ed12, 0x0ed26, 0x0ed28, 0x0ed2b, 0x0ed2d, 0x0ed2f, 0x0ed2f,
+ 0x0ed40, 0x0ed41, 0x0ed45, 0x0ed45, 0x0ed47, 0x0ed47, 0x0ed4a, 0x0ed4a,
+ 0x0ed52, 0x0ed52, 0x0ed66, 0x0ed68, 0x0ed6b, 0x0ed6d, 0x0ed6f, 0x0ed6f,
+ 0x0ed80, 0x0ed81, 0x0ed85, 0x0ed85, 0x0ed87, 0x0ed87, 0x0ed8a, 0x0ed8a,
+ 0x0ed92, 0x0ed92, 0x0eda6, 0x0eda8, 0x0edab, 0x0edad, 0x0edaf, 0x0edaf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gpu_registers), 8));
+
+static const u32 gen7_2_0_gmu_registers[] = {
+ 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
+ 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
+ 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
+ 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
+ 0x1a79b, 0x1a79b, 0x1a7ac, 0x1a7b9, 0x1a7dc, 0x1a7dd, 0x1a7e0, 0x1a7e1,
+ 0x1a803, 0x1a803, 0x1a805, 0x1a806, 0x1a84e, 0x1a84e, 0x1a856, 0x1a856,
+ 0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
+ 0x1f509, 0x1f50b, 0x1f700, 0x1f701, 0x1f704, 0x1f706, 0x1f708, 0x1f709,
+ 0x1f70c, 0x1f70d, 0x1f710, 0x1f711, 0x1f713, 0x1f716, 0x1f720, 0x1f724,
+ 0x1f729, 0x1f729, 0x1f730, 0x1f747, 0x1f760, 0x1f761, 0x1f764, 0x1f76b,
+ 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f80f,
+ 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c, 0x1f824, 0x1f82a,
+ 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860, 0x1f862, 0x1f864,
+ 0x1f868, 0x1f868, 0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889,
+ 0x1f8a0, 0x1f8a2, 0x1f890, 0x1f892, 0x1f894, 0x1f896, 0x1f8a4, 0x1f8af,
+ 0x1f8b8, 0x1f8b9, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
+ 0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f917, 0x1f920, 0x1f921,
+ 0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
+ 0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f954, 0x1f955,
+ 0x1f958, 0x1f95a, 0x1f95d, 0x1f95d, 0x1f962, 0x1f96b, 0x1f970, 0x1f979,
+ 0x1f97c, 0x1f97c, 0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993,
+ 0x1f996, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1,
+ 0x1f9f8, 0x1f9fa, 0x1f9fc, 0x1f9fc, 0x1fa00, 0x1fa03, 0x20000, 0x20012,
+ 0x20018, 0x20018, 0x2001a, 0x2001a, 0x20020, 0x20024, 0x20030, 0x20031,
+ 0x20034, 0x20036, 0x23801, 0x23801, 0x23803, 0x23803, 0x23805, 0x23805,
+ 0x23807, 0x23807, 0x23809, 0x23809, 0x2380b, 0x2380b, 0x2380d, 0x2380d,
+ 0x2380f, 0x2380f, 0x23811, 0x23811, 0x23813, 0x23813, 0x23815, 0x23815,
+ 0x23817, 0x23817, 0x23819, 0x23819, 0x2381b, 0x2381b, 0x2381d, 0x2381d,
+ 0x2381f, 0x23820, 0x23822, 0x23822, 0x23824, 0x23824, 0x23826, 0x23826,
+ 0x23828, 0x23828, 0x2382a, 0x2382a, 0x2382c, 0x2382c, 0x2382e, 0x2382e,
+ 0x23830, 0x23830, 0x23832, 0x23832, 0x23834, 0x23834, 0x23836, 0x23836,
+ 0x23838, 0x23838, 0x2383a, 0x2383a, 0x2383c, 0x2383c, 0x2383e, 0x2383e,
+ 0x23840, 0x23847, 0x23b00, 0x23b01, 0x23b03, 0x23b03, 0x23b05, 0x23b0e,
+ 0x23b10, 0x23b13, 0x23b15, 0x23b16, 0x23b20, 0x23b20, 0x23b28, 0x23b28,
+ 0x23b30, 0x23b30,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gmu_registers), 8));
+
+static const u32 gen7_2_0_gmugx_registers[] = {
+ 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df,
+ 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df,
+ 0x1a600, 0x1a61f, 0x1a640, 0x1a65f, 0x1a780, 0x1a781, 0x1a783, 0x1a785,
+ 0x1a787, 0x1a789, 0x1a78b, 0x1a78d, 0x1a78f, 0x1a791, 0x1a793, 0x1a795,
+ 0x1a797, 0x1a799, 0x1a79c, 0x1a79d, 0x1a79f, 0x1a79f, 0x1a7a0, 0x1a7a1,
+ 0x1a7a3, 0x1a7a3, 0x1a7a8, 0x1a7ab, 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5,
+ 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd, 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5,
+ 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd, 0x1a800, 0x1a802, 0x1a804, 0x1a804,
+ 0x1a816, 0x1a816, 0x1a81e, 0x1a81e, 0x1a826, 0x1a826, 0x1a82e, 0x1a82e,
+ 0x1a836, 0x1a836, 0x1a83e, 0x1a83e, 0x1a846, 0x1a846, 0x1a860, 0x1a862,
+ 0x1a864, 0x1a867, 0x1a870, 0x1a870, 0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2,
+ 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3, 0x1a900, 0x1a92b, 0x1a940, 0x1a940,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gmugx_registers), 8));
+
+static const u32 gen7_2_0_noncontext_pipe_br_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b,
+ 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640,
+ 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a,
+ 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16,
+ 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31,
+ 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79,
+ 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f,
+ 0x0a630, 0x0a631, 0x0a638, 0x0a63c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_pipe_br_registers), 8));
+
+static const u32 gen7_2_0_noncontext_pipe_bv_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b,
+ 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640,
+ 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a,
+ 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16,
+ 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31,
+ 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79,
+ 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f,
+ 0x0a630, 0x0a631, 0x0a638, 0x0a63c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_pipe_bv_registers), 8));
+
+static const u32 gen7_2_0_noncontext_rb_rac_pipe_br_registers[] = {
+ 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a, 0x08ea0, 0x08ea3,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_rb_rac_pipe_br_registers), 8));
+
+static const u32 gen7_2_0_noncontext_rb_rbp_pipe_br_registers[] = {
+ 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c,
+ 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e40, 0x08e50, 0x08e50,
+ 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e66,
+ 0x08e68, 0x08e69, 0x08e70, 0x08e79, 0x08e80, 0x08e8f,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_rb_rbp_pipe_br_registers), 8));
+
+static const u32 gen7_2_0_gras_cluster_gras_pipe_br_registers[] = {
+ 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08113, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gras_cluster_gras_pipe_br_registers), 8));
+
+static const u32 gen7_2_0_gras_cluster_gras_pipe_bv_registers[] = {
+ 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08113, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gras_cluster_gras_pipe_bv_registers), 8));
+
+static const u32 gen7_2_0_rb_rac_cluster_ps_pipe_br_registers[] = {
+ 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811,
+ 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829,
+ 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839,
+ 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849,
+ 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859,
+ 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876,
+ 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891,
+ 0x08898, 0x08899, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5,
+ 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35,
+ 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_rb_rac_cluster_ps_pipe_br_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = {
+ 0x0a980, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, 0x0a9aa, 0x0a9aa,
+ 0x0a9ae, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
+ 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc, 0x0aa00, 0x0aa00,
+ 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = {
+ 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8,
+ 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5,
+ 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa01,
+ 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b,
+ 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = {
+ 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae,
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3,
+ 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa01, 0x0aa01,
+ 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22,
+ 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = {
+ 0x0a9b0, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
+ 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc,
+ 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = {
+ 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5,
+ 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = {
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3,
+ 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31,
+ 0x0ab00, 0x0ab01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = {
+ 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872,
+ 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898,
+ 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab03,
+ 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840,
+ 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871,
+ 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af,
+ 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b,
+ 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861,
+ 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899,
+ 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = {
+ 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872,
+ 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898,
+ 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840,
+ 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871,
+ 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af,
+ 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8));
+
+static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861,
+ 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899,
+ 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8));
+
+static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
+ 0x0af88, 0x0af8b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
+
+static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0x0,
+};
+
+static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0x9,
+};
+
+static struct gen7_cluster_registers gen7_2_0_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_2_0_noncontext_pipe_br_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
+ gen7_2_0_noncontext_pipe_bv_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
+ gen7_0_0_noncontext_pipe_lpac_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_2_0_noncontext_rb_rac_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_2_0_noncontext_rb_rbp_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_2_0_gras_cluster_gras_pipe_br_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_2_0_gras_cluster_gras_pipe_br_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_pc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_pc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
+};
+
+static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
+ gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
+ { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
+};
+
+static const u32 gen7_2_0_dbgc_registers[] = {
+ 0x005ff, 0x0061c, 0x0061e, 0x00634, 0x00640, 0x0065e, 0x00679, 0x0067e,
+ 0x00699, 0x00699, 0x0069b, 0x0069e, 0x006a0, 0x006a3, 0x006c0, 0x006c1,
+ 0x18400, 0x1841c, 0x1841e, 0x18434, 0x18440, 0x1845c, 0x18479, 0x1847c,
+ 0x18580, 0x18581,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_dbgc_registers), 8));
+
+static const u32 gen7_2_0_rscc_registers[] = {
+ 0x14000, 0x14036, 0x14040, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c,
+ 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac,
+ 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132, 0x14154, 0x1416b,
+ 0x14340, 0x14342, 0x14344, 0x1437c, 0x143f0, 0x143f8, 0x143fa, 0x143fe,
+ 0x14400, 0x14404, 0x14406, 0x1440a, 0x1440c, 0x14410, 0x14412, 0x14416,
+ 0x14418, 0x1441c, 0x1441e, 0x14422, 0x14424, 0x14424, 0x14498, 0x144a0,
+ 0x144a2, 0x144a6, 0x144a8, 0x144ac, 0x144ae, 0x144b2, 0x144b4, 0x144b8,
+ 0x144ba, 0x144be, 0x144c0, 0x144c4, 0x144c6, 0x144ca, 0x144cc, 0x144cc,
+ 0x14540, 0x14548, 0x1454a, 0x1454e, 0x14550, 0x14554, 0x14556, 0x1455a,
+ 0x1455c, 0x14560, 0x14562, 0x14566, 0x14568, 0x1456c, 0x1456e, 0x14572,
+ 0x14574, 0x14574, 0x145e8, 0x145f0, 0x145f2, 0x145f6, 0x145f8, 0x145fc,
+ 0x145fe, 0x14602, 0x14604, 0x14608, 0x1460a, 0x1460e, 0x14610, 0x14614,
+ 0x14616, 0x1461a, 0x1461c, 0x1461c, 0x14690, 0x14698, 0x1469a, 0x1469e,
+ 0x146a0, 0x146a4, 0x146a6, 0x146aa, 0x146ac, 0x146b0, 0x146b2, 0x146b6,
+ 0x146b8, 0x146bc, 0x146be, 0x146c2, 0x146c4, 0x146c4, 0x14738, 0x14740,
+ 0x14742, 0x14746, 0x14748, 0x1474c, 0x1474e, 0x14752, 0x14754, 0x14758,
+ 0x1475a, 0x1475e, 0x14760, 0x14764, 0x14766, 0x1476a, 0x1476c, 0x1476c,
+ 0x147e0, 0x147e8, 0x147ea, 0x147ee, 0x147f0, 0x147f4, 0x147f6, 0x147fa,
+ 0x147fc, 0x14800, 0x14802, 0x14806, 0x14808, 0x1480c, 0x1480e, 0x14812,
+ 0x14814, 0x14814, 0x14888, 0x14890, 0x14892, 0x14896, 0x14898, 0x1489c,
+ 0x1489e, 0x148a2, 0x148a4, 0x148a8, 0x148aa, 0x148ae, 0x148b0, 0x148b4,
+ 0x148b6, 0x148ba, 0x148bc, 0x148bc, 0x14930, 0x14938, 0x1493a, 0x1493e,
+ 0x14940, 0x14944, 0x14946, 0x1494a, 0x1494c, 0x14950, 0x14952, 0x14956,
+ 0x14958, 0x1495c, 0x1495e, 0x14962, 0x14964, 0x14964,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_rscc_registers), 8));
+
+static const u32 gen7_2_0_cpr_registers[] = {
+ 0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c,
+ 0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850,
+ 0x26880, 0x2689e, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee,
+ 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f,
+ 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274ad,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_cpr_registers), 8));
+
+static const u32 gen7_2_0_dpm_lkg_registers[] = {
+ 0x21c00, 0x21c00, 0x21c08, 0x21c09, 0x21c0e, 0x21c0f, 0x21c4f, 0x21c50,
+ 0x21c52, 0x21c52, 0x21c54, 0x21c56, 0x21c58, 0x21c5a, 0x21c5c, 0x21c60,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_lkg_registers), 8));
+
+static const u32 gen7_2_0_gpucc_registers[] = {
+ 0x24000, 0x2400f, 0x24400, 0x2440f, 0x24800, 0x24805, 0x24c00, 0x24cff,
+ 0x25400, 0x25404, 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004,
+ 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26433,
+ 0x26441, 0x2644b, 0x2644d, 0x26457, 0x26466, 0x26468, 0x26478, 0x2647a,
+ 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a4, 0x264c5, 0x264c7,
+ 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2651c, 0x2651e,
+ 0x26540, 0x26576, 0x26600, 0x26616, 0x26620, 0x2662d, 0x26630, 0x26631,
+ 0x26635, 0x26635, 0x26637, 0x26637, 0x2663a, 0x2663a, 0x26642, 0x26642,
+ 0x26656, 0x26658, 0x2665b, 0x2665d, 0x2665f, 0x26662,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_gpucc_registers), 8));
+
+static const u32 gen7_2_0_cx_misc_registers[] = {
+ 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27832, 0x27857,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_cx_misc_registers), 8));
+
+static const u32 gen7_2_0_dpm_registers[] = {
+ 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12,
+ 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8));
+
+static struct gen7_reg_list gen7_2_0_reg_list[] = {
+ { gen7_2_0_gpu_registers, NULL },
+ { gen7_2_0_cx_misc_registers, NULL },
+ { gen7_2_0_dpm_registers, NULL },
+ { gen7_2_0_dbgc_registers, NULL },
+ { NULL, NULL },
+};
+
+static const u32 *gen7_2_0_external_core_regs[] = {
+ gen7_2_0_gpucc_registers,
+ gen7_2_0_cpr_registers,
+ gen7_2_0_dpm_lkg_registers,
+};
+#endif /*_ADRENO_GEN7_2_0_SNAPSHOT_H */
ADRENO_6XX_GEN4, /* a660 family */
ADRENO_7XX_GEN1, /* a730 family */
ADRENO_7XX_GEN2, /* a740 family */
+ ADRENO_7XX_GEN3, /* a750 family */
};
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
};
extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
-extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
+extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[];
struct adreno_speedbin {
uint16_t fuse;
return adreno_is_revn(gpu, 305);
}
+static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x03000512;
+}
+
static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
{
/* yes, 307, because a305c is 306 */
return gpu->info->chip_ids[0] == 0x06090000;
}
+static inline int adreno_is_a702(const struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x07000200;
+}
+
+static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
+{
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+
+ /* TODO: A612 */
+ return adreno_is_a610(gpu) || adreno_is_a702(gpu);
+}
+
/* check for a615, a616, a618, a619 or any a630 derivatives */
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x43050a01;
}
-/* Placeholder to make future diffs smaller */
+static inline int adreno_is_a750(struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x43051401;
+}
+
static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
- return gpu->info->family == ADRENO_7XX_GEN2;
+ return gpu->info->family == ADRENO_7XX_GEN2 ||
+ gpu->info->family == ADRENO_7XX_GEN3;
}
static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
/* Autogenerated file, DO NOT EDIT manually!
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
*/
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
enum vgt_event_type {
VS_DEALLOC = 0,
LRZ_FLUSH = 38,
BLIT_OP_FILL_2D = 39,
BLIT_OP_COPY_2D = 40,
+ UNK_40 = 40,
BLIT_OP_SCALE_2D = 42,
CONTEXT_DONE_2D = 43,
UNK_2C = 44,
UNK_2D = 45,
CACHE_INVALIDATE = 49,
LABEL = 63,
+ DUMMY_EVENT = 1,
CCU_INVALIDATE_DEPTH = 24,
CCU_INVALIDATE_COLOR = 25,
CCU_RESOLVE_CLEAN = 26,
};
enum adreno_pm4_packet_type {
- CP_TYPE0_PKT = 0,
+ CP_TYPE0_PKT = 0x00000000,
CP_TYPE1_PKT = 0x40000000,
CP_TYPE2_PKT = 0x80000000,
CP_TYPE3_PKT = 0xc0000000,
CP_COND_WRITE = 69,
CP_COND_WRITE5 = 69,
CP_EVENT_WRITE = 70,
+ CP_EVENT_WRITE7 = 70,
CP_EVENT_WRITE_SHD = 88,
CP_EVENT_WRITE_CFL = 89,
CP_EVENT_WRITE_ZPD = 91,
CP_WAIT_TWO_REGS = 112,
CP_MEMCPY = 117,
CP_SET_BIN_DATA5_OFFSET = 46,
+ CP_SET_UNK_BIN_DATA = 45,
CP_CONTEXT_SWITCH = 84,
CP_SET_CTXSWITCH_IB = 85,
CP_REG_WRITE = 109,
CP_END_BIN = 81,
CP_PREEMPT_DISABLE = 108,
CP_WAIT_TIMESTAMP = 20,
+ CP_GLOBAL_TIMESTAMP = 21,
+ CP_LOCAL_TIMESTAMP = 22,
CP_THREAD_CONTROL = 23,
+ CP_RESOURCE_LIST = 24,
+ CP_BV_BR_COUNT_OPS = 27,
+ CP_MODIFY_TIMESTAMP = 28,
CP_CONTEXT_REG_BUNCH2 = 93,
- CP_UNK15 = 21,
- CP_UNK16 = 22,
- CP_UNK18 = 24,
- CP_UNK1B = 27,
- CP_UNK49 = 73,
+ CP_MEM_TO_SCRATCH_MEM = 73,
+ CP_FIXED_STRIDE_DRAW_TABLE = 127,
+ CP_RESET_CONTEXT_STATE = 31,
};
enum adreno_state_block {
WRITE_GT = 6,
};
+enum poll_memory_type {
+ POLL_REGISTER = 0,
+ POLL_MEMORY = 1,
+ POLL_SCRATCH = 2,
+ POLL_ON_CHIP = 3,
+};
+
enum render_mode_cmd {
BYPASS = 1,
BINNING = 2,
END2D = 8,
};
+enum event_write_src {
+ EV_WRITE_USER_32B = 0,
+ EV_WRITE_USER_64B = 1,
+ EV_WRITE_TIMESTAMP_SUM = 2,
+ EV_WRITE_ALWAYSON = 3,
+ EV_WRITE_REGS_CONTENT = 4,
+};
+
+enum event_write_dst {
+ EV_DST_RAM = 0,
+ EV_DST_ONCHIP = 1,
+};
+
enum cp_blit_cmd {
BLIT_OP_FILL = 0,
BLIT_OP_COPY = 1,
SECURE_SAVE_ADDR = 2,
NON_PRIV_SAVE_ADDR = 3,
COUNTER = 4,
+ DRAW_STRM_ADDRESS = 8,
+ DRAW_STRM_SIZE_ADDRESS = 9,
+ PRIM_STRM_ADDRESS = 10,
+ UNK_STRM_ADDRESS = 11,
+ UNK_STRM_SIZE_ADDRESS = 12,
+ BINDLESS_BASE_0_ADDR = 16,
+ BINDLESS_BASE_1_ADDR = 17,
+ BINDLESS_BASE_2_ADDR = 18,
+ BINDLESS_BASE_3_ADDR = 19,
+ BINDLESS_BASE_4_ADDR = 20,
+ BINDLESS_BASE_5_ADDR = 21,
+ BINDLESS_BASE_6_ADDR = 22,
+};
+
+enum source_type {
+ SOURCE_REG = 0,
+ SOURCE_SCRATCH_MEM = 1,
};
enum compare_mode {
PRED_TEST = 1,
REG_COMPARE = 2,
RENDER_MODE = 3,
+ REG_COMPARE_IMM = 4,
+ THREAD_MODE = 5,
};
enum ctxswitch_ib {
TRACK_LRZ = 8,
};
+enum ts_wait_value_src {
+ TS_WAIT_GE_32B = 0,
+ TS_WAIT_GE_64B = 1,
+ TS_WAIT_GE_TIMESTAMP_SUM = 2,
+};
+
+enum ts_wait_type {
+ TS_WAIT_RAM = 0,
+ TS_WAIT_ONCHIP = 1,
+};
+
+enum pipe_count_op {
+ PIPE_CLEAR_BV_BR = 1,
+ PIPE_SET_BR_OFFSET = 2,
+ PIPE_BR_WAIT_FOR_BV = 3,
+ PIPE_BV_WAIT_FOR_BR = 4,
+};
+
+enum timestamp_op {
+ MODIFY_TIMESTAMP_CLEAR = 0,
+ MODIFY_TIMESTAMP_ADD_GLOBAL = 1,
+ MODIFY_TIMESTAMP_ADD_LOCAL = 2,
+};
+
enum cp_thread {
CP_SET_THREAD_BR = 1,
CP_SET_THREAD_BV = 2,
#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
{
- return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
}
#define REG_CP_LOAD_STATE4_0 0x00000000
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
{
- return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
}
#define REG_CP_LOAD_STATE4_2 0x00000002
#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
{
- return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
+ assert(!(val & 0x3));
+ return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
}
#define REG_CP_LOAD_STATE6_2 0x00000002
return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
}
-
-#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
-#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
+#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004
+#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
+#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
+static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
{
- return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
+ return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
}
-#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
-#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
+#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005
+#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
+#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
+static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
{
- return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
+ return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
}
-#define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
+#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
-#define REG_CP_DRAW_INDX_OFFSET_6 0x00000006
-#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
+#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006
+#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
+#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
+static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
{
- return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
+ return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
}
#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
+static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val)
{
return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
}
#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
-
#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
}
-
#define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
-
#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
}
-
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
+#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
-#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
+#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
-#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
+#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
+#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
-#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
+#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
-#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
+#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008
-#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
+#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
-#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
+#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005
+#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007
-#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
+#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
-#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
+#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
-#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
+#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
+#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008
-#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
+#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a
-#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
+#define REG_CP_DRAW_AUTO_0 0x00000000
+#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f
+#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0
+static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val)
+{
+ return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK;
+}
+#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0
+#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6
+static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val)
+{
+ return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK;
+}
+#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300
+#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8
+static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val)
+{
+ return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK;
+}
+#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00
+#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10
+static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val)
+{
+ return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK;
+}
+#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000
+#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12
+static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val)
+{
+ return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK;
+}
+#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000
+#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000
-#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
+#define REG_CP_DRAW_AUTO_1 0x00000001
+#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff
+#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0
+static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val)
+{
+ return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK;
+}
-#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
+#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002
-#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
+#define REG_CP_DRAW_AUTO_4 0x00000004
+#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff
+#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0
+static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val)
+{
+ return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK;
+}
+
+#define REG_CP_DRAW_AUTO_5 0x00000005
+#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff
+#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0
+static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val)
+{
+ return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK;
+}
#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
-static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
+#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0))
static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
}
#define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
-#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
-#define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020
+#define CP_COND_WRITE5_0_POLL__MASK 0x00000030
+#define CP_COND_WRITE5_0_POLL__SHIFT 4
+static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val)
+{
+ return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK;
+}
#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
#define REG_CP_COND_WRITE5_1 0x00000001
return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
}
#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
-#define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010
-#define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020
+#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030
+#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4
+static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val)
+{
+ return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK;
+}
#define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
#define REG_CP_WAIT_REG_MEM_1 0x00000001
#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
-#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
-}
#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
+#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
+#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
+static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
+{
+ return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
+}
#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
#define REG_CP_EVENT_WRITE_3 0x00000003
+#define REG_CP_EVENT_WRITE7_0 0x00000000
+#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff
+#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0
+static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val)
+{
+ return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK;
+}
+#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000
+#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000
+#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000
+#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000
+#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000
+#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000
+#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000
+#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000
+#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20
+static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val)
+{
+ return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK;
+}
+#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000
+#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24
+static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val)
+{
+ return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK;
+}
+#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000
+
+#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001
+#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff
+#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0
+static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val)
+{
+ return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK;
+}
+
+#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002
+#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff
+#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0
+static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val)
+{
+ return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK;
+}
+
+#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003
+#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
+#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
+static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
+{
+ return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
+}
+
+#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004
+#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
+#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
+static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
+{
+ return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
+}
+
+#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0
+static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val)
+{
+ return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK;
+}
+
+#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
+static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
+{
+ return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
+}
+
+#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
+#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
+static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
+{
+ return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
+}
+
#define REG_CP_BLIT_0 0x00000000
#define CP_BLIT_0_OP__MASK 0x0000000f
#define CP_BLIT_0_OP__SHIFT 0
#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
-
#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
}
-
#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
}
-static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
+#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0))
static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
-#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
+#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff
#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
{
{
return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
}
+#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff
+#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0
+static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val)
+{
+ return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK;
+}
+#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000
+#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18
+static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val)
+{
+ return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK;
+}
#define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
#define A6XX_CP_REG_TEST_0_BIT__SHIFT 20
static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
{
return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;
}
+#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000
+#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000
#define CP_COND_REG_EXEC_0_BINNING 0x02000000
#define CP_COND_REG_EXEC_0_GMEM 0x04000000
#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
+#define CP_COND_REG_EXEC_0_BV 0x02000000
+#define CP_COND_REG_EXEC_0_BR 0x04000000
+#define CP_COND_REG_EXEC_0_LPAC 0x08000000
#define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
#define CP_COND_REG_EXEC_0_MODE__SHIFT 28
static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
}
-#define REG_CP_COND_REG_EXEC_1 0x00000001
-#define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff
-#define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
-static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
+#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001
+#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
+#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
+static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
+{
+ return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK;
+}
+
+#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001
+#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff
+#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0
+static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val)
{
- return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
+ return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK;
+}
+#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000
+
+#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001
+#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
+#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
+static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
+{
+ return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
+}
+
+#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001
+#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff
+#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0
+static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val)
+{
+ return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK;
+}
+
+#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001
+#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
+#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
+static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
+{
+ return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
+}
+
+#define REG_CP_COND_REG_EXEC_2 0x00000002
+#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff
+#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0
+static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val)
+{
+ return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK;
}
#define REG_CP_COND_EXEC_0 0x00000000
#define REG_CP_START_BIN_BODY_DWORDS 0x00000004
#define REG_CP_WAIT_TIMESTAMP_0 0x00000000
+#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003
+#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0
+static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val)
+{
+ return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK;
+}
+#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010
+#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4
+static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val)
+{
+ return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK;
+}
+
+#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001
-#define REG_CP_WAIT_TIMESTAMP_ADDR 0x00000001
+#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001
-#define REG_CP_WAIT_TIMESTAMP_TIMESTAMP 0x00000003
+#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003
+
+#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004
+
+#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000
+#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f
+#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0
+static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val)
+{
+ return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK;
+}
+
+#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001
+#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff
+#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0
+static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val)
+{
+ return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK;
+}
+
+#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000
+#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff
+#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0
+static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val)
+{
+ return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK;
+}
+#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000
+#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28
+static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val)
+{
+ return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK;
+}
+
+#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000
+#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f
+#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0
+static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val)
+{
+ return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK;
+}
+
+#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001
+#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f
+#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0
+static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val)
+{
+ return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK;
+}
+
+#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002
+#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff
+#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0
+static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val)
+{
+ return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK;
+}
+
+#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003
+#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff
+#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0
+static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val)
+{
+ return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK;
+}
#define REG_CP_THREAD_CONTROL_0 0x00000000
#define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003
#define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000
#define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000
+#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000
+
+#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002
+#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff
+#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0
+static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val)
+{
+ return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK;
+}
+#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000
+#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20
+static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val)
+{
+ return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK;
+}
+
+#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003
+#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff
+#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0
+static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val)
+{
+ return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK;
+}
+
+#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000
+#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001
+#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002
+#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004
+
+#ifdef __cplusplus
+#endif
#endif /* ADRENO_PM4_XML */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023. Linaro Inc. All rights reserved.
+ */
+
+#ifndef _DPU_3_2_SDM660_H
+#define _DPU_3_2_SDM660_H
+
+static const struct dpu_caps sdm660_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg sdm660_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x458,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
+ },
+};
+
+static const struct dpu_ctl_cfg sdm660_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+};
+
+static const struct dpu_sspp_cfg sdm660_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &dpu_vig_sblk_qseed3_1_2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &dpu_vig_sblk_qseed3_1_2,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1ac,
+ .features = DMA_CURSOR_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
+};
+
+static const struct dpu_lm_cfg sdm660_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ },
+};
+
+static const struct dpu_pingpong_cfg sdm660_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
+ },
+};
+
+static const struct dpu_dsc_cfg sdm660_dsc[] = {
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ },
+};
+
+static const struct dpu_dspp_cfg sdm660_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ },
+};
+
+static const struct dpu_intf_cfg sdm660_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x280,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x280,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = -1,
+ },
+};
+
+static const struct dpu_perf_cfg sdm660_perf_data = {
+ .max_bw_low = 6600000,
+ .max_bw_high = 6600000,
+ .min_core_ib = 3100000,
+ .min_llcc_ib = 800000,
+ .min_dram_ib = 800000,
+ .undersized_prefill_lines = 2,
+ .xtra_prefill_lines = 2,
+ .dest_scale_prefill_lines = 3,
+ .macrotile_prefill_lines = 4,
+ .yuv_nv12_prefill_lines = 8,
+ .linear_prefill_lines = 1,
+ .downscaling_prefill_lines = 1,
+ .amortizable_threshold = 25,
+ .min_prefill_lines = 25,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(msm8998_qos_linear),
+ .entries = msm8998_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
+ .entries = msm8998_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(msm8998_qos_nrt),
+ .entries = msm8998_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 200,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sdm660_mdss_ver = {
+ .core_major_ver = 3,
+ .core_minor_ver = 2,
+};
+
+const struct dpu_mdss_cfg dpu_sdm660_cfg = {
+ .mdss_ver = &sdm660_mdss_ver,
+ .caps = &sdm660_dpu_caps,
+ .mdp = &sdm660_mdp,
+ .ctl_count = ARRAY_SIZE(sdm660_ctl),
+ .ctl = sdm660_ctl,
+ .sspp_count = ARRAY_SIZE(sdm660_sspp),
+ .sspp = sdm660_sspp,
+ .mixer_count = ARRAY_SIZE(sdm660_lm),
+ .mixer = sdm660_lm,
+ .dspp_count = ARRAY_SIZE(sdm660_dspp),
+ .dspp = sdm660_dspp,
+ .pingpong_count = ARRAY_SIZE(sdm660_pp),
+ .pingpong = sdm660_pp,
+ .dsc_count = ARRAY_SIZE(sdm660_dsc),
+ .dsc = sdm660_dsc,
+ .intf_count = ARRAY_SIZE(sdm660_intf),
+ .intf = sdm660_intf,
+ .vbif_count = ARRAY_SIZE(msm8998_vbif),
+ .vbif = msm8998_vbif,
+ .perf = &sdm660_perf_data,
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023. Linaro Inc. All rights reserved.
+ */
+
+#ifndef _DPU_3_3_SDM630_H
+#define _DPU_3_3_SDM630_H
+
+static const struct dpu_caps sdm630_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg sdm630_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x458,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
+ },
+};
+
+static const struct dpu_ctl_cfg sdm630_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+};
+
+static const struct dpu_sspp_cfg sdm630_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &dpu_vig_sblk_qseed3_1_2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1ac,
+ .features = DMA_CURSOR_MSM8998_MASK,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
+};
+
+static const struct dpu_lm_cfg sdm630_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .pingpong = PINGPONG_2,
+ },
+};
+
+static const struct dpu_pingpong_cfg sdm630_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
+ },
+};
+
+static const struct dpu_dspp_cfg sdm630_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ },
+};
+
+static const struct dpu_intf_cfg sdm630_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x280,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = -1,
+ },
+};
+
+static const struct dpu_perf_cfg sdm630_perf_data = {
+ .max_bw_low = 4100000,
+ .max_bw_high = 4100000,
+ .min_core_ib = 3200000,
+ .min_llcc_ib = 800000,
+ .min_dram_ib = 800000,
+ .undersized_prefill_lines = 2,
+ .xtra_prefill_lines = 2,
+ .dest_scale_prefill_lines = 3,
+ .macrotile_prefill_lines = 4,
+ .yuv_nv12_prefill_lines = 8,
+ .linear_prefill_lines = 1,
+ .downscaling_prefill_lines = 1,
+ .amortizable_threshold = 25,
+ .min_prefill_lines = 25,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(msm8998_qos_linear),
+ .entries = msm8998_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
+ .entries = msm8998_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(msm8998_qos_nrt),
+ .entries = msm8998_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 200,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sdm630_mdss_ver = {
+ .core_major_ver = 3,
+ .core_minor_ver = 3,
+};
+
+const struct dpu_mdss_cfg dpu_sdm630_cfg = {
+ .mdss_ver = &sdm630_mdss_ver,
+ .caps = &sdm630_dpu_caps,
+ .mdp = &sdm630_mdp,
+ .ctl_count = ARRAY_SIZE(sdm630_ctl),
+ .ctl = sdm630_ctl,
+ .sspp_count = ARRAY_SIZE(sdm630_sspp),
+ .sspp = sdm630_sspp,
+ .mixer_count = ARRAY_SIZE(sdm630_lm),
+ .mixer = sdm630_lm,
+ .dspp_count = ARRAY_SIZE(sdm630_dspp),
+ .dspp = sdm630_dspp,
+ .pingpong_count = ARRAY_SIZE(sdm630_pp),
+ .pingpong = sdm630_pp,
+ .intf_count = ARRAY_SIZE(sdm630_intf),
+ .intf = sdm630_intf,
+ .vbif_count = ARRAY_SIZE(msm8998_vbif),
+ .vbif = msm8998_vbif,
+ .perf = &sdm630_perf_data,
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_9_2_X1E80100_H
+#define _DPU_9_2_X1E80100_H
+
+static const struct dpu_caps x1e80100_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg x1e80100_mdp = {
+ .name = "top_0",
+ .base = 0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
+static const struct dpu_ctl_cfg x1e80100_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,
+ .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg x1e80100_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x344,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_3,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x344,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_3,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x344,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_3,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x344,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_12", .id = SSPP_DMA4,
+ .base = 0x2c000, .len = 0x344,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 14,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_13", .id = SSPP_DMA5,
+ .base = 0x2e000, .len = 0x344,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 15,
+ .type = SSPP_TYPE_DMA,
+ },
+};
+
+static const struct dpu_lm_cfg x1e80100_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
+};
+
+static const struct dpu_dspp_cfg x1e80100_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sdm845_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg x1e80100_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x6d000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x6e000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ }, {
+ .name = "pingpong_6", .id = PINGPONG_6,
+ .base = 0x66000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ }, {
+ .name = "pingpong_7", .id = PINGPONG_7,
+ .base = 0x66400, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ },
+};
+
+static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = {
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x4e000, .len = 0x8,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x50000, .len = 0x8,
+ }, {
+ .name = "merge_3d_3", .id = MERGE_3D_3,
+ .base = 0x66700, .len = 0x8,
+ },
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg x1e80100_dsc[] = {
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x4,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x4,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x81000, .len = 0x4,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x81000, .len = 0x4,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_1,
+ },
+};
+
+static const struct dpu_wb_cfg x1e80100_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats_rgb,
+ .num_formats = ARRAY_SIZE(wb2_formats_rgb),
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
+static const struct dpu_intf_cfg x1e80100_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ }, {
+ .name = "intf_4", .id = INTF_4,
+ .base = 0x38000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_2,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
+ }, {
+ .name = "intf_5", .id = INTF_5,
+ .base = 0x39000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_3,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
+ },
+};
+
+static const struct dpu_perf_cfg x1e80100_perf_data = {
+ .max_bw_low = 13600000,
+ .max_bw_high = 18200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 35,
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version x1e80100_mdss_ver = {
+ .core_major_ver = 9,
+ .core_minor_ver = 2,
+};
+
+const struct dpu_mdss_cfg dpu_x1e80100_cfg = {
+ .mdss_ver = &x1e80100_mdss_ver,
+ .caps = &x1e80100_dpu_caps,
+ .mdp = &x1e80100_mdp,
+ .ctl_count = ARRAY_SIZE(x1e80100_ctl),
+ .ctl = x1e80100_ctl,
+ .sspp_count = ARRAY_SIZE(x1e80100_sspp),
+ .sspp = x1e80100_sspp,
+ .mixer_count = ARRAY_SIZE(x1e80100_lm),
+ .mixer = x1e80100_lm,
+ .dspp_count = ARRAY_SIZE(x1e80100_dspp),
+ .dspp = x1e80100_dspp,
+ .pingpong_count = ARRAY_SIZE(x1e80100_pp),
+ .pingpong = x1e80100_pp,
+ .dsc_count = ARRAY_SIZE(x1e80100_dsc),
+ .dsc = x1e80100_dsc,
+ .merge_3d_count = ARRAY_SIZE(x1e80100_merge_3d),
+ .merge_3d = x1e80100_merge_3d,
+ .wb_count = ARRAY_SIZE(x1e80100_wb),
+ .wb = x1e80100_wb,
+ .intf_count = ARRAY_SIZE(x1e80100_intf),
+ .intf = x1e80100_intf,
+ .vbif_count = ARRAY_SIZE(sm8550_vbif),
+ .vbif = sm8550_vbif,
+ .perf = &x1e80100_perf_data,
+};
+
+#endif
return dpu_enc->wide_bus_en;
}
+bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
+{
+ const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+ return dpu_enc->dsc ? true : false;
+}
+
int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc;
struct dpu_global_state *global_state;
struct drm_framebuffer *fb;
struct drm_dsc_config *dsc;
- int i = 0;
int ret = 0;
if (!drm_enc || !crtc_state || !conn_state) {
trace_dpu_enc_atomic_check(DRMID(drm_enc));
- /* perform atomic check on the first physical encoder (master) */
- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
- if (phys->ops.atomic_check)
- ret = phys->ops.atomic_check(phys, crtc_state,
- conn_state);
- if (ret) {
- DPU_ERROR_ENC(dpu_enc,
- "mode unsupported, phys idx %d\n", i);
- return ret;
- }
- }
-
dsc = dpu_encoder_get_dsc_config(drm_enc);
topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);
}
}
-static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
+static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc;
int i;
dpu_enc = to_dpu_encoder_virt(drm_enc);
- DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
+ DPU_DEBUG_ENC(dpu_enc, "\n");
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
- if (phys->ops.irq_control)
- phys->ops.irq_control(phys, enable);
+ phys->ops.irq_enable(phys);
}
+}
+
+static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc)
+{
+ struct dpu_encoder_virt *dpu_enc;
+ int i;
+ if (!drm_enc) {
+ DPU_ERROR("invalid encoder\n");
+ return;
+ }
+
+ dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+ DPU_DEBUG_ENC(dpu_enc, "\n");
+ for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+ struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+ phys->ops.irq_disable(phys);
+ }
}
-static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
- bool enable)
+static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc)
{
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
- trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
+ trace_dpu_enc_rc_enable(DRMID(drm_enc));
if (!dpu_enc->cur_master) {
DPU_ERROR("encoder master not set\n");
return;
}
- if (enable) {
- /* enable DPU core clks */
- pm_runtime_get_sync(&dpu_kms->pdev->dev);
+ /* enable DPU core clks */
+ pm_runtime_get_sync(&dpu_kms->pdev->dev);
- /* enable all the irq */
- _dpu_encoder_irq_control(drm_enc, true);
+ /* enable all the irq */
+ _dpu_encoder_irq_enable(drm_enc);
+}
- } else {
- /* disable all the irq */
- _dpu_encoder_irq_control(drm_enc, false);
+static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc)
+{
+ struct msm_drm_private *priv;
+ struct dpu_kms *dpu_kms;
+ struct dpu_encoder_virt *dpu_enc;
+
+ dpu_enc = to_dpu_encoder_virt(drm_enc);
+ priv = drm_enc->dev->dev_private;
+ dpu_kms = to_dpu_kms(priv->kms);
- /* disable DPU core clks */
- pm_runtime_put_sync(&dpu_kms->pdev->dev);
+ trace_dpu_enc_rc_disable(DRMID(drm_enc));
+
+ if (!dpu_enc->cur_master) {
+ DPU_ERROR("encoder master not set\n");
+ return;
}
+ /* disable all the irq */
+ _dpu_encoder_irq_disable(drm_enc);
+
+ /* disable DPU core clks */
+ pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
}
if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
- _dpu_encoder_irq_control(drm_enc, true);
+ _dpu_encoder_irq_enable(drm_enc);
else
- _dpu_encoder_resource_control_helper(drm_enc, true);
+ _dpu_encoder_resource_enable(drm_enc);
dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
if (is_vid_mode &&
dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
- _dpu_encoder_irq_control(drm_enc, true);
+ _dpu_encoder_irq_enable(drm_enc);
}
/* skip if is already OFF or IDLE, resources are off already */
else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
* and in IDLE state the resources are already disabled
*/
if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
- _dpu_encoder_resource_control_helper(drm_enc, false);
+ _dpu_encoder_resource_disable(drm_enc);
dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
}
if (is_vid_mode)
- _dpu_encoder_irq_control(drm_enc, false);
+ _dpu_encoder_irq_disable(drm_enc);
else
- _dpu_encoder_resource_control_helper(drm_enc, false);
+ _dpu_encoder_resource_disable(drm_enc);
dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
phys->cached_mode = crtc_state->adjusted_mode;
- if (phys->ops.atomic_mode_set)
- phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
}
}
dsc_common_mode = 0;
pic_width = dsc->pic_width;
- dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
+ dsc_common_mode = DSC_MODE_SPLIT_PANEL;
+ if (dpu_encoder_use_dsc_merge(enc_master->parent))
+ dsc_common_mode |= DSC_MODE_MULTIPLEX;
if (enc_master->intf_mode == INTF_MODE_VIDEO)
dsc_common_mode |= DSC_MODE_VIDEO;
bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
+/**
+ * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
+ * for the encoder.
+ * @drm_enc: Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc);
+
/**
* dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
* in virtual encoder that can collect CRC values
* @is_master: Whether this phys_enc is the current master
* encoder. Can be switched at enable time. Based
* on split_role and current mode (CMD/VID).
- * @atomic_mode_set: DRM Call. Set a DRM mode.
- * This likely caches the mode, for use at enable.
* @enable: DRM Call. Enable a DRM mode.
* @disable: DRM Call. Disable mode.
- * @atomic_check: DRM Call. Atomic check new DRM state.
* @control_vblank_irq Register/Deregister for VBLANK IRQ
* @wait_for_commit_done: Wait for hardware to have flushed the
* current pending frames to hardware
* @handle_post_kickoff: Do any work necessary post-kickoff work
* @trigger_start: Process start event on physical encoder
* @needs_single_flush: Whether encoder slaves need to be flushed
- * @irq_control: Handler to enable/disable all the encoder IRQs
+ * @irq_enable: Handler to enable all the encoder IRQs
+ * @irq_disable: Handler to disable all the encoder IRQs
* @prepare_idle_pc: phys encoder can update the vsync_enable status
* on idle power collapse prepare
* @restore: Restore all the encoder configs.
struct dpu_encoder_phys_ops {
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
bool (*is_master)(struct dpu_encoder_phys *encoder);
- void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state);
void (*enable)(struct dpu_encoder_phys *encoder);
void (*disable)(struct dpu_encoder_phys *encoder);
- int (*atomic_check)(struct dpu_encoder_phys *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state);
int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
- void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
+ void (*irq_enable)(struct dpu_encoder_phys *phys);
+ void (*irq_disable)(struct dpu_encoder_phys *phys);
void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
void (*restore)(struct dpu_encoder_phys *phys);
int (*get_line_count)(struct dpu_encoder_phys *phys);
dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
}
-static void dpu_encoder_phys_cmd_atomic_mode_set(
- struct dpu_encoder_phys *phys_enc,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
-
- phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
-
- if (phys_enc->has_intf_te)
- phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
- else
- phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
-
- phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
-}
-
static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
struct dpu_encoder_phys *phys_enc)
{
return ret;
}
-static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
- bool enable)
+static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc)
{
- trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0,
- enable, phys_enc->vblank_refcount);
+ trace_dpu_enc_phys_cmd_irq_enable(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->vblank_refcount);
- if (enable) {
- dpu_core_irq_register_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_PINGPONG],
- dpu_encoder_phys_cmd_pp_tx_done_irq,
- phys_enc);
+ phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
+ phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
+
+ if (phys_enc->has_intf_te)
+ phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
+ else
+ phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
+
+ dpu_core_irq_register_callback(phys_enc->dpu_kms,
+ phys_enc->irq[INTR_IDX_PINGPONG],
+ dpu_encoder_phys_cmd_pp_tx_done_irq,
+ phys_enc);
+ dpu_core_irq_register_callback(phys_enc->dpu_kms,
+ phys_enc->irq[INTR_IDX_UNDERRUN],
+ dpu_encoder_phys_cmd_underrun_irq,
+ phys_enc);
+ dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
+
+ if (dpu_encoder_phys_cmd_is_master(phys_enc))
dpu_core_irq_register_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_UNDERRUN],
- dpu_encoder_phys_cmd_underrun_irq,
- phys_enc);
- dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
-
- if (dpu_encoder_phys_cmd_is_master(phys_enc))
- dpu_core_irq_register_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_CTL_START],
- dpu_encoder_phys_cmd_ctl_start_irq,
- phys_enc);
- } else {
- if (dpu_encoder_phys_cmd_is_master(phys_enc))
- dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_CTL_START]);
+ phys_enc->irq[INTR_IDX_CTL_START],
+ dpu_encoder_phys_cmd_ctl_start_irq,
+ phys_enc);
+}
+static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc)
+{
+ trace_dpu_enc_phys_cmd_irq_disable(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->vblank_refcount);
+
+ if (dpu_encoder_phys_cmd_is_master(phys_enc))
dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_UNDERRUN]);
- dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
- dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_PINGPONG]);
- }
+ phys_enc->irq[INTR_IDX_CTL_START]);
+
+ dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]);
+ dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
+ dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]);
+
+ phys_enc->irq[INTR_IDX_CTL_START] = 0;
+ phys_enc->irq[INTR_IDX_PINGPONG] = 0;
+ phys_enc->irq[INTR_IDX_RDPTR] = 0;
}
static void dpu_encoder_phys_cmd_tearcheck_config(
struct dpu_encoder_phys_ops *ops)
{
ops->is_master = dpu_encoder_phys_cmd_is_master;
- ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set;
ops->enable = dpu_encoder_phys_cmd_enable;
ops->disable = dpu_encoder_phys_cmd_disable;
ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;
ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;
ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
- ops->irq_control = dpu_encoder_phys_cmd_irq_control;
+ ops->irq_enable = dpu_encoder_phys_cmd_irq_enable;
+ ops->irq_disable = dpu_encoder_phys_cmd_irq_disable;
ops->restore = dpu_encoder_phys_cmd_enable_helper;
ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff;
dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
phys_enc->intf_mode = INTF_MODE_CMD;
+ phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
+
cmd_enc->stream_sel = 0;
if (!phys_enc->hw_intf) {
}
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+ timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
/*
* for DP, divide the horizonal parameters by 2 when
return phys_enc->split_role != ENC_ROLE_SOLO;
}
-static void dpu_encoder_phys_vid_atomic_mode_set(
- struct dpu_encoder_phys *phys_enc,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
-
- phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
-}
-
static int dpu_encoder_phys_vid_control_vblank_irq(
struct dpu_encoder_phys *phys_enc,
bool enable)
}
}
-static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
- bool enable)
+static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc)
{
int ret;
- trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
- phys_enc->hw_intf->idx - INTF_0,
- enable,
- phys_enc->vblank_refcount);
+ trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent),
+ phys_enc->hw_intf->idx - INTF_0,
+ phys_enc->vblank_refcount);
- if (enable) {
- ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
- if (WARN_ON(ret))
- return;
-
- dpu_core_irq_register_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_UNDERRUN],
- dpu_encoder_phys_vid_underrun_irq,
- phys_enc);
- } else {
- dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
- dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
- phys_enc->irq[INTR_IDX_UNDERRUN]);
- }
+ ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
+ if (WARN_ON(ret))
+ return;
+
+ dpu_core_irq_register_callback(phys_enc->dpu_kms,
+ phys_enc->irq[INTR_IDX_UNDERRUN],
+ dpu_encoder_phys_vid_underrun_irq,
+ phys_enc);
+}
+
+static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc)
+{
+ trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent),
+ phys_enc->hw_intf->idx - INTF_0,
+ phys_enc->vblank_refcount);
+
+ dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
+ dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
+ phys_enc->irq[INTR_IDX_UNDERRUN]);
}
static int dpu_encoder_phys_vid_get_line_count(
static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
{
ops->is_master = dpu_encoder_phys_vid_is_master;
- ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
ops->enable = dpu_encoder_phys_vid_enable;
ops->disable = dpu_encoder_phys_vid_disable;
ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
- ops->irq_control = dpu_encoder_phys_vid_irq_control;
+ ops->irq_enable = dpu_encoder_phys_vid_irq_enable;
+ ops->irq_disable = dpu_encoder_phys_vid_irq_disable;
ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
phys_enc->intf_mode = INTF_MODE_VIDEO;
+ phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
+ phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
}
}
-/**
- * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states
- * @phys_enc: Pointer to physical encoder
- * @crtc_state: Pointer to CRTC atomic state
- * @conn_state: Pointer to connector atomic state
- */
-static int dpu_encoder_phys_wb_atomic_check(
- struct dpu_encoder_phys *phys_enc,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct drm_framebuffer *fb;
- const struct drm_display_mode *mode = &crtc_state->mode;
-
- DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
- phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);
-
- if (!conn_state || !conn_state->connector) {
- DPU_ERROR("invalid connector state\n");
- return -EINVAL;
- } else if (conn_state->connector->status !=
- connector_status_connected) {
- DPU_ERROR("connector not connected %d\n",
- conn_state->connector->status);
- return -EINVAL;
- }
-
- if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
- return 0;
-
- fb = conn_state->writeback_job->fb;
-
- DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
- fb->width, fb->height);
-
- if (fb->width != mode->hdisplay) {
- DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
- mode->hdisplay);
- return -EINVAL;
- } else if (fb->height != mode->vdisplay) {
- DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
- mode->vdisplay);
- return -EINVAL;
- } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
- DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
- fb->width, phys_enc->hw_wb->caps->maxlinewidth);
- return -EINVAL;
- }
-
- return drm_atomic_helper_check_wb_connector_state(conn_state->connector, conn_state->state);
-}
-
-
/**
* _dpu_encoder_phys_wb_update_flush - flush hardware update
* @phys_enc: Pointer to physical encoder
}
/**
- * dpu_encoder_phys_wb_irq_ctrl - irq control of WB
+ * dpu_encoder_phys_wb_irq_enable - irq control of WB
* @phys: Pointer to physical encoder
- * @enable: indicates enable or disable interrupts
*/
-static void dpu_encoder_phys_wb_irq_ctrl(
- struct dpu_encoder_phys *phys, bool enable)
+static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys)
{
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
- if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
+ if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
dpu_core_irq_register_callback(phys->dpu_kms,
- phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys);
- else if (!enable &&
- atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
- dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
+ phys->irq[INTR_IDX_WB_DONE],
+ dpu_encoder_phys_wb_done_irq,
+ phys);
}
-static void dpu_encoder_phys_wb_atomic_mode_set(
- struct dpu_encoder_phys *phys_enc,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
+/**
+ * dpu_encoder_phys_wb_irq_disable - irq control of WB
+ * @phys: Pointer to physical encoder
+ */
+static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)
{
- phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
+ struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
+
+ if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
+ dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
}
static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
{
ops->is_master = dpu_encoder_phys_wb_is_master;
- ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
ops->enable = dpu_encoder_phys_wb_enable;
ops->disable = dpu_encoder_phys_wb_disable;
- ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
ops->trigger_start = dpu_encoder_helper_trigger_start;
ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
- ops->irq_control = dpu_encoder_phys_wb_irq_ctrl;
+ ops->irq_enable = dpu_encoder_phys_wb_irq_enable;
+ ops->irq_disable = dpu_encoder_phys_wb_irq_disable;
ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
}
dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
phys_enc->intf_mode = INTF_MODE_WB_LINE;
+ phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
atomic_set(&wb_enc->wbirq_refcount, 0);
*************************************************************/
#include "catalog/dpu_3_0_msm8998.h"
+#include "catalog/dpu_3_2_sdm660.h"
+#include "catalog/dpu_3_3_sdm630.h"
#include "catalog/dpu_4_0_sdm845.h"
#include "catalog/dpu_4_1_sdm670.h"
#include "catalog/dpu_9_0_sm8550.h"
+#include "catalog/dpu_9_2_x1e80100.h"
+
#include "catalog/dpu_10_0_sm8650.h"
};
extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
+extern const struct dpu_mdss_cfg dpu_sdm630_cfg;
+extern const struct dpu_mdss_cfg dpu_sdm660_cfg;
extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
extern const struct dpu_mdss_cfg dpu_sdm670_cfg;
extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
+extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
#endif /* _DPU_HW_CATALOG_H */
hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
- /*
- * DATA_HCTL_EN controls data timing which can be different from
- * video timing. It is recommended to enable it for all cases, except
- * if compression is enabled in 1 pixel per clock mode
- */
if (p->wide_bus_en)
- intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN;
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
data_width = p->width;
DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
+ /*
+ * DATA_HCTL_EN controls data timing which can be different from
+ * video timing. It is recommended to enable it for all cases, except
+ * if compression is enabled in 1 pixel per clock mode
+ */
+ if (!(p->compression_en && !p->wide_bus_en))
+ intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
+
DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
u32 hsync_skew;
bool wide_bus_en;
+ bool compression_en;
};
struct dpu_hw_intf_prog_fetch {
struct msm_drm_private *priv = s->dev->dev_private;
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct drm_private_state *priv_state;
- int ret;
-
- ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
- if (ret)
- return ERR_PTR(ret);
priv_state = drm_atomic_get_private_obj_state(s,
&dpu_kms->global_state);
{
struct dpu_global_state *state;
- drm_modeset_lock_init(&dpu_kms->global_state_lock);
-
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
return 0;
}
+static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)
+{
+ drm_atomic_private_obj_fini(&dpu_kms->global_state);
+}
+
static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
{
struct icc_path *path0;
{
struct drm_encoder *encoder = NULL;
struct msm_display_info info;
+ const enum dpu_wb wb_idx = WB_2;
+ u32 maxlinewidth;
int rc;
memset(&info, 0, sizeof(info));
info.num_of_h_tiles = 1;
/* use only WB idx 2 instance for DPU */
- info.h_tile_instance[0] = WB_2;
+ info.h_tile_instance[0] = wb_idx;
info.intf_type = INTF_WB;
+ maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth;
+
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info);
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
return PTR_ERR(encoder);
}
- rc = dpu_writeback_init(dev, encoder, wb_formats,
- n_formats);
+ rc = dpu_writeback_init(dev, encoder, wb_formats, n_formats, maxlinewidth);
if (rc) {
DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
return rc;
dpu_kms->hw_vbif[i] = NULL;
}
+ dpu_kms_global_obj_fini(dpu_kms);
+
dpu_kms->catalog = NULL;
dpu_kms->hw_mdp = NULL;
return 0;
}
+static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms)
+{
+ struct platform_device *pdev = dpu_kms->pdev;
+ struct platform_device *mdss_dev;
+ int ret;
+
+ if (!dev_is_platform(dpu_kms->pdev->dev.parent))
+ return -EINVAL;
+
+ mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent);
+
+ dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys");
+ if (IS_ERR(dpu_kms->mmio)) {
+ ret = PTR_ERR(dpu_kms->mmio);
+ DPU_ERROR("mdp register memory map failed: %d\n", ret);
+ dpu_kms->mmio = NULL;
+ return ret;
+ }
+ DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
+
+ dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev,
+ dpu_kms->pdev,
+ "vbif_phys");
+ if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
+ ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
+ DPU_ERROR("vbif register memory map failed: %d\n", ret);
+ dpu_kms->vbif[VBIF_RT] = NULL;
+ return ret;
+ }
+
+ dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev,
+ dpu_kms->pdev,
+ "vbif_nrt_phys");
+ if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
+ dpu_kms->vbif[VBIF_NRT] = NULL;
+ DPU_DEBUG("VBIF NRT is not defined");
+ }
+
+ return 0;
+}
+
+static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms)
+{
+ struct platform_device *pdev = dpu_kms->pdev;
+ int ret;
+
+ dpu_kms->mmio = msm_ioremap(pdev, "mdp");
+ if (IS_ERR(dpu_kms->mmio)) {
+ ret = PTR_ERR(dpu_kms->mmio);
+ DPU_ERROR("mdp register memory map failed: %d\n", ret);
+ dpu_kms->mmio = NULL;
+ return ret;
+ }
+ DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
+
+ dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");
+ if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
+ ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
+ DPU_ERROR("vbif register memory map failed: %d\n", ret);
+ dpu_kms->vbif[VBIF_RT] = NULL;
+ return ret;
+ }
+
+ dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");
+ if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
+ dpu_kms->vbif[VBIF_NRT] = NULL;
+ DPU_DEBUG("VBIF NRT is not defined");
+ }
+
+ return 0;
+}
+
static int dpu_dev_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int irq;
int ret = 0;
+ if (!msm_disp_drv_should_bind(&pdev->dev, true))
+ return -ENODEV;
+
dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL);
if (!dpu_kms)
return -ENOMEM;
dpu_kms->base.irq = irq;
- dpu_kms->mmio = msm_ioremap(pdev, "mdp");
- if (IS_ERR(dpu_kms->mmio)) {
- ret = PTR_ERR(dpu_kms->mmio);
- DPU_ERROR("mdp register memory map failed: %d\n", ret);
- dpu_kms->mmio = NULL;
- return ret;
- }
- DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
-
- dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");
- if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
- ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
- DPU_ERROR("vbif register memory map failed: %d\n", ret);
- dpu_kms->vbif[VBIF_RT] = NULL;
+ if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5"))
+ ret = dpu_kms_mmap_mdp5(dpu_kms);
+ else
+ ret = dpu_kms_mmap_dpu(dpu_kms);
+ if (ret)
return ret;
- }
-
- dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");
- if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
- dpu_kms->vbif[VBIF_NRT] = NULL;
- DPU_DEBUG("VBIF NRT is not defined");
- }
ret = dpu_kms_parse_data_bus_icc_path(dpu_kms);
if (ret)
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
{ .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
+ { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
+ { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
{ .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
{ .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
{ .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
+ { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
* Global private object state, Do not access directly, use
* dpu_kms_global_get_state()
*/
- struct drm_modeset_lock global_state_lock;
struct drm_private_obj global_state;
struct dpu_rm rm;
return 0;
}
-static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
- struct dpu_global_state *global_state,
- struct drm_encoder *enc,
- const struct msm_display_topology *top)
+static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_state,
+ int start,
+ uint32_t enc_id)
{
- int num_dsc = top->num_dsc;
int i;
- /* check if DSC required are allocated or not */
- for (i = 0; i < num_dsc; i++) {
- if (!rm->dsc_blks[i]) {
- DPU_ERROR("DSC %d does not exist\n", i);
- return -EIO;
+ for (i = start; i < (PINGPONG_MAX - PINGPONG_0); i++) {
+ if (global_state->pingpong_to_enc_id[i] == enc_id)
+ return i;
+ }
+
+ return -ENAVAIL;
+}
+
+static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int pp_idx)
+{
+ /*
+ * DSC with even index must be used with the PINGPONG with even index
+ * DSC with odd index must be used with the PINGPONG with odd index
+ */
+ if ((dsc_idx & 0x01) != (pp_idx & 0x01))
+ return -ENAVAIL;
+
+ return 0;
+}
+
+static int _dpu_rm_dsc_alloc(struct dpu_rm *rm,
+ struct dpu_global_state *global_state,
+ uint32_t enc_id,
+ const struct msm_display_topology *top)
+{
+ int num_dsc = 0;
+ int pp_idx = 0;
+ int dsc_idx;
+ int ret;
+
+ for (dsc_idx = 0; dsc_idx < ARRAY_SIZE(rm->dsc_blks) &&
+ num_dsc < top->num_dsc; dsc_idx++) {
+ if (!rm->dsc_blks[dsc_idx])
+ continue;
+
+ if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id))
+ continue;
+
+ pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id);
+ if (pp_idx < 0)
+ return -ENAVAIL;
+
+ ret = _dpu_rm_pingpong_dsc_check(dsc_idx, pp_idx);
+ if (ret)
+ return -ENAVAIL;
+
+ global_state->dsc_to_enc_id[dsc_idx] = enc_id;
+ num_dsc++;
+ pp_idx++;
+ }
+
+ if (num_dsc < top->num_dsc) {
+ DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n",
+ num_dsc, top->num_dsc);
+ return -ENAVAIL;
+ }
+
+ return 0;
+}
+
+static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm,
+ struct dpu_global_state *global_state,
+ uint32_t enc_id,
+ const struct msm_display_topology *top)
+{
+ int num_dsc = 0;
+ int dsc_idx, pp_idx = 0;
+ int ret;
+
+ /* only start from even dsc index */
+ for (dsc_idx = 0; dsc_idx < ARRAY_SIZE(rm->dsc_blks) &&
+ num_dsc < top->num_dsc; dsc_idx += 2) {
+ if (!rm->dsc_blks[dsc_idx] ||
+ !rm->dsc_blks[dsc_idx + 1])
+ continue;
+
+ /* consective dsc index to be paired */
+ if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) ||
+ reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id))
+ continue;
+
+ pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id);
+ if (pp_idx < 0)
+ return -ENAVAIL;
+
+ ret = _dpu_rm_pingpong_dsc_check(dsc_idx, pp_idx);
+ if (ret) {
+ pp_idx = 0;
+ continue;
}
- if (global_state->dsc_to_enc_id[i]) {
- DPU_ERROR("DSC %d is already allocated\n", i);
- return -EIO;
+ pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id);
+ if (pp_idx < 0)
+ return -ENAVAIL;
+
+ ret = _dpu_rm_pingpong_dsc_check(dsc_idx + 1, pp_idx);
+ if (ret) {
+ pp_idx = 0;
+ continue;
}
+
+ global_state->dsc_to_enc_id[dsc_idx] = enc_id;
+ global_state->dsc_to_enc_id[dsc_idx + 1] = enc_id;
+ num_dsc += 2;
+ pp_idx++; /* start for next pair */
}
- for (i = 0; i < num_dsc; i++)
- global_state->dsc_to_enc_id[i] = enc->base.id;
+ if (num_dsc < top->num_dsc) {
+ DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n",
+ num_dsc, top->num_dsc);
+ return -ENAVAIL;
+ }
+
+ return 0;
+}
+
+static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
+ struct dpu_global_state *global_state,
+ struct drm_encoder *enc,
+ const struct msm_display_topology *top)
+{
+ uint32_t enc_id = enc->base.id;
+
+ if (!top->num_dsc || !top->num_intf)
+ return 0;
+
+ /*
+ * Facts:
+ * 1) no pingpong split (two layer mixers shared one pingpong)
+ * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc
+ * 3) even PINGPONG connects to even DSC
+ * 4) odd PINGPONG connects to odd DSC
+ * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0
+ * +--> pp_idx_1 --> dsc_idx_1
+ */
+
+ /* num_dsc should be either 1, 2 or 4 */
+ if (top->num_dsc > top->num_intf) /* merge mode */
+ return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top);
+ else
+ return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top);
return 0;
}
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_enable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_disable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
TRACE_EVENT(dpu_enc_enable,
TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
TP_printk("id=%u, enable=%s",
__entry->drm_id, __entry->enable ? "true" : "false")
);
-DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
- TP_PROTO(uint32_t drm_id, bool enable),
- TP_ARGS(drm_id, enable)
-);
DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
TP_PROTO(uint32_t drm_id, bool enable),
TP_ARGS(drm_id, enable)
__entry->expected_time, __entry->atomic_cnt)
);
-TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
- TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
+TRACE_EVENT(dpu_enc_phys_cmd_irq_enable,
+ TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp,
int refcnt),
- TP_ARGS(drm_id, pp, enable, refcnt),
+ TP_ARGS(drm_id, pp, refcnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_pingpong, pp )
+ __field( int, refcnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->pp = pp;
+ __entry->refcnt = refcnt;
+ ),
+ TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id,
+ __entry->pp,
+ __entry->refcnt)
+);
+
+TRACE_EVENT(dpu_enc_phys_cmd_irq_disable,
+ TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp,
+ int refcnt),
+ TP_ARGS(drm_id, pp, refcnt),
TP_STRUCT__entry(
__field( uint32_t, drm_id )
__field( enum dpu_pingpong, pp )
- __field( bool, enable )
__field( int, refcnt )
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->pp = pp;
- __entry->enable = enable;
__entry->refcnt = refcnt;
),
- TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
- __entry->pp, __entry->enable ? "true" : "false",
+ TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id,
+ __entry->pp,
__entry->refcnt)
);
TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
);
-TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
- TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
+TRACE_EVENT(dpu_enc_phys_vid_irq_enable,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
int refcnt),
- TP_ARGS(drm_id, intf_idx, enable, refcnt),
+ TP_ARGS(drm_id, intf_idx, refcnt),
+ TP_STRUCT__entry(
+ __field( uint32_t, drm_id )
+ __field( enum dpu_intf, intf_idx )
+ __field( int, refcnt )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intf_idx = intf_idx;
+ __entry->refcnt = refcnt;
+ ),
+ TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id,
+ __entry->intf_idx,
+ __entry->drm_id)
+);
+
+TRACE_EVENT(dpu_enc_phys_vid_irq_disable,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
+ int refcnt),
+ TP_ARGS(drm_id, intf_idx, refcnt),
TP_STRUCT__entry(
__field( uint32_t, drm_id )
__field( enum dpu_intf, intf_idx )
- __field( bool, enable )
__field( int, refcnt )
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->intf_idx = intf_idx;
- __entry->enable = enable;
__entry->refcnt = refcnt;
),
- TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
- __entry->intf_idx, __entry->enable ? "true" : "false",
+ TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id,
+ __entry->intf_idx,
__entry->drm_id)
);
*/
#include <drm/drm_edid.h>
+#include <drm/drm_framebuffer.h>
#include "dpu_writeback.h"
dev->mode_config.max_height);
}
+static int dpu_wb_conn_atomic_check(struct drm_connector *connector,
+ struct drm_atomic_state *state)
+{
+ struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
+ struct dpu_wb_connector *dpu_wb_conn = to_dpu_wb_conn(wb_conn);
+ struct drm_connector_state *conn_state =
+ drm_atomic_get_new_connector_state(state, connector);
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ const struct drm_display_mode *mode;
+ struct drm_framebuffer *fb;
+
+ DPU_DEBUG("[atomic_check:%d]\n", connector->base.id);
+
+ if (!conn_state || !conn_state->connector) {
+ DPU_ERROR("invalid connector state\n");
+ return -EINVAL;
+ } else if (conn_state->connector->status != connector_status_connected) {
+ DPU_ERROR("connector not connected %d\n", conn_state->connector->status);
+ return -EINVAL;
+ }
+
+ crtc = conn_state->crtc;
+ if (!crtc)
+ return 0;
+
+ if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
+ return 0;
+
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ mode = &crtc_state->mode;
+
+ fb = conn_state->writeback_job->fb;
+
+ DPU_DEBUG("[fb_id:%u][fb:%u,%u][mode:\"%s\":%ux%u]\n", fb->base.id, fb->width, fb->height,
+ mode->name, mode->hdisplay, mode->vdisplay);
+
+ if (fb->width != mode->hdisplay) {
+ DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width, mode->hdisplay);
+ return -EINVAL;
+ } else if (fb->height != mode->vdisplay) {
+ DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height, mode->vdisplay);
+ return -EINVAL;
+ } else if (fb->width > dpu_wb_conn->maxlinewidth) {
+ DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
+ fb->width, dpu_wb_conn->maxlinewidth);
+ return -EINVAL;
+ }
+
+ return drm_atomic_helper_check_wb_connector_state(conn_state->connector, conn_state->state);
+}
+
static const struct drm_connector_funcs dpu_wb_conn_funcs = {
.reset = drm_atomic_helper_connector_reset,
.fill_modes = drm_helper_probe_single_connector_modes,
static const struct drm_connector_helper_funcs dpu_wb_conn_helper_funcs = {
.get_modes = dpu_wb_conn_get_modes,
+ .atomic_check = dpu_wb_conn_atomic_check,
.prepare_writeback_job = dpu_wb_conn_prepare_job,
.cleanup_writeback_job = dpu_wb_conn_cleanup_job,
};
int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc,
- const u32 *format_list, u32 num_formats)
+ const u32 *format_list, u32 num_formats, u32 maxlinewidth)
{
struct dpu_wb_connector *dpu_wb_conn;
int rc = 0;
if (!dpu_wb_conn)
return -ENOMEM;
+ dpu_wb_conn->maxlinewidth = maxlinewidth;
+
drm_connector_helper_add(&dpu_wb_conn->base.base, &dpu_wb_conn_helper_funcs);
/* DPU initializes the encoder and sets it up completely for writeback
struct dpu_wb_connector {
struct drm_writeback_connector base;
struct drm_encoder *wb_enc;
+ u32 maxlinewidth;
};
static inline struct dpu_wb_connector *to_dpu_wb_conn(struct drm_writeback_connector *conn)
}
int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc,
- const u32 *format_list, u32 num_formats);
+ const u32 *format_list, u32 num_formats, u32 maxlinewidth);
#endif /*_DPU_WRITEBACK_H */
mdp5_cmd_enc->enabled = true;
}
-
-int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder)
-{
- struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
- struct mdp5_kms *mdp5_kms;
- struct device *dev;
- int intf_num;
- u32 data = 0;
-
- if (!encoder || !slave_encoder)
- return -EINVAL;
-
- mdp5_kms = get_kms(encoder);
- intf_num = mdp5_cmd_enc->intf->num;
-
- /* Switch slave encoder's trigger MUX, to use the master's
- * start signal for the slave encoder
- */
- if (intf_num == 1)
- data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
- else if (intf_num == 2)
- data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
- else
- return -EINVAL;
-
- /* Smart Panel, Sync mode */
- data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL;
-
- dev = &mdp5_kms->pdev->dev;
-
- /* Make sure clocks are on when connectors calling this function. */
- pm_runtime_get_sync(dev);
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data);
-
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
- MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
- pm_runtime_put_sync(dev);
-
- return 0;
-}
#endif /* CONFIG_DRM_MSM_DSI */
return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf));
}
-int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder)
-{
- struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
- struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
- struct mdp5_kms *mdp5_kms;
- struct device *dev;
- int intf_num;
- u32 data = 0;
-
- if (!encoder || !slave_encoder)
- return -EINVAL;
-
- mdp5_kms = get_kms(encoder);
- intf_num = mdp5_encoder->intf->num;
-
- /* Switch slave encoder's TimingGen Sync mode,
- * to use the master's enable signal for the slave encoder.
- */
- if (intf_num == 1)
- data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
- else if (intf_num == 2)
- data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
- else
- return -EINVAL;
-
- dev = &mdp5_kms->pdev->dev;
- /* Make sure clocks are on when connectors calling this function. */
- pm_runtime_get_sync(dev);
-
- /* Dumb Panel, Sync mode */
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
- mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
-
- mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
-
- pm_runtime_put_sync(dev);
-
- return 0;
-}
-
void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode)
{
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
if (dumpstate && __ratelimit(&rs)) {
struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);
drm_state_dump(mdp5_kms->dev, &p);
- if (mdp5_kms->smp)
- mdp5_smp_dump(mdp5_kms->smp, &p);
}
}
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
struct drm_private_state *priv_state;
- int ret;
-
- ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
- if (ret)
- return ERR_PTR(ret);
priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
if (IS_ERR(priv_state))
kfree(mdp5_state);
}
+static void mdp5_global_print_state(struct drm_printer *p,
+ const struct drm_private_state *state)
+{
+ struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
+
+ if (mdp5_state->mdp5_kms->smp)
+ mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state);
+}
+
static const struct drm_private_state_funcs mdp5_global_state_funcs = {
.atomic_duplicate_state = mdp5_global_duplicate_state,
.atomic_destroy_state = mdp5_global_destroy_state,
+ .atomic_print_state = mdp5_global_print_state,
};
static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
{
struct mdp5_global_state *state;
- drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
-
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
}
-static int mdp5_set_split_display(struct msm_kms *kms,
- struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder,
- bool is_cmd_mode)
-{
- if (is_cmd_mode)
- return mdp5_cmd_encoder_set_split_display(encoder,
- slave_encoder);
- else
- return mdp5_vid_encoder_set_split_display(encoder,
- slave_encoder);
-}
-
static void mdp5_destroy(struct mdp5_kms *mdp5_kms);
static void mdp5_kms_destroy(struct msm_kms *kms)
mdp5_destroy(mdp5_kms);
}
-#ifdef CONFIG_DEBUG_FS
-static int smp_show(struct seq_file *m, void *arg)
-{
- struct drm_info_node *node = m->private;
- struct drm_device *dev = node->minor->dev;
- struct msm_drm_private *priv = dev->dev_private;
- struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
- struct drm_printer p = drm_seq_file_printer(m);
-
- if (!mdp5_kms->smp) {
- drm_printf(&p, "no SMP pool\n");
- return 0;
- }
-
- mdp5_smp_dump(mdp5_kms->smp, &p);
-
- return 0;
-}
-
-static struct drm_info_list mdp5_debugfs_list[] = {
- {"smp", smp_show },
-};
-
-static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
-{
- drm_debugfs_create_files(mdp5_debugfs_list,
- ARRAY_SIZE(mdp5_debugfs_list),
- minor->debugfs_root, minor);
-
- return 0;
-}
-#endif
-
static const struct mdp_kms_funcs kms_funcs = {
.base = {
.hw_init = mdp5_hw_init,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
.get_format = mdp_get_format,
- .set_split_display = mdp5_set_split_display,
.destroy = mdp5_kms_destroy,
-#ifdef CONFIG_DEBUG_FS
- .debugfs_init = mdp5_kms_debugfs_init,
-#endif
},
.set_irqmask = mdp5_set_irqmask,
};
pm_runtime_disable(&mdp5_kms->pdev->dev);
drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
- drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
}
static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
DBG("");
+ if (!msm_disp_drv_should_bind(&pdev->dev, false))
+ return -ENODEV;
+
mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
if (!mdp5_kms)
return -ENOMEM;
* Global private object state, Do not access directly, use
* mdp5_global_get_state()
*/
- struct drm_modeset_lock glob_state_lock;
struct drm_private_obj glob_state;
struct mdp5_smp *smp;
struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
-int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder);
void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
struct drm_display_mode *adjusted_mode);
void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
-int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder);
#else
static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
{
}
-static inline int mdp5_cmd_encoder_set_split_display(
- struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
-{
- return -EINVAL;
-}
#endif
#endif /* __MDP5_KMS_H__ */
state->released = 0;
}
-void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p)
+void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
+ struct mdp5_global_state *global_state)
{
struct mdp5_kms *mdp5_kms = get_kms(smp);
struct mdp5_hw_pipe_state *hwpstate;
struct mdp5_smp_state *state;
- struct mdp5_global_state *global_state;
int total = 0, i, j;
drm_printf(p, "name\tinuse\tplane\n");
drm_printf(p, "----\t-----\t-----\n");
- if (drm_can_sleep())
- drm_modeset_lock(&mdp5_kms->glob_state_lock, NULL);
-
- global_state = mdp5_get_existing_global_state(mdp5_kms);
-
/* grab these *after* we hold the state_lock */
hwpstate = &global_state->hwpipe;
state = &global_state->smp;
drm_printf(p, "TOTAL:\t%d\t(of %d)\n", total, smp->blk_cnt);
drm_printf(p, "AVAIL:\t%d\n", smp->blk_cnt -
bitmap_weight(state->state, smp->blk_cnt));
-
- if (drm_can_sleep())
- drm_modeset_unlock(&mdp5_kms->glob_state_lock);
}
struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,
const struct mdp5_smp_block *cfg);
-void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p);
+struct mdp5_global_state;
+void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
+ struct mdp5_global_state *global_state);
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
const struct mdp_format *format,
*/
#include <linux/delay.h>
+#include <linux/phy/phy.h>
#include <drm/drm_print.h>
#include "dp_reg.h"
struct device *dev;
struct dp_catalog *catalog;
+ struct phy *phy;
+
struct mutex mutex;
struct completion comp;
if (aux->native) {
aux->retry_cnt++;
if (!(aux->retry_cnt % MAX_AUX_RETRIES))
- dp_catalog_aux_update_cfg(aux->catalog);
+ phy_calibrate(aux->phy);
}
/* reset aux if link is in connected state */
if (dp_catalog_link_is_connected(aux->catalog))
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
- dp_catalog_aux_update_cfg(aux->catalog);
+ phy_calibrate(aux->phy);
dp_catalog_aux_reset(aux->catalog);
}
}
struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,
+ struct phy *phy,
bool is_edp)
{
struct dp_aux_private *aux;
aux->dev = dev;
aux->catalog = catalog;
+ aux->phy = phy;
aux->retry_cnt = 0;
/*
void dp_aux_deinit(struct drm_dp_aux *dp_aux);
void dp_aux_reconfig(struct drm_dp_aux *dp_aux);
+struct phy;
struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,
+ struct phy *phy,
bool is_edp);
void dp_aux_put(struct drm_dp_aux *aux);
#include <linux/delay.h>
#include <linux/iopoll.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-dp.h>
+#include <linux/platform_device.h>
#include <linux/rational.h>
#include <drm/display/drm_dp_helper.h>
#include <drm/drm_print.h>
(PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
+#define DP_DEFAULT_AHB_OFFSET 0x0000
+#define DP_DEFAULT_AHB_SIZE 0x0200
+#define DP_DEFAULT_AUX_OFFSET 0x0200
+#define DP_DEFAULT_AUX_SIZE 0x0200
+#define DP_DEFAULT_LINK_OFFSET 0x0400
+#define DP_DEFAULT_LINK_SIZE 0x0C00
+#define DP_DEFAULT_P0_OFFSET 0x1000
+#define DP_DEFAULT_P0_SIZE 0x0400
+
+struct dss_io_region {
+ size_t len;
+ void __iomem *base;
+};
+
+struct dss_io_data {
+ struct dss_io_region ahb;
+ struct dss_io_region aux;
+ struct dss_io_region link;
+ struct dss_io_region p0;
+};
+
struct dp_catalog_private {
struct device *dev;
struct drm_device *drm_dev;
- struct dp_io *io;
+ struct dss_io_data io;
u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
struct dp_catalog dp_catalog;
u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- struct dss_io_data *dss = &catalog->io->dp_controller;
+ struct dss_io_data *dss = &catalog->io;
msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb");
msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_aux");
static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset)
{
- return readl_relaxed(catalog->io->dp_controller.aux.base + offset);
+ return readl_relaxed(catalog->io.aux.base + offset);
}
static inline void dp_write_aux(struct dp_catalog_private *catalog,
* To make sure aux reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->dp_controller.aux.base + offset);
+ writel(data, catalog->io.aux.base + offset);
}
static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset)
{
- return readl_relaxed(catalog->io->dp_controller.ahb.base + offset);
+ return readl_relaxed(catalog->io.ahb.base + offset);
}
static inline void dp_write_ahb(struct dp_catalog_private *catalog,
* To make sure phy reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->dp_controller.ahb.base + offset);
+ writel(data, catalog->io.ahb.base + offset);
}
static inline void dp_write_p0(struct dp_catalog_private *catalog,
* To make sure interface reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->dp_controller.p0.base + offset);
+ writel(data, catalog->io.p0.base + offset);
}
static inline u32 dp_read_p0(struct dp_catalog_private *catalog,
* To make sure interface reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- return readl_relaxed(catalog->io->dp_controller.p0.base + offset);
+ return readl_relaxed(catalog->io.p0.base + offset);
}
static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset)
{
- return readl_relaxed(catalog->io->dp_controller.link.base + offset);
+ return readl_relaxed(catalog->io.link.base + offset);
}
static inline void dp_write_link(struct dp_catalog_private *catalog,
* To make sure link reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->dp_controller.link.base + offset);
+ writel(data, catalog->io.link.base + offset);
}
/* aux related catalog functions */
dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
}
-void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog)
-{
- struct dp_catalog_private *catalog = container_of(dp_catalog,
- struct dp_catalog_private, dp_catalog);
- struct dp_io *dp_io = catalog->io;
- struct phy *phy = dp_io->phy;
-
- phy_calibrate(phy);
-}
-
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog)
{
u32 state;
struct dp_catalog_private, dp_catalog);
/* poll for hpd connected status every 2ms and timeout after 500ms */
- return readl_poll_timeout(catalog->io->dp_controller.aux.base +
+ return readl_poll_timeout(catalog->io.aux.base +
REG_DP_DP_HPD_INT_STATUS,
state, state & DP_DP_HPD_STATE_STATUS_CONNECTED,
2000, 500000);
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- struct dss_io_data *io = &catalog->io->dp_controller;
+ struct dss_io_data *io = &catalog->io;
pr_info("AHB regs\n");
dump_regs(io->ahb.base, io->ahb.len);
bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
/* Poll for mainlink ready status */
- ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base +
+ ret = readx_poll_timeout(readl, catalog->io.link.base +
REG_DP_MAINLINK_READY,
data, data & bit,
POLLING_SLEEP_US, POLLING_TIMEOUT_US);
struct dp_catalog_private, dp_catalog);
/* Poll for mainlink ready status */
- ret = readl_poll_timeout(catalog->io->dp_controller.link.base +
+ ret = readl_poll_timeout(catalog->io.link.base +
REG_DP_MAINLINK_READY,
data, data & DP_MAINLINK_READY_FOR_VIDEO,
POLLING_SLEEP_US, POLLING_TIMEOUT_US);
dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0);
}
-int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog,
- u8 v_level, u8 p_level)
-{
- struct dp_catalog_private *catalog = container_of(dp_catalog,
- struct dp_catalog_private, dp_catalog);
- struct dp_io *dp_io = catalog->io;
- struct phy *phy = dp_io->phy;
- struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
-
- /* TODO: Update for all lanes instead of just first one */
- opts_dp->voltage[0] = v_level;
- opts_dp->pre[0] = p_level;
- opts_dp->set_voltages = 1;
- phy_configure(phy, &dp_io->phy_opts);
- opts_dp->set_voltages = 0;
-
- return 0;
-}
-
void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
u32 pattern)
{
dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);
}
-struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io)
+static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len)
{
- struct dp_catalog_private *catalog;
+ struct resource *res;
+ void __iomem *base;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, idx, &res);
+ if (!IS_ERR(base))
+ *len = resource_size(res);
- if (!io) {
- DRM_ERROR("invalid input\n");
- return ERR_PTR(-EINVAL);
+ return base;
+}
+
+static int dp_catalog_get_io(struct dp_catalog_private *catalog)
+{
+ struct platform_device *pdev = to_platform_device(catalog->dev);
+ struct dss_io_data *dss = &catalog->io;
+
+ dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len);
+ if (IS_ERR(dss->ahb.base))
+ return PTR_ERR(dss->ahb.base);
+
+ dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len);
+ if (IS_ERR(dss->aux.base)) {
+ /*
+ * The initial binding had a single reg, but in order to
+ * support variation in the sub-region sizes this was split.
+ * dp_ioremap() will fail with -EINVAL here if only a single
+ * reg is specified, so fill in the sub-region offsets and
+ * lengths based on this single region.
+ */
+ if (PTR_ERR(dss->aux.base) == -EINVAL) {
+ if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {
+ DRM_ERROR("legacy memory region not large enough\n");
+ return -EINVAL;
+ }
+
+ dss->ahb.len = DP_DEFAULT_AHB_SIZE;
+ dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET;
+ dss->aux.len = DP_DEFAULT_AUX_SIZE;
+ dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET;
+ dss->link.len = DP_DEFAULT_LINK_SIZE;
+ dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET;
+ dss->p0.len = DP_DEFAULT_P0_SIZE;
+ } else {
+ DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base);
+ return PTR_ERR(dss->aux.base);
+ }
+ } else {
+ dss->link.base = dp_ioremap(pdev, 2, &dss->link.len);
+ if (IS_ERR(dss->link.base)) {
+ DRM_ERROR("unable to remap link region: %pe\n", dss->link.base);
+ return PTR_ERR(dss->link.base);
+ }
+
+ dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len);
+ if (IS_ERR(dss->p0.base)) {
+ DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base);
+ return PTR_ERR(dss->p0.base);
+ }
}
+ return 0;
+}
+
+struct dp_catalog *dp_catalog_get(struct device *dev)
+{
+ struct dp_catalog_private *catalog;
+ int ret;
+
catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
if (!catalog)
return ERR_PTR(-ENOMEM);
catalog->dev = dev;
- catalog->io = io;
+
+ ret = dp_catalog_get_io(catalog);
+ if (ret)
+ return ERR_PTR(ret);
return &catalog->dp_catalog;
}
#include <drm/drm_modes.h>
-#include "dp_parser.h"
#include "disp/msm_disp_snapshot.h"
/* interrupts */
int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog);
void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
-void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog);
u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
-int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
- u8 p_level);
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
struct drm_display_mode *drm_mode);
void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog);
-struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io);
+struct dp_catalog *dp_catalog_get(struct device *dev);
/* DP Audio APIs */
void dp_catalog_audio_get_header(struct dp_catalog *catalog);
struct drm_dp_aux *aux;
struct dp_panel *panel;
struct dp_link *link;
- struct dp_power *power;
- struct dp_parser *parser;
struct dp_catalog *catalog;
+ struct phy *phy;
+
+ unsigned int num_core_clks;
+ struct clk_bulk_data *core_clks;
+
+ unsigned int num_link_clks;
+ struct clk_bulk_data *link_clks;
+
+ struct clk *pixel_clk;
+
+ union phy_configure_opts phy_opts;
+
struct completion idle_comp;
struct completion psr_op_comp;
struct completion video_comp;
+
+ bool core_clks_on;
+ bool link_clks_on;
+ bool stream_clks_on;
};
static int dp_aux_link_configure(struct drm_dp_aux *aux,
return ret;
}
+static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl,
+ u8 v_level, u8 p_level)
+{
+ union phy_configure_opts *phy_opts = &ctrl->phy_opts;
+
+ /* TODO: Update for all lanes instead of just first one */
+ phy_opts->dp.voltage[0] = v_level;
+ phy_opts->dp.pre[0] = p_level;
+ phy_opts->dp.set_voltages = 1;
+ phy_configure(ctrl->phy, phy_opts);
+ phy_opts->dp.set_voltages = 0;
+
+ return 0;
+}
+
static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
{
struct dp_link *link = ctrl->link;
drm_dbg_dp(ctrl->drm_dev,
"voltage level: %d emphasis level: %d\n",
voltage_swing_level, pre_emphasis_level);
- ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
+ ret = dp_ctrl_set_vx_px(ctrl,
voltage_swing_level, pre_emphasis_level);
if (ret)
return ret;
}
-static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
- enum dp_pm_type module, char *name, unsigned long rate)
+int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl)
{
- u32 num = ctrl->parser->mp[module].num_clk;
- struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks;
+ struct dp_ctrl_private *ctrl;
+ int ret = 0;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- while (num && strcmp(cfg->id, name)) {
- num--;
- cfg++;
+ if (ctrl->core_clks_on) {
+ drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n");
+ return 0;
}
- drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
- rate, name);
+ ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks);
+ if (ret)
+ return ret;
- if (num)
- clk_set_rate(cfg->clk, rate);
- else
- DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
- name, rate);
+ ctrl->core_clks_on = true;
+
+ drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n");
+ drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
+ ctrl->stream_clks_on ? "on" : "off",
+ ctrl->link_clks_on ? "on" : "off",
+ ctrl->core_clks_on ? "on" : "off");
+
+ return 0;
+}
+
+void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl)
+{
+ struct dp_ctrl_private *ctrl;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks);
+
+ ctrl->core_clks_on = false;
+
+ drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n");
+ drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
+ ctrl->stream_clks_on ? "on" : "off",
+ ctrl->link_clks_on ? "on" : "off",
+ ctrl->core_clks_on ? "on" : "off");
+}
+
+static int dp_ctrl_link_clk_enable(struct dp_ctrl *dp_ctrl)
+{
+ struct dp_ctrl_private *ctrl;
+ int ret = 0;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ if (ctrl->link_clks_on) {
+ drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n");
+ return 0;
+ }
+
+ if (!ctrl->core_clks_on) {
+ drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n");
+
+ dp_ctrl_core_clk_enable(dp_ctrl);
+ }
+
+ ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks);
+ if (ret)
+ return ret;
+
+ ctrl->link_clks_on = true;
+
+ drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n");
+ drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
+ ctrl->stream_clks_on ? "on" : "off",
+ ctrl->link_clks_on ? "on" : "off",
+ ctrl->core_clks_on ? "on" : "off");
+
+ return 0;
+}
+
+static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl)
+{
+ struct dp_ctrl_private *ctrl;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks);
+
+ ctrl->link_clks_on = false;
+
+ drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n");
+ drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
+ ctrl->stream_clks_on ? "on" : "off",
+ ctrl->link_clks_on ? "on" : "off",
+ ctrl->core_clks_on ? "on" : "off");
}
static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
{
int ret = 0;
- struct dp_io *dp_io = &ctrl->parser->io;
- struct phy *phy = dp_io->phy;
- struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
+ struct phy *phy = ctrl->phy;
const u8 *dpcd = ctrl->panel->dpcd;
- opts_dp->lanes = ctrl->link->link_params.num_lanes;
- opts_dp->link_rate = ctrl->link->link_params.rate / 100;
- opts_dp->ssc = drm_dp_max_downspread(dpcd);
+ ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
+ ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100;
+ ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd);
- phy_configure(phy, &dp_io->phy_opts);
+ phy_configure(phy, &ctrl->phy_opts);
phy_power_on(phy);
dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
+ ret = dp_ctrl_link_clk_enable(&ctrl->dp_ctrl);
if (ret)
DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
- struct dp_io *dp_io;
struct phy *phy;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
dp_catalog_ctrl_phy_reset(ctrl->catalog);
phy_init(phy);
void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
- struct dp_io *dp_io;
struct phy *phy;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
dp_catalog_ctrl_phy_reset(ctrl->catalog);
phy_exit(phy);
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
+ struct phy *phy = ctrl->phy;
int ret = 0;
- struct dp_io *dp_io = &ctrl->parser->io;
- struct phy *phy = dp_io->phy;
- struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- opts_dp->lanes = ctrl->link->link_params.num_lanes;
- phy_configure(phy, &dp_io->phy_opts);
+ ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
+ phy_configure(phy, &ctrl->phy_opts);
/*
* Disable and re-enable the mainlink clock since the
* link clock might have been adjusted as part of the
* link maintenance.
*/
dev_pm_opp_set_rate(ctrl->dev, 0);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
- return ret;
- }
+
+ dp_ctrl_link_clk_disable(&ctrl->dp_ctrl);
+
phy_power_off(phy);
/* hw recommended delay before re-enabling clocks */
msleep(20);
static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
- struct dp_io *dp_io;
struct phy *phy;
- int ret;
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
dp_catalog_ctrl_reset(ctrl->catalog);
dev_pm_opp_set_rate(ctrl->dev, 0);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
- }
+ dp_ctrl_link_clk_disable(&ctrl->dp_ctrl);
phy_power_off(phy);
drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
- if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
+ if (dp_ctrl_set_vx_px(ctrl,
ctrl->link->phy_params.v_level,
ctrl->link->phy_params.p_level)) {
DRM_ERROR("Failed to set v/p levels\n");
* running. Add the global reset just before disabling the
* link clocks and core clocks.
*/
- ret = dp_ctrl_off(&ctrl->dp_ctrl);
- if (ret) {
- DRM_ERROR("failed to disable DP controller\n");
- return ret;
- }
+ dp_ctrl_off(&ctrl->dp_ctrl);
ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
if (ret) {
}
pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
- dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
-
- ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
+ ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
if (ret) {
- DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+ DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
return ret;
}
+ if (ctrl->stream_clks_on) {
+ drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
+ } else {
+ ret = clk_prepare_enable(ctrl->pixel_clk);
+ if (ret) {
+ DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+ return ret;
+ }
+ ctrl->stream_clks_on = true;
+ }
+
dp_ctrl_send_phy_test_pattern(ctrl);
return 0;
rate = ctrl->panel->link_info.rate;
pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
- dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
+ dp_ctrl_core_clk_enable(&ctrl->dp_ctrl);
if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
drm_dbg_dp(ctrl->drm_dev,
ctrl->link->link_params.rate,
ctrl->link->link_params.num_lanes, pixel_rate);
- if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
+ drm_dbg_dp(ctrl->drm_dev,
+ "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n",
+ ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on);
+
+ if (!ctrl->link_clks_on) { /* link clk is off */
ret = dp_ctrl_enable_mainlink_clocks(ctrl);
if (ret) {
DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
}
}
- dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
-
- ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
+ ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
if (ret) {
- DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret);
+ DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
goto end;
}
+ if (ctrl->stream_clks_on) {
+ drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
+ } else {
+ ret = clk_prepare_enable(ctrl->pixel_clk);
+ if (ret) {
+ DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+ goto end;
+ }
+ ctrl->stream_clks_on = true;
+ }
+
if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
dp_ctrl_link_retrain(ctrl);
return ret;
}
-int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
+void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
- struct dp_io *dp_io;
struct phy *phy;
- int ret;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
/* set dongle to D3 (power off) mode */
dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
- ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
- return ret;
- }
+ if (ctrl->stream_clks_on) {
+ clk_disable_unprepare(ctrl->pixel_clk);
+ ctrl->stream_clks_on = false;
}
dev_pm_opp_set_rate(ctrl->dev, 0);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
- return ret;
- }
+ dp_ctrl_link_clk_disable(&ctrl->dp_ctrl);
phy_power_off(phy);
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
phy, phy->init_count, phy->power_count);
- return ret;
}
-int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
+void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
- struct dp_io *dp_io;
struct phy *phy;
- int ret;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
- }
+ dp_ctrl_link_clk_disable(&ctrl->dp_ctrl);
DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
phy, phy->init_count, phy->power_count);
DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
phy, phy->init_count, phy->power_count);
-
- return ret;
}
-int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
+void dp_ctrl_off(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
- struct dp_io *dp_io;
struct phy *phy;
- int ret = 0;
-
- if (!dp_ctrl)
- return -EINVAL;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
- dp_io = &ctrl->parser->io;
- phy = dp_io->phy;
+ phy = ctrl->phy;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
dp_catalog_ctrl_reset(ctrl->catalog);
- ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
- if (ret)
- DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
+ if (ctrl->stream_clks_on) {
+ clk_disable_unprepare(ctrl->pixel_clk);
+ ctrl->stream_clks_on = false;
+ }
dev_pm_opp_set_rate(ctrl->dev, 0);
- ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
- if (ret) {
- DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
- }
+ dp_ctrl_link_clk_disable(&ctrl->dp_ctrl);
phy_power_off(phy);
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
phy, phy->init_count, phy->power_count);
-
- return ret;
}
irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
return ret;
}
+static const char *core_clks[] = {
+ "core_iface",
+ "core_aux",
+};
+
+static const char *ctrl_clks[] = {
+ "ctrl_link",
+ "ctrl_link_iface",
+};
+
+static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl)
+{
+ struct dp_ctrl_private *ctrl;
+ struct device *dev;
+ int i, rc;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ dev = ctrl->dev;
+
+ ctrl->num_core_clks = ARRAY_SIZE(core_clks);
+ ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL);
+ if (!ctrl->core_clks)
+ return -ENOMEM;
+
+ for (i = 0; i < ctrl->num_core_clks; i++)
+ ctrl->core_clks[i].id = core_clks[i];
+
+ rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks);
+ if (rc)
+ return rc;
+
+ ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks);
+ ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL);
+ if (!ctrl->link_clks)
+ return -ENOMEM;
+
+ for (i = 0; i < ctrl->num_link_clks; i++)
+ ctrl->link_clks[i].id = ctrl_clks[i];
+
+ rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks);
+ if (rc)
+ return rc;
+
+ ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel");
+ if (IS_ERR(ctrl->pixel_clk))
+ return PTR_ERR(ctrl->pixel_clk);
+
+ return 0;
+}
+
struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
struct dp_panel *panel, struct drm_dp_aux *aux,
- struct dp_power *power, struct dp_catalog *catalog,
- struct dp_parser *parser)
+ struct dp_catalog *catalog,
+ struct phy *phy)
{
struct dp_ctrl_private *ctrl;
int ret;
init_completion(&ctrl->video_comp);
/* in parameters */
- ctrl->parser = parser;
ctrl->panel = panel;
- ctrl->power = power;
ctrl->aux = aux;
ctrl->link = link;
ctrl->catalog = catalog;
ctrl->dev = dev;
+ ctrl->phy = phy;
+
+ ret = dp_ctrl_clk_init(&ctrl->dp_ctrl);
+ if (ret) {
+ dev_err(dev, "failed to init clocks\n");
+ return ERR_PTR(ret);
+ }
return &ctrl->dp_ctrl;
}
#include "dp_aux.h"
#include "dp_panel.h"
#include "dp_link.h"
-#include "dp_parser.h"
-#include "dp_power.h"
#include "dp_catalog.h"
struct dp_ctrl {
bool wide_bus_en;
};
+struct phy;
+
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train);
-int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
-int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl);
-int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_off(struct dp_ctrl *dp_ctrl);
void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl);
irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl);
void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl);
struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
struct dp_panel *panel, struct drm_dp_aux *aux,
- struct dp_power *power, struct dp_catalog *catalog,
- struct dp_parser *parser);
+ struct dp_catalog *catalog,
+ struct phy *phy);
void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable);
void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl);
void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
+int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl);
+
#endif /* _DP_CTRL_H_ */
#include <drm/drm_connector.h>
#include <drm/drm_file.h>
-#include "dp_parser.h"
#include "dp_catalog.h"
#include "dp_aux.h"
#include "dp_ctrl.h"
seq_printf(m, "vdisplay: %d\n",
debug->link->test_video.test_v_height);
seq_printf(m, "bpc: %u\n",
- dp_link_bit_depth_to_bpc(bpc));
+ dp_link_bit_depth_to_bpp(bpc) / 3);
} else {
seq_puts(m, "0");
}
#include <linux/debugfs.h>
#include <linux/component.h>
#include <linux/of_irq.h>
+#include <linux/phy/phy.h>
#include <linux/delay.h>
#include <drm/display/drm_dp_aux_bus.h>
#include <drm/drm_edid.h>
#include "msm_drv.h"
#include "msm_kms.h"
-#include "dp_parser.h"
-#include "dp_power.h"
+#include "dp_ctrl.h"
#include "dp_catalog.h"
#include "dp_aux.h"
#include "dp_reg.h"
#include "dp_link.h"
#include "dp_panel.h"
-#include "dp_ctrl.h"
#include "dp_display.h"
#include "dp_drm.h"
#include "dp_audio.h"
struct drm_device *drm_dev;
struct dentry *root;
- struct dp_parser *parser;
- struct dp_power *power;
struct dp_catalog *catalog;
struct drm_dp_aux *aux;
struct dp_link *link;
int rc = 0;
struct edid *edid;
- dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
- dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
-
- drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
- dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
-
rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
if (rc)
goto end;
dp->audio_supported = drm_detect_monitor_audio(edid);
dp_panel_handle_sink_request(dp->panel);
- dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
-
/*
* set sink to normal operation mode -- D0
* before dpcd read
dp->dp_display.connector_type, dp->core_initialized,
dp->phy_initialized);
- dp_power_init(dp->power);
+ dp_ctrl_core_clk_enable(dp->ctrl);
dp_ctrl_reset_irq_ctrl(dp->ctrl, true);
dp_aux_init(dp->aux);
dp->core_initialized = true;
dp_ctrl_reset_irq_ctrl(dp->ctrl, false);
dp_aux_deinit(dp->aux);
- dp_power_deinit(dp->power);
+ dp_ctrl_core_clk_disable(dp->ctrl);
dp->core_initialized = false;
}
struct dp_panel_in panel_in = {
.dev = dev,
};
+ struct phy *phy;
- dp->parser = dp_parser_get(dp->dp_display.pdev);
- if (IS_ERR(dp->parser)) {
- rc = PTR_ERR(dp->parser);
- DRM_ERROR("failed to initialize parser, rc = %d\n", rc);
- dp->parser = NULL;
- goto error;
- }
+ phy = devm_phy_get(dev, "dp");
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
- dp->catalog = dp_catalog_get(dev, &dp->parser->io);
+ dp->catalog = dp_catalog_get(dev);
if (IS_ERR(dp->catalog)) {
rc = PTR_ERR(dp->catalog);
DRM_ERROR("failed to initialize catalog, rc = %d\n", rc);
goto error;
}
- dp->power = dp_power_get(dev, dp->parser);
- if (IS_ERR(dp->power)) {
- rc = PTR_ERR(dp->power);
- DRM_ERROR("failed to initialize power, rc = %d\n", rc);
- dp->power = NULL;
- goto error;
- }
-
- dp->aux = dp_aux_get(dev, dp->catalog, dp->dp_display.is_edp);
+ dp->aux = dp_aux_get(dev, dp->catalog,
+ phy,
+ dp->dp_display.is_edp);
if (IS_ERR(dp->aux)) {
rc = PTR_ERR(dp->aux);
DRM_ERROR("failed to initialize aux, rc = %d\n", rc);
}
dp->ctrl = dp_ctrl_get(dev, dp->link, dp->panel, dp->aux,
- dp->power, dp->catalog, dp->parser);
+ dp->catalog,
+ phy);
if (IS_ERR(dp->ctrl)) {
rc = PTR_ERR(dp->ctrl);
DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc);
return NULL;
}
-static int dp_display_get_next_bridge(struct msm_dp *dp);
-
static int dp_display_probe_tail(struct device *dev)
{
struct msm_dp *dp = dev_get_drvdata(dev);
int ret;
- ret = dp_display_get_next_bridge(dp);
- if (ret)
- return ret;
+ /*
+ * External bridges are mandatory for eDP interfaces: one has to
+ * provide at least an eDP panel (which gets wrapped into panel-bridge).
+ *
+ * For DisplayPort interfaces external bridges are optional, so
+ * silently ignore an error if one is not present (-ENODEV).
+ */
+ dp->next_bridge = devm_drm_of_get_bridge(&dp->pdev->dev, dp->pdev->dev.of_node, 1, 0);
+ if (IS_ERR(dp->next_bridge)) {
+ ret = PTR_ERR(dp->next_bridge);
+ dp->next_bridge = NULL;
+ if (dp->is_edp || ret != -ENODEV)
+ return ret;
+ }
ret = component_add(dev, &dp_display_comp_ops);
if (ret)
return -EPROBE_DEFER;
}
- rc = dp->parser->parse(dp->parser);
- if (rc) {
- DRM_ERROR("device tree parsing failed\n");
- goto err;
- }
-
- rc = dp_power_client_init(dp->power);
- if (rc) {
- DRM_ERROR("Power client create failed\n");
- goto err;
- }
-
/* setup event q */
mutex_init(&dp->event_mutex);
init_waitqueue_head(&dp->event_q);
}
}
-static int dp_display_get_next_bridge(struct msm_dp *dp)
-{
- int rc;
- struct dp_display_private *dp_priv;
-
- dp_priv = container_of(dp, struct dp_display_private, dp_display);
-
- /*
- * External bridges are mandatory for eDP interfaces: one has to
- * provide at least an eDP panel (which gets wrapped into panel-bridge).
- *
- * For DisplayPort interfaces external bridges are optional, so
- * silently ignore an error if one is not present (-ENODEV).
- */
- rc = devm_dp_parser_find_next_bridge(&dp->pdev->dev, dp_priv->parser);
- if (!dp->is_edp && rc == -ENODEV)
- return 0;
-
- if (!rc)
- dp->next_bridge = dp_priv->parser->next_bridge;
-
- return rc;
-}
-
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder)
{
#include <sound/hdmi-codec.h>
#include "disp/msm_disp_snapshot.h"
+#define DP_MAX_PIXEL_CLK_KHZ 675000
+
struct msm_dp {
struct drm_device *drm_dev;
struct platform_device *pdev;
bool wide_bus_en;
- u32 max_dp_lanes;
struct dp_audio *dp_audio;
bool psr_supported;
};
}
}
-/**
- * dp_test_bit_depth_to_bpc() - convert test bit depth to bpc
- * @tbd: test bit depth
- *
- * Returns the bits per comp (bpc) to be used corresponding to the
- * bit depth value. This function assumes that bit depth has
- * already been validated.
- */
-static inline u32 dp_link_bit_depth_to_bpc(u32 tbd)
-{
- switch (tbd) {
- case DP_TEST_BIT_DEPTH_6:
- return 6;
- case DP_TEST_BIT_DEPTH_8:
- return 8;
- case DP_TEST_BIT_DEPTH_10:
- return 10;
- case DP_TEST_BIT_DEPTH_UNKNOWN:
- default:
- return 0;
- }
-}
-
void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link);
u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp);
int dp_link_process_request(struct dp_link *dp_link);
#include <drm/drm_connector.h>
#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
#include <drm/drm_print.h>
+#define DP_MAX_NUM_DP_LANES 4
+#define DP_LINK_RATE_HBR2 540000 /* kbytes */
+
struct dp_panel_private {
struct device *dev;
struct drm_device *drm_dev;
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
+ drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
+ dp_panel->max_dp_lanes, dp_panel->max_dp_link_rate);
+
rc = dp_panel_read_dpcd(dp_panel);
if (rc) {
DRM_ERROR("read dpcd failed %d\n", rc);
return 0;
}
+static u32 dp_panel_link_frequencies(struct device_node *of_node)
+{
+ struct device_node *endpoint;
+ u64 frequency = 0;
+ int cnt;
+
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
+ if (!endpoint)
+ return 0;
+
+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+
+ if (cnt > 0)
+ of_property_read_u64_index(endpoint, "link-frequencies",
+ cnt - 1, &frequency);
+ of_node_put(endpoint);
+
+ do_div(frequency,
+ 10 * /* from symbol rate to link rate */
+ 1000); /* kbytes */
+
+ return frequency;
+}
+
+static int dp_panel_parse_dt(struct dp_panel *dp_panel)
+{
+ struct dp_panel_private *panel;
+ struct device_node *of_node;
+ int cnt;
+
+ panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
+ of_node = panel->dev->of_node;
+
+ /*
+ * data-lanes is the property of dp_out endpoint
+ */
+ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
+ if (cnt < 0) {
+ /* legacy code, data-lanes is the property of mdss_dp node */
+ cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
+ }
+
+ if (cnt > 0)
+ dp_panel->max_dp_lanes = cnt;
+ else
+ dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
+
+ dp_panel->max_dp_link_rate = dp_panel_link_frequencies(of_node);
+ if (!dp_panel->max_dp_link_rate)
+ dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2;
+
+ return 0;
+}
+
struct dp_panel *dp_panel_get(struct dp_panel_in *in)
{
struct dp_panel_private *panel;
struct dp_panel *dp_panel;
+ int ret;
if (!in->dev || !in->catalog || !in->aux || !in->link) {
DRM_ERROR("invalid input\n");
dp_panel = &panel->dp_panel;
dp_panel->max_bw_code = DP_LINK_BW_8_1;
+ ret = dp_panel_parse_dt(dp_panel);
+ if (ret)
+ return ERR_PTR(ret);
+
return dp_panel;
}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
- */
-
-#include <linux/of_gpio.h>
-#include <linux/phy/phy.h>
-
-#include <drm/drm_of.h>
-#include <drm/drm_print.h>
-#include <drm/drm_bridge.h>
-
-#include "dp_parser.h"
-#include "dp_reg.h"
-
-#define DP_DEFAULT_AHB_OFFSET 0x0000
-#define DP_DEFAULT_AHB_SIZE 0x0200
-#define DP_DEFAULT_AUX_OFFSET 0x0200
-#define DP_DEFAULT_AUX_SIZE 0x0200
-#define DP_DEFAULT_LINK_OFFSET 0x0400
-#define DP_DEFAULT_LINK_SIZE 0x0C00
-#define DP_DEFAULT_P0_OFFSET 0x1000
-#define DP_DEFAULT_P0_SIZE 0x0400
-
-static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len)
-{
- struct resource *res;
- void __iomem *base;
-
- base = devm_platform_get_and_ioremap_resource(pdev, idx, &res);
- if (!IS_ERR(base))
- *len = resource_size(res);
-
- return base;
-}
-
-static int dp_parser_ctrl_res(struct dp_parser *parser)
-{
- struct platform_device *pdev = parser->pdev;
- struct dp_io *io = &parser->io;
- struct dss_io_data *dss = &io->dp_controller;
-
- dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len);
- if (IS_ERR(dss->ahb.base))
- return PTR_ERR(dss->ahb.base);
-
- dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len);
- if (IS_ERR(dss->aux.base)) {
- /*
- * The initial binding had a single reg, but in order to
- * support variation in the sub-region sizes this was split.
- * dp_ioremap() will fail with -EINVAL here if only a single
- * reg is specified, so fill in the sub-region offsets and
- * lengths based on this single region.
- */
- if (PTR_ERR(dss->aux.base) == -EINVAL) {
- if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {
- DRM_ERROR("legacy memory region not large enough\n");
- return -EINVAL;
- }
-
- dss->ahb.len = DP_DEFAULT_AHB_SIZE;
- dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET;
- dss->aux.len = DP_DEFAULT_AUX_SIZE;
- dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET;
- dss->link.len = DP_DEFAULT_LINK_SIZE;
- dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET;
- dss->p0.len = DP_DEFAULT_P0_SIZE;
- } else {
- DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base);
- return PTR_ERR(dss->aux.base);
- }
- } else {
- dss->link.base = dp_ioremap(pdev, 2, &dss->link.len);
- if (IS_ERR(dss->link.base)) {
- DRM_ERROR("unable to remap link region: %pe\n", dss->link.base);
- return PTR_ERR(dss->link.base);
- }
-
- dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len);
- if (IS_ERR(dss->p0.base)) {
- DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base);
- return PTR_ERR(dss->p0.base);
- }
- }
-
- io->phy = devm_phy_get(&pdev->dev, "dp");
- if (IS_ERR(io->phy))
- return PTR_ERR(io->phy);
-
- return 0;
-}
-
-static u32 dp_parser_link_frequencies(struct device_node *of_node)
-{
- struct device_node *endpoint;
- u64 frequency = 0;
- int cnt;
-
- endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
- if (!endpoint)
- return 0;
-
- cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
-
- if (cnt > 0)
- of_property_read_u64_index(endpoint, "link-frequencies",
- cnt - 1, &frequency);
- of_node_put(endpoint);
-
- do_div(frequency,
- 10 * /* from symbol rate to link rate */
- 1000); /* kbytes */
-
- return frequency;
-}
-
-static int dp_parser_misc(struct dp_parser *parser)
-{
- struct device_node *of_node = parser->pdev->dev.of_node;
- int cnt;
-
- /*
- * data-lanes is the property of dp_out endpoint
- */
- cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
- if (cnt < 0) {
- /* legacy code, data-lanes is the property of mdss_dp node */
- cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
- }
-
- if (cnt > 0)
- parser->max_dp_lanes = cnt;
- else
- parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
-
- parser->max_dp_link_rate = dp_parser_link_frequencies(of_node);
- if (!parser->max_dp_link_rate)
- parser->max_dp_link_rate = DP_LINK_RATE_HBR2;
-
- return 0;
-}
-
-static inline bool dp_parser_check_prefix(const char *clk_prefix,
- const char *clk_name)
-{
- return !strncmp(clk_prefix, clk_name, strlen(clk_prefix));
-}
-
-static int dp_parser_init_clk_data(struct dp_parser *parser)
-{
- int num_clk, i, rc;
- int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0;
- const char *clk_name;
- struct device *dev = &parser->pdev->dev;
- struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
- struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM];
- struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM];
-
- num_clk = of_property_count_strings(dev->of_node, "clock-names");
- if (num_clk <= 0) {
- DRM_ERROR("no clocks are defined\n");
- return -EINVAL;
- }
-
- for (i = 0; i < num_clk; i++) {
- rc = of_property_read_string_index(dev->of_node,
- "clock-names", i, &clk_name);
- if (rc < 0)
- return rc;
-
- if (dp_parser_check_prefix("core", clk_name))
- core_clk_count++;
-
- if (dp_parser_check_prefix("ctrl", clk_name))
- ctrl_clk_count++;
-
- if (dp_parser_check_prefix("stream", clk_name))
- stream_clk_count++;
- }
-
- /* Initialize the CORE power module */
- if (core_clk_count == 0) {
- DRM_ERROR("no core clocks are defined\n");
- return -EINVAL;
- }
-
- core_power->num_clk = core_clk_count;
- core_power->clocks = devm_kcalloc(dev,
- core_power->num_clk, sizeof(struct clk_bulk_data),
- GFP_KERNEL);
- if (!core_power->clocks)
- return -ENOMEM;
-
- /* Initialize the CTRL power module */
- if (ctrl_clk_count == 0) {
- DRM_ERROR("no ctrl clocks are defined\n");
- return -EINVAL;
- }
-
- ctrl_power->num_clk = ctrl_clk_count;
- ctrl_power->clocks = devm_kcalloc(dev,
- ctrl_power->num_clk, sizeof(struct clk_bulk_data),
- GFP_KERNEL);
- if (!ctrl_power->clocks) {
- ctrl_power->num_clk = 0;
- return -ENOMEM;
- }
-
- /* Initialize the STREAM power module */
- if (stream_clk_count == 0) {
- DRM_ERROR("no stream (pixel) clocks are defined\n");
- return -EINVAL;
- }
-
- stream_power->num_clk = stream_clk_count;
- stream_power->clocks = devm_kcalloc(dev,
- stream_power->num_clk, sizeof(struct clk_bulk_data),
- GFP_KERNEL);
- if (!stream_power->clocks) {
- stream_power->num_clk = 0;
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static int dp_parser_clock(struct dp_parser *parser)
-{
- int rc = 0, i = 0;
- int num_clk = 0;
- int core_clk_index = 0, ctrl_clk_index = 0, stream_clk_index = 0;
- int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0;
- const char *clk_name;
- struct device *dev = &parser->pdev->dev;
- struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
- struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM];
- struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM];
-
- rc = dp_parser_init_clk_data(parser);
- if (rc) {
- DRM_ERROR("failed to initialize power data %d\n", rc);
- return -EINVAL;
- }
-
- core_clk_count = core_power->num_clk;
- ctrl_clk_count = ctrl_power->num_clk;
- stream_clk_count = stream_power->num_clk;
-
- num_clk = core_clk_count + ctrl_clk_count + stream_clk_count;
-
- for (i = 0; i < num_clk; i++) {
- rc = of_property_read_string_index(dev->of_node, "clock-names",
- i, &clk_name);
- if (rc) {
- DRM_ERROR("error reading clock-names %d\n", rc);
- return rc;
- }
- if (dp_parser_check_prefix("core", clk_name) &&
- core_clk_index < core_clk_count) {
- core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
- core_clk_index++;
- } else if (dp_parser_check_prefix("stream", clk_name) &&
- stream_clk_index < stream_clk_count) {
- stream_power->clocks[stream_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
- stream_clk_index++;
- } else if (dp_parser_check_prefix("ctrl", clk_name) &&
- ctrl_clk_index < ctrl_clk_count) {
- ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
- ctrl_clk_index++;
- }
- }
-
- return 0;
-}
-
-int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser)
-{
- struct platform_device *pdev = parser->pdev;
- struct drm_bridge *bridge;
-
- bridge = devm_drm_of_get_bridge(dev, pdev->dev.of_node, 1, 0);
- if (IS_ERR(bridge))
- return PTR_ERR(bridge);
-
- parser->next_bridge = bridge;
-
- return 0;
-}
-
-static int dp_parser_parse(struct dp_parser *parser)
-{
- int rc = 0;
-
- if (!parser) {
- DRM_ERROR("invalid input\n");
- return -EINVAL;
- }
-
- rc = dp_parser_ctrl_res(parser);
- if (rc)
- return rc;
-
- rc = dp_parser_misc(parser);
- if (rc)
- return rc;
-
- rc = dp_parser_clock(parser);
- if (rc)
- return rc;
-
- return 0;
-}
-
-struct dp_parser *dp_parser_get(struct platform_device *pdev)
-{
- struct dp_parser *parser;
-
- parser = devm_kzalloc(&pdev->dev, sizeof(*parser), GFP_KERNEL);
- if (!parser)
- return ERR_PTR(-ENOMEM);
-
- parser->parse = dp_parser_parse;
- parser->pdev = pdev;
-
- return parser;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DP_PARSER_H_
-#define _DP_PARSER_H_
-
-#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-dp.h>
-
-#include "msm_drv.h"
-
-#define DP_LABEL "MDSS DP DISPLAY"
-#define DP_MAX_PIXEL_CLK_KHZ 675000
-#define DP_MAX_NUM_DP_LANES 4
-#define DP_LINK_RATE_HBR2 540000 /* kbytes */
-
-enum dp_pm_type {
- DP_CORE_PM,
- DP_CTRL_PM,
- DP_STREAM_PM,
- DP_PHY_PM,
- DP_MAX_PM
-};
-
-struct dss_io_region {
- size_t len;
- void __iomem *base;
-};
-
-struct dss_io_data {
- struct dss_io_region ahb;
- struct dss_io_region aux;
- struct dss_io_region link;
- struct dss_io_region p0;
-};
-
-static inline const char *dp_parser_pm_name(enum dp_pm_type module)
-{
- switch (module) {
- case DP_CORE_PM: return "DP_CORE_PM";
- case DP_CTRL_PM: return "DP_CTRL_PM";
- case DP_STREAM_PM: return "DP_STREAM_PM";
- case DP_PHY_PM: return "DP_PHY_PM";
- default: return "???";
- }
-}
-
-/**
- * struct dp_display_data - display related device tree data.
- *
- * @ctrl_node: referece to controller device
- * @phy_node: reference to phy device
- * @is_active: is the controller currently active
- * @name: name of the display
- * @display_type: type of the display
- */
-struct dp_display_data {
- struct device_node *ctrl_node;
- struct device_node *phy_node;
- bool is_active;
- const char *name;
- const char *display_type;
-};
-
-/**
- * struct dp_ctrl_resource - controller's IO related data
- *
- * @dp_controller: Display Port controller mapped memory address
- * @phy_io: phy's mapped memory address
- */
-struct dp_io {
- struct dss_io_data dp_controller;
- struct phy *phy;
- union phy_configure_opts phy_opts;
-};
-
-/**
- * struct dp_pinctrl - DP's pin control
- *
- * @pin: pin-controller's instance
- * @state_active: active state pin control
- * @state_hpd_active: hpd active state pin control
- * @state_suspend: suspend state pin control
- */
-struct dp_pinctrl {
- struct pinctrl *pin;
- struct pinctrl_state *state_active;
- struct pinctrl_state *state_hpd_active;
- struct pinctrl_state *state_suspend;
-};
-
-/* Regulators for DP devices */
-struct dp_reg_entry {
- char name[32];
- int enable_load;
- int disable_load;
-};
-
-struct dss_module_power {
- unsigned int num_clk;
- struct clk_bulk_data *clocks;
-};
-
-/**
- * struct dp_parser - DP parser's data exposed to clients
- *
- * @pdev: platform data of the client
- * @mp: gpio, regulator and clock related data
- * @pinctrl: pin-control related data
- * @disp_data: controller's display related data
- * @parse: function to be called by client to parse device tree.
- */
-struct dp_parser {
- struct platform_device *pdev;
- struct dss_module_power mp[DP_MAX_PM];
- struct dp_pinctrl pinctrl;
- struct dp_io io;
- struct dp_display_data disp_data;
- u32 max_dp_lanes;
- u32 max_dp_link_rate;
- struct drm_bridge *next_bridge;
-
- int (*parse)(struct dp_parser *parser);
-};
-
-/**
- * dp_parser_get() - get the DP's device tree parser module
- *
- * @pdev: platform data of the client
- * return: pointer to dp_parser structure.
- *
- * This function provides client capability to parse the
- * device tree and populate the data structures. The data
- * related to clock, regulators, pin-control and other
- * can be parsed using this module.
- */
-struct dp_parser *dp_parser_get(struct platform_device *pdev);
-
-/**
- * devm_dp_parser_find_next_bridge() - find an additional bridge to DP
- *
- * @dev: device to tie bridge lifetime to
- * @parser: dp_parser data from client
- *
- * This function is used to find any additional bridge attached to
- * the DP controller. The eDP interface requires a panel bridge.
- *
- * Return: 0 if able to get the bridge, otherwise negative errno for failure.
- */
-int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
- */
-
-#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/regulator/consumer.h>
-#include <linux/pm_opp.h>
-#include "dp_power.h"
-#include "msm_drv.h"
-
-struct dp_power_private {
- struct dp_parser *parser;
- struct device *dev;
- struct drm_device *drm_dev;
- struct clk *link_clk_src;
- struct clk *pixel_provider;
- struct clk *link_provider;
-
- struct dp_power dp_power;
-};
-
-static int dp_power_clk_init(struct dp_power_private *power)
-{
- int rc = 0;
- struct dss_module_power *core, *ctrl, *stream;
- struct device *dev = power->dev;
-
- core = &power->parser->mp[DP_CORE_PM];
- ctrl = &power->parser->mp[DP_CTRL_PM];
- stream = &power->parser->mp[DP_STREAM_PM];
-
- rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks);
- if (rc)
- return rc;
-
- rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks);
- if (rc)
- return -ENODEV;
-
- rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks);
- if (rc)
- return -ENODEV;
-
- return 0;
-}
-
-int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type)
-{
- struct dp_power_private *power;
-
- power = container_of(dp_power, struct dp_power_private, dp_power);
-
- drm_dbg_dp(power->drm_dev,
- "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n",
- dp_power->core_clks_on, dp_power->link_clks_on, dp_power->stream_clks_on);
-
- if (pm_type == DP_CORE_PM)
- return dp_power->core_clks_on;
-
- if (pm_type == DP_CTRL_PM)
- return dp_power->link_clks_on;
-
- if (pm_type == DP_STREAM_PM)
- return dp_power->stream_clks_on;
-
- return 0;
-}
-
-int dp_power_clk_enable(struct dp_power *dp_power,
- enum dp_pm_type pm_type, bool enable)
-{
- int rc = 0;
- struct dp_power_private *power;
- struct dss_module_power *mp;
-
- power = container_of(dp_power, struct dp_power_private, dp_power);
-
- if (pm_type != DP_CORE_PM && pm_type != DP_CTRL_PM &&
- pm_type != DP_STREAM_PM) {
- DRM_ERROR("unsupported power module: %s\n",
- dp_parser_pm_name(pm_type));
- return -EINVAL;
- }
-
- if (enable) {
- if (pm_type == DP_CORE_PM && dp_power->core_clks_on) {
- drm_dbg_dp(power->drm_dev,
- "core clks already enabled\n");
- return 0;
- }
-
- if (pm_type == DP_CTRL_PM && dp_power->link_clks_on) {
- drm_dbg_dp(power->drm_dev,
- "links clks already enabled\n");
- return 0;
- }
-
- if (pm_type == DP_STREAM_PM && dp_power->stream_clks_on) {
- drm_dbg_dp(power->drm_dev,
- "pixel clks already enabled\n");
- return 0;
- }
-
- if ((pm_type == DP_CTRL_PM) && (!dp_power->core_clks_on)) {
- drm_dbg_dp(power->drm_dev,
- "Enable core clks before link clks\n");
- mp = &power->parser->mp[DP_CORE_PM];
-
- rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
- if (rc)
- return rc;
-
- dp_power->core_clks_on = true;
- }
- }
-
- mp = &power->parser->mp[pm_type];
- if (enable) {
- rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
- if (rc)
- return rc;
- } else {
- clk_bulk_disable_unprepare(mp->num_clk, mp->clocks);
- }
-
- if (pm_type == DP_CORE_PM)
- dp_power->core_clks_on = enable;
- else if (pm_type == DP_STREAM_PM)
- dp_power->stream_clks_on = enable;
- else
- dp_power->link_clks_on = enable;
-
- drm_dbg_dp(power->drm_dev, "%s clocks for %s\n",
- enable ? "enable" : "disable",
- dp_parser_pm_name(pm_type));
- drm_dbg_dp(power->drm_dev,
- "strem_clks:%s link_clks:%s core_clks:%s\n",
- dp_power->stream_clks_on ? "on" : "off",
- dp_power->link_clks_on ? "on" : "off",
- dp_power->core_clks_on ? "on" : "off");
-
- return 0;
-}
-
-int dp_power_client_init(struct dp_power *dp_power)
-{
- struct dp_power_private *power;
-
- power = container_of(dp_power, struct dp_power_private, dp_power);
-
- return dp_power_clk_init(power);
-}
-
-int dp_power_init(struct dp_power *dp_power)
-{
- return dp_power_clk_enable(dp_power, DP_CORE_PM, true);
-}
-
-int dp_power_deinit(struct dp_power *dp_power)
-{
- return dp_power_clk_enable(dp_power, DP_CORE_PM, false);
-}
-
-struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser)
-{
- struct dp_power_private *power;
- struct dp_power *dp_power;
-
- power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
- if (!power)
- return ERR_PTR(-ENOMEM);
-
- power->parser = parser;
- power->dev = dev;
-
- dp_power = &power->dp_power;
-
- return dp_power;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DP_POWER_H_
-#define _DP_POWER_H_
-
-#include "dp_parser.h"
-
-/**
- * sruct dp_power - DisplayPort's power related data
- *
- * @init: initializes the regulators/core clocks/GPIOs/pinctrl
- * @deinit: turns off the regulators/core clocks/GPIOs/pinctrl
- * @clk_enable: enable/disable the DP clocks
- * @set_pixel_clk_parent: set the parent of DP pixel clock
- */
-struct dp_power {
- bool core_clks_on;
- bool link_clks_on;
- bool stream_clks_on;
-};
-
-/**
- * dp_power_init() - enable power supplies for display controller
- *
- * @power: instance of power module
- * return: 0 if success or error if failure.
- *
- * This API will turn on the regulators and configures gpio's
- * aux/hpd.
- */
-int dp_power_init(struct dp_power *power);
-
-/**
- * dp_power_deinit() - turn off regulators and gpios.
- *
- * @power: instance of power module
- * return: 0 for success
- *
- * This API turns off power and regulators.
- */
-int dp_power_deinit(struct dp_power *power);
-
-/**
- * dp_power_clk_status() - display controller clocks status
- *
- * @power: instance of power module
- * @pm_type: type of pm, core/ctrl/phy
- * return: status of power clocks
- *
- * This API return status of DP clocks
- */
-
-int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type);
-
-/**
- * dp_power_clk_enable() - enable display controller clocks
- *
- * @power: instance of power module
- * @pm_type: type of pm, core/ctrl/phy
- * @enable: enables or disables
- * return: pointer to allocated power module data
- *
- * This API will call setrate and enable for DP clocks
- */
-
-int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type,
- bool enable);
-
-/**
- * dp_power_client_init() - initialize clock and regulator modules
- *
- * @power: instance of power module
- * return: 0 for success, error for failure.
- *
- * This API will configure the DisplayPort's clocks and regulator
- * modules.
- */
-int dp_power_client_init(struct dp_power *power);
-
-/**
- * dp_power_get() - configure and get the DisplayPort power module data
- *
- * @parser: instance of parser module
- * return: pointer to allocated power module data
- *
- * This API will configure the DisplayPort's power module and provides
- * methods to be called by the client to configure the power related
- * modules.
- */
-struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser);
-
-#endif /* _DP_POWER_H_ */
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
struct drm_encoder *encoder)
{
+ struct drm_bridge *bridge;
int ret;
msm_dsi->dev = dev;
return 0;
}
- msm_dsi->encoder = encoder;
-
- ret = msm_dsi_manager_bridge_init(msm_dsi);
- if (ret) {
+ bridge = msm_dsi_manager_bridge_init(msm_dsi, encoder);
+ if (IS_ERR(bridge)) {
+ ret = PTR_ERR(bridge);
DRM_DEV_ERROR(dev->dev, "failed to create dsi bridge: %d\n", ret);
return ret;
}
- ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id);
+ ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id, bridge);
if (ret) {
DRM_DEV_ERROR(dev->dev,
"failed to create dsi connector: %d\n", ret);
struct drm_device *dev;
struct platform_device *pdev;
- /* internal dsi bridge attached to MDP interface */
- struct drm_bridge *bridge;
-
struct mipi_dsi_host *host;
struct msm_dsi_phy *phy;
- /*
- * external_bridge connected to dsi bridge output
- */
- struct drm_bridge *external_bridge;
-
struct device *phy_dev;
bool phy_enabled;
- /* the encoder we are hooked to (outside of dsi block) */
- struct drm_encoder *encoder;
-
int id;
};
/* dsi manager */
-int msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi);
-int msm_dsi_manager_ext_bridge_init(u8 id);
+struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
+ struct drm_encoder *encoder);
+int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge);
int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
void msm_dsi_manager_tpg_enable(void);
-/* msm dsi */
-static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
-{
- return msm_dsi->external_bridge;
-}
-
/* dsi host */
struct msm_dsi_host;
int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
int irq;
};
-static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
-{
- switch (fmt) {
- case MIPI_DSI_FMT_RGB565: return 16;
- case MIPI_DSI_FMT_RGB666_PACKED: return 18;
- case MIPI_DSI_FMT_RGB666:
- case MIPI_DSI_FMT_RGB888:
- default: return 24;
- }
-}
static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
{
clk_disable_unprepare(msm_host->byte_clk);
}
+/**
+ * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case
+ * @mode: The selected mode for the DSI output
+ * @dsc: DRM DSC configuration for this DSI output
+ *
+ * Adjust the pclk rate by calculating a new hdisplay proportional to
+ * the compression ratio such that:
+ * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp
+ *
+ * Porches do not need to be adjusted:
+ * - For VIDEO mode they are not compressed by DSC and are passed as is.
+ * - For CMD mode there are no actual porches. Instead these fields
+ * currently represent the overhead to the image data transfer. As such, they
+ * are calculated for the final mode parameters (after the compression) and
+ * are not to be adjusted too.
+ *
+ * FIXME: Reconsider this if/when CMD mode handling is rewritten to use
+ * transfer time and data overhead as a starting point of the calculations.
+ */
static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
const struct drm_dsc_config *dsc)
{
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
u8 lanes = msm_host->lanes;
- u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format);
unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);
unsigned long pclk_bpp;
int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
- u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format);
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
if (ret)
return;
- /* Divide the display by 3 but keep back/font porch and
- * pulse width same
+ /*
+ * DPU sends 3 bytes per pclk cycle to DSI. If widebus is
+ * enabled, bus width is extended to 6 bytes.
+ *
+ * Calculate the number of pclks needed to transmit one line of
+ * the compressed data.
+
+ * The back/font porch and pulse width are kept intact. For
+ * VIDEO mode they represent timing parameters rather than
+ * actual data transfer, see the documentation for
+ * dsi_adjust_pclk_for_compression(). For CMD mode they are
+ * unused anyway.
*/
h_total -= hdisplay;
if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
/* image data and 1 byte write_memory_start cmd */
if (!msm_host->dsc)
- wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1;
else
/*
* When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1.
{
int len, ret;
int bllp_len = msm_host->mode->hdisplay *
- dsi_get_bpp(msm_host->format) / 8;
+ mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8;
len = dsi_cmd_dma_add(msm_host, msg);
if (len < 0) {
return dsi_bridge->id;
}
-static void msm_dsi_manager_set_split_display(u8 id)
-{
- struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
- struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
- struct msm_drm_private *priv = msm_dsi->dev->dev_private;
- struct msm_kms *kms = priv->kms;
- struct msm_dsi *master_dsi, *slave_dsi;
-
- if (IS_BONDED_DSI() && !IS_MASTER_DSI_LINK(id)) {
- master_dsi = other_dsi;
- slave_dsi = msm_dsi;
- } else {
- master_dsi = msm_dsi;
- slave_dsi = other_dsi;
- }
-
- if (!msm_dsi->external_bridge || !IS_BONDED_DSI())
- return;
-
- /*
- * Set split display info to kms once bonded DSI panel is connected to
- * both hosts.
- */
- if (other_dsi && other_dsi->external_bridge && kms->funcs->set_split_display) {
- kms->funcs->set_split_display(kms, master_dsi->encoder,
- slave_dsi->encoder,
- msm_dsi_is_cmd_mode(msm_dsi));
- }
-}
-
static int dsi_mgr_bridge_power_on(struct drm_bridge *bridge)
{
int id = dsi_mgr_bridge_get_id(bridge);
int ret;
DBG("id=%d", id);
- if (!msm_dsi_device_connected(msm_dsi))
- return;
/* Do nothing with the host if it is slave-DSI in case of bonded DSI */
if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id))
DBG("id=%d", id);
- if (!msm_dsi_device_connected(msm_dsi))
- return;
-
/*
* Do nothing with the host if it is slave-DSI in case of bonded DSI.
* It is safe to call dsi_mgr_phy_disable() here because a single PHY
};
/* initialize bridge */
-int msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi)
+struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
+ struct drm_encoder *encoder)
{
- struct drm_bridge *bridge = NULL;
+ struct drm_bridge *bridge;
struct dsi_bridge *dsi_bridge;
- struct drm_encoder *encoder;
int ret;
dsi_bridge = devm_kzalloc(msm_dsi->dev->dev,
sizeof(*dsi_bridge), GFP_KERNEL);
if (!dsi_bridge)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
dsi_bridge->id = msm_dsi->id;
- encoder = msm_dsi->encoder;
-
bridge = &dsi_bridge->base;
bridge->funcs = &dsi_mgr_bridge_funcs;
ret = devm_drm_bridge_add(msm_dsi->dev->dev, bridge);
if (ret)
- return ret;
+ return ERR_PTR(ret);
ret = drm_bridge_attach(encoder, bridge, NULL, 0);
if (ret)
- return ret;
-
- msm_dsi->bridge = bridge;
+ return ERR_PTR(ret);
- return 0;
+ return bridge;
}
-int msm_dsi_manager_ext_bridge_init(u8 id)
+int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge)
{
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct drm_device *dev = msm_dsi->dev;
struct drm_encoder *encoder;
- struct drm_bridge *int_bridge, *ext_bridge;
+ struct drm_bridge *ext_bridge;
int ret;
- int_bridge = msm_dsi->bridge;
ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev,
msm_dsi->pdev->dev.of_node, 1, 0);
if (IS_ERR(ext_bridge))
return PTR_ERR(ext_bridge);
- msm_dsi->external_bridge = ext_bridge;
-
- encoder = msm_dsi->encoder;
+ encoder = int_bridge->encoder;
/*
* Try first to create the bridge without it creating its own
return ret;
}
- /* The pipeline is ready, ping encoders if necessary */
- msm_dsi_manager_set_split_display(id);
-
return 0;
}
return 0;
}
+#if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
+bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
+{
+ /* If just a single driver is enabled, use it no matter what */
+ return true;
+}
+#else
+
+static bool prefer_mdp5 = true;
+MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
+module_param(prefer_mdp5, bool, 0444);
+
+/* list all platforms supported by both mdp5 and dpu drivers */
+static const char *const msm_mdp5_dpu_migration[] = {
+ "qcom,sdm630-mdp5",
+ "qcom,sdm660-mdp5",
+ NULL,
+};
+
+bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
+{
+ /* If it is not an MDP5 device, do not try MDP5 driver */
+ if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
+ return dpu_driver;
+
+ /* If it is not in the migration list, use MDP5 */
+ if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
+ return !dpu_driver;
+
+ return prefer_mdp5 ? !dpu_driver : dpu_driver;
+}
+#endif
+
/*
* We don't know what's the best binding to link the gpu with the drm device.
* Fow now, we just hunt for all the possible gpus that we support, and add them
void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
phys_addr_t *size);
void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
+void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
+ struct platform_device *dev,
+ const char *name);
struct icc_path *msm_icc_get(struct device *dev, const char *name);
struct msm_kms *kms);
void msm_kms_shutdown(struct platform_device *pdev);
+bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver);
#endif /* __MSM_DRV_H__ */
return clk;
}
+void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
+ struct platform_device *pdev,
+ const char *name)
+{
+ struct resource *res;
+
+ res = platform_get_resource_byname(mdss_pdev, IORESOURCE_MEM, name);
+ if (!res)
+ return ERR_PTR(-EINVAL);
+
+ return devm_ioremap_resource(&pdev->dev, res);
+}
+
static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
bool quiet, phys_addr_t *psize)
{
/* misc: */
long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
struct drm_encoder *encoder);
- int (*set_split_display)(struct msm_kms *kms,
- struct drm_encoder *encoder,
- struct drm_encoder *slave_encoder,
- bool is_cmd_mode);
/* cleanup: */
void (*destroy)(struct msm_kms *kms);
* Copyright (c) 2018, The Linux Foundation
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interconnect.h>
}
}
+#define MDSS_HW_MAJ_MIN GENMASK(31, 16)
+
+#define MDSS_HW_MSM8996 0x1007
+#define MDSS_HW_MSM8937 0x100e
+#define MDSS_HW_MSM8953 0x1010
+#define MDSS_HW_MSM8998 0x3000
+#define MDSS_HW_SDM660 0x3002
+#define MDSS_HW_SDM630 0x3003
+
+/*
+ * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data
+ */
+static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
+{
+ struct msm_mdss_data *data;
+ u32 hw_rev;
+
+ data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return NULL;
+
+ hw_rev = readl_relaxed(mdss->mmio + HW_REV);
+ hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
+
+ if (hw_rev == MDSS_HW_MSM8996 ||
+ hw_rev == MDSS_HW_MSM8937 ||
+ hw_rev == MDSS_HW_MSM8953 ||
+ hw_rev == MDSS_HW_MSM8998 ||
+ hw_rev == MDSS_HW_SDM660 ||
+ hw_rev == MDSS_HW_SDM630) {
+ data->ubwc_dec_version = UBWC_1_0;
+ data->ubwc_enc_version = UBWC_1_0;
+ }
+
+ if (hw_rev == MDSS_HW_MSM8996 ||
+ hw_rev == MDSS_HW_MSM8998)
+ data->highest_bank_bit = 2;
+ else
+ data->highest_bank_bit = 1;
+
+ return data;
+}
+
const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
{
struct msm_mdss *mdss;
mdss = dev_get_drvdata(dev);
+ /*
+ * We could not do it at the probe time, since hw revision register was
+ * not readable. Fill data structure now for the MDP5 platforms.
+ */
+ if (!mdss->mdss_data && mdss->is_mdp5)
+ mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
+
return mdss->mdss_data;
}
.macrotile_mode = 1,
.reg_bus_bw = 57000,
};
+
+static const struct msm_mdss_data x1e80100_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_3,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 1,
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ .highest_bank_bit = 3,
+ .macrotile_mode = 1,
+ /* TODO: Add reg_bus_bw with real value */
+};
+
static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
{ .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
+ { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
return ret;
/* Modeset init */
- drm_mode_config_init(drm);
+ ret = drmm_mode_config_init(drm);
+ if (ret) {
+ dev_err(drm->dev, "Failed to initialize mode config\n");
+ return ret;
+ }
ret = lcdif_kms_init(lcdif);
if (ret < 0) {
drm_crtc_vblank_off(&lcdif->crtc);
drm_kms_helper_poll_fini(drm);
- drm_mode_config_cleanup(drm);
pm_runtime_put_sync(drm->dev);
pm_runtime_disable(drm->dev);
pm_runtime_enable(drm->dev);
/* Modeset init */
- drm_mode_config_init(drm);
+ ret = drmm_mode_config_init(drm);
+ if (ret) {
+ dev_err(drm->dev, "Failed to initialize mode config\n");
+ goto err_vblank;
+ }
ret = mxsfb_kms_init(mxsfb);
if (ret < 0) {
static void mxsfb_unload(struct drm_device *drm)
{
drm_kms_helper_poll_fini(drm);
- drm_mode_config_cleanup(drm);
pm_runtime_get_sync(drm->dev);
mxsfb_irq_uninstall(drm);
#include "wndw.h"
#include "handles.h"
+#include <linux/backlight.h>
#include <linux/dma-mapping.h>
#include <linux/hdmi.h>
#include <linux/component.h>
{
struct panel_edp *p = dev_get_drvdata(dev);
+ drm_dp_dpcd_set_powered(p->aux, false);
gpiod_set_value_cansleep(p->enable_gpio, 0);
regulator_disable(p->supply);
p->unprepared_time = ktime_get_boottime();
}
gpiod_set_value_cansleep(p->enable_gpio, 1);
+ drm_dp_dpcd_set_powered(p->aux, true);
p->powered_on_time = ktime_get_boottime();
return 0;
error:
+ drm_dp_dpcd_set_powered(p->aux, false);
gpiod_set_value_cansleep(p->enable_gpio, 0);
regulator_disable(p->supply);
p->unprepared_time = ktime_get_boottime();
if (p->el3_was_on)
atana33xc20_wait(p->el_on3_off_time, 150);
+ drm_dp_dpcd_set_powered(p->aux, false);
ret = regulator_disable(p->supply);
if (ret)
return ret;
ret = regulator_enable(p->supply);
if (ret)
return ret;
+ drm_dp_dpcd_set_powered(p->aux, true);
p->powered_on_time = ktime_get_boottime();
if (p->no_hpd) {
static int __init drm_sched_fence_slab_init(void)
{
- sched_fence_slab = kmem_cache_create(
- "drm_sched_fence", sizeof(struct drm_sched_fence), 0,
- SLAB_HWCACHE_ALIGN, NULL);
+ sched_fence_slab = KMEM_CACHE(drm_sched_fence, SLAB_HWCACHE_ALIGN);
if (!sched_fence_slab)
return -ENOMEM;
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include "sun4i_drv.h"
#include "sun4i_hdmi.h"
-static inline struct sun4i_hdmi *
-drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
-{
- return container_of(encoder, struct sun4i_hdmi,
- encoder);
-}
+#define drm_encoder_to_sun4i_hdmi(e) \
+ container_of_const(e, struct sun4i_hdmi, encoder)
-static inline struct sun4i_hdmi *
-drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
-{
- return container_of(connector, struct sun4i_hdmi,
- connector);
-}
+#define drm_connector_to_sun4i_hdmi(c) \
+ container_of_const(c, struct sun4i_hdmi, connector)
static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
struct drm_display_mode *mode)
return 0;
}
-static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct drm_display_mode *mode = &crtc_state->mode;
-
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return -EINVAL;
-
- return 0;
-}
-
-static void sun4i_hdmi_disable(struct drm_encoder *encoder)
+static void sun4i_hdmi_disable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
{
struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
u32 val;
clk_disable_unprepare(hdmi->tmds_clk);
}
-static void sun4i_hdmi_enable(struct drm_encoder *encoder)
+static void sun4i_hdmi_enable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
{
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
struct drm_display_info *display = &hdmi->connector.display_info;
+ unsigned int x, y;
u32 val = 0;
DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
- clk_prepare_enable(hdmi->tmds_clk);
-
- sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
- val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
- val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
- writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
-
- val = SUN4I_HDMI_VID_CTRL_ENABLE;
- if (display->is_hdmi)
- val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
-
- writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
-}
-
-static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
- unsigned int x, y;
- u32 val;
-
clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
+
+ clk_prepare_enable(hdmi->tmds_clk);
+
+ sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
+ val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
+ val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
+ writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
+
+ val = SUN4I_HDMI_VID_CTRL_ENABLE;
+ if (display->is_hdmi)
+ val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
+
+ writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
}
-static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
- const struct drm_display_mode *mode)
+static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
+ .atomic_disable = sun4i_hdmi_disable,
+ .atomic_enable = sun4i_hdmi_enable,
+};
+
+static enum drm_mode_status
+sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector,
+ const struct drm_display_mode *mode,
+ unsigned long long clock)
{
- struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
- unsigned long rate = mode->clock * 1000;
- unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
+ const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
+ unsigned long diff = clock / 200; /* +-0.5% allowed by HDMI spec */
long rounded_rate;
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_BAD;
+
/* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
- if (rate > 165000000)
+ if (clock > 165000000)
return MODE_CLOCK_HIGH;
- rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
+
+ rounded_rate = clk_round_rate(hdmi->tmds_clk, clock);
if (rounded_rate > 0 &&
- max_t(unsigned long, rounded_rate, rate) -
- min_t(unsigned long, rounded_rate, rate) < diff)
+ max_t(unsigned long, rounded_rate, clock) -
+ min_t(unsigned long, rounded_rate, clock) < diff)
return MODE_OK;
+
return MODE_NOCLOCK;
}
-static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
- .atomic_check = sun4i_hdmi_atomic_check,
- .disable = sun4i_hdmi_disable,
- .enable = sun4i_hdmi_enable,
- .mode_set = sun4i_hdmi_mode_set,
- .mode_valid = sun4i_hdmi_mode_valid,
-};
+static int sun4i_hdmi_connector_atomic_check(struct drm_connector *connector,
+ struct drm_atomic_state *state)
+{
+ struct drm_connector_state *conn_state =
+ drm_atomic_get_new_connector_state(state, connector);
+ struct drm_crtc *crtc = conn_state->crtc;
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ enum drm_mode_status status;
+
+ status = sun4i_hdmi_connector_clock_valid(connector, mode,
+ mode->clock * 1000);
+ if (status != MODE_OK)
+ return -EINVAL;
+
+ return 0;
+}
+
+static enum drm_mode_status
+sun4i_hdmi_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ return sun4i_hdmi_connector_clock_valid(connector, mode,
+ mode->clock * 1000);
+}
static int sun4i_hdmi_get_modes(struct drm_connector *connector)
{
}
static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
+ .atomic_check = sun4i_hdmi_connector_atomic_check,
+ .mode_valid = sun4i_hdmi_connector_mode_valid,
.get_modes = sun4i_hdmi_get_modes,
};
if (gem->size < size) {
err = -EINVAL;
+ drm_gem_object_put(gem);
goto unreference;
}
* Kunit test for drm_modes functions
*/
+#include <linux/i2c.h>
+
+#include <drm/drm_atomic_state_helper.h>
#include <drm/drm_connector.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_kunit_helpers.h>
#include <kunit/test.h>
+struct drm_connector_init_priv {
+ struct drm_device drm;
+ struct drm_connector connector;
+ struct i2c_adapter ddc;
+};
+
+static const struct drm_connector_funcs dummy_funcs = {
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .reset = drm_atomic_helper_connector_reset,
+};
+
+static int dummy_ddc_xfer(struct i2c_adapter *adapter,
+ struct i2c_msg *msgs, int num)
+{
+ return num;
+}
+
+static u32 dummy_ddc_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm dummy_ddc_algorithm = {
+ .master_xfer = dummy_ddc_xfer,
+ .functionality = dummy_ddc_func,
+};
+
+static void i2c_del_adapter_wrapper(void *ptr)
+{
+ struct i2c_adapter *adap = ptr;
+
+ i2c_del_adapter(adap);
+}
+
+static int drm_test_connector_init(struct kunit *test)
+{
+ struct drm_connector_init_priv *priv;
+ struct device *dev;
+ int ret;
+
+ dev = drm_kunit_helper_alloc_device(test);
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+ priv = drm_kunit_helper_alloc_drm_device(test, dev,
+ struct drm_connector_init_priv, drm,
+ DRIVER_MODESET | DRIVER_ATOMIC);
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv);
+
+ strscpy(priv->ddc.name, "dummy-connector-ddc", sizeof(priv->ddc.name));
+ priv->ddc.owner = THIS_MODULE;
+ priv->ddc.algo = &dummy_ddc_algorithm;
+ priv->ddc.dev.parent = dev;
+
+ ret = i2c_add_adapter(&priv->ddc);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ ret = kunit_add_action_or_reset(test, i2c_del_adapter_wrapper, &priv->ddc);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ test->priv = priv;
+ return 0;
+}
+
+/*
+ * Test that the registration of a bog standard connector works as
+ * expected and doesn't report any error.
+ */
+static void drm_test_drmm_connector_init(struct kunit *test)
+{
+ struct drm_connector_init_priv *priv = test->priv;
+ int ret;
+
+ ret = drmm_connector_init(&priv->drm, &priv->connector,
+ &dummy_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ &priv->ddc);
+ KUNIT_EXPECT_EQ(test, ret, 0);
+}
+
+/*
+ * Test that the registration of a connector without a DDC adapter
+ * doesn't report any error.
+ */
+static void drm_test_drmm_connector_init_null_ddc(struct kunit *test)
+{
+ struct drm_connector_init_priv *priv = test->priv;
+ int ret;
+
+ ret = drmm_connector_init(&priv->drm, &priv->connector,
+ &dummy_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ NULL);
+ KUNIT_EXPECT_EQ(test, ret, 0);
+}
+
+/*
+ * Test that the registration of a connector succeeds for all possible
+ * connector types.
+ */
+static void drm_test_drmm_connector_init_type_valid(struct kunit *test)
+{
+ struct drm_connector_init_priv *priv = test->priv;
+ unsigned int connector_type = *(unsigned int *)test->param_value;
+ int ret;
+
+ ret = drmm_connector_init(&priv->drm, &priv->connector,
+ &dummy_funcs,
+ connector_type,
+ &priv->ddc);
+ KUNIT_EXPECT_EQ(test, ret, 0);
+}
+
+static const unsigned int drm_connector_init_type_valid_tests[] = {
+ DRM_MODE_CONNECTOR_Unknown,
+ DRM_MODE_CONNECTOR_VGA,
+ DRM_MODE_CONNECTOR_DVII,
+ DRM_MODE_CONNECTOR_DVID,
+ DRM_MODE_CONNECTOR_DVIA,
+ DRM_MODE_CONNECTOR_Composite,
+ DRM_MODE_CONNECTOR_SVIDEO,
+ DRM_MODE_CONNECTOR_LVDS,
+ DRM_MODE_CONNECTOR_Component,
+ DRM_MODE_CONNECTOR_9PinDIN,
+ DRM_MODE_CONNECTOR_DisplayPort,
+ DRM_MODE_CONNECTOR_HDMIA,
+ DRM_MODE_CONNECTOR_HDMIB,
+ DRM_MODE_CONNECTOR_TV,
+ DRM_MODE_CONNECTOR_eDP,
+ DRM_MODE_CONNECTOR_VIRTUAL,
+ DRM_MODE_CONNECTOR_DSI,
+ DRM_MODE_CONNECTOR_DPI,
+ DRM_MODE_CONNECTOR_WRITEBACK,
+ DRM_MODE_CONNECTOR_SPI,
+ DRM_MODE_CONNECTOR_USB,
+};
+
+static void drm_connector_init_type_desc(const unsigned int *type, char *desc)
+{
+ sprintf(desc, "%s", drm_get_connector_type_name(*type));
+}
+
+KUNIT_ARRAY_PARAM(drm_connector_init_type_valid,
+ drm_connector_init_type_valid_tests,
+ drm_connector_init_type_desc);
+
+static struct kunit_case drmm_connector_init_tests[] = {
+ KUNIT_CASE(drm_test_drmm_connector_init),
+ KUNIT_CASE(drm_test_drmm_connector_init_null_ddc),
+ KUNIT_CASE_PARAM(drm_test_drmm_connector_init_type_valid,
+ drm_connector_init_type_valid_gen_params),
+ { }
+};
+
+static struct kunit_suite drmm_connector_init_test_suite = {
+ .name = "drmm_connector_init",
+ .init = drm_test_connector_init,
+ .test_cases = drmm_connector_init_tests,
+};
+
struct drm_get_tv_mode_from_name_test {
const char *name;
enum drm_connector_tv_mode expected_mode;
.test_cases = drm_get_tv_mode_from_name_tests,
};
-kunit_test_suite(drm_get_tv_mode_from_name_test_suite);
+kunit_test_suites(
+ &drmm_connector_init_test_suite,
+ &drm_get_tv_mode_from_name_test_suite
+);
MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>");
MODULE_LICENSE("GPL");
// SPDX-License-Identifier: GPL-2.0
#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
+#include <drm/drm_fourcc.h>
#include <drm/drm_kunit_helpers.h>
#include <drm/drm_managed.h>
#define KUNIT_DEVICE_NAME "drm-kunit-mock-device"
static const struct drm_mode_config_funcs drm_mode_config_funcs = {
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
};
/**
}
EXPORT_SYMBOL_GPL(drm_kunit_helper_atomic_state_alloc);
+static const uint32_t default_plane_formats[] = {
+ DRM_FORMAT_XRGB8888,
+};
+
+static const uint64_t default_plane_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const struct drm_plane_helper_funcs default_plane_helper_funcs = {
+};
+
+static const struct drm_plane_funcs default_plane_funcs = {
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .reset = drm_atomic_helper_plane_reset,
+};
+
+/**
+ * drm_kunit_helper_create_primary_plane - Creates a mock primary plane for a KUnit test
+ * @test: The test context object
+ * @drm: The device to alloc the plane for
+ * @funcs: Callbacks for the new plane. Optional.
+ * @helper_funcs: Helpers callbacks for the new plane. Optional.
+ * @formats: array of supported formats (DRM_FORMAT\_\*). Optional.
+ * @num_formats: number of elements in @formats
+ * @modifiers: array of struct drm_format modifiers terminated by
+ * DRM_FORMAT_MOD_INVALID. Optional.
+ *
+ * This allocates and initializes a mock struct &drm_plane meant to be
+ * part of a mock device for a KUnit test.
+ *
+ * Resources will be cleaned up automatically.
+ *
+ * @funcs will default to the default helpers implementations.
+ * @helper_funcs will default to an empty implementation. @formats will
+ * default to XRGB8888 only. @modifiers will default to a linear
+ * modifier only.
+ *
+ * Returns:
+ * A pointer to the new plane, or an ERR_PTR() otherwise.
+ */
+struct drm_plane *
+drm_kunit_helper_create_primary_plane(struct kunit *test,
+ struct drm_device *drm,
+ const struct drm_plane_funcs *funcs,
+ const struct drm_plane_helper_funcs *helper_funcs,
+ const uint32_t *formats,
+ unsigned int num_formats,
+ const uint64_t *modifiers)
+{
+ struct drm_plane *plane;
+
+ if (!funcs)
+ funcs = &default_plane_funcs;
+
+ if (!helper_funcs)
+ helper_funcs = &default_plane_helper_funcs;
+
+ if (!formats || !num_formats) {
+ formats = default_plane_formats;
+ num_formats = ARRAY_SIZE(default_plane_formats);
+ }
+
+ if (!modifiers)
+ modifiers = default_plane_modifiers;
+
+ plane = __drmm_universal_plane_alloc(drm,
+ sizeof(struct drm_plane), 0,
+ 0,
+ funcs,
+ formats,
+ num_formats,
+ default_plane_modifiers,
+ DRM_PLANE_TYPE_PRIMARY,
+ NULL);
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, plane);
+
+ drm_plane_helper_add(plane, helper_funcs);
+
+ return plane;
+}
+EXPORT_SYMBOL_GPL(drm_kunit_helper_create_primary_plane);
+
+static const struct drm_crtc_helper_funcs default_crtc_helper_funcs = {
+};
+
+static const struct drm_crtc_funcs default_crtc_funcs = {
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .reset = drm_atomic_helper_crtc_reset,
+};
+
+/**
+ * drm_kunit_helper_create_crtc - Creates a mock CRTC for a KUnit test
+ * @test: The test context object
+ * @drm: The device to alloc the plane for
+ * @primary: Primary plane for CRTC
+ * @cursor: Cursor plane for CRTC. Optional.
+ * @funcs: Callbacks for the new plane. Optional.
+ * @helper_funcs: Helpers callbacks for the new plane. Optional.
+ *
+ * This allocates and initializes a mock struct &drm_crtc meant to be
+ * part of a mock device for a KUnit test.
+ *
+ * Resources will be cleaned up automatically.
+ *
+ * @funcs will default to the default helpers implementations.
+ * @helper_funcs will default to an empty implementation.
+ *
+ * Returns:
+ * A pointer to the new CRTC, or an ERR_PTR() otherwise.
+ */
+struct drm_crtc *
+drm_kunit_helper_create_crtc(struct kunit *test,
+ struct drm_device *drm,
+ struct drm_plane *primary,
+ struct drm_plane *cursor,
+ const struct drm_crtc_funcs *funcs,
+ const struct drm_crtc_helper_funcs *helper_funcs)
+{
+ struct drm_crtc *crtc;
+ int ret;
+
+ if (!funcs)
+ funcs = &default_crtc_funcs;
+
+ if (!helper_funcs)
+ helper_funcs = &default_crtc_helper_funcs;
+
+ crtc = drmm_kzalloc(drm, sizeof(*crtc), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, crtc);
+
+ ret = drmm_crtc_init_with_planes(drm, crtc,
+ primary,
+ cursor,
+ funcs,
+ NULL);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ drm_crtc_helper_add(crtc, helper_funcs);
+
+ return crtc;
+}
+EXPORT_SYMBOL_GPL(drm_kunit_helper_create_crtc);
+
MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>");
MODULE_LICENSE("GPL");
reinit_completion(&tcrtc->framedone_completion);
+ /*
+ * If a layer is left enabled when the videoport is disabled, and the
+ * vid pipeline that was used for the layer is taken into use on
+ * another videoport, the DSS will report sync lost issues. Disable all
+ * the layers here as a work-around.
+ */
+ for (u32 layer = 0; layer < tidss->feat->num_planes; layer++)
+ dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
+ false);
+
dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport);
if (!wait_for_completion_timeout(&tcrtc->framedone_completion,
drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
- drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
+ drm_plane_create_zpos_property(&tplane->plane, tidss->num_planes, 0,
num_planes - 1);
ret = drm_plane_create_color_properties(&tplane->plane,
mutex_lock(&v3d->bo_lock);
v3d->bo_stats.num_allocated--;
- v3d->bo_stats.pages_allocated -= obj->size >> PAGE_SHIFT;
+ v3d->bo_stats.pages_allocated -= obj->size >> V3D_MMU_PAGE_SHIFT;
mutex_unlock(&v3d->bo_lock);
spin_lock(&v3d->mm_lock);
* lifetime of the BO.
*/
ret = drm_mm_insert_node_generic(&v3d->mm, &bo->node,
- obj->size >> PAGE_SHIFT,
- GMP_GRANULARITY >> PAGE_SHIFT, 0, 0);
+ obj->size >> V3D_MMU_PAGE_SHIFT,
+ GMP_GRANULARITY >> V3D_MMU_PAGE_SHIFT, 0, 0);
spin_unlock(&v3d->mm_lock);
if (ret)
return ret;
/* Track stats for /debug/dri/n/bo_stats. */
mutex_lock(&v3d->bo_lock);
v3d->bo_stats.num_allocated++;
- v3d->bo_stats.pages_allocated += obj->size >> PAGE_SHIFT;
+ v3d->bo_stats.pages_allocated += obj->size >> V3D_MMU_PAGE_SHIFT;
mutex_unlock(&v3d->bo_lock);
v3d_mmu_insert_ptes(bo);
if (IS_ERR(bo))
return PTR_ERR(bo);
- args->offset = bo->node.start << PAGE_SHIFT;
+ args->offset = bo->node.start << V3D_MMU_PAGE_SHIFT;
ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle);
drm_gem_object_put(&bo->base.base);
}
bo = to_v3d_bo(gem_obj);
- args->offset = bo->node.start << PAGE_SHIFT;
+ args->offset = bo->node.start << V3D_MMU_PAGE_SHIFT;
drm_gem_object_put(gem_obj);
return 0;
seq_printf(m, "allocated bos: %d\n",
v3d->bo_stats.num_allocated);
seq_printf(m, "allocated bo size (kb): %ld\n",
- (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
+ (long)v3d->bo_stats.pages_allocated << (V3D_MMU_PAGE_SHIFT - 10));
mutex_unlock(&v3d->bo_lock);
return 0;
#define GMP_GRANULARITY (128 * 1024)
+#define V3D_MMU_PAGE_SHIFT 12
+
#define V3D_MAX_QUEUES (V3D_CPU + 1)
static inline char *v3d_queue_to_string(enum v3d_queue queue)
list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
spin_unlock_irqrestore(&v3d->job_lock, irqflags);
- V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
+ V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT);
V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
out:
#include "v3d_drv.h"
#include "v3d_regs.h"
-#define V3D_MMU_PAGE_SHIFT 12
-
/* Note: All PTEs for the 1MB superpage must be filled with the
* superpage bit set.
*/
// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/backlight.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
* by Eric Miao <eric.miao@marvell.com>
*/
+#include <linux/backlight.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
# define STREAM_STATUS_CHANGED (1 << 2)
# define HDMI_LINK_STATUS_CHANGED (1 << 3)
# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
+# define DP_TUNNELING_IRQ (1 << 5)
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+/* DP-tunneling */
+#define DP_TUNNELING_OUI 0xe0000
+#define DP_TUNNELING_OUI_BYTES 3
+
+#define DP_TUNNELING_DEV_ID 0xe0003
+#define DP_TUNNELING_DEV_ID_BYTES 6
+
+#define DP_TUNNELING_HW_REV 0xe0009
+#define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4
+#define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
+#define DP_TUNNELING_HW_REV_MINOR_SHIFT 0
+#define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
+
+#define DP_TUNNELING_SW_REV_MAJOR 0xe000a
+#define DP_TUNNELING_SW_REV_MINOR 0xe000b
+
+#define DP_TUNNELING_CAPABILITIES 0xe000d
+#define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
+#define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6)
+#define DP_TUNNELING_SUPPORT (1 << 0)
+
+#define DP_IN_ADAPTER_INFO 0xe000e
+#define DP_IN_ADAPTER_NUMBER_BITS 7
+#define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)
+
+#define DP_USB4_DRIVER_ID 0xe000f
+#define DP_USB4_DRIVER_ID_BITS 4
+#define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1)
+
+#define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020
+#define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
+
+#define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021
+#define DP_GROUP_ID_BITS 3
+#define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1)
+
+#define DP_BW_GRANULARITY 0xe0022
+#define DP_BW_GRANULARITY_MASK 0x3
+
+#define DP_ESTIMATED_BW 0xe0023
+#define DP_ALLOCATED_BW 0xe0024
+
+#define DP_TUNNELING_STATUS 0xe0025
+#define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3)
+#define DP_ESTIMATED_BW_CHANGED (1 << 2)
+#define DP_BW_REQUEST_SUCCEEDED (1 << 1)
+#define DP_BW_REQUEST_FAILED (1 << 0)
+
+#define DP_TUNNELING_MAX_LINK_RATE 0xe0028
+
+#define DP_TUNNELING_MAX_LANE_COUNT 0xe0029
+#define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f
+
+#define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030
+#define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7)
+#define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6)
+
+#define DP_REQUEST_BW 0xe0031
+#define MAX_DP_REQUEST_BW 255
+
/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
+bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
* @is_remote: Is this AUX CH actually using sideband messaging.
*/
bool is_remote;
+
+ /**
+ * @powered_down: If true then the remote endpoint is powered down.
+ */
+ bool powered_down;
};
int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
+void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
void *buffer, size_t size);
ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
int dsc_slice_count,
int bpp_x16, unsigned long flags);
int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
+int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
+
+ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
#endif /* _DRM_DP_HELPER_H_ */
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __DRM_DP_TUNNEL_H__
+#define __DRM_DP_TUNNEL_H__
+
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct drm_dp_aux;
+
+struct drm_device;
+
+struct drm_atomic_state;
+struct drm_dp_tunnel_mgr;
+struct drm_dp_tunnel_state;
+
+struct ref_tracker;
+
+struct drm_dp_tunnel_ref {
+ struct drm_dp_tunnel *tunnel;
+ struct ref_tracker *tracker;
+};
+
+#ifdef CONFIG_DRM_DISPLAY_DP_TUNNEL
+
+struct drm_dp_tunnel *
+drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
+
+void
+drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker);
+
+static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
+ struct drm_dp_tunnel_ref *tunnel_ref)
+{
+ tunnel_ref->tunnel = drm_dp_tunnel_get(tunnel, &tunnel_ref->tracker);
+}
+
+static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref)
+{
+ drm_dp_tunnel_put(tunnel_ref->tunnel, &tunnel_ref->tracker);
+ tunnel_ref->tunnel = NULL;
+}
+
+struct drm_dp_tunnel *
+drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux);
+int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel);
+
+int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
+int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
+bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
+int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
+int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
+int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
+
+void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel);
+
+int drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux);
+
+int drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel);
+int drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel);
+int drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel);
+
+const char *drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel);
+
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel);
+
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_old_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel);
+
+struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel);
+
+int drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel,
+ u8 stream_id, int bw);
+int drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel,
+ u32 *stream_mask);
+
+int drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state,
+ u32 *failed_stream_mask);
+
+int drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state);
+
+struct drm_dp_tunnel_mgr *
+drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count);
+void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr);
+
+#else
+
+static inline struct drm_dp_tunnel *
+drm_dp_tunnel_get(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker)
+{
+ return NULL;
+}
+
+static inline void
+drm_dp_tunnel_put(struct drm_dp_tunnel *tunnel, struct ref_tracker **tracker) {}
+
+static inline void drm_dp_tunnel_ref_get(struct drm_dp_tunnel *tunnel,
+ struct drm_dp_tunnel_ref *tunnel_ref) {}
+
+static inline void drm_dp_tunnel_ref_put(struct drm_dp_tunnel_ref *tunnel_ref) {}
+
+static inline struct drm_dp_tunnel *
+drm_dp_tunnel_detect(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline int
+drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel)
+{
+ return 0;
+}
+
+static inline int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
+{
+ return false;
+}
+
+static inline int
+drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int
+drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel)
+{
+ return -1;
+}
+
+static inline int
+drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void drm_dp_tunnel_set_io_error(struct drm_dp_tunnel *tunnel) {}
+
+static inline int
+drm_dp_tunnel_handle_irq(struct drm_dp_tunnel_mgr *mgr,
+ struct drm_dp_aux *aux)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int
+drm_dp_tunnel_max_dprx_rate(const struct drm_dp_tunnel *tunnel)
+{
+ return 0;
+}
+
+static inline int
+drm_dp_tunnel_max_dprx_lane_count(const struct drm_dp_tunnel *tunnel)
+{
+ return 0;
+}
+
+static inline int
+drm_dp_tunnel_available_bw(const struct drm_dp_tunnel *tunnel)
+{
+ return -1;
+}
+
+static inline const char *
+drm_dp_tunnel_name(const struct drm_dp_tunnel *tunnel)
+{
+ return NULL;
+}
+
+static inline struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_state(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline struct drm_dp_tunnel_state *
+drm_dp_tunnel_atomic_get_new_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline int
+drm_dp_tunnel_atomic_set_stream_bw(struct drm_atomic_state *state,
+ struct drm_dp_tunnel *tunnel,
+ u8 stream_id, int bw)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int
+drm_dp_tunnel_atomic_get_group_streams_in_state(struct drm_atomic_state *state,
+ const struct drm_dp_tunnel *tunnel,
+ u32 *stream_mask)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int
+drm_dp_tunnel_atomic_check_stream_bws(struct drm_atomic_state *state,
+ u32 *failed_stream_mask)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int
+drm_dp_tunnel_atomic_get_required_bw(const struct drm_dp_tunnel_state *tunnel_state)
+{
+ return 0;
+}
+
+static inline struct drm_dp_tunnel_mgr *
+drm_dp_tunnel_mgr_create(struct drm_device *dev, int max_group_count)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline
+void drm_dp_tunnel_mgr_destroy(struct drm_dp_tunnel_mgr *mgr) {}
+
+#endif /* CONFIG_DRM_DISPLAY_DP_TUNNEL */
+
+#endif /* __DRM_DP_TUNNEL_H__ */
#ifndef DRM_KUNIT_HELPERS_H_
#define DRM_KUNIT_HELPERS_H_
+#include <drm/drm_drv.h>
+
#include <linux/device.h>
#include <kunit/test.h>
+struct drm_crtc_funcs;
+struct drm_crtc_helper_funcs;
struct drm_device;
+struct drm_plane_funcs;
+struct drm_plane_helper_funcs;
struct kunit;
struct device *drm_kunit_helper_alloc_device(struct kunit *test);
struct drm_device *drm,
struct drm_modeset_acquire_ctx *ctx);
+struct drm_plane *
+drm_kunit_helper_create_primary_plane(struct kunit *test,
+ struct drm_device *drm,
+ const struct drm_plane_funcs *funcs,
+ const struct drm_plane_helper_funcs *helper_funcs,
+ const uint32_t *formats,
+ unsigned int num_formats,
+ const uint64_t *modifiers);
+
+struct drm_crtc *
+drm_kunit_helper_create_crtc(struct kunit *test,
+ struct drm_device *drm,
+ struct drm_plane *primary,
+ struct drm_plane *cursor,
+ const struct drm_crtc_funcs *funcs,
+ const struct drm_crtc_helper_funcs *helper_funcs);
+
#endif // DRM_KUNIT_HELPERS_H_
#define INTEL_ADLN_IDS(info) \
INTEL_VGA_DEVICE(0x46D0, info), \
INTEL_VGA_DEVICE(0x46D1, info), \
- INTEL_VGA_DEVICE(0x46D2, info)
+ INTEL_VGA_DEVICE(0x46D2, info), \
+ INTEL_VGA_DEVICE(0x46D3, info), \
+ INTEL_VGA_DEVICE(0x46D4, info)
/* RPL-S */
#define INTEL_RPLS_IDS(info) \
#ifndef _LINUX_FB_H
#define _LINUX_FB_H
-#include <linux/refcount.h>
-#include <linux/kgdb.h>
#include <uapi/linux/fb.h>
#define FBIO_CURSOR _IOWR('F', 0x08, struct fb_cursor_user)
-#include <linux/fs.h>
-#include <linux/init.h>
+#include <linux/mutex.h>
+#include <linux/printk.h>
+#include <linux/refcount.h>
+#include <linux/types.h>
#include <linux/workqueue.h>
-#include <linux/notifier.h>
-#include <linux/list.h>
-#include <linux/backlight.h>
-#include <linux/slab.h>
#include <asm/fb.h>
-struct vm_area_struct;
-struct fb_info;
+struct backlight_device;
struct device;
+struct device_node;
+struct fb_info;
struct file;
+struct i2c_adapter;
+struct inode;
+struct module;
+struct notifier_block;
+struct page;
struct videomode;
-struct device_node;
+struct vm_area_struct;
/* Definitions below are used in the parsed monitor specs */
#define FB_DPMS_ACTIVE_OFF 1
* struct drm_i915_query_guc_submission_version - query GuC submission interface version
*/
struct drm_i915_query_guc_submission_version {
+ /** @branch: Firmware branch version. */
__u32 branch;
+ /** @major: Firmware major version. */
__u32 major;
+ /** @minor: Firmware minor version. */
__u32 minor;
+ /** @patch: Firmware patch version. */
__u32 patch;
};
+++ /dev/null
-/*
- 1024x768.S: EDID data set for standard 1024x768 60 Hz monitor
-
- Copyright (C) 2011 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 65000 /* kHz */
-#define XPIX 1024
-#define YPIX 768
-#define XY_RATIO XY_RATIO_4_3
-#define XBLANK 320
-#define YBLANK 38
-#define XOFFSET 8
-#define XPULSE 144
-#define YOFFSET 3
-#define YPULSE 6
-#define DPI 72
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux XGA"
-#define ESTABLISHED_TIMING2_BITS 0x08 /* Bit 3 -> 1024x768 @60 Hz */
-#define HSYNC_POL 0
-#define VSYNC_POL 0
-
-#include "edid.S"
+++ /dev/null
-/*
- 1280x1024.S: EDID data set for standard 1280x1024 60 Hz monitor
-
- Copyright (C) 2011 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 108000 /* kHz */
-#define XPIX 1280
-#define YPIX 1024
-#define XY_RATIO XY_RATIO_5_4
-#define XBLANK 408
-#define YBLANK 42
-#define XOFFSET 48
-#define XPULSE 112
-#define YOFFSET 1
-#define YPULSE 3
-#define DPI 72
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux SXGA"
-/* No ESTABLISHED_TIMINGx_BITS */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-
-#include "edid.S"
+++ /dev/null
-/*
- 1600x1200.S: EDID data set for standard 1600x1200 60 Hz monitor
-
- Copyright (C) 2013 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 162000 /* kHz */
-#define XPIX 1600
-#define YPIX 1200
-#define XY_RATIO XY_RATIO_4_3
-#define XBLANK 560
-#define YBLANK 50
-#define XOFFSET 64
-#define XPULSE 192
-#define YOFFSET 1
-#define YPULSE 3
-#define DPI 72
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux UXGA"
-/* No ESTABLISHED_TIMINGx_BITS */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-
-#include "edid.S"
+++ /dev/null
-/*
- 1680x1050.S: EDID data set for standard 1680x1050 60 Hz monitor
-
- Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 146250 /* kHz */
-#define XPIX 1680
-#define YPIX 1050
-#define XY_RATIO XY_RATIO_16_10
-#define XBLANK 560
-#define YBLANK 39
-#define XOFFSET 104
-#define XPULSE 176
-#define YOFFSET 3
-#define YPULSE 6
-#define DPI 96
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux WSXGA"
-/* No ESTABLISHED_TIMINGx_BITS */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-
-#include "edid.S"
+++ /dev/null
-/*
- 1920x1080.S: EDID data set for standard 1920x1080 60 Hz monitor
-
- Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 148500 /* kHz */
-#define XPIX 1920
-#define YPIX 1080
-#define XY_RATIO XY_RATIO_16_9
-#define XBLANK 280
-#define YBLANK 45
-#define XOFFSET 88
-#define XPULSE 44
-#define YOFFSET 4
-#define YPULSE 5
-#define DPI 96
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux FHD"
-/* No ESTABLISHED_TIMINGx_BITS */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-
-#include "edid.S"
+++ /dev/null
-/*
- 800x600.S: EDID data set for standard 800x600 60 Hz monitor
-
- Copyright (C) 2011 Carsten Emde <C.Emde@osadl.org>
- Copyright (C) 2014 Linaro Limited
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 40000 /* kHz */
-#define XPIX 800
-#define YPIX 600
-#define XY_RATIO XY_RATIO_4_3
-#define XBLANK 256
-#define YBLANK 28
-#define XOFFSET 40
-#define XPULSE 128
-#define YOFFSET 1
-#define YPULSE 4
-#define DPI 72
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux SVGA"
-#define ESTABLISHED_TIMING1_BITS 0x01 /* Bit 0: 800x600 @ 60Hz */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-
-#include "edid.S"
+++ /dev/null
-
-SOURCES := $(wildcard [0-9]*x[0-9]*.S)
-
-BIN := $(patsubst %.S, %.bin, $(SOURCES))
-
-IHEX := $(patsubst %.S, %.bin.ihex, $(SOURCES))
-
-CODE := $(patsubst %.S, %.c, $(SOURCES))
-
-all: $(BIN) $(IHEX) $(CODE)
-
-clean:
- @rm -f *.o *.bin.ihex *.bin *.c
-
-%.o: %.S
- @cc -c $^
-
-%.bin.nocrc: %.o
- @objcopy -Obinary $^ $@
-
-%.crc: %.bin.nocrc
- @list=$$(for i in `seq 1 127`; do head -c$$i $^ | tail -c1 \
- | hexdump -v -e '/1 "%02X+"'; done); \
- echo "ibase=16;100-($${list%?})%100" | bc >$@
-
-%.p: %.crc %.S
- @cc -c -DCRC="$$(cat $*.crc)" -o $@ $*.S
-
-%.bin: %.p
- @objcopy -Obinary $^ $@
-
-%.bin.ihex: %.p
- @objcopy -Oihex $^ $@
- @dos2unix $@ 2>/dev/null
-
-%.c: %.bin
- @echo "{" >$@; hexdump -f hex $^ >>$@; echo "};" >>$@
+++ /dev/null
-/*
- edid.S: EDID data template
-
- Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-
-/* Manufacturer */
-#define MFG_LNX1 'L'
-#define MFG_LNX2 'N'
-#define MFG_LNX3 'X'
-#define SERIAL 0
-#define YEAR 2012
-#define WEEK 5
-
-/* EDID 1.3 standard definitions */
-#define XY_RATIO_16_10 0b00
-#define XY_RATIO_4_3 0b01
-#define XY_RATIO_5_4 0b10
-#define XY_RATIO_16_9 0b11
-
-/* Provide defaults for the timing bits */
-#ifndef ESTABLISHED_TIMING1_BITS
-#define ESTABLISHED_TIMING1_BITS 0x00
-#endif
-#ifndef ESTABLISHED_TIMING2_BITS
-#define ESTABLISHED_TIMING2_BITS 0x00
-#endif
-#ifndef ESTABLISHED_TIMING3_BITS
-#define ESTABLISHED_TIMING3_BITS 0x00
-#endif
-
-#define mfgname2id(v1,v2,v3) \
- ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
-#define swap16(v1) ((v1>>8)+((v1&0xff)<<8))
-#define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f))
-#define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
-#define msbs4(v1,v2,v3,v4) \
- ((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\
- (((v3>>4)&0x03)<<2)+((v4>>4)&0x03))
-#define pixdpi2mm(pix,dpi) ((pix*25)/dpi)
-#define xsize pixdpi2mm(XPIX,DPI)
-#define ysize pixdpi2mm(YPIX,DPI)
-
- .data
-
-/* Fixed header pattern */
-header: .byte 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00
-
-mfg_id: .hword swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))
-
-prod_code: .hword 0
-
-/* Serial number. 32 bits, little endian. */
-serial_number: .long SERIAL
-
-/* Week of manufacture */
-week: .byte WEEK
-
-/* Year of manufacture, less 1990. (1990-2245)
- If week=255, it is the model year instead */
-year: .byte YEAR-1990
-
-version: .byte VERSION /* EDID version, usually 1 (for 1.3) */
-revision: .byte REVISION /* EDID revision, usually 3 (for 1.3) */
-
-/* If Bit 7=1 Digital input. If set, the following bit definitions apply:
- Bits 6-1 Reserved, must be 0
- Bit 0 Signal is compatible with VESA DFP 1.x TMDS CRGB,
- 1 pixel per clock, up to 8 bits per color, MSB aligned,
- If Bit 7=0 Analog input. If clear, the following bit definitions apply:
- Bits 6-5 Video white and sync levels, relative to blank
- 00=+0.7/-0.3 V; 01=+0.714/-0.286 V;
- 10=+1.0/-0.4 V; 11=+0.7/0 V
- Bit 4 Blank-to-black setup (pedestal) expected
- Bit 3 Separate sync supported
- Bit 2 Composite sync (on HSync) supported
- Bit 1 Sync on green supported
- Bit 0 VSync pulse must be serrated when somposite or
- sync-on-green is used. */
-video_parms: .byte 0x6d
-
-/* Maximum horizontal image size, in centimetres
- (max 292 cm/115 in at 16:9 aspect ratio) */
-max_hor_size: .byte xsize/10
-
-/* Maximum vertical image size, in centimetres.
- If either byte is 0, undefined (e.g. projector) */
-max_vert_size: .byte ysize/10
-
-/* Display gamma, minus 1, times 100 (range 1.00-3.5 */
-gamma: .byte 120
-
-/* Bit 7 DPMS standby supported
- Bit 6 DPMS suspend supported
- Bit 5 DPMS active-off supported
- Bits 4-3 Display type: 00=monochrome; 01=RGB colour;
- 10=non-RGB multicolour; 11=undefined
- Bit 2 Standard sRGB colour space. Bytes 25-34 must contain
- sRGB standard values.
- Bit 1 Preferred timing mode specified in descriptor block 1.
- Bit 0 GTF supported with default parameter values. */
-dsp_features: .byte 0xea
-
-/* Chromaticity coordinates. */
-/* Red and green least-significant bits
- Bits 7-6 Red x value least-significant 2 bits
- Bits 5-4 Red y value least-significant 2 bits
- Bits 3-2 Green x value lst-significant 2 bits
- Bits 1-0 Green y value least-significant 2 bits */
-red_green_lsb: .byte 0x5e
-
-/* Blue and white least-significant 2 bits */
-blue_white_lsb: .byte 0xc0
-
-/* Red x value most significant 8 bits.
- 0-255 encodes 0-0.996 (255/256); 0-0.999 (1023/1024) with lsbits */
-red_x_msb: .byte 0xa4
-
-/* Red y value most significant 8 bits */
-red_y_msb: .byte 0x59
-
-/* Green x and y value most significant 8 bits */
-green_x_y_msb: .byte 0x4a,0x98
-
-/* Blue x and y value most significant 8 bits */
-blue_x_y_msb: .byte 0x25,0x20
-
-/* Default white point x and y value most significant 8 bits */
-white_x_y_msb: .byte 0x50,0x54
-
-/* Established timings */
-/* Bit 7 720x400 @ 70 Hz
- Bit 6 720x400 @ 88 Hz
- Bit 5 640x480 @ 60 Hz
- Bit 4 640x480 @ 67 Hz
- Bit 3 640x480 @ 72 Hz
- Bit 2 640x480 @ 75 Hz
- Bit 1 800x600 @ 56 Hz
- Bit 0 800x600 @ 60 Hz */
-estbl_timing1: .byte ESTABLISHED_TIMING1_BITS
-
-/* Bit 7 800x600 @ 72 Hz
- Bit 6 800x600 @ 75 Hz
- Bit 5 832x624 @ 75 Hz
- Bit 4 1024x768 @ 87 Hz, interlaced (1024x768)
- Bit 3 1024x768 @ 60 Hz
- Bit 2 1024x768 @ 72 Hz
- Bit 1 1024x768 @ 75 Hz
- Bit 0 1280x1024 @ 75 Hz */
-estbl_timing2: .byte ESTABLISHED_TIMING2_BITS
-
-/* Bit 7 1152x870 @ 75 Hz (Apple Macintosh II)
- Bits 6-0 Other manufacturer-specific display mod */
-estbl_timing3: .byte ESTABLISHED_TIMING3_BITS
-
-/* Standard timing */
-/* X resolution, less 31, divided by 8 (256-2288 pixels) */
-std_xres: .byte (XPIX/8)-31
-/* Y resolution, X:Y pixel ratio
- Bits 7-6 X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9.
- Bits 5-0 Vertical frequency, less 60 (60-123 Hz) */
-std_vres: .byte (XY_RATIO<<6)+VFREQ-60
- .fill 7,2,0x0101 /* Unused */
-
-descriptor1:
-/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */
-clock: .hword CLOCK/10
-
-/* Horizontal active pixels 8 lsbits (0-4095) */
-x_act_lsb: .byte XPIX&0xff
-/* Horizontal blanking pixels 8 lsbits (0-4095)
- End of active to start of next active. */
-x_blk_lsb: .byte XBLANK&0xff
-/* Bits 7-4 Horizontal active pixels 4 msbits
- Bits 3-0 Horizontal blanking pixels 4 msbits */
-x_msbs: .byte msbs2(XPIX,XBLANK)
-
-/* Vertical active lines 8 lsbits (0-4095) */
-y_act_lsb: .byte YPIX&0xff
-/* Vertical blanking lines 8 lsbits (0-4095) */
-y_blk_lsb: .byte YBLANK&0xff
-/* Bits 7-4 Vertical active lines 4 msbits
- Bits 3-0 Vertical blanking lines 4 msbits */
-y_msbs: .byte msbs2(YPIX,YBLANK)
-
-/* Horizontal sync offset pixels 8 lsbits (0-1023) From blanking start */
-x_snc_off_lsb: .byte XOFFSET&0xff
-/* Horizontal sync pulse width pixels 8 lsbits (0-1023) */
-x_snc_pls_lsb: .byte XPULSE&0xff
-/* Bits 7-4 Vertical sync offset lines 4 lsbits (0-63)
- Bits 3-0 Vertical sync pulse width lines 4 lsbits (0-63) */
-y_snc_lsb: .byte lsbs2(YOFFSET, YPULSE)
-/* Bits 7-6 Horizontal sync offset pixels 2 msbits
- Bits 5-4 Horizontal sync pulse width pixels 2 msbits
- Bits 3-2 Vertical sync offset lines 2 msbits
- Bits 1-0 Vertical sync pulse width lines 2 msbits */
-xy_snc_msbs: .byte msbs4(XOFFSET,XPULSE,YOFFSET,YPULSE)
-
-/* Horizontal display size, mm, 8 lsbits (0-4095 mm, 161 in) */
-x_dsp_size: .byte xsize&0xff
-
-/* Vertical display size, mm, 8 lsbits (0-4095 mm, 161 in) */
-y_dsp_size: .byte ysize&0xff
-
-/* Bits 7-4 Horizontal display size, mm, 4 msbits
- Bits 3-0 Vertical display size, mm, 4 msbits */
-dsp_size_mbsb: .byte msbs2(xsize,ysize)
-
-/* Horizontal border pixels (each side; total is twice this) */
-x_border: .byte 0
-/* Vertical border lines (each side; total is twice this) */
-y_border: .byte 0
-
-/* Bit 7 Interlaced
- Bits 6-5 Stereo mode: 00=No stereo; other values depend on bit 0:
- Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar,
- sync=1 during left; 11=4-way interleaved stereo
- Bit 0=1 2-way interleaved stereo: 01=Right image on even lines;
- 10=Left image on even lines; 11=side-by-side
- Bits 4-3 Sync type: 00=Analog composite; 01=Bipolar analog composite;
- 10=Digital composite (on HSync); 11=Digital separate
- Bit 2 If digital separate: Vertical sync polarity (1=positive)
- Other types: VSync serrated (HSync during VSync)
- Bit 1 If analog sync: Sync on all 3 RGB lines (else green only)
- Digital: HSync polarity (1=positive)
- Bit 0 2-way line-interleaved stereo, if bits 4-3 are not 00. */
-features: .byte 0x18+(VSYNC_POL<<2)+(HSYNC_POL<<1)
-
-descriptor2: .byte 0,0 /* Not a detailed timing descriptor */
- .byte 0 /* Must be zero */
- .byte 0xff /* Descriptor is monitor serial number (text) */
- .byte 0 /* Must be zero */
-start1: .ascii "Linux #0"
-end1: .byte 0x0a /* End marker */
- .fill 12-(end1-start1), 1, 0x20 /* Padded spaces */
-descriptor3: .byte 0,0 /* Not a detailed timing descriptor */
- .byte 0 /* Must be zero */
- .byte 0xfd /* Descriptor is monitor range limits */
- .byte 0 /* Must be zero */
-start2: .byte VFREQ-1 /* Minimum vertical field rate (1-255 Hz) */
- .byte VFREQ+1 /* Maximum vertical field rate (1-255 Hz) */
- .byte (CLOCK/(XPIX+XBLANK))-1 /* Minimum horizontal line rate
- (1-255 kHz) */
- .byte (CLOCK/(XPIX+XBLANK))+1 /* Maximum horizontal line rate
- (1-255 kHz) */
- .byte (CLOCK/10000)+1 /* Maximum pixel clock rate, rounded up
- to 10 MHz multiple (10-2550 MHz) */
- .byte 0 /* No extended timing information type */
-end2: .byte 0x0a /* End marker */
- .fill 12-(end2-start2), 1, 0x20 /* Padded spaces */
-descriptor4: .byte 0,0 /* Not a detailed timing descriptor */
- .byte 0 /* Must be zero */
- .byte 0xfc /* Descriptor is text */
- .byte 0 /* Must be zero */
-start3: .ascii TIMING_NAME
-end3: .byte 0x0a /* End marker */
- .fill 12-(end3-start3), 1, 0x20 /* Padded spaces */
-extensions: .byte 0 /* Number of extensions to follow */
-checksum: .byte CRC /* Sum of all bytes must be 0 */
+++ /dev/null
-"\t" 8/1 "0x%02x, " "\n"
git.samba.org / sfrench / cifs-2.6.git / commitdiff