arm64: dts: qcom: sm8250: Add cpufreq hw node

Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores
on SM8250 SoCs.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Amit Kucheria <amitk@kernel.org>
Link: https://lore.kernel.org/r/20200915072423.18437-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index f49a4a1651e23b4fced3f82095d191889cbda41e..357e4bfba70c42a1e1c078431581febd5798f4f6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -89,6 +89,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -104,6 +105,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -116,6 +118,7 @@
                        reg = <0x0 0x200>;
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -128,6 +131,7 @@
                        reg = <0x0 0x300>;
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -140,6 +144,7 @@
                        reg = <0x0 0x400>;
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_400: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -152,6 +157,7 @@
                        reg = <0x0 0x500>;
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_500: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -165,6 +171,7 @@
                        reg = <0x0 0x600>;
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -177,6 +184,7 @@
                        reg = <0x0 0x700>;
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
+                       qcom,freq-domain = <&cpufreq_hw 2>;
                        L2_700: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -2316,6 +2324,20 @@
 
                        #interconnect-cells = <1>;
                };
+
+               cpufreq_hw: cpufreq@18591000 {
+                       compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
+                       reg = <0 0x18591000 0 0x1000>,
+                             <0 0x18592000 0 0x1000>,
+                             <0 0x18593000 0 0x1000>;
+                       reg-names = "freq-domain0", "freq-domain1",
+                                   "freq-domain2";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
        };
 
        timer {