1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <linux/uaccess.h>
11 #include <asm/kvm_mmu.h>
12 #include <asm/cputype.h>
17 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
18 phys_addr_t addr, phys_addr_t alignment)
20 if (addr & ~kvm_phys_mask(kvm))
23 if (!IS_ALIGNED(addr, alignment))
26 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
32 static int vgic_check_type(struct kvm *kvm, int type_needed)
34 if (kvm->arch.vgic.vgic_model != type_needed)
41 * kvm_vgic_addr - set or get vgic VM base addresses
42 * @kvm: pointer to the vm struct
43 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
44 * @addr: pointer to address value
45 * @write: if true set the address in the VM address space, if false read the
48 * Set or get the vgic base addresses for the distributor and the virtual CPU
49 * interface in the VM physical address space. These addresses are properties
50 * of the emulated core/SoC and therefore user space initially knows this
52 * Check them for sanity (alignment, double assignment). We can't check for
53 * overlapping regions in case of a virtual GICv3 here, since we don't know
54 * the number of VCPUs yet, so we defer this check to map_resources().
56 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
59 struct vgic_dist *vgic = &kvm->arch.vgic;
60 phys_addr_t *addr_ptr, alignment;
61 u64 undef_value = VGIC_ADDR_UNDEF;
63 mutex_lock(&kvm->lock);
65 case KVM_VGIC_V2_ADDR_TYPE_DIST:
66 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
67 addr_ptr = &vgic->vgic_dist_base;
70 case KVM_VGIC_V2_ADDR_TYPE_CPU:
71 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
72 addr_ptr = &vgic->vgic_cpu_base;
75 case KVM_VGIC_V3_ADDR_TYPE_DIST:
76 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
77 addr_ptr = &vgic->vgic_dist_base;
80 case KVM_VGIC_V3_ADDR_TYPE_REDIST: {
81 struct vgic_redist_region *rdreg;
83 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
87 r = vgic_v3_set_redist_base(kvm, 0, *addr, 0);
90 rdreg = list_first_entry(&vgic->rd_regions,
91 struct vgic_redist_region, list);
93 addr_ptr = &undef_value;
95 addr_ptr = &rdreg->base;
98 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
100 struct vgic_redist_region *rdreg;
103 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
107 index = *addr & KVM_VGIC_V3_RDIST_INDEX_MASK;
110 gpa_t base = *addr & KVM_VGIC_V3_RDIST_BASE_MASK;
111 u32 count = (*addr & KVM_VGIC_V3_RDIST_COUNT_MASK)
112 >> KVM_VGIC_V3_RDIST_COUNT_SHIFT;
113 u8 flags = (*addr & KVM_VGIC_V3_RDIST_FLAGS_MASK)
114 >> KVM_VGIC_V3_RDIST_FLAGS_SHIFT;
119 r = vgic_v3_set_redist_base(kvm, index,
124 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
131 *addr |= rdreg->base;
132 *addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT;
143 r = vgic_check_ioaddr(kvm, addr_ptr, *addr, alignment);
151 mutex_unlock(&kvm->lock);
155 static int vgic_set_common_attr(struct kvm_device *dev,
156 struct kvm_device_attr *attr)
160 switch (attr->group) {
161 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
162 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
164 unsigned long type = (unsigned long)attr->attr;
166 if (copy_from_user(&addr, uaddr, sizeof(addr)))
169 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
170 return (r == -ENODEV) ? -ENXIO : r;
172 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
173 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
177 if (get_user(val, uaddr))
182 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
183 * - at most 1024 interrupts
184 * - a multiple of 32 interrupts
186 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
187 val > VGIC_MAX_RESERVED ||
191 mutex_lock(&dev->kvm->lock);
193 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_spis)
196 dev->kvm->arch.vgic.nr_spis =
197 val - VGIC_NR_PRIVATE_IRQS;
199 mutex_unlock(&dev->kvm->lock);
203 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
204 switch (attr->attr) {
205 case KVM_DEV_ARM_VGIC_CTRL_INIT:
206 mutex_lock(&dev->kvm->lock);
207 r = vgic_init(dev->kvm);
208 mutex_unlock(&dev->kvm->lock);
218 static int vgic_get_common_attr(struct kvm_device *dev,
219 struct kvm_device_attr *attr)
223 switch (attr->group) {
224 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
225 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
227 unsigned long type = (unsigned long)attr->attr;
229 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
231 return (r == -ENODEV) ? -ENXIO : r;
233 if (copy_to_user(uaddr, &addr, sizeof(addr)))
237 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
238 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
240 r = put_user(dev->kvm->arch.vgic.nr_spis +
241 VGIC_NR_PRIVATE_IRQS, uaddr);
249 static int vgic_create(struct kvm_device *dev, u32 type)
251 return kvm_vgic_create(dev->kvm, type);
254 static void vgic_destroy(struct kvm_device *dev)
259 int kvm_register_vgic_device(unsigned long type)
264 case KVM_DEV_TYPE_ARM_VGIC_V2:
265 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
266 KVM_DEV_TYPE_ARM_VGIC_V2);
268 case KVM_DEV_TYPE_ARM_VGIC_V3:
269 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
270 KVM_DEV_TYPE_ARM_VGIC_V3);
274 ret = kvm_vgic_register_its_device();
281 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
282 struct vgic_reg_attr *reg_attr)
286 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
287 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
289 if (cpuid >= atomic_read(&dev->kvm->online_vcpus))
292 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, cpuid);
293 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
298 /* unlocks vcpus from @vcpu_lock_idx and smaller */
299 static void unlock_vcpus(struct kvm *kvm, int vcpu_lock_idx)
301 struct kvm_vcpu *tmp_vcpu;
303 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
304 tmp_vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
305 mutex_unlock(&tmp_vcpu->mutex);
309 void unlock_all_vcpus(struct kvm *kvm)
311 unlock_vcpus(kvm, atomic_read(&kvm->online_vcpus) - 1);
314 /* Returns true if all vcpus were locked, false otherwise */
315 bool lock_all_vcpus(struct kvm *kvm)
317 struct kvm_vcpu *tmp_vcpu;
321 * Any time a vcpu is run, vcpu_load is called which tries to grab the
322 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
323 * that no other VCPUs are run and fiddle with the vgic state while we
326 kvm_for_each_vcpu(c, tmp_vcpu, kvm) {
327 if (!mutex_trylock(&tmp_vcpu->mutex)) {
328 unlock_vcpus(kvm, c - 1);
337 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
339 * @dev: kvm device handle
340 * @attr: kvm device attribute
341 * @reg: address the value is read or written
342 * @is_write: true if userspace is writing a register
344 static int vgic_v2_attr_regs_access(struct kvm_device *dev,
345 struct kvm_device_attr *attr,
346 u32 *reg, bool is_write)
348 struct vgic_reg_attr reg_attr;
350 struct kvm_vcpu *vcpu;
353 ret = vgic_v2_parse_attr(dev, attr, ®_attr);
357 vcpu = reg_attr.vcpu;
358 addr = reg_attr.addr;
360 mutex_lock(&dev->kvm->lock);
362 ret = vgic_init(dev->kvm);
366 if (!lock_all_vcpus(dev->kvm)) {
371 switch (attr->group) {
372 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
373 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, reg);
375 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
376 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, reg);
383 unlock_all_vcpus(dev->kvm);
385 mutex_unlock(&dev->kvm->lock);
389 static int vgic_v2_set_attr(struct kvm_device *dev,
390 struct kvm_device_attr *attr)
394 ret = vgic_set_common_attr(dev, attr);
398 switch (attr->group) {
399 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
400 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
401 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
404 if (get_user(reg, uaddr))
407 return vgic_v2_attr_regs_access(dev, attr, ®, true);
414 static int vgic_v2_get_attr(struct kvm_device *dev,
415 struct kvm_device_attr *attr)
419 ret = vgic_get_common_attr(dev, attr);
423 switch (attr->group) {
424 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
425 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
426 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
429 ret = vgic_v2_attr_regs_access(dev, attr, ®, false);
432 return put_user(reg, uaddr);
439 static int vgic_v2_has_attr(struct kvm_device *dev,
440 struct kvm_device_attr *attr)
442 switch (attr->group) {
443 case KVM_DEV_ARM_VGIC_GRP_ADDR:
444 switch (attr->attr) {
445 case KVM_VGIC_V2_ADDR_TYPE_DIST:
446 case KVM_VGIC_V2_ADDR_TYPE_CPU:
450 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
451 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
452 return vgic_v2_has_attr_regs(dev, attr);
453 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
455 case KVM_DEV_ARM_VGIC_GRP_CTRL:
456 switch (attr->attr) {
457 case KVM_DEV_ARM_VGIC_CTRL_INIT:
464 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
465 .name = "kvm-arm-vgic-v2",
466 .create = vgic_create,
467 .destroy = vgic_destroy,
468 .set_attr = vgic_v2_set_attr,
469 .get_attr = vgic_v2_get_attr,
470 .has_attr = vgic_v2_has_attr,
473 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
474 struct vgic_reg_attr *reg_attr)
476 unsigned long vgic_mpidr, mpidr_reg;
479 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
480 * attr might not hold MPIDR. Hence assume vcpu0.
482 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
483 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
484 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
486 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
487 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
489 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
495 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
501 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
503 * @dev: kvm device handle
504 * @attr: kvm device attribute
505 * @reg: address the value is read or written
506 * @is_write: true if userspace is writing a register
508 static int vgic_v3_attr_regs_access(struct kvm_device *dev,
509 struct kvm_device_attr *attr,
510 u64 *reg, bool is_write)
512 struct vgic_reg_attr reg_attr;
514 struct kvm_vcpu *vcpu;
518 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
522 vcpu = reg_attr.vcpu;
523 addr = reg_attr.addr;
525 mutex_lock(&dev->kvm->lock);
527 if (unlikely(!vgic_initialized(dev->kvm))) {
532 if (!lock_all_vcpus(dev->kvm)) {
537 switch (attr->group) {
538 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
542 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
546 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
550 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
554 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
557 regid = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
558 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, is_write,
562 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
563 unsigned int info, intid;
565 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
566 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
567 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
569 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
570 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
582 unlock_all_vcpus(dev->kvm);
584 mutex_unlock(&dev->kvm->lock);
588 static int vgic_v3_set_attr(struct kvm_device *dev,
589 struct kvm_device_attr *attr)
593 ret = vgic_set_common_attr(dev, attr);
597 switch (attr->group) {
598 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
599 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
600 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
604 if (get_user(tmp32, uaddr))
608 return vgic_v3_attr_regs_access(dev, attr, ®, true);
610 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
611 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
614 if (get_user(reg, uaddr))
617 return vgic_v3_attr_regs_access(dev, attr, ®, true);
619 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
620 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
624 if (get_user(tmp32, uaddr))
628 return vgic_v3_attr_regs_access(dev, attr, ®, true);
630 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
633 switch (attr->attr) {
634 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
635 mutex_lock(&dev->kvm->lock);
637 if (!lock_all_vcpus(dev->kvm)) {
638 mutex_unlock(&dev->kvm->lock);
641 ret = vgic_v3_save_pending_tables(dev->kvm);
642 unlock_all_vcpus(dev->kvm);
643 mutex_unlock(&dev->kvm->lock);
652 static int vgic_v3_get_attr(struct kvm_device *dev,
653 struct kvm_device_attr *attr)
657 ret = vgic_get_common_attr(dev, attr);
661 switch (attr->group) {
662 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
663 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
664 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
668 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
672 return put_user(tmp32, uaddr);
674 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
675 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
678 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
681 return put_user(reg, uaddr);
683 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
684 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
688 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
692 return put_user(tmp32, uaddr);
698 static int vgic_v3_has_attr(struct kvm_device *dev,
699 struct kvm_device_attr *attr)
701 switch (attr->group) {
702 case KVM_DEV_ARM_VGIC_GRP_ADDR:
703 switch (attr->attr) {
704 case KVM_VGIC_V3_ADDR_TYPE_DIST:
705 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
706 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
710 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
711 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
712 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
713 return vgic_v3_has_attr_regs(dev, attr);
714 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
716 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
717 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
718 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
719 VGIC_LEVEL_INFO_LINE_LEVEL)
723 case KVM_DEV_ARM_VGIC_GRP_CTRL:
724 switch (attr->attr) {
725 case KVM_DEV_ARM_VGIC_CTRL_INIT:
727 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
734 struct kvm_device_ops kvm_arm_vgic_v3_ops = {
735 .name = "kvm-arm-vgic-v3",
736 .create = vgic_create,
737 .destroy = vgic_destroy,
738 .set_attr = vgic_v3_set_attr,
739 .get_attr = vgic_v3_get_attr,
740 .has_attr = vgic_v3_has_attr,