1 // SPDX-License-Identifier: GPL-2.0-only
3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
10 #include <linux/clk-provider.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/regmap.h>
17 #include <sound/asoundef.h>
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
22 #include "stm32_sai.h"
24 #define SAI_FREE_PROTOCOL 0x0
25 #define SAI_SPDIF_PROTOCOL 0x1
27 #define SAI_SLOT_SIZE_AUTO 0x0
28 #define SAI_SLOT_SIZE_16 0x1
29 #define SAI_SLOT_SIZE_32 0x2
31 #define SAI_DATASIZE_8 0x2
32 #define SAI_DATASIZE_10 0x3
33 #define SAI_DATASIZE_16 0x4
34 #define SAI_DATASIZE_20 0x5
35 #define SAI_DATASIZE_24 0x6
36 #define SAI_DATASIZE_32 0x7
38 #define STM_SAI_FIFO_SIZE 8
39 #define STM_SAI_DAI_NAME_SIZE 15
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
44 #define STM_SAI_A_ID 0x0
45 #define STM_SAI_B_ID 0x1
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
48 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
49 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
51 #define SAI_SYNC_NONE 0x0
52 #define SAI_SYNC_INTERNAL 0x1
53 #define SAI_SYNC_EXTERNAL 0x2
55 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
56 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif)
57 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
59 #define SAI_IEC60958_BLOCK_FRAMES 192
60 #define SAI_IEC60958_STATUS_BYTES 24
62 #define SAI_MCLK_NAME_LEN 32
63 #define SAI_RATE_11K 11025
66 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
67 * @pdev: device data pointer
68 * @regmap: SAI register map pointer
69 * @regmap_config: SAI sub block register map configuration pointer
70 * @dma_params: dma configuration data for rx or tx channel
71 * @cpu_dai_drv: DAI driver data pointer
72 * @cpu_dai: DAI runtime data pointer
73 * @substream: PCM substream data pointer
74 * @pdata: SAI block parent data pointer
75 * @np_sync_provider: synchronization provider node
76 * @sai_ck: kernel clock feeding the SAI clock generator
77 * @sai_mclk: master clock from SAI mclk provider
78 * @phys_addr: SAI registers physical base address
79 * @mclk_rate: SAI block master clock frequency (Hz). set at init
80 * @id: SAI sub block id corresponding to sub-block A or B
81 * @dir: SAI block direction (playback or capture). set at init
82 * @master: SAI block mode flag. (true=master, false=slave) set at init
83 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
84 * @fmt: SAI block format. relevant only for custom protocols. set at init
85 * @sync: SAI block synchronization mode. (none, internal or external)
86 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
87 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
88 * @fs_length: frame synchronization length. depends on protocol settings
89 * @slots: rx or tx slot number
90 * @slot_width: rx or tx slot width in bits
91 * @slot_mask: rx or tx active slots mask. set at init or at runtime
92 * @data_size: PCM data width. corresponds to PCM substream width.
93 * @spdif_frm_cnt: S/PDIF playback frame counter
94 * @iec958: iec958 data
95 * @ctrl_lock: control lock
96 * @irq_lock: prevent race condition with IRQ
98 struct stm32_sai_sub_data {
99 struct platform_device *pdev;
100 struct regmap *regmap;
101 const struct regmap_config *regmap_config;
102 struct snd_dmaengine_dai_dma_data dma_params;
103 struct snd_soc_dai_driver cpu_dai_drv;
104 struct snd_soc_dai *cpu_dai;
105 struct snd_pcm_substream *substream;
106 struct stm32_sai_data *pdata;
107 struct device_node *np_sync_provider;
109 struct clk *sai_mclk;
110 dma_addr_t phys_addr;
111 unsigned int mclk_rate;
125 unsigned int spdif_frm_cnt;
126 struct snd_aes_iec958 iec958;
127 struct mutex ctrl_lock; /* protect resources accessed by controls */
128 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
131 enum stm32_sai_fifo_th {
132 STM_SAI_FIFO_TH_EMPTY,
133 STM_SAI_FIFO_TH_QUARTER,
134 STM_SAI_FIFO_TH_HALF,
135 STM_SAI_FIFO_TH_3_QUARTER,
136 STM_SAI_FIFO_TH_FULL,
139 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
142 case STM_SAI_CR1_REGX:
143 case STM_SAI_CR2_REGX:
144 case STM_SAI_FRCR_REGX:
145 case STM_SAI_SLOTR_REGX:
146 case STM_SAI_IMR_REGX:
147 case STM_SAI_SR_REGX:
148 case STM_SAI_CLRFR_REGX:
149 case STM_SAI_DR_REGX:
150 case STM_SAI_PDMCR_REGX:
151 case STM_SAI_PDMLY_REGX:
158 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
161 case STM_SAI_DR_REGX:
162 case STM_SAI_SR_REGX:
169 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
172 case STM_SAI_CR1_REGX:
173 case STM_SAI_CR2_REGX:
174 case STM_SAI_FRCR_REGX:
175 case STM_SAI_SLOTR_REGX:
176 case STM_SAI_IMR_REGX:
177 case STM_SAI_CLRFR_REGX:
178 case STM_SAI_DR_REGX:
179 case STM_SAI_PDMCR_REGX:
180 case STM_SAI_PDMLY_REGX:
187 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
191 .max_register = STM_SAI_DR_REGX,
192 .readable_reg = stm32_sai_sub_readable_reg,
193 .volatile_reg = stm32_sai_sub_volatile_reg,
194 .writeable_reg = stm32_sai_sub_writeable_reg,
196 .cache_type = REGCACHE_FLAT,
199 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
203 .max_register = STM_SAI_PDMLY_REGX,
204 .readable_reg = stm32_sai_sub_readable_reg,
205 .volatile_reg = stm32_sai_sub_volatile_reg,
206 .writeable_reg = stm32_sai_sub_writeable_reg,
208 .cache_type = REGCACHE_FLAT,
211 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_info *uinfo)
214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
220 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *uctl)
223 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
225 mutex_lock(&sai->ctrl_lock);
226 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
227 mutex_unlock(&sai->ctrl_lock);
232 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *uctl)
235 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
237 mutex_lock(&sai->ctrl_lock);
238 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
239 mutex_unlock(&sai->ctrl_lock);
244 static const struct snd_kcontrol_new iec958_ctls = {
245 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
246 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
247 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
248 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
249 .info = snd_pcm_iec958_info,
250 .get = snd_pcm_iec958_get,
251 .put = snd_pcm_iec958_put,
254 struct stm32_sai_mclk_data {
257 struct stm32_sai_sub_data *sai_data;
260 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
261 #define STM32_SAI_MAX_CLKS 1
263 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
264 unsigned long input_rate,
265 unsigned long output_rate)
267 int version = sai->pdata->conf->version;
270 div = DIV_ROUND_CLOSEST(input_rate, output_rate);
271 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
272 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
275 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
277 if (input_rate % div)
278 dev_dbg(&sai->pdev->dev,
279 "Rate not accurate. requested (%ld), actual (%ld)\n",
280 output_rate, input_rate / div);
285 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
288 int version = sai->pdata->conf->version;
291 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
292 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
296 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
297 cr1 = SAI_XCR1_MCKDIV_SET(div);
298 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
300 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
305 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
308 struct platform_device *pdev = sai->pdev;
309 struct clk *parent_clk = sai->pdata->clk_x8k;
312 if (!(rate % SAI_RATE_11K))
313 parent_clk = sai->pdata->clk_x11k;
315 ret = clk_set_parent(sai->sai_ck, parent_clk);
317 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
319 "Active stream rates conflict\n" : "\n");
324 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
325 unsigned long *prate)
327 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
328 struct stm32_sai_sub_data *sai = mclk->sai_data;
331 div = stm32_sai_get_clk_div(sai, *prate, rate);
335 mclk->freq = *prate / div;
340 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
341 unsigned long parent_rate)
343 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
348 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
349 unsigned long parent_rate)
351 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
352 struct stm32_sai_sub_data *sai = mclk->sai_data;
355 div = stm32_sai_get_clk_div(sai, parent_rate, rate);
359 ret = stm32_sai_set_clk_div(sai, div);
368 static int stm32_sai_mclk_enable(struct clk_hw *hw)
370 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
371 struct stm32_sai_sub_data *sai = mclk->sai_data;
373 dev_dbg(&sai->pdev->dev, "Enable master clock\n");
375 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
376 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
379 static void stm32_sai_mclk_disable(struct clk_hw *hw)
381 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
382 struct stm32_sai_sub_data *sai = mclk->sai_data;
384 dev_dbg(&sai->pdev->dev, "Disable master clock\n");
386 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
389 static const struct clk_ops mclk_ops = {
390 .enable = stm32_sai_mclk_enable,
391 .disable = stm32_sai_mclk_disable,
392 .recalc_rate = stm32_sai_mclk_recalc_rate,
393 .round_rate = stm32_sai_mclk_round_rate,
394 .set_rate = stm32_sai_mclk_set_rate,
397 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
400 struct stm32_sai_mclk_data *mclk;
401 struct device *dev = &sai->pdev->dev;
402 const char *pname = __clk_get_name(sai->sai_ck);
403 char *mclk_name, *p, *s = (char *)pname;
406 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
410 mclk_name = devm_kcalloc(dev, sizeof(char),
411 SAI_MCLK_NAME_LEN, GFP_KERNEL);
416 * Forge mclk clock name from parent clock name and suffix.
417 * String after "_" char is stripped in parent name.
420 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
424 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
426 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
427 mclk->sai_data = sai;
430 dev_dbg(dev, "Register master clock %s\n", mclk_name);
431 ret = devm_clk_hw_register(&sai->pdev->dev, hw);
433 dev_err(dev, "mclk register returned %d\n", ret);
436 sai->sai_mclk = hw->clk;
438 /* register mclk provider */
439 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
442 static irqreturn_t stm32_sai_isr(int irq, void *devid)
444 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
445 struct platform_device *pdev = sai->pdev;
446 unsigned int sr, imr, flags;
447 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
449 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
450 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
456 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
459 if (!sai->substream) {
460 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
464 if (flags & SAI_XIMR_OVRUDRIE) {
465 dev_err(&pdev->dev, "IRQ %s\n",
466 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
467 status = SNDRV_PCM_STATE_XRUN;
470 if (flags & SAI_XIMR_MUTEDETIE)
471 dev_dbg(&pdev->dev, "IRQ mute detected\n");
473 if (flags & SAI_XIMR_WCKCFGIE) {
474 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
475 status = SNDRV_PCM_STATE_DISCONNECTED;
478 if (flags & SAI_XIMR_CNRDYIE)
479 dev_err(&pdev->dev, "IRQ Codec not ready\n");
481 if (flags & SAI_XIMR_AFSDETIE) {
482 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
483 status = SNDRV_PCM_STATE_XRUN;
486 if (flags & SAI_XIMR_LFSDETIE) {
487 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
488 status = SNDRV_PCM_STATE_XRUN;
491 spin_lock(&sai->irq_lock);
492 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
493 snd_pcm_stop_xrun(sai->substream);
494 spin_unlock(&sai->irq_lock);
499 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
500 int clk_id, unsigned int freq, int dir)
502 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
505 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
506 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
508 (unsigned int)~SAI_XCR1_NODIV);
512 /* If master clock is used, set parent clock now */
513 ret = stm32_sai_set_parent_clock(sai, freq);
517 ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
519 dev_err(cpu_dai->dev,
521 "Active streams have incompatible rates" :
522 "Could not set mclk rate\n");
526 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
527 sai->mclk_rate = freq;
533 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
534 u32 rx_mask, int slots, int slot_width)
536 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
537 int slotr, slotr_mask, slot_size;
539 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
540 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
544 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
545 tx_mask, rx_mask, slots, slot_width);
547 switch (slot_width) {
549 slot_size = SAI_SLOT_SIZE_16;
552 slot_size = SAI_SLOT_SIZE_32;
555 slot_size = SAI_SLOT_SIZE_AUTO;
559 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
560 SAI_XSLOTR_NBSLOT_SET(slots - 1);
561 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
563 /* tx/rx mask set in machine init, if slot number defined in DT */
564 if (STM_SAI_IS_PLAYBACK(sai)) {
565 sai->slot_mask = tx_mask;
566 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
569 if (STM_SAI_IS_CAPTURE(sai)) {
570 sai->slot_mask = rx_mask;
571 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
574 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
576 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
578 sai->slot_width = slot_width;
584 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
586 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
588 int cr1_mask, frcr_mask = 0;
591 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
593 /* Do not generate master by default */
594 cr1 = SAI_XCR1_NODIV;
595 cr1_mask = SAI_XCR1_NODIV;
597 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
598 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
599 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
603 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
606 /* SCK active high for all protocols */
607 case SND_SOC_DAIFMT_I2S:
608 cr1 |= SAI_XCR1_CKSTR;
609 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
612 case SND_SOC_DAIFMT_MSB:
613 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
615 /* Right justified */
616 case SND_SOC_DAIFMT_LSB:
617 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
619 case SND_SOC_DAIFMT_DSP_A:
620 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
622 case SND_SOC_DAIFMT_DSP_B:
623 frcr |= SAI_XFRCR_FSPOL;
626 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
627 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
631 cr1_mask |= SAI_XCR1_CKSTR;
632 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
635 /* DAI clock strobing. Invert setting previously set */
636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
637 case SND_SOC_DAIFMT_NB_NF:
639 case SND_SOC_DAIFMT_IB_NF:
640 cr1 ^= SAI_XCR1_CKSTR;
642 case SND_SOC_DAIFMT_NB_IF:
643 frcr ^= SAI_XFRCR_FSPOL;
645 case SND_SOC_DAIFMT_IB_IF:
646 /* Invert fs & sck */
647 cr1 ^= SAI_XCR1_CKSTR;
648 frcr ^= SAI_XFRCR_FSPOL;
651 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
652 fmt & SND_SOC_DAIFMT_INV_MASK);
655 cr1_mask |= SAI_XCR1_CKSTR;
656 frcr_mask |= SAI_XFRCR_FSPOL;
658 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
660 /* DAI clock master masks */
661 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
662 case SND_SOC_DAIFMT_CBM_CFM:
663 /* codec is master */
664 cr1 |= SAI_XCR1_SLAVE;
667 case SND_SOC_DAIFMT_CBS_CFS:
671 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
672 fmt & SND_SOC_DAIFMT_MASTER_MASK);
676 /* Set slave mode if sub-block is synchronized with another SAI */
678 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
679 cr1 |= SAI_XCR1_SLAVE;
683 cr1_mask |= SAI_XCR1_SLAVE;
686 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
688 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
697 static int stm32_sai_startup(struct snd_pcm_substream *substream,
698 struct snd_soc_dai *cpu_dai)
700 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
704 spin_lock_irqsave(&sai->irq_lock, flags);
705 sai->substream = substream;
706 spin_unlock_irqrestore(&sai->irq_lock, flags);
708 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
709 snd_pcm_hw_constraint_mask64(substream->runtime,
710 SNDRV_PCM_HW_PARAM_FORMAT,
711 SNDRV_PCM_FMTBIT_S32_LE);
712 snd_pcm_hw_constraint_single(substream->runtime,
713 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
716 ret = clk_prepare_enable(sai->sai_ck);
718 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
723 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX,
724 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
726 imr = SAI_XIMR_OVRUDRIE;
727 if (STM_SAI_IS_CAPTURE(sai)) {
728 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
729 if (cr2 & SAI_XCR2_MUTECNT_MASK)
730 imr |= SAI_XIMR_MUTEDETIE;
734 imr |= SAI_XIMR_WCKCFGIE;
736 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
738 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
744 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
745 struct snd_pcm_substream *substream,
746 struct snd_pcm_hw_params *params)
748 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
749 int cr1, cr1_mask, ret;
752 * DMA bursts increment is set to 4 words.
753 * SAI fifo threshold is set to half fifo, to keep enough space
754 * for DMA incoming bursts.
756 regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX,
757 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
759 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
761 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
762 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
763 sai->spdif_frm_cnt = 0;
767 /* Mode, data format and channel config */
768 cr1_mask = SAI_XCR1_DS_MASK;
769 switch (params_format(params)) {
770 case SNDRV_PCM_FORMAT_S8:
771 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
773 case SNDRV_PCM_FORMAT_S16_LE:
774 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
776 case SNDRV_PCM_FORMAT_S32_LE:
777 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
780 dev_err(cpu_dai->dev, "Data format not supported");
784 cr1_mask |= SAI_XCR1_MONO;
785 if ((sai->slots == 2) && (params_channels(params) == 1))
786 cr1 |= SAI_XCR1_MONO;
788 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
790 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
797 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
799 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
802 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
805 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
806 * By default slot width = data size, if not forced from DT
808 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
809 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
810 sai->slot_width = sai->data_size;
812 if (sai->slot_width < sai->data_size) {
813 dev_err(cpu_dai->dev,
814 "Data size %d larger than slot width\n",
819 /* Slot number is set to 2, if not specified in DT */
823 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
824 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
825 SAI_XSLOTR_NBSLOT_MASK,
826 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
828 /* Set default slots mask if not already set from DT */
829 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
830 sai->slot_mask = (1 << sai->slots) - 1;
831 regmap_update_bits(sai->regmap,
832 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
833 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
836 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
837 sai->slots, sai->slot_width);
842 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
844 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
845 int fs_active, offset, format;
848 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
849 sai->fs_length = sai->slot_width * sai->slots;
851 fs_active = sai->fs_length / 2;
852 if ((format == SND_SOC_DAIFMT_DSP_A) ||
853 (format == SND_SOC_DAIFMT_DSP_B))
856 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
857 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
858 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
860 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
861 sai->fs_length, fs_active);
863 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
865 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
866 offset = sai->slot_width - sai->data_size;
868 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
869 SAI_XSLOTR_FBOFF_MASK,
870 SAI_XSLOTR_FBOFF_SET(offset));
874 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
876 unsigned char *cs = sai->iec958.status;
878 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
879 cs[1] = IEC958_AES1_CON_GENERAL;
880 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
881 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
884 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
885 struct snd_pcm_runtime *runtime)
890 /* Force the sample rate according to runtime rate */
891 mutex_lock(&sai->ctrl_lock);
892 switch (runtime->rate) {
894 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
897 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
900 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
903 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
906 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
909 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
912 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
915 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
918 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
921 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
924 mutex_unlock(&sai->ctrl_lock);
927 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
928 struct snd_pcm_hw_params *params)
930 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
931 int div = 0, cr1 = 0;
932 int sai_clk_rate, mclk_ratio, den;
933 unsigned int rate = params_rate(params);
936 if (!sai->sai_mclk) {
937 ret = stm32_sai_set_parent_clock(sai, rate);
941 sai_clk_rate = clk_get_rate(sai->sai_ck);
943 if (STM_SAI_IS_F4(sai->pdata)) {
945 * mclk_rate = 256 * fs
946 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
947 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
949 * MCKDIV ignored. sck = sai_ck
954 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
955 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
964 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
965 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
967 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
968 * Note: NOMCK/NODIV correspond to same bit.
970 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
971 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
976 if (sai->mclk_rate) {
977 mclk_ratio = sai->mclk_rate / rate;
978 if (mclk_ratio == 512) {
980 } else if (mclk_ratio != 256) {
981 dev_err(cpu_dai->dev,
982 "Wrong mclk ratio %d\n",
987 regmap_update_bits(sai->regmap,
991 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
996 /* mclk-fs not set, master clock not active */
997 den = sai->fs_length * params_rate(params);
998 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1006 return stm32_sai_set_clk_div(sai, div);
1009 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1010 struct snd_pcm_hw_params *params,
1011 struct snd_soc_dai *cpu_dai)
1013 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1016 sai->data_size = params_width(params);
1018 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1019 /* Rate not already set in runtime structure */
1020 substream->runtime->rate = params_rate(params);
1021 stm32_sai_set_iec958_status(sai, substream->runtime);
1023 ret = stm32_sai_set_slots(cpu_dai);
1026 stm32_sai_set_frame(cpu_dai);
1029 ret = stm32_sai_set_config(cpu_dai, substream, params);
1034 ret = stm32_sai_configure_clock(cpu_dai, params);
1039 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1040 struct snd_soc_dai *cpu_dai)
1042 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1046 case SNDRV_PCM_TRIGGER_START:
1047 case SNDRV_PCM_TRIGGER_RESUME:
1048 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1049 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1051 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1052 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1055 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1056 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1058 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1060 case SNDRV_PCM_TRIGGER_SUSPEND:
1061 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1062 case SNDRV_PCM_TRIGGER_STOP:
1063 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1065 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
1068 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1070 (unsigned int)~SAI_XCR1_SAIEN);
1072 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1074 (unsigned int)~SAI_XCR1_DMAEN);
1076 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1078 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1079 sai->spdif_frm_cnt = 0;
1088 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1089 struct snd_soc_dai *cpu_dai)
1091 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1092 unsigned long flags;
1094 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1096 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
1099 /* Release mclk rate only if rate was actually set */
1100 if (sai->mclk_rate) {
1101 clk_rate_exclusive_put(sai->sai_mclk);
1105 clk_disable_unprepare(sai->sai_ck);
1107 spin_lock_irqsave(&sai->irq_lock, flags);
1108 sai->substream = NULL;
1109 spin_unlock_irqrestore(&sai->irq_lock, flags);
1112 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1113 struct snd_soc_dai *cpu_dai)
1115 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1116 struct snd_kcontrol_new knew = iec958_ctls;
1118 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1119 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1120 knew.device = rtd->pcm->device;
1121 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1127 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1129 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1130 int cr1 = 0, cr1_mask, ret;
1132 sai->cpu_dai = cpu_dai;
1134 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1136 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1137 * as it allows bytes, half-word and words transfers. (See DMA fifos
1140 sai->dma_params.maxburst = 4;
1141 /* Buswidth will be set by framework at runtime */
1142 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1144 if (STM_SAI_IS_PLAYBACK(sai))
1145 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1147 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1149 /* Next settings are not relevant for spdif mode */
1150 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1153 cr1_mask = SAI_XCR1_RX_TX;
1154 if (STM_SAI_IS_CAPTURE(sai))
1155 cr1 |= SAI_XCR1_RX_TX;
1157 /* Configure synchronization */
1158 if (sai->sync == SAI_SYNC_EXTERNAL) {
1159 /* Configure synchro client and provider */
1160 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1161 sai->synco, sai->synci);
1166 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1167 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1169 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
1172 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1173 .set_sysclk = stm32_sai_set_sysclk,
1174 .set_fmt = stm32_sai_set_dai_fmt,
1175 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1176 .startup = stm32_sai_startup,
1177 .hw_params = stm32_sai_hw_params,
1178 .trigger = stm32_sai_trigger,
1179 .shutdown = stm32_sai_shutdown,
1182 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1183 int channel, unsigned long hwoff,
1184 void *buf, unsigned long bytes)
1186 struct snd_pcm_runtime *runtime = substream->runtime;
1187 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1188 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
1189 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1190 int *ptr = (int *)(runtime->dma_area + hwoff +
1191 channel * (runtime->dma_bytes / runtime->channels));
1192 ssize_t cnt = bytes_to_samples(runtime, bytes);
1193 unsigned int frm_cnt = sai->spdif_frm_cnt;
1198 *ptr = ((*ptr >> 8) & 0x00ffffff);
1200 /* Set channel status bit */
1201 byte = frm_cnt >> 3;
1202 mask = 1 << (frm_cnt - (byte << 3));
1203 if (sai->iec958.status[byte] & mask)
1210 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1213 sai->spdif_frm_cnt = frm_cnt;
1218 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1219 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1220 .buffer_bytes_max = 8 * PAGE_SIZE,
1221 .period_bytes_min = 1024, /* 5ms at 48kHz */
1222 .period_bytes_max = PAGE_SIZE,
1227 static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1228 .probe = stm32_sai_dai_probe,
1229 .pcm_new = stm32_sai_pcm_new,
1230 .id = 1, /* avoid call to fmt_single_name() */
1236 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1237 /* DMA does not support 24 bits transfers */
1239 SNDRV_PCM_FMTBIT_S8 |
1240 SNDRV_PCM_FMTBIT_S16_LE |
1241 SNDRV_PCM_FMTBIT_S32_LE,
1243 .ops = &stm32_sai_pcm_dai_ops,
1246 static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1247 .probe = stm32_sai_dai_probe,
1248 .id = 1, /* avoid call to fmt_single_name() */
1254 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1255 /* DMA does not support 24 bits transfers */
1257 SNDRV_PCM_FMTBIT_S8 |
1258 SNDRV_PCM_FMTBIT_S16_LE |
1259 SNDRV_PCM_FMTBIT_S32_LE,
1261 .ops = &stm32_sai_pcm_dai_ops,
1264 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1265 .pcm_hardware = &stm32_sai_pcm_hw,
1266 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1269 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1270 .pcm_hardware = &stm32_sai_pcm_hw,
1271 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1272 .process = stm32_sai_pcm_process_spdif,
1275 static const struct snd_soc_component_driver stm32_component = {
1276 .name = "stm32-sai",
1279 static const struct of_device_id stm32_sai_sub_ids[] = {
1280 { .compatible = "st,stm32-sai-sub-a",
1281 .data = (void *)STM_SAI_A_ID},
1282 { .compatible = "st,stm32-sai-sub-b",
1283 .data = (void *)STM_SAI_B_ID},
1286 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1288 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1289 struct stm32_sai_sub_data *sai)
1291 struct device_node *np = pdev->dev.of_node;
1292 struct resource *res;
1294 struct of_phandle_args args;
1300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301 base = devm_ioremap_resource(&pdev->dev, res);
1303 return PTR_ERR(base);
1305 sai->phys_addr = res->start;
1307 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1308 /* Note: PDM registers not available for H7 sub-block B */
1309 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
1310 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1312 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1313 base, sai->regmap_config);
1314 if (IS_ERR(sai->regmap)) {
1315 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1316 return PTR_ERR(sai->regmap);
1319 /* Get direction property */
1320 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1321 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1322 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1323 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1325 dev_err(&pdev->dev, "Unsupported direction\n");
1329 /* Get spdif iec60958 property */
1331 if (of_get_property(np, "st,iec60958", NULL)) {
1332 if (!STM_SAI_HAS_SPDIF(sai) ||
1333 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1334 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1337 stm32_sai_init_iec958_status(sai);
1342 /* Get synchronization property */
1344 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1345 if (ret < 0 && ret != -ENOENT) {
1346 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1350 sai->sync = SAI_SYNC_NONE;
1352 if (args.np == np) {
1353 dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1354 of_node_put(args.np);
1358 sai->np_sync_provider = of_get_parent(args.np);
1359 if (!sai->np_sync_provider) {
1360 dev_err(&pdev->dev, "%pOFn parent node not found\n",
1362 of_node_put(args.np);
1366 sai->sync = SAI_SYNC_INTERNAL;
1367 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1368 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1370 "External synchro not supported\n");
1371 of_node_put(args.np);
1374 sai->sync = SAI_SYNC_EXTERNAL;
1376 sai->synci = args.args[0];
1377 if (sai->synci < 1 ||
1378 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1379 dev_err(&pdev->dev, "Wrong SAI index\n");
1380 of_node_put(args.np);
1384 if (of_property_match_string(args.np, "compatible",
1385 "st,stm32-sai-sub-a") >= 0)
1386 sai->synco = STM_SAI_SYNC_OUT_A;
1388 if (of_property_match_string(args.np, "compatible",
1389 "st,stm32-sai-sub-b") >= 0)
1390 sai->synco = STM_SAI_SYNC_OUT_B;
1393 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1394 of_node_put(args.np);
1399 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1400 pdev->name, args.np->full_name);
1403 of_node_put(args.np);
1404 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1405 if (IS_ERR(sai->sai_ck)) {
1406 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1407 return PTR_ERR(sai->sai_ck);
1410 if (STM_SAI_IS_F4(sai->pdata))
1413 /* Register mclk provider if requested */
1414 if (of_find_property(np, "#clock-cells", NULL)) {
1415 ret = stm32_sai_add_mclk_provider(sai);
1419 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
1420 if (IS_ERR(sai->sai_mclk)) {
1421 if (PTR_ERR(sai->sai_mclk) != -ENOENT)
1422 return PTR_ERR(sai->sai_mclk);
1423 sai->sai_mclk = NULL;
1430 static int stm32_sai_sub_probe(struct platform_device *pdev)
1432 struct stm32_sai_sub_data *sai;
1433 const struct of_device_id *of_id;
1434 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1437 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1441 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1444 sai->id = (uintptr_t)of_id->data;
1447 mutex_init(&sai->ctrl_lock);
1448 spin_lock_init(&sai->irq_lock);
1449 platform_set_drvdata(pdev, sai);
1451 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1453 dev_err(&pdev->dev, "Parent device data not available\n");
1457 ret = stm32_sai_sub_parse_of(pdev, sai);
1461 if (STM_SAI_IS_PLAYBACK(sai))
1462 sai->cpu_dai_drv = stm32_sai_playback_dai;
1464 sai->cpu_dai_drv = stm32_sai_capture_dai;
1465 sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1467 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1468 IRQF_SHARED, dev_name(&pdev->dev), sai);
1470 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1474 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1475 &sai->cpu_dai_drv, 1);
1479 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1480 conf = &stm32_sai_pcm_config_spdif;
1482 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1484 dev_err(&pdev->dev, "Could not register pcm dma\n");
1491 #ifdef CONFIG_PM_SLEEP
1492 static int stm32_sai_sub_suspend(struct device *dev)
1494 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1496 regcache_cache_only(sai->regmap, true);
1497 regcache_mark_dirty(sai->regmap);
1501 static int stm32_sai_sub_resume(struct device *dev)
1503 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1505 regcache_cache_only(sai->regmap, false);
1506 return regcache_sync(sai->regmap);
1508 #endif /* CONFIG_PM_SLEEP */
1510 static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1511 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1514 static struct platform_driver stm32_sai_sub_driver = {
1516 .name = "st,stm32-sai-sub",
1517 .of_match_table = stm32_sai_sub_ids,
1518 .pm = &stm32_sai_sub_pm_ops,
1520 .probe = stm32_sai_sub_probe,
1523 module_platform_driver(stm32_sai_sub_driver);
1525 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1526 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1527 MODULE_ALIAS("platform:st,stm32-sai-sub");
1528 MODULE_LICENSE("GPL v2");