2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/workqueue.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
34 #define RT5663_DEVICE_ID_2 0x6451
35 #define RT5663_DEVICE_ID_1 0x6406
37 #define RT5663_POWER_ON_DELAY_MS 300
38 #define RT5663_SUPPLY_CURRENT_UA 500000
45 struct impedance_mapping_table {
49 unsigned int dc_offset_l_manual;
50 unsigned int dc_offset_r_manual;
51 unsigned int dc_offset_l_manual_mic;
52 unsigned int dc_offset_r_manual_mic;
55 static const char *const rt5663_supply_names[] = {
61 struct snd_soc_component *component;
62 struct rt5663_platform_data pdata;
63 struct regmap *regmap;
64 struct delayed_work jack_detect_work, jd_unplug_work;
65 struct snd_soc_jack *hs_jack;
66 struct timer_list btn_check_timer;
67 struct impedance_mapping_table *imp_table;
68 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
82 static const struct reg_sequence rt5663_patch_list[] = {
90 static const struct reg_default rt5663_v2_reg[] = {
492 static const struct reg_default rt5663_reg[] = {
750 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
754 case RT5663_SIL_DET_CTL:
755 case RT5663_HP_IMP_GAIN_2:
756 case RT5663_AD_DA_MIXER:
757 case RT5663_FRAC_DIV_2:
758 case RT5663_MICBIAS_1:
759 case RT5663_ASRC_11_2:
760 case RT5663_ADC_EQ_1:
761 case RT5663_INT_ST_1:
762 case RT5663_INT_ST_2:
763 case RT5663_GPIO_STA1:
764 case RT5663_SIN_GEN_1:
765 case RT5663_IL_CMD_1:
766 case RT5663_IL_CMD_5:
767 case RT5663_IL_CMD_PWRSAV1:
768 case RT5663_EM_JACK_TYPE_1:
769 case RT5663_EM_JACK_TYPE_2:
770 case RT5663_EM_JACK_TYPE_3:
771 case RT5663_JD_CTRL2:
772 case RT5663_VENDOR_ID:
773 case RT5663_VENDOR_ID_1:
774 case RT5663_VENDOR_ID_2:
775 case RT5663_PLL_INT_REG:
776 case RT5663_SOFT_RAMP:
777 case RT5663_STO_DRE_1:
778 case RT5663_STO_DRE_5:
779 case RT5663_STO_DRE_6:
780 case RT5663_STO_DRE_7:
781 case RT5663_MIC_DECRO_1:
782 case RT5663_MIC_DECRO_4:
783 case RT5663_HP_IMP_SEN_1:
784 case RT5663_HP_IMP_SEN_3:
785 case RT5663_HP_IMP_SEN_4:
786 case RT5663_HP_IMP_SEN_5:
787 case RT5663_HP_CALIB_1_1:
788 case RT5663_HP_CALIB_9:
789 case RT5663_HP_CALIB_ST1:
790 case RT5663_HP_CALIB_ST2:
791 case RT5663_HP_CALIB_ST3:
792 case RT5663_HP_CALIB_ST4:
793 case RT5663_HP_CALIB_ST5:
794 case RT5663_HP_CALIB_ST6:
795 case RT5663_HP_CALIB_ST7:
796 case RT5663_HP_CALIB_ST8:
797 case RT5663_HP_CALIB_ST9:
805 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
809 case RT5663_HP_OUT_EN:
810 case RT5663_HP_LCH_DRE:
811 case RT5663_HP_RCH_DRE:
812 case RT5663_CALIB_BST:
814 case RT5663_SIL_DET_CTL:
815 case RT5663_PWR_SAV_SILDET:
816 case RT5663_SIDETONE_CTL:
817 case RT5663_STO1_DAC_DIG_VOL:
818 case RT5663_STO1_ADC_DIG_VOL:
819 case RT5663_STO1_BOOST:
820 case RT5663_HP_IMP_GAIN_1:
821 case RT5663_HP_IMP_GAIN_2:
822 case RT5663_STO1_ADC_MIXER:
823 case RT5663_AD_DA_MIXER:
824 case RT5663_STO_DAC_MIXER:
825 case RT5663_DIG_SIDE_MIXER:
826 case RT5663_BYPASS_STO_DAC:
827 case RT5663_CALIB_REC_MIX:
828 case RT5663_PWR_DIG_1:
829 case RT5663_PWR_DIG_2:
830 case RT5663_PWR_ANLG_1:
831 case RT5663_PWR_ANLG_2:
832 case RT5663_PWR_ANLG_3:
833 case RT5663_PWR_MIXER:
834 case RT5663_SIG_CLK_DET:
835 case RT5663_PRE_DIV_GATING_1:
836 case RT5663_PRE_DIV_GATING_2:
837 case RT5663_I2S1_SDP:
838 case RT5663_ADDA_CLK_1:
839 case RT5663_ADDA_RST:
840 case RT5663_FRAC_DIV_1:
841 case RT5663_FRAC_DIV_2:
853 case RT5663_DUMMY_REG:
860 case RT5663_HP_CHARGE_PUMP_1:
861 case RT5663_HP_CHARGE_PUMP_2:
862 case RT5663_MICBIAS_1:
864 case RT5663_ASRC_11_2:
865 case RT5663_DUMMY_REG_2:
866 case RT5663_REC_PATH_GAIN:
867 case RT5663_AUTO_1MRC_CLK:
868 case RT5663_ADC_EQ_1:
869 case RT5663_ADC_EQ_2:
875 case RT5663_INT_ST_1:
876 case RT5663_INT_ST_2:
879 case RT5663_GPIO_STA1:
880 case RT5663_SIN_GEN_1:
881 case RT5663_SIN_GEN_2:
882 case RT5663_SIN_GEN_3:
883 case RT5663_SOF_VOL_ZC1:
884 case RT5663_IL_CMD_1:
885 case RT5663_IL_CMD_2:
886 case RT5663_IL_CMD_3:
887 case RT5663_IL_CMD_4:
888 case RT5663_IL_CMD_5:
889 case RT5663_IL_CMD_6:
890 case RT5663_IL_CMD_7:
891 case RT5663_IL_CMD_8:
892 case RT5663_IL_CMD_PWRSAV1:
893 case RT5663_IL_CMD_PWRSAV2:
894 case RT5663_EM_JACK_TYPE_1:
895 case RT5663_EM_JACK_TYPE_2:
896 case RT5663_EM_JACK_TYPE_3:
897 case RT5663_EM_JACK_TYPE_4:
898 case RT5663_EM_JACK_TYPE_5:
899 case RT5663_EM_JACK_TYPE_6:
900 case RT5663_STO1_HPF_ADJ1:
901 case RT5663_STO1_HPF_ADJ2:
902 case RT5663_FAST_OFF_MICBIAS:
903 case RT5663_JD_CTRL1:
904 case RT5663_JD_CTRL2:
905 case RT5663_DIG_MISC:
906 case RT5663_VENDOR_ID:
907 case RT5663_VENDOR_ID_1:
908 case RT5663_VENDOR_ID_2:
909 case RT5663_DIG_VOL_ZCD:
910 case RT5663_ANA_BIAS_CUR_1:
911 case RT5663_ANA_BIAS_CUR_2:
912 case RT5663_ANA_BIAS_CUR_3:
913 case RT5663_ANA_BIAS_CUR_4:
914 case RT5663_ANA_BIAS_CUR_5:
915 case RT5663_ANA_BIAS_CUR_6:
916 case RT5663_BIAS_CUR_5:
917 case RT5663_BIAS_CUR_6:
918 case RT5663_BIAS_CUR_7:
919 case RT5663_BIAS_CUR_8:
920 case RT5663_DACREF_LDO:
921 case RT5663_DUMMY_REG_3:
922 case RT5663_BIAS_CUR_9:
923 case RT5663_DUMMY_REG_4:
924 case RT5663_VREFADJ_OP:
925 case RT5663_VREF_RECMIX:
926 case RT5663_CHARGE_PUMP_1:
927 case RT5663_CHARGE_PUMP_1_2:
928 case RT5663_CHARGE_PUMP_1_3:
929 case RT5663_CHARGE_PUMP_2:
930 case RT5663_DIG_IN_PIN1:
931 case RT5663_PAD_DRV_CTL:
932 case RT5663_PLL_INT_REG:
933 case RT5663_CHOP_DAC_L:
934 case RT5663_CHOP_ADC:
935 case RT5663_CALIB_ADC:
936 case RT5663_CHOP_DAC_R:
937 case RT5663_DUMMY_CTL_DACLR:
938 case RT5663_DUMMY_REG_5:
939 case RT5663_SOFT_RAMP:
940 case RT5663_TEST_MODE_1:
941 case RT5663_TEST_MODE_2:
942 case RT5663_TEST_MODE_3:
943 case RT5663_STO_DRE_1:
944 case RT5663_STO_DRE_2:
945 case RT5663_STO_DRE_3:
946 case RT5663_STO_DRE_4:
947 case RT5663_STO_DRE_5:
948 case RT5663_STO_DRE_6:
949 case RT5663_STO_DRE_7:
950 case RT5663_STO_DRE_8:
951 case RT5663_STO_DRE_9:
952 case RT5663_STO_DRE_10:
953 case RT5663_MIC_DECRO_1:
954 case RT5663_MIC_DECRO_2:
955 case RT5663_MIC_DECRO_3:
956 case RT5663_MIC_DECRO_4:
957 case RT5663_MIC_DECRO_5:
958 case RT5663_MIC_DECRO_6:
959 case RT5663_HP_DECRO_1:
960 case RT5663_HP_DECRO_2:
961 case RT5663_HP_DECRO_3:
962 case RT5663_HP_DECRO_4:
963 case RT5663_HP_DECOUP:
964 case RT5663_HP_IMP_SEN_MAP8:
965 case RT5663_HP_IMP_SEN_MAP9:
966 case RT5663_HP_IMP_SEN_MAP10:
967 case RT5663_HP_IMP_SEN_MAP11:
968 case RT5663_HP_IMP_SEN_1:
969 case RT5663_HP_IMP_SEN_2:
970 case RT5663_HP_IMP_SEN_3:
971 case RT5663_HP_IMP_SEN_4:
972 case RT5663_HP_IMP_SEN_5:
973 case RT5663_HP_IMP_SEN_6:
974 case RT5663_HP_IMP_SEN_7:
975 case RT5663_HP_IMP_SEN_8:
976 case RT5663_HP_IMP_SEN_9:
977 case RT5663_HP_IMP_SEN_10:
978 case RT5663_HP_IMP_SEN_11:
979 case RT5663_HP_IMP_SEN_12:
980 case RT5663_HP_IMP_SEN_13:
981 case RT5663_HP_IMP_SEN_14:
982 case RT5663_HP_IMP_SEN_15:
983 case RT5663_HP_IMP_SEN_16:
984 case RT5663_HP_IMP_SEN_17:
985 case RT5663_HP_IMP_SEN_18:
986 case RT5663_HP_IMP_SEN_19:
987 case RT5663_HP_IMPSEN_DIG5:
988 case RT5663_HP_IMPSEN_MAP1:
989 case RT5663_HP_IMPSEN_MAP2:
990 case RT5663_HP_IMPSEN_MAP3:
991 case RT5663_HP_IMPSEN_MAP4:
992 case RT5663_HP_IMPSEN_MAP5:
993 case RT5663_HP_IMPSEN_MAP7:
994 case RT5663_HP_LOGIC_1:
995 case RT5663_HP_LOGIC_2:
996 case RT5663_HP_CALIB_1:
997 case RT5663_HP_CALIB_1_1:
998 case RT5663_HP_CALIB_2:
999 case RT5663_HP_CALIB_3:
1000 case RT5663_HP_CALIB_4:
1001 case RT5663_HP_CALIB_5:
1002 case RT5663_HP_CALIB_5_1:
1003 case RT5663_HP_CALIB_6:
1004 case RT5663_HP_CALIB_7:
1005 case RT5663_HP_CALIB_9:
1006 case RT5663_HP_CALIB_10:
1007 case RT5663_HP_CALIB_11:
1008 case RT5663_HP_CALIB_ST1:
1009 case RT5663_HP_CALIB_ST2:
1010 case RT5663_HP_CALIB_ST3:
1011 case RT5663_HP_CALIB_ST4:
1012 case RT5663_HP_CALIB_ST5:
1013 case RT5663_HP_CALIB_ST6:
1014 case RT5663_HP_CALIB_ST7:
1015 case RT5663_HP_CALIB_ST8:
1016 case RT5663_HP_CALIB_ST9:
1017 case RT5663_HP_AMP_DET:
1018 case RT5663_DUMMY_REG_6:
1019 case RT5663_HP_BIAS:
1023 case RT5663_DUMMY_1:
1024 case RT5663_DUMMY_2:
1025 case RT5663_DUMMY_3:
1027 case RT5663_ADC_LCH_LPF1_A1:
1028 case RT5663_ADC_RCH_LPF1_A1:
1029 case RT5663_ADC_LCH_LPF1_H0:
1030 case RT5663_ADC_RCH_LPF1_H0:
1031 case RT5663_ADC_LCH_BPF1_A1:
1032 case RT5663_ADC_RCH_BPF1_A1:
1033 case RT5663_ADC_LCH_BPF1_A2:
1034 case RT5663_ADC_RCH_BPF1_A2:
1035 case RT5663_ADC_LCH_BPF1_H0:
1036 case RT5663_ADC_RCH_BPF1_H0:
1037 case RT5663_ADC_LCH_BPF2_A1:
1038 case RT5663_ADC_RCH_BPF2_A1:
1039 case RT5663_ADC_LCH_BPF2_A2:
1040 case RT5663_ADC_RCH_BPF2_A2:
1041 case RT5663_ADC_LCH_BPF2_H0:
1042 case RT5663_ADC_RCH_BPF2_H0:
1043 case RT5663_ADC_LCH_BPF3_A1:
1044 case RT5663_ADC_RCH_BPF3_A1:
1045 case RT5663_ADC_LCH_BPF3_A2:
1046 case RT5663_ADC_RCH_BPF3_A2:
1047 case RT5663_ADC_LCH_BPF3_H0:
1048 case RT5663_ADC_RCH_BPF3_H0:
1049 case RT5663_ADC_LCH_BPF4_A1:
1050 case RT5663_ADC_RCH_BPF4_A1:
1051 case RT5663_ADC_LCH_BPF4_A2:
1052 case RT5663_ADC_RCH_BPF4_A2:
1053 case RT5663_ADC_LCH_BPF4_H0:
1054 case RT5663_ADC_RCH_BPF4_H0:
1055 case RT5663_ADC_LCH_HPF1_A1:
1056 case RT5663_ADC_RCH_HPF1_A1:
1057 case RT5663_ADC_LCH_HPF1_H0:
1058 case RT5663_ADC_RCH_HPF1_H0:
1059 case RT5663_ADC_EQ_PRE_VOL_L:
1060 case RT5663_ADC_EQ_PRE_VOL_R:
1061 case RT5663_ADC_EQ_POST_VOL_L:
1062 case RT5663_ADC_EQ_POST_VOL_R:
1069 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1073 case RT5663_CBJ_TYPE_2:
1074 case RT5663_PDM_OUT_CTL:
1075 case RT5663_PDM_I2C_DATA_CTL1:
1076 case RT5663_PDM_I2C_DATA_CTL4:
1077 case RT5663_ALC_BK_GAIN:
1079 case RT5663_MICBIAS_1:
1080 case RT5663_ADC_EQ_1:
1081 case RT5663_INT_ST_1:
1082 case RT5663_GPIO_STA2:
1083 case RT5663_IL_CMD_1:
1084 case RT5663_IL_CMD_5:
1085 case RT5663_A_JD_CTRL:
1086 case RT5663_JD_CTRL2:
1087 case RT5663_VENDOR_ID:
1088 case RT5663_VENDOR_ID_1:
1089 case RT5663_VENDOR_ID_2:
1090 case RT5663_STO_DRE_1:
1091 case RT5663_STO_DRE_5:
1092 case RT5663_STO_DRE_6:
1093 case RT5663_STO_DRE_7:
1094 case RT5663_MONO_DYNA_6:
1095 case RT5663_STO1_SIL_DET:
1096 case RT5663_MONOL_SIL_DET:
1097 case RT5663_MONOR_SIL_DET:
1098 case RT5663_STO2_DAC_SIL:
1099 case RT5663_MONO_AMP_CAL_ST1:
1100 case RT5663_MONO_AMP_CAL_ST2:
1101 case RT5663_MONO_AMP_CAL_ST3:
1102 case RT5663_MONO_AMP_CAL_ST4:
1103 case RT5663_HP_IMP_SEN_2:
1104 case RT5663_HP_IMP_SEN_3:
1105 case RT5663_HP_IMP_SEN_4:
1106 case RT5663_HP_IMP_SEN_10:
1107 case RT5663_HP_CALIB_1:
1108 case RT5663_HP_CALIB_10:
1109 case RT5663_HP_CALIB_ST1:
1110 case RT5663_HP_CALIB_ST4:
1111 case RT5663_HP_CALIB_ST5:
1112 case RT5663_HP_CALIB_ST6:
1113 case RT5663_HP_CALIB_ST7:
1114 case RT5663_HP_CALIB_ST8:
1115 case RT5663_HP_CALIB_ST9:
1116 case RT5663_HP_CALIB_ST10:
1117 case RT5663_HP_CALIB_ST11:
1124 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1127 case RT5663_LOUT_CTRL:
1128 case RT5663_HP_AMP_2:
1129 case RT5663_MONO_OUT:
1130 case RT5663_MONO_GAIN:
1131 case RT5663_AEC_BST:
1132 case RT5663_IN1_IN2:
1133 case RT5663_IN3_IN4:
1134 case RT5663_INL1_INR1:
1135 case RT5663_CBJ_TYPE_2:
1136 case RT5663_CBJ_TYPE_3:
1137 case RT5663_CBJ_TYPE_4:
1138 case RT5663_CBJ_TYPE_5:
1139 case RT5663_CBJ_TYPE_8:
1140 case RT5663_DAC3_DIG_VOL:
1141 case RT5663_DAC3_CTRL:
1142 case RT5663_MONO_ADC_DIG_VOL:
1143 case RT5663_STO2_ADC_DIG_VOL:
1144 case RT5663_MONO_ADC_BST_GAIN:
1145 case RT5663_STO2_ADC_BST_GAIN:
1146 case RT5663_SIDETONE_CTRL:
1147 case RT5663_MONO1_ADC_MIXER:
1148 case RT5663_STO2_ADC_MIXER:
1149 case RT5663_MONO_DAC_MIXER:
1150 case RT5663_DAC2_SRC_CTRL:
1151 case RT5663_IF_3_4_DATA_CTL:
1152 case RT5663_IF_5_DATA_CTL:
1153 case RT5663_PDM_OUT_CTL:
1154 case RT5663_PDM_I2C_DATA_CTL1:
1155 case RT5663_PDM_I2C_DATA_CTL2:
1156 case RT5663_PDM_I2C_DATA_CTL3:
1157 case RT5663_PDM_I2C_DATA_CTL4:
1158 case RT5663_RECMIX1_NEW:
1159 case RT5663_RECMIX1L_0:
1160 case RT5663_RECMIX1L:
1161 case RT5663_RECMIX1R_0:
1162 case RT5663_RECMIX1R:
1163 case RT5663_RECMIX2_NEW:
1164 case RT5663_RECMIX2_L_2:
1165 case RT5663_RECMIX2_R:
1166 case RT5663_RECMIX2_R_2:
1167 case RT5663_CALIB_REC_LR:
1168 case RT5663_ALC_BK_GAIN:
1169 case RT5663_MONOMIX_GAIN:
1170 case RT5663_MONOMIX_IN_GAIN:
1171 case RT5663_OUT_MIXL_GAIN:
1172 case RT5663_OUT_LMIX_IN_GAIN:
1173 case RT5663_OUT_RMIX_IN_GAIN:
1174 case RT5663_OUT_RMIX_IN_GAIN1:
1175 case RT5663_LOUT_MIXER_CTRL:
1176 case RT5663_PWR_VOL:
1177 case RT5663_ADCDAC_RST:
1178 case RT5663_I2S34_SDP:
1179 case RT5663_I2S5_SDP:
1187 case RT5663_PLL_TRK_13:
1188 case RT5663_I2S_M_CLK_CTL:
1189 case RT5663_FDIV_I2S34_M_CLK:
1190 case RT5663_FDIV_I2S34_M_CLK2:
1191 case RT5663_FDIV_I2S5_M_CLK:
1192 case RT5663_FDIV_I2S5_M_CLK2:
1193 case RT5663_V2_IRQ_4:
1196 case RT5663_GPIO_STA2:
1197 case RT5663_HP_AMP_DET1:
1198 case RT5663_HP_AMP_DET2:
1199 case RT5663_HP_AMP_DET3:
1200 case RT5663_MID_BD_HP_AMP:
1201 case RT5663_LOW_BD_HP_AMP:
1202 case RT5663_SOF_VOL_ZC2:
1203 case RT5663_ADC_STO2_ADJ1:
1204 case RT5663_ADC_STO2_ADJ2:
1205 case RT5663_A_JD_CTRL:
1206 case RT5663_JD1_TRES_CTRL:
1207 case RT5663_JD2_TRES_CTRL:
1208 case RT5663_V2_JD_CTRL2:
1209 case RT5663_DUM_REG_2:
1210 case RT5663_DUM_REG_3:
1211 case RT5663_VENDOR_ID:
1212 case RT5663_VENDOR_ID_1:
1213 case RT5663_VENDOR_ID_2:
1214 case RT5663_DACADC_DIG_VOL2:
1215 case RT5663_DIG_IN_PIN2:
1216 case RT5663_PAD_DRV_CTL1:
1217 case RT5663_SOF_RAM_DEPOP:
1218 case RT5663_VOL_TEST:
1219 case RT5663_TEST_MODE_4:
1220 case RT5663_TEST_MODE_5:
1221 case RT5663_STO_DRE_9:
1222 case RT5663_MONO_DYNA_1:
1223 case RT5663_MONO_DYNA_2:
1224 case RT5663_MONO_DYNA_3:
1225 case RT5663_MONO_DYNA_4:
1226 case RT5663_MONO_DYNA_5:
1227 case RT5663_MONO_DYNA_6:
1228 case RT5663_STO1_SIL_DET:
1229 case RT5663_MONOL_SIL_DET:
1230 case RT5663_MONOR_SIL_DET:
1231 case RT5663_STO2_DAC_SIL:
1232 case RT5663_PWR_SAV_CTL1:
1233 case RT5663_PWR_SAV_CTL2:
1234 case RT5663_PWR_SAV_CTL3:
1235 case RT5663_PWR_SAV_CTL4:
1236 case RT5663_PWR_SAV_CTL5:
1237 case RT5663_PWR_SAV_CTL6:
1238 case RT5663_MONO_AMP_CAL1:
1239 case RT5663_MONO_AMP_CAL2:
1240 case RT5663_MONO_AMP_CAL3:
1241 case RT5663_MONO_AMP_CAL4:
1242 case RT5663_MONO_AMP_CAL5:
1243 case RT5663_MONO_AMP_CAL6:
1244 case RT5663_MONO_AMP_CAL7:
1245 case RT5663_MONO_AMP_CAL_ST1:
1246 case RT5663_MONO_AMP_CAL_ST2:
1247 case RT5663_MONO_AMP_CAL_ST3:
1248 case RT5663_MONO_AMP_CAL_ST4:
1249 case RT5663_MONO_AMP_CAL_ST5:
1250 case RT5663_V2_HP_IMP_SEN_13:
1251 case RT5663_V2_HP_IMP_SEN_14:
1252 case RT5663_V2_HP_IMP_SEN_6:
1253 case RT5663_V2_HP_IMP_SEN_7:
1254 case RT5663_V2_HP_IMP_SEN_8:
1255 case RT5663_V2_HP_IMP_SEN_9:
1256 case RT5663_V2_HP_IMP_SEN_10:
1257 case RT5663_HP_LOGIC_3:
1258 case RT5663_HP_CALIB_ST10:
1259 case RT5663_HP_CALIB_ST11:
1260 case RT5663_PRO_REG_TBL_4:
1261 case RT5663_PRO_REG_TBL_5:
1262 case RT5663_PRO_REG_TBL_6:
1263 case RT5663_PRO_REG_TBL_7:
1264 case RT5663_PRO_REG_TBL_8:
1265 case RT5663_PRO_REG_TBL_9:
1266 case RT5663_SAR_ADC_INL_1:
1267 case RT5663_SAR_ADC_INL_2:
1268 case RT5663_SAR_ADC_INL_3:
1269 case RT5663_SAR_ADC_INL_4:
1270 case RT5663_SAR_ADC_INL_5:
1271 case RT5663_SAR_ADC_INL_6:
1272 case RT5663_SAR_ADC_INL_7:
1273 case RT5663_SAR_ADC_INL_8:
1274 case RT5663_SAR_ADC_INL_9:
1275 case RT5663_SAR_ADC_INL_10:
1276 case RT5663_SAR_ADC_INL_11:
1277 case RT5663_SAR_ADC_INL_12:
1278 case RT5663_DRC_CTRL_1:
1279 case RT5663_DRC1_CTRL_2:
1280 case RT5663_DRC1_CTRL_3:
1281 case RT5663_DRC1_CTRL_4:
1282 case RT5663_DRC1_CTRL_5:
1283 case RT5663_DRC1_CTRL_6:
1284 case RT5663_DRC1_HD_CTRL_1:
1285 case RT5663_DRC1_HD_CTRL_2:
1286 case RT5663_DRC1_PRI_REG_1:
1287 case RT5663_DRC1_PRI_REG_2:
1288 case RT5663_DRC1_PRI_REG_3:
1289 case RT5663_DRC1_PRI_REG_4:
1290 case RT5663_DRC1_PRI_REG_5:
1291 case RT5663_DRC1_PRI_REG_6:
1292 case RT5663_DRC1_PRI_REG_7:
1293 case RT5663_DRC1_PRI_REG_8:
1294 case RT5663_ALC_PGA_CTL_1:
1295 case RT5663_ALC_PGA_CTL_2:
1296 case RT5663_ALC_PGA_CTL_3:
1297 case RT5663_ALC_PGA_CTL_4:
1298 case RT5663_ALC_PGA_CTL_5:
1299 case RT5663_ALC_PGA_CTL_6:
1300 case RT5663_ALC_PGA_CTL_7:
1301 case RT5663_ALC_PGA_CTL_8:
1302 case RT5663_ALC_PGA_REG_1:
1303 case RT5663_ALC_PGA_REG_2:
1304 case RT5663_ALC_PGA_REG_3:
1305 case RT5663_ADC_EQ_RECOV_1:
1306 case RT5663_ADC_EQ_RECOV_2:
1307 case RT5663_ADC_EQ_RECOV_3:
1308 case RT5663_ADC_EQ_RECOV_4:
1309 case RT5663_ADC_EQ_RECOV_5:
1310 case RT5663_ADC_EQ_RECOV_6:
1311 case RT5663_ADC_EQ_RECOV_7:
1312 case RT5663_ADC_EQ_RECOV_8:
1313 case RT5663_ADC_EQ_RECOV_9:
1314 case RT5663_ADC_EQ_RECOV_10:
1315 case RT5663_ADC_EQ_RECOV_11:
1316 case RT5663_ADC_EQ_RECOV_12:
1317 case RT5663_ADC_EQ_RECOV_13:
1318 case RT5663_VID_HIDDEN:
1319 case RT5663_VID_CUSTOMER:
1320 case RT5663_SCAN_MODE:
1321 case RT5663_I2C_BYPA:
1324 case RT5663_DEPOP_3:
1325 case RT5663_ASRC_11_2:
1326 case RT5663_INT_ST_2:
1327 case RT5663_GPIO_STA1:
1328 case RT5663_SIN_GEN_1:
1329 case RT5663_SIN_GEN_2:
1330 case RT5663_SIN_GEN_3:
1331 case RT5663_IL_CMD_PWRSAV1:
1332 case RT5663_IL_CMD_PWRSAV2:
1333 case RT5663_EM_JACK_TYPE_1:
1334 case RT5663_EM_JACK_TYPE_2:
1335 case RT5663_EM_JACK_TYPE_3:
1336 case RT5663_EM_JACK_TYPE_4:
1337 case RT5663_FAST_OFF_MICBIAS:
1338 case RT5663_ANA_BIAS_CUR_1:
1339 case RT5663_ANA_BIAS_CUR_2:
1340 case RT5663_BIAS_CUR_9:
1341 case RT5663_DUMMY_REG_4:
1342 case RT5663_VREF_RECMIX:
1343 case RT5663_CHARGE_PUMP_1_2:
1344 case RT5663_CHARGE_PUMP_1_3:
1345 case RT5663_CHARGE_PUMP_2:
1346 case RT5663_CHOP_DAC_R:
1347 case RT5663_DUMMY_CTL_DACLR:
1348 case RT5663_DUMMY_REG_5:
1349 case RT5663_SOFT_RAMP:
1350 case RT5663_TEST_MODE_1:
1351 case RT5663_STO_DRE_10:
1352 case RT5663_MIC_DECRO_1:
1353 case RT5663_MIC_DECRO_2:
1354 case RT5663_MIC_DECRO_3:
1355 case RT5663_MIC_DECRO_4:
1356 case RT5663_MIC_DECRO_5:
1357 case RT5663_MIC_DECRO_6:
1358 case RT5663_HP_DECRO_1:
1359 case RT5663_HP_DECRO_2:
1360 case RT5663_HP_DECRO_3:
1361 case RT5663_HP_DECRO_4:
1362 case RT5663_HP_DECOUP:
1363 case RT5663_HP_IMPSEN_MAP4:
1364 case RT5663_HP_IMPSEN_MAP5:
1365 case RT5663_HP_IMPSEN_MAP7:
1366 case RT5663_HP_CALIB_1:
1372 return rt5663_readable_register(dev, reg);
1376 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1377 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1378 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1379 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1381 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1382 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1383 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1384 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1385 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1386 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1387 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1388 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1389 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1392 /* Interface data select */
1393 static const char * const rt5663_if1_adc_data_select[] = {
1394 "L/R", "R/L", "L/L", "R/R"
1397 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1398 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1400 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1403 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1406 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1407 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1408 /* reset in-line command */
1409 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1410 RT5663_RESET_4BTN_INL_MASK,
1411 RT5663_RESET_4BTN_INL_RESET);
1412 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1413 RT5663_RESET_4BTN_INL_MASK,
1414 RT5663_RESET_4BTN_INL_NOR);
1415 switch (rt5663->codec_ver) {
1417 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1418 RT5663_V2_EN_IRQ_INLINE_MASK,
1419 RT5663_V2_EN_IRQ_INLINE_NOR);
1422 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1423 RT5663_EN_IRQ_INLINE_MASK,
1424 RT5663_EN_IRQ_INLINE_NOR);
1427 dev_err(component->dev, "Unknown CODEC Version\n");
1430 switch (rt5663->codec_ver) {
1432 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1433 RT5663_V2_EN_IRQ_INLINE_MASK,
1434 RT5663_V2_EN_IRQ_INLINE_BYP);
1437 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1438 RT5663_EN_IRQ_INLINE_MASK,
1439 RT5663_EN_IRQ_INLINE_BYP);
1442 dev_err(component->dev, "Unknown CODEC Version\n");
1444 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1445 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1446 /* reset in-line command */
1447 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1448 RT5663_RESET_4BTN_INL_MASK,
1449 RT5663_RESET_4BTN_INL_RESET);
1450 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1451 RT5663_RESET_4BTN_INL_MASK,
1452 RT5663_RESET_4BTN_INL_NOR);
1457 * rt5663_v2_jack_detect - Detect headset.
1458 * @component: SoC audio component device.
1459 * @jack_insert: Jack insert or not.
1461 * Detect whether is headset or not when jack inserted.
1463 * Returns detect status.
1466 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1468 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1469 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1470 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1472 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1474 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1475 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1477 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1478 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1479 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1480 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1481 snd_soc_dapm_sync(dapm);
1482 snd_soc_component_update_bits(component, RT5663_RC_CLK,
1483 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1484 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1487 msleep(sleep_time[i]);
1488 val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003;
1489 if (val == 0x1 || val == 0x2 || val == 0x3)
1491 dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1492 __func__, val, sleep_time[i]);
1495 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1499 rt5663->jack_type = SND_JACK_HEADSET;
1500 rt5663_enable_push_button_irq(component, true);
1503 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1504 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1505 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1506 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1507 snd_soc_dapm_sync(dapm);
1508 rt5663->jack_type = SND_JACK_HEADPHONE;
1512 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1514 if (rt5663->jack_type == SND_JACK_HEADSET) {
1515 rt5663_enable_push_button_irq(component, false);
1516 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1517 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1518 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1519 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1520 snd_soc_dapm_sync(dapm);
1522 rt5663->jack_type = 0;
1525 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1526 return rt5663->jack_type;
1530 * rt5663_jack_detect - Detect headset.
1531 * @component: SoC audio component device.
1532 * @jack_insert: Jack insert or not.
1534 * Detect whether is headset or not when jack inserted.
1536 * Returns detect status.
1538 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1540 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1543 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1546 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1547 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1548 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1549 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1550 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1551 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1552 snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1553 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1554 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1555 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1556 snd_soc_component_update_bits(component, RT5663_CBJ_1,
1557 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1558 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1559 snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1560 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1561 /* BST1 power on for JD */
1562 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1563 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1564 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1565 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1566 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1567 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1568 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1569 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1570 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1571 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1572 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1573 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1574 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1575 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1577 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1578 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1579 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1580 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1581 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1582 snd_soc_component_update_bits(component, RT5663_IRQ_1,
1583 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1584 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1585 RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1586 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1587 RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1590 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1592 usleep_range(10000, 10005);
1601 val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1602 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1604 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1605 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1606 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1611 rt5663->jack_type = SND_JACK_HEADSET;
1612 rt5663_enable_push_button_irq(component, true);
1614 if (rt5663->pdata.impedance_sensing_num)
1617 if (rt5663->pdata.dc_offset_l_manual_mic) {
1618 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1619 rt5663->pdata.dc_offset_l_manual_mic >>
1621 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1622 rt5663->pdata.dc_offset_l_manual_mic &
1626 if (rt5663->pdata.dc_offset_r_manual_mic) {
1627 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1628 rt5663->pdata.dc_offset_r_manual_mic >>
1630 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1631 rt5663->pdata.dc_offset_r_manual_mic &
1636 rt5663->jack_type = SND_JACK_HEADPHONE;
1637 snd_soc_component_update_bits(component,
1639 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1640 RT5663_PWR_VREF2_MASK, 0);
1641 if (rt5663->pdata.impedance_sensing_num)
1644 if (rt5663->pdata.dc_offset_l_manual) {
1645 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1646 rt5663->pdata.dc_offset_l_manual >> 16);
1647 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1648 rt5663->pdata.dc_offset_l_manual &
1652 if (rt5663->pdata.dc_offset_r_manual) {
1653 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1654 rt5663->pdata.dc_offset_r_manual >> 16);
1655 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1656 rt5663->pdata.dc_offset_r_manual &
1662 if (rt5663->jack_type == SND_JACK_HEADSET)
1663 rt5663_enable_push_button_irq(component, false);
1664 rt5663->jack_type = 0;
1665 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1666 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1667 RT5663_PWR_VREF2_MASK, 0);
1670 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1671 return rt5663->jack_type;
1674 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1676 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1677 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1679 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1680 if (rt5663->imp_table[i].vol == 7)
1684 if (rt5663->jack_type == SND_JACK_HEADSET) {
1685 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1686 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1687 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1688 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1689 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1690 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1691 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1692 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1694 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1695 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1696 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1697 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1698 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1699 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1700 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1701 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1704 reg84 = snd_soc_component_read32(component, RT5663_ASRC_2);
1705 reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER);
1706 reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1);
1707 reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1);
1708 reg10 = snd_soc_component_read32(component, RT5663_RECMIX);
1709 reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK);
1711 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1712 snd_soc_component_write(component, RT5663_ASRC_2, 0);
1713 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1714 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1715 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1716 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1717 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1718 usleep_range(10000, 10005);
1719 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1720 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1721 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1722 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1723 RT5663_SCLK_SRC_RCCLK);
1724 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1725 RT5663_DIG_25M_CLK_EN);
1726 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1727 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1728 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1729 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1730 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1731 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1732 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1733 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1734 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1735 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1736 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1737 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1738 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1739 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1741 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1742 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1745 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1746 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1747 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1749 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1750 snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1751 snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1752 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1753 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1754 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1755 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1756 snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1757 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1758 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1759 snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1760 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1761 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1762 snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1763 snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1764 snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1765 snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1766 snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1767 snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1768 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1769 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1770 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1772 for (i = 0; i < 100; i++) {
1774 if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2)
1778 value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4);
1780 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1781 snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1782 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1783 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1784 RT5663_DIG_25M_CLK_DIS);
1785 snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1786 snd_soc_component_write(component, RT5663_RECMIX, reg10);
1787 snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1788 snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1789 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1790 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1791 snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1792 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1793 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1794 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1795 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1796 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1797 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1798 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1799 RT5663_PWR_ADC_R1, 0);
1800 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1801 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1802 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1803 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1804 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1805 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1806 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1807 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1808 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1809 snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1811 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1812 if (value >= rt5663->imp_table[i].imp_min &&
1813 value <= rt5663->imp_table[i].imp_max)
1817 snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1818 rt5663->imp_table[i].vol);
1819 snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1820 rt5663->imp_table[i].vol);
1822 if (rt5663->jack_type == SND_JACK_HEADSET) {
1823 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1824 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1825 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1826 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1827 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1828 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1829 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1830 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1832 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1833 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1834 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1835 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1836 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1837 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1838 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1839 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1845 static int rt5663_button_detect(struct snd_soc_component *component)
1849 val = snd_soc_component_read32(component, RT5663_IL_CMD_5);
1850 dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1851 btn_type = val & 0xfff0;
1852 snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1857 static irqreturn_t rt5663_irq(int irq, void *data)
1859 struct rt5663_priv *rt5663 = data;
1861 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1864 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1865 msecs_to_jiffies(250));
1870 static int rt5663_set_jack_detect(struct snd_soc_component *component,
1871 struct snd_soc_jack *hs_jack, void *data)
1873 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1875 rt5663->hs_jack = hs_jack;
1877 rt5663_irq(0, rt5663);
1882 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1884 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1885 int val = snd_soc_component_read32(component, RT5663_INT_ST_1);
1887 dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1890 switch (rt5663->codec_ver) {
1892 return !(val & 0x2000);
1894 return !(val & 0x1000);
1896 dev_err(component->dev, "Unknown CODEC Version\n");
1902 static void rt5663_jack_detect_work(struct work_struct *work)
1904 struct rt5663_priv *rt5663 =
1905 container_of(work, struct rt5663_priv, jack_detect_work.work);
1906 struct snd_soc_component *component = rt5663->component;
1907 int btn_type, report = 0;
1912 if (rt5663_check_jd_status(component)) {
1914 if (rt5663->jack_type == 0) {
1915 /* jack was out, report jack type */
1916 switch (rt5663->codec_ver) {
1918 report = rt5663_v2_jack_detect(
1919 rt5663->component, 1);
1922 report = rt5663_jack_detect(rt5663->component, 1);
1923 if (rt5663->pdata.impedance_sensing_num)
1924 rt5663_impedance_sensing(rt5663->component);
1927 dev_err(component->dev, "Unknown CODEC Version\n");
1930 /* Delay the jack insert report to avoid pop noise */
1933 /* jack is already in, report button event */
1934 report = SND_JACK_HEADSET;
1935 btn_type = rt5663_button_detect(rt5663->component);
1937 * rt5663 can report three kinds of button behavior,
1938 * one click, double click and hold. However,
1939 * currently we will report button pressed/released
1940 * event. So all the three button behaviors are
1941 * treated as button pressed.
1947 report |= SND_JACK_BTN_0;
1952 report |= SND_JACK_BTN_1;
1957 report |= SND_JACK_BTN_2;
1962 report |= SND_JACK_BTN_3;
1964 case 0x0000: /* unpressed */
1968 dev_err(rt5663->component->dev,
1969 "Unexpected button code 0x%04x\n",
1973 /* button release or spurious interrput*/
1974 if (btn_type == 0) {
1975 report = rt5663->jack_type;
1976 cancel_delayed_work_sync(
1977 &rt5663->jd_unplug_work);
1979 queue_delayed_work(system_wq,
1980 &rt5663->jd_unplug_work,
1981 msecs_to_jiffies(500));
1986 switch (rt5663->codec_ver) {
1988 report = rt5663_v2_jack_detect(rt5663->component, 0);
1991 report = rt5663_jack_detect(rt5663->component, 0);
1994 dev_err(component->dev, "Unknown CODEC Version\n");
1997 dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1998 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1999 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2000 SND_JACK_BTN_2 | SND_JACK_BTN_3);
2003 static void rt5663_jd_unplug_work(struct work_struct *work)
2005 struct rt5663_priv *rt5663 =
2006 container_of(work, struct rt5663_priv, jd_unplug_work.work);
2007 struct snd_soc_component *component = rt5663->component;
2012 if (!rt5663_check_jd_status(component)) {
2014 switch (rt5663->codec_ver) {
2016 rt5663_v2_jack_detect(rt5663->component, 0);
2019 rt5663_jack_detect(rt5663->component, 0);
2022 dev_err(component->dev, "Unknown CODEC Version\n");
2025 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2026 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2027 SND_JACK_BTN_2 | SND_JACK_BTN_3);
2029 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2030 msecs_to_jiffies(500));
2034 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2035 /* DAC Digital Volume */
2036 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2037 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2038 87, 0, dac_vol_tlv),
2039 /* ADC Digital Volume Control */
2040 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2041 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2042 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2043 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2044 63, 0, adc_vol_tlv),
2047 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2048 /* Headphone Output Volume */
2049 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2050 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2051 rt5663_v2_hp_vol_tlv),
2052 /* Mic Boost Volume */
2053 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2054 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2057 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2058 /* Mic Boost Volume*/
2059 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2060 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2061 /* Data Swap for Slot0/1 in ADCDAT1 */
2062 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2065 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2066 /* Headphone Output Volume */
2067 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2068 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2072 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2073 struct snd_soc_dapm_widget *sink)
2076 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2078 val = snd_soc_component_read32(component, RT5663_GLB_CLK);
2079 val &= RT5663_SCLK_SRC_MASK;
2080 if (val == RT5663_SCLK_SRC_PLL1)
2086 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2087 struct snd_soc_dapm_widget *sink)
2089 unsigned int reg, shift, val;
2090 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2091 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2093 if (rt5663->codec_ver == CODEC_VER_1) {
2095 case RT5663_ADC_STO1_ASRC_SHIFT:
2096 reg = RT5663_ASRC_3;
2097 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2099 case RT5663_DAC_STO1_ASRC_SHIFT:
2100 reg = RT5663_ASRC_2;
2101 shift = RT5663_DA_STO1_TRACK_SHIFT;
2108 case RT5663_ADC_STO1_ASRC_SHIFT:
2109 reg = RT5663_ASRC_2;
2110 shift = RT5663_AD_STO1_TRACK_SHIFT;
2112 case RT5663_DAC_STO1_ASRC_SHIFT:
2113 reg = RT5663_ASRC_2;
2114 shift = RT5663_DA_STO1_TRACK_SHIFT;
2121 val = (snd_soc_component_read32(component, reg) >> shift) & 0x7;
2129 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2130 struct snd_soc_dapm_widget *sink)
2132 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2133 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2134 int da_asrc_en, ad_asrc_en;
2136 da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2137 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2138 switch (rt5663->codec_ver) {
2140 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) &
2141 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2144 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2145 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2148 dev_err(component->dev, "Unknown CODEC Version\n");
2152 if (da_asrc_en || ad_asrc_en)
2153 if (rt5663->sysclk > rt5663->lrck * 384)
2156 dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2162 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2163 * @component: SoC audio component device.
2164 * @filter_mask: mask of filters.
2165 * @clk_src: clock source
2167 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2168 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2169 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2170 * ASRC function will track i2s clock and generate a corresponding system clock
2171 * for codec. This function provides an API to select the clock source for a
2172 * set of filters specified by the mask. And the codec driver will turn on ASRC
2173 * for these filters if ASRC is selected as their clock source.
2175 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2176 unsigned int filter_mask, unsigned int clk_src)
2178 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2179 unsigned int asrc2_mask = 0;
2180 unsigned int asrc2_value = 0;
2181 unsigned int asrc3_mask = 0;
2182 unsigned int asrc3_value = 0;
2185 case RT5663_CLK_SEL_SYS:
2186 case RT5663_CLK_SEL_I2S1_ASRC:
2193 if (filter_mask & RT5663_DA_STEREO_FILTER) {
2194 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2195 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2198 if (filter_mask & RT5663_AD_STEREO_FILTER) {
2199 switch (rt5663->codec_ver) {
2201 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2202 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2205 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2206 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2209 dev_err(component->dev, "Unknown CODEC Version\n");
2214 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2218 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2223 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2226 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2227 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2228 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2229 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2230 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2233 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2234 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2235 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2239 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2240 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2241 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2242 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2243 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2246 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2247 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2248 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2249 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2250 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2253 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2254 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2255 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2256 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2257 RT5663_M_DAC1_L_SHIFT, 1, 1),
2260 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2261 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2262 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2263 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2264 RT5663_M_DAC1_R_SHIFT, 1, 1),
2267 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2268 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2269 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2272 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2273 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2274 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2278 static const struct snd_kcontrol_new rt5663_hpo_switch =
2279 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2280 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2282 /* Stereo ADC source */
2283 static const char * const rt5663_sto1_adc_src[] = {
2287 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2288 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2290 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2291 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2293 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2294 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2296 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2297 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2299 /* RT5663: Analog DACL1 input source */
2300 static const char * const rt5663_alg_dacl_src[] = {
2301 "DAC L", "STO DAC MIXL"
2304 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2305 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2307 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2308 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2310 /* RT5663: Analog DACR1 input source */
2311 static const char * const rt5663_alg_dacr_src[] = {
2312 "DAC R", "STO DAC MIXR"
2315 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2316 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2318 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2319 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2321 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2322 struct snd_kcontrol *kcontrol, int event)
2324 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2325 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2328 case SND_SOC_DAPM_POST_PMU:
2329 if (rt5663->codec_ver == CODEC_VER_1) {
2330 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2331 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2332 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2333 RT5663_HP_SIG_SRC1_MASK,
2334 RT5663_HP_SIG_SRC1_SILENCE);
2336 snd_soc_component_update_bits(component,
2337 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2338 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2339 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2340 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2341 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2342 snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2343 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2344 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2345 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2346 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2347 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2349 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2351 snd_soc_component_update_bits(component,
2352 RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
2356 case SND_SOC_DAPM_PRE_PMD:
2357 if (rt5663->codec_ver == CODEC_VER_1) {
2358 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2359 RT5663_HP_SIG_SRC1_MASK,
2360 RT5663_HP_SIG_SRC1_REG);
2362 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2363 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2364 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2365 snd_soc_component_update_bits(component,
2366 RT5663_DACREF_LDO, 0x3e0e, 0);
2367 snd_soc_component_update_bits(component,
2368 RT5663_DIG_VOL_ZCD, 0x00c0, 0);
2379 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2380 struct snd_kcontrol *kcontrol, int event)
2382 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2383 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2386 case SND_SOC_DAPM_PRE_PMU:
2387 if (rt5663->codec_ver == CODEC_VER_0) {
2388 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2390 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2395 case SND_SOC_DAPM_POST_PMD:
2396 if (rt5663->codec_ver == CODEC_VER_0) {
2397 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2398 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2409 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2410 struct snd_kcontrol *kcontrol, int event)
2412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2415 case SND_SOC_DAPM_POST_PMU:
2416 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2417 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2418 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2421 case SND_SOC_DAPM_PRE_PMD:
2422 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2423 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2433 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2434 struct snd_kcontrol *kcontrol, int event)
2436 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2439 case SND_SOC_DAPM_POST_PMU:
2440 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2441 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2444 case SND_SOC_DAPM_PRE_PMD:
2445 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2446 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2456 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2457 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2461 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2462 RT5663_PWR_MB1_SHIFT, 0),
2463 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2464 RT5663_PWR_MB2_SHIFT, 0),
2467 SND_SOC_DAPM_INPUT("IN1P"),
2468 SND_SOC_DAPM_INPUT("IN1N"),
2470 /* REC Mixer Power */
2471 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2472 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2475 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2476 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2477 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2478 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2479 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2482 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2483 0, 0, rt5663_sto1_adc_l_mix,
2484 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2486 /* ADC Filter Power */
2487 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2488 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2490 /* Digital Interface */
2491 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2493 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2497 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2499 /* Audio Interface */
2500 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2501 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2503 /* DAC mixer before sound effect */
2504 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2505 ARRAY_SIZE(rt5663_adda_l_mix)),
2506 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2507 ARRAY_SIZE(rt5663_adda_r_mix)),
2508 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2509 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2512 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2513 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2514 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2515 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2516 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2517 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2520 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2521 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2522 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2523 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2524 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2525 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2528 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2529 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2530 SND_SOC_DAPM_POST_PMD),
2531 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2532 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2535 SND_SOC_DAPM_OUTPUT("HPOL"),
2536 SND_SOC_DAPM_OUTPUT("HPOR"),
2539 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2540 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2541 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2542 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2543 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2544 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2545 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2548 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2549 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2550 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2551 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2552 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2553 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2556 SND_SOC_DAPM_INPUT("IN2P"),
2557 SND_SOC_DAPM_INPUT("IN2N"),
2560 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2561 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2562 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2564 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2565 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2566 SND_SOC_DAPM_POST_PMU),
2569 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2570 ARRAY_SIZE(rt5663_recmix1l)),
2571 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2572 ARRAY_SIZE(rt5663_recmix1r)),
2573 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2574 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2577 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2578 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2579 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2583 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2585 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2587 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2588 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2589 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2591 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2592 &rt5663_sto1_adcl_mux),
2593 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2594 &rt5663_sto1_adcr_mux),
2597 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2598 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2600 /* Analog DAC Clock */
2601 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2602 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2605 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2606 &rt5663_hpo_switch),
2609 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2610 /* System Clock Pre Divider Gating */
2611 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2612 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2613 SND_SOC_DAPM_PRE_PMD),
2616 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2617 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2620 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2621 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2623 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2624 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2625 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2628 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2631 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2632 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2634 /* Analog DAC source */
2635 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2636 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2639 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2641 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2644 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2645 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2646 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2648 { "ADC L", NULL, "ADC L Power" },
2649 { "ADC L", NULL, "ADC Clock" },
2651 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2653 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2654 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2655 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2657 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2658 { "IF ADC", NULL, "IF1 ADC1" },
2659 { "AIFTX", NULL, "IF ADC" },
2660 { "AIFTX", NULL, "I2S" },
2662 { "AIFRX", NULL, "I2S" },
2663 { "IF DAC", NULL, "AIFRX" },
2664 { "IF1 DAC1 L", NULL, "IF DAC" },
2665 { "IF1 DAC1 R", NULL, "IF DAC" },
2667 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2668 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2669 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2670 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2671 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2672 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2673 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2675 { "DAC L1", NULL, "ADDA MIXL" },
2676 { "DAC R1", NULL, "ADDA MIXR" },
2678 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2679 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2680 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2681 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2682 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2683 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2685 { "HP Amp", NULL, "HP Charge Pump" },
2686 { "HP Amp", NULL, "DAC L" },
2687 { "HP Amp", NULL, "DAC R" },
2690 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2691 { "MICBIAS1", NULL, "LDO2" },
2692 { "MICBIAS2", NULL, "LDO2" },
2694 { "BST1 CBJ", NULL, "IN1P" },
2695 { "BST1 CBJ", NULL, "IN1N" },
2696 { "BST1 CBJ", NULL, "CBJ Power" },
2698 { "BST2", NULL, "IN2P" },
2699 { "BST2", NULL, "IN2N" },
2700 { "BST2", NULL, "BST2 Power" },
2702 { "RECMIX1L", "BST2 Switch", "BST2" },
2703 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2704 { "RECMIX1L", NULL, "RECMIX1L Power" },
2705 { "RECMIX1R", "BST2 Switch", "BST2" },
2706 { "RECMIX1R", NULL, "RECMIX1R Power" },
2708 { "ADC L", NULL, "RECMIX1L" },
2709 { "ADC R", NULL, "RECMIX1R" },
2710 { "ADC R", NULL, "ADC R Power" },
2711 { "ADC R", NULL, "ADC Clock" },
2713 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2714 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2715 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2717 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2718 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2719 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2720 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2722 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2723 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2724 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2726 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2728 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2730 { "DAC L", NULL, "STO1 DAC MIXL" },
2731 { "DAC L", NULL, "LDO DAC" },
2732 { "DAC L", NULL, "DAC Clock" },
2733 { "DAC R", NULL, "STO1 DAC MIXR" },
2734 { "DAC R", NULL, "LDO DAC" },
2735 { "DAC R", NULL, "DAC Clock" },
2737 { "HPO Playback", "Switch", "HP Amp" },
2738 { "HPOL", NULL, "HPO Playback" },
2739 { "HPOR", NULL, "HPO Playback" },
2742 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2743 { "I2S", NULL, "Pre Div Power" },
2745 { "BST1", NULL, "IN1P" },
2746 { "BST1", NULL, "IN1N" },
2747 { "BST1", NULL, "RECMIX1L Power" },
2749 { "ADC L", NULL, "BST1" },
2751 { "STO1 ADC L1", NULL, "ADC L" },
2753 { "DAC L Mux", "DAC L", "DAC L1" },
2754 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2755 { "DAC R Mux", "DAC R", "DAC R1"},
2756 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2758 { "DAC L", NULL, "DAC L Mux" },
2759 { "DAC R", NULL, "DAC R Mux" },
2761 { "HPOL", NULL, "HP Amp" },
2762 { "HPOR", NULL, "HP Amp" },
2765 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2766 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2768 struct snd_soc_component *component = dai->component;
2769 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2770 unsigned int val_len = 0;
2773 rt5663->lrck = params_rate(params);
2775 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2776 rt5663->lrck, rt5663->sysclk);
2778 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2780 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2781 rt5663->lrck, dai->id);
2785 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2787 switch (params_width(params)) {
2789 val_len = RT5663_I2S_DL_8;
2792 val_len = RT5663_I2S_DL_16;
2795 val_len = RT5663_I2S_DL_20;
2798 val_len = RT5663_I2S_DL_24;
2804 snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2805 RT5663_I2S_DL_MASK, val_len);
2807 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2808 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2813 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2815 struct snd_soc_component *component = dai->component;
2816 unsigned int reg_val = 0;
2818 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2819 case SND_SOC_DAIFMT_CBM_CFM:
2821 case SND_SOC_DAIFMT_CBS_CFS:
2822 reg_val |= RT5663_I2S_MS_S;
2828 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2829 case SND_SOC_DAIFMT_NB_NF:
2831 case SND_SOC_DAIFMT_IB_NF:
2832 reg_val |= RT5663_I2S_BP_INV;
2838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2839 case SND_SOC_DAIFMT_I2S:
2841 case SND_SOC_DAIFMT_LEFT_J:
2842 reg_val |= RT5663_I2S_DF_LEFT;
2844 case SND_SOC_DAIFMT_DSP_A:
2845 reg_val |= RT5663_I2S_DF_PCM_A;
2847 case SND_SOC_DAIFMT_DSP_B:
2848 reg_val |= RT5663_I2S_DF_PCM_B;
2854 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2855 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2860 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2861 unsigned int freq, int dir)
2863 struct snd_soc_component *component = dai->component;
2864 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2865 unsigned int reg_val = 0;
2867 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2871 case RT5663_SCLK_S_MCLK:
2872 reg_val |= RT5663_SCLK_SRC_MCLK;
2874 case RT5663_SCLK_S_PLL1:
2875 reg_val |= RT5663_SCLK_SRC_PLL1;
2877 case RT5663_SCLK_S_RCCLK:
2878 reg_val |= RT5663_SCLK_SRC_RCCLK;
2881 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2884 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2886 rt5663->sysclk = freq;
2887 rt5663->sysclk_src = clk_id;
2889 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2895 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2896 unsigned int freq_in, unsigned int freq_out)
2898 struct snd_soc_component *component = dai->component;
2899 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2900 struct rl6231_pll_code pll_code;
2902 int mask, shift, val;
2904 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2905 freq_out == rt5663->pll_out)
2908 if (!freq_in || !freq_out) {
2909 dev_dbg(component->dev, "PLL disabled\n");
2912 rt5663->pll_out = 0;
2913 snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2914 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2918 switch (rt5663->codec_ver) {
2920 mask = RT5663_V2_PLL1_SRC_MASK;
2921 shift = RT5663_V2_PLL1_SRC_SHIFT;
2924 mask = RT5663_PLL1_SRC_MASK;
2925 shift = RT5663_PLL1_SRC_SHIFT;
2928 dev_err(component->dev, "Unknown CODEC Version\n");
2933 case RT5663_PLL1_S_MCLK:
2936 case RT5663_PLL1_S_BCLK1:
2940 dev_err(component->dev, "Unknown PLL source %d\n", source);
2943 snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2945 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2947 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2951 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2952 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2955 snd_soc_component_write(component, RT5663_PLL_1,
2956 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2957 snd_soc_component_write(component, RT5663_PLL_2,
2958 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2959 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2961 rt5663->pll_in = freq_in;
2962 rt5663->pll_out = freq_out;
2963 rt5663->pll_src = source;
2968 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2969 unsigned int rx_mask, int slots, int slot_width)
2971 struct snd_soc_component *component = dai->component;
2972 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2973 unsigned int val = 0, reg;
2975 if (rx_mask || tx_mask)
2976 val |= RT5663_TDM_MODE_TDM;
2980 val |= RT5663_TDM_IN_CH_4;
2981 val |= RT5663_TDM_OUT_CH_4;
2984 val |= RT5663_TDM_IN_CH_6;
2985 val |= RT5663_TDM_OUT_CH_6;
2988 val |= RT5663_TDM_IN_CH_8;
2989 val |= RT5663_TDM_OUT_CH_8;
2997 switch (slot_width) {
2999 val |= RT5663_TDM_IN_LEN_20;
3000 val |= RT5663_TDM_OUT_LEN_20;
3003 val |= RT5663_TDM_IN_LEN_24;
3004 val |= RT5663_TDM_OUT_LEN_24;
3007 val |= RT5663_TDM_IN_LEN_32;
3008 val |= RT5663_TDM_OUT_LEN_32;
3016 switch (rt5663->codec_ver) {
3024 dev_err(component->dev, "Unknown CODEC Version\n");
3028 snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3029 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3030 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3035 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3037 struct snd_soc_component *component = dai->component;
3038 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3041 dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3043 if (rt5663->codec_ver == CODEC_VER_1)
3050 snd_soc_component_update_bits(component, reg,
3051 RT5663_TDM_LENGTN_MASK,
3052 RT5663_TDM_LENGTN_16);
3055 snd_soc_component_update_bits(component, reg,
3056 RT5663_TDM_LENGTN_MASK,
3057 RT5663_TDM_LENGTN_20);
3060 snd_soc_component_update_bits(component, reg,
3061 RT5663_TDM_LENGTN_MASK,
3062 RT5663_TDM_LENGTN_24);
3065 snd_soc_component_update_bits(component, reg,
3066 RT5663_TDM_LENGTN_MASK,
3067 RT5663_TDM_LENGTN_32);
3070 dev_err(component->dev, "Invalid ratio!\n");
3077 static int rt5663_set_bias_level(struct snd_soc_component *component,
3078 enum snd_soc_bias_level level)
3080 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3083 case SND_SOC_BIAS_ON:
3084 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3085 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3086 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3089 case SND_SOC_BIAS_PREPARE:
3090 if (rt5663->codec_ver == CODEC_VER_1) {
3091 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3092 RT5663_DIG_GATE_CTRL_MASK,
3093 RT5663_DIG_GATE_CTRL_EN);
3094 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3095 RT5663_EN_ANA_CLK_DET_MASK |
3096 RT5663_PWR_CLK_DET_MASK,
3097 RT5663_EN_ANA_CLK_DET_AUTO |
3098 RT5663_PWR_CLK_DET_EN);
3102 case SND_SOC_BIAS_STANDBY:
3103 if (rt5663->codec_ver == CODEC_VER_1)
3104 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3105 RT5663_DIG_GATE_CTRL_MASK,
3106 RT5663_DIG_GATE_CTRL_DIS);
3107 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3108 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3109 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3110 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3111 RT5663_PWR_VREF2 | RT5663_PWR_MB);
3112 usleep_range(10000, 10005);
3113 if (rt5663->codec_ver == CODEC_VER_1) {
3114 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3115 RT5663_EN_ANA_CLK_DET_MASK |
3116 RT5663_PWR_CLK_DET_MASK,
3117 RT5663_EN_ANA_CLK_DET_DIS |
3118 RT5663_PWR_CLK_DET_DIS);
3122 case SND_SOC_BIAS_OFF:
3123 if (rt5663->jack_type != SND_JACK_HEADSET)
3124 snd_soc_component_update_bits(component,
3126 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3127 RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3128 RT5663_PWR_MB_MASK, 0);
3130 snd_soc_component_update_bits(component,
3132 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3133 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3143 static int rt5663_probe(struct snd_soc_component *component)
3145 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3146 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3148 rt5663->component = component;
3150 switch (rt5663->codec_ver) {
3152 snd_soc_dapm_new_controls(dapm,
3153 rt5663_v2_specific_dapm_widgets,
3154 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3155 snd_soc_dapm_add_routes(dapm,
3156 rt5663_v2_specific_dapm_routes,
3157 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3158 snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3159 ARRAY_SIZE(rt5663_v2_specific_controls));
3162 snd_soc_dapm_new_controls(dapm,
3163 rt5663_specific_dapm_widgets,
3164 ARRAY_SIZE(rt5663_specific_dapm_widgets));
3165 snd_soc_dapm_add_routes(dapm,
3166 rt5663_specific_dapm_routes,
3167 ARRAY_SIZE(rt5663_specific_dapm_routes));
3168 snd_soc_add_component_controls(component, rt5663_specific_controls,
3169 ARRAY_SIZE(rt5663_specific_controls));
3171 if (!rt5663->imp_table)
3172 snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3173 ARRAY_SIZE(rt5663_hpvol_controls));
3180 static void rt5663_remove(struct snd_soc_component *component)
3182 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3184 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3188 static int rt5663_suspend(struct snd_soc_component *component)
3190 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3192 regcache_cache_only(rt5663->regmap, true);
3193 regcache_mark_dirty(rt5663->regmap);
3198 static int rt5663_resume(struct snd_soc_component *component)
3200 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3202 regcache_cache_only(rt5663->regmap, false);
3203 regcache_sync(rt5663->regmap);
3205 rt5663_irq(0, rt5663);
3210 #define rt5663_suspend NULL
3211 #define rt5663_resume NULL
3214 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3215 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3216 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3218 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3219 .hw_params = rt5663_hw_params,
3220 .set_fmt = rt5663_set_dai_fmt,
3221 .set_sysclk = rt5663_set_dai_sysclk,
3222 .set_pll = rt5663_set_dai_pll,
3223 .set_tdm_slot = rt5663_set_tdm_slot,
3224 .set_bclk_ratio = rt5663_set_bclk_ratio,
3227 static struct snd_soc_dai_driver rt5663_dai[] = {
3229 .name = "rt5663-aif",
3232 .stream_name = "AIF Playback",
3235 .rates = RT5663_STEREO_RATES,
3236 .formats = RT5663_FORMATS,
3239 .stream_name = "AIF Capture",
3242 .rates = RT5663_STEREO_RATES,
3243 .formats = RT5663_FORMATS,
3245 .ops = &rt5663_aif_dai_ops,
3249 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3250 .probe = rt5663_probe,
3251 .remove = rt5663_remove,
3252 .suspend = rt5663_suspend,
3253 .resume = rt5663_resume,
3254 .set_bias_level = rt5663_set_bias_level,
3255 .controls = rt5663_snd_controls,
3256 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
3257 .dapm_widgets = rt5663_dapm_widgets,
3258 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3259 .dapm_routes = rt5663_dapm_routes,
3260 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3261 .set_jack = rt5663_set_jack_detect,
3262 .use_pmdown_time = 1,
3264 .non_legacy_dai_naming = 1,
3267 static const struct regmap_config rt5663_v2_regmap = {
3270 .use_single_read = true,
3271 .use_single_write = true,
3272 .max_register = 0x07fa,
3273 .volatile_reg = rt5663_v2_volatile_register,
3274 .readable_reg = rt5663_v2_readable_register,
3275 .cache_type = REGCACHE_RBTREE,
3276 .reg_defaults = rt5663_v2_reg,
3277 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3280 static const struct regmap_config rt5663_regmap = {
3283 .use_single_read = true,
3284 .use_single_write = true,
3285 .max_register = 0x03f3,
3286 .volatile_reg = rt5663_volatile_register,
3287 .readable_reg = rt5663_readable_register,
3288 .cache_type = REGCACHE_RBTREE,
3289 .reg_defaults = rt5663_reg,
3290 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3293 static const struct regmap_config temp_regmap = {
3297 .use_single_read = true,
3298 .use_single_write = true,
3299 .max_register = 0x03f3,
3300 .cache_type = REGCACHE_NONE,
3303 static const struct i2c_device_id rt5663_i2c_id[] = {
3307 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3309 #if defined(CONFIG_OF)
3310 static const struct of_device_id rt5663_of_match[] = {
3311 { .compatible = "realtek,rt5663", },
3314 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3318 static const struct acpi_device_id rt5663_acpi_match[] = {
3322 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3325 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3327 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3328 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3329 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3330 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3331 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3332 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3333 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3334 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3335 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3336 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3338 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3339 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3340 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3344 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3348 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3350 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3351 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3352 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3353 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3354 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3355 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3356 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3357 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3358 regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3359 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3361 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3362 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3363 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3364 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3365 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3366 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3367 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3368 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3369 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3370 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3374 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3375 if (!(value & 0x80))
3376 usleep_range(10000, 10005);
3384 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3385 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3386 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3387 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3388 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3389 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3390 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3391 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3392 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3393 regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3394 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3396 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3397 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3398 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3399 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3400 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3401 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3402 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3403 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3404 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3405 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3406 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3407 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3408 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3409 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3410 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3411 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3412 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3413 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3414 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3415 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3416 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3417 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3418 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3422 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3424 usleep_range(10000, 10005);
3433 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3434 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3435 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3439 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3441 usleep_range(10000, 10005);
3450 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3451 usleep_range(10000, 10005);
3452 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3453 usleep_range(10000, 10005);
3454 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3455 usleep_range(10000, 10005);
3456 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3457 usleep_range(10000, 10005);
3458 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3459 usleep_range(10000, 10005);
3460 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3461 usleep_range(10000, 10005);
3464 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3468 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3469 &rt5663->pdata.dc_offset_l_manual);
3470 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3471 &rt5663->pdata.dc_offset_r_manual);
3472 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3473 &rt5663->pdata.dc_offset_l_manual_mic);
3474 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3475 &rt5663->pdata.dc_offset_r_manual_mic);
3476 device_property_read_u32(dev, "realtek,impedance_sensing_num",
3477 &rt5663->pdata.impedance_sensing_num);
3479 if (rt5663->pdata.impedance_sensing_num) {
3480 table_size = sizeof(struct impedance_mapping_table) *
3481 rt5663->pdata.impedance_sensing_num;
3482 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3483 device_property_read_u32_array(dev,
3484 "realtek,impedance_sensing_table",
3485 (u32 *)rt5663->imp_table, table_size);
3491 static int rt5663_i2c_probe(struct i2c_client *i2c,
3492 const struct i2c_device_id *id)
3494 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3495 struct rt5663_priv *rt5663;
3498 struct regmap *regmap;
3500 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3506 i2c_set_clientdata(i2c, rt5663);
3509 rt5663->pdata = *pdata;
3511 rt5663_parse_dp(rt5663, &i2c->dev);
3513 for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
3514 rt5663->supplies[i].supply = rt5663_supply_names[i];
3516 ret = devm_regulator_bulk_get(&i2c->dev,
3517 ARRAY_SIZE(rt5663->supplies),
3520 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3524 /* Set load for regulator. */
3525 for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
3526 ret = regulator_set_load(rt5663->supplies[i].consumer,
3527 RT5663_SUPPLY_CURRENT_UA);
3530 "Failed to set regulator load on %s, ret: %d\n",
3531 rt5663->supplies[i].supply, ret);
3536 ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
3540 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3543 msleep(RT5663_POWER_ON_DELAY_MS);
3545 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3546 if (IS_ERR(regmap)) {
3547 ret = PTR_ERR(regmap);
3548 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3553 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3554 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3556 "Device with ID register %#x is not rt5663, retry one time.\n",
3559 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3563 case RT5663_DEVICE_ID_2:
3564 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3565 rt5663->codec_ver = CODEC_VER_1;
3567 case RT5663_DEVICE_ID_1:
3568 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3569 rt5663->codec_ver = CODEC_VER_0;
3573 "Device with ID register %#x is not rt5663\n",
3579 if (IS_ERR(rt5663->regmap)) {
3580 ret = PTR_ERR(rt5663->regmap);
3581 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3586 /* reset and calibrate */
3587 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3588 regcache_cache_bypass(rt5663->regmap, true);
3589 switch (rt5663->codec_ver) {
3591 rt5663_v2_calibrate(rt5663);
3594 rt5663_calibrate(rt5663);
3597 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3599 regcache_cache_bypass(rt5663->regmap, false);
3600 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3601 dev_dbg(&i2c->dev, "calibrate done\n");
3603 switch (rt5663->codec_ver) {
3607 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3608 ARRAY_SIZE(rt5663_patch_list));
3611 "Failed to apply regmap patch: %d\n", ret);
3614 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3618 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3619 RT5663_GP1_PIN_IRQ);
3620 /* 4btn inline command debounce */
3621 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3622 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3624 switch (rt5663->codec_ver) {
3626 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3628 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3629 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3630 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3631 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3632 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3633 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3634 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3636 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3637 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3638 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3639 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3640 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3641 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3642 /* Set GPIO4 and GPIO8 as input for combo jack */
3643 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3644 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3645 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3646 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3647 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3648 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3649 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3652 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3653 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3654 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3655 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3656 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3657 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3658 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3659 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3660 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3661 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3662 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3663 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3664 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3665 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3666 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3667 RT5663_DATA_SWAP_ADCDAT1_MASK,
3668 RT5663_DATA_SWAP_ADCDAT1_LL);
3671 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3674 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3675 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3678 ret = request_irq(i2c->irq, rt5663_irq,
3679 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3680 | IRQF_ONESHOT, "rt5663", rt5663);
3682 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3688 ret = devm_snd_soc_register_component(&i2c->dev,
3689 &soc_component_dev_rt5663,
3690 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3699 * Error after enabling regulators should goto err_enable
3700 * to disable regulators.
3704 free_irq(i2c->irq, rt5663);
3706 regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3710 static int rt5663_i2c_remove(struct i2c_client *i2c)
3712 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3715 free_irq(i2c->irq, rt5663);
3717 regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
3722 static void rt5663_i2c_shutdown(struct i2c_client *client)
3724 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3726 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3729 static struct i2c_driver rt5663_i2c_driver = {
3732 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3733 .of_match_table = of_match_ptr(rt5663_of_match),
3735 .probe = rt5663_i2c_probe,
3736 .remove = rt5663_i2c_remove,
3737 .shutdown = rt5663_i2c_shutdown,
3738 .id_table = rt5663_i2c_id,
3740 module_i2c_driver(rt5663_i2c_driver);
3742 MODULE_DESCRIPTION("ASoC RT5663 driver");
3743 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3744 MODULE_LICENSE("GPL v2");
git.samba.org / sfrench / cifs-2.6.git / blob