sound/soc/codecs/rt286.c

   1 /*
   2  * rt286.c  --  RT286 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2013 Realtek Semiconductor Corp.
   5  * Author: Bard Liao <bardliao@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/dmi.h>
  21 #include <linux/acpi.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/jack.h>
  30 #include <linux/workqueue.h>
  31 #include <sound/rt286.h>
  32 #include <sound/hda_verbs.h>
  33
  34 #include "rt286.h"
  35
  36 #define RT286_VENDOR_ID 0x10ec0286
  37 #define RT288_VENDOR_ID 0x10ec0288
  38
  39 struct rt286_priv {
  40         struct regmap *regmap;
  41         struct snd_soc_codec *codec;
  42         struct rt286_platform_data pdata;
  43         struct i2c_client *i2c;
  44         struct snd_soc_jack *jack;
  45         struct delayed_work jack_detect_work;
  46         int sys_clk;
  47         int clk_id;
  48         struct reg_default *index_cache;
  49 };
  50
  51 static struct reg_default rt286_index_def[] = {
  52         { 0x01, 0xaaaa },
  53         { 0x02, 0x8aaa },
  54         { 0x03, 0x0002 },
  55         { 0x04, 0xaf01 },
  56         { 0x08, 0x000d },
  57         { 0x09, 0xd810 },
  58         { 0x0a, 0x0120 },
  59         { 0x0b, 0x0000 },
  60         { 0x0d, 0x2800 },
  61         { 0x0f, 0x0000 },
  62         { 0x19, 0x0a17 },
  63         { 0x20, 0x0020 },
  64         { 0x33, 0x0208 },
  65         { 0x49, 0x0004 },
  66         { 0x4f, 0x50e9 },
  67         { 0x50, 0x2000 },
  68         { 0x63, 0x2902 },
  69         { 0x67, 0x1111 },
  70         { 0x68, 0x1016 },
  71         { 0x69, 0x273f },
  72 };
  73 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  74
  75 static const struct reg_default rt286_reg[] = {
  76         { 0x00170500, 0x00000400 },
  77         { 0x00220000, 0x00000031 },
  78         { 0x00239000, 0x0000007f },
  79         { 0x0023a000, 0x0000007f },
  80         { 0x00270500, 0x00000400 },
  81         { 0x00370500, 0x00000400 },
  82         { 0x00870500, 0x00000400 },
  83         { 0x00920000, 0x00000031 },
  84         { 0x00935000, 0x000000c3 },
  85         { 0x00936000, 0x000000c3 },
  86         { 0x00970500, 0x00000400 },
  87         { 0x00b37000, 0x00000097 },
  88         { 0x00b37200, 0x00000097 },
  89         { 0x00b37300, 0x00000097 },
  90         { 0x00c37000, 0x00000000 },
  91         { 0x00c37100, 0x00000080 },
  92         { 0x01270500, 0x00000400 },
  93         { 0x01370500, 0x00000400 },
  94         { 0x01371f00, 0x411111f0 },
  95         { 0x01439000, 0x00000080 },
  96         { 0x0143a000, 0x00000080 },
  97         { 0x01470700, 0x00000000 },
  98         { 0x01470500, 0x00000400 },
  99         { 0x01470c00, 0x00000000 },
 100         { 0x01470100, 0x00000000 },
 101         { 0x01837000, 0x00000000 },
 102         { 0x01870500, 0x00000400 },
 103         { 0x02050000, 0x00000000 },
 104         { 0x02139000, 0x00000080 },
 105         { 0x0213a000, 0x00000080 },
 106         { 0x02170100, 0x00000000 },
 107         { 0x02170500, 0x00000400 },
 108         { 0x02170700, 0x00000000 },
 109         { 0x02270100, 0x00000000 },
 110         { 0x02370100, 0x00000000 },
 111         { 0x01870700, 0x00000020 },
 112         { 0x00830000, 0x000000c3 },
 113         { 0x00930000, 0x000000c3 },
 114         { 0x01270700, 0x00000000 },
 115 };
 116
 117 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
 118 {
 119         switch (reg) {
 120         case 0 ... 0xff:
 121         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 122         case RT286_GET_HP_SENSE:
 123         case RT286_GET_MIC1_SENSE:
 124         case RT286_PROC_COEF:
 125                 return true;
 126         default:
 127                 return false;
 128         }
 129
 130
 131 }
 132
 133 static bool rt286_readable_register(struct device *dev, unsigned int reg)
 134 {
 135         switch (reg) {
 136         case 0 ... 0xff:
 137         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 138         case RT286_GET_HP_SENSE:
 139         case RT286_GET_MIC1_SENSE:
 140         case RT286_SET_AUDIO_POWER:
 141         case RT286_SET_HPO_POWER:
 142         case RT286_SET_SPK_POWER:
 143         case RT286_SET_DMIC1_POWER:
 144         case RT286_SPK_MUX:
 145         case RT286_HPO_MUX:
 146         case RT286_ADC0_MUX:
 147         case RT286_ADC1_MUX:
 148         case RT286_SET_MIC1:
 149         case RT286_SET_PIN_HPO:
 150         case RT286_SET_PIN_SPK:
 151         case RT286_SET_PIN_DMIC1:
 152         case RT286_SPK_EAPD:
 153         case RT286_SET_AMP_GAIN_HPO:
 154         case RT286_SET_DMIC2_DEFAULT:
 155         case RT286_DACL_GAIN:
 156         case RT286_DACR_GAIN:
 157         case RT286_ADCL_GAIN:
 158         case RT286_ADCR_GAIN:
 159         case RT286_MIC_GAIN:
 160         case RT286_SPOL_GAIN:
 161         case RT286_SPOR_GAIN:
 162         case RT286_HPOL_GAIN:
 163         case RT286_HPOR_GAIN:
 164         case RT286_F_DAC_SWITCH:
 165         case RT286_F_RECMIX_SWITCH:
 166         case RT286_REC_MIC_SWITCH:
 167         case RT286_REC_I2S_SWITCH:
 168         case RT286_REC_LINE_SWITCH:
 169         case RT286_REC_BEEP_SWITCH:
 170         case RT286_DAC_FORMAT:
 171         case RT286_ADC_FORMAT:
 172         case RT286_COEF_INDEX:
 173         case RT286_PROC_COEF:
 174         case RT286_SET_AMP_GAIN_ADC_IN1:
 175         case RT286_SET_AMP_GAIN_ADC_IN2:
 176         case RT286_SET_POWER(RT286_DAC_OUT1):
 177         case RT286_SET_POWER(RT286_DAC_OUT2):
 178         case RT286_SET_POWER(RT286_ADC_IN1):
 179         case RT286_SET_POWER(RT286_ADC_IN2):
 180         case RT286_SET_POWER(RT286_DMIC2):
 181         case RT286_SET_POWER(RT286_MIC1):
 182                 return true;
 183         default:
 184                 return false;
 185         }
 186 }
 187
 188 static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
 189 {
 190         struct i2c_client *client = context;
 191         struct rt286_priv *rt286 = i2c_get_clientdata(client);
 192         u8 data[4];
 193         int ret, i;
 194
 195         /* handle index registers */
 196         if (reg <= 0xff) {
 197                 rt286_hw_write(client, RT286_COEF_INDEX, reg);
 198                 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
 199                         if (reg == rt286->index_cache[i].reg) {
 200                                 rt286->index_cache[i].def = value;
 201                                 break;
 202                         }
 203
 204                 }
 205                 reg = RT286_PROC_COEF;
 206         }
 207
 208         data[0] = (reg >> 24) & 0xff;
 209         data[1] = (reg >> 16) & 0xff;
 210         /*
 211          * 4 bit VID: reg should be 0
 212          * 12 bit VID: value should be 0
 213          * So we use an OR operator to handle it rather than use if condition.
 214          */
 215         data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
 216         data[3] = value & 0xff;
 217
 218         ret = i2c_master_send(client, data, 4);
 219
 220         if (ret == 4)
 221                 return 0;
 222         else
 223                 pr_err("ret=%d\n", ret);
 224         if (ret < 0)
 225                 return ret;
 226         else
 227                 return -EIO;
 228 }
 229
 230 static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
 231 {
 232         struct i2c_client *client = context;
 233         struct i2c_msg xfer[2];
 234         int ret;
 235         __be32 be_reg;
 236         unsigned int index, vid, buf = 0x0;
 237
 238         /* handle index registers */
 239         if (reg <= 0xff) {
 240                 rt286_hw_write(client, RT286_COEF_INDEX, reg);
 241                 reg = RT286_PROC_COEF;
 242         }
 243
 244         reg = reg | 0x80000;
 245         vid = (reg >> 8) & 0xfff;
 246
 247         if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
 248                 index = (reg >> 8) & 0xf;
 249                 reg = (reg & ~0xf0f) | index;
 250         }
 251         be_reg = cpu_to_be32(reg);
 252
 253         /* Write register */
 254         xfer[0].addr = client->addr;
 255         xfer[0].flags = 0;
 256         xfer[0].len = 4;
 257         xfer[0].buf = (u8 *)&be_reg;
 258
 259         /* Read data */
 260         xfer[1].addr = client->addr;
 261         xfer[1].flags = I2C_M_RD;
 262         xfer[1].len = 4;
 263         xfer[1].buf = (u8 *)&buf;
 264
 265         ret = i2c_transfer(client->adapter, xfer, 2);
 266         if (ret < 0)
 267                 return ret;
 268         else if (ret != 2)
 269                 return -EIO;
 270
 271         *value = be32_to_cpu(buf);
 272
 273         return 0;
 274 }
 275
 276 #ifdef CONFIG_PM
 277 static void rt286_index_sync(struct snd_soc_codec *codec)
 278 {
 279         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 280         int i;
 281
 282         for (i = 0; i < INDEX_CACHE_SIZE; i++) {
 283                 snd_soc_write(codec, rt286->index_cache[i].reg,
 284                                   rt286->index_cache[i].def);
 285         }
 286 }
 287 #endif
 288
 289 static int rt286_support_power_controls[] = {
 290         RT286_DAC_OUT1,
 291         RT286_DAC_OUT2,
 292         RT286_ADC_IN1,
 293         RT286_ADC_IN2,
 294         RT286_MIC1,
 295         RT286_DMIC1,
 296         RT286_DMIC2,
 297         RT286_SPK_OUT,
 298         RT286_HP_OUT,
 299 };
 300 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
 301
 302 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
 303 {
 304         unsigned int val, buf;
 305
 306         *hp = false;
 307         *mic = false;
 308
 309         if (!rt286->codec)
 310                 return -EINVAL;
 311         if (rt286->pdata.cbj_en) {
 312                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 313                 *hp = buf & 0x80000000;
 314                 if (*hp) {
 315                         /* power on HV,VERF */
 316                         regmap_update_bits(rt286->regmap,
 317                                 RT286_DC_GAIN, 0x200, 0x200);
 318
 319                         snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
 320                                                         "HV");
 321                         snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
 322                                                         "VREF");
 323                         /* power LDO1 */
 324                         snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
 325                                                         "LDO1");
 326                         snd_soc_dapm_sync(&rt286->codec->dapm);
 327
 328                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
 329                         msleep(50);
 330
 331                         regmap_update_bits(rt286->regmap,
 332                                 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
 333                         msleep(300);
 334                         regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
 335
 336                         if (0x0070 == (val & 0x0070)) {
 337                                 *mic = true;
 338                         } else {
 339                                 regmap_update_bits(rt286->regmap,
 340                                         RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
 341                                 msleep(300);
 342                                 regmap_read(rt286->regmap,
 343                                         RT286_CBJ_CTRL2, &val);
 344                                 if (0x0070 == (val & 0x0070))
 345                                         *mic = true;
 346                                 else
 347                                         *mic = false;
 348                         }
 349                         regmap_update_bits(rt286->regmap,
 350                                 RT286_DC_GAIN, 0x200, 0x0);
 351
 352                 } else {
 353                         *mic = false;
 354                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
 355                 }
 356         } else {
 357                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 358                 *hp = buf & 0x80000000;
 359                 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
 360                 *mic = buf & 0x80000000;
 361         }
 362
 363         snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
 364         snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
 365         if (!*hp)
 366                 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
 367         snd_soc_dapm_sync(&rt286->codec->dapm);
 368
 369         return 0;
 370 }
 371
 372 static void rt286_jack_detect_work(struct work_struct *work)
 373 {
 374         struct rt286_priv *rt286 =
 375                 container_of(work, struct rt286_priv, jack_detect_work.work);
 376         int status = 0;
 377         bool hp = false;
 378         bool mic = false;
 379
 380         rt286_jack_detect(rt286, &hp, &mic);
 381
 382         if (hp == true)
 383                 status |= SND_JACK_HEADPHONE;
 384
 385         if (mic == true)
 386                 status |= SND_JACK_MICROPHONE;
 387
 388         snd_soc_jack_report(rt286->jack, status,
 389                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 390 }
 391
 392 int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
 393 {
 394         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 395
 396         rt286->jack = jack;
 397
 398         /* Send an initial empty report */
 399         snd_soc_jack_report(rt286->jack, 0,
 400                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 401
 402         return 0;
 403 }
 404 EXPORT_SYMBOL_GPL(rt286_mic_detect);
 405
 406 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
 407                          struct snd_soc_dapm_widget *sink)
 408 {
 409         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 410         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 411
 412         if (rt286->clk_id == RT286_SCLK_S_MCLK)
 413                 return 1;
 414         else
 415                 return 0;
 416 }
 417
 418 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
 419 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
 420
 421 static const struct snd_kcontrol_new rt286_snd_controls[] = {
 422         SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
 423                             RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 424         SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
 425                             RT286_ADCR_GAIN, 7, 1, 1),
 426         SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
 427                             RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 428         SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
 429                             0, 0x3, 0, mic_vol_tlv),
 430         SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
 431                             RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
 432 };
 433
 434 /* Digital Mixer */
 435 static const struct snd_kcontrol_new rt286_front_mix[] = {
 436         SOC_DAPM_SINGLE("DAC Switch",  RT286_F_DAC_SWITCH,
 437                         RT286_MUTE_SFT, 1, 1),
 438         SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
 439                         RT286_MUTE_SFT, 1, 1),
 440 };
 441
 442 /* Analog Input Mixer */
 443 static const struct snd_kcontrol_new rt286_rec_mix[] = {
 444         SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
 445                         RT286_MUTE_SFT, 1, 1),
 446         SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
 447                         RT286_MUTE_SFT, 1, 1),
 448         SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
 449                         RT286_MUTE_SFT, 1, 1),
 450         SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
 451                         RT286_MUTE_SFT, 1, 1),
 452 };
 453
 454 static const struct snd_kcontrol_new spo_enable_control =
 455         SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
 456                         RT286_SET_PIN_SFT, 1, 0);
 457
 458 static const struct snd_kcontrol_new hpol_enable_control =
 459         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
 460                         RT286_MUTE_SFT, 1, 1);
 461
 462 static const struct snd_kcontrol_new hpor_enable_control =
 463         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
 464                         RT286_MUTE_SFT, 1, 1);
 465
 466 /* ADC0 source */
 467 static const char * const rt286_adc_src[] = {
 468         "Mic", "RECMIX", "Dmic"
 469 };
 470
 471 static const int rt286_adc_values[] = {
 472         0, 4, 5,
 473 };
 474
 475 static SOC_VALUE_ENUM_SINGLE_DECL(
 476         rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
 477         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 478
 479 static const struct snd_kcontrol_new rt286_adc0_mux =
 480         SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
 481
 482 static SOC_VALUE_ENUM_SINGLE_DECL(
 483         rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
 484         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 485
 486 static const struct snd_kcontrol_new rt286_adc1_mux =
 487         SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
 488
 489 static const char * const rt286_dac_src[] = {
 490         "Front", "Surround"
 491 };
 492 /* HP-OUT source */
 493 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
 494                                 0, rt286_dac_src);
 495
 496 static const struct snd_kcontrol_new rt286_hpo_mux =
 497 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
 498
 499 /* SPK-OUT source */
 500 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
 501                                 0, rt286_dac_src);
 502
 503 static const struct snd_kcontrol_new rt286_spo_mux =
 504 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
 505
 506 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
 507                             struct snd_kcontrol *kcontrol, int event)
 508 {
 509         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 510
 511         switch (event) {
 512         case SND_SOC_DAPM_POST_PMU:
 513                 snd_soc_write(codec,
 514                         RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
 515                 break;
 516         case SND_SOC_DAPM_PRE_PMD:
 517                 snd_soc_write(codec,
 518                         RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
 519                 break;
 520
 521         default:
 522                 return 0;
 523         }
 524
 525         return 0;
 526 }
 527
 528 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
 529                                   struct snd_kcontrol *kcontrol, int event)
 530 {
 531         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 532
 533         switch (event) {
 534         case SND_SOC_DAPM_POST_PMU:
 535                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
 536                 break;
 537         case SND_SOC_DAPM_PRE_PMD:
 538                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
 539                 break;
 540         default:
 541                 return 0;
 542         }
 543
 544         return 0;
 545 }
 546
 547 static int rt286_vref_event(struct snd_soc_dapm_widget *w,
 548                              struct snd_kcontrol *kcontrol, int event)
 549 {
 550         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 551
 552         switch (event) {
 553         case SND_SOC_DAPM_PRE_PMU:
 554                 snd_soc_update_bits(codec,
 555                         RT286_CBJ_CTRL1, 0x0400, 0x0000);
 556                 mdelay(50);
 557                 break;
 558         default:
 559                 return 0;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
 566                              struct snd_kcontrol *kcontrol, int event)
 567 {
 568         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 569
 570         switch (event) {
 571         case SND_SOC_DAPM_POST_PMU:
 572                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
 573                 break;
 574         case SND_SOC_DAPM_PRE_PMD:
 575                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
 576                 break;
 577         default:
 578                 return 0;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
 585                              struct snd_kcontrol *kcontrol, int event)
 586 {
 587         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 588
 589         switch (event) {
 590         case SND_SOC_DAPM_PRE_PMU:
 591                 snd_soc_update_bits(codec,
 592                         RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
 593                 snd_soc_update_bits(codec,
 594                         RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
 595                 break;
 596         case SND_SOC_DAPM_POST_PMD:
 597                 snd_soc_update_bits(codec,
 598                         RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
 599                 snd_soc_update_bits(codec,
 600                         RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
 601                 break;
 602         default:
 603                 return 0;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
 610         SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
 611                 12, 1, NULL, 0),
 612         SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
 613                 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
 614         SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
 615                 2, 0, NULL, 0),
 616         SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
 617                 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
 618                 SND_SOC_DAPM_POST_PMU),
 619         SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
 620                 5, 0, NULL, 0),
 621         SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
 622                 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
 623                 SND_SOC_DAPM_POST_PMD),
 624
 625         /* Input Lines */
 626         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
 627         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
 628         SND_SOC_DAPM_INPUT("MIC1"),
 629         SND_SOC_DAPM_INPUT("LINE1"),
 630         SND_SOC_DAPM_INPUT("Beep"),
 631
 632         /* DMIC */
 633         SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
 634                 NULL, 0, rt286_set_dmic1_event,
 635                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 636         SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
 637                 NULL, 0),
 638         SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
 639                 0, 0, NULL, 0),
 640
 641         /* REC Mixer */
 642         SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
 643                 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
 644
 645         /* ADCs */
 646         SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
 647         SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
 648
 649         /* ADC Mux */
 650         SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
 651                 &rt286_adc0_mux),
 652         SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
 653                 &rt286_adc1_mux),
 654
 655         /* Audio Interface */
 656         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 657         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 658         SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
 659         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
 660
 661         /* Output Side */
 662         /* DACs */
 663         SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
 664         SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
 665
 666         /* Output Mux */
 667         SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
 668         SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
 669
 670         SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
 671                 RT286_SET_PIN_SFT, 0, NULL, 0),
 672
 673         /* Output Mixer */
 674         SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
 675                         rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
 676         SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
 677                         NULL, 0),
 678
 679         /* Output Pga */
 680         SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
 681                 &spo_enable_control, rt286_spk_event,
 682                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 683         SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
 684                 &hpol_enable_control),
 685         SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
 686                 &hpor_enable_control),
 687
 688         /* Output Lines */
 689         SND_SOC_DAPM_OUTPUT("SPOL"),
 690         SND_SOC_DAPM_OUTPUT("SPOR"),
 691         SND_SOC_DAPM_OUTPUT("HPO Pin"),
 692         SND_SOC_DAPM_OUTPUT("SPDIF"),
 693 };
 694
 695 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
 696         {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
 697         {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
 698         {"Front", NULL, "MCLK MODE", is_mclk_mode},
 699         {"Surround", NULL, "MCLK MODE", is_mclk_mode},
 700
 701         {"HP Power", NULL, "LDO1"},
 702         {"HP Power", NULL, "LDO2"},
 703
 704         {"MIC1", NULL, "LDO1"},
 705         {"MIC1", NULL, "LDO2"},
 706         {"MIC1", NULL, "HV"},
 707         {"MIC1", NULL, "VREF"},
 708         {"MIC1", NULL, "MIC1 Input Buffer"},
 709
 710         {"SPO", NULL, "LDO1"},
 711         {"SPO", NULL, "LDO2"},
 712         {"SPO", NULL, "HV"},
 713         {"SPO", NULL, "VREF"},
 714
 715         {"DMIC1", NULL, "DMIC1 Pin"},
 716         {"DMIC2", NULL, "DMIC2 Pin"},
 717         {"DMIC1", NULL, "DMIC Receiver"},
 718         {"DMIC2", NULL, "DMIC Receiver"},
 719
 720         {"RECMIX", "Beep Switch", "Beep"},
 721         {"RECMIX", "Line1 Switch", "LINE1"},
 722         {"RECMIX", "Mic1 Switch", "MIC1"},
 723
 724         {"ADC 0 Mux", "Dmic", "DMIC1"},
 725         {"ADC 0 Mux", "RECMIX", "RECMIX"},
 726         {"ADC 0 Mux", "Mic", "MIC1"},
 727         {"ADC 1 Mux", "Dmic", "DMIC2"},
 728         {"ADC 1 Mux", "RECMIX", "RECMIX"},
 729         {"ADC 1 Mux", "Mic", "MIC1"},
 730
 731         {"ADC 0", NULL, "ADC 0 Mux"},
 732         {"ADC 1", NULL, "ADC 1 Mux"},
 733
 734         {"AIF1TX", NULL, "ADC 0"},
 735         {"AIF2TX", NULL, "ADC 1"},
 736
 737         {"DAC 0", NULL, "AIF1RX"},
 738         {"DAC 1", NULL, "AIF2RX"},
 739
 740         {"Front", "DAC Switch", "DAC 0"},
 741         {"Front", "RECMIX Switch", "RECMIX"},
 742
 743         {"Surround", NULL, "DAC 1"},
 744
 745         {"SPK Mux", "Front", "Front"},
 746         {"SPK Mux", "Surround", "Surround"},
 747
 748         {"HPO Mux", "Front", "Front"},
 749         {"HPO Mux", "Surround", "Surround"},
 750
 751         {"SPO", "Switch", "SPK Mux"},
 752         {"HPO L", "Switch", "HPO Mux"},
 753         {"HPO R", "Switch", "HPO Mux"},
 754         {"HPO L", NULL, "HP Power"},
 755         {"HPO R", NULL, "HP Power"},
 756
 757         {"SPOL", NULL, "SPO"},
 758         {"SPOR", NULL, "SPO"},
 759         {"HPO Pin", NULL, "HPO L"},
 760         {"HPO Pin", NULL, "HPO R"},
 761 };
 762
 763 static int rt286_hw_params(struct snd_pcm_substream *substream,
 764                             struct snd_pcm_hw_params *params,
 765                             struct snd_soc_dai *dai)
 766 {
 767         struct snd_soc_codec *codec = dai->codec;
 768         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 769         unsigned int val = 0;
 770         int d_len_code;
 771
 772         switch (params_rate(params)) {
 773         /* bit 14 0:48K 1:44.1K */
 774         case 44100:
 775                 val |= 0x4000;
 776                 break;
 777         case 48000:
 778                 break;
 779         default:
 780                 dev_err(codec->dev, "Unsupported sample rate %d\n",
 781                                         params_rate(params));
 782                 return -EINVAL;
 783         }
 784         switch (rt286->sys_clk) {
 785         case 12288000:
 786         case 24576000:
 787                 if (params_rate(params) != 48000) {
 788                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 789                                         params_rate(params), rt286->sys_clk);
 790                         return -EINVAL;
 791                 }
 792                 break;
 793         case 11289600:
 794         case 22579200:
 795                 if (params_rate(params) != 44100) {
 796                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 797                                         params_rate(params), rt286->sys_clk);
 798                         return -EINVAL;
 799                 }
 800                 break;
 801         }
 802
 803         if (params_channels(params) <= 16) {
 804                 /* bit 3:0 Number of Channel */
 805                 val |= (params_channels(params) - 1);
 806         } else {
 807                 dev_err(codec->dev, "Unsupported channels %d\n",
 808                                         params_channels(params));
 809                 return -EINVAL;
 810         }
 811
 812         d_len_code = 0;
 813         switch (params_width(params)) {
 814         /* bit 6:4 Bits per Sample */
 815         case 16:
 816                 d_len_code = 0;
 817                 val |= (0x1 << 4);
 818                 break;
 819         case 32:
 820                 d_len_code = 2;
 821                 val |= (0x4 << 4);
 822                 break;
 823         case 20:
 824                 d_len_code = 1;
 825                 val |= (0x2 << 4);
 826                 break;
 827         case 24:
 828                 d_len_code = 2;
 829                 val |= (0x3 << 4);
 830                 break;
 831         case 8:
 832                 d_len_code = 3;
 833                 break;
 834         default:
 835                 return -EINVAL;
 836         }
 837
 838         snd_soc_update_bits(codec,
 839                 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
 840         dev_dbg(codec->dev, "format val = 0x%x\n", val);
 841
 842         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
 843         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
 844
 845         return 0;
 846 }
 847
 848 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 849 {
 850         struct snd_soc_codec *codec = dai->codec;
 851
 852         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 853         case SND_SOC_DAIFMT_CBM_CFM:
 854                 snd_soc_update_bits(codec,
 855                         RT286_I2S_CTRL1, 0x800, 0x800);
 856                 break;
 857         case SND_SOC_DAIFMT_CBS_CFS:
 858                 snd_soc_update_bits(codec,
 859                         RT286_I2S_CTRL1, 0x800, 0x0);
 860                 break;
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 866         case SND_SOC_DAIFMT_I2S:
 867                 snd_soc_update_bits(codec,
 868                         RT286_I2S_CTRL1, 0x300, 0x0);
 869                 break;
 870         case SND_SOC_DAIFMT_LEFT_J:
 871                 snd_soc_update_bits(codec,
 872                         RT286_I2S_CTRL1, 0x300, 0x1 << 8);
 873                 break;
 874         case SND_SOC_DAIFMT_DSP_A:
 875                 snd_soc_update_bits(codec,
 876                         RT286_I2S_CTRL1, 0x300, 0x2 << 8);
 877                 break;
 878         case SND_SOC_DAIFMT_DSP_B:
 879                 snd_soc_update_bits(codec,
 880                         RT286_I2S_CTRL1, 0x300, 0x3 << 8);
 881                 break;
 882         default:
 883                 return -EINVAL;
 884         }
 885         /* bit 15 Stream Type 0:PCM 1:Non-PCM */
 886         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
 887         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
 888
 889         return 0;
 890 }
 891
 892 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
 893                                 int clk_id, unsigned int freq, int dir)
 894 {
 895         struct snd_soc_codec *codec = dai->codec;
 896         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 897
 898         dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
 899
 900         if (RT286_SCLK_S_MCLK == clk_id) {
 901                 snd_soc_update_bits(codec,
 902                         RT286_I2S_CTRL2, 0x0100, 0x0);
 903                 snd_soc_update_bits(codec,
 904                         RT286_PLL_CTRL1, 0x20, 0x20);
 905         } else {
 906                 snd_soc_update_bits(codec,
 907                         RT286_I2S_CTRL2, 0x0100, 0x0100);
 908                 snd_soc_update_bits(codec,
 909                         RT286_PLL_CTRL, 0x4, 0x4);
 910                 snd_soc_update_bits(codec,
 911                         RT286_PLL_CTRL1, 0x20, 0x0);
 912         }
 913
 914         switch (freq) {
 915         case 19200000:
 916                 if (RT286_SCLK_S_MCLK == clk_id) {
 917                         dev_err(codec->dev, "Should not use MCLK\n");
 918                         return -EINVAL;
 919                 }
 920                 snd_soc_update_bits(codec,
 921                         RT286_I2S_CTRL2, 0x40, 0x40);
 922                 break;
 923         case 24000000:
 924                 if (RT286_SCLK_S_MCLK == clk_id) {
 925                         dev_err(codec->dev, "Should not use MCLK\n");
 926                         return -EINVAL;
 927                 }
 928                 snd_soc_update_bits(codec,
 929                         RT286_I2S_CTRL2, 0x40, 0x0);
 930                 break;
 931         case 12288000:
 932         case 11289600:
 933                 snd_soc_update_bits(codec,
 934                         RT286_I2S_CTRL2, 0x8, 0x0);
 935                 snd_soc_update_bits(codec,
 936                         RT286_CLK_DIV, 0xfc1e, 0x0004);
 937                 break;
 938         case 24576000:
 939         case 22579200:
 940                 snd_soc_update_bits(codec,
 941                         RT286_I2S_CTRL2, 0x8, 0x8);
 942                 snd_soc_update_bits(codec,
 943                         RT286_CLK_DIV, 0xfc1e, 0x5406);
 944                 break;
 945         default:
 946                 dev_err(codec->dev, "Unsupported system clock\n");
 947                 return -EINVAL;
 948         }
 949
 950         rt286->sys_clk = freq;
 951         rt286->clk_id = clk_id;
 952
 953         return 0;
 954 }
 955
 956 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
 957 {
 958         struct snd_soc_codec *codec = dai->codec;
 959
 960         dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
 961         if (50 == ratio)
 962                 snd_soc_update_bits(codec,
 963                         RT286_I2S_CTRL1, 0x1000, 0x1000);
 964         else
 965                 snd_soc_update_bits(codec,
 966                         RT286_I2S_CTRL1, 0x1000, 0x0);
 967
 968
 969         return 0;
 970 }
 971
 972 static int rt286_set_bias_level(struct snd_soc_codec *codec,
 973                                  enum snd_soc_bias_level level)
 974 {
 975         switch (level) {
 976         case SND_SOC_BIAS_PREPARE:
 977                 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
 978                         snd_soc_write(codec,
 979                                 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
 980                         snd_soc_update_bits(codec,
 981                                 RT286_DC_GAIN, 0x200, 0x200);
 982                 }
 983                 break;
 984
 985         case SND_SOC_BIAS_ON:
 986                 mdelay(10);
 987                 snd_soc_update_bits(codec,
 988                         RT286_CBJ_CTRL1, 0x0400, 0x0400);
 989                 snd_soc_update_bits(codec,
 990                         RT286_DC_GAIN, 0x200, 0x0);
 991
 992                 break;
 993
 994         case SND_SOC_BIAS_STANDBY:
 995                 snd_soc_write(codec,
 996                         RT286_SET_AUDIO_POWER, AC_PWRST_D3);
 997                 snd_soc_update_bits(codec,
 998                         RT286_CBJ_CTRL1, 0x0400, 0x0000);
 999                 break;
1000
1001         default:
1002                 break;
1003         }
1004         codec->dapm.bias_level = level;
1005
1006         return 0;
1007 }
1008
1009 static irqreturn_t rt286_irq(int irq, void *data)
1010 {
1011         struct rt286_priv *rt286 = data;
1012         bool hp = false;
1013         bool mic = false;
1014         int status = 0;
1015
1016         rt286_jack_detect(rt286, &hp, &mic);
1017
1018         /* Clear IRQ */
1019         regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
1020
1021         if (hp == true)
1022                 status |= SND_JACK_HEADPHONE;
1023
1024         if (mic == true)
1025                 status |= SND_JACK_MICROPHONE;
1026
1027         snd_soc_jack_report(rt286->jack, status,
1028                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1029
1030         pm_wakeup_event(&rt286->i2c->dev, 300);
1031
1032         return IRQ_HANDLED;
1033 }
1034
1035 static int rt286_probe(struct snd_soc_codec *codec)
1036 {
1037         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1038
1039         rt286->codec = codec;
1040         codec->dapm.bias_level = SND_SOC_BIAS_OFF;
1041
1042         if (rt286->i2c->irq) {
1043                 regmap_update_bits(rt286->regmap,
1044                                         RT286_IRQ_CTRL, 0x2, 0x2);
1045
1046                 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1047                                         rt286_jack_detect_work);
1048                 schedule_delayed_work(&rt286->jack_detect_work,
1049                                         msecs_to_jiffies(1250));
1050         }
1051
1052         return 0;
1053 }
1054
1055 static int rt286_remove(struct snd_soc_codec *codec)
1056 {
1057         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1058
1059         cancel_delayed_work_sync(&rt286->jack_detect_work);
1060
1061         return 0;
1062 }
1063
1064 #ifdef CONFIG_PM
1065 static int rt286_suspend(struct snd_soc_codec *codec)
1066 {
1067         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1068
1069         regcache_cache_only(rt286->regmap, true);
1070         regcache_mark_dirty(rt286->regmap);
1071
1072         return 0;
1073 }
1074
1075 static int rt286_resume(struct snd_soc_codec *codec)
1076 {
1077         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1078
1079         regcache_cache_only(rt286->regmap, false);
1080         rt286_index_sync(codec);
1081         regcache_sync(rt286->regmap);
1082
1083         return 0;
1084 }
1085 #else
1086 #define rt286_suspend NULL
1087 #define rt286_resume NULL
1088 #endif
1089
1090 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1091 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1092                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1093
1094 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1095         .hw_params = rt286_hw_params,
1096         .set_fmt = rt286_set_dai_fmt,
1097         .set_sysclk = rt286_set_dai_sysclk,
1098         .set_bclk_ratio = rt286_set_bclk_ratio,
1099 };
1100
1101 static struct snd_soc_dai_driver rt286_dai[] = {
1102         {
1103                 .name = "rt286-aif1",
1104                 .id = RT286_AIF1,
1105                 .playback = {
1106                         .stream_name = "AIF1 Playback",
1107                         .channels_min = 1,
1108                         .channels_max = 2,
1109                         .rates = RT286_STEREO_RATES,
1110                         .formats = RT286_FORMATS,
1111                 },
1112                 .capture = {
1113                         .stream_name = "AIF1 Capture",
1114                         .channels_min = 1,
1115                         .channels_max = 2,
1116                         .rates = RT286_STEREO_RATES,
1117                         .formats = RT286_FORMATS,
1118                 },
1119                 .ops = &rt286_aif_dai_ops,
1120                 .symmetric_rates = 1,
1121         },
1122         {
1123                 .name = "rt286-aif2",
1124                 .id = RT286_AIF2,
1125                 .playback = {
1126                         .stream_name = "AIF2 Playback",
1127                         .channels_min = 1,
1128                         .channels_max = 2,
1129                         .rates = RT286_STEREO_RATES,
1130                         .formats = RT286_FORMATS,
1131                 },
1132                 .capture = {
1133                         .stream_name = "AIF2 Capture",
1134                         .channels_min = 1,
1135                         .channels_max = 2,
1136                         .rates = RT286_STEREO_RATES,
1137                         .formats = RT286_FORMATS,
1138                 },
1139                 .ops = &rt286_aif_dai_ops,
1140                 .symmetric_rates = 1,
1141         },
1142
1143 };
1144
1145 static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1146         .probe = rt286_probe,
1147         .remove = rt286_remove,
1148         .suspend = rt286_suspend,
1149         .resume = rt286_resume,
1150         .set_bias_level = rt286_set_bias_level,
1151         .idle_bias_off = true,
1152         .controls = rt286_snd_controls,
1153         .num_controls = ARRAY_SIZE(rt286_snd_controls),
1154         .dapm_widgets = rt286_dapm_widgets,
1155         .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1156         .dapm_routes = rt286_dapm_routes,
1157         .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1158 };
1159
1160 static const struct regmap_config rt286_regmap = {
1161         .reg_bits = 32,
1162         .val_bits = 32,
1163         .max_register = 0x02370100,
1164         .volatile_reg = rt286_volatile_register,
1165         .readable_reg = rt286_readable_register,
1166         .reg_write = rt286_hw_write,
1167         .reg_read = rt286_hw_read,
1168         .cache_type = REGCACHE_RBTREE,
1169         .reg_defaults = rt286_reg,
1170         .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1171 };
1172
1173 static const struct i2c_device_id rt286_i2c_id[] = {
1174         {"rt286", 0},
1175         {"rt288", 0},
1176         {}
1177 };
1178 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1179
1180 static const struct acpi_device_id rt286_acpi_match[] = {
1181         { "INT343A", 0 },
1182         {},
1183 };
1184 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1185
1186 static struct dmi_system_id force_combo_jack_table[] = {
1187         {
1188                 .ident = "Intel Wilson Beach",
1189                 .matches = {
1190                         DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1191                 }
1192         },
1193         { }
1194 };
1195
1196 static struct dmi_system_id dmi_dell_dino[] = {
1197         {
1198                 .ident = "Dell Dino",
1199                 .matches = {
1200                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1201                         DMI_MATCH(DMI_BOARD_NAME, "0144P8")
1202                 }
1203         },
1204         { }
1205 };
1206
1207 static int rt286_i2c_probe(struct i2c_client *i2c,
1208                            const struct i2c_device_id *id)
1209 {
1210         struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1211         struct rt286_priv *rt286;
1212         int i, ret;
1213
1214         rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1215                                 GFP_KERNEL);
1216         if (NULL == rt286)
1217                 return -ENOMEM;
1218
1219         rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1220         if (IS_ERR(rt286->regmap)) {
1221                 ret = PTR_ERR(rt286->regmap);
1222                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1223                         ret);
1224                 return ret;
1225         }
1226
1227         regmap_read(rt286->regmap,
1228                 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1229         if (ret != RT286_VENDOR_ID && ret != RT288_VENDOR_ID) {
1230                 dev_err(&i2c->dev,
1231                         "Device with ID register %x is not rt286\n", ret);
1232                 return -ENODEV;
1233         }
1234
1235         rt286->index_cache = rt286_index_def;
1236         rt286->i2c = i2c;
1237         i2c_set_clientdata(i2c, rt286);
1238
1239         if (pdata)
1240                 rt286->pdata = *pdata;
1241
1242         if (dmi_check_system(force_combo_jack_table) ||
1243                 dmi_check_system(dmi_dell_dino))
1244                 rt286->pdata.cbj_en = true;
1245
1246         regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1247
1248         for (i = 0; i < RT286_POWER_REG_LEN; i++)
1249                 regmap_write(rt286->regmap,
1250                         RT286_SET_POWER(rt286_support_power_controls[i]),
1251                         AC_PWRST_D1);
1252
1253         if (!rt286->pdata.cbj_en) {
1254                 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1255                 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1256                 regmap_update_bits(rt286->regmap,
1257                                         RT286_CBJ_CTRL1, 0xf000, 0xb000);
1258         } else {
1259                 regmap_update_bits(rt286->regmap,
1260                                         RT286_CBJ_CTRL1, 0xf000, 0x5000);
1261         }
1262
1263         mdelay(10);
1264
1265         if (!rt286->pdata.gpio2_en)
1266                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1267         else
1268                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1269
1270         mdelay(10);
1271
1272         regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1273         /* Power down LDO, VREF */
1274         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1275         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1276
1277         /* Set depop parameter */
1278         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1279         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1280         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1281
1282         if (dmi_check_system(dmi_dell_dino)) {
1283                 regmap_update_bits(rt286->regmap,
1284                         RT286_SET_GPIO_MASK, 0x40, 0x40);
1285                 regmap_update_bits(rt286->regmap,
1286                         RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1287                 regmap_update_bits(rt286->regmap,
1288                         RT286_SET_GPIO_DATA, 0x40, 0x40);
1289                 regmap_update_bits(rt286->regmap,
1290                         RT286_GPIO_CTRL, 0xc, 0x8);
1291         }
1292
1293         if (rt286->i2c->irq) {
1294                 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1295                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1296                 if (ret != 0) {
1297                         dev_err(&i2c->dev,
1298                                 "Failed to reguest IRQ: %d\n", ret);
1299                         return ret;
1300                 }
1301         }
1302
1303         ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1304                                      rt286_dai, ARRAY_SIZE(rt286_dai));
1305
1306         return ret;
1307 }
1308
1309 static int rt286_i2c_remove(struct i2c_client *i2c)
1310 {
1311         struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1312
1313         if (i2c->irq)
1314                 free_irq(i2c->irq, rt286);
1315         snd_soc_unregister_codec(&i2c->dev);
1316
1317         return 0;
1318 }
1319
1320
1321 static struct i2c_driver rt286_i2c_driver = {
1322         .driver = {
1323                    .name = "rt286",
1324                    .owner = THIS_MODULE,
1325                    .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1326                    },
1327         .probe = rt286_i2c_probe,
1328         .remove = rt286_i2c_remove,
1329         .id_table = rt286_i2c_id,
1330 };
1331
1332 module_i2c_driver(rt286_i2c_driver);
1333
1334 MODULE_DESCRIPTION("ASoC RT286 driver");
1335 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1336 MODULE_LICENSE("GPL");