sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39
  40 #ifdef CONFIG_X86
  41 /* for snoop control */
  42 #include <asm/pgtable.h>
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dsp_driver = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dsp_driver, bool, 0444);
 164 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1)");
 166
 167 #ifdef CONFIG_PM
 168 static int param_set_xint(const char *val, const struct kernel_param *kp);
 169 static const struct kernel_param_ops param_ops_xint = {
 170         .set = param_set_xint,
 171         .get = param_get_int,
 172 };
 173 #define param_check_xint param_check_int
 174
 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 176 module_param(power_save, xint, 0644);
 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 178                  "(in second, 0 = disable).");
 179
 180 static bool pm_blacklist = true;
 181 module_param(pm_blacklist, bool, 0644);
 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 183
 184 /* reset the HD-audio controller in power save mode.
 185  * this may give more power-saving, but will take longer time to
 186  * wake up.
 187  */
 188 static bool power_save_controller = 1;
 189 module_param(power_save_controller, bool, 0644);
 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 191 #else
 192 #define power_save      0
 193 #endif /* CONFIG_PM */
 194
 195 static int align_buffer_size = -1;
 196 module_param(align_buffer_size, bint, 0644);
 197 MODULE_PARM_DESC(align_buffer_size,
 198                 "Force buffer and period sizes to be multiple of 128 bytes.");
 199
 200 #ifdef CONFIG_X86
 201 static int hda_snoop = -1;
 202 module_param_named(snoop, hda_snoop, bint, 0444);
 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 204 #else
 205 #define hda_snoop               true
 206 #endif
 207
 208
 209 MODULE_LICENSE("GPL");
 210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 211                          "{Intel, ICH6M},"
 212                          "{Intel, ICH7},"
 213                          "{Intel, ESB2},"
 214                          "{Intel, ICH8},"
 215                          "{Intel, ICH9},"
 216                          "{Intel, ICH10},"
 217                          "{Intel, PCH},"
 218                          "{Intel, CPT},"
 219                          "{Intel, PPT},"
 220                          "{Intel, LPT},"
 221                          "{Intel, LPT_LP},"
 222                          "{Intel, WPT_LP},"
 223                          "{Intel, SPT},"
 224                          "{Intel, SPT_LP},"
 225                          "{Intel, HPT},"
 226                          "{Intel, PBG},"
 227                          "{Intel, SCH},"
 228                          "{ATI, SB450},"
 229                          "{ATI, SB600},"
 230                          "{ATI, RS600},"
 231                          "{ATI, RS690},"
 232                          "{ATI, RS780},"
 233                          "{ATI, R600},"
 234                          "{ATI, RV630},"
 235                          "{ATI, RV610},"
 236                          "{ATI, RV670},"
 237                          "{ATI, RV635},"
 238                          "{ATI, RV620},"
 239                          "{ATI, RV770},"
 240                          "{VIA, VT8251},"
 241                          "{VIA, VT8237A},"
 242                          "{SiS, SIS966},"
 243                          "{ULI, M5461}}");
 244 MODULE_DESCRIPTION("Intel HDA driver");
 245
 246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 248 #define SUPPORT_VGA_SWITCHEROO
 249 #endif
 250 #endif
 251
 252
 253 /*
 254  */
 255
 256 /* driver types */
 257 enum {
 258         AZX_DRIVER_ICH,
 259         AZX_DRIVER_PCH,
 260         AZX_DRIVER_SCH,
 261         AZX_DRIVER_SKL,
 262         AZX_DRIVER_HDMI,
 263         AZX_DRIVER_ATI,
 264         AZX_DRIVER_ATIHDMI,
 265         AZX_DRIVER_ATIHDMI_NS,
 266         AZX_DRIVER_VIA,
 267         AZX_DRIVER_SIS,
 268         AZX_DRIVER_ULI,
 269         AZX_DRIVER_NVIDIA,
 270         AZX_DRIVER_TERA,
 271         AZX_DRIVER_CTX,
 272         AZX_DRIVER_CTHDA,
 273         AZX_DRIVER_CMEDIA,
 274         AZX_DRIVER_ZHAOXIN,
 275         AZX_DRIVER_GENERIC,
 276         AZX_NUM_DRIVERS, /* keep this as last entry */
 277 };
 278
 279 #define azx_get_snoop_type(chip) \
 280         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 281 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 282
 283 /* quirks for old Intel chipsets */
 284 #define AZX_DCAPS_INTEL_ICH \
 285         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 286
 287 /* quirks for Intel PCH */
 288 #define AZX_DCAPS_INTEL_PCH_BASE \
 289         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 290          AZX_DCAPS_SNOOP_TYPE(SCH))
 291
 292 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 293 #define AZX_DCAPS_INTEL_PCH_NOPM \
 294         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 295
 296 /* PCH for HSW/BDW; with runtime PM */
 297 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 298 #define AZX_DCAPS_INTEL_PCH \
 299         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 300
 301 /* HSW HDMI */
 302 #define AZX_DCAPS_INTEL_HASWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 308 #define AZX_DCAPS_INTEL_BROADWELL \
 309         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 310          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 311          AZX_DCAPS_SNOOP_TYPE(SCH))
 312
 313 #define AZX_DCAPS_INTEL_BAYTRAIL \
 314         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 315
 316 #define AZX_DCAPS_INTEL_BRASWELL \
 317         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 318          AZX_DCAPS_I915_COMPONENT)
 319
 320 #define AZX_DCAPS_INTEL_SKYLAKE \
 321         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 322          AZX_DCAPS_SYNC_WRITE |\
 323          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 324
 325 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 326
 327 /* quirks for ATI SB / AMD Hudson */
 328 #define AZX_DCAPS_PRESET_ATI_SB \
 329         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 330          AZX_DCAPS_SNOOP_TYPE(ATI))
 331
 332 /* quirks for ATI/AMD HDMI */
 333 #define AZX_DCAPS_PRESET_ATI_HDMI \
 334         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 335          AZX_DCAPS_NO_MSI64)
 336
 337 /* quirks for ATI HDMI with snoop off */
 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 339         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 340
 341 /* quirks for AMD SB */
 342 #define AZX_DCAPS_PRESET_AMD_SB \
 343         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 344          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 345
 346 /* quirks for Nvidia */
 347 #define AZX_DCAPS_PRESET_NVIDIA \
 348         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 349          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 350
 351 #define AZX_DCAPS_PRESET_CTHDA \
 352         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 353          AZX_DCAPS_NO_64BIT |\
 354          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 355
 356 /*
 357  * vga_switcheroo support
 358  */
 359 #ifdef SUPPORT_VGA_SWITCHEROO
 360 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 361 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 362 #else
 363 #define use_vga_switcheroo(chip)        0
 364 #define needs_eld_notify_link(chip)     false
 365 #endif
 366
 367 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 368                                         ((pci)->device == 0x0c0c) || \
 369                                         ((pci)->device == 0x0d0c) || \
 370                                         ((pci)->device == 0x160c))
 371
 372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 373
 374 static char *driver_short_names[] = {
 375         [AZX_DRIVER_ICH] = "HDA Intel",
 376         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 377         [AZX_DRIVER_SCH] = "HDA Intel MID",
 378         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 379         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 380         [AZX_DRIVER_ATI] = "HDA ATI SB",
 381         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 382         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 383         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 384         [AZX_DRIVER_SIS] = "HDA SIS966",
 385         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 386         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 387         [AZX_DRIVER_TERA] = "HDA Teradici",
 388         [AZX_DRIVER_CTX] = "HDA Creative",
 389         [AZX_DRIVER_CTHDA] = "HDA Creative",
 390         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 391         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 392         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 393 };
 394
 395 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 396 static void set_default_power_save(struct azx *chip);
 397
 398 /*
 399  * initialize the PCI registers
 400  */
 401 /* update bits in a PCI register byte */
 402 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 403                             unsigned char mask, unsigned char val)
 404 {
 405         unsigned char data;
 406
 407         pci_read_config_byte(pci, reg, &data);
 408         data &= ~mask;
 409         data |= (val & mask);
 410         pci_write_config_byte(pci, reg, data);
 411 }
 412
 413 static void azx_init_pci(struct azx *chip)
 414 {
 415         int snoop_type = azx_get_snoop_type(chip);
 416
 417         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 418          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 419          * Ensuring these bits are 0 clears playback static on some HD Audio
 420          * codecs.
 421          * The PCI register TCSEL is defined in the Intel manuals.
 422          */
 423         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 424                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 425                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 426         }
 427
 428         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 429          * we need to enable snoop.
 430          */
 431         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 432                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 433                         azx_snoop(chip));
 434                 update_pci_byte(chip->pci,
 435                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 436                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 437         }
 438
 439         /* For NVIDIA HDA, enable snoop */
 440         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 441                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 442                         azx_snoop(chip));
 443                 update_pci_byte(chip->pci,
 444                                 NVIDIA_HDA_TRANSREG_ADDR,
 445                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 446                 update_pci_byte(chip->pci,
 447                                 NVIDIA_HDA_ISTRM_COH,
 448                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 449                 update_pci_byte(chip->pci,
 450                                 NVIDIA_HDA_OSTRM_COH,
 451                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 452         }
 453
 454         /* Enable SCH/PCH snoop if needed */
 455         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 456                 unsigned short snoop;
 457                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 458                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 459                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 460                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 461                         if (!azx_snoop(chip))
 462                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 463                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 464                         pci_read_config_word(chip->pci,
 465                                 INTEL_SCH_HDA_DEVC, &snoop);
 466                 }
 467                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 468                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 469                         "Disabled" : "Enabled");
 470         }
 471 }
 472
 473 /*
 474  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 475  * and makes an audio stream sensitive to system latencies when
 476  * 24/32 bits are playing.
 477  * Adjusting threshold of DMA fifo to force the DMA request
 478  * sooner to improve latency tolerance at the expense of power.
 479  */
 480 static void bxt_reduce_dma_latency(struct azx *chip)
 481 {
 482         u32 val;
 483
 484         val = azx_readl(chip, VS_EM4L);
 485         val &= (0x3 << 20);
 486         azx_writel(chip, VS_EM4L, val);
 487 }
 488
 489 /*
 490  * ML_LCAP bits:
 491  *  bit 0: 6 MHz Supported
 492  *  bit 1: 12 MHz Supported
 493  *  bit 2: 24 MHz Supported
 494  *  bit 3: 48 MHz Supported
 495  *  bit 4: 96 MHz Supported
 496  *  bit 5: 192 MHz Supported
 497  */
 498 static int intel_get_lctl_scf(struct azx *chip)
 499 {
 500         struct hdac_bus *bus = azx_bus(chip);
 501         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 502         u32 val, t;
 503         int i;
 504
 505         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 506
 507         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 508                 t = preferred_bits[i];
 509                 if (val & (1 << t))
 510                         return t;
 511         }
 512
 513         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 514         return 0;
 515 }
 516
 517 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 518 {
 519         struct hdac_bus *bus = azx_bus(chip);
 520         u32 val;
 521         int timeout;
 522
 523         /*
 524          * the codecs are sharing the first link setting by default
 525          * If other links are enabled for stream, they need similar fix
 526          */
 527         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 528         val &= ~AZX_MLCTL_SPA;
 529         val |= state << AZX_MLCTL_SPA_SHIFT;
 530         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 531         /* wait for CPA */
 532         timeout = 50;
 533         while (timeout) {
 534                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 535                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 536                         return 0;
 537                 timeout--;
 538                 udelay(10);
 539         }
 540
 541         return -1;
 542 }
 543
 544 static void intel_init_lctl(struct azx *chip)
 545 {
 546         struct hdac_bus *bus = azx_bus(chip);
 547         u32 val;
 548         int ret;
 549
 550         /* 0. check lctl register value is correct or not */
 551         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 552         /* if SCF is already set, let's use it */
 553         if ((val & ML_LCTL_SCF_MASK) != 0)
 554                 return;
 555
 556         /*
 557          * Before operating on SPA, CPA must match SPA.
 558          * Any deviation may result in undefined behavior.
 559          */
 560         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 561                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 562                 return;
 563
 564         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 565         ret = intel_ml_lctl_set_power(chip, 0);
 566         udelay(100);
 567         if (ret)
 568                 goto set_spa;
 569
 570         /* 2. update SCF to select a properly audio clock*/
 571         val &= ~ML_LCTL_SCF_MASK;
 572         val |= intel_get_lctl_scf(chip);
 573         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 574
 575 set_spa:
 576         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 577         intel_ml_lctl_set_power(chip, 1);
 578         udelay(100);
 579 }
 580
 581 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 582 {
 583         struct hdac_bus *bus = azx_bus(chip);
 584         struct pci_dev *pci = chip->pci;
 585         u32 val;
 586
 587         snd_hdac_set_codec_wakeup(bus, true);
 588         if (chip->driver_type == AZX_DRIVER_SKL) {
 589                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 590                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 591                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 592         }
 593         azx_init_chip(chip, full_reset);
 594         if (chip->driver_type == AZX_DRIVER_SKL) {
 595                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 596                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 597                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 598         }
 599
 600         snd_hdac_set_codec_wakeup(bus, false);
 601
 602         /* reduce dma latency to avoid noise */
 603         if (IS_BXT(pci))
 604                 bxt_reduce_dma_latency(chip);
 605
 606         if (bus->mlcap != NULL)
 607                 intel_init_lctl(chip);
 608 }
 609
 610 /* calculate runtime delay from LPIB */
 611 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 612                                    unsigned int pos)
 613 {
 614         struct snd_pcm_substream *substream = azx_dev->core.substream;
 615         int stream = substream->stream;
 616         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 617         int delay;
 618
 619         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 620                 delay = pos - lpib_pos;
 621         else
 622                 delay = lpib_pos - pos;
 623         if (delay < 0) {
 624                 if (delay >= azx_dev->core.delay_negative_threshold)
 625                         delay = 0;
 626                 else
 627                         delay += azx_dev->core.bufsize;
 628         }
 629
 630         if (delay >= azx_dev->core.period_bytes) {
 631                 dev_info(chip->card->dev,
 632                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 633                          delay, azx_dev->core.period_bytes);
 634                 delay = 0;
 635                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 636                 chip->get_delay[stream] = NULL;
 637         }
 638
 639         return bytes_to_frames(substream->runtime, delay);
 640 }
 641
 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 643
 644 /* called from IRQ */
 645 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 646 {
 647         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 648         int ok;
 649
 650         ok = azx_position_ok(chip, azx_dev);
 651         if (ok == 1) {
 652                 azx_dev->irq_pending = 0;
 653                 return ok;
 654         } else if (ok == 0) {
 655                 /* bogus IRQ, process it later */
 656                 azx_dev->irq_pending = 1;
 657                 schedule_work(&hda->irq_pending_work);
 658         }
 659         return 0;
 660 }
 661
 662 #define display_power(chip, enable) \
 663         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 664
 665 /*
 666  * Check whether the current DMA position is acceptable for updating
 667  * periods.  Returns non-zero if it's OK.
 668  *
 669  * Many HD-audio controllers appear pretty inaccurate about
 670  * the update-IRQ timing.  The IRQ is issued before actually the
 671  * data is processed.  So, we need to process it afterwords in a
 672  * workqueue.
 673  */
 674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 675 {
 676         struct snd_pcm_substream *substream = azx_dev->core.substream;
 677         int stream = substream->stream;
 678         u32 wallclk;
 679         unsigned int pos;
 680
 681         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 682         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 683                 return -1;      /* bogus (too early) interrupt */
 684
 685         if (chip->get_position[stream])
 686                 pos = chip->get_position[stream](chip, azx_dev);
 687         else { /* use the position buffer as default */
 688                 pos = azx_get_pos_posbuf(chip, azx_dev);
 689                 if (!pos || pos == (u32)-1) {
 690                         dev_info(chip->card->dev,
 691                                  "Invalid position buffer, using LPIB read method instead.\n");
 692                         chip->get_position[stream] = azx_get_pos_lpib;
 693                         if (chip->get_position[0] == azx_get_pos_lpib &&
 694                             chip->get_position[1] == azx_get_pos_lpib)
 695                                 azx_bus(chip)->use_posbuf = false;
 696                         pos = azx_get_pos_lpib(chip, azx_dev);
 697                         chip->get_delay[stream] = NULL;
 698                 } else {
 699                         chip->get_position[stream] = azx_get_pos_posbuf;
 700                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 701                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 702                 }
 703         }
 704
 705         if (pos >= azx_dev->core.bufsize)
 706                 pos = 0;
 707
 708         if (WARN_ONCE(!azx_dev->core.period_bytes,
 709                       "hda-intel: zero azx_dev->period_bytes"))
 710                 return -1; /* this shouldn't happen! */
 711         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 712             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 713                 /* NG - it's below the first next period boundary */
 714                 return chip->bdl_pos_adj ? 0 : -1;
 715         azx_dev->core.start_wallclk += wallclk;
 716         return 1; /* OK, it's fine */
 717 }
 718
 719 /*
 720  * The work for pending PCM period updates.
 721  */
 722 static void azx_irq_pending_work(struct work_struct *work)
 723 {
 724         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 725         struct azx *chip = &hda->chip;
 726         struct hdac_bus *bus = azx_bus(chip);
 727         struct hdac_stream *s;
 728         int pending, ok;
 729
 730         if (!hda->irq_pending_warned) {
 731                 dev_info(chip->card->dev,
 732                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 733                          chip->card->number);
 734                 hda->irq_pending_warned = 1;
 735         }
 736
 737         for (;;) {
 738                 pending = 0;
 739                 spin_lock_irq(&bus->reg_lock);
 740                 list_for_each_entry(s, &bus->stream_list, list) {
 741                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 742                         if (!azx_dev->irq_pending ||
 743                             !s->substream ||
 744                             !s->running)
 745                                 continue;
 746                         ok = azx_position_ok(chip, azx_dev);
 747                         if (ok > 0) {
 748                                 azx_dev->irq_pending = 0;
 749                                 spin_unlock(&bus->reg_lock);
 750                                 snd_pcm_period_elapsed(s->substream);
 751                                 spin_lock(&bus->reg_lock);
 752                         } else if (ok < 0) {
 753                                 pending = 0;    /* too early */
 754                         } else
 755                                 pending++;
 756                 }
 757                 spin_unlock_irq(&bus->reg_lock);
 758                 if (!pending)
 759                         return;
 760                 msleep(1);
 761         }
 762 }
 763
 764 /* clear irq_pending flags and assure no on-going workq */
 765 static void azx_clear_irq_pending(struct azx *chip)
 766 {
 767         struct hdac_bus *bus = azx_bus(chip);
 768         struct hdac_stream *s;
 769
 770         spin_lock_irq(&bus->reg_lock);
 771         list_for_each_entry(s, &bus->stream_list, list) {
 772                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 773                 azx_dev->irq_pending = 0;
 774         }
 775         spin_unlock_irq(&bus->reg_lock);
 776 }
 777
 778 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 779 {
 780         struct hdac_bus *bus = azx_bus(chip);
 781
 782         if (request_irq(chip->pci->irq, azx_interrupt,
 783                         chip->msi ? 0 : IRQF_SHARED,
 784                         chip->card->irq_descr, chip)) {
 785                 dev_err(chip->card->dev,
 786                         "unable to grab IRQ %d, disabling device\n",
 787                         chip->pci->irq);
 788                 if (do_disconnect)
 789                         snd_card_disconnect(chip->card);
 790                 return -1;
 791         }
 792         bus->irq = chip->pci->irq;
 793         chip->card->sync_irq = bus->irq;
 794         pci_intx(chip->pci, !chip->msi);
 795         return 0;
 796 }
 797
 798 /* get the current DMA position with correction on VIA chips */
 799 static unsigned int azx_via_get_position(struct azx *chip,
 800                                          struct azx_dev *azx_dev)
 801 {
 802         unsigned int link_pos, mini_pos, bound_pos;
 803         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 804         unsigned int fifo_size;
 805
 806         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 807         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 808                 /* Playback, no problem using link position */
 809                 return link_pos;
 810         }
 811
 812         /* Capture */
 813         /* For new chipset,
 814          * use mod to get the DMA position just like old chipset
 815          */
 816         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 817         mod_dma_pos %= azx_dev->core.period_bytes;
 818
 819         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 820
 821         if (azx_dev->insufficient) {
 822                 /* Link position never gather than FIFO size */
 823                 if (link_pos <= fifo_size)
 824                         return 0;
 825
 826                 azx_dev->insufficient = 0;
 827         }
 828
 829         if (link_pos <= fifo_size)
 830                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 831         else
 832                 mini_pos = link_pos - fifo_size;
 833
 834         /* Find nearest previous boudary */
 835         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 836         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 837         if (mod_link_pos >= fifo_size)
 838                 bound_pos = link_pos - mod_link_pos;
 839         else if (mod_dma_pos >= mod_mini_pos)
 840                 bound_pos = mini_pos - mod_mini_pos;
 841         else {
 842                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 843                 if (bound_pos >= azx_dev->core.bufsize)
 844                         bound_pos = 0;
 845         }
 846
 847         /* Calculate real DMA position we want */
 848         return bound_pos + mod_dma_pos;
 849 }
 850
 851 #define AMD_FIFO_SIZE   32
 852
 853 /* get the current DMA position with FIFO size correction */
 854 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 855 {
 856         struct snd_pcm_substream *substream = azx_dev->core.substream;
 857         struct snd_pcm_runtime *runtime = substream->runtime;
 858         unsigned int pos, delay;
 859
 860         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 861         if (!runtime)
 862                 return pos;
 863
 864         runtime->delay = AMD_FIFO_SIZE;
 865         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 866         if (azx_dev->insufficient) {
 867                 if (pos < delay) {
 868                         delay = pos;
 869                         runtime->delay = bytes_to_frames(runtime, pos);
 870                 } else {
 871                         azx_dev->insufficient = 0;
 872                 }
 873         }
 874
 875         /* correct the DMA position for capture stream */
 876         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 877                 if (pos < delay)
 878                         pos += azx_dev->core.bufsize;
 879                 pos -= delay;
 880         }
 881
 882         return pos;
 883 }
 884
 885 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 886                                    unsigned int pos)
 887 {
 888         struct snd_pcm_substream *substream = azx_dev->core.substream;
 889
 890         /* just read back the calculated value in the above */
 891         return substream->runtime->delay;
 892 }
 893
 894 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 895                                          struct azx_dev *azx_dev)
 896 {
 897         return _snd_hdac_chip_readl(azx_bus(chip),
 898                                     AZX_REG_VS_SDXDPIB_XBASE +
 899                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 900                                      azx_dev->core.index));
 901 }
 902
 903 /* get the current DMA position with correction on SKL+ chips */
 904 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 905 {
 906         /* DPIB register gives a more accurate position for playback */
 907         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 908                 return azx_skl_get_dpib_pos(chip, azx_dev);
 909
 910         /* For capture, we need to read posbuf, but it requires a delay
 911          * for the possible boundary overlap; the read of DPIB fetches the
 912          * actual posbuf
 913          */
 914         udelay(20);
 915         azx_skl_get_dpib_pos(chip, azx_dev);
 916         return azx_get_pos_posbuf(chip, azx_dev);
 917 }
 918
 919 #ifdef CONFIG_PM
 920 static DEFINE_MUTEX(card_list_lock);
 921 static LIST_HEAD(card_list);
 922
 923 static void azx_add_card_list(struct azx *chip)
 924 {
 925         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 926         mutex_lock(&card_list_lock);
 927         list_add(&hda->list, &card_list);
 928         mutex_unlock(&card_list_lock);
 929 }
 930
 931 static void azx_del_card_list(struct azx *chip)
 932 {
 933         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 934         mutex_lock(&card_list_lock);
 935         list_del_init(&hda->list);
 936         mutex_unlock(&card_list_lock);
 937 }
 938
 939 /* trigger power-save check at writing parameter */
 940 static int param_set_xint(const char *val, const struct kernel_param *kp)
 941 {
 942         struct hda_intel *hda;
 943         struct azx *chip;
 944         int prev = power_save;
 945         int ret = param_set_int(val, kp);
 946
 947         if (ret || prev == power_save)
 948                 return ret;
 949
 950         mutex_lock(&card_list_lock);
 951         list_for_each_entry(hda, &card_list, list) {
 952                 chip = &hda->chip;
 953                 if (!hda->probe_continued || chip->disabled)
 954                         continue;
 955                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 956         }
 957         mutex_unlock(&card_list_lock);
 958         return 0;
 959 }
 960
 961 /*
 962  * power management
 963  */
 964 static bool azx_is_pm_ready(struct snd_card *card)
 965 {
 966         struct azx *chip;
 967         struct hda_intel *hda;
 968
 969         if (!card)
 970                 return false;
 971         chip = card->private_data;
 972         hda = container_of(chip, struct hda_intel, chip);
 973         if (chip->disabled || hda->init_failed || !chip->running)
 974                 return false;
 975         return true;
 976 }
 977
 978 static void __azx_runtime_suspend(struct azx *chip)
 979 {
 980         azx_stop_chip(chip);
 981         azx_enter_link_reset(chip);
 982         azx_clear_irq_pending(chip);
 983         display_power(chip, false);
 984 }
 985
 986 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 987 {
 988         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 989         struct hdac_bus *bus = azx_bus(chip);
 990         struct hda_codec *codec;
 991         int status;
 992
 993         display_power(chip, true);
 994         if (hda->need_i915_power)
 995                 snd_hdac_i915_set_bclk(bus);
 996
 997         /* Read STATESTS before controller reset */
 998         status = azx_readw(chip, STATESTS);
 999
1000         azx_init_pci(chip);
1001         hda_intel_init_chip(chip, true);
1002
1003         if (status && from_rt) {
1004                 list_for_each_codec(codec, &chip->bus)
1005                         if (status & (1 << codec->addr))
1006                                 schedule_delayed_work(&codec->jackpoll_work,
1007                                                       codec->jackpoll_interval);
1008         }
1009
1010         /* power down again for link-controlled chips */
1011         if (!hda->need_i915_power)
1012                 display_power(chip, false);
1013 }
1014
1015 #ifdef CONFIG_PM_SLEEP
1016 static int azx_suspend(struct device *dev)
1017 {
1018         struct snd_card *card = dev_get_drvdata(dev);
1019         struct azx *chip;
1020         struct hdac_bus *bus;
1021
1022         if (!azx_is_pm_ready(card))
1023                 return 0;
1024
1025         chip = card->private_data;
1026         bus = azx_bus(chip);
1027         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1028         __azx_runtime_suspend(chip);
1029         if (bus->irq >= 0) {
1030                 free_irq(bus->irq, chip);
1031                 bus->irq = -1;
1032                 chip->card->sync_irq = -1;
1033         }
1034
1035         if (chip->msi)
1036                 pci_disable_msi(chip->pci);
1037
1038         trace_azx_suspend(chip);
1039         return 0;
1040 }
1041
1042 static int azx_resume(struct device *dev)
1043 {
1044         struct snd_card *card = dev_get_drvdata(dev);
1045         struct azx *chip;
1046
1047         if (!azx_is_pm_ready(card))
1048                 return 0;
1049
1050         chip = card->private_data;
1051         if (chip->msi)
1052                 if (pci_enable_msi(chip->pci) < 0)
1053                         chip->msi = 0;
1054         if (azx_acquire_irq(chip, 1) < 0)
1055                 return -EIO;
1056         __azx_runtime_resume(chip, false);
1057         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1058
1059         trace_azx_resume(chip);
1060         return 0;
1061 }
1062
1063 /* put codec down to D3 at hibernation for Intel SKL+;
1064  * otherwise BIOS may still access the codec and screw up the driver
1065  */
1066 static int azx_freeze_noirq(struct device *dev)
1067 {
1068         struct snd_card *card = dev_get_drvdata(dev);
1069         struct azx *chip = card->private_data;
1070         struct pci_dev *pci = to_pci_dev(dev);
1071
1072         if (chip->driver_type == AZX_DRIVER_SKL)
1073                 pci_set_power_state(pci, PCI_D3hot);
1074
1075         return 0;
1076 }
1077
1078 static int azx_thaw_noirq(struct device *dev)
1079 {
1080         struct snd_card *card = dev_get_drvdata(dev);
1081         struct azx *chip = card->private_data;
1082         struct pci_dev *pci = to_pci_dev(dev);
1083
1084         if (chip->driver_type == AZX_DRIVER_SKL)
1085                 pci_set_power_state(pci, PCI_D0);
1086
1087         return 0;
1088 }
1089 #endif /* CONFIG_PM_SLEEP */
1090
1091 static int azx_runtime_suspend(struct device *dev)
1092 {
1093         struct snd_card *card = dev_get_drvdata(dev);
1094         struct azx *chip;
1095
1096         if (!azx_is_pm_ready(card))
1097                 return 0;
1098         chip = card->private_data;
1099         if (!azx_has_pm_runtime(chip))
1100                 return 0;
1101
1102         /* enable controller wake up event */
1103         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1104                   STATESTS_INT_MASK);
1105
1106         __azx_runtime_suspend(chip);
1107         trace_azx_runtime_suspend(chip);
1108         return 0;
1109 }
1110
1111 static int azx_runtime_resume(struct device *dev)
1112 {
1113         struct snd_card *card = dev_get_drvdata(dev);
1114         struct azx *chip;
1115
1116         if (!azx_is_pm_ready(card))
1117                 return 0;
1118         chip = card->private_data;
1119         if (!azx_has_pm_runtime(chip))
1120                 return 0;
1121         __azx_runtime_resume(chip, true);
1122
1123         /* disable controller Wake Up event*/
1124         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1125                         ~STATESTS_INT_MASK);
1126
1127         trace_azx_runtime_resume(chip);
1128         return 0;
1129 }
1130
1131 static int azx_runtime_idle(struct device *dev)
1132 {
1133         struct snd_card *card = dev_get_drvdata(dev);
1134         struct azx *chip;
1135         struct hda_intel *hda;
1136
1137         if (!card)
1138                 return 0;
1139
1140         chip = card->private_data;
1141         hda = container_of(chip, struct hda_intel, chip);
1142         if (chip->disabled || hda->init_failed)
1143                 return 0;
1144
1145         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1146             azx_bus(chip)->codec_powered || !chip->running)
1147                 return -EBUSY;
1148
1149         /* ELD notification gets broken when HD-audio bus is off */
1150         if (needs_eld_notify_link(chip))
1151                 return -EBUSY;
1152
1153         return 0;
1154 }
1155
1156 static const struct dev_pm_ops azx_pm = {
1157         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1158 #ifdef CONFIG_PM_SLEEP
1159         .freeze_noirq = azx_freeze_noirq,
1160         .thaw_noirq = azx_thaw_noirq,
1161 #endif
1162         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1163 };
1164
1165 #define AZX_PM_OPS      &azx_pm
1166 #else
1167 #define azx_add_card_list(chip) /* NOP */
1168 #define azx_del_card_list(chip) /* NOP */
1169 #define AZX_PM_OPS      NULL
1170 #endif /* CONFIG_PM */
1171
1172
1173 static int azx_probe_continue(struct azx *chip);
1174
1175 #ifdef SUPPORT_VGA_SWITCHEROO
1176 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1177
1178 static void azx_vs_set_state(struct pci_dev *pci,
1179                              enum vga_switcheroo_state state)
1180 {
1181         struct snd_card *card = pci_get_drvdata(pci);
1182         struct azx *chip = card->private_data;
1183         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1184         struct hda_codec *codec;
1185         bool disabled;
1186
1187         wait_for_completion(&hda->probe_wait);
1188         if (hda->init_failed)
1189                 return;
1190
1191         disabled = (state == VGA_SWITCHEROO_OFF);
1192         if (chip->disabled == disabled)
1193                 return;
1194
1195         if (!hda->probe_continued) {
1196                 chip->disabled = disabled;
1197                 if (!disabled) {
1198                         dev_info(chip->card->dev,
1199                                  "Start delayed initialization\n");
1200                         if (azx_probe_continue(chip) < 0) {
1201                                 dev_err(chip->card->dev, "initialization error\n");
1202                                 hda->init_failed = true;
1203                         }
1204                 }
1205         } else {
1206                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1207                          disabled ? "Disabling" : "Enabling");
1208                 if (disabled) {
1209                         list_for_each_codec(codec, &chip->bus) {
1210                                 pm_runtime_suspend(hda_codec_dev(codec));
1211                                 pm_runtime_disable(hda_codec_dev(codec));
1212                         }
1213                         pm_runtime_suspend(card->dev);
1214                         pm_runtime_disable(card->dev);
1215                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1216                          * however we have no ACPI handle, so pci/acpi can't put us there,
1217                          * put ourselves there */
1218                         pci->current_state = PCI_D3cold;
1219                         chip->disabled = true;
1220                         if (snd_hda_lock_devices(&chip->bus))
1221                                 dev_warn(chip->card->dev,
1222                                          "Cannot lock devices!\n");
1223                 } else {
1224                         snd_hda_unlock_devices(&chip->bus);
1225                         chip->disabled = false;
1226                         pm_runtime_enable(card->dev);
1227                         list_for_each_codec(codec, &chip->bus) {
1228                                 pm_runtime_enable(hda_codec_dev(codec));
1229                                 pm_runtime_resume(hda_codec_dev(codec));
1230                         }
1231                 }
1232         }
1233 }
1234
1235 static bool azx_vs_can_switch(struct pci_dev *pci)
1236 {
1237         struct snd_card *card = pci_get_drvdata(pci);
1238         struct azx *chip = card->private_data;
1239         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1240
1241         wait_for_completion(&hda->probe_wait);
1242         if (hda->init_failed)
1243                 return false;
1244         if (chip->disabled || !hda->probe_continued)
1245                 return true;
1246         if (snd_hda_lock_devices(&chip->bus))
1247                 return false;
1248         snd_hda_unlock_devices(&chip->bus);
1249         return true;
1250 }
1251
1252 /*
1253  * The discrete GPU cannot power down unless the HDA controller runtime
1254  * suspends, so activate runtime PM on codecs even if power_save == 0.
1255  */
1256 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1257 {
1258         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1259         struct hda_codec *codec;
1260
1261         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1262                 list_for_each_codec(codec, &chip->bus)
1263                         codec->auto_runtime_pm = 1;
1264                 /* reset the power save setup */
1265                 if (chip->running)
1266                         set_default_power_save(chip);
1267         }
1268 }
1269
1270 static void azx_vs_gpu_bound(struct pci_dev *pci,
1271                              enum vga_switcheroo_client_id client_id)
1272 {
1273         struct snd_card *card = pci_get_drvdata(pci);
1274         struct azx *chip = card->private_data;
1275
1276         if (client_id == VGA_SWITCHEROO_DIS)
1277                 chip->bus.keep_power = 0;
1278         setup_vga_switcheroo_runtime_pm(chip);
1279 }
1280
1281 static void init_vga_switcheroo(struct azx *chip)
1282 {
1283         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1284         struct pci_dev *p = get_bound_vga(chip->pci);
1285         struct pci_dev *parent;
1286         if (p) {
1287                 dev_info(chip->card->dev,
1288                          "Handle vga_switcheroo audio client\n");
1289                 hda->use_vga_switcheroo = 1;
1290
1291                 /* cleared in either gpu_bound op or codec probe, or when its
1292                  * upstream port has _PR3 (i.e. dGPU).
1293                  */
1294                 parent = pci_upstream_bridge(p);
1295                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1296                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1297                 pci_dev_put(p);
1298         }
1299 }
1300
1301 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1302         .set_gpu_state = azx_vs_set_state,
1303         .can_switch = azx_vs_can_switch,
1304         .gpu_bound = azx_vs_gpu_bound,
1305 };
1306
1307 static int register_vga_switcheroo(struct azx *chip)
1308 {
1309         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1310         struct pci_dev *p;
1311         int err;
1312
1313         if (!hda->use_vga_switcheroo)
1314                 return 0;
1315
1316         p = get_bound_vga(chip->pci);
1317         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1318         pci_dev_put(p);
1319
1320         if (err < 0)
1321                 return err;
1322         hda->vga_switcheroo_registered = 1;
1323
1324         return 0;
1325 }
1326 #else
1327 #define init_vga_switcheroo(chip)               /* NOP */
1328 #define register_vga_switcheroo(chip)           0
1329 #define check_hdmi_disabled(pci)        false
1330 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1331 #endif /* SUPPORT_VGA_SWITCHER */
1332
1333 /*
1334  * destructor
1335  */
1336 static int azx_free(struct azx *chip)
1337 {
1338         struct pci_dev *pci = chip->pci;
1339         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1340         struct hdac_bus *bus = azx_bus(chip);
1341
1342         if (azx_has_pm_runtime(chip) && chip->running)
1343                 pm_runtime_get_noresume(&pci->dev);
1344         chip->running = 0;
1345
1346         azx_del_card_list(chip);
1347
1348         hda->init_failed = 1; /* to be sure */
1349         complete_all(&hda->probe_wait);
1350
1351         if (use_vga_switcheroo(hda)) {
1352                 if (chip->disabled && hda->probe_continued)
1353                         snd_hda_unlock_devices(&chip->bus);
1354                 if (hda->vga_switcheroo_registered)
1355                         vga_switcheroo_unregister_client(chip->pci);
1356         }
1357
1358         if (bus->chip_init) {
1359                 azx_clear_irq_pending(chip);
1360                 azx_stop_all_streams(chip);
1361                 azx_stop_chip(chip);
1362         }
1363
1364         if (bus->irq >= 0)
1365                 free_irq(bus->irq, (void*)chip);
1366         if (chip->msi)
1367                 pci_disable_msi(chip->pci);
1368         iounmap(bus->remap_addr);
1369
1370         azx_free_stream_pages(chip);
1371         azx_free_streams(chip);
1372         snd_hdac_bus_exit(bus);
1373
1374         if (chip->region_requested)
1375                 pci_release_regions(chip->pci);
1376
1377         pci_disable_device(chip->pci);
1378 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1379         release_firmware(chip->fw);
1380 #endif
1381         display_power(chip, false);
1382
1383         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1384                 snd_hdac_i915_exit(bus);
1385         kfree(hda);
1386
1387         return 0;
1388 }
1389
1390 static int azx_dev_disconnect(struct snd_device *device)
1391 {
1392         struct azx *chip = device->device_data;
1393         struct hdac_bus *bus = azx_bus(chip);
1394
1395         chip->bus.shutdown = 1;
1396         cancel_work_sync(&bus->unsol_work);
1397
1398         return 0;
1399 }
1400
1401 static int azx_dev_free(struct snd_device *device)
1402 {
1403         return azx_free(device->device_data);
1404 }
1405
1406 #ifdef SUPPORT_VGA_SWITCHEROO
1407 #ifdef CONFIG_ACPI
1408 /* ATPX is in the integrated GPU's namespace */
1409 static bool atpx_present(void)
1410 {
1411         struct pci_dev *pdev = NULL;
1412         acpi_handle dhandle, atpx_handle;
1413         acpi_status status;
1414
1415         while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
1416                 dhandle = ACPI_HANDLE(&pdev->dev);
1417                 if (dhandle) {
1418                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1419                         if (!ACPI_FAILURE(status)) {
1420                                 pci_dev_put(pdev);
1421                                 return true;
1422                         }
1423                 }
1424         }
1425         return false;
1426 }
1427 #else
1428 static bool atpx_present(void)
1429 {
1430         return false;
1431 }
1432 #endif
1433
1434 /*
1435  * Check of disabled HDMI controller by vga_switcheroo
1436  */
1437 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1438 {
1439         struct pci_dev *p;
1440
1441         /* check only discrete GPU */
1442         switch (pci->vendor) {
1443         case PCI_VENDOR_ID_ATI:
1444         case PCI_VENDOR_ID_AMD:
1445                 if (pci->devfn == 1) {
1446                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1447                                                         pci->bus->number, 0);
1448                         if (p) {
1449                                 /* ATPX is in the integrated GPU's ACPI namespace
1450                                  * rather than the dGPU's namespace. However,
1451                                  * the dGPU is the one who is involved in
1452                                  * vgaswitcheroo.
1453                                  */
1454                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1455                                     atpx_present())
1456                                         return p;
1457                                 pci_dev_put(p);
1458                         }
1459                 }
1460                 break;
1461         case PCI_VENDOR_ID_NVIDIA:
1462                 if (pci->devfn == 1) {
1463                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1464                                                         pci->bus->number, 0);
1465                         if (p) {
1466                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1467                                         return p;
1468                                 pci_dev_put(p);
1469                         }
1470                 }
1471                 break;
1472         }
1473         return NULL;
1474 }
1475
1476 static bool check_hdmi_disabled(struct pci_dev *pci)
1477 {
1478         bool vga_inactive = false;
1479         struct pci_dev *p = get_bound_vga(pci);
1480
1481         if (p) {
1482                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1483                         vga_inactive = true;
1484                 pci_dev_put(p);
1485         }
1486         return vga_inactive;
1487 }
1488 #endif /* SUPPORT_VGA_SWITCHEROO */
1489
1490 /*
1491  * white/black-listing for position_fix
1492  */
1493 static struct snd_pci_quirk position_fix_list[] = {
1494         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1495         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1496         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1497         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1498         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1499         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1500         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1501         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1502         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1503         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1504         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1505         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1506         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1507         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1508         {}
1509 };
1510
1511 static int check_position_fix(struct azx *chip, int fix)
1512 {
1513         const struct snd_pci_quirk *q;
1514
1515         switch (fix) {
1516         case POS_FIX_AUTO:
1517         case POS_FIX_LPIB:
1518         case POS_FIX_POSBUF:
1519         case POS_FIX_VIACOMBO:
1520         case POS_FIX_COMBO:
1521         case POS_FIX_SKL:
1522         case POS_FIX_FIFO:
1523                 return fix;
1524         }
1525
1526         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1527         if (q) {
1528                 dev_info(chip->card->dev,
1529                          "position_fix set to %d for device %04x:%04x\n",
1530                          q->value, q->subvendor, q->subdevice);
1531                 return q->value;
1532         }
1533
1534         /* Check VIA/ATI HD Audio Controller exist */
1535         if (chip->driver_type == AZX_DRIVER_VIA) {
1536                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1537                 return POS_FIX_VIACOMBO;
1538         }
1539         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1540                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1541                 return POS_FIX_FIFO;
1542         }
1543         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1544                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1545                 return POS_FIX_LPIB;
1546         }
1547         if (chip->driver_type == AZX_DRIVER_SKL) {
1548                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1549                 return POS_FIX_SKL;
1550         }
1551         return POS_FIX_AUTO;
1552 }
1553
1554 static void assign_position_fix(struct azx *chip, int fix)
1555 {
1556         static azx_get_pos_callback_t callbacks[] = {
1557                 [POS_FIX_AUTO] = NULL,
1558                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1559                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1560                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1561                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1562                 [POS_FIX_SKL] = azx_get_pos_skl,
1563                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1564         };
1565
1566         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1567
1568         /* combo mode uses LPIB only for playback */
1569         if (fix == POS_FIX_COMBO)
1570                 chip->get_position[1] = NULL;
1571
1572         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1573             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1574                 chip->get_delay[0] = chip->get_delay[1] =
1575                         azx_get_delay_from_lpib;
1576         }
1577
1578         if (fix == POS_FIX_FIFO)
1579                 chip->get_delay[0] = chip->get_delay[1] =
1580                         azx_get_delay_from_fifo;
1581 }
1582
1583 /*
1584  * black-lists for probe_mask
1585  */
1586 static struct snd_pci_quirk probe_mask_list[] = {
1587         /* Thinkpad often breaks the controller communication when accessing
1588          * to the non-working (or non-existing) modem codec slot.
1589          */
1590         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1591         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1592         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1593         /* broken BIOS */
1594         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1595         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1596         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1597         /* forced codec slots */
1598         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1599         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1600         /* WinFast VP200 H (Teradici) user reported broken communication */
1601         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1602         {}
1603 };
1604
1605 #define AZX_FORCE_CODEC_MASK    0x100
1606
1607 static void check_probe_mask(struct azx *chip, int dev)
1608 {
1609         const struct snd_pci_quirk *q;
1610
1611         chip->codec_probe_mask = probe_mask[dev];
1612         if (chip->codec_probe_mask == -1) {
1613                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1614                 if (q) {
1615                         dev_info(chip->card->dev,
1616                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1617                                  q->value, q->subvendor, q->subdevice);
1618                         chip->codec_probe_mask = q->value;
1619                 }
1620         }
1621
1622         /* check forced option */
1623         if (chip->codec_probe_mask != -1 &&
1624             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1625                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1626                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1627                          (int)azx_bus(chip)->codec_mask);
1628         }
1629 }
1630
1631 /*
1632  * white/black-list for enable_msi
1633  */
1634 static struct snd_pci_quirk msi_black_list[] = {
1635         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1636         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1637         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1638         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1639         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1640         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1641         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1642         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1643         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1644         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1645         {}
1646 };
1647
1648 static void check_msi(struct azx *chip)
1649 {
1650         const struct snd_pci_quirk *q;
1651
1652         if (enable_msi >= 0) {
1653                 chip->msi = !!enable_msi;
1654                 return;
1655         }
1656         chip->msi = 1;  /* enable MSI as default */
1657         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1658         if (q) {
1659                 dev_info(chip->card->dev,
1660                          "msi for device %04x:%04x set to %d\n",
1661                          q->subvendor, q->subdevice, q->value);
1662                 chip->msi = q->value;
1663                 return;
1664         }
1665
1666         /* NVidia chipsets seem to cause troubles with MSI */
1667         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1668                 dev_info(chip->card->dev, "Disabling MSI\n");
1669                 chip->msi = 0;
1670         }
1671 }
1672
1673 /* check the snoop mode availability */
1674 static void azx_check_snoop_available(struct azx *chip)
1675 {
1676         int snoop = hda_snoop;
1677
1678         if (snoop >= 0) {
1679                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1680                          snoop ? "snoop" : "non-snoop");
1681                 chip->snoop = snoop;
1682                 chip->uc_buffer = !snoop;
1683                 return;
1684         }
1685
1686         snoop = true;
1687         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1688             chip->driver_type == AZX_DRIVER_VIA) {
1689                 /* force to non-snoop mode for a new VIA controller
1690                  * when BIOS is set
1691                  */
1692                 u8 val;
1693                 pci_read_config_byte(chip->pci, 0x42, &val);
1694                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1695                                       chip->pci->revision == 0x20))
1696                         snoop = false;
1697         }
1698
1699         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1700                 snoop = false;
1701
1702         chip->snoop = snoop;
1703         if (!snoop) {
1704                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1705                 /* C-Media requires non-cached pages only for CORB/RIRB */
1706                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1707                         chip->uc_buffer = true;
1708         }
1709 }
1710
1711 static void azx_probe_work(struct work_struct *work)
1712 {
1713         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1714         azx_probe_continue(&hda->chip);
1715 }
1716
1717 static int default_bdl_pos_adj(struct azx *chip)
1718 {
1719         /* some exceptions: Atoms seem problematic with value 1 */
1720         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1721                 switch (chip->pci->device) {
1722                 case 0x0f04: /* Baytrail */
1723                 case 0x2284: /* Braswell */
1724                         return 32;
1725                 }
1726         }
1727
1728         switch (chip->driver_type) {
1729         case AZX_DRIVER_ICH:
1730         case AZX_DRIVER_PCH:
1731                 return 1;
1732         default:
1733                 return 32;
1734         }
1735 }
1736
1737 /*
1738  * constructor
1739  */
1740 static const struct hda_controller_ops pci_hda_ops;
1741
1742 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1743                       int dev, unsigned int driver_caps,
1744                       struct azx **rchip)
1745 {
1746         static struct snd_device_ops ops = {
1747                 .dev_disconnect = azx_dev_disconnect,
1748                 .dev_free = azx_dev_free,
1749         };
1750         struct hda_intel *hda;
1751         struct azx *chip;
1752         int err;
1753
1754         *rchip = NULL;
1755
1756         err = pci_enable_device(pci);
1757         if (err < 0)
1758                 return err;
1759
1760         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1761         if (!hda) {
1762                 pci_disable_device(pci);
1763                 return -ENOMEM;
1764         }
1765
1766         chip = &hda->chip;
1767         mutex_init(&chip->open_mutex);
1768         chip->card = card;
1769         chip->pci = pci;
1770         chip->ops = &pci_hda_ops;
1771         chip->driver_caps = driver_caps;
1772         chip->driver_type = driver_caps & 0xff;
1773         check_msi(chip);
1774         chip->dev_index = dev;
1775         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1776                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1777         INIT_LIST_HEAD(&chip->pcm_list);
1778         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1779         INIT_LIST_HEAD(&hda->list);
1780         init_vga_switcheroo(chip);
1781         init_completion(&hda->probe_wait);
1782
1783         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1784
1785         check_probe_mask(chip, dev);
1786
1787         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1788                 chip->fallback_to_single_cmd = 1;
1789         else /* explicitly set to single_cmd or not */
1790                 chip->single_cmd = single_cmd;
1791
1792         azx_check_snoop_available(chip);
1793
1794         if (bdl_pos_adj[dev] < 0)
1795                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1796         else
1797                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1798
1799         err = azx_bus_init(chip, model[dev]);
1800         if (err < 0) {
1801                 kfree(hda);
1802                 pci_disable_device(pci);
1803                 return err;
1804         }
1805
1806         /* use the non-cached pages in non-snoop mode */
1807         if (!azx_snoop(chip))
1808                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1809
1810         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1811                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1812                 chip->bus.core.needs_damn_long_delay = 1;
1813         }
1814
1815         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1816         if (err < 0) {
1817                 dev_err(card->dev, "Error creating device [card]!\n");
1818                 azx_free(chip);
1819                 return err;
1820         }
1821
1822         /* continue probing in work context as may trigger request module */
1823         INIT_WORK(&hda->probe_work, azx_probe_work);
1824
1825         *rchip = chip;
1826
1827         return 0;
1828 }
1829
1830 static int azx_first_init(struct azx *chip)
1831 {
1832         int dev = chip->dev_index;
1833         struct pci_dev *pci = chip->pci;
1834         struct snd_card *card = chip->card;
1835         struct hdac_bus *bus = azx_bus(chip);
1836         int err;
1837         unsigned short gcap;
1838         unsigned int dma_bits = 64;
1839
1840 #if BITS_PER_LONG != 64
1841         /* Fix up base address on ULI M5461 */
1842         if (chip->driver_type == AZX_DRIVER_ULI) {
1843                 u16 tmp3;
1844                 pci_read_config_word(pci, 0x40, &tmp3);
1845                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1846                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1847         }
1848 #endif
1849
1850         err = pci_request_regions(pci, "ICH HD audio");
1851         if (err < 0)
1852                 return err;
1853         chip->region_requested = 1;
1854
1855         bus->addr = pci_resource_start(pci, 0);
1856         bus->remap_addr = pci_ioremap_bar(pci, 0);
1857         if (bus->remap_addr == NULL) {
1858                 dev_err(card->dev, "ioremap error\n");
1859                 return -ENXIO;
1860         }
1861
1862         if (chip->driver_type == AZX_DRIVER_SKL)
1863                 snd_hdac_bus_parse_capabilities(bus);
1864
1865         /*
1866          * Some Intel CPUs has always running timer (ART) feature and
1867          * controller may have Global time sync reporting capability, so
1868          * check both of these before declaring synchronized time reporting
1869          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1870          */
1871         chip->gts_present = false;
1872
1873 #ifdef CONFIG_X86
1874         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1875                 chip->gts_present = true;
1876 #endif
1877
1878         if (chip->msi) {
1879                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1880                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1881                         pci->no_64bit_msi = true;
1882                 }
1883                 if (pci_enable_msi(pci) < 0)
1884                         chip->msi = 0;
1885         }
1886
1887         pci_set_master(pci);
1888
1889         gcap = azx_readw(chip, GCAP);
1890         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1891
1892         /* AMD devices support 40 or 48bit DMA, take the safe one */
1893         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1894                 dma_bits = 40;
1895
1896         /* disable SB600 64bit support for safety */
1897         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1898                 struct pci_dev *p_smbus;
1899                 dma_bits = 40;
1900                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1901                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1902                                          NULL);
1903                 if (p_smbus) {
1904                         if (p_smbus->revision < 0x30)
1905                                 gcap &= ~AZX_GCAP_64OK;
1906                         pci_dev_put(p_smbus);
1907                 }
1908         }
1909
1910         /* NVidia hardware normally only supports up to 40 bits of DMA */
1911         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1912                 dma_bits = 40;
1913
1914         /* disable 64bit DMA address on some devices */
1915         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1916                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1917                 gcap &= ~AZX_GCAP_64OK;
1918         }
1919
1920         /* disable buffer size rounding to 128-byte multiples if supported */
1921         if (align_buffer_size >= 0)
1922                 chip->align_buffer_size = !!align_buffer_size;
1923         else {
1924                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1925                         chip->align_buffer_size = 0;
1926                 else
1927                         chip->align_buffer_size = 1;
1928         }
1929
1930         /* allow 64bit DMA address if supported by H/W */
1931         if (!(gcap & AZX_GCAP_64OK))
1932                 dma_bits = 32;
1933         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1934                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1935         } else {
1936                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1937                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1938         }
1939
1940         /* read number of streams from GCAP register instead of using
1941          * hardcoded value
1942          */
1943         chip->capture_streams = (gcap >> 8) & 0x0f;
1944         chip->playback_streams = (gcap >> 12) & 0x0f;
1945         if (!chip->playback_streams && !chip->capture_streams) {
1946                 /* gcap didn't give any info, switching to old method */
1947
1948                 switch (chip->driver_type) {
1949                 case AZX_DRIVER_ULI:
1950                         chip->playback_streams = ULI_NUM_PLAYBACK;
1951                         chip->capture_streams = ULI_NUM_CAPTURE;
1952                         break;
1953                 case AZX_DRIVER_ATIHDMI:
1954                 case AZX_DRIVER_ATIHDMI_NS:
1955                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1956                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1957                         break;
1958                 case AZX_DRIVER_GENERIC:
1959                 default:
1960                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1961                         chip->capture_streams = ICH6_NUM_CAPTURE;
1962                         break;
1963                 }
1964         }
1965         chip->capture_index_offset = 0;
1966         chip->playback_index_offset = chip->capture_streams;
1967         chip->num_streams = chip->playback_streams + chip->capture_streams;
1968
1969         /* sanity check for the SDxCTL.STRM field overflow */
1970         if (chip->num_streams > 15 &&
1971             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1972                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1973                          "forcing separate stream tags", chip->num_streams);
1974                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1975         }
1976
1977         /* initialize streams */
1978         err = azx_init_streams(chip);
1979         if (err < 0)
1980                 return err;
1981
1982         err = azx_alloc_stream_pages(chip);
1983         if (err < 0)
1984                 return err;
1985
1986         /* initialize chip */
1987         azx_init_pci(chip);
1988
1989         snd_hdac_i915_set_bclk(bus);
1990
1991         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1992
1993         /* codec detection */
1994         if (!azx_bus(chip)->codec_mask) {
1995                 dev_err(card->dev, "no codecs found!\n");
1996                 return -ENODEV;
1997         }
1998
1999         if (azx_acquire_irq(chip, 0) < 0)
2000                 return -EBUSY;
2001
2002         strcpy(card->driver, "HDA-Intel");
2003         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2004                 sizeof(card->shortname));
2005         snprintf(card->longname, sizeof(card->longname),
2006                  "%s at 0x%lx irq %i",
2007                  card->shortname, bus->addr, bus->irq);
2008
2009         return 0;
2010 }
2011
2012 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2013 /* callback from request_firmware_nowait() */
2014 static void azx_firmware_cb(const struct firmware *fw, void *context)
2015 {
2016         struct snd_card *card = context;
2017         struct azx *chip = card->private_data;
2018         struct pci_dev *pci = chip->pci;
2019
2020         if (!fw) {
2021                 dev_err(card->dev, "Cannot load firmware, aborting\n");
2022                 goto error;
2023         }
2024
2025         chip->fw = fw;
2026         if (!chip->disabled) {
2027                 /* continue probing */
2028                 if (azx_probe_continue(chip))
2029                         goto error;
2030         }
2031         return; /* OK */
2032
2033  error:
2034         snd_card_free(card);
2035         pci_set_drvdata(pci, NULL);
2036 }
2037 #endif
2038
2039 static int disable_msi_reset_irq(struct azx *chip)
2040 {
2041         struct hdac_bus *bus = azx_bus(chip);
2042         int err;
2043
2044         free_irq(bus->irq, chip);
2045         bus->irq = -1;
2046         chip->card->sync_irq = -1;
2047         pci_disable_msi(chip->pci);
2048         chip->msi = 0;
2049         err = azx_acquire_irq(chip, 1);
2050         if (err < 0)
2051                 return err;
2052
2053         return 0;
2054 }
2055
2056 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2057                              struct vm_area_struct *area)
2058 {
2059 #ifdef CONFIG_X86
2060         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2061         struct azx *chip = apcm->chip;
2062         if (chip->uc_buffer)
2063                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2064 #endif
2065 }
2066
2067 static const struct hda_controller_ops pci_hda_ops = {
2068         .disable_msi_reset_irq = disable_msi_reset_irq,
2069         .pcm_mmap_prepare = pcm_mmap_prepare,
2070         .position_check = azx_position_check,
2071 };
2072
2073 static int azx_probe(struct pci_dev *pci,
2074                      const struct pci_device_id *pci_id)
2075 {
2076         static int dev;
2077         struct snd_card *card;
2078         struct hda_intel *hda;
2079         struct azx *chip;
2080         bool schedule_probe;
2081         int err;
2082
2083         if (dev >= SNDRV_CARDS)
2084                 return -ENODEV;
2085         if (!enable[dev]) {
2086                 dev++;
2087                 return -ENOENT;
2088         }
2089
2090         /*
2091          * stop probe if another Intel's DSP driver should be activated
2092          */
2093         if (dsp_driver) {
2094                 err = snd_intel_dsp_driver_probe(pci);
2095                 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2096                     err != SND_INTEL_DSP_DRIVER_LEGACY)
2097                         return -ENODEV;
2098         }
2099
2100         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2101                            0, &card);
2102         if (err < 0) {
2103                 dev_err(&pci->dev, "Error creating card!\n");
2104                 return err;
2105         }
2106
2107         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2108         if (err < 0)
2109                 goto out_free;
2110         card->private_data = chip;
2111         hda = container_of(chip, struct hda_intel, chip);
2112
2113         pci_set_drvdata(pci, card);
2114
2115         err = register_vga_switcheroo(chip);
2116         if (err < 0) {
2117                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2118                 goto out_free;
2119         }
2120
2121         if (check_hdmi_disabled(pci)) {
2122                 dev_info(card->dev, "VGA controller is disabled\n");
2123                 dev_info(card->dev, "Delaying initialization\n");
2124                 chip->disabled = true;
2125         }
2126
2127         schedule_probe = !chip->disabled;
2128
2129 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2130         if (patch[dev] && *patch[dev]) {
2131                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2132                          patch[dev]);
2133                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2134                                               &pci->dev, GFP_KERNEL, card,
2135                                               azx_firmware_cb);
2136                 if (err < 0)
2137                         goto out_free;
2138                 schedule_probe = false; /* continued in azx_firmware_cb() */
2139         }
2140 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2141
2142 #ifndef CONFIG_SND_HDA_I915
2143         if (CONTROLLER_IN_GPU(pci))
2144                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2145 #endif
2146
2147         if (schedule_probe)
2148                 schedule_work(&hda->probe_work);
2149
2150         dev++;
2151         if (chip->disabled)
2152                 complete_all(&hda->probe_wait);
2153         return 0;
2154
2155 out_free:
2156         snd_card_free(card);
2157         return err;
2158 }
2159
2160 #ifdef CONFIG_PM
2161 /* On some boards setting power_save to a non 0 value leads to clicking /
2162  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2163  * figure out how to avoid these sounds, but that is not always feasible.
2164  * So we keep a list of devices where we disable powersaving as its known
2165  * to causes problems on these devices.
2166  */
2167 static struct snd_pci_quirk power_save_blacklist[] = {
2168         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2169         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2170         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2171         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2172         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2173         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2174         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2175         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2176         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2177         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2178         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2179         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2180         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2181         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2182         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2183         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2184         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2185         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2186         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2187         /* https://bugs.launchpad.net/bugs/1821663 */
2188         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2189         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2190         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2191         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2192         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2193         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2194         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2195         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2196         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2197         /* https://bugs.launchpad.net/bugs/1821663 */
2198         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2199         {}
2200 };
2201 #endif /* CONFIG_PM */
2202
2203 static void set_default_power_save(struct azx *chip)
2204 {
2205         int val = power_save;
2206
2207 #ifdef CONFIG_PM
2208         if (pm_blacklist) {
2209                 const struct snd_pci_quirk *q;
2210
2211                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2212                 if (q && val) {
2213                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2214                                  q->subvendor, q->subdevice);
2215                         val = 0;
2216                 }
2217         }
2218 #endif /* CONFIG_PM */
2219         snd_hda_set_power_save(&chip->bus, val * 1000);
2220 }
2221
2222 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2223 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2224         [AZX_DRIVER_NVIDIA] = 8,
2225         [AZX_DRIVER_TERA] = 1,
2226 };
2227
2228 static int azx_probe_continue(struct azx *chip)
2229 {
2230         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2231         struct hdac_bus *bus = azx_bus(chip);
2232         struct pci_dev *pci = chip->pci;
2233         int dev = chip->dev_index;
2234         int err;
2235
2236         to_hda_bus(bus)->bus_probing = 1;
2237         hda->probe_continued = 1;
2238
2239         /* bind with i915 if needed */
2240         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2241                 err = snd_hdac_i915_init(bus);
2242                 if (err < 0) {
2243                         /* if the controller is bound only with HDMI/DP
2244                          * (for HSW and BDW), we need to abort the probe;
2245                          * for other chips, still continue probing as other
2246                          * codecs can be on the same link.
2247                          */
2248                         if (CONTROLLER_IN_GPU(pci)) {
2249                                 dev_err(chip->card->dev,
2250                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2251                                 goto out_free;
2252                         } else {
2253                                 /* don't bother any longer */
2254                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2255                         }
2256                 }
2257
2258                 /* HSW/BDW controllers need this power */
2259                 if (CONTROLLER_IN_GPU(pci))
2260                         hda->need_i915_power = 1;
2261         }
2262
2263         /* Request display power well for the HDA controller or codec. For
2264          * Haswell/Broadwell, both the display HDA controller and codec need
2265          * this power. For other platforms, like Baytrail/Braswell, only the
2266          * display codec needs the power and it can be released after probe.
2267          */
2268         display_power(chip, true);
2269
2270         err = azx_first_init(chip);
2271         if (err < 0)
2272                 goto out_free;
2273
2274 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2275         chip->beep_mode = beep_mode[dev];
2276 #endif
2277
2278         /* create codec instances */
2279         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2280         if (err < 0)
2281                 goto out_free;
2282
2283 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2284         if (chip->fw) {
2285                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2286                                          chip->fw->data);
2287                 if (err < 0)
2288                         goto out_free;
2289 #ifndef CONFIG_PM
2290                 release_firmware(chip->fw); /* no longer needed */
2291                 chip->fw = NULL;
2292 #endif
2293         }
2294 #endif
2295         if ((probe_only[dev] & 1) == 0) {
2296                 err = azx_codec_configure(chip);
2297                 if (err < 0)
2298                         goto out_free;
2299         }
2300
2301         err = snd_card_register(chip->card);
2302         if (err < 0)
2303                 goto out_free;
2304
2305         setup_vga_switcheroo_runtime_pm(chip);
2306
2307         chip->running = 1;
2308         azx_add_card_list(chip);
2309
2310         set_default_power_save(chip);
2311
2312         if (azx_has_pm_runtime(chip))
2313                 pm_runtime_put_autosuspend(&pci->dev);
2314
2315 out_free:
2316         if (err < 0 || !hda->need_i915_power)
2317                 display_power(chip, false);
2318         if (err < 0)
2319                 hda->init_failed = 1;
2320         complete_all(&hda->probe_wait);
2321         to_hda_bus(bus)->bus_probing = 0;
2322         return err;
2323 }
2324
2325 static void azx_remove(struct pci_dev *pci)
2326 {
2327         struct snd_card *card = pci_get_drvdata(pci);
2328         struct azx *chip;
2329         struct hda_intel *hda;
2330
2331         if (card) {
2332                 /* cancel the pending probing work */
2333                 chip = card->private_data;
2334                 hda = container_of(chip, struct hda_intel, chip);
2335                 /* FIXME: below is an ugly workaround.
2336                  * Both device_release_driver() and driver_probe_device()
2337                  * take *both* the device's and its parent's lock before
2338                  * calling the remove() and probe() callbacks.  The codec
2339                  * probe takes the locks of both the codec itself and its
2340                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2341                  * the PCI controller is unbound, it takes its lock, too
2342                  * ==> ouch, a deadlock!
2343                  * As a workaround, we unlock temporarily here the controller
2344                  * device during cancel_work_sync() call.
2345                  */
2346                 device_unlock(&pci->dev);
2347                 cancel_work_sync(&hda->probe_work);
2348                 device_lock(&pci->dev);
2349
2350                 snd_card_free(card);
2351         }
2352 }
2353
2354 static void azx_shutdown(struct pci_dev *pci)
2355 {
2356         struct snd_card *card = pci_get_drvdata(pci);
2357         struct azx *chip;
2358
2359         if (!card)
2360                 return;
2361         chip = card->private_data;
2362         if (chip && chip->running)
2363                 azx_stop_chip(chip);
2364 }
2365
2366 /* PCI IDs */
2367 static const struct pci_device_id azx_ids[] = {
2368         /* CPT */
2369         { PCI_DEVICE(0x8086, 0x1c20),
2370           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2371         /* PBG */
2372         { PCI_DEVICE(0x8086, 0x1d20),
2373           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2374         /* Panther Point */
2375         { PCI_DEVICE(0x8086, 0x1e20),
2376           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2377         /* Lynx Point */
2378         { PCI_DEVICE(0x8086, 0x8c20),
2379           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2380         /* 9 Series */
2381         { PCI_DEVICE(0x8086, 0x8ca0),
2382           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2383         /* Wellsburg */
2384         { PCI_DEVICE(0x8086, 0x8d20),
2385           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2386         { PCI_DEVICE(0x8086, 0x8d21),
2387           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2388         /* Lewisburg */
2389         { PCI_DEVICE(0x8086, 0xa1f0),
2390           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2391         { PCI_DEVICE(0x8086, 0xa270),
2392           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2393         /* Lynx Point-LP */
2394         { PCI_DEVICE(0x8086, 0x9c20),
2395           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2396         /* Lynx Point-LP */
2397         { PCI_DEVICE(0x8086, 0x9c21),
2398           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2399         /* Wildcat Point-LP */
2400         { PCI_DEVICE(0x8086, 0x9ca0),
2401           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2402         /* Sunrise Point */
2403         { PCI_DEVICE(0x8086, 0xa170),
2404           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2405         /* Sunrise Point-LP */
2406         { PCI_DEVICE(0x8086, 0x9d70),
2407           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2408         /* Kabylake */
2409         { PCI_DEVICE(0x8086, 0xa171),
2410           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2411         /* Kabylake-LP */
2412         { PCI_DEVICE(0x8086, 0x9d71),
2413           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2414         /* Kabylake-H */
2415         { PCI_DEVICE(0x8086, 0xa2f0),
2416           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2417         /* Coffelake */
2418         { PCI_DEVICE(0x8086, 0xa348),
2419           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2420         /* Cannonlake */
2421         { PCI_DEVICE(0x8086, 0x9dc8),
2422           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2423         /* CometLake-LP */
2424         { PCI_DEVICE(0x8086, 0x02C8),
2425           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2426         /* CometLake-H */
2427         { PCI_DEVICE(0x8086, 0x06C8),
2428           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2429         /* CometLake-S */
2430         { PCI_DEVICE(0x8086, 0xa3f0),
2431           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2432         /* Icelake */
2433         { PCI_DEVICE(0x8086, 0x34c8),
2434           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2435         /* Jasperlake */
2436         { PCI_DEVICE(0x8086, 0x38c8),
2437           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2438         /* Tigerlake */
2439         { PCI_DEVICE(0x8086, 0xa0c8),
2440           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2441         /* Elkhart Lake */
2442         { PCI_DEVICE(0x8086, 0x4b55),
2443           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2444         /* Broxton-P(Apollolake) */
2445         { PCI_DEVICE(0x8086, 0x5a98),
2446           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2447         /* Broxton-T */
2448         { PCI_DEVICE(0x8086, 0x1a98),
2449           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2450         /* Gemini-Lake */
2451         { PCI_DEVICE(0x8086, 0x3198),
2452           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2453         /* Haswell */
2454         { PCI_DEVICE(0x8086, 0x0a0c),
2455           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2456         { PCI_DEVICE(0x8086, 0x0c0c),
2457           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2458         { PCI_DEVICE(0x8086, 0x0d0c),
2459           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2460         /* Broadwell */
2461         { PCI_DEVICE(0x8086, 0x160c),
2462           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2463         /* 5 Series/3400 */
2464         { PCI_DEVICE(0x8086, 0x3b56),
2465           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2466         /* Poulsbo */
2467         { PCI_DEVICE(0x8086, 0x811b),
2468           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2469         /* Oaktrail */
2470         { PCI_DEVICE(0x8086, 0x080a),
2471           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2472         /* BayTrail */
2473         { PCI_DEVICE(0x8086, 0x0f04),
2474           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2475         /* Braswell */
2476         { PCI_DEVICE(0x8086, 0x2284),
2477           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2478         /* ICH6 */
2479         { PCI_DEVICE(0x8086, 0x2668),
2480           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2481         /* ICH7 */
2482         { PCI_DEVICE(0x8086, 0x27d8),
2483           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2484         /* ESB2 */
2485         { PCI_DEVICE(0x8086, 0x269a),
2486           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2487         /* ICH8 */
2488         { PCI_DEVICE(0x8086, 0x284b),
2489           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2490         /* ICH9 */
2491         { PCI_DEVICE(0x8086, 0x293e),
2492           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2493         /* ICH9 */
2494         { PCI_DEVICE(0x8086, 0x293f),
2495           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2496         /* ICH10 */
2497         { PCI_DEVICE(0x8086, 0x3a3e),
2498           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2499         /* ICH10 */
2500         { PCI_DEVICE(0x8086, 0x3a6e),
2501           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2502         /* Generic Intel */
2503         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2504           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2505           .class_mask = 0xffffff,
2506           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2507         /* ATI SB 450/600/700/800/900 */
2508         { PCI_DEVICE(0x1002, 0x437b),
2509           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2510         { PCI_DEVICE(0x1002, 0x4383),
2511           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2512         /* AMD Hudson */
2513         { PCI_DEVICE(0x1022, 0x780d),
2514           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2515         /* AMD, X370 & co */
2516         { PCI_DEVICE(0x1022, 0x1457),
2517           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2518         /* AMD, X570 & co */
2519         { PCI_DEVICE(0x1022, 0x1487),
2520           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2521         /* AMD Stoney */
2522         { PCI_DEVICE(0x1022, 0x157a),
2523           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2524                          AZX_DCAPS_PM_RUNTIME },
2525         /* AMD Raven */
2526         { PCI_DEVICE(0x1022, 0x15e3),
2527           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2528         /* ATI HDMI */
2529         { PCI_DEVICE(0x1002, 0x0002),
2530           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2531         { PCI_DEVICE(0x1002, 0x1308),
2532           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2533         { PCI_DEVICE(0x1002, 0x157a),
2534           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2535         { PCI_DEVICE(0x1002, 0x15b3),
2536           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2537         { PCI_DEVICE(0x1002, 0x793b),
2538           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2539         { PCI_DEVICE(0x1002, 0x7919),
2540           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2541         { PCI_DEVICE(0x1002, 0x960f),
2542           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2543         { PCI_DEVICE(0x1002, 0x970f),
2544           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2545         { PCI_DEVICE(0x1002, 0x9840),
2546           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2547         { PCI_DEVICE(0x1002, 0xaa00),
2548           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2549         { PCI_DEVICE(0x1002, 0xaa08),
2550           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2551         { PCI_DEVICE(0x1002, 0xaa10),
2552           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2553         { PCI_DEVICE(0x1002, 0xaa18),
2554           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2555         { PCI_DEVICE(0x1002, 0xaa20),
2556           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2557         { PCI_DEVICE(0x1002, 0xaa28),
2558           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2559         { PCI_DEVICE(0x1002, 0xaa30),
2560           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2561         { PCI_DEVICE(0x1002, 0xaa38),
2562           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2563         { PCI_DEVICE(0x1002, 0xaa40),
2564           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2565         { PCI_DEVICE(0x1002, 0xaa48),
2566           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2567         { PCI_DEVICE(0x1002, 0xaa50),
2568           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2569         { PCI_DEVICE(0x1002, 0xaa58),
2570           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2571         { PCI_DEVICE(0x1002, 0xaa60),
2572           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2573         { PCI_DEVICE(0x1002, 0xaa68),
2574           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2575         { PCI_DEVICE(0x1002, 0xaa80),
2576           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2577         { PCI_DEVICE(0x1002, 0xaa88),
2578           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2579         { PCI_DEVICE(0x1002, 0xaa90),
2580           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581         { PCI_DEVICE(0x1002, 0xaa98),
2582           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583         { PCI_DEVICE(0x1002, 0x9902),
2584           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2585         { PCI_DEVICE(0x1002, 0xaaa0),
2586           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2587         { PCI_DEVICE(0x1002, 0xaaa8),
2588           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2589         { PCI_DEVICE(0x1002, 0xaab0),
2590           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2591         { PCI_DEVICE(0x1002, 0xaac0),
2592           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2593         { PCI_DEVICE(0x1002, 0xaac8),
2594           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2595         { PCI_DEVICE(0x1002, 0xaad8),
2596           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2597           AZX_DCAPS_PM_RUNTIME },
2598         { PCI_DEVICE(0x1002, 0xaae0),
2599           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2600           AZX_DCAPS_PM_RUNTIME },
2601         { PCI_DEVICE(0x1002, 0xaae8),
2602           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2603           AZX_DCAPS_PM_RUNTIME },
2604         { PCI_DEVICE(0x1002, 0xaaf0),
2605           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2606           AZX_DCAPS_PM_RUNTIME },
2607         { PCI_DEVICE(0x1002, 0xaaf8),
2608           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2609           AZX_DCAPS_PM_RUNTIME },
2610         { PCI_DEVICE(0x1002, 0xab00),
2611           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2612           AZX_DCAPS_PM_RUNTIME },
2613         { PCI_DEVICE(0x1002, 0xab08),
2614           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2615           AZX_DCAPS_PM_RUNTIME },
2616         { PCI_DEVICE(0x1002, 0xab10),
2617           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2618           AZX_DCAPS_PM_RUNTIME },
2619         { PCI_DEVICE(0x1002, 0xab18),
2620           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2621           AZX_DCAPS_PM_RUNTIME },
2622         { PCI_DEVICE(0x1002, 0xab20),
2623           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2624           AZX_DCAPS_PM_RUNTIME },
2625         { PCI_DEVICE(0x1002, 0xab38),
2626           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2627           AZX_DCAPS_PM_RUNTIME },
2628         /* VIA VT8251/VT8237A */
2629         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2630         /* VIA GFX VT7122/VX900 */
2631         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2632         /* VIA GFX VT6122/VX11 */
2633         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2634         /* SIS966 */
2635         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2636         /* ULI M5461 */
2637         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2638         /* NVIDIA MCP */
2639         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2640           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2641           .class_mask = 0xffffff,
2642           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2643         /* Teradici */
2644         { PCI_DEVICE(0x6549, 0x1200),
2645           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2646         { PCI_DEVICE(0x6549, 0x2200),
2647           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2648         /* Creative X-Fi (CA0110-IBG) */
2649         /* CTHDA chips */
2650         { PCI_DEVICE(0x1102, 0x0010),
2651           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2652         { PCI_DEVICE(0x1102, 0x0012),
2653           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2654 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2655         /* the following entry conflicts with snd-ctxfi driver,
2656          * as ctxfi driver mutates from HD-audio to native mode with
2657          * a special command sequence.
2658          */
2659         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2660           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2661           .class_mask = 0xffffff,
2662           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2663           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2664 #else
2665         /* this entry seems still valid -- i.e. without emu20kx chip */
2666         { PCI_DEVICE(0x1102, 0x0009),
2667           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2668           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2669 #endif
2670         /* CM8888 */
2671         { PCI_DEVICE(0x13f6, 0x5011),
2672           .driver_data = AZX_DRIVER_CMEDIA |
2673           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2674         /* Vortex86MX */
2675         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2676         /* VMware HDAudio */
2677         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2678         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2679         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2680           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2681           .class_mask = 0xffffff,
2682           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2683         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2684           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2685           .class_mask = 0xffffff,
2686           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2687         /* Zhaoxin */
2688         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2689         { 0, }
2690 };
2691 MODULE_DEVICE_TABLE(pci, azx_ids);
2692
2693 /* pci_driver definition */
2694 static struct pci_driver azx_driver = {
2695         .name = KBUILD_MODNAME,
2696         .id_table = azx_ids,
2697         .probe = azx_probe,
2698         .remove = azx_remove,
2699         .shutdown = azx_shutdown,
2700         .driver = {
2701                 .pm = AZX_PM_OPS,
2702         },
2703 };
2704
2705 module_pci_driver(azx_driver);