sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include <sound/hda_codec.h>
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 static bool pm_blacklist = true;
 190 module_param(pm_blacklist, bool, 0644);
 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 192
 193 /* reset the HD-audio controller in power save mode.
 194  * this may give more power-saving, but will take longer time to
 195  * wake up.
 196  */
 197 static bool power_save_controller = 1;
 198 module_param(power_save_controller, bool, 0644);
 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 200 #else
 201 #define power_save      0
 202 #endif /* CONFIG_PM */
 203
 204 static int align_buffer_size = -1;
 205 module_param(align_buffer_size, bint, 0644);
 206 MODULE_PARM_DESC(align_buffer_size,
 207                 "Force buffer and period sizes to be multiple of 128 bytes.");
 208
 209 #ifdef CONFIG_X86
 210 static int hda_snoop = -1;
 211 module_param_named(snoop, hda_snoop, bint, 0444);
 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 213 #else
 214 #define hda_snoop               true
 215 #endif
 216
 217
 218 MODULE_LICENSE("GPL");
 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 220                          "{Intel, ICH6M},"
 221                          "{Intel, ICH7},"
 222                          "{Intel, ESB2},"
 223                          "{Intel, ICH8},"
 224                          "{Intel, ICH9},"
 225                          "{Intel, ICH10},"
 226                          "{Intel, PCH},"
 227                          "{Intel, CPT},"
 228                          "{Intel, PPT},"
 229                          "{Intel, LPT},"
 230                          "{Intel, LPT_LP},"
 231                          "{Intel, WPT_LP},"
 232                          "{Intel, SPT},"
 233                          "{Intel, SPT_LP},"
 234                          "{Intel, HPT},"
 235                          "{Intel, PBG},"
 236                          "{Intel, SCH},"
 237                          "{ATI, SB450},"
 238                          "{ATI, SB600},"
 239                          "{ATI, RS600},"
 240                          "{ATI, RS690},"
 241                          "{ATI, RS780},"
 242                          "{ATI, R600},"
 243                          "{ATI, RV630},"
 244                          "{ATI, RV610},"
 245                          "{ATI, RV670},"
 246                          "{ATI, RV635},"
 247                          "{ATI, RV620},"
 248                          "{ATI, RV770},"
 249                          "{VIA, VT8251},"
 250                          "{VIA, VT8237A},"
 251                          "{SiS, SIS966},"
 252                          "{ULI, M5461}}");
 253 MODULE_DESCRIPTION("Intel HDA driver");
 254
 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 257 #define SUPPORT_VGA_SWITCHEROO
 258 #endif
 259 #endif
 260
 261
 262 /*
 263  */
 264
 265 /* driver types */
 266 enum {
 267         AZX_DRIVER_ICH,
 268         AZX_DRIVER_PCH,
 269         AZX_DRIVER_SCH,
 270         AZX_DRIVER_SKL,
 271         AZX_DRIVER_HDMI,
 272         AZX_DRIVER_ATI,
 273         AZX_DRIVER_ATIHDMI,
 274         AZX_DRIVER_ATIHDMI_NS,
 275         AZX_DRIVER_VIA,
 276         AZX_DRIVER_SIS,
 277         AZX_DRIVER_ULI,
 278         AZX_DRIVER_NVIDIA,
 279         AZX_DRIVER_TERA,
 280         AZX_DRIVER_CTX,
 281         AZX_DRIVER_CTHDA,
 282         AZX_DRIVER_CMEDIA,
 283         AZX_DRIVER_GENERIC,
 284         AZX_NUM_DRIVERS, /* keep this as last entry */
 285 };
 286
 287 #define azx_get_snoop_type(chip) \
 288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 290
 291 /* quirks for old Intel chipsets */
 292 #define AZX_DCAPS_INTEL_ICH \
 293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 294
 295 /* quirks for Intel PCH */
 296 #define AZX_DCAPS_INTEL_PCH_BASE \
 297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 301 #define AZX_DCAPS_INTEL_PCH_NOPM \
 302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 303
 304 /* PCH for HSW/BDW; with runtime PM */
 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 306 #define AZX_DCAPS_INTEL_PCH \
 307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 308
 309 /* HSW HDMI */
 310 #define AZX_DCAPS_INTEL_HASWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 316 #define AZX_DCAPS_INTEL_BROADWELL \
 317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 319          AZX_DCAPS_SNOOP_TYPE(SCH))
 320
 321 #define AZX_DCAPS_INTEL_BAYTRAIL \
 322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BRASWELL \
 325         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 326          AZX_DCAPS_I915_COMPONENT)
 327
 328 #define AZX_DCAPS_INTEL_SKYLAKE \
 329         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 330          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 331
 332 #define AZX_DCAPS_INTEL_BROXTON \
 333         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 334          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 335
 336 /* quirks for ATI SB / AMD Hudson */
 337 #define AZX_DCAPS_PRESET_ATI_SB \
 338         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 339          AZX_DCAPS_SNOOP_TYPE(ATI))
 340
 341 /* quirks for ATI/AMD HDMI */
 342 #define AZX_DCAPS_PRESET_ATI_HDMI \
 343         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 344          AZX_DCAPS_NO_MSI64)
 345
 346 /* quirks for ATI HDMI with snoop off */
 347 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 348         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 349
 350 /* quirks for Nvidia */
 351 #define AZX_DCAPS_PRESET_NVIDIA \
 352         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 353          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 354
 355 #define AZX_DCAPS_PRESET_CTHDA \
 356         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 357          AZX_DCAPS_NO_64BIT |\
 358          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 359
 360 /*
 361  * vga_switcheroo support
 362  */
 363 #ifdef SUPPORT_VGA_SWITCHEROO
 364 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 365 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 366 #else
 367 #define use_vga_switcheroo(chip)        0
 368 #define needs_eld_notify_link(chip)     false
 369 #endif
 370
 371 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 372                                         ((pci)->device == 0x0c0c) || \
 373                                         ((pci)->device == 0x0d0c) || \
 374                                         ((pci)->device == 0x160c))
 375
 376 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 377 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 378
 379 static char *driver_short_names[] = {
 380         [AZX_DRIVER_ICH] = "HDA Intel",
 381         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 382         [AZX_DRIVER_SCH] = "HDA Intel MID",
 383         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 384         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 385         [AZX_DRIVER_ATI] = "HDA ATI SB",
 386         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 387         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 388         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 389         [AZX_DRIVER_SIS] = "HDA SIS966",
 390         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 391         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 392         [AZX_DRIVER_TERA] = "HDA Teradici",
 393         [AZX_DRIVER_CTX] = "HDA Creative",
 394         [AZX_DRIVER_CTHDA] = "HDA Creative",
 395         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 396         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 397 };
 398
 399 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 400 static void set_default_power_save(struct azx *chip);
 401
 402 /*
 403  * initialize the PCI registers
 404  */
 405 /* update bits in a PCI register byte */
 406 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 407                             unsigned char mask, unsigned char val)
 408 {
 409         unsigned char data;
 410
 411         pci_read_config_byte(pci, reg, &data);
 412         data &= ~mask;
 413         data |= (val & mask);
 414         pci_write_config_byte(pci, reg, data);
 415 }
 416
 417 static void azx_init_pci(struct azx *chip)
 418 {
 419         int snoop_type = azx_get_snoop_type(chip);
 420
 421         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 422          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 423          * Ensuring these bits are 0 clears playback static on some HD Audio
 424          * codecs.
 425          * The PCI register TCSEL is defined in the Intel manuals.
 426          */
 427         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 428                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 429                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 430         }
 431
 432         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 433          * we need to enable snoop.
 434          */
 435         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 436                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 437                         azx_snoop(chip));
 438                 update_pci_byte(chip->pci,
 439                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 440                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 441         }
 442
 443         /* For NVIDIA HDA, enable snoop */
 444         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 445                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 446                         azx_snoop(chip));
 447                 update_pci_byte(chip->pci,
 448                                 NVIDIA_HDA_TRANSREG_ADDR,
 449                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 450                 update_pci_byte(chip->pci,
 451                                 NVIDIA_HDA_ISTRM_COH,
 452                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 453                 update_pci_byte(chip->pci,
 454                                 NVIDIA_HDA_OSTRM_COH,
 455                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 456         }
 457
 458         /* Enable SCH/PCH snoop if needed */
 459         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 460                 unsigned short snoop;
 461                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 462                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 463                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 464                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 465                         if (!azx_snoop(chip))
 466                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 467                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 468                         pci_read_config_word(chip->pci,
 469                                 INTEL_SCH_HDA_DEVC, &snoop);
 470                 }
 471                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 472                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 473                         "Disabled" : "Enabled");
 474         }
 475 }
 476
 477 /*
 478  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 479  * and makes an audio stream sensitive to system latencies when
 480  * 24/32 bits are playing.
 481  * Adjusting threshold of DMA fifo to force the DMA request
 482  * sooner to improve latency tolerance at the expense of power.
 483  */
 484 static void bxt_reduce_dma_latency(struct azx *chip)
 485 {
 486         u32 val;
 487
 488         val = azx_readl(chip, VS_EM4L);
 489         val &= (0x3 << 20);
 490         azx_writel(chip, VS_EM4L, val);
 491 }
 492
 493 /*
 494  * ML_LCAP bits:
 495  *  bit 0: 6 MHz Supported
 496  *  bit 1: 12 MHz Supported
 497  *  bit 2: 24 MHz Supported
 498  *  bit 3: 48 MHz Supported
 499  *  bit 4: 96 MHz Supported
 500  *  bit 5: 192 MHz Supported
 501  */
 502 static int intel_get_lctl_scf(struct azx *chip)
 503 {
 504         struct hdac_bus *bus = azx_bus(chip);
 505         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 506         u32 val, t;
 507         int i;
 508
 509         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 510
 511         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 512                 t = preferred_bits[i];
 513                 if (val & (1 << t))
 514                         return t;
 515         }
 516
 517         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 518         return 0;
 519 }
 520
 521 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 522 {
 523         struct hdac_bus *bus = azx_bus(chip);
 524         u32 val;
 525         int timeout;
 526
 527         /*
 528          * the codecs are sharing the first link setting by default
 529          * If other links are enabled for stream, they need similar fix
 530          */
 531         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 532         val &= ~AZX_MLCTL_SPA;
 533         val |= state << AZX_MLCTL_SPA_SHIFT;
 534         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 535         /* wait for CPA */
 536         timeout = 50;
 537         while (timeout) {
 538                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 539                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 540                         return 0;
 541                 timeout--;
 542                 udelay(10);
 543         }
 544
 545         return -1;
 546 }
 547
 548 static void intel_init_lctl(struct azx *chip)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         u32 val;
 552         int ret;
 553
 554         /* 0. check lctl register value is correct or not */
 555         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 556         /* if SCF is already set, let's use it */
 557         if ((val & ML_LCTL_SCF_MASK) != 0)
 558                 return;
 559
 560         /*
 561          * Before operating on SPA, CPA must match SPA.
 562          * Any deviation may result in undefined behavior.
 563          */
 564         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 565                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 566                 return;
 567
 568         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 569         ret = intel_ml_lctl_set_power(chip, 0);
 570         udelay(100);
 571         if (ret)
 572                 goto set_spa;
 573
 574         /* 2. update SCF to select a properly audio clock*/
 575         val &= ~ML_LCTL_SCF_MASK;
 576         val |= intel_get_lctl_scf(chip);
 577         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 578
 579 set_spa:
 580         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 581         intel_ml_lctl_set_power(chip, 1);
 582         udelay(100);
 583 }
 584
 585 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 586 {
 587         struct hdac_bus *bus = azx_bus(chip);
 588         struct pci_dev *pci = chip->pci;
 589         u32 val;
 590
 591         snd_hdac_set_codec_wakeup(bus, true);
 592         if (chip->driver_type == AZX_DRIVER_SKL) {
 593                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 594                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 595                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 596         }
 597         azx_init_chip(chip, full_reset);
 598         if (chip->driver_type == AZX_DRIVER_SKL) {
 599                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 600                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 601                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 602         }
 603
 604         snd_hdac_set_codec_wakeup(bus, false);
 605
 606         /* reduce dma latency to avoid noise */
 607         if (IS_BXT(pci))
 608                 bxt_reduce_dma_latency(chip);
 609
 610         if (bus->mlcap != NULL)
 611                 intel_init_lctl(chip);
 612 }
 613
 614 /* calculate runtime delay from LPIB */
 615 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 616                                    unsigned int pos)
 617 {
 618         struct snd_pcm_substream *substream = azx_dev->core.substream;
 619         int stream = substream->stream;
 620         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 621         int delay;
 622
 623         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 624                 delay = pos - lpib_pos;
 625         else
 626                 delay = lpib_pos - pos;
 627         if (delay < 0) {
 628                 if (delay >= azx_dev->core.delay_negative_threshold)
 629                         delay = 0;
 630                 else
 631                         delay += azx_dev->core.bufsize;
 632         }
 633
 634         if (delay >= azx_dev->core.period_bytes) {
 635                 dev_info(chip->card->dev,
 636                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 637                          delay, azx_dev->core.period_bytes);
 638                 delay = 0;
 639                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 640                 chip->get_delay[stream] = NULL;
 641         }
 642
 643         return bytes_to_frames(substream->runtime, delay);
 644 }
 645
 646 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 647
 648 /* called from IRQ */
 649 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 650 {
 651         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 652         int ok;
 653
 654         ok = azx_position_ok(chip, azx_dev);
 655         if (ok == 1) {
 656                 azx_dev->irq_pending = 0;
 657                 return ok;
 658         } else if (ok == 0) {
 659                 /* bogus IRQ, process it later */
 660                 azx_dev->irq_pending = 1;
 661                 schedule_work(&hda->irq_pending_work);
 662         }
 663         return 0;
 664 }
 665
 666 #define display_power(chip, enable) \
 667         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 668
 669 /*
 670  * Check whether the current DMA position is acceptable for updating
 671  * periods.  Returns non-zero if it's OK.
 672  *
 673  * Many HD-audio controllers appear pretty inaccurate about
 674  * the update-IRQ timing.  The IRQ is issued before actually the
 675  * data is processed.  So, we need to process it afterwords in a
 676  * workqueue.
 677  */
 678 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 679 {
 680         struct snd_pcm_substream *substream = azx_dev->core.substream;
 681         int stream = substream->stream;
 682         u32 wallclk;
 683         unsigned int pos;
 684
 685         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 686         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 687                 return -1;      /* bogus (too early) interrupt */
 688
 689         if (chip->get_position[stream])
 690                 pos = chip->get_position[stream](chip, azx_dev);
 691         else { /* use the position buffer as default */
 692                 pos = azx_get_pos_posbuf(chip, azx_dev);
 693                 if (!pos || pos == (u32)-1) {
 694                         dev_info(chip->card->dev,
 695                                  "Invalid position buffer, using LPIB read method instead.\n");
 696                         chip->get_position[stream] = azx_get_pos_lpib;
 697                         if (chip->get_position[0] == azx_get_pos_lpib &&
 698                             chip->get_position[1] == azx_get_pos_lpib)
 699                                 azx_bus(chip)->use_posbuf = false;
 700                         pos = azx_get_pos_lpib(chip, azx_dev);
 701                         chip->get_delay[stream] = NULL;
 702                 } else {
 703                         chip->get_position[stream] = azx_get_pos_posbuf;
 704                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 705                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 706                 }
 707         }
 708
 709         if (pos >= azx_dev->core.bufsize)
 710                 pos = 0;
 711
 712         if (WARN_ONCE(!azx_dev->core.period_bytes,
 713                       "hda-intel: zero azx_dev->period_bytes"))
 714                 return -1; /* this shouldn't happen! */
 715         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 716             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 717                 /* NG - it's below the first next period boundary */
 718                 return chip->bdl_pos_adj ? 0 : -1;
 719         azx_dev->core.start_wallclk += wallclk;
 720         return 1; /* OK, it's fine */
 721 }
 722
 723 /*
 724  * The work for pending PCM period updates.
 725  */
 726 static void azx_irq_pending_work(struct work_struct *work)
 727 {
 728         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 729         struct azx *chip = &hda->chip;
 730         struct hdac_bus *bus = azx_bus(chip);
 731         struct hdac_stream *s;
 732         int pending, ok;
 733
 734         if (!hda->irq_pending_warned) {
 735                 dev_info(chip->card->dev,
 736                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 737                          chip->card->number);
 738                 hda->irq_pending_warned = 1;
 739         }
 740
 741         for (;;) {
 742                 pending = 0;
 743                 spin_lock_irq(&bus->reg_lock);
 744                 list_for_each_entry(s, &bus->stream_list, list) {
 745                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 746                         if (!azx_dev->irq_pending ||
 747                             !s->substream ||
 748                             !s->running)
 749                                 continue;
 750                         ok = azx_position_ok(chip, azx_dev);
 751                         if (ok > 0) {
 752                                 azx_dev->irq_pending = 0;
 753                                 spin_unlock(&bus->reg_lock);
 754                                 snd_pcm_period_elapsed(s->substream);
 755                                 spin_lock(&bus->reg_lock);
 756                         } else if (ok < 0) {
 757                                 pending = 0;    /* too early */
 758                         } else
 759                                 pending++;
 760                 }
 761                 spin_unlock_irq(&bus->reg_lock);
 762                 if (!pending)
 763                         return;
 764                 msleep(1);
 765         }
 766 }
 767
 768 /* clear irq_pending flags and assure no on-going workq */
 769 static void azx_clear_irq_pending(struct azx *chip)
 770 {
 771         struct hdac_bus *bus = azx_bus(chip);
 772         struct hdac_stream *s;
 773
 774         spin_lock_irq(&bus->reg_lock);
 775         list_for_each_entry(s, &bus->stream_list, list) {
 776                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 777                 azx_dev->irq_pending = 0;
 778         }
 779         spin_unlock_irq(&bus->reg_lock);
 780 }
 781
 782 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 783 {
 784         struct hdac_bus *bus = azx_bus(chip);
 785
 786         if (request_irq(chip->pci->irq, azx_interrupt,
 787                         chip->msi ? 0 : IRQF_SHARED,
 788                         chip->card->irq_descr, chip)) {
 789                 dev_err(chip->card->dev,
 790                         "unable to grab IRQ %d, disabling device\n",
 791                         chip->pci->irq);
 792                 if (do_disconnect)
 793                         snd_card_disconnect(chip->card);
 794                 return -1;
 795         }
 796         bus->irq = chip->pci->irq;
 797         pci_intx(chip->pci, !chip->msi);
 798         return 0;
 799 }
 800
 801 /* get the current DMA position with correction on VIA chips */
 802 static unsigned int azx_via_get_position(struct azx *chip,
 803                                          struct azx_dev *azx_dev)
 804 {
 805         unsigned int link_pos, mini_pos, bound_pos;
 806         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 807         unsigned int fifo_size;
 808
 809         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 810         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 811                 /* Playback, no problem using link position */
 812                 return link_pos;
 813         }
 814
 815         /* Capture */
 816         /* For new chipset,
 817          * use mod to get the DMA position just like old chipset
 818          */
 819         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 820         mod_dma_pos %= azx_dev->core.period_bytes;
 821
 822         /* azx_dev->fifo_size can't get FIFO size of in stream.
 823          * Get from base address + offset.
 824          */
 825         fifo_size = readw(azx_bus(chip)->remap_addr +
 826                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 827
 828         if (azx_dev->insufficient) {
 829                 /* Link position never gather than FIFO size */
 830                 if (link_pos <= fifo_size)
 831                         return 0;
 832
 833                 azx_dev->insufficient = 0;
 834         }
 835
 836         if (link_pos <= fifo_size)
 837                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 838         else
 839                 mini_pos = link_pos - fifo_size;
 840
 841         /* Find nearest previous boudary */
 842         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 843         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 844         if (mod_link_pos >= fifo_size)
 845                 bound_pos = link_pos - mod_link_pos;
 846         else if (mod_dma_pos >= mod_mini_pos)
 847                 bound_pos = mini_pos - mod_mini_pos;
 848         else {
 849                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 850                 if (bound_pos >= azx_dev->core.bufsize)
 851                         bound_pos = 0;
 852         }
 853
 854         /* Calculate real DMA position we want */
 855         return bound_pos + mod_dma_pos;
 856 }
 857
 858 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 859                                          struct azx_dev *azx_dev)
 860 {
 861         return _snd_hdac_chip_readl(azx_bus(chip),
 862                                     AZX_REG_VS_SDXDPIB_XBASE +
 863                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 864                                      azx_dev->core.index));
 865 }
 866
 867 /* get the current DMA position with correction on SKL+ chips */
 868 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 869 {
 870         /* DPIB register gives a more accurate position for playback */
 871         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 872                 return azx_skl_get_dpib_pos(chip, azx_dev);
 873
 874         /* For capture, we need to read posbuf, but it requires a delay
 875          * for the possible boundary overlap; the read of DPIB fetches the
 876          * actual posbuf
 877          */
 878         udelay(20);
 879         azx_skl_get_dpib_pos(chip, azx_dev);
 880         return azx_get_pos_posbuf(chip, azx_dev);
 881 }
 882
 883 #ifdef CONFIG_PM
 884 static DEFINE_MUTEX(card_list_lock);
 885 static LIST_HEAD(card_list);
 886
 887 static void azx_add_card_list(struct azx *chip)
 888 {
 889         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 890         mutex_lock(&card_list_lock);
 891         list_add(&hda->list, &card_list);
 892         mutex_unlock(&card_list_lock);
 893 }
 894
 895 static void azx_del_card_list(struct azx *chip)
 896 {
 897         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 898         mutex_lock(&card_list_lock);
 899         list_del_init(&hda->list);
 900         mutex_unlock(&card_list_lock);
 901 }
 902
 903 /* trigger power-save check at writing parameter */
 904 static int param_set_xint(const char *val, const struct kernel_param *kp)
 905 {
 906         struct hda_intel *hda;
 907         struct azx *chip;
 908         int prev = power_save;
 909         int ret = param_set_int(val, kp);
 910
 911         if (ret || prev == power_save)
 912                 return ret;
 913
 914         mutex_lock(&card_list_lock);
 915         list_for_each_entry(hda, &card_list, list) {
 916                 chip = &hda->chip;
 917                 if (!hda->probe_continued || chip->disabled)
 918                         continue;
 919                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 920         }
 921         mutex_unlock(&card_list_lock);
 922         return 0;
 923 }
 924
 925 /*
 926  * power management
 927  */
 928 static bool azx_is_pm_ready(struct snd_card *card)
 929 {
 930         struct azx *chip;
 931         struct hda_intel *hda;
 932
 933         if (!card)
 934                 return false;
 935         chip = card->private_data;
 936         hda = container_of(chip, struct hda_intel, chip);
 937         if (chip->disabled || hda->init_failed || !chip->running)
 938                 return false;
 939         return true;
 940 }
 941
 942 static void __azx_runtime_suspend(struct azx *chip)
 943 {
 944         azx_stop_chip(chip);
 945         azx_enter_link_reset(chip);
 946         azx_clear_irq_pending(chip);
 947         display_power(chip, false);
 948 }
 949
 950 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 951 {
 952         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 953         struct hdac_bus *bus = azx_bus(chip);
 954         struct hda_codec *codec;
 955         int status;
 956
 957         display_power(chip, true);
 958         if (hda->need_i915_power)
 959                 snd_hdac_i915_set_bclk(bus);
 960
 961         /* Read STATESTS before controller reset */
 962         status = azx_readw(chip, STATESTS);
 963
 964         azx_init_pci(chip);
 965         hda_intel_init_chip(chip, true);
 966
 967         if (status && from_rt) {
 968                 list_for_each_codec(codec, &chip->bus)
 969                         if (status & (1 << codec->addr))
 970                                 schedule_delayed_work(&codec->jackpoll_work,
 971                                                       codec->jackpoll_interval);
 972         }
 973
 974         /* power down again for link-controlled chips */
 975         if (!hda->need_i915_power)
 976                 display_power(chip, false);
 977 }
 978
 979 #ifdef CONFIG_PM_SLEEP
 980 static int azx_suspend(struct device *dev)
 981 {
 982         struct snd_card *card = dev_get_drvdata(dev);
 983         struct azx *chip;
 984         struct hdac_bus *bus;
 985
 986         if (!azx_is_pm_ready(card))
 987                 return 0;
 988
 989         chip = card->private_data;
 990         bus = azx_bus(chip);
 991         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 992         __azx_runtime_suspend(chip);
 993         if (bus->irq >= 0) {
 994                 free_irq(bus->irq, chip);
 995                 bus->irq = -1;
 996         }
 997
 998         if (chip->msi)
 999                 pci_disable_msi(chip->pci);
1000
1001         trace_azx_suspend(chip);
1002         return 0;
1003 }
1004
1005 static int azx_resume(struct device *dev)
1006 {
1007         struct snd_card *card = dev_get_drvdata(dev);
1008         struct azx *chip;
1009
1010         if (!azx_is_pm_ready(card))
1011                 return 0;
1012
1013         chip = card->private_data;
1014         if (chip->msi)
1015                 if (pci_enable_msi(chip->pci) < 0)
1016                         chip->msi = 0;
1017         if (azx_acquire_irq(chip, 1) < 0)
1018                 return -EIO;
1019         __azx_runtime_resume(chip, false);
1020         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1021
1022         trace_azx_resume(chip);
1023         return 0;
1024 }
1025
1026 /* put codec down to D3 at hibernation for Intel SKL+;
1027  * otherwise BIOS may still access the codec and screw up the driver
1028  */
1029 static int azx_freeze_noirq(struct device *dev)
1030 {
1031         struct snd_card *card = dev_get_drvdata(dev);
1032         struct azx *chip = card->private_data;
1033         struct pci_dev *pci = to_pci_dev(dev);
1034
1035         if (chip->driver_type == AZX_DRIVER_SKL)
1036                 pci_set_power_state(pci, PCI_D3hot);
1037
1038         return 0;
1039 }
1040
1041 static int azx_thaw_noirq(struct device *dev)
1042 {
1043         struct snd_card *card = dev_get_drvdata(dev);
1044         struct azx *chip = card->private_data;
1045         struct pci_dev *pci = to_pci_dev(dev);
1046
1047         if (chip->driver_type == AZX_DRIVER_SKL)
1048                 pci_set_power_state(pci, PCI_D0);
1049
1050         return 0;
1051 }
1052 #endif /* CONFIG_PM_SLEEP */
1053
1054 static int azx_runtime_suspend(struct device *dev)
1055 {
1056         struct snd_card *card = dev_get_drvdata(dev);
1057         struct azx *chip;
1058
1059         if (!azx_is_pm_ready(card))
1060                 return 0;
1061         chip = card->private_data;
1062         if (!azx_has_pm_runtime(chip))
1063                 return 0;
1064
1065         /* enable controller wake up event */
1066         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1067                   STATESTS_INT_MASK);
1068
1069         __azx_runtime_suspend(chip);
1070         trace_azx_runtime_suspend(chip);
1071         return 0;
1072 }
1073
1074 static int azx_runtime_resume(struct device *dev)
1075 {
1076         struct snd_card *card = dev_get_drvdata(dev);
1077         struct azx *chip;
1078
1079         if (!azx_is_pm_ready(card))
1080                 return 0;
1081         chip = card->private_data;
1082         if (!azx_has_pm_runtime(chip))
1083                 return 0;
1084         __azx_runtime_resume(chip, true);
1085
1086         /* disable controller Wake Up event*/
1087         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1088                         ~STATESTS_INT_MASK);
1089
1090         trace_azx_runtime_resume(chip);
1091         return 0;
1092 }
1093
1094 static int azx_runtime_idle(struct device *dev)
1095 {
1096         struct snd_card *card = dev_get_drvdata(dev);
1097         struct azx *chip;
1098         struct hda_intel *hda;
1099
1100         if (!card)
1101                 return 0;
1102
1103         chip = card->private_data;
1104         hda = container_of(chip, struct hda_intel, chip);
1105         if (chip->disabled || hda->init_failed)
1106                 return 0;
1107
1108         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1109             azx_bus(chip)->codec_powered || !chip->running)
1110                 return -EBUSY;
1111
1112         /* ELD notification gets broken when HD-audio bus is off */
1113         if (needs_eld_notify_link(hda))
1114                 return -EBUSY;
1115
1116         return 0;
1117 }
1118
1119 static const struct dev_pm_ops azx_pm = {
1120         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1121 #ifdef CONFIG_PM_SLEEP
1122         .freeze_noirq = azx_freeze_noirq,
1123         .thaw_noirq = azx_thaw_noirq,
1124 #endif
1125         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1126 };
1127
1128 #define AZX_PM_OPS      &azx_pm
1129 #else
1130 #define azx_add_card_list(chip) /* NOP */
1131 #define azx_del_card_list(chip) /* NOP */
1132 #define AZX_PM_OPS      NULL
1133 #endif /* CONFIG_PM */
1134
1135
1136 static int azx_probe_continue(struct azx *chip);
1137
1138 #ifdef SUPPORT_VGA_SWITCHEROO
1139 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1140
1141 static void azx_vs_set_state(struct pci_dev *pci,
1142                              enum vga_switcheroo_state state)
1143 {
1144         struct snd_card *card = pci_get_drvdata(pci);
1145         struct azx *chip = card->private_data;
1146         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1147         struct hda_codec *codec;
1148         bool disabled;
1149
1150         wait_for_completion(&hda->probe_wait);
1151         if (hda->init_failed)
1152                 return;
1153
1154         disabled = (state == VGA_SWITCHEROO_OFF);
1155         if (chip->disabled == disabled)
1156                 return;
1157
1158         if (!hda->probe_continued) {
1159                 chip->disabled = disabled;
1160                 if (!disabled) {
1161                         dev_info(chip->card->dev,
1162                                  "Start delayed initialization\n");
1163                         if (azx_probe_continue(chip) < 0) {
1164                                 dev_err(chip->card->dev, "initialization error\n");
1165                                 hda->init_failed = true;
1166                         }
1167                 }
1168         } else {
1169                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1170                          disabled ? "Disabling" : "Enabling");
1171                 if (disabled) {
1172                         list_for_each_codec(codec, &chip->bus) {
1173                                 pm_runtime_suspend(hda_codec_dev(codec));
1174                                 pm_runtime_disable(hda_codec_dev(codec));
1175                         }
1176                         pm_runtime_suspend(card->dev);
1177                         pm_runtime_disable(card->dev);
1178                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1179                          * however we have no ACPI handle, so pci/acpi can't put us there,
1180                          * put ourselves there */
1181                         pci->current_state = PCI_D3cold;
1182                         chip->disabled = true;
1183                         if (snd_hda_lock_devices(&chip->bus))
1184                                 dev_warn(chip->card->dev,
1185                                          "Cannot lock devices!\n");
1186                 } else {
1187                         snd_hda_unlock_devices(&chip->bus);
1188                         chip->disabled = false;
1189                         pm_runtime_enable(card->dev);
1190                         list_for_each_codec(codec, &chip->bus) {
1191                                 pm_runtime_enable(hda_codec_dev(codec));
1192                                 pm_runtime_resume(hda_codec_dev(codec));
1193                         }
1194                 }
1195         }
1196 }
1197
1198 static bool azx_vs_can_switch(struct pci_dev *pci)
1199 {
1200         struct snd_card *card = pci_get_drvdata(pci);
1201         struct azx *chip = card->private_data;
1202         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1203
1204         wait_for_completion(&hda->probe_wait);
1205         if (hda->init_failed)
1206                 return false;
1207         if (chip->disabled || !hda->probe_continued)
1208                 return true;
1209         if (snd_hda_lock_devices(&chip->bus))
1210                 return false;
1211         snd_hda_unlock_devices(&chip->bus);
1212         return true;
1213 }
1214
1215 /*
1216  * The discrete GPU cannot power down unless the HDA controller runtime
1217  * suspends, so activate runtime PM on codecs even if power_save == 0.
1218  */
1219 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1220 {
1221         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222         struct hda_codec *codec;
1223
1224         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1225                 list_for_each_codec(codec, &chip->bus)
1226                         codec->auto_runtime_pm = 1;
1227                 /* reset the power save setup */
1228                 if (chip->running)
1229                         set_default_power_save(chip);
1230         }
1231 }
1232
1233 static void azx_vs_gpu_bound(struct pci_dev *pci,
1234                              enum vga_switcheroo_client_id client_id)
1235 {
1236         struct snd_card *card = pci_get_drvdata(pci);
1237         struct azx *chip = card->private_data;
1238         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1239
1240         if (client_id == VGA_SWITCHEROO_DIS)
1241                 hda->need_eld_notify_link = 0;
1242         setup_vga_switcheroo_runtime_pm(chip);
1243 }
1244
1245 static void init_vga_switcheroo(struct azx *chip)
1246 {
1247         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1248         struct pci_dev *p = get_bound_vga(chip->pci);
1249         if (p) {
1250                 dev_info(chip->card->dev,
1251                          "Handle vga_switcheroo audio client\n");
1252                 hda->use_vga_switcheroo = 1;
1253                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1254                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1255                 pci_dev_put(p);
1256         }
1257 }
1258
1259 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1260         .set_gpu_state = azx_vs_set_state,
1261         .can_switch = azx_vs_can_switch,
1262         .gpu_bound = azx_vs_gpu_bound,
1263 };
1264
1265 static int register_vga_switcheroo(struct azx *chip)
1266 {
1267         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1268         struct pci_dev *p;
1269         int err;
1270
1271         if (!hda->use_vga_switcheroo)
1272                 return 0;
1273
1274         p = get_bound_vga(chip->pci);
1275         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1276         pci_dev_put(p);
1277
1278         if (err < 0)
1279                 return err;
1280         hda->vga_switcheroo_registered = 1;
1281
1282         return 0;
1283 }
1284 #else
1285 #define init_vga_switcheroo(chip)               /* NOP */
1286 #define register_vga_switcheroo(chip)           0
1287 #define check_hdmi_disabled(pci)        false
1288 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1289 #endif /* SUPPORT_VGA_SWITCHER */
1290
1291 /*
1292  * destructor
1293  */
1294 static int azx_free(struct azx *chip)
1295 {
1296         struct pci_dev *pci = chip->pci;
1297         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1298         struct hdac_bus *bus = azx_bus(chip);
1299
1300         if (azx_has_pm_runtime(chip) && chip->running)
1301                 pm_runtime_get_noresume(&pci->dev);
1302         chip->running = 0;
1303
1304         azx_del_card_list(chip);
1305
1306         hda->init_failed = 1; /* to be sure */
1307         complete_all(&hda->probe_wait);
1308
1309         if (use_vga_switcheroo(hda)) {
1310                 if (chip->disabled && hda->probe_continued)
1311                         snd_hda_unlock_devices(&chip->bus);
1312                 if (hda->vga_switcheroo_registered)
1313                         vga_switcheroo_unregister_client(chip->pci);
1314         }
1315
1316         if (bus->chip_init) {
1317                 azx_clear_irq_pending(chip);
1318                 azx_stop_all_streams(chip);
1319                 azx_stop_chip(chip);
1320         }
1321
1322         if (bus->irq >= 0)
1323                 free_irq(bus->irq, (void*)chip);
1324         if (chip->msi)
1325                 pci_disable_msi(chip->pci);
1326         iounmap(bus->remap_addr);
1327
1328         azx_free_stream_pages(chip);
1329         azx_free_streams(chip);
1330         snd_hdac_bus_exit(bus);
1331
1332         if (chip->region_requested)
1333                 pci_release_regions(chip->pci);
1334
1335         pci_disable_device(chip->pci);
1336 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1337         release_firmware(chip->fw);
1338 #endif
1339         display_power(chip, false);
1340
1341         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1342                 snd_hdac_i915_exit(bus);
1343         kfree(hda);
1344
1345         return 0;
1346 }
1347
1348 static int azx_dev_disconnect(struct snd_device *device)
1349 {
1350         struct azx *chip = device->device_data;
1351
1352         chip->bus.shutdown = 1;
1353         return 0;
1354 }
1355
1356 static int azx_dev_free(struct snd_device *device)
1357 {
1358         return azx_free(device->device_data);
1359 }
1360
1361 #ifdef SUPPORT_VGA_SWITCHEROO
1362 /*
1363  * Check of disabled HDMI controller by vga_switcheroo
1364  */
1365 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1366 {
1367         struct pci_dev *p;
1368
1369         /* check only discrete GPU */
1370         switch (pci->vendor) {
1371         case PCI_VENDOR_ID_ATI:
1372         case PCI_VENDOR_ID_AMD:
1373         case PCI_VENDOR_ID_NVIDIA:
1374                 if (pci->devfn == 1) {
1375                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1376                                                         pci->bus->number, 0);
1377                         if (p) {
1378                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1379                                         return p;
1380                                 pci_dev_put(p);
1381                         }
1382                 }
1383                 break;
1384         }
1385         return NULL;
1386 }
1387
1388 static bool check_hdmi_disabled(struct pci_dev *pci)
1389 {
1390         bool vga_inactive = false;
1391         struct pci_dev *p = get_bound_vga(pci);
1392
1393         if (p) {
1394                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1395                         vga_inactive = true;
1396                 pci_dev_put(p);
1397         }
1398         return vga_inactive;
1399 }
1400 #endif /* SUPPORT_VGA_SWITCHEROO */
1401
1402 /*
1403  * white/black-listing for position_fix
1404  */
1405 static struct snd_pci_quirk position_fix_list[] = {
1406         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1407         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1408         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1409         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1410         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1411         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1412         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1413         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1414         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1415         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1416         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1417         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1418         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1419         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1420         {}
1421 };
1422
1423 static int check_position_fix(struct azx *chip, int fix)
1424 {
1425         const struct snd_pci_quirk *q;
1426
1427         switch (fix) {
1428         case POS_FIX_AUTO:
1429         case POS_FIX_LPIB:
1430         case POS_FIX_POSBUF:
1431         case POS_FIX_VIACOMBO:
1432         case POS_FIX_COMBO:
1433         case POS_FIX_SKL:
1434                 return fix;
1435         }
1436
1437         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1438         if (q) {
1439                 dev_info(chip->card->dev,
1440                          "position_fix set to %d for device %04x:%04x\n",
1441                          q->value, q->subvendor, q->subdevice);
1442                 return q->value;
1443         }
1444
1445         /* Check VIA/ATI HD Audio Controller exist */
1446         if (chip->driver_type == AZX_DRIVER_VIA) {
1447                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1448                 return POS_FIX_VIACOMBO;
1449         }
1450         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1451                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1452                 return POS_FIX_LPIB;
1453         }
1454         if (chip->driver_type == AZX_DRIVER_SKL) {
1455                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1456                 return POS_FIX_SKL;
1457         }
1458         return POS_FIX_AUTO;
1459 }
1460
1461 static void assign_position_fix(struct azx *chip, int fix)
1462 {
1463         static azx_get_pos_callback_t callbacks[] = {
1464                 [POS_FIX_AUTO] = NULL,
1465                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1466                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1467                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1468                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1469                 [POS_FIX_SKL] = azx_get_pos_skl,
1470         };
1471
1472         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1473
1474         /* combo mode uses LPIB only for playback */
1475         if (fix == POS_FIX_COMBO)
1476                 chip->get_position[1] = NULL;
1477
1478         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1479             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1480                 chip->get_delay[0] = chip->get_delay[1] =
1481                         azx_get_delay_from_lpib;
1482         }
1483
1484 }
1485
1486 /*
1487  * black-lists for probe_mask
1488  */
1489 static struct snd_pci_quirk probe_mask_list[] = {
1490         /* Thinkpad often breaks the controller communication when accessing
1491          * to the non-working (or non-existing) modem codec slot.
1492          */
1493         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1494         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1495         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1496         /* broken BIOS */
1497         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1498         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1499         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1500         /* forced codec slots */
1501         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1502         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1503         /* WinFast VP200 H (Teradici) user reported broken communication */
1504         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1505         {}
1506 };
1507
1508 #define AZX_FORCE_CODEC_MASK    0x100
1509
1510 static void check_probe_mask(struct azx *chip, int dev)
1511 {
1512         const struct snd_pci_quirk *q;
1513
1514         chip->codec_probe_mask = probe_mask[dev];
1515         if (chip->codec_probe_mask == -1) {
1516                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1517                 if (q) {
1518                         dev_info(chip->card->dev,
1519                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1520                                  q->value, q->subvendor, q->subdevice);
1521                         chip->codec_probe_mask = q->value;
1522                 }
1523         }
1524
1525         /* check forced option */
1526         if (chip->codec_probe_mask != -1 &&
1527             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1528                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1529                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1530                          (int)azx_bus(chip)->codec_mask);
1531         }
1532 }
1533
1534 /*
1535  * white/black-list for enable_msi
1536  */
1537 static struct snd_pci_quirk msi_black_list[] = {
1538         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1539         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1540         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1541         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1542         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1543         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1544         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1545         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1546         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1547         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1548         {}
1549 };
1550
1551 static void check_msi(struct azx *chip)
1552 {
1553         const struct snd_pci_quirk *q;
1554
1555         if (enable_msi >= 0) {
1556                 chip->msi = !!enable_msi;
1557                 return;
1558         }
1559         chip->msi = 1;  /* enable MSI as default */
1560         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1561         if (q) {
1562                 dev_info(chip->card->dev,
1563                          "msi for device %04x:%04x set to %d\n",
1564                          q->subvendor, q->subdevice, q->value);
1565                 chip->msi = q->value;
1566                 return;
1567         }
1568
1569         /* NVidia chipsets seem to cause troubles with MSI */
1570         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1571                 dev_info(chip->card->dev, "Disabling MSI\n");
1572                 chip->msi = 0;
1573         }
1574 }
1575
1576 /* check the snoop mode availability */
1577 static void azx_check_snoop_available(struct azx *chip)
1578 {
1579         int snoop = hda_snoop;
1580
1581         if (snoop >= 0) {
1582                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1583                          snoop ? "snoop" : "non-snoop");
1584                 chip->snoop = snoop;
1585                 chip->uc_buffer = !snoop;
1586                 return;
1587         }
1588
1589         snoop = true;
1590         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1591             chip->driver_type == AZX_DRIVER_VIA) {
1592                 /* force to non-snoop mode for a new VIA controller
1593                  * when BIOS is set
1594                  */
1595                 u8 val;
1596                 pci_read_config_byte(chip->pci, 0x42, &val);
1597                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1598                                       chip->pci->revision == 0x20))
1599                         snoop = false;
1600         }
1601
1602         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1603                 snoop = false;
1604
1605         chip->snoop = snoop;
1606         if (!snoop) {
1607                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1608                 /* C-Media requires non-cached pages only for CORB/RIRB */
1609                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1610                         chip->uc_buffer = true;
1611         }
1612 }
1613
1614 static void azx_probe_work(struct work_struct *work)
1615 {
1616         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1617         azx_probe_continue(&hda->chip);
1618 }
1619
1620 static int default_bdl_pos_adj(struct azx *chip)
1621 {
1622         /* some exceptions: Atoms seem problematic with value 1 */
1623         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1624                 switch (chip->pci->device) {
1625                 case 0x0f04: /* Baytrail */
1626                 case 0x2284: /* Braswell */
1627                         return 32;
1628                 }
1629         }
1630
1631         switch (chip->driver_type) {
1632         case AZX_DRIVER_ICH:
1633         case AZX_DRIVER_PCH:
1634                 return 1;
1635         default:
1636                 return 32;
1637         }
1638 }
1639
1640 /*
1641  * constructor
1642  */
1643 static const struct hdac_io_ops pci_hda_io_ops;
1644 static const struct hda_controller_ops pci_hda_ops;
1645
1646 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1647                       int dev, unsigned int driver_caps,
1648                       struct azx **rchip)
1649 {
1650         static struct snd_device_ops ops = {
1651                 .dev_disconnect = azx_dev_disconnect,
1652                 .dev_free = azx_dev_free,
1653         };
1654         struct hda_intel *hda;
1655         struct azx *chip;
1656         int err;
1657
1658         *rchip = NULL;
1659
1660         err = pci_enable_device(pci);
1661         if (err < 0)
1662                 return err;
1663
1664         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1665         if (!hda) {
1666                 pci_disable_device(pci);
1667                 return -ENOMEM;
1668         }
1669
1670         chip = &hda->chip;
1671         mutex_init(&chip->open_mutex);
1672         chip->card = card;
1673         chip->pci = pci;
1674         chip->ops = &pci_hda_ops;
1675         chip->driver_caps = driver_caps;
1676         chip->driver_type = driver_caps & 0xff;
1677         check_msi(chip);
1678         chip->dev_index = dev;
1679         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1680                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1681         INIT_LIST_HEAD(&chip->pcm_list);
1682         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1683         INIT_LIST_HEAD(&hda->list);
1684         init_vga_switcheroo(chip);
1685         init_completion(&hda->probe_wait);
1686
1687         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1688
1689         check_probe_mask(chip, dev);
1690
1691         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1692                 chip->fallback_to_single_cmd = 1;
1693         else /* explicitly set to single_cmd or not */
1694                 chip->single_cmd = single_cmd;
1695
1696         azx_check_snoop_available(chip);
1697
1698         if (bdl_pos_adj[dev] < 0)
1699                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1700         else
1701                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1702
1703         /* Workaround for a communication error on CFL (bko#199007) */
1704         if (IS_CFL(pci))
1705                 chip->polling_mode = 1;
1706
1707         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1708         if (err < 0) {
1709                 kfree(hda);
1710                 pci_disable_device(pci);
1711                 return err;
1712         }
1713
1714         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1715                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1716                 chip->bus.needs_damn_long_delay = 1;
1717         }
1718
1719         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1720         if (err < 0) {
1721                 dev_err(card->dev, "Error creating device [card]!\n");
1722                 azx_free(chip);
1723                 return err;
1724         }
1725
1726         /* continue probing in work context as may trigger request module */
1727         INIT_WORK(&hda->probe_work, azx_probe_work);
1728
1729         *rchip = chip;
1730
1731         return 0;
1732 }
1733
1734 static int azx_first_init(struct azx *chip)
1735 {
1736         int dev = chip->dev_index;
1737         struct pci_dev *pci = chip->pci;
1738         struct snd_card *card = chip->card;
1739         struct hdac_bus *bus = azx_bus(chip);
1740         int err;
1741         unsigned short gcap;
1742         unsigned int dma_bits = 64;
1743
1744 #if BITS_PER_LONG != 64
1745         /* Fix up base address on ULI M5461 */
1746         if (chip->driver_type == AZX_DRIVER_ULI) {
1747                 u16 tmp3;
1748                 pci_read_config_word(pci, 0x40, &tmp3);
1749                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1750                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1751         }
1752 #endif
1753
1754         err = pci_request_regions(pci, "ICH HD audio");
1755         if (err < 0)
1756                 return err;
1757         chip->region_requested = 1;
1758
1759         bus->addr = pci_resource_start(pci, 0);
1760         bus->remap_addr = pci_ioremap_bar(pci, 0);
1761         if (bus->remap_addr == NULL) {
1762                 dev_err(card->dev, "ioremap error\n");
1763                 return -ENXIO;
1764         }
1765
1766         if (chip->driver_type == AZX_DRIVER_SKL)
1767                 snd_hdac_bus_parse_capabilities(bus);
1768
1769         /*
1770          * Some Intel CPUs has always running timer (ART) feature and
1771          * controller may have Global time sync reporting capability, so
1772          * check both of these before declaring synchronized time reporting
1773          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1774          */
1775         chip->gts_present = false;
1776
1777 #ifdef CONFIG_X86
1778         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1779                 chip->gts_present = true;
1780 #endif
1781
1782         if (chip->msi) {
1783                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1784                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1785                         pci->no_64bit_msi = true;
1786                 }
1787                 if (pci_enable_msi(pci) < 0)
1788                         chip->msi = 0;
1789         }
1790
1791         pci_set_master(pci);
1792         synchronize_irq(bus->irq);
1793
1794         gcap = azx_readw(chip, GCAP);
1795         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1796
1797         /* AMD devices support 40 or 48bit DMA, take the safe one */
1798         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1799                 dma_bits = 40;
1800
1801         /* disable SB600 64bit support for safety */
1802         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1803                 struct pci_dev *p_smbus;
1804                 dma_bits = 40;
1805                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1806                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1807                                          NULL);
1808                 if (p_smbus) {
1809                         if (p_smbus->revision < 0x30)
1810                                 gcap &= ~AZX_GCAP_64OK;
1811                         pci_dev_put(p_smbus);
1812                 }
1813         }
1814
1815         /* NVidia hardware normally only supports up to 40 bits of DMA */
1816         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1817                 dma_bits = 40;
1818
1819         /* disable 64bit DMA address on some devices */
1820         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1821                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1822                 gcap &= ~AZX_GCAP_64OK;
1823         }
1824
1825         /* disable buffer size rounding to 128-byte multiples if supported */
1826         if (align_buffer_size >= 0)
1827                 chip->align_buffer_size = !!align_buffer_size;
1828         else {
1829                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1830                         chip->align_buffer_size = 0;
1831                 else
1832                         chip->align_buffer_size = 1;
1833         }
1834
1835         /* allow 64bit DMA address if supported by H/W */
1836         if (!(gcap & AZX_GCAP_64OK))
1837                 dma_bits = 32;
1838         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1839                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1840         } else {
1841                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1842                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1843         }
1844
1845         /* read number of streams from GCAP register instead of using
1846          * hardcoded value
1847          */
1848         chip->capture_streams = (gcap >> 8) & 0x0f;
1849         chip->playback_streams = (gcap >> 12) & 0x0f;
1850         if (!chip->playback_streams && !chip->capture_streams) {
1851                 /* gcap didn't give any info, switching to old method */
1852
1853                 switch (chip->driver_type) {
1854                 case AZX_DRIVER_ULI:
1855                         chip->playback_streams = ULI_NUM_PLAYBACK;
1856                         chip->capture_streams = ULI_NUM_CAPTURE;
1857                         break;
1858                 case AZX_DRIVER_ATIHDMI:
1859                 case AZX_DRIVER_ATIHDMI_NS:
1860                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1861                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1862                         break;
1863                 case AZX_DRIVER_GENERIC:
1864                 default:
1865                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1866                         chip->capture_streams = ICH6_NUM_CAPTURE;
1867                         break;
1868                 }
1869         }
1870         chip->capture_index_offset = 0;
1871         chip->playback_index_offset = chip->capture_streams;
1872         chip->num_streams = chip->playback_streams + chip->capture_streams;
1873
1874         /* sanity check for the SDxCTL.STRM field overflow */
1875         if (chip->num_streams > 15 &&
1876             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1877                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1878                          "forcing separate stream tags", chip->num_streams);
1879                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1880         }
1881
1882         /* initialize streams */
1883         err = azx_init_streams(chip);
1884         if (err < 0)
1885                 return err;
1886
1887         err = azx_alloc_stream_pages(chip);
1888         if (err < 0)
1889                 return err;
1890
1891         /* initialize chip */
1892         azx_init_pci(chip);
1893
1894         snd_hdac_i915_set_bclk(bus);
1895
1896         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1897
1898         /* codec detection */
1899         if (!azx_bus(chip)->codec_mask) {
1900                 dev_err(card->dev, "no codecs found!\n");
1901                 return -ENODEV;
1902         }
1903
1904         if (azx_acquire_irq(chip, 0) < 0)
1905                 return -EBUSY;
1906
1907         strcpy(card->driver, "HDA-Intel");
1908         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1909                 sizeof(card->shortname));
1910         snprintf(card->longname, sizeof(card->longname),
1911                  "%s at 0x%lx irq %i",
1912                  card->shortname, bus->addr, bus->irq);
1913
1914         return 0;
1915 }
1916
1917 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1918 /* callback from request_firmware_nowait() */
1919 static void azx_firmware_cb(const struct firmware *fw, void *context)
1920 {
1921         struct snd_card *card = context;
1922         struct azx *chip = card->private_data;
1923         struct pci_dev *pci = chip->pci;
1924
1925         if (!fw) {
1926                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1927                 goto error;
1928         }
1929
1930         chip->fw = fw;
1931         if (!chip->disabled) {
1932                 /* continue probing */
1933                 if (azx_probe_continue(chip))
1934                         goto error;
1935         }
1936         return; /* OK */
1937
1938  error:
1939         snd_card_free(card);
1940         pci_set_drvdata(pci, NULL);
1941 }
1942 #endif
1943
1944 /*
1945  * HDA controller ops.
1946  */
1947
1948 /* PCI register access. */
1949 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1950 {
1951         writel(value, addr);
1952 }
1953
1954 static u32 pci_azx_readl(u32 __iomem *addr)
1955 {
1956         return readl(addr);
1957 }
1958
1959 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1960 {
1961         writew(value, addr);
1962 }
1963
1964 static u16 pci_azx_readw(u16 __iomem *addr)
1965 {
1966         return readw(addr);
1967 }
1968
1969 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1970 {
1971         writeb(value, addr);
1972 }
1973
1974 static u8 pci_azx_readb(u8 __iomem *addr)
1975 {
1976         return readb(addr);
1977 }
1978
1979 static int disable_msi_reset_irq(struct azx *chip)
1980 {
1981         struct hdac_bus *bus = azx_bus(chip);
1982         int err;
1983
1984         free_irq(bus->irq, chip);
1985         bus->irq = -1;
1986         pci_disable_msi(chip->pci);
1987         chip->msi = 0;
1988         err = azx_acquire_irq(chip, 1);
1989         if (err < 0)
1990                 return err;
1991
1992         return 0;
1993 }
1994
1995 /* DMA page allocation helpers.  */
1996 static int dma_alloc_pages(struct hdac_bus *bus,
1997                            int type,
1998                            size_t size,
1999                            struct snd_dma_buffer *buf)
2000 {
2001         struct azx *chip = bus_to_azx(bus);
2002
2003         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2004                 type = SNDRV_DMA_TYPE_DEV_UC;
2005         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2006 }
2007
2008 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2009 {
2010         snd_dma_free_pages(buf);
2011 }
2012
2013 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2014                              struct vm_area_struct *area)
2015 {
2016 #ifdef CONFIG_X86
2017         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2018         struct azx *chip = apcm->chip;
2019         if (chip->uc_buffer)
2020                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2021 #endif
2022 }
2023
2024 static const struct hdac_io_ops pci_hda_io_ops = {
2025         .reg_writel = pci_azx_writel,
2026         .reg_readl = pci_azx_readl,
2027         .reg_writew = pci_azx_writew,
2028         .reg_readw = pci_azx_readw,
2029         .reg_writeb = pci_azx_writeb,
2030         .reg_readb = pci_azx_readb,
2031         .dma_alloc_pages = dma_alloc_pages,
2032         .dma_free_pages = dma_free_pages,
2033 };
2034
2035 static const struct hda_controller_ops pci_hda_ops = {
2036         .disable_msi_reset_irq = disable_msi_reset_irq,
2037         .pcm_mmap_prepare = pcm_mmap_prepare,
2038         .position_check = azx_position_check,
2039 };
2040
2041 static int azx_probe(struct pci_dev *pci,
2042                      const struct pci_device_id *pci_id)
2043 {
2044         static int dev;
2045         struct snd_card *card;
2046         struct hda_intel *hda;
2047         struct azx *chip;
2048         bool schedule_probe;
2049         int err;
2050
2051         if (dev >= SNDRV_CARDS)
2052                 return -ENODEV;
2053         if (!enable[dev]) {
2054                 dev++;
2055                 return -ENOENT;
2056         }
2057
2058         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2059                            0, &card);
2060         if (err < 0) {
2061                 dev_err(&pci->dev, "Error creating card!\n");
2062                 return err;
2063         }
2064
2065         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2066         if (err < 0)
2067                 goto out_free;
2068         card->private_data = chip;
2069         hda = container_of(chip, struct hda_intel, chip);
2070
2071         pci_set_drvdata(pci, card);
2072
2073         err = register_vga_switcheroo(chip);
2074         if (err < 0) {
2075                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2076                 goto out_free;
2077         }
2078
2079         if (check_hdmi_disabled(pci)) {
2080                 dev_info(card->dev, "VGA controller is disabled\n");
2081                 dev_info(card->dev, "Delaying initialization\n");
2082                 chip->disabled = true;
2083         }
2084
2085         schedule_probe = !chip->disabled;
2086
2087 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2088         if (patch[dev] && *patch[dev]) {
2089                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2090                          patch[dev]);
2091                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2092                                               &pci->dev, GFP_KERNEL, card,
2093                                               azx_firmware_cb);
2094                 if (err < 0)
2095                         goto out_free;
2096                 schedule_probe = false; /* continued in azx_firmware_cb() */
2097         }
2098 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2099
2100 #ifndef CONFIG_SND_HDA_I915
2101         if (CONTROLLER_IN_GPU(pci))
2102                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2103 #endif
2104
2105         if (schedule_probe)
2106                 schedule_work(&hda->probe_work);
2107
2108         dev++;
2109         if (chip->disabled)
2110                 complete_all(&hda->probe_wait);
2111         return 0;
2112
2113 out_free:
2114         snd_card_free(card);
2115         return err;
2116 }
2117
2118 #ifdef CONFIG_PM
2119 /* On some boards setting power_save to a non 0 value leads to clicking /
2120  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2121  * figure out how to avoid these sounds, but that is not always feasible.
2122  * So we keep a list of devices where we disable powersaving as its known
2123  * to causes problems on these devices.
2124  */
2125 static struct snd_pci_quirk power_save_blacklist[] = {
2126         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2127         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2128         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2129         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2130         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2131         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2132         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2133         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2134         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2135         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2136         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2137         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2138         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2139         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2140         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2141         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2142         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2143         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2144         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2145         /* https://bugs.launchpad.net/bugs/1821663 */
2146         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2147         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2148         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2149         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2150         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2151         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2152         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2154         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2155         /* https://bugs.launchpad.net/bugs/1821663 */
2156         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2157         {}
2158 };
2159 #endif /* CONFIG_PM */
2160
2161 static void set_default_power_save(struct azx *chip)
2162 {
2163         int val = power_save;
2164
2165 #ifdef CONFIG_PM
2166         if (pm_blacklist) {
2167                 const struct snd_pci_quirk *q;
2168
2169                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2170                 if (q && val) {
2171                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2172                                  q->subvendor, q->subdevice);
2173                         val = 0;
2174                 }
2175         }
2176 #endif /* CONFIG_PM */
2177         snd_hda_set_power_save(&chip->bus, val * 1000);
2178 }
2179
2180 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2181 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2182         [AZX_DRIVER_NVIDIA] = 8,
2183         [AZX_DRIVER_TERA] = 1,
2184 };
2185
2186 static int azx_probe_continue(struct azx *chip)
2187 {
2188         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2189         struct hdac_bus *bus = azx_bus(chip);
2190         struct pci_dev *pci = chip->pci;
2191         int dev = chip->dev_index;
2192         int err;
2193
2194         to_hda_bus(bus)->bus_probing = 1;
2195         hda->probe_continued = 1;
2196
2197         /* bind with i915 if needed */
2198         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2199                 err = snd_hdac_i915_init(bus);
2200                 if (err < 0) {
2201                         /* if the controller is bound only with HDMI/DP
2202                          * (for HSW and BDW), we need to abort the probe;
2203                          * for other chips, still continue probing as other
2204                          * codecs can be on the same link.
2205                          */
2206                         if (CONTROLLER_IN_GPU(pci)) {
2207                                 dev_err(chip->card->dev,
2208                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2209                                 goto out_free;
2210                         } else {
2211                                 /* don't bother any longer */
2212                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2213                         }
2214                 }
2215
2216                 /* HSW/BDW controllers need this power */
2217                 if (CONTROLLER_IN_GPU(pci))
2218                         hda->need_i915_power = 1;
2219         }
2220
2221         /* Request display power well for the HDA controller or codec. For
2222          * Haswell/Broadwell, both the display HDA controller and codec need
2223          * this power. For other platforms, like Baytrail/Braswell, only the
2224          * display codec needs the power and it can be released after probe.
2225          */
2226         display_power(chip, true);
2227
2228         err = azx_first_init(chip);
2229         if (err < 0)
2230                 goto out_free;
2231
2232 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2233         chip->beep_mode = beep_mode[dev];
2234 #endif
2235
2236         /* create codec instances */
2237         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2238         if (err < 0)
2239                 goto out_free;
2240
2241 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2242         if (chip->fw) {
2243                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2244                                          chip->fw->data);
2245                 if (err < 0)
2246                         goto out_free;
2247 #ifndef CONFIG_PM
2248                 release_firmware(chip->fw); /* no longer needed */
2249                 chip->fw = NULL;
2250 #endif
2251         }
2252 #endif
2253         if ((probe_only[dev] & 1) == 0) {
2254                 err = azx_codec_configure(chip);
2255                 if (err < 0)
2256                         goto out_free;
2257         }
2258
2259         err = snd_card_register(chip->card);
2260         if (err < 0)
2261                 goto out_free;
2262
2263         setup_vga_switcheroo_runtime_pm(chip);
2264
2265         chip->running = 1;
2266         azx_add_card_list(chip);
2267
2268         set_default_power_save(chip);
2269
2270         if (azx_has_pm_runtime(chip))
2271                 pm_runtime_put_autosuspend(&pci->dev);
2272
2273 out_free:
2274         if (err < 0 || !hda->need_i915_power)
2275                 display_power(chip, false);
2276         if (err < 0)
2277                 hda->init_failed = 1;
2278         complete_all(&hda->probe_wait);
2279         to_hda_bus(bus)->bus_probing = 0;
2280         return err;
2281 }
2282
2283 static void azx_remove(struct pci_dev *pci)
2284 {
2285         struct snd_card *card = pci_get_drvdata(pci);
2286         struct azx *chip;
2287         struct hda_intel *hda;
2288
2289         if (card) {
2290                 /* cancel the pending probing work */
2291                 chip = card->private_data;
2292                 hda = container_of(chip, struct hda_intel, chip);
2293                 /* FIXME: below is an ugly workaround.
2294                  * Both device_release_driver() and driver_probe_device()
2295                  * take *both* the device's and its parent's lock before
2296                  * calling the remove() and probe() callbacks.  The codec
2297                  * probe takes the locks of both the codec itself and its
2298                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2299                  * the PCI controller is unbound, it takes its lock, too
2300                  * ==> ouch, a deadlock!
2301                  * As a workaround, we unlock temporarily here the controller
2302                  * device during cancel_work_sync() call.
2303                  */
2304                 device_unlock(&pci->dev);
2305                 cancel_work_sync(&hda->probe_work);
2306                 device_lock(&pci->dev);
2307
2308                 snd_card_free(card);
2309         }
2310 }
2311
2312 static void azx_shutdown(struct pci_dev *pci)
2313 {
2314         struct snd_card *card = pci_get_drvdata(pci);
2315         struct azx *chip;
2316
2317         if (!card)
2318                 return;
2319         chip = card->private_data;
2320         if (chip && chip->running)
2321                 azx_stop_chip(chip);
2322 }
2323
2324 /* PCI IDs */
2325 static const struct pci_device_id azx_ids[] = {
2326         /* CPT */
2327         { PCI_DEVICE(0x8086, 0x1c20),
2328           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2329         /* PBG */
2330         { PCI_DEVICE(0x8086, 0x1d20),
2331           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2332         /* Panther Point */
2333         { PCI_DEVICE(0x8086, 0x1e20),
2334           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2335         /* Lynx Point */
2336         { PCI_DEVICE(0x8086, 0x8c20),
2337           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2338         /* 9 Series */
2339         { PCI_DEVICE(0x8086, 0x8ca0),
2340           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2341         /* Wellsburg */
2342         { PCI_DEVICE(0x8086, 0x8d20),
2343           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2344         { PCI_DEVICE(0x8086, 0x8d21),
2345           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2346         /* Lewisburg */
2347         { PCI_DEVICE(0x8086, 0xa1f0),
2348           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2349         { PCI_DEVICE(0x8086, 0xa270),
2350           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2351         /* Lynx Point-LP */
2352         { PCI_DEVICE(0x8086, 0x9c20),
2353           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2354         /* Lynx Point-LP */
2355         { PCI_DEVICE(0x8086, 0x9c21),
2356           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2357         /* Wildcat Point-LP */
2358         { PCI_DEVICE(0x8086, 0x9ca0),
2359           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2360         /* Sunrise Point */
2361         { PCI_DEVICE(0x8086, 0xa170),
2362           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2363         /* Sunrise Point-LP */
2364         { PCI_DEVICE(0x8086, 0x9d70),
2365           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2366         /* Kabylake */
2367         { PCI_DEVICE(0x8086, 0xa171),
2368           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2369         /* Kabylake-LP */
2370         { PCI_DEVICE(0x8086, 0x9d71),
2371           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2372         /* Kabylake-H */
2373         { PCI_DEVICE(0x8086, 0xa2f0),
2374           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2375         /* Coffelake */
2376         { PCI_DEVICE(0x8086, 0xa348),
2377           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2378         /* Cannonlake */
2379         { PCI_DEVICE(0x8086, 0x9dc8),
2380           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2381         /* CometLake-LP */
2382         { PCI_DEVICE(0x8086, 0x02C8),
2383           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2384         /* CometLake-H */
2385         { PCI_DEVICE(0x8086, 0x06C8),
2386           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2387         /* Icelake */
2388         { PCI_DEVICE(0x8086, 0x34c8),
2389           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2390         /* Broxton-P(Apollolake) */
2391         { PCI_DEVICE(0x8086, 0x5a98),
2392           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2393         /* Broxton-T */
2394         { PCI_DEVICE(0x8086, 0x1a98),
2395           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2396         /* Gemini-Lake */
2397         { PCI_DEVICE(0x8086, 0x3198),
2398           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2399         /* Haswell */
2400         { PCI_DEVICE(0x8086, 0x0a0c),
2401           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2402         { PCI_DEVICE(0x8086, 0x0c0c),
2403           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2404         { PCI_DEVICE(0x8086, 0x0d0c),
2405           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2406         /* Broadwell */
2407         { PCI_DEVICE(0x8086, 0x160c),
2408           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2409         /* 5 Series/3400 */
2410         { PCI_DEVICE(0x8086, 0x3b56),
2411           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2412         /* Poulsbo */
2413         { PCI_DEVICE(0x8086, 0x811b),
2414           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2415         /* Oaktrail */
2416         { PCI_DEVICE(0x8086, 0x080a),
2417           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2418         /* BayTrail */
2419         { PCI_DEVICE(0x8086, 0x0f04),
2420           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2421         /* Braswell */
2422         { PCI_DEVICE(0x8086, 0x2284),
2423           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2424         /* ICH6 */
2425         { PCI_DEVICE(0x8086, 0x2668),
2426           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2427         /* ICH7 */
2428         { PCI_DEVICE(0x8086, 0x27d8),
2429           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2430         /* ESB2 */
2431         { PCI_DEVICE(0x8086, 0x269a),
2432           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2433         /* ICH8 */
2434         { PCI_DEVICE(0x8086, 0x284b),
2435           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2436         /* ICH9 */
2437         { PCI_DEVICE(0x8086, 0x293e),
2438           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2439         /* ICH9 */
2440         { PCI_DEVICE(0x8086, 0x293f),
2441           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2442         /* ICH10 */
2443         { PCI_DEVICE(0x8086, 0x3a3e),
2444           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2445         /* ICH10 */
2446         { PCI_DEVICE(0x8086, 0x3a6e),
2447           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2448         /* Generic Intel */
2449         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2450           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2451           .class_mask = 0xffffff,
2452           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2453         /* ATI SB 450/600/700/800/900 */
2454         { PCI_DEVICE(0x1002, 0x437b),
2455           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2456         { PCI_DEVICE(0x1002, 0x4383),
2457           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2458         /* AMD Hudson */
2459         { PCI_DEVICE(0x1022, 0x780d),
2460           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2461         /* AMD Stoney */
2462         { PCI_DEVICE(0x1022, 0x157a),
2463           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2464                          AZX_DCAPS_PM_RUNTIME },
2465         /* AMD Raven */
2466         { PCI_DEVICE(0x1022, 0x15e3),
2467           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2468                          AZX_DCAPS_PM_RUNTIME },
2469         /* ATI HDMI */
2470         { PCI_DEVICE(0x1002, 0x0002),
2471           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2472         { PCI_DEVICE(0x1002, 0x1308),
2473           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2474         { PCI_DEVICE(0x1002, 0x157a),
2475           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2476         { PCI_DEVICE(0x1002, 0x15b3),
2477           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2478         { PCI_DEVICE(0x1002, 0x793b),
2479           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480         { PCI_DEVICE(0x1002, 0x7919),
2481           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482         { PCI_DEVICE(0x1002, 0x960f),
2483           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484         { PCI_DEVICE(0x1002, 0x970f),
2485           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486         { PCI_DEVICE(0x1002, 0x9840),
2487           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2488         { PCI_DEVICE(0x1002, 0xaa00),
2489           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490         { PCI_DEVICE(0x1002, 0xaa08),
2491           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492         { PCI_DEVICE(0x1002, 0xaa10),
2493           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494         { PCI_DEVICE(0x1002, 0xaa18),
2495           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496         { PCI_DEVICE(0x1002, 0xaa20),
2497           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498         { PCI_DEVICE(0x1002, 0xaa28),
2499           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500         { PCI_DEVICE(0x1002, 0xaa30),
2501           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502         { PCI_DEVICE(0x1002, 0xaa38),
2503           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504         { PCI_DEVICE(0x1002, 0xaa40),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0xaa48),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0xaa50),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0xaa58),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0xaa60),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0xaa68),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa80),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa88),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa90),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa98),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0x9902),
2525           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2526         { PCI_DEVICE(0x1002, 0xaaa0),
2527           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2528         { PCI_DEVICE(0x1002, 0xaaa8),
2529           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530         { PCI_DEVICE(0x1002, 0xaab0),
2531           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532         { PCI_DEVICE(0x1002, 0xaac0),
2533           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2534         { PCI_DEVICE(0x1002, 0xaac8),
2535           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2536         { PCI_DEVICE(0x1002, 0xaad8),
2537           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2538         { PCI_DEVICE(0x1002, 0xaae8),
2539           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2540         { PCI_DEVICE(0x1002, 0xaae0),
2541           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2542         { PCI_DEVICE(0x1002, 0xaaf0),
2543           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544         /* VIA VT8251/VT8237A */
2545         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2546         /* VIA GFX VT7122/VX900 */
2547         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2548         /* VIA GFX VT6122/VX11 */
2549         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2550         /* SIS966 */
2551         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2552         /* ULI M5461 */
2553         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2554         /* NVIDIA MCP */
2555         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2556           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2557           .class_mask = 0xffffff,
2558           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2559         /* Teradici */
2560         { PCI_DEVICE(0x6549, 0x1200),
2561           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2562         { PCI_DEVICE(0x6549, 0x2200),
2563           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2564         /* Creative X-Fi (CA0110-IBG) */
2565         /* CTHDA chips */
2566         { PCI_DEVICE(0x1102, 0x0010),
2567           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2568         { PCI_DEVICE(0x1102, 0x0012),
2569           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2570 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2571         /* the following entry conflicts with snd-ctxfi driver,
2572          * as ctxfi driver mutates from HD-audio to native mode with
2573          * a special command sequence.
2574          */
2575         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2576           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2577           .class_mask = 0xffffff,
2578           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2579           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2580 #else
2581         /* this entry seems still valid -- i.e. without emu20kx chip */
2582         { PCI_DEVICE(0x1102, 0x0009),
2583           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2584           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2585 #endif
2586         /* CM8888 */
2587         { PCI_DEVICE(0x13f6, 0x5011),
2588           .driver_data = AZX_DRIVER_CMEDIA |
2589           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2590         /* Vortex86MX */
2591         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2592         /* VMware HDAudio */
2593         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2594         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2595         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2596           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2597           .class_mask = 0xffffff,
2598           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2599         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2600           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2601           .class_mask = 0xffffff,
2602           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2603         { 0, }
2604 };
2605 MODULE_DEVICE_TABLE(pci, azx_ids);
2606
2607 /* pci_driver definition */
2608 static struct pci_driver azx_driver = {
2609         .name = KBUILD_MODNAME,
2610         .id_table = azx_ids,
2611         .probe = azx_probe,
2612         .remove = azx_remove,
2613         .shutdown = azx_shutdown,
2614         .driver = {
2615                 .pm = AZX_PM_OPS,
2616         },
2617 };
2618
2619 module_pci_driver(azx_driver);