1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_PGTABLE_H
3 #define _LINUX_PGTABLE_H
6 #include <asm/pgtable.h>
11 #include <linux/mm_types.h>
12 #include <linux/bug.h>
13 #include <linux/errno.h>
14 #include <asm-generic/pgtable_uffd.h>
15 #include <linux/page_table_check.h>
17 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
18 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
19 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
23 * On almost all architectures and configurations, 0 can be used as the
24 * upper ceiling to free_pgtables(): on many architectures it has the same
25 * effect as using TASK_SIZE. However, there is one configuration which
26 * must impose a more careful limit, to avoid freeing kernel pgtables.
28 #ifndef USER_PGTABLES_CEILING
29 #define USER_PGTABLES_CEILING 0UL
33 * This defines the first usable user address. Platforms
34 * can override its value with custom FIRST_USER_ADDRESS
35 * defined in their respective <asm/pgtable.h>.
37 #ifndef FIRST_USER_ADDRESS
38 #define FIRST_USER_ADDRESS 0UL
42 * This defines the generic helper for accessing PMD page
43 * table page. Although platforms can still override this
44 * via their respective <asm/pgtable.h>.
47 #define pmd_pgtable(pmd) pmd_page(pmd)
51 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD]
53 * The pXx_index() functions return the index of the entry in the page
54 * table page which would control the given virtual address
56 * As these functions may be used by the same code for different levels of
57 * the page table folding, they are always available, regardless of
58 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0
59 * because in such cases PTRS_PER_PxD equals 1.
62 static inline unsigned long pte_index(unsigned long address)
64 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
66 #define pte_index pte_index
69 static inline unsigned long pmd_index(unsigned long address)
71 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
73 #define pmd_index pmd_index
77 static inline unsigned long pud_index(unsigned long address)
79 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
81 #define pud_index pud_index
85 /* Must be a compile-time constant, so implement it as a macro */
86 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
89 #ifndef pte_offset_kernel
90 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
92 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
94 #define pte_offset_kernel pte_offset_kernel
98 #define __pte_map(pmd, address) \
99 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address)))
100 #define pte_unmap(pte) do { \
101 kunmap_local((pte)); \
102 /* rcu_read_unlock() to be added later */ \
105 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address)
107 return pte_offset_kernel(pmd, address);
109 static inline void pte_unmap(pte_t *pte)
111 /* rcu_read_unlock() to be added later */
115 /* Find an entry in the second-level page table.. */
117 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
119 return pud_pgtable(*pud) + pmd_index(address);
121 #define pmd_offset pmd_offset
125 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address)
127 return p4d_pgtable(*p4d) + pud_index(address);
129 #define pud_offset pud_offset
132 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address)
134 return (pgd + pgd_index(address));
138 * a shortcut to get a pgd_t in a given mm
141 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
145 * a shortcut which implies the use of the kernel's pgd, instead
149 #define pgd_offset_k(address) pgd_offset(&init_mm, (address))
153 * In many cases it is known that a virtual address is mapped at PMD or PTE
154 * level, so instead of traversing all the page table levels, we can get a
155 * pointer to the PMD entry in user or kernel page table or translate a virtual
156 * address to the pointer in the PTE in the kernel page tables with simple
159 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
161 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va);
164 static inline pmd_t *pmd_off_k(unsigned long va)
166 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va);
169 static inline pte_t *virt_to_kpte(unsigned long vaddr)
171 pmd_t *pmd = pmd_off_k(vaddr);
173 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr);
177 static inline int pmd_young(pmd_t pmd)
183 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
184 extern int ptep_set_access_flags(struct vm_area_struct *vma,
185 unsigned long address, pte_t *ptep,
186 pte_t entry, int dirty);
189 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
190 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
191 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
192 unsigned long address, pmd_t *pmdp,
193 pmd_t entry, int dirty);
194 extern int pudp_set_access_flags(struct vm_area_struct *vma,
195 unsigned long address, pud_t *pudp,
196 pud_t entry, int dirty);
198 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
199 unsigned long address, pmd_t *pmdp,
200 pmd_t entry, int dirty)
205 static inline int pudp_set_access_flags(struct vm_area_struct *vma,
206 unsigned long address, pud_t *pudp,
207 pud_t entry, int dirty)
212 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
216 static inline pte_t ptep_get(pte_t *ptep)
218 return READ_ONCE(*ptep);
223 static inline pmd_t pmdp_get(pmd_t *pmdp)
225 return READ_ONCE(*pmdp);
229 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
230 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
231 unsigned long address,
234 pte_t pte = ptep_get(ptep);
239 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
244 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
245 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
246 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
247 unsigned long address,
255 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
259 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
260 unsigned long address,
266 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */
269 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
270 int ptep_clear_flush_young(struct vm_area_struct *vma,
271 unsigned long address, pte_t *ptep);
274 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
275 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
276 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
277 unsigned long address, pmd_t *pmdp);
280 * Despite relevant to THP only, this API is called from generic rmap code
281 * under PageTransHuge(), hence needs a dummy implementation for !THP
283 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
284 unsigned long address, pmd_t *pmdp)
289 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
292 #ifndef arch_has_hw_nonleaf_pmd_young
294 * Return whether the accessed bit in non-leaf PMD entries is supported on the
297 static inline bool arch_has_hw_nonleaf_pmd_young(void)
299 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG);
303 #ifndef arch_has_hw_pte_young
305 * Return whether the accessed bit is supported on the local CPU.
307 * This stub assumes accessing through an old PTE triggers a page fault.
308 * Architectures that automatically set the access bit should overwrite it.
310 static inline bool arch_has_hw_pte_young(void)
316 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
317 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
318 unsigned long address,
321 pte_t pte = ptep_get(ptep);
322 pte_clear(mm, address, ptep);
323 page_table_check_pte_clear(mm, address, pte);
328 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
331 ptep_get_and_clear(mm, addr, ptep);
334 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH
336 * For walking the pagetables without holding any locks. Some architectures
337 * (eg x86-32 PAE) cannot load the entries atomically without using expensive
338 * instructions. We are guaranteed that a PTE will only either go from not
339 * present to present, or present to not present -- it will not switch to a
340 * completely different present page without a TLB flush inbetween; which we
341 * are blocking by holding interrupts off.
343 * Setting ptes from not present to present goes:
345 * ptep->pte_high = h;
349 * And present to not present goes:
353 * ptep->pte_high = 0;
355 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'.
356 * We load pte_high *after* loading pte_low, which ensures we don't see an older
357 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't
358 * picked up a changed pte high. We might have gotten rubbish values from
359 * pte_low and pte_high, but we are guaranteed that pte_low will not have the
360 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only
361 * operates on present ptes we're safe.
363 static inline pte_t ptep_get_lockless(pte_t *ptep)
368 pte.pte_low = ptep->pte_low;
370 pte.pte_high = ptep->pte_high;
372 } while (unlikely(pte.pte_low != ptep->pte_low));
376 #define ptep_get_lockless ptep_get_lockless
378 #if CONFIG_PGTABLE_LEVELS > 2
379 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
384 pmd.pmd_low = pmdp->pmd_low;
386 pmd.pmd_high = pmdp->pmd_high;
388 } while (unlikely(pmd.pmd_low != pmdp->pmd_low));
392 #define pmdp_get_lockless pmdp_get_lockless
393 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
394 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */
397 * We require that the PTE can be read atomically.
399 #ifndef ptep_get_lockless
400 static inline pte_t ptep_get_lockless(pte_t *ptep)
402 return ptep_get(ptep);
406 #ifndef pmdp_get_lockless
407 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
409 return pmdp_get(pmdp);
413 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
414 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
415 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
416 unsigned long address,
422 page_table_check_pmd_clear(mm, address, pmd);
426 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
427 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
428 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
429 unsigned long address,
435 page_table_check_pud_clear(mm, address, pud);
439 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
440 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
442 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
443 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
444 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
445 unsigned long address, pmd_t *pmdp,
448 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
452 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
453 static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm,
454 unsigned long address, pud_t *pudp,
457 return pudp_huge_get_and_clear(mm, address, pudp);
460 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
462 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
463 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
464 unsigned long address, pte_t *ptep,
467 return ptep_get_and_clear(mm, address, ptep);
473 * If two threads concurrently fault at the same page, the thread that
474 * won the race updates the PTE and its local TLB/Cache. The other thread
475 * gives up, simply does nothing, and continues; on architectures where
476 * software can update TLB, local TLB can be updated here to avoid next page
477 * fault. This function updates TLB only, do nothing with cache or others.
478 * It is the difference with function update_mmu_cache.
480 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB
481 static inline void update_mmu_tlb(struct vm_area_struct *vma,
482 unsigned long address, pte_t *ptep)
485 #define __HAVE_ARCH_UPDATE_MMU_TLB
489 * Some architectures may be able to avoid expensive synchronization
490 * primitives when modifications are made to PTE's which are already
491 * not present, or in the process of an address space destruction.
493 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
494 static inline void pte_clear_not_present_full(struct mm_struct *mm,
495 unsigned long address,
499 pte_clear(mm, address, ptep);
503 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
504 extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
505 unsigned long address,
509 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
510 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
511 unsigned long address,
513 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
514 unsigned long address,
518 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
520 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
522 pte_t old_pte = ptep_get(ptep);
523 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
528 * On some architectures hardware does not set page access bit when accessing
529 * memory page, it is responsibility of software setting this bit. It brings
530 * out extra page fault penalty to track page access bit. For optimization page
531 * access bit can be set during all page fault flow on these arches.
532 * To be differentiate with macro pte_mkyoung, this macro is used on platforms
533 * where software maintains page access bit.
535 #ifndef pte_sw_mkyoung
536 static inline pte_t pte_sw_mkyoung(pte_t pte)
540 #define pte_sw_mkyoung pte_sw_mkyoung
543 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
544 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
545 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
546 unsigned long address, pmd_t *pmdp)
548 pmd_t old_pmd = *pmdp;
549 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
552 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
553 unsigned long address, pmd_t *pmdp)
557 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
559 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
560 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
561 static inline void pudp_set_wrprotect(struct mm_struct *mm,
562 unsigned long address, pud_t *pudp)
564 pud_t old_pud = *pudp;
566 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
569 static inline void pudp_set_wrprotect(struct mm_struct *mm,
570 unsigned long address, pud_t *pudp)
574 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
577 #ifndef pmdp_collapse_flush
578 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
579 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
580 unsigned long address, pmd_t *pmdp);
582 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
583 unsigned long address,
589 #define pmdp_collapse_flush pmdp_collapse_flush
590 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
593 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
594 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
598 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
599 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
602 #ifndef arch_needs_pgtable_deposit
603 #define arch_needs_pgtable_deposit() (false)
606 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
608 * This is an implementation of pmdp_establish() that is only suitable for an
609 * architecture that doesn't have hardware dirty/accessed bits. In this case we
610 * can't race with CPU which sets these bits and non-atomic approach is fine.
612 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
613 unsigned long address, pmd_t *pmdp, pmd_t pmd)
615 pmd_t old_pmd = *pmdp;
616 set_pmd_at(vma->vm_mm, address, pmdp, pmd);
621 #ifndef __HAVE_ARCH_PMDP_INVALIDATE
622 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
626 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD
629 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent
630 * hugepage mapping in the page tables. This function is similar to
631 * pmdp_invalidate(), but should only be used if the access and dirty bits would
632 * not be cleared by the software in the new PMD value. The function ensures
633 * that hardware changes of the access and dirty bits updates would not be lost.
635 * Doing so can allow in certain architectures to avoid a TLB flush in most
636 * cases. Yet, another TLB flush might be necessary later if the PMD update
637 * itself requires such flush (e.g., if protection was set to be stricter). Yet,
638 * even when a TLB flush is needed because of the update, the caller may be able
639 * to batch these TLB flushing operations, so fewer TLB flush operations are
642 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
643 unsigned long address, pmd_t *pmdp);
646 #ifndef __HAVE_ARCH_PTE_SAME
647 static inline int pte_same(pte_t pte_a, pte_t pte_b)
649 return pte_val(pte_a) == pte_val(pte_b);
653 #ifndef __HAVE_ARCH_PTE_UNUSED
655 * Some architectures provide facilities to virtualization guests
656 * so that they can flag allocated pages as unused. This allows the
657 * host to transparently reclaim unused pages. This function returns
658 * whether the pte's page is unused.
660 static inline int pte_unused(pte_t pte)
666 #ifndef pte_access_permitted
667 #define pte_access_permitted(pte, write) \
668 (pte_present(pte) && (!(write) || pte_write(pte)))
671 #ifndef pmd_access_permitted
672 #define pmd_access_permitted(pmd, write) \
673 (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
676 #ifndef pud_access_permitted
677 #define pud_access_permitted(pud, write) \
678 (pud_present(pud) && (!(write) || pud_write(pud)))
681 #ifndef p4d_access_permitted
682 #define p4d_access_permitted(p4d, write) \
683 (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
686 #ifndef pgd_access_permitted
687 #define pgd_access_permitted(pgd, write) \
688 (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
691 #ifndef __HAVE_ARCH_PMD_SAME
692 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
694 return pmd_val(pmd_a) == pmd_val(pmd_b);
697 static inline int pud_same(pud_t pud_a, pud_t pud_b)
699 return pud_val(pud_a) == pud_val(pud_b);
703 #ifndef __HAVE_ARCH_P4D_SAME
704 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
706 return p4d_val(p4d_a) == p4d_val(p4d_b);
710 #ifndef __HAVE_ARCH_PGD_SAME
711 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
713 return pgd_val(pgd_a) == pgd_val(pgd_b);
718 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
719 * TLB flush will be required as a result of the "set". For example, use
720 * in scenarios where it is known ahead of time that the routine is
721 * setting non-present entries, or re-setting an existing entry to the
722 * same value. Otherwise, use the typical "set" helpers and flush the
725 #define set_pte_safe(ptep, pte) \
727 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \
728 set_pte(ptep, pte); \
731 #define set_pmd_safe(pmdp, pmd) \
733 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \
734 set_pmd(pmdp, pmd); \
737 #define set_pud_safe(pudp, pud) \
739 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \
740 set_pud(pudp, pud); \
743 #define set_p4d_safe(p4dp, p4d) \
745 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
746 set_p4d(p4dp, p4d); \
749 #define set_pgd_safe(pgdp, pgd) \
751 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
752 set_pgd(pgdp, pgd); \
755 #ifndef __HAVE_ARCH_DO_SWAP_PAGE
757 * Some architectures support metadata associated with a page. When a
758 * page is being swapped out, this metadata must be saved so it can be
759 * restored when the page is swapped back in. SPARC M7 and newer
760 * processors support an ADI (Application Data Integrity) tag for the
761 * page as metadata for the page. arch_do_swap_page() can restore this
762 * metadata when a page is swapped back in.
764 static inline void arch_do_swap_page(struct mm_struct *mm,
765 struct vm_area_struct *vma,
767 pte_t pte, pte_t oldpte)
773 #ifndef __HAVE_ARCH_UNMAP_ONE
775 * Some architectures support metadata associated with a page. When a
776 * page is being swapped out, this metadata must be saved so it can be
777 * restored when the page is swapped back in. SPARC M7 and newer
778 * processors support an ADI (Application Data Integrity) tag for the
779 * page as metadata for the page. arch_unmap_one() can save this
780 * metadata on a swap-out of a page.
782 static inline int arch_unmap_one(struct mm_struct *mm,
783 struct vm_area_struct *vma,
792 * Allow architectures to preserve additional metadata associated with
793 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function
794 * prototypes must be defined in the arch-specific asm/pgtable.h file.
796 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP
797 static inline int arch_prepare_to_swap(struct page *page)
803 #ifndef __HAVE_ARCH_SWAP_INVALIDATE
804 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
808 static inline void arch_swap_invalidate_area(int type)
813 #ifndef __HAVE_ARCH_SWAP_RESTORE
814 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
819 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE
820 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
823 #ifndef __HAVE_ARCH_MOVE_PTE
824 #define move_pte(pte, prot, old_addr, new_addr) (pte)
827 #ifndef pte_accessible
828 # define pte_accessible(mm, pte) ((void)(pte), 1)
831 #ifndef flush_tlb_fix_spurious_fault
832 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address)
836 * When walking page tables, get the address of the next boundary,
837 * or the end address of the range if that comes earlier. Although no
838 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
841 #define pgd_addr_end(addr, end) \
842 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
843 (__boundary - 1 < (end) - 1)? __boundary: (end); \
847 #define p4d_addr_end(addr, end) \
848 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
849 (__boundary - 1 < (end) - 1)? __boundary: (end); \
854 #define pud_addr_end(addr, end) \
855 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
856 (__boundary - 1 < (end) - 1)? __boundary: (end); \
861 #define pmd_addr_end(addr, end) \
862 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
863 (__boundary - 1 < (end) - 1)? __boundary: (end); \
868 * When walking page tables, we usually want to skip any p?d_none entries;
869 * and any p?d_bad entries - reporting the error before resetting to none.
870 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
872 void pgd_clear_bad(pgd_t *);
874 #ifndef __PAGETABLE_P4D_FOLDED
875 void p4d_clear_bad(p4d_t *);
877 #define p4d_clear_bad(p4d) do { } while (0)
880 #ifndef __PAGETABLE_PUD_FOLDED
881 void pud_clear_bad(pud_t *);
883 #define pud_clear_bad(p4d) do { } while (0)
886 void pmd_clear_bad(pmd_t *);
888 static inline int pgd_none_or_clear_bad(pgd_t *pgd)
892 if (unlikely(pgd_bad(*pgd))) {
899 static inline int p4d_none_or_clear_bad(p4d_t *p4d)
903 if (unlikely(p4d_bad(*p4d))) {
910 static inline int pud_none_or_clear_bad(pud_t *pud)
914 if (unlikely(pud_bad(*pud))) {
921 static inline int pmd_none_or_clear_bad(pmd_t *pmd)
925 if (unlikely(pmd_bad(*pmd))) {
932 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
937 * Get the current pte state, but zero it out to make it
938 * non-present, preventing the hardware from asynchronously
941 return ptep_get_and_clear(vma->vm_mm, addr, ptep);
944 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
946 pte_t *ptep, pte_t pte)
949 * The pte is non-present, so there's no hardware state to
952 set_pte_at(vma->vm_mm, addr, ptep, pte);
955 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
957 * Start a pte protection read-modify-write transaction, which
958 * protects against asynchronous hardware modifications to the pte.
959 * The intention is not to prevent the hardware from making pte
960 * updates, but to prevent any updates it may make from being lost.
962 * This does not protect against other software modifications of the
963 * pte; the appropriate pte lock must be held over the transaction.
965 * Note that this interface is intended to be batchable, meaning that
966 * ptep_modify_prot_commit may not actually update the pte, but merely
967 * queue the update to be done at some later time. The update must be
968 * actually committed before the pte lock is released, however.
970 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
974 return __ptep_modify_prot_start(vma, addr, ptep);
978 * Commit an update to a pte, leaving any hardware-controlled bits in
979 * the PTE unmodified.
981 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
983 pte_t *ptep, pte_t old_pte, pte_t pte)
985 __ptep_modify_prot_commit(vma, addr, ptep, pte);
987 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
988 #endif /* CONFIG_MMU */
991 * No-op macros that just return the current protection value. Defined here
992 * because these macros can be used even if CONFIG_MMU is not defined.
996 #define pgprot_nx(prot) (prot)
999 #ifndef pgprot_noncached
1000 #define pgprot_noncached(prot) (prot)
1003 #ifndef pgprot_writecombine
1004 #define pgprot_writecombine pgprot_noncached
1007 #ifndef pgprot_writethrough
1008 #define pgprot_writethrough pgprot_noncached
1011 #ifndef pgprot_device
1012 #define pgprot_device pgprot_noncached
1016 #define pgprot_mhp(prot) (prot)
1020 #ifndef pgprot_modify
1021 #define pgprot_modify pgprot_modify
1022 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
1024 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
1025 newprot = pgprot_noncached(newprot);
1026 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
1027 newprot = pgprot_writecombine(newprot);
1028 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
1029 newprot = pgprot_device(newprot);
1033 #endif /* CONFIG_MMU */
1035 #ifndef pgprot_encrypted
1036 #define pgprot_encrypted(prot) (prot)
1039 #ifndef pgprot_decrypted
1040 #define pgprot_decrypted(prot) (prot)
1044 * A facility to provide lazy MMU batching. This allows PTE updates and
1045 * page invalidations to be delayed until a call to leave lazy MMU mode
1046 * is issued. Some architectures may benefit from doing this, and it is
1047 * beneficial for both shadow and direct mode hypervisors, which may batch
1048 * the PTE updates which happen during this window. Note that using this
1049 * interface requires that read hazards be removed from the code. A read
1050 * hazard could result in the direct mode hypervisor case, since the actual
1051 * write to the page tables may not yet have taken place, so reads though
1052 * a raw PTE pointer after it has been modified are not guaranteed to be
1053 * up to date. This mode can only be entered and left under the protection of
1054 * the page table locks for all page tables which may be modified. In the UP
1055 * case, this is required so that preemption is disabled, and in the SMP case,
1056 * it must synchronize the delayed page table writes properly on other CPUs.
1058 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1059 #define arch_enter_lazy_mmu_mode() do {} while (0)
1060 #define arch_leave_lazy_mmu_mode() do {} while (0)
1061 #define arch_flush_lazy_mmu_mode() do {} while (0)
1065 * A facility to provide batching of the reload of page tables and
1066 * other process state with the actual context switch code for
1067 * paravirtualized guests. By convention, only one of the batched
1068 * update (lazy) modes (CPU, MMU) should be active at any given time,
1069 * entry should never be nested, and entry and exits should always be
1070 * paired. This is for sanity of maintaining and reasoning about the
1071 * kernel code. In this case, the exit (end of the context switch) is
1072 * in architecture-specific code, and so doesn't need a generic
1075 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
1076 #define arch_start_context_switch(prev) do {} while (0)
1079 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1080 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
1081 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1086 static inline int pmd_swp_soft_dirty(pmd_t pmd)
1091 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1096 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */
1097 static inline int pte_soft_dirty(pte_t pte)
1102 static inline int pmd_soft_dirty(pmd_t pmd)
1107 static inline pte_t pte_mksoft_dirty(pte_t pte)
1112 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
1117 static inline pte_t pte_clear_soft_dirty(pte_t pte)
1122 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
1127 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
1132 static inline int pte_swp_soft_dirty(pte_t pte)
1137 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
1142 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1147 static inline int pmd_swp_soft_dirty(pmd_t pmd)
1152 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1158 #ifndef __HAVE_PFNMAP_TRACKING
1160 * Interfaces that can be used by architecture code to keep track of
1161 * memory type of pfn mappings specified by the remap_pfn_range,
1166 * track_pfn_remap is called when a _new_ pfn mapping is being established
1167 * by remap_pfn_range() for physical range indicated by pfn and size.
1169 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1170 unsigned long pfn, unsigned long addr,
1177 * track_pfn_insert is called when a _new_ single pfn is established
1178 * by vmf_insert_pfn().
1180 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1186 * track_pfn_copy is called when vma that is covering the pfnmap gets
1187 * copied through copy_page_range().
1189 static inline int track_pfn_copy(struct vm_area_struct *vma)
1195 * untrack_pfn is called while unmapping a pfnmap for a region.
1196 * untrack can be called for a specific region indicated by pfn and size or
1197 * can be for the entire vma (in which case pfn, size are zero).
1199 static inline void untrack_pfn(struct vm_area_struct *vma,
1200 unsigned long pfn, unsigned long size,
1206 * untrack_pfn_clear is called while mremapping a pfnmap for a new region
1207 * or fails to copy pgtable during duplicate vm area.
1209 static inline void untrack_pfn_clear(struct vm_area_struct *vma)
1213 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1214 unsigned long pfn, unsigned long addr,
1215 unsigned long size);
1216 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1218 extern int track_pfn_copy(struct vm_area_struct *vma);
1219 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
1220 unsigned long size, bool mm_wr_locked);
1221 extern void untrack_pfn_clear(struct vm_area_struct *vma);
1225 #ifdef __HAVE_COLOR_ZERO_PAGE
1226 static inline int is_zero_pfn(unsigned long pfn)
1228 extern unsigned long zero_pfn;
1229 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
1230 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
1233 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
1236 static inline int is_zero_pfn(unsigned long pfn)
1238 extern unsigned long zero_pfn;
1239 return pfn == zero_pfn;
1242 static inline unsigned long my_zero_pfn(unsigned long addr)
1244 extern unsigned long zero_pfn;
1249 static inline int is_zero_pfn(unsigned long pfn)
1254 static inline unsigned long my_zero_pfn(unsigned long addr)
1258 #endif /* CONFIG_MMU */
1262 #ifndef CONFIG_TRANSPARENT_HUGEPAGE
1263 static inline int pmd_trans_huge(pmd_t pmd)
1268 static inline int pmd_write(pmd_t pmd)
1273 #endif /* pmd_write */
1274 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1277 static inline int pud_write(pud_t pud)
1282 #endif /* pud_write */
1284 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE)
1285 static inline int pmd_devmap(pmd_t pmd)
1289 static inline int pud_devmap(pud_t pud)
1293 static inline int pgd_devmap(pgd_t pgd)
1299 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
1300 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1301 static inline int pud_trans_huge(pud_t pud)
1307 static inline int pud_trans_unstable(pud_t *pud)
1309 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
1310 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1311 pud_t pudval = READ_ONCE(*pud);
1313 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval))
1315 if (unlikely(pud_bad(pudval))) {
1323 #ifndef CONFIG_NUMA_BALANCING
1325 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but
1326 * the only case the kernel cares is for NUMA balancing and is only ever set
1327 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked
1328 * _PAGE_PROTNONE so by default, implement the helper as "always no". It
1329 * is the responsibility of the caller to distinguish between PROT_NONE
1330 * protections and NUMA hinting fault protections.
1332 static inline int pte_protnone(pte_t pte)
1337 static inline int pmd_protnone(pmd_t pmd)
1341 #endif /* CONFIG_NUMA_BALANCING */
1343 #endif /* CONFIG_MMU */
1345 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
1347 #ifndef __PAGETABLE_P4D_FOLDED
1348 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
1349 void p4d_clear_huge(p4d_t *p4d);
1351 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1355 static inline void p4d_clear_huge(p4d_t *p4d) { }
1356 #endif /* !__PAGETABLE_P4D_FOLDED */
1358 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
1359 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
1360 int pud_clear_huge(pud_t *pud);
1361 int pmd_clear_huge(pmd_t *pmd);
1362 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
1363 int pud_free_pmd_page(pud_t *pud, unsigned long addr);
1364 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
1365 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
1366 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1370 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1374 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1378 static inline void p4d_clear_huge(p4d_t *p4d) { }
1379 static inline int pud_clear_huge(pud_t *pud)
1383 static inline int pmd_clear_huge(pmd_t *pmd)
1387 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1391 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
1395 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
1399 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
1401 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
1402 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1404 * ARCHes with special requirements for evicting THP backing TLB entries can
1405 * implement this. Otherwise also, it can help optimize normal TLB flush in
1406 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the
1407 * entire TLB if flush span is greater than a threshold, which will
1408 * likely be true for a single huge page. Thus a single THP flush will
1409 * invalidate the entire TLB which is not desirable.
1410 * e.g. see arch/arc: flush_pmd_tlb_range
1412 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1413 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1415 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
1416 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
1421 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
1422 unsigned long size, pgprot_t *vma_prot);
1424 #ifndef CONFIG_X86_ESPFIX64
1425 static inline void init_espfix_bsp(void) { }
1428 extern void __init pgtable_cache_init(void);
1430 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
1431 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
1436 static inline bool arch_has_pfn_modify_check(void)
1440 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */
1443 * Architecture PAGE_KERNEL_* fallbacks
1445 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
1446 * because they really don't support them, or the port needs to be updated to
1447 * reflect the required functionality. Below are a set of relatively safe
1448 * fallbacks, as best effort, which we can count on in lieu of the architectures
1449 * not defining them on their own yet.
1452 #ifndef PAGE_KERNEL_RO
1453 # define PAGE_KERNEL_RO PAGE_KERNEL
1456 #ifndef PAGE_KERNEL_EXEC
1457 # define PAGE_KERNEL_EXEC PAGE_KERNEL
1461 * Page Table Modification bits for pgtbl_mod_mask.
1463 * These are used by the p?d_alloc_track*() set of functions an in the generic
1464 * vmalloc/ioremap code to track at which page-table levels entries have been
1465 * modified. Based on that the code can better decide when vmalloc and ioremap
1466 * mapping changes need to be synchronized to other page-tables in the system.
1468 #define __PGTBL_PGD_MODIFIED 0
1469 #define __PGTBL_P4D_MODIFIED 1
1470 #define __PGTBL_PUD_MODIFIED 2
1471 #define __PGTBL_PMD_MODIFIED 3
1472 #define __PGTBL_PTE_MODIFIED 4
1474 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
1475 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED)
1476 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
1477 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
1478 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
1480 /* Page-Table Modification Mask */
1481 typedef unsigned int pgtbl_mod_mask;
1483 #endif /* !__ASSEMBLY__ */
1485 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
1486 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1488 * ZSMALLOC needs to know the highest PFN on 32-bit architectures
1489 * with physical address space extension, but falls back to
1490 * BITS_PER_LONG otherwise.
1492 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition
1494 #define MAX_POSSIBLE_PHYSMEM_BITS 32
1498 #ifndef has_transparent_hugepage
1499 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
1503 * On some architectures it depends on the mm if the p4d/pud or pmd
1504 * layer of the page table hierarchy is folded or not.
1506 #ifndef mm_p4d_folded
1507 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
1510 #ifndef mm_pud_folded
1511 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
1514 #ifndef mm_pmd_folded
1515 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
1518 #ifndef p4d_offset_lockless
1519 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address)
1521 #ifndef pud_offset_lockless
1522 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address)
1524 #ifndef pmd_offset_lockless
1525 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address)
1529 * p?d_leaf() - true if this entry is a final mapping to a physical address.
1530 * This differs from p?d_huge() by the fact that they are always available (if
1531 * the architecture supports large pages at the appropriate level) even
1532 * if CONFIG_HUGETLB_PAGE is not defined.
1533 * Only meaningful when called on a valid entry.
1536 #define pgd_leaf(x) 0
1539 #define p4d_leaf(x) 0
1542 #define pud_leaf(x) 0
1545 #define pmd_leaf(x) 0
1548 #ifndef pgd_leaf_size
1549 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
1551 #ifndef p4d_leaf_size
1552 #define p4d_leaf_size(x) P4D_SIZE
1554 #ifndef pud_leaf_size
1555 #define pud_leaf_size(x) PUD_SIZE
1557 #ifndef pmd_leaf_size
1558 #define pmd_leaf_size(x) PMD_SIZE
1560 #ifndef pte_leaf_size
1561 #define pte_leaf_size(x) PAGE_SIZE
1565 * Some architectures have MMUs that are configurable or selectable at boot
1566 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it
1567 * helps to have a static maximum value.
1570 #ifndef MAX_PTRS_PER_PTE
1571 #define MAX_PTRS_PER_PTE PTRS_PER_PTE
1574 #ifndef MAX_PTRS_PER_PMD
1575 #define MAX_PTRS_PER_PMD PTRS_PER_PMD
1578 #ifndef MAX_PTRS_PER_PUD
1579 #define MAX_PTRS_PER_PUD PTRS_PER_PUD
1582 #ifndef MAX_PTRS_PER_P4D
1583 #define MAX_PTRS_PER_P4D PTRS_PER_P4D
1586 /* description of effects of mapping type and prot in current implementation.
1587 * this is due to the limited x86 page protection hardware. The expected
1588 * behavior is in parens:
1591 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC
1592 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1593 * w: (no) no w: (no) no w: (yes) yes w: (no) no
1594 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1596 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1597 * w: (no) no w: (no) no w: (copy) copy w: (no) no
1598 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1600 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and
1601 * MAP_PRIVATE (with Enhanced PAN supported):
1606 #define DECLARE_VM_GET_PAGE_PROT \
1607 pgprot_t vm_get_page_prot(unsigned long vm_flags) \
1609 return protection_map[vm_flags & \
1610 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \
1612 EXPORT_SYMBOL(vm_get_page_prot);
1614 #endif /* _LINUX_PGTABLE_H */