include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
  69         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  70         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  71         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  72         MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
  74         MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
  75 };
  76
  77 enum {
  78         MLX5_SHARED_RESOURCE_UID = 0xffff,
  79 };
  80
  81 enum {
  82         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  83         MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
  84 };
  85
  86 enum {
  87         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  88         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
  91                 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
  92         MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
  93 };
  94
  95 enum {
  96         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  97         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  98         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  99         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
 100         MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
 101         MLX5_OBJ_TYPE_MKEY = 0xff01,
 102         MLX5_OBJ_TYPE_QP = 0xff02,
 103         MLX5_OBJ_TYPE_PSV = 0xff03,
 104         MLX5_OBJ_TYPE_RMP = 0xff04,
 105         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 106         MLX5_OBJ_TYPE_RQ = 0xff06,
 107         MLX5_OBJ_TYPE_SQ = 0xff07,
 108         MLX5_OBJ_TYPE_TIR = 0xff08,
 109         MLX5_OBJ_TYPE_TIS = 0xff09,
 110         MLX5_OBJ_TYPE_DCT = 0xff0a,
 111         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 112         MLX5_OBJ_TYPE_RQT = 0xff0e,
 113         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 114         MLX5_OBJ_TYPE_CQ = 0xff10,
 115 };
 116
 117 enum {
 118         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 119         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 120         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 121         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 122         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 123         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 124         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 125         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 126         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 127         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 128         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 129         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 130         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 131         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 132         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 133         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 134         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 135         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 136         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 137         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 138         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 139         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 140         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 141         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 142         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 143         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 144         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 145         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 146         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 147         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 148         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 149         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 150         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 151         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 152         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 153         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 154         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 155         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 156         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 157         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 158         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 159         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 160         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 161         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 162         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 163         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 164         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 165         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 166         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 167         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 168         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 169         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 170         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 171         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 172         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 173         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 174         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 175         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 176         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 177         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 178         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 179         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 180         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 181         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 182         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 183         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 184         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 185         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 186         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 187         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 188         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 189         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 190         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 191         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 192         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 193         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 194         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 195         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 196         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 197         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 198         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 199         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 200         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 201         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 202         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 203         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 204         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 205         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 206         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 207         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 208         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 209         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 210         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 211         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 212         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 213         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 214         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 215         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 216         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 217         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 218         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 219         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 220         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 221         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 222         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 223         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 224         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 225         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 226         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 227         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 228         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 229         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 230         MLX5_CMD_OP_NOP                           = 0x80d,
 231         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 232         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 233         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 234         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 235         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 236         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 237         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 238         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 239         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 240         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 241         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 242         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 243         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 244         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 245         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 246         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 247         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 248         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 249         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 250         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 251         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 252         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 253         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 254         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 255         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 256         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 257         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 258         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 259         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 260         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 261         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 262         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 263         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 264         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 265         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 266         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 267         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 268         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 269         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 270         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 271         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 272         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 273         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 274         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 275         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 276         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 277         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 278         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 279         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 280         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 281         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 282         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 283         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 284         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 285         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 286         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 287         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 288         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 289         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 290         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 291         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 292         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 293         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 294         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 295         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 296         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 297         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 298         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 299         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 300         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 301         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 302         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 303         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 304         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 305         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 306         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 307         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 308         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 309         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 310         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 311         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 312         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 313         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 314         MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
 315         MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
 316         MLX5_CMD_OP_MAX
 317 };
 318
 319 /* Valid range for general commands that don't work over an object */
 320 enum {
 321         MLX5_CMD_OP_GENERAL_START = 0xb00,
 322         MLX5_CMD_OP_GENERAL_END = 0xd00,
 323 };
 324
 325 enum {
 326         MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
 327         MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
 328 };
 329
 330 enum {
 331         MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
 332 };
 333
 334 struct mlx5_ifc_flow_table_fields_supported_bits {
 335         u8         outer_dmac[0x1];
 336         u8         outer_smac[0x1];
 337         u8         outer_ether_type[0x1];
 338         u8         outer_ip_version[0x1];
 339         u8         outer_first_prio[0x1];
 340         u8         outer_first_cfi[0x1];
 341         u8         outer_first_vid[0x1];
 342         u8         outer_ipv4_ttl[0x1];
 343         u8         outer_second_prio[0x1];
 344         u8         outer_second_cfi[0x1];
 345         u8         outer_second_vid[0x1];
 346         u8         reserved_at_b[0x1];
 347         u8         outer_sip[0x1];
 348         u8         outer_dip[0x1];
 349         u8         outer_frag[0x1];
 350         u8         outer_ip_protocol[0x1];
 351         u8         outer_ip_ecn[0x1];
 352         u8         outer_ip_dscp[0x1];
 353         u8         outer_udp_sport[0x1];
 354         u8         outer_udp_dport[0x1];
 355         u8         outer_tcp_sport[0x1];
 356         u8         outer_tcp_dport[0x1];
 357         u8         outer_tcp_flags[0x1];
 358         u8         outer_gre_protocol[0x1];
 359         u8         outer_gre_key[0x1];
 360         u8         outer_vxlan_vni[0x1];
 361         u8         outer_geneve_vni[0x1];
 362         u8         outer_geneve_oam[0x1];
 363         u8         outer_geneve_protocol_type[0x1];
 364         u8         outer_geneve_opt_len[0x1];
 365         u8         source_vhca_port[0x1];
 366         u8         source_eswitch_port[0x1];
 367
 368         u8         inner_dmac[0x1];
 369         u8         inner_smac[0x1];
 370         u8         inner_ether_type[0x1];
 371         u8         inner_ip_version[0x1];
 372         u8         inner_first_prio[0x1];
 373         u8         inner_first_cfi[0x1];
 374         u8         inner_first_vid[0x1];
 375         u8         reserved_at_27[0x1];
 376         u8         inner_second_prio[0x1];
 377         u8         inner_second_cfi[0x1];
 378         u8         inner_second_vid[0x1];
 379         u8         reserved_at_2b[0x1];
 380         u8         inner_sip[0x1];
 381         u8         inner_dip[0x1];
 382         u8         inner_frag[0x1];
 383         u8         inner_ip_protocol[0x1];
 384         u8         inner_ip_ecn[0x1];
 385         u8         inner_ip_dscp[0x1];
 386         u8         inner_udp_sport[0x1];
 387         u8         inner_udp_dport[0x1];
 388         u8         inner_tcp_sport[0x1];
 389         u8         inner_tcp_dport[0x1];
 390         u8         inner_tcp_flags[0x1];
 391         u8         reserved_at_37[0x9];
 392
 393         u8         geneve_tlv_option_0_data[0x1];
 394         u8         geneve_tlv_option_0_exist[0x1];
 395         u8         reserved_at_42[0x3];
 396         u8         outer_first_mpls_over_udp[0x4];
 397         u8         outer_first_mpls_over_gre[0x4];
 398         u8         inner_first_mpls[0x4];
 399         u8         outer_first_mpls[0x4];
 400         u8         reserved_at_55[0x2];
 401         u8         outer_esp_spi[0x1];
 402         u8         reserved_at_58[0x2];
 403         u8         bth_dst_qp[0x1];
 404         u8         reserved_at_5b[0x5];
 405
 406         u8         reserved_at_60[0x18];
 407         u8         metadata_reg_c_7[0x1];
 408         u8         metadata_reg_c_6[0x1];
 409         u8         metadata_reg_c_5[0x1];
 410         u8         metadata_reg_c_4[0x1];
 411         u8         metadata_reg_c_3[0x1];
 412         u8         metadata_reg_c_2[0x1];
 413         u8         metadata_reg_c_1[0x1];
 414         u8         metadata_reg_c_0[0x1];
 415 };
 416
 417 /* Table 2170 - Flow Table Fields Supported 2 Format */
 418 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 419         u8         reserved_at_0[0xe];
 420         u8         bth_opcode[0x1];
 421         u8         reserved_at_f[0x1];
 422         u8         tunnel_header_0_1[0x1];
 423         u8         reserved_at_11[0xf];
 424
 425         u8         reserved_at_20[0x60];
 426 };
 427
 428 struct mlx5_ifc_flow_table_prop_layout_bits {
 429         u8         ft_support[0x1];
 430         u8         reserved_at_1[0x1];
 431         u8         flow_counter[0x1];
 432         u8         flow_modify_en[0x1];
 433         u8         modify_root[0x1];
 434         u8         identified_miss_table_mode[0x1];
 435         u8         flow_table_modify[0x1];
 436         u8         reformat[0x1];
 437         u8         decap[0x1];
 438         u8         reset_root_to_default[0x1];
 439         u8         pop_vlan[0x1];
 440         u8         push_vlan[0x1];
 441         u8         reserved_at_c[0x1];
 442         u8         pop_vlan_2[0x1];
 443         u8         push_vlan_2[0x1];
 444         u8         reformat_and_vlan_action[0x1];
 445         u8         reserved_at_10[0x1];
 446         u8         sw_owner[0x1];
 447         u8         reformat_l3_tunnel_to_l2[0x1];
 448         u8         reformat_l2_to_l3_tunnel[0x1];
 449         u8         reformat_and_modify_action[0x1];
 450         u8         ignore_flow_level[0x1];
 451         u8         reserved_at_16[0x1];
 452         u8         table_miss_action_domain[0x1];
 453         u8         termination_table[0x1];
 454         u8         reformat_and_fwd_to_table[0x1];
 455         u8         reserved_at_1a[0x2];
 456         u8         ipsec_encrypt[0x1];
 457         u8         ipsec_decrypt[0x1];
 458         u8         sw_owner_v2[0x1];
 459         u8         reserved_at_1f[0x1];
 460
 461         u8         termination_table_raw_traffic[0x1];
 462         u8         reserved_at_21[0x1];
 463         u8         log_max_ft_size[0x6];
 464         u8         log_max_modify_header_context[0x8];
 465         u8         max_modify_header_actions[0x8];
 466         u8         max_ft_level[0x8];
 467
 468         u8         reformat_add_esp_trasport[0x1];
 469         u8         reformat_l2_to_l3_esp_tunnel[0x1];
 470         u8         reformat_add_esp_transport_over_udp[0x1];
 471         u8         reformat_del_esp_trasport[0x1];
 472         u8         reformat_l3_esp_tunnel_to_l2[0x1];
 473         u8         reformat_del_esp_transport_over_udp[0x1];
 474         u8         execute_aso[0x1];
 475         u8         reserved_at_47[0x19];
 476
 477         u8         reserved_at_60[0x2];
 478         u8         reformat_insert[0x1];
 479         u8         reformat_remove[0x1];
 480         u8         macsec_encrypt[0x1];
 481         u8         macsec_decrypt[0x1];
 482         u8         reserved_at_66[0x2];
 483         u8         reformat_add_macsec[0x1];
 484         u8         reformat_remove_macsec[0x1];
 485         u8         reserved_at_6a[0xe];
 486         u8         log_max_ft_num[0x8];
 487
 488         u8         reserved_at_80[0x10];
 489         u8         log_max_flow_counter[0x8];
 490         u8         log_max_destination[0x8];
 491
 492         u8         reserved_at_a0[0x18];
 493         u8         log_max_flow[0x8];
 494
 495         u8         reserved_at_c0[0x40];
 496
 497         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 498
 499         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 500 };
 501
 502 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 503         u8         send[0x1];
 504         u8         receive[0x1];
 505         u8         write[0x1];
 506         u8         read[0x1];
 507         u8         atomic[0x1];
 508         u8         srq_receive[0x1];
 509         u8         reserved_at_6[0x1a];
 510 };
 511
 512 struct mlx5_ifc_ipv4_layout_bits {
 513         u8         reserved_at_0[0x60];
 514
 515         u8         ipv4[0x20];
 516 };
 517
 518 struct mlx5_ifc_ipv6_layout_bits {
 519         u8         ipv6[16][0x8];
 520 };
 521
 522 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 523         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 524         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 525         u8         reserved_at_0[0x80];
 526 };
 527
 528 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 529         u8         smac_47_16[0x20];
 530
 531         u8         smac_15_0[0x10];
 532         u8         ethertype[0x10];
 533
 534         u8         dmac_47_16[0x20];
 535
 536         u8         dmac_15_0[0x10];
 537         u8         first_prio[0x3];
 538         u8         first_cfi[0x1];
 539         u8         first_vid[0xc];
 540
 541         u8         ip_protocol[0x8];
 542         u8         ip_dscp[0x6];
 543         u8         ip_ecn[0x2];
 544         u8         cvlan_tag[0x1];
 545         u8         svlan_tag[0x1];
 546         u8         frag[0x1];
 547         u8         ip_version[0x4];
 548         u8         tcp_flags[0x9];
 549
 550         u8         tcp_sport[0x10];
 551         u8         tcp_dport[0x10];
 552
 553         u8         reserved_at_c0[0x10];
 554         u8         ipv4_ihl[0x4];
 555         u8         reserved_at_c4[0x4];
 556
 557         u8         ttl_hoplimit[0x8];
 558
 559         u8         udp_sport[0x10];
 560         u8         udp_dport[0x10];
 561
 562         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 563
 564         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 565 };
 566
 567 struct mlx5_ifc_nvgre_key_bits {
 568         u8 hi[0x18];
 569         u8 lo[0x8];
 570 };
 571
 572 union mlx5_ifc_gre_key_bits {
 573         struct mlx5_ifc_nvgre_key_bits nvgre;
 574         u8 key[0x20];
 575 };
 576
 577 struct mlx5_ifc_fte_match_set_misc_bits {
 578         u8         gre_c_present[0x1];
 579         u8         reserved_at_1[0x1];
 580         u8         gre_k_present[0x1];
 581         u8         gre_s_present[0x1];
 582         u8         source_vhca_port[0x4];
 583         u8         source_sqn[0x18];
 584
 585         u8         source_eswitch_owner_vhca_id[0x10];
 586         u8         source_port[0x10];
 587
 588         u8         outer_second_prio[0x3];
 589         u8         outer_second_cfi[0x1];
 590         u8         outer_second_vid[0xc];
 591         u8         inner_second_prio[0x3];
 592         u8         inner_second_cfi[0x1];
 593         u8         inner_second_vid[0xc];
 594
 595         u8         outer_second_cvlan_tag[0x1];
 596         u8         inner_second_cvlan_tag[0x1];
 597         u8         outer_second_svlan_tag[0x1];
 598         u8         inner_second_svlan_tag[0x1];
 599         u8         reserved_at_64[0xc];
 600         u8         gre_protocol[0x10];
 601
 602         union mlx5_ifc_gre_key_bits gre_key;
 603
 604         u8         vxlan_vni[0x18];
 605         u8         bth_opcode[0x8];
 606
 607         u8         geneve_vni[0x18];
 608         u8         reserved_at_d8[0x6];
 609         u8         geneve_tlv_option_0_exist[0x1];
 610         u8         geneve_oam[0x1];
 611
 612         u8         reserved_at_e0[0xc];
 613         u8         outer_ipv6_flow_label[0x14];
 614
 615         u8         reserved_at_100[0xc];
 616         u8         inner_ipv6_flow_label[0x14];
 617
 618         u8         reserved_at_120[0xa];
 619         u8         geneve_opt_len[0x6];
 620         u8         geneve_protocol_type[0x10];
 621
 622         u8         reserved_at_140[0x8];
 623         u8         bth_dst_qp[0x18];
 624         u8         inner_esp_spi[0x20];
 625         u8         outer_esp_spi[0x20];
 626         u8         reserved_at_1a0[0x60];
 627 };
 628
 629 struct mlx5_ifc_fte_match_mpls_bits {
 630         u8         mpls_label[0x14];
 631         u8         mpls_exp[0x3];
 632         u8         mpls_s_bos[0x1];
 633         u8         mpls_ttl[0x8];
 634 };
 635
 636 struct mlx5_ifc_fte_match_set_misc2_bits {
 637         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 638
 639         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 640
 641         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 642
 643         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 644
 645         u8         metadata_reg_c_7[0x20];
 646
 647         u8         metadata_reg_c_6[0x20];
 648
 649         u8         metadata_reg_c_5[0x20];
 650
 651         u8         metadata_reg_c_4[0x20];
 652
 653         u8         metadata_reg_c_3[0x20];
 654
 655         u8         metadata_reg_c_2[0x20];
 656
 657         u8         metadata_reg_c_1[0x20];
 658
 659         u8         metadata_reg_c_0[0x20];
 660
 661         u8         metadata_reg_a[0x20];
 662
 663         u8         reserved_at_1a0[0x8];
 664
 665         u8         macsec_syndrome[0x8];
 666         u8         ipsec_syndrome[0x8];
 667         u8         reserved_at_1b8[0x8];
 668
 669         u8         reserved_at_1c0[0x40];
 670 };
 671
 672 struct mlx5_ifc_fte_match_set_misc3_bits {
 673         u8         inner_tcp_seq_num[0x20];
 674
 675         u8         outer_tcp_seq_num[0x20];
 676
 677         u8         inner_tcp_ack_num[0x20];
 678
 679         u8         outer_tcp_ack_num[0x20];
 680
 681         u8         reserved_at_80[0x8];
 682         u8         outer_vxlan_gpe_vni[0x18];
 683
 684         u8         outer_vxlan_gpe_next_protocol[0x8];
 685         u8         outer_vxlan_gpe_flags[0x8];
 686         u8         reserved_at_b0[0x10];
 687
 688         u8         icmp_header_data[0x20];
 689
 690         u8         icmpv6_header_data[0x20];
 691
 692         u8         icmp_type[0x8];
 693         u8         icmp_code[0x8];
 694         u8         icmpv6_type[0x8];
 695         u8         icmpv6_code[0x8];
 696
 697         u8         geneve_tlv_option_0_data[0x20];
 698
 699         u8         gtpu_teid[0x20];
 700
 701         u8         gtpu_msg_type[0x8];
 702         u8         gtpu_msg_flags[0x8];
 703         u8         reserved_at_170[0x10];
 704
 705         u8         gtpu_dw_2[0x20];
 706
 707         u8         gtpu_first_ext_dw_0[0x20];
 708
 709         u8         gtpu_dw_0[0x20];
 710
 711         u8         reserved_at_1e0[0x20];
 712 };
 713
 714 struct mlx5_ifc_fte_match_set_misc4_bits {
 715         u8         prog_sample_field_value_0[0x20];
 716
 717         u8         prog_sample_field_id_0[0x20];
 718
 719         u8         prog_sample_field_value_1[0x20];
 720
 721         u8         prog_sample_field_id_1[0x20];
 722
 723         u8         prog_sample_field_value_2[0x20];
 724
 725         u8         prog_sample_field_id_2[0x20];
 726
 727         u8         prog_sample_field_value_3[0x20];
 728
 729         u8         prog_sample_field_id_3[0x20];
 730
 731         u8         reserved_at_100[0x100];
 732 };
 733
 734 struct mlx5_ifc_fte_match_set_misc5_bits {
 735         u8         macsec_tag_0[0x20];
 736
 737         u8         macsec_tag_1[0x20];
 738
 739         u8         macsec_tag_2[0x20];
 740
 741         u8         macsec_tag_3[0x20];
 742
 743         u8         tunnel_header_0[0x20];
 744
 745         u8         tunnel_header_1[0x20];
 746
 747         u8         tunnel_header_2[0x20];
 748
 749         u8         tunnel_header_3[0x20];
 750
 751         u8         reserved_at_100[0x100];
 752 };
 753
 754 struct mlx5_ifc_cmd_pas_bits {
 755         u8         pa_h[0x20];
 756
 757         u8         pa_l[0x14];
 758         u8         reserved_at_34[0xc];
 759 };
 760
 761 struct mlx5_ifc_uint64_bits {
 762         u8         hi[0x20];
 763
 764         u8         lo[0x20];
 765 };
 766
 767 enum {
 768         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 769         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 770         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 771         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 772         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 773         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 774         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 775         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 776         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 777         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 778 };
 779
 780 struct mlx5_ifc_ads_bits {
 781         u8         fl[0x1];
 782         u8         free_ar[0x1];
 783         u8         reserved_at_2[0xe];
 784         u8         pkey_index[0x10];
 785
 786         u8         reserved_at_20[0x8];
 787         u8         grh[0x1];
 788         u8         mlid[0x7];
 789         u8         rlid[0x10];
 790
 791         u8         ack_timeout[0x5];
 792         u8         reserved_at_45[0x3];
 793         u8         src_addr_index[0x8];
 794         u8         reserved_at_50[0x4];
 795         u8         stat_rate[0x4];
 796         u8         hop_limit[0x8];
 797
 798         u8         reserved_at_60[0x4];
 799         u8         tclass[0x8];
 800         u8         flow_label[0x14];
 801
 802         u8         rgid_rip[16][0x8];
 803
 804         u8         reserved_at_100[0x4];
 805         u8         f_dscp[0x1];
 806         u8         f_ecn[0x1];
 807         u8         reserved_at_106[0x1];
 808         u8         f_eth_prio[0x1];
 809         u8         ecn[0x2];
 810         u8         dscp[0x6];
 811         u8         udp_sport[0x10];
 812
 813         u8         dei_cfi[0x1];
 814         u8         eth_prio[0x3];
 815         u8         sl[0x4];
 816         u8         vhca_port_num[0x8];
 817         u8         rmac_47_32[0x10];
 818
 819         u8         rmac_31_0[0x20];
 820 };
 821
 822 struct mlx5_ifc_flow_table_nic_cap_bits {
 823         u8         nic_rx_multi_path_tirs[0x1];
 824         u8         nic_rx_multi_path_tirs_fts[0x1];
 825         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 826         u8         reserved_at_3[0x4];
 827         u8         sw_owner_reformat_supported[0x1];
 828         u8         reserved_at_8[0x18];
 829
 830         u8         encap_general_header[0x1];
 831         u8         reserved_at_21[0xa];
 832         u8         log_max_packet_reformat_context[0x5];
 833         u8         reserved_at_30[0x6];
 834         u8         max_encap_header_size[0xa];
 835         u8         reserved_at_40[0x1c0];
 836
 837         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 838
 839         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 840
 841         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 842
 843         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 844
 845         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 846
 847         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 848
 849         u8         reserved_at_e00[0x700];
 850
 851         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 852
 853         u8         reserved_at_1580[0x280];
 854
 855         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 856
 857         u8         reserved_at_1880[0x780];
 858
 859         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 860
 861         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 862
 863         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 864
 865         u8         reserved_at_20c0[0x5f40];
 866 };
 867
 868 struct mlx5_ifc_port_selection_cap_bits {
 869         u8         reserved_at_0[0x10];
 870         u8         port_select_flow_table[0x1];
 871         u8         reserved_at_11[0x1];
 872         u8         port_select_flow_table_bypass[0x1];
 873         u8         reserved_at_13[0xd];
 874
 875         u8         reserved_at_20[0x1e0];
 876
 877         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 878
 879         u8         reserved_at_400[0x7c00];
 880 };
 881
 882 enum {
 883         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 884         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 885         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 886         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 887         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 888         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 889         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 890         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 891 };
 892
 893 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 894         u8      fdb_to_vport_reg_c_id[0x8];
 895         u8      reserved_at_8[0x5];
 896         u8      fdb_uplink_hairpin[0x1];
 897         u8      fdb_multi_path_any_table_limit_regc[0x1];
 898         u8      reserved_at_f[0x3];
 899         u8      fdb_multi_path_any_table[0x1];
 900         u8      reserved_at_13[0x2];
 901         u8      fdb_modify_header_fwd_to_table[0x1];
 902         u8      fdb_ipv4_ttl_modify[0x1];
 903         u8      flow_source[0x1];
 904         u8      reserved_at_18[0x2];
 905         u8      multi_fdb_encap[0x1];
 906         u8      egress_acl_forward_to_vport[0x1];
 907         u8      fdb_multi_path_to_table[0x1];
 908         u8      reserved_at_1d[0x3];
 909
 910         u8      reserved_at_20[0x1e0];
 911
 912         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 913
 914         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 915
 916         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 917
 918         u8      reserved_at_800[0xC00];
 919
 920         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
 921
 922         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
 923
 924         u8      reserved_at_1500[0x300];
 925
 926         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 927
 928         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 929
 930         u8      sw_steering_uplink_icm_address_rx[0x40];
 931
 932         u8      sw_steering_uplink_icm_address_tx[0x40];
 933
 934         u8      reserved_at_1900[0x6700];
 935 };
 936
 937 enum {
 938         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 939         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 940 };
 941
 942 struct mlx5_ifc_e_switch_cap_bits {
 943         u8         vport_svlan_strip[0x1];
 944         u8         vport_cvlan_strip[0x1];
 945         u8         vport_svlan_insert[0x1];
 946         u8         vport_cvlan_insert_if_not_exist[0x1];
 947         u8         vport_cvlan_insert_overwrite[0x1];
 948         u8         reserved_at_5[0x1];
 949         u8         vport_cvlan_insert_always[0x1];
 950         u8         esw_shared_ingress_acl[0x1];
 951         u8         esw_uplink_ingress_acl[0x1];
 952         u8         root_ft_on_other_esw[0x1];
 953         u8         reserved_at_a[0xf];
 954         u8         esw_functions_changed[0x1];
 955         u8         reserved_at_1a[0x1];
 956         u8         ecpf_vport_exists[0x1];
 957         u8         counter_eswitch_affinity[0x1];
 958         u8         merged_eswitch[0x1];
 959         u8         nic_vport_node_guid_modify[0x1];
 960         u8         nic_vport_port_guid_modify[0x1];
 961
 962         u8         vxlan_encap_decap[0x1];
 963         u8         nvgre_encap_decap[0x1];
 964         u8         reserved_at_22[0x1];
 965         u8         log_max_fdb_encap_uplink[0x5];
 966         u8         reserved_at_21[0x3];
 967         u8         log_max_packet_reformat_context[0x5];
 968         u8         reserved_2b[0x6];
 969         u8         max_encap_header_size[0xa];
 970
 971         u8         reserved_at_40[0xb];
 972         u8         log_max_esw_sf[0x5];
 973         u8         esw_sf_base_id[0x10];
 974
 975         u8         reserved_at_60[0x7a0];
 976
 977 };
 978
 979 struct mlx5_ifc_qos_cap_bits {
 980         u8         packet_pacing[0x1];
 981         u8         esw_scheduling[0x1];
 982         u8         esw_bw_share[0x1];
 983         u8         esw_rate_limit[0x1];
 984         u8         reserved_at_4[0x1];
 985         u8         packet_pacing_burst_bound[0x1];
 986         u8         packet_pacing_typical_size[0x1];
 987         u8         reserved_at_7[0x1];
 988         u8         nic_sq_scheduling[0x1];
 989         u8         nic_bw_share[0x1];
 990         u8         nic_rate_limit[0x1];
 991         u8         packet_pacing_uid[0x1];
 992         u8         log_esw_max_sched_depth[0x4];
 993         u8         reserved_at_10[0x10];
 994
 995         u8         reserved_at_20[0xb];
 996         u8         log_max_qos_nic_queue_group[0x5];
 997         u8         reserved_at_30[0x10];
 998
 999         u8         packet_pacing_max_rate[0x20];
1000
1001         u8         packet_pacing_min_rate[0x20];
1002
1003         u8         reserved_at_80[0x10];
1004         u8         packet_pacing_rate_table_size[0x10];
1005
1006         u8         esw_element_type[0x10];
1007         u8         esw_tsar_type[0x10];
1008
1009         u8         reserved_at_c0[0x10];
1010         u8         max_qos_para_vport[0x10];
1011
1012         u8         max_tsar_bw_share[0x20];
1013
1014         u8         reserved_at_100[0x20];
1015
1016         u8         reserved_at_120[0x3];
1017         u8         log_meter_aso_granularity[0x5];
1018         u8         reserved_at_128[0x3];
1019         u8         log_meter_aso_max_alloc[0x5];
1020         u8         reserved_at_130[0x3];
1021         u8         log_max_num_meter_aso[0x5];
1022         u8         reserved_at_138[0x8];
1023
1024         u8         reserved_at_140[0x6c0];
1025 };
1026
1027 struct mlx5_ifc_debug_cap_bits {
1028         u8         core_dump_general[0x1];
1029         u8         core_dump_qp[0x1];
1030         u8         reserved_at_2[0x7];
1031         u8         resource_dump[0x1];
1032         u8         reserved_at_a[0x16];
1033
1034         u8         reserved_at_20[0x2];
1035         u8         stall_detect[0x1];
1036         u8         reserved_at_23[0x1d];
1037
1038         u8         reserved_at_40[0x7c0];
1039 };
1040
1041 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1042         u8         csum_cap[0x1];
1043         u8         vlan_cap[0x1];
1044         u8         lro_cap[0x1];
1045         u8         lro_psh_flag[0x1];
1046         u8         lro_time_stamp[0x1];
1047         u8         reserved_at_5[0x2];
1048         u8         wqe_vlan_insert[0x1];
1049         u8         self_lb_en_modifiable[0x1];
1050         u8         reserved_at_9[0x2];
1051         u8         max_lso_cap[0x5];
1052         u8         multi_pkt_send_wqe[0x2];
1053         u8         wqe_inline_mode[0x2];
1054         u8         rss_ind_tbl_cap[0x4];
1055         u8         reg_umr_sq[0x1];
1056         u8         scatter_fcs[0x1];
1057         u8         enhanced_multi_pkt_send_wqe[0x1];
1058         u8         tunnel_lso_const_out_ip_id[0x1];
1059         u8         tunnel_lro_gre[0x1];
1060         u8         tunnel_lro_vxlan[0x1];
1061         u8         tunnel_stateless_gre[0x1];
1062         u8         tunnel_stateless_vxlan[0x1];
1063
1064         u8         swp[0x1];
1065         u8         swp_csum[0x1];
1066         u8         swp_lso[0x1];
1067         u8         cqe_checksum_full[0x1];
1068         u8         tunnel_stateless_geneve_tx[0x1];
1069         u8         tunnel_stateless_mpls_over_udp[0x1];
1070         u8         tunnel_stateless_mpls_over_gre[0x1];
1071         u8         tunnel_stateless_vxlan_gpe[0x1];
1072         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1073         u8         tunnel_stateless_ip_over_ip[0x1];
1074         u8         insert_trailer[0x1];
1075         u8         reserved_at_2b[0x1];
1076         u8         tunnel_stateless_ip_over_ip_rx[0x1];
1077         u8         tunnel_stateless_ip_over_ip_tx[0x1];
1078         u8         reserved_at_2e[0x2];
1079         u8         max_vxlan_udp_ports[0x8];
1080         u8         reserved_at_38[0x6];
1081         u8         max_geneve_opt_len[0x1];
1082         u8         tunnel_stateless_geneve_rx[0x1];
1083
1084         u8         reserved_at_40[0x10];
1085         u8         lro_min_mss_size[0x10];
1086
1087         u8         reserved_at_60[0x120];
1088
1089         u8         lro_timer_supported_periods[4][0x20];
1090
1091         u8         reserved_at_200[0x600];
1092 };
1093
1094 enum {
1095         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1096         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1097         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1098 };
1099
1100 struct mlx5_ifc_roce_cap_bits {
1101         u8         roce_apm[0x1];
1102         u8         reserved_at_1[0x3];
1103         u8         sw_r_roce_src_udp_port[0x1];
1104         u8         fl_rc_qp_when_roce_disabled[0x1];
1105         u8         fl_rc_qp_when_roce_enabled[0x1];
1106         u8         reserved_at_7[0x1];
1107         u8         qp_ooo_transmit_default[0x1];
1108         u8         reserved_at_9[0x15];
1109         u8         qp_ts_format[0x2];
1110
1111         u8         reserved_at_20[0x60];
1112
1113         u8         reserved_at_80[0xc];
1114         u8         l3_type[0x4];
1115         u8         reserved_at_90[0x8];
1116         u8         roce_version[0x8];
1117
1118         u8         reserved_at_a0[0x10];
1119         u8         r_roce_dest_udp_port[0x10];
1120
1121         u8         r_roce_max_src_udp_port[0x10];
1122         u8         r_roce_min_src_udp_port[0x10];
1123
1124         u8         reserved_at_e0[0x10];
1125         u8         roce_address_table_size[0x10];
1126
1127         u8         reserved_at_100[0x700];
1128 };
1129
1130 struct mlx5_ifc_sync_steering_in_bits {
1131         u8         opcode[0x10];
1132         u8         uid[0x10];
1133
1134         u8         reserved_at_20[0x10];
1135         u8         op_mod[0x10];
1136
1137         u8         reserved_at_40[0xc0];
1138 };
1139
1140 struct mlx5_ifc_sync_steering_out_bits {
1141         u8         status[0x8];
1142         u8         reserved_at_8[0x18];
1143
1144         u8         syndrome[0x20];
1145
1146         u8         reserved_at_40[0x40];
1147 };
1148
1149 struct mlx5_ifc_sync_crypto_in_bits {
1150         u8         opcode[0x10];
1151         u8         uid[0x10];
1152
1153         u8         reserved_at_20[0x10];
1154         u8         op_mod[0x10];
1155
1156         u8         reserved_at_40[0x20];
1157
1158         u8         reserved_at_60[0x10];
1159         u8         crypto_type[0x10];
1160
1161         u8         reserved_at_80[0x80];
1162 };
1163
1164 struct mlx5_ifc_sync_crypto_out_bits {
1165         u8         status[0x8];
1166         u8         reserved_at_8[0x18];
1167
1168         u8         syndrome[0x20];
1169
1170         u8         reserved_at_40[0x40];
1171 };
1172
1173 struct mlx5_ifc_device_mem_cap_bits {
1174         u8         memic[0x1];
1175         u8         reserved_at_1[0x1f];
1176
1177         u8         reserved_at_20[0xb];
1178         u8         log_min_memic_alloc_size[0x5];
1179         u8         reserved_at_30[0x8];
1180         u8         log_max_memic_addr_alignment[0x8];
1181
1182         u8         memic_bar_start_addr[0x40];
1183
1184         u8         memic_bar_size[0x20];
1185
1186         u8         max_memic_size[0x20];
1187
1188         u8         steering_sw_icm_start_address[0x40];
1189
1190         u8         reserved_at_100[0x8];
1191         u8         log_header_modify_sw_icm_size[0x8];
1192         u8         reserved_at_110[0x2];
1193         u8         log_sw_icm_alloc_granularity[0x6];
1194         u8         log_steering_sw_icm_size[0x8];
1195
1196         u8         log_indirect_encap_sw_icm_size[0x8];
1197         u8         reserved_at_128[0x10];
1198         u8         log_header_modify_pattern_sw_icm_size[0x8];
1199
1200         u8         header_modify_sw_icm_start_address[0x40];
1201
1202         u8         reserved_at_180[0x40];
1203
1204         u8         header_modify_pattern_sw_icm_start_address[0x40];
1205
1206         u8         memic_operations[0x20];
1207
1208         u8         reserved_at_220[0x20];
1209
1210         u8         indirect_encap_sw_icm_start_address[0x40];
1211
1212         u8         reserved_at_280[0x580];
1213 };
1214
1215 struct mlx5_ifc_device_event_cap_bits {
1216         u8         user_affiliated_events[4][0x40];
1217
1218         u8         user_unaffiliated_events[4][0x40];
1219 };
1220
1221 struct mlx5_ifc_virtio_emulation_cap_bits {
1222         u8         desc_tunnel_offload_type[0x1];
1223         u8         eth_frame_offload_type[0x1];
1224         u8         virtio_version_1_0[0x1];
1225         u8         device_features_bits_mask[0xd];
1226         u8         event_mode[0x8];
1227         u8         virtio_queue_type[0x8];
1228
1229         u8         max_tunnel_desc[0x10];
1230         u8         reserved_at_30[0x3];
1231         u8         log_doorbell_stride[0x5];
1232         u8         reserved_at_38[0x3];
1233         u8         log_doorbell_bar_size[0x5];
1234
1235         u8         doorbell_bar_offset[0x40];
1236
1237         u8         max_emulated_devices[0x8];
1238         u8         max_num_virtio_queues[0x18];
1239
1240         u8         reserved_at_a0[0x20];
1241
1242         u8         reserved_at_c0[0x13];
1243         u8         desc_group_mkey_supported[0x1];
1244         u8         freeze_to_rdy_supported[0x1];
1245         u8         reserved_at_d5[0xb];
1246
1247         u8         reserved_at_e0[0x20];
1248
1249         u8         umem_1_buffer_param_a[0x20];
1250
1251         u8         umem_1_buffer_param_b[0x20];
1252
1253         u8         umem_2_buffer_param_a[0x20];
1254
1255         u8         umem_2_buffer_param_b[0x20];
1256
1257         u8         umem_3_buffer_param_a[0x20];
1258
1259         u8         umem_3_buffer_param_b[0x20];
1260
1261         u8         reserved_at_1c0[0x640];
1262 };
1263
1264 enum {
1265         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1266         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1267         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1268         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1269         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1270         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1271         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1272         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1273         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1274 };
1275
1276 enum {
1277         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1278         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1279         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1280         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1281         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1282         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1283         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1284         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1285         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1286 };
1287
1288 struct mlx5_ifc_atomic_caps_bits {
1289         u8         reserved_at_0[0x40];
1290
1291         u8         atomic_req_8B_endianness_mode[0x2];
1292         u8         reserved_at_42[0x4];
1293         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1294
1295         u8         reserved_at_47[0x19];
1296
1297         u8         reserved_at_60[0x20];
1298
1299         u8         reserved_at_80[0x10];
1300         u8         atomic_operations[0x10];
1301
1302         u8         reserved_at_a0[0x10];
1303         u8         atomic_size_qp[0x10];
1304
1305         u8         reserved_at_c0[0x10];
1306         u8         atomic_size_dc[0x10];
1307
1308         u8         reserved_at_e0[0x720];
1309 };
1310
1311 struct mlx5_ifc_odp_cap_bits {
1312         u8         reserved_at_0[0x40];
1313
1314         u8         sig[0x1];
1315         u8         reserved_at_41[0x1f];
1316
1317         u8         reserved_at_60[0x20];
1318
1319         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1320
1321         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1322
1323         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1324
1325         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1326
1327         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1328
1329         u8         reserved_at_120[0x6E0];
1330 };
1331
1332 struct mlx5_ifc_tls_cap_bits {
1333         u8         tls_1_2_aes_gcm_128[0x1];
1334         u8         tls_1_3_aes_gcm_128[0x1];
1335         u8         tls_1_2_aes_gcm_256[0x1];
1336         u8         tls_1_3_aes_gcm_256[0x1];
1337         u8         reserved_at_4[0x1c];
1338
1339         u8         reserved_at_20[0x7e0];
1340 };
1341
1342 struct mlx5_ifc_ipsec_cap_bits {
1343         u8         ipsec_full_offload[0x1];
1344         u8         ipsec_crypto_offload[0x1];
1345         u8         ipsec_esn[0x1];
1346         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1347         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1348         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1349         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1350         u8         reserved_at_7[0x4];
1351         u8         log_max_ipsec_offload[0x5];
1352         u8         reserved_at_10[0x10];
1353
1354         u8         min_log_ipsec_full_replay_window[0x8];
1355         u8         max_log_ipsec_full_replay_window[0x8];
1356         u8         reserved_at_30[0x7d0];
1357 };
1358
1359 struct mlx5_ifc_macsec_cap_bits {
1360         u8    macsec_epn[0x1];
1361         u8    reserved_at_1[0x2];
1362         u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1363         u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1364         u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1365         u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1366         u8    reserved_at_7[0x4];
1367         u8    log_max_macsec_offload[0x5];
1368         u8    reserved_at_10[0x10];
1369
1370         u8    min_log_macsec_full_replay_window[0x8];
1371         u8    max_log_macsec_full_replay_window[0x8];
1372         u8    reserved_at_30[0x10];
1373
1374         u8    reserved_at_40[0x7c0];
1375 };
1376
1377 enum {
1378         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1379         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1380         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1381         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1382 };
1383
1384 enum {
1385         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1386         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1387 };
1388
1389 enum {
1390         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1391         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1392         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1393         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1394         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1395 };
1396
1397 enum {
1398         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1399         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1400         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1401         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1402         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1403         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1404 };
1405
1406 enum {
1407         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1408         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1409 };
1410
1411 enum {
1412         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1413         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1414         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1415 };
1416
1417 enum {
1418         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1419         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1420 };
1421
1422 enum {
1423         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1424         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1425         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1426 };
1427
1428 enum {
1429         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1430         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1431         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1432         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1433         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1434         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1435         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1436         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1437         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1438         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1439         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1440         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1441 };
1442
1443 enum {
1444         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1445         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1446 };
1447
1448 #define MLX5_FC_BULK_SIZE_FACTOR 128
1449
1450 enum mlx5_fc_bulk_alloc_bitmask {
1451         MLX5_FC_BULK_128   = (1 << 0),
1452         MLX5_FC_BULK_256   = (1 << 1),
1453         MLX5_FC_BULK_512   = (1 << 2),
1454         MLX5_FC_BULK_1024  = (1 << 3),
1455         MLX5_FC_BULK_2048  = (1 << 4),
1456         MLX5_FC_BULK_4096  = (1 << 5),
1457         MLX5_FC_BULK_8192  = (1 << 6),
1458         MLX5_FC_BULK_16384 = (1 << 7),
1459 };
1460
1461 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1462
1463 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1464
1465 enum {
1466         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1467         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1468         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1469 };
1470
1471 struct mlx5_ifc_cmd_hca_cap_bits {
1472         u8         reserved_at_0[0x10];
1473         u8         shared_object_to_user_object_allowed[0x1];
1474         u8         reserved_at_13[0xe];
1475         u8         vhca_resource_manager[0x1];
1476
1477         u8         hca_cap_2[0x1];
1478         u8         create_lag_when_not_master_up[0x1];
1479         u8         dtor[0x1];
1480         u8         event_on_vhca_state_teardown_request[0x1];
1481         u8         event_on_vhca_state_in_use[0x1];
1482         u8         event_on_vhca_state_active[0x1];
1483         u8         event_on_vhca_state_allocated[0x1];
1484         u8         event_on_vhca_state_invalid[0x1];
1485         u8         reserved_at_28[0x8];
1486         u8         vhca_id[0x10];
1487
1488         u8         reserved_at_40[0x40];
1489
1490         u8         log_max_srq_sz[0x8];
1491         u8         log_max_qp_sz[0x8];
1492         u8         event_cap[0x1];
1493         u8         reserved_at_91[0x2];
1494         u8         isolate_vl_tc_new[0x1];
1495         u8         reserved_at_94[0x4];
1496         u8         prio_tag_required[0x1];
1497         u8         reserved_at_99[0x2];
1498         u8         log_max_qp[0x5];
1499
1500         u8         reserved_at_a0[0x3];
1501         u8         ece_support[0x1];
1502         u8         reserved_at_a4[0x5];
1503         u8         reg_c_preserve[0x1];
1504         u8         reserved_at_aa[0x1];
1505         u8         log_max_srq[0x5];
1506         u8         reserved_at_b0[0x1];
1507         u8         uplink_follow[0x1];
1508         u8         ts_cqe_to_dest_cqn[0x1];
1509         u8         reserved_at_b3[0x6];
1510         u8         go_back_n[0x1];
1511         u8         shampo[0x1];
1512         u8         reserved_at_bb[0x5];
1513
1514         u8         max_sgl_for_optimized_performance[0x8];
1515         u8         log_max_cq_sz[0x8];
1516         u8         relaxed_ordering_write_umr[0x1];
1517         u8         relaxed_ordering_read_umr[0x1];
1518         u8         reserved_at_d2[0x7];
1519         u8         virtio_net_device_emualtion_manager[0x1];
1520         u8         virtio_blk_device_emualtion_manager[0x1];
1521         u8         log_max_cq[0x5];
1522
1523         u8         log_max_eq_sz[0x8];
1524         u8         relaxed_ordering_write[0x1];
1525         u8         relaxed_ordering_read_pci_enabled[0x1];
1526         u8         log_max_mkey[0x6];
1527         u8         reserved_at_f0[0x6];
1528         u8         terminate_scatter_list_mkey[0x1];
1529         u8         repeated_mkey[0x1];
1530         u8         dump_fill_mkey[0x1];
1531         u8         reserved_at_f9[0x2];
1532         u8         fast_teardown[0x1];
1533         u8         log_max_eq[0x4];
1534
1535         u8         max_indirection[0x8];
1536         u8         fixed_buffer_size[0x1];
1537         u8         log_max_mrw_sz[0x7];
1538         u8         force_teardown[0x1];
1539         u8         reserved_at_111[0x1];
1540         u8         log_max_bsf_list_size[0x6];
1541         u8         umr_extended_translation_offset[0x1];
1542         u8         null_mkey[0x1];
1543         u8         log_max_klm_list_size[0x6];
1544
1545         u8         reserved_at_120[0x2];
1546         u8         qpc_extension[0x1];
1547         u8         reserved_at_123[0x7];
1548         u8         log_max_ra_req_dc[0x6];
1549         u8         reserved_at_130[0x2];
1550         u8         eth_wqe_too_small[0x1];
1551         u8         reserved_at_133[0x6];
1552         u8         vnic_env_cq_overrun[0x1];
1553         u8         log_max_ra_res_dc[0x6];
1554
1555         u8         reserved_at_140[0x5];
1556         u8         release_all_pages[0x1];
1557         u8         must_not_use[0x1];
1558         u8         reserved_at_147[0x2];
1559         u8         roce_accl[0x1];
1560         u8         log_max_ra_req_qp[0x6];
1561         u8         reserved_at_150[0xa];
1562         u8         log_max_ra_res_qp[0x6];
1563
1564         u8         end_pad[0x1];
1565         u8         cc_query_allowed[0x1];
1566         u8         cc_modify_allowed[0x1];
1567         u8         start_pad[0x1];
1568         u8         cache_line_128byte[0x1];
1569         u8         reserved_at_165[0x4];
1570         u8         rts2rts_qp_counters_set_id[0x1];
1571         u8         reserved_at_16a[0x2];
1572         u8         vnic_env_int_rq_oob[0x1];
1573         u8         sbcam_reg[0x1];
1574         u8         reserved_at_16e[0x1];
1575         u8         qcam_reg[0x1];
1576         u8         gid_table_size[0x10];
1577
1578         u8         out_of_seq_cnt[0x1];
1579         u8         vport_counters[0x1];
1580         u8         retransmission_q_counters[0x1];
1581         u8         debug[0x1];
1582         u8         modify_rq_counter_set_id[0x1];
1583         u8         rq_delay_drop[0x1];
1584         u8         max_qp_cnt[0xa];
1585         u8         pkey_table_size[0x10];
1586
1587         u8         vport_group_manager[0x1];
1588         u8         vhca_group_manager[0x1];
1589         u8         ib_virt[0x1];
1590         u8         eth_virt[0x1];
1591         u8         vnic_env_queue_counters[0x1];
1592         u8         ets[0x1];
1593         u8         nic_flow_table[0x1];
1594         u8         eswitch_manager[0x1];
1595         u8         device_memory[0x1];
1596         u8         mcam_reg[0x1];
1597         u8         pcam_reg[0x1];
1598         u8         local_ca_ack_delay[0x5];
1599         u8         port_module_event[0x1];
1600         u8         enhanced_error_q_counters[0x1];
1601         u8         ports_check[0x1];
1602         u8         reserved_at_1b3[0x1];
1603         u8         disable_link_up[0x1];
1604         u8         beacon_led[0x1];
1605         u8         port_type[0x2];
1606         u8         num_ports[0x8];
1607
1608         u8         reserved_at_1c0[0x1];
1609         u8         pps[0x1];
1610         u8         pps_modify[0x1];
1611         u8         log_max_msg[0x5];
1612         u8         reserved_at_1c8[0x4];
1613         u8         max_tc[0x4];
1614         u8         temp_warn_event[0x1];
1615         u8         dcbx[0x1];
1616         u8         general_notification_event[0x1];
1617         u8         reserved_at_1d3[0x2];
1618         u8         fpga[0x1];
1619         u8         rol_s[0x1];
1620         u8         rol_g[0x1];
1621         u8         reserved_at_1d8[0x1];
1622         u8         wol_s[0x1];
1623         u8         wol_g[0x1];
1624         u8         wol_a[0x1];
1625         u8         wol_b[0x1];
1626         u8         wol_m[0x1];
1627         u8         wol_u[0x1];
1628         u8         wol_p[0x1];
1629
1630         u8         stat_rate_support[0x10];
1631         u8         reserved_at_1f0[0x1];
1632         u8         pci_sync_for_fw_update_event[0x1];
1633         u8         reserved_at_1f2[0x6];
1634         u8         init2_lag_tx_port_affinity[0x1];
1635         u8         reserved_at_1fa[0x3];
1636         u8         cqe_version[0x4];
1637
1638         u8         compact_address_vector[0x1];
1639         u8         striding_rq[0x1];
1640         u8         reserved_at_202[0x1];
1641         u8         ipoib_enhanced_offloads[0x1];
1642         u8         ipoib_basic_offloads[0x1];
1643         u8         reserved_at_205[0x1];
1644         u8         repeated_block_disabled[0x1];
1645         u8         umr_modify_entity_size_disabled[0x1];
1646         u8         umr_modify_atomic_disabled[0x1];
1647         u8         umr_indirect_mkey_disabled[0x1];
1648         u8         umr_fence[0x2];
1649         u8         dc_req_scat_data_cqe[0x1];
1650         u8         reserved_at_20d[0x2];
1651         u8         drain_sigerr[0x1];
1652         u8         cmdif_checksum[0x2];
1653         u8         sigerr_cqe[0x1];
1654         u8         reserved_at_213[0x1];
1655         u8         wq_signature[0x1];
1656         u8         sctr_data_cqe[0x1];
1657         u8         reserved_at_216[0x1];
1658         u8         sho[0x1];
1659         u8         tph[0x1];
1660         u8         rf[0x1];
1661         u8         dct[0x1];
1662         u8         qos[0x1];
1663         u8         eth_net_offloads[0x1];
1664         u8         roce[0x1];
1665         u8         atomic[0x1];
1666         u8         reserved_at_21f[0x1];
1667
1668         u8         cq_oi[0x1];
1669         u8         cq_resize[0x1];
1670         u8         cq_moderation[0x1];
1671         u8         reserved_at_223[0x3];
1672         u8         cq_eq_remap[0x1];
1673         u8         pg[0x1];
1674         u8         block_lb_mc[0x1];
1675         u8         reserved_at_229[0x1];
1676         u8         scqe_break_moderation[0x1];
1677         u8         cq_period_start_from_cqe[0x1];
1678         u8         cd[0x1];
1679         u8         reserved_at_22d[0x1];
1680         u8         apm[0x1];
1681         u8         vector_calc[0x1];
1682         u8         umr_ptr_rlky[0x1];
1683         u8         imaicl[0x1];
1684         u8         qp_packet_based[0x1];
1685         u8         reserved_at_233[0x3];
1686         u8         qkv[0x1];
1687         u8         pkv[0x1];
1688         u8         set_deth_sqpn[0x1];
1689         u8         reserved_at_239[0x3];
1690         u8         xrc[0x1];
1691         u8         ud[0x1];
1692         u8         uc[0x1];
1693         u8         rc[0x1];
1694
1695         u8         uar_4k[0x1];
1696         u8         reserved_at_241[0x7];
1697         u8         fl_rc_qp_when_roce_disabled[0x1];
1698         u8         regexp_params[0x1];
1699         u8         uar_sz[0x6];
1700         u8         port_selection_cap[0x1];
1701         u8         reserved_at_251[0x1];
1702         u8         umem_uid_0[0x1];
1703         u8         reserved_at_253[0x5];
1704         u8         log_pg_sz[0x8];
1705
1706         u8         bf[0x1];
1707         u8         driver_version[0x1];
1708         u8         pad_tx_eth_packet[0x1];
1709         u8         reserved_at_263[0x3];
1710         u8         mkey_by_name[0x1];
1711         u8         reserved_at_267[0x4];
1712
1713         u8         log_bf_reg_size[0x5];
1714
1715         u8         reserved_at_270[0x3];
1716         u8         qp_error_syndrome[0x1];
1717         u8         reserved_at_274[0x2];
1718         u8         lag_dct[0x2];
1719         u8         lag_tx_port_affinity[0x1];
1720         u8         lag_native_fdb_selection[0x1];
1721         u8         reserved_at_27a[0x1];
1722         u8         lag_master[0x1];
1723         u8         num_lag_ports[0x4];
1724
1725         u8         reserved_at_280[0x10];
1726         u8         max_wqe_sz_sq[0x10];
1727
1728         u8         reserved_at_2a0[0x10];
1729         u8         max_wqe_sz_rq[0x10];
1730
1731         u8         max_flow_counter_31_16[0x10];
1732         u8         max_wqe_sz_sq_dc[0x10];
1733
1734         u8         reserved_at_2e0[0x7];
1735         u8         max_qp_mcg[0x19];
1736
1737         u8         reserved_at_300[0x10];
1738         u8         flow_counter_bulk_alloc[0x8];
1739         u8         log_max_mcg[0x8];
1740
1741         u8         reserved_at_320[0x3];
1742         u8         log_max_transport_domain[0x5];
1743         u8         reserved_at_328[0x2];
1744         u8         relaxed_ordering_read[0x1];
1745         u8         log_max_pd[0x5];
1746         u8         reserved_at_330[0x6];
1747         u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1748         u8         vnic_env_cnt_steering_fail[0x1];
1749         u8         vport_counter_local_loopback[0x1];
1750         u8         q_counter_aggregation[0x1];
1751         u8         q_counter_other_vport[0x1];
1752         u8         log_max_xrcd[0x5];
1753
1754         u8         nic_receive_steering_discard[0x1];
1755         u8         receive_discard_vport_down[0x1];
1756         u8         transmit_discard_vport_down[0x1];
1757         u8         eq_overrun_count[0x1];
1758         u8         reserved_at_344[0x1];
1759         u8         invalid_command_count[0x1];
1760         u8         quota_exceeded_count[0x1];
1761         u8         reserved_at_347[0x1];
1762         u8         log_max_flow_counter_bulk[0x8];
1763         u8         max_flow_counter_15_0[0x10];
1764
1765
1766         u8         reserved_at_360[0x3];
1767         u8         log_max_rq[0x5];
1768         u8         reserved_at_368[0x3];
1769         u8         log_max_sq[0x5];
1770         u8         reserved_at_370[0x3];
1771         u8         log_max_tir[0x5];
1772         u8         reserved_at_378[0x3];
1773         u8         log_max_tis[0x5];
1774
1775         u8         basic_cyclic_rcv_wqe[0x1];
1776         u8         reserved_at_381[0x2];
1777         u8         log_max_rmp[0x5];
1778         u8         reserved_at_388[0x3];
1779         u8         log_max_rqt[0x5];
1780         u8         reserved_at_390[0x3];
1781         u8         log_max_rqt_size[0x5];
1782         u8         reserved_at_398[0x3];
1783         u8         log_max_tis_per_sq[0x5];
1784
1785         u8         ext_stride_num_range[0x1];
1786         u8         roce_rw_supported[0x1];
1787         u8         log_max_current_uc_list_wr_supported[0x1];
1788         u8         log_max_stride_sz_rq[0x5];
1789         u8         reserved_at_3a8[0x3];
1790         u8         log_min_stride_sz_rq[0x5];
1791         u8         reserved_at_3b0[0x3];
1792         u8         log_max_stride_sz_sq[0x5];
1793         u8         reserved_at_3b8[0x3];
1794         u8         log_min_stride_sz_sq[0x5];
1795
1796         u8         hairpin[0x1];
1797         u8         reserved_at_3c1[0x2];
1798         u8         log_max_hairpin_queues[0x5];
1799         u8         reserved_at_3c8[0x3];
1800         u8         log_max_hairpin_wq_data_sz[0x5];
1801         u8         reserved_at_3d0[0x3];
1802         u8         log_max_hairpin_num_packets[0x5];
1803         u8         reserved_at_3d8[0x3];
1804         u8         log_max_wq_sz[0x5];
1805
1806         u8         nic_vport_change_event[0x1];
1807         u8         disable_local_lb_uc[0x1];
1808         u8         disable_local_lb_mc[0x1];
1809         u8         log_min_hairpin_wq_data_sz[0x5];
1810         u8         reserved_at_3e8[0x1];
1811         u8         silent_mode[0x1];
1812         u8         vhca_state[0x1];
1813         u8         log_max_vlan_list[0x5];
1814         u8         reserved_at_3f0[0x3];
1815         u8         log_max_current_mc_list[0x5];
1816         u8         reserved_at_3f8[0x3];
1817         u8         log_max_current_uc_list[0x5];
1818
1819         u8         general_obj_types[0x40];
1820
1821         u8         sq_ts_format[0x2];
1822         u8         rq_ts_format[0x2];
1823         u8         steering_format_version[0x4];
1824         u8         create_qp_start_hint[0x18];
1825
1826         u8         reserved_at_460[0x1];
1827         u8         ats[0x1];
1828         u8         cross_vhca_rqt[0x1];
1829         u8         log_max_uctx[0x5];
1830         u8         reserved_at_468[0x1];
1831         u8         crypto[0x1];
1832         u8         ipsec_offload[0x1];
1833         u8         log_max_umem[0x5];
1834         u8         max_num_eqs[0x10];
1835
1836         u8         reserved_at_480[0x1];
1837         u8         tls_tx[0x1];
1838         u8         tls_rx[0x1];
1839         u8         log_max_l2_table[0x5];
1840         u8         reserved_at_488[0x8];
1841         u8         log_uar_page_sz[0x10];
1842
1843         u8         reserved_at_4a0[0x20];
1844         u8         device_frequency_mhz[0x20];
1845         u8         device_frequency_khz[0x20];
1846
1847         u8         reserved_at_500[0x20];
1848         u8         num_of_uars_per_page[0x20];
1849
1850         u8         flex_parser_protocols[0x20];
1851
1852         u8         max_geneve_tlv_options[0x8];
1853         u8         reserved_at_568[0x3];
1854         u8         max_geneve_tlv_option_data_len[0x5];
1855         u8         reserved_at_570[0x9];
1856         u8         adv_virtualization[0x1];
1857         u8         reserved_at_57a[0x6];
1858
1859         u8         reserved_at_580[0xb];
1860         u8         log_max_dci_stream_channels[0x5];
1861         u8         reserved_at_590[0x3];
1862         u8         log_max_dci_errored_streams[0x5];
1863         u8         reserved_at_598[0x8];
1864
1865         u8         reserved_at_5a0[0x10];
1866         u8         enhanced_cqe_compression[0x1];
1867         u8         reserved_at_5b1[0x2];
1868         u8         log_max_dek[0x5];
1869         u8         reserved_at_5b8[0x4];
1870         u8         mini_cqe_resp_stride_index[0x1];
1871         u8         cqe_128_always[0x1];
1872         u8         cqe_compression_128[0x1];
1873         u8         cqe_compression[0x1];
1874
1875         u8         cqe_compression_timeout[0x10];
1876         u8         cqe_compression_max_num[0x10];
1877
1878         u8         reserved_at_5e0[0x8];
1879         u8         flex_parser_id_gtpu_dw_0[0x4];
1880         u8         reserved_at_5ec[0x4];
1881         u8         tag_matching[0x1];
1882         u8         rndv_offload_rc[0x1];
1883         u8         rndv_offload_dc[0x1];
1884         u8         log_tag_matching_list_sz[0x5];
1885         u8         reserved_at_5f8[0x3];
1886         u8         log_max_xrq[0x5];
1887
1888         u8         affiliate_nic_vport_criteria[0x8];
1889         u8         native_port_num[0x8];
1890         u8         num_vhca_ports[0x8];
1891         u8         flex_parser_id_gtpu_teid[0x4];
1892         u8         reserved_at_61c[0x2];
1893         u8         sw_owner_id[0x1];
1894         u8         reserved_at_61f[0x1];
1895
1896         u8         max_num_of_monitor_counters[0x10];
1897         u8         num_ppcnt_monitor_counters[0x10];
1898
1899         u8         max_num_sf[0x10];
1900         u8         num_q_monitor_counters[0x10];
1901
1902         u8         reserved_at_660[0x20];
1903
1904         u8         sf[0x1];
1905         u8         sf_set_partition[0x1];
1906         u8         reserved_at_682[0x1];
1907         u8         log_max_sf[0x5];
1908         u8         apu[0x1];
1909         u8         reserved_at_689[0x4];
1910         u8         migration[0x1];
1911         u8         reserved_at_68e[0x2];
1912         u8         log_min_sf_size[0x8];
1913         u8         max_num_sf_partitions[0x8];
1914
1915         u8         uctx_cap[0x20];
1916
1917         u8         reserved_at_6c0[0x4];
1918         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1919         u8         flex_parser_id_icmp_dw1[0x4];
1920         u8         flex_parser_id_icmp_dw0[0x4];
1921         u8         flex_parser_id_icmpv6_dw1[0x4];
1922         u8         flex_parser_id_icmpv6_dw0[0x4];
1923         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1924         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1925
1926         u8         max_num_match_definer[0x10];
1927         u8         sf_base_id[0x10];
1928
1929         u8         flex_parser_id_gtpu_dw_2[0x4];
1930         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1931         u8         num_total_dynamic_vf_msix[0x18];
1932         u8         reserved_at_720[0x14];
1933         u8         dynamic_msix_table_size[0xc];
1934         u8         reserved_at_740[0xc];
1935         u8         min_dynamic_vf_msix_table_size[0x4];
1936         u8         reserved_at_750[0x4];
1937         u8         max_dynamic_vf_msix_table_size[0xc];
1938
1939         u8         reserved_at_760[0x3];
1940         u8         log_max_num_header_modify_argument[0x5];
1941         u8         reserved_at_768[0x4];
1942         u8         log_header_modify_argument_granularity[0x4];
1943         u8         reserved_at_770[0x3];
1944         u8         log_header_modify_argument_max_alloc[0x5];
1945         u8         reserved_at_778[0x8];
1946
1947         u8         vhca_tunnel_commands[0x40];
1948         u8         match_definer_format_supported[0x40];
1949 };
1950
1951 enum {
1952         MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
1953         MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
1954 };
1955
1956 enum {
1957         MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
1958 };
1959
1960 struct mlx5_ifc_cmd_hca_cap_2_bits {
1961         u8         reserved_at_0[0x80];
1962
1963         u8         migratable[0x1];
1964         u8         reserved_at_81[0x1f];
1965
1966         u8         max_reformat_insert_size[0x8];
1967         u8         max_reformat_insert_offset[0x8];
1968         u8         max_reformat_remove_size[0x8];
1969         u8         max_reformat_remove_offset[0x8];
1970
1971         u8         reserved_at_c0[0x8];
1972         u8         migration_multi_load[0x1];
1973         u8         migration_tracking_state[0x1];
1974         u8         reserved_at_ca[0x6];
1975         u8         migration_in_chunks[0x1];
1976         u8         reserved_at_d1[0xf];
1977
1978         u8         cross_vhca_object_to_object_supported[0x20];
1979
1980         u8         allowed_object_for_other_vhca_access[0x40];
1981
1982         u8         reserved_at_140[0x60];
1983
1984         u8         flow_table_type_2_type[0x8];
1985         u8         reserved_at_1a8[0x3];
1986         u8         log_min_mkey_entity_size[0x5];
1987         u8         reserved_at_1b0[0x10];
1988
1989         u8         reserved_at_1c0[0x60];
1990
1991         u8         reserved_at_220[0x1];
1992         u8         sw_vhca_id_valid[0x1];
1993         u8         sw_vhca_id[0xe];
1994         u8         reserved_at_230[0x10];
1995
1996         u8         reserved_at_240[0xb];
1997         u8         ts_cqe_metadata_size2wqe_counter[0x5];
1998         u8         reserved_at_250[0x10];
1999
2000         u8         reserved_at_260[0x120];
2001         u8         reserved_at_380[0x10];
2002         u8         ec_vf_vport_base[0x10];
2003
2004         u8         reserved_at_3a0[0x10];
2005         u8         max_rqt_vhca_id[0x10];
2006
2007         u8         reserved_at_3c0[0x440];
2008 };
2009
2010 enum mlx5_ifc_flow_destination_type {
2011         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2012         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2013         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2014         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2015         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2016         MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2017 };
2018
2019 enum mlx5_flow_table_miss_action {
2020         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2021         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2022         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2023 };
2024
2025 struct mlx5_ifc_dest_format_struct_bits {
2026         u8         destination_type[0x8];
2027         u8         destination_id[0x18];
2028
2029         u8         destination_eswitch_owner_vhca_id_valid[0x1];
2030         u8         packet_reformat[0x1];
2031         u8         reserved_at_22[0x6];
2032         u8         destination_table_type[0x8];
2033         u8         destination_eswitch_owner_vhca_id[0x10];
2034 };
2035
2036 struct mlx5_ifc_flow_counter_list_bits {
2037         u8         flow_counter_id[0x20];
2038
2039         u8         reserved_at_20[0x20];
2040 };
2041
2042 struct mlx5_ifc_extended_dest_format_bits {
2043         struct mlx5_ifc_dest_format_struct_bits destination_entry;
2044
2045         u8         packet_reformat_id[0x20];
2046
2047         u8         reserved_at_60[0x20];
2048 };
2049
2050 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2051         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2052         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2053 };
2054
2055 struct mlx5_ifc_fte_match_param_bits {
2056         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2057
2058         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2059
2060         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2061
2062         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2063
2064         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2065
2066         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2067
2068         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2069
2070         u8         reserved_at_e00[0x200];
2071 };
2072
2073 enum {
2074         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2075         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2076         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2077         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2078         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2079 };
2080
2081 struct mlx5_ifc_rx_hash_field_select_bits {
2082         u8         l3_prot_type[0x1];
2083         u8         l4_prot_type[0x1];
2084         u8         selected_fields[0x1e];
2085 };
2086
2087 enum {
2088         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2089         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2090 };
2091
2092 enum {
2093         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2094         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2095 };
2096
2097 struct mlx5_ifc_wq_bits {
2098         u8         wq_type[0x4];
2099         u8         wq_signature[0x1];
2100         u8         end_padding_mode[0x2];
2101         u8         cd_slave[0x1];
2102         u8         reserved_at_8[0x18];
2103
2104         u8         hds_skip_first_sge[0x1];
2105         u8         log2_hds_buf_size[0x3];
2106         u8         reserved_at_24[0x7];
2107         u8         page_offset[0x5];
2108         u8         lwm[0x10];
2109
2110         u8         reserved_at_40[0x8];
2111         u8         pd[0x18];
2112
2113         u8         reserved_at_60[0x8];
2114         u8         uar_page[0x18];
2115
2116         u8         dbr_addr[0x40];
2117
2118         u8         hw_counter[0x20];
2119
2120         u8         sw_counter[0x20];
2121
2122         u8         reserved_at_100[0xc];
2123         u8         log_wq_stride[0x4];
2124         u8         reserved_at_110[0x3];
2125         u8         log_wq_pg_sz[0x5];
2126         u8         reserved_at_118[0x3];
2127         u8         log_wq_sz[0x5];
2128
2129         u8         dbr_umem_valid[0x1];
2130         u8         wq_umem_valid[0x1];
2131         u8         reserved_at_122[0x1];
2132         u8         log_hairpin_num_packets[0x5];
2133         u8         reserved_at_128[0x3];
2134         u8         log_hairpin_data_sz[0x5];
2135
2136         u8         reserved_at_130[0x4];
2137         u8         log_wqe_num_of_strides[0x4];
2138         u8         two_byte_shift_en[0x1];
2139         u8         reserved_at_139[0x4];
2140         u8         log_wqe_stride_size[0x3];
2141
2142         u8         reserved_at_140[0x80];
2143
2144         u8         headers_mkey[0x20];
2145
2146         u8         shampo_enable[0x1];
2147         u8         reserved_at_1e1[0x4];
2148         u8         log_reservation_size[0x3];
2149         u8         reserved_at_1e8[0x5];
2150         u8         log_max_num_of_packets_per_reservation[0x3];
2151         u8         reserved_at_1f0[0x6];
2152         u8         log_headers_entry_size[0x2];
2153         u8         reserved_at_1f8[0x4];
2154         u8         log_headers_buffer_entry_num[0x4];
2155
2156         u8         reserved_at_200[0x400];
2157
2158         struct mlx5_ifc_cmd_pas_bits pas[];
2159 };
2160
2161 struct mlx5_ifc_rq_num_bits {
2162         u8         reserved_at_0[0x8];
2163         u8         rq_num[0x18];
2164 };
2165
2166 struct mlx5_ifc_rq_vhca_bits {
2167         u8         reserved_at_0[0x8];
2168         u8         rq_num[0x18];
2169         u8         reserved_at_20[0x10];
2170         u8         rq_vhca_id[0x10];
2171 };
2172
2173 struct mlx5_ifc_mac_address_layout_bits {
2174         u8         reserved_at_0[0x10];
2175         u8         mac_addr_47_32[0x10];
2176
2177         u8         mac_addr_31_0[0x20];
2178 };
2179
2180 struct mlx5_ifc_vlan_layout_bits {
2181         u8         reserved_at_0[0x14];
2182         u8         vlan[0x0c];
2183
2184         u8         reserved_at_20[0x20];
2185 };
2186
2187 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2188         u8         reserved_at_0[0xa0];
2189
2190         u8         min_time_between_cnps[0x20];
2191
2192         u8         reserved_at_c0[0x12];
2193         u8         cnp_dscp[0x6];
2194         u8         reserved_at_d8[0x4];
2195         u8         cnp_prio_mode[0x1];
2196         u8         cnp_802p_prio[0x3];
2197
2198         u8         reserved_at_e0[0x720];
2199 };
2200
2201 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2202         u8         reserved_at_0[0x60];
2203
2204         u8         reserved_at_60[0x4];
2205         u8         clamp_tgt_rate[0x1];
2206         u8         reserved_at_65[0x3];
2207         u8         clamp_tgt_rate_after_time_inc[0x1];
2208         u8         reserved_at_69[0x17];
2209
2210         u8         reserved_at_80[0x20];
2211
2212         u8         rpg_time_reset[0x20];
2213
2214         u8         rpg_byte_reset[0x20];
2215
2216         u8         rpg_threshold[0x20];
2217
2218         u8         rpg_max_rate[0x20];
2219
2220         u8         rpg_ai_rate[0x20];
2221
2222         u8         rpg_hai_rate[0x20];
2223
2224         u8         rpg_gd[0x20];
2225
2226         u8         rpg_min_dec_fac[0x20];
2227
2228         u8         rpg_min_rate[0x20];
2229
2230         u8         reserved_at_1c0[0xe0];
2231
2232         u8         rate_to_set_on_first_cnp[0x20];
2233
2234         u8         dce_tcp_g[0x20];
2235
2236         u8         dce_tcp_rtt[0x20];
2237
2238         u8         rate_reduce_monitor_period[0x20];
2239
2240         u8         reserved_at_320[0x20];
2241
2242         u8         initial_alpha_value[0x20];
2243
2244         u8         reserved_at_360[0x4a0];
2245 };
2246
2247 struct mlx5_ifc_cong_control_r_roce_general_bits {
2248         u8         reserved_at_0[0x80];
2249
2250         u8         reserved_at_80[0x10];
2251         u8         rtt_resp_dscp_valid[0x1];
2252         u8         reserved_at_91[0x9];
2253         u8         rtt_resp_dscp[0x6];
2254
2255         u8         reserved_at_a0[0x760];
2256 };
2257
2258 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2259         u8         reserved_at_0[0x80];
2260
2261         u8         rppp_max_rps[0x20];
2262
2263         u8         rpg_time_reset[0x20];
2264
2265         u8         rpg_byte_reset[0x20];
2266
2267         u8         rpg_threshold[0x20];
2268
2269         u8         rpg_max_rate[0x20];
2270
2271         u8         rpg_ai_rate[0x20];
2272
2273         u8         rpg_hai_rate[0x20];
2274
2275         u8         rpg_gd[0x20];
2276
2277         u8         rpg_min_dec_fac[0x20];
2278
2279         u8         rpg_min_rate[0x20];
2280
2281         u8         reserved_at_1c0[0x640];
2282 };
2283
2284 enum {
2285         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2286         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2287         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2288 };
2289
2290 struct mlx5_ifc_resize_field_select_bits {
2291         u8         resize_field_select[0x20];
2292 };
2293
2294 struct mlx5_ifc_resource_dump_bits {
2295         u8         more_dump[0x1];
2296         u8         inline_dump[0x1];
2297         u8         reserved_at_2[0xa];
2298         u8         seq_num[0x4];
2299         u8         segment_type[0x10];
2300
2301         u8         reserved_at_20[0x10];
2302         u8         vhca_id[0x10];
2303
2304         u8         index1[0x20];
2305
2306         u8         index2[0x20];
2307
2308         u8         num_of_obj1[0x10];
2309         u8         num_of_obj2[0x10];
2310
2311         u8         reserved_at_a0[0x20];
2312
2313         u8         device_opaque[0x40];
2314
2315         u8         mkey[0x20];
2316
2317         u8         size[0x20];
2318
2319         u8         address[0x40];
2320
2321         u8         inline_data[52][0x20];
2322 };
2323
2324 struct mlx5_ifc_resource_dump_menu_record_bits {
2325         u8         reserved_at_0[0x4];
2326         u8         num_of_obj2_supports_active[0x1];
2327         u8         num_of_obj2_supports_all[0x1];
2328         u8         must_have_num_of_obj2[0x1];
2329         u8         support_num_of_obj2[0x1];
2330         u8         num_of_obj1_supports_active[0x1];
2331         u8         num_of_obj1_supports_all[0x1];
2332         u8         must_have_num_of_obj1[0x1];
2333         u8         support_num_of_obj1[0x1];
2334         u8         must_have_index2[0x1];
2335         u8         support_index2[0x1];
2336         u8         must_have_index1[0x1];
2337         u8         support_index1[0x1];
2338         u8         segment_type[0x10];
2339
2340         u8         segment_name[4][0x20];
2341
2342         u8         index1_name[4][0x20];
2343
2344         u8         index2_name[4][0x20];
2345 };
2346
2347 struct mlx5_ifc_resource_dump_segment_header_bits {
2348         u8         length_dw[0x10];
2349         u8         segment_type[0x10];
2350 };
2351
2352 struct mlx5_ifc_resource_dump_command_segment_bits {
2353         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2354
2355         u8         segment_called[0x10];
2356         u8         vhca_id[0x10];
2357
2358         u8         index1[0x20];
2359
2360         u8         index2[0x20];
2361
2362         u8         num_of_obj1[0x10];
2363         u8         num_of_obj2[0x10];
2364 };
2365
2366 struct mlx5_ifc_resource_dump_error_segment_bits {
2367         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2368
2369         u8         reserved_at_20[0x10];
2370         u8         syndrome_id[0x10];
2371
2372         u8         reserved_at_40[0x40];
2373
2374         u8         error[8][0x20];
2375 };
2376
2377 struct mlx5_ifc_resource_dump_info_segment_bits {
2378         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2379
2380         u8         reserved_at_20[0x18];
2381         u8         dump_version[0x8];
2382
2383         u8         hw_version[0x20];
2384
2385         u8         fw_version[0x20];
2386 };
2387
2388 struct mlx5_ifc_resource_dump_menu_segment_bits {
2389         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2390
2391         u8         reserved_at_20[0x10];
2392         u8         num_of_records[0x10];
2393
2394         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2395 };
2396
2397 struct mlx5_ifc_resource_dump_resource_segment_bits {
2398         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2399
2400         u8         reserved_at_20[0x20];
2401
2402         u8         index1[0x20];
2403
2404         u8         index2[0x20];
2405
2406         u8         payload[][0x20];
2407 };
2408
2409 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2410         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2411 };
2412
2413 struct mlx5_ifc_menu_resource_dump_response_bits {
2414         struct mlx5_ifc_resource_dump_info_segment_bits info;
2415         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2416         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2417         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2418 };
2419
2420 enum {
2421         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2422         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2423         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2424         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2425 };
2426
2427 struct mlx5_ifc_modify_field_select_bits {
2428         u8         modify_field_select[0x20];
2429 };
2430
2431 struct mlx5_ifc_field_select_r_roce_np_bits {
2432         u8         field_select_r_roce_np[0x20];
2433 };
2434
2435 struct mlx5_ifc_field_select_r_roce_rp_bits {
2436         u8         field_select_r_roce_rp[0x20];
2437 };
2438
2439 enum {
2440         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2441         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2442         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2443         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2444         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2445         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2446         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2447         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2448         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2449         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2450 };
2451
2452 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2453         u8         field_select_8021qaurp[0x20];
2454 };
2455
2456 struct mlx5_ifc_phys_layer_cntrs_bits {
2457         u8         time_since_last_clear_high[0x20];
2458
2459         u8         time_since_last_clear_low[0x20];
2460
2461         u8         symbol_errors_high[0x20];
2462
2463         u8         symbol_errors_low[0x20];
2464
2465         u8         sync_headers_errors_high[0x20];
2466
2467         u8         sync_headers_errors_low[0x20];
2468
2469         u8         edpl_bip_errors_lane0_high[0x20];
2470
2471         u8         edpl_bip_errors_lane0_low[0x20];
2472
2473         u8         edpl_bip_errors_lane1_high[0x20];
2474
2475         u8         edpl_bip_errors_lane1_low[0x20];
2476
2477         u8         edpl_bip_errors_lane2_high[0x20];
2478
2479         u8         edpl_bip_errors_lane2_low[0x20];
2480
2481         u8         edpl_bip_errors_lane3_high[0x20];
2482
2483         u8         edpl_bip_errors_lane3_low[0x20];
2484
2485         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2486
2487         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2488
2489         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2490
2491         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2492
2493         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2494
2495         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2496
2497         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2498
2499         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2500
2501         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2502
2503         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2504
2505         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2506
2507         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2508
2509         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2510
2511         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2512
2513         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2514
2515         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2516
2517         u8         rs_fec_corrected_blocks_high[0x20];
2518
2519         u8         rs_fec_corrected_blocks_low[0x20];
2520
2521         u8         rs_fec_uncorrectable_blocks_high[0x20];
2522
2523         u8         rs_fec_uncorrectable_blocks_low[0x20];
2524
2525         u8         rs_fec_no_errors_blocks_high[0x20];
2526
2527         u8         rs_fec_no_errors_blocks_low[0x20];
2528
2529         u8         rs_fec_single_error_blocks_high[0x20];
2530
2531         u8         rs_fec_single_error_blocks_low[0x20];
2532
2533         u8         rs_fec_corrected_symbols_total_high[0x20];
2534
2535         u8         rs_fec_corrected_symbols_total_low[0x20];
2536
2537         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2538
2539         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2540
2541         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2542
2543         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2544
2545         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2546
2547         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2548
2549         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2550
2551         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2552
2553         u8         link_down_events[0x20];
2554
2555         u8         successful_recovery_events[0x20];
2556
2557         u8         reserved_at_640[0x180];
2558 };
2559
2560 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2561         u8         time_since_last_clear_high[0x20];
2562
2563         u8         time_since_last_clear_low[0x20];
2564
2565         u8         phy_received_bits_high[0x20];
2566
2567         u8         phy_received_bits_low[0x20];
2568
2569         u8         phy_symbol_errors_high[0x20];
2570
2571         u8         phy_symbol_errors_low[0x20];
2572
2573         u8         phy_corrected_bits_high[0x20];
2574
2575         u8         phy_corrected_bits_low[0x20];
2576
2577         u8         phy_corrected_bits_lane0_high[0x20];
2578
2579         u8         phy_corrected_bits_lane0_low[0x20];
2580
2581         u8         phy_corrected_bits_lane1_high[0x20];
2582
2583         u8         phy_corrected_bits_lane1_low[0x20];
2584
2585         u8         phy_corrected_bits_lane2_high[0x20];
2586
2587         u8         phy_corrected_bits_lane2_low[0x20];
2588
2589         u8         phy_corrected_bits_lane3_high[0x20];
2590
2591         u8         phy_corrected_bits_lane3_low[0x20];
2592
2593         u8         reserved_at_200[0x5c0];
2594 };
2595
2596 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2597         u8         symbol_error_counter[0x10];
2598
2599         u8         link_error_recovery_counter[0x8];
2600
2601         u8         link_downed_counter[0x8];
2602
2603         u8         port_rcv_errors[0x10];
2604
2605         u8         port_rcv_remote_physical_errors[0x10];
2606
2607         u8         port_rcv_switch_relay_errors[0x10];
2608
2609         u8         port_xmit_discards[0x10];
2610
2611         u8         port_xmit_constraint_errors[0x8];
2612
2613         u8         port_rcv_constraint_errors[0x8];
2614
2615         u8         reserved_at_70[0x8];
2616
2617         u8         link_overrun_errors[0x8];
2618
2619         u8         reserved_at_80[0x10];
2620
2621         u8         vl_15_dropped[0x10];
2622
2623         u8         reserved_at_a0[0x80];
2624
2625         u8         port_xmit_wait[0x20];
2626 };
2627
2628 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2629         u8         transmit_queue_high[0x20];
2630
2631         u8         transmit_queue_low[0x20];
2632
2633         u8         no_buffer_discard_uc_high[0x20];
2634
2635         u8         no_buffer_discard_uc_low[0x20];
2636
2637         u8         reserved_at_80[0x740];
2638 };
2639
2640 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2641         u8         wred_discard_high[0x20];
2642
2643         u8         wred_discard_low[0x20];
2644
2645         u8         ecn_marked_tc_high[0x20];
2646
2647         u8         ecn_marked_tc_low[0x20];
2648
2649         u8         reserved_at_80[0x740];
2650 };
2651
2652 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2653         u8         rx_octets_high[0x20];
2654
2655         u8         rx_octets_low[0x20];
2656
2657         u8         reserved_at_40[0xc0];
2658
2659         u8         rx_frames_high[0x20];
2660
2661         u8         rx_frames_low[0x20];
2662
2663         u8         tx_octets_high[0x20];
2664
2665         u8         tx_octets_low[0x20];
2666
2667         u8         reserved_at_180[0xc0];
2668
2669         u8         tx_frames_high[0x20];
2670
2671         u8         tx_frames_low[0x20];
2672
2673         u8         rx_pause_high[0x20];
2674
2675         u8         rx_pause_low[0x20];
2676
2677         u8         rx_pause_duration_high[0x20];
2678
2679         u8         rx_pause_duration_low[0x20];
2680
2681         u8         tx_pause_high[0x20];
2682
2683         u8         tx_pause_low[0x20];
2684
2685         u8         tx_pause_duration_high[0x20];
2686
2687         u8         tx_pause_duration_low[0x20];
2688
2689         u8         rx_pause_transition_high[0x20];
2690
2691         u8         rx_pause_transition_low[0x20];
2692
2693         u8         rx_discards_high[0x20];
2694
2695         u8         rx_discards_low[0x20];
2696
2697         u8         device_stall_minor_watermark_cnt_high[0x20];
2698
2699         u8         device_stall_minor_watermark_cnt_low[0x20];
2700
2701         u8         device_stall_critical_watermark_cnt_high[0x20];
2702
2703         u8         device_stall_critical_watermark_cnt_low[0x20];
2704
2705         u8         reserved_at_480[0x340];
2706 };
2707
2708 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2709         u8         port_transmit_wait_high[0x20];
2710
2711         u8         port_transmit_wait_low[0x20];
2712
2713         u8         reserved_at_40[0x100];
2714
2715         u8         rx_buffer_almost_full_high[0x20];
2716
2717         u8         rx_buffer_almost_full_low[0x20];
2718
2719         u8         rx_buffer_full_high[0x20];
2720
2721         u8         rx_buffer_full_low[0x20];
2722
2723         u8         rx_icrc_encapsulated_high[0x20];
2724
2725         u8         rx_icrc_encapsulated_low[0x20];
2726
2727         u8         reserved_at_200[0x5c0];
2728 };
2729
2730 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2731         u8         dot3stats_alignment_errors_high[0x20];
2732
2733         u8         dot3stats_alignment_errors_low[0x20];
2734
2735         u8         dot3stats_fcs_errors_high[0x20];
2736
2737         u8         dot3stats_fcs_errors_low[0x20];
2738
2739         u8         dot3stats_single_collision_frames_high[0x20];
2740
2741         u8         dot3stats_single_collision_frames_low[0x20];
2742
2743         u8         dot3stats_multiple_collision_frames_high[0x20];
2744
2745         u8         dot3stats_multiple_collision_frames_low[0x20];
2746
2747         u8         dot3stats_sqe_test_errors_high[0x20];
2748
2749         u8         dot3stats_sqe_test_errors_low[0x20];
2750
2751         u8         dot3stats_deferred_transmissions_high[0x20];
2752
2753         u8         dot3stats_deferred_transmissions_low[0x20];
2754
2755         u8         dot3stats_late_collisions_high[0x20];
2756
2757         u8         dot3stats_late_collisions_low[0x20];
2758
2759         u8         dot3stats_excessive_collisions_high[0x20];
2760
2761         u8         dot3stats_excessive_collisions_low[0x20];
2762
2763         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2764
2765         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2766
2767         u8         dot3stats_carrier_sense_errors_high[0x20];
2768
2769         u8         dot3stats_carrier_sense_errors_low[0x20];
2770
2771         u8         dot3stats_frame_too_longs_high[0x20];
2772
2773         u8         dot3stats_frame_too_longs_low[0x20];
2774
2775         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2776
2777         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2778
2779         u8         dot3stats_symbol_errors_high[0x20];
2780
2781         u8         dot3stats_symbol_errors_low[0x20];
2782
2783         u8         dot3control_in_unknown_opcodes_high[0x20];
2784
2785         u8         dot3control_in_unknown_opcodes_low[0x20];
2786
2787         u8         dot3in_pause_frames_high[0x20];
2788
2789         u8         dot3in_pause_frames_low[0x20];
2790
2791         u8         dot3out_pause_frames_high[0x20];
2792
2793         u8         dot3out_pause_frames_low[0x20];
2794
2795         u8         reserved_at_400[0x3c0];
2796 };
2797
2798 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2799         u8         ether_stats_drop_events_high[0x20];
2800
2801         u8         ether_stats_drop_events_low[0x20];
2802
2803         u8         ether_stats_octets_high[0x20];
2804
2805         u8         ether_stats_octets_low[0x20];
2806
2807         u8         ether_stats_pkts_high[0x20];
2808
2809         u8         ether_stats_pkts_low[0x20];
2810
2811         u8         ether_stats_broadcast_pkts_high[0x20];
2812
2813         u8         ether_stats_broadcast_pkts_low[0x20];
2814
2815         u8         ether_stats_multicast_pkts_high[0x20];
2816
2817         u8         ether_stats_multicast_pkts_low[0x20];
2818
2819         u8         ether_stats_crc_align_errors_high[0x20];
2820
2821         u8         ether_stats_crc_align_errors_low[0x20];
2822
2823         u8         ether_stats_undersize_pkts_high[0x20];
2824
2825         u8         ether_stats_undersize_pkts_low[0x20];
2826
2827         u8         ether_stats_oversize_pkts_high[0x20];
2828
2829         u8         ether_stats_oversize_pkts_low[0x20];
2830
2831         u8         ether_stats_fragments_high[0x20];
2832
2833         u8         ether_stats_fragments_low[0x20];
2834
2835         u8         ether_stats_jabbers_high[0x20];
2836
2837         u8         ether_stats_jabbers_low[0x20];
2838
2839         u8         ether_stats_collisions_high[0x20];
2840
2841         u8         ether_stats_collisions_low[0x20];
2842
2843         u8         ether_stats_pkts64octets_high[0x20];
2844
2845         u8         ether_stats_pkts64octets_low[0x20];
2846
2847         u8         ether_stats_pkts65to127octets_high[0x20];
2848
2849         u8         ether_stats_pkts65to127octets_low[0x20];
2850
2851         u8         ether_stats_pkts128to255octets_high[0x20];
2852
2853         u8         ether_stats_pkts128to255octets_low[0x20];
2854
2855         u8         ether_stats_pkts256to511octets_high[0x20];
2856
2857         u8         ether_stats_pkts256to511octets_low[0x20];
2858
2859         u8         ether_stats_pkts512to1023octets_high[0x20];
2860
2861         u8         ether_stats_pkts512to1023octets_low[0x20];
2862
2863         u8         ether_stats_pkts1024to1518octets_high[0x20];
2864
2865         u8         ether_stats_pkts1024to1518octets_low[0x20];
2866
2867         u8         ether_stats_pkts1519to2047octets_high[0x20];
2868
2869         u8         ether_stats_pkts1519to2047octets_low[0x20];
2870
2871         u8         ether_stats_pkts2048to4095octets_high[0x20];
2872
2873         u8         ether_stats_pkts2048to4095octets_low[0x20];
2874
2875         u8         ether_stats_pkts4096to8191octets_high[0x20];
2876
2877         u8         ether_stats_pkts4096to8191octets_low[0x20];
2878
2879         u8         ether_stats_pkts8192to10239octets_high[0x20];
2880
2881         u8         ether_stats_pkts8192to10239octets_low[0x20];
2882
2883         u8         reserved_at_540[0x280];
2884 };
2885
2886 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2887         u8         if_in_octets_high[0x20];
2888
2889         u8         if_in_octets_low[0x20];
2890
2891         u8         if_in_ucast_pkts_high[0x20];
2892
2893         u8         if_in_ucast_pkts_low[0x20];
2894
2895         u8         if_in_discards_high[0x20];
2896
2897         u8         if_in_discards_low[0x20];
2898
2899         u8         if_in_errors_high[0x20];
2900
2901         u8         if_in_errors_low[0x20];
2902
2903         u8         if_in_unknown_protos_high[0x20];
2904
2905         u8         if_in_unknown_protos_low[0x20];
2906
2907         u8         if_out_octets_high[0x20];
2908
2909         u8         if_out_octets_low[0x20];
2910
2911         u8         if_out_ucast_pkts_high[0x20];
2912
2913         u8         if_out_ucast_pkts_low[0x20];
2914
2915         u8         if_out_discards_high[0x20];
2916
2917         u8         if_out_discards_low[0x20];
2918
2919         u8         if_out_errors_high[0x20];
2920
2921         u8         if_out_errors_low[0x20];
2922
2923         u8         if_in_multicast_pkts_high[0x20];
2924
2925         u8         if_in_multicast_pkts_low[0x20];
2926
2927         u8         if_in_broadcast_pkts_high[0x20];
2928
2929         u8         if_in_broadcast_pkts_low[0x20];
2930
2931         u8         if_out_multicast_pkts_high[0x20];
2932
2933         u8         if_out_multicast_pkts_low[0x20];
2934
2935         u8         if_out_broadcast_pkts_high[0x20];
2936
2937         u8         if_out_broadcast_pkts_low[0x20];
2938
2939         u8         reserved_at_340[0x480];
2940 };
2941
2942 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2943         u8         a_frames_transmitted_ok_high[0x20];
2944
2945         u8         a_frames_transmitted_ok_low[0x20];
2946
2947         u8         a_frames_received_ok_high[0x20];
2948
2949         u8         a_frames_received_ok_low[0x20];
2950
2951         u8         a_frame_check_sequence_errors_high[0x20];
2952
2953         u8         a_frame_check_sequence_errors_low[0x20];
2954
2955         u8         a_alignment_errors_high[0x20];
2956
2957         u8         a_alignment_errors_low[0x20];
2958
2959         u8         a_octets_transmitted_ok_high[0x20];
2960
2961         u8         a_octets_transmitted_ok_low[0x20];
2962
2963         u8         a_octets_received_ok_high[0x20];
2964
2965         u8         a_octets_received_ok_low[0x20];
2966
2967         u8         a_multicast_frames_xmitted_ok_high[0x20];
2968
2969         u8         a_multicast_frames_xmitted_ok_low[0x20];
2970
2971         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2972
2973         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2974
2975         u8         a_multicast_frames_received_ok_high[0x20];
2976
2977         u8         a_multicast_frames_received_ok_low[0x20];
2978
2979         u8         a_broadcast_frames_received_ok_high[0x20];
2980
2981         u8         a_broadcast_frames_received_ok_low[0x20];
2982
2983         u8         a_in_range_length_errors_high[0x20];
2984
2985         u8         a_in_range_length_errors_low[0x20];
2986
2987         u8         a_out_of_range_length_field_high[0x20];
2988
2989         u8         a_out_of_range_length_field_low[0x20];
2990
2991         u8         a_frame_too_long_errors_high[0x20];
2992
2993         u8         a_frame_too_long_errors_low[0x20];
2994
2995         u8         a_symbol_error_during_carrier_high[0x20];
2996
2997         u8         a_symbol_error_during_carrier_low[0x20];
2998
2999         u8         a_mac_control_frames_transmitted_high[0x20];
3000
3001         u8         a_mac_control_frames_transmitted_low[0x20];
3002
3003         u8         a_mac_control_frames_received_high[0x20];
3004
3005         u8         a_mac_control_frames_received_low[0x20];
3006
3007         u8         a_unsupported_opcodes_received_high[0x20];
3008
3009         u8         a_unsupported_opcodes_received_low[0x20];
3010
3011         u8         a_pause_mac_ctrl_frames_received_high[0x20];
3012
3013         u8         a_pause_mac_ctrl_frames_received_low[0x20];
3014
3015         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3016
3017         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3018
3019         u8         reserved_at_4c0[0x300];
3020 };
3021
3022 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3023         u8         life_time_counter_high[0x20];
3024
3025         u8         life_time_counter_low[0x20];
3026
3027         u8         rx_errors[0x20];
3028
3029         u8         tx_errors[0x20];
3030
3031         u8         l0_to_recovery_eieos[0x20];
3032
3033         u8         l0_to_recovery_ts[0x20];
3034
3035         u8         l0_to_recovery_framing[0x20];
3036
3037         u8         l0_to_recovery_retrain[0x20];
3038
3039         u8         crc_error_dllp[0x20];
3040
3041         u8         crc_error_tlp[0x20];
3042
3043         u8         tx_overflow_buffer_pkt_high[0x20];
3044
3045         u8         tx_overflow_buffer_pkt_low[0x20];
3046
3047         u8         outbound_stalled_reads[0x20];
3048
3049         u8         outbound_stalled_writes[0x20];
3050
3051         u8         outbound_stalled_reads_events[0x20];
3052
3053         u8         outbound_stalled_writes_events[0x20];
3054
3055         u8         reserved_at_200[0x5c0];
3056 };
3057
3058 struct mlx5_ifc_cmd_inter_comp_event_bits {
3059         u8         command_completion_vector[0x20];
3060
3061         u8         reserved_at_20[0xc0];
3062 };
3063
3064 struct mlx5_ifc_stall_vl_event_bits {
3065         u8         reserved_at_0[0x18];
3066         u8         port_num[0x1];
3067         u8         reserved_at_19[0x3];
3068         u8         vl[0x4];
3069
3070         u8         reserved_at_20[0xa0];
3071 };
3072
3073 struct mlx5_ifc_db_bf_congestion_event_bits {
3074         u8         event_subtype[0x8];
3075         u8         reserved_at_8[0x8];
3076         u8         congestion_level[0x8];
3077         u8         reserved_at_18[0x8];
3078
3079         u8         reserved_at_20[0xa0];
3080 };
3081
3082 struct mlx5_ifc_gpio_event_bits {
3083         u8         reserved_at_0[0x60];
3084
3085         u8         gpio_event_hi[0x20];
3086
3087         u8         gpio_event_lo[0x20];
3088
3089         u8         reserved_at_a0[0x40];
3090 };
3091
3092 struct mlx5_ifc_port_state_change_event_bits {
3093         u8         reserved_at_0[0x40];
3094
3095         u8         port_num[0x4];
3096         u8         reserved_at_44[0x1c];
3097
3098         u8         reserved_at_60[0x80];
3099 };
3100
3101 struct mlx5_ifc_dropped_packet_logged_bits {
3102         u8         reserved_at_0[0xe0];
3103 };
3104
3105 struct mlx5_ifc_default_timeout_bits {
3106         u8         to_multiplier[0x3];
3107         u8         reserved_at_3[0x9];
3108         u8         to_value[0x14];
3109 };
3110
3111 struct mlx5_ifc_dtor_reg_bits {
3112         u8         reserved_at_0[0x20];
3113
3114         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3115
3116         u8         reserved_at_40[0x60];
3117
3118         struct mlx5_ifc_default_timeout_bits health_poll_to;
3119
3120         struct mlx5_ifc_default_timeout_bits full_crdump_to;
3121
3122         struct mlx5_ifc_default_timeout_bits fw_reset_to;
3123
3124         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3125
3126         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3127
3128         struct mlx5_ifc_default_timeout_bits tear_down_to;
3129
3130         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3131
3132         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3133
3134         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3135
3136         struct mlx5_ifc_default_timeout_bits reset_unload_to;
3137
3138         u8         reserved_at_1c0[0x20];
3139 };
3140
3141 enum {
3142         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3143         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3144 };
3145
3146 struct mlx5_ifc_cq_error_bits {
3147         u8         reserved_at_0[0x8];
3148         u8         cqn[0x18];
3149
3150         u8         reserved_at_20[0x20];
3151
3152         u8         reserved_at_40[0x18];
3153         u8         syndrome[0x8];
3154
3155         u8         reserved_at_60[0x80];
3156 };
3157
3158 struct mlx5_ifc_rdma_page_fault_event_bits {
3159         u8         bytes_committed[0x20];
3160
3161         u8         r_key[0x20];
3162
3163         u8         reserved_at_40[0x10];
3164         u8         packet_len[0x10];
3165
3166         u8         rdma_op_len[0x20];
3167
3168         u8         rdma_va[0x40];
3169
3170         u8         reserved_at_c0[0x5];
3171         u8         rdma[0x1];
3172         u8         write[0x1];
3173         u8         requestor[0x1];
3174         u8         qp_number[0x18];
3175 };
3176
3177 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3178         u8         bytes_committed[0x20];
3179
3180         u8         reserved_at_20[0x10];
3181         u8         wqe_index[0x10];
3182
3183         u8         reserved_at_40[0x10];
3184         u8         len[0x10];
3185
3186         u8         reserved_at_60[0x60];
3187
3188         u8         reserved_at_c0[0x5];
3189         u8         rdma[0x1];
3190         u8         write_read[0x1];
3191         u8         requestor[0x1];
3192         u8         qpn[0x18];
3193 };
3194
3195 struct mlx5_ifc_qp_events_bits {
3196         u8         reserved_at_0[0xa0];
3197
3198         u8         type[0x8];
3199         u8         reserved_at_a8[0x18];
3200
3201         u8         reserved_at_c0[0x8];
3202         u8         qpn_rqn_sqn[0x18];
3203 };
3204
3205 struct mlx5_ifc_dct_events_bits {
3206         u8         reserved_at_0[0xc0];
3207
3208         u8         reserved_at_c0[0x8];
3209         u8         dct_number[0x18];
3210 };
3211
3212 struct mlx5_ifc_comp_event_bits {
3213         u8         reserved_at_0[0xc0];
3214
3215         u8         reserved_at_c0[0x8];
3216         u8         cq_number[0x18];
3217 };
3218
3219 enum {
3220         MLX5_QPC_STATE_RST        = 0x0,
3221         MLX5_QPC_STATE_INIT       = 0x1,
3222         MLX5_QPC_STATE_RTR        = 0x2,
3223         MLX5_QPC_STATE_RTS        = 0x3,
3224         MLX5_QPC_STATE_SQER       = 0x4,
3225         MLX5_QPC_STATE_ERR        = 0x6,
3226         MLX5_QPC_STATE_SQD        = 0x7,
3227         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3228 };
3229
3230 enum {
3231         MLX5_QPC_ST_RC            = 0x0,
3232         MLX5_QPC_ST_UC            = 0x1,
3233         MLX5_QPC_ST_UD            = 0x2,
3234         MLX5_QPC_ST_XRC           = 0x3,
3235         MLX5_QPC_ST_DCI           = 0x5,
3236         MLX5_QPC_ST_QP0           = 0x7,
3237         MLX5_QPC_ST_QP1           = 0x8,
3238         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3239         MLX5_QPC_ST_REG_UMR       = 0xc,
3240 };
3241
3242 enum {
3243         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3244         MLX5_QPC_PM_STATE_REARM     = 0x1,
3245         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3246         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3247 };
3248
3249 enum {
3250         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3251 };
3252
3253 enum {
3254         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3255         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3256 };
3257
3258 enum {
3259         MLX5_QPC_MTU_256_BYTES        = 0x1,
3260         MLX5_QPC_MTU_512_BYTES        = 0x2,
3261         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3262         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3263         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3264         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3265 };
3266
3267 enum {
3268         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3269         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3270         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3271         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3272         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3273         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3274         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3275         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3276 };
3277
3278 enum {
3279         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3280         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3281         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3282 };
3283
3284 enum {
3285         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3286         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3287         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3288 };
3289
3290 enum {
3291         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3292         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3293         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3294 };
3295
3296 struct mlx5_ifc_qpc_bits {
3297         u8         state[0x4];
3298         u8         lag_tx_port_affinity[0x4];
3299         u8         st[0x8];
3300         u8         reserved_at_10[0x2];
3301         u8         isolate_vl_tc[0x1];
3302         u8         pm_state[0x2];
3303         u8         reserved_at_15[0x1];
3304         u8         req_e2e_credit_mode[0x2];
3305         u8         offload_type[0x4];
3306         u8         end_padding_mode[0x2];
3307         u8         reserved_at_1e[0x2];
3308
3309         u8         wq_signature[0x1];
3310         u8         block_lb_mc[0x1];
3311         u8         atomic_like_write_en[0x1];
3312         u8         latency_sensitive[0x1];
3313         u8         reserved_at_24[0x1];
3314         u8         drain_sigerr[0x1];
3315         u8         reserved_at_26[0x2];
3316         u8         pd[0x18];
3317
3318         u8         mtu[0x3];
3319         u8         log_msg_max[0x5];
3320         u8         reserved_at_48[0x1];
3321         u8         log_rq_size[0x4];
3322         u8         log_rq_stride[0x3];
3323         u8         no_sq[0x1];
3324         u8         log_sq_size[0x4];
3325         u8         reserved_at_55[0x1];
3326         u8         retry_mode[0x2];
3327         u8         ts_format[0x2];
3328         u8         reserved_at_5a[0x1];
3329         u8         rlky[0x1];
3330         u8         ulp_stateless_offload_mode[0x4];
3331
3332         u8         counter_set_id[0x8];
3333         u8         uar_page[0x18];
3334
3335         u8         reserved_at_80[0x8];
3336         u8         user_index[0x18];
3337
3338         u8         reserved_at_a0[0x3];
3339         u8         log_page_size[0x5];
3340         u8         remote_qpn[0x18];
3341
3342         struct mlx5_ifc_ads_bits primary_address_path;
3343
3344         struct mlx5_ifc_ads_bits secondary_address_path;
3345
3346         u8         log_ack_req_freq[0x4];
3347         u8         reserved_at_384[0x4];
3348         u8         log_sra_max[0x3];
3349         u8         reserved_at_38b[0x2];
3350         u8         retry_count[0x3];
3351         u8         rnr_retry[0x3];
3352         u8         reserved_at_393[0x1];
3353         u8         fre[0x1];
3354         u8         cur_rnr_retry[0x3];
3355         u8         cur_retry_count[0x3];
3356         u8         reserved_at_39b[0x5];
3357
3358         u8         reserved_at_3a0[0x20];
3359
3360         u8         reserved_at_3c0[0x8];
3361         u8         next_send_psn[0x18];
3362
3363         u8         reserved_at_3e0[0x3];
3364         u8         log_num_dci_stream_channels[0x5];
3365         u8         cqn_snd[0x18];
3366
3367         u8         reserved_at_400[0x3];
3368         u8         log_num_dci_errored_streams[0x5];
3369         u8         deth_sqpn[0x18];
3370
3371         u8         reserved_at_420[0x20];
3372
3373         u8         reserved_at_440[0x8];
3374         u8         last_acked_psn[0x18];
3375
3376         u8         reserved_at_460[0x8];
3377         u8         ssn[0x18];
3378
3379         u8         reserved_at_480[0x8];
3380         u8         log_rra_max[0x3];
3381         u8         reserved_at_48b[0x1];
3382         u8         atomic_mode[0x4];
3383         u8         rre[0x1];
3384         u8         rwe[0x1];
3385         u8         rae[0x1];
3386         u8         reserved_at_493[0x1];
3387         u8         page_offset[0x6];
3388         u8         reserved_at_49a[0x3];
3389         u8         cd_slave_receive[0x1];
3390         u8         cd_slave_send[0x1];
3391         u8         cd_master[0x1];
3392
3393         u8         reserved_at_4a0[0x3];
3394         u8         min_rnr_nak[0x5];
3395         u8         next_rcv_psn[0x18];
3396
3397         u8         reserved_at_4c0[0x8];
3398         u8         xrcd[0x18];
3399
3400         u8         reserved_at_4e0[0x8];
3401         u8         cqn_rcv[0x18];
3402
3403         u8         dbr_addr[0x40];
3404
3405         u8         q_key[0x20];
3406
3407         u8         reserved_at_560[0x5];
3408         u8         rq_type[0x3];
3409         u8         srqn_rmpn_xrqn[0x18];
3410
3411         u8         reserved_at_580[0x8];
3412         u8         rmsn[0x18];
3413
3414         u8         hw_sq_wqebb_counter[0x10];
3415         u8         sw_sq_wqebb_counter[0x10];
3416
3417         u8         hw_rq_counter[0x20];
3418
3419         u8         sw_rq_counter[0x20];
3420
3421         u8         reserved_at_600[0x20];
3422
3423         u8         reserved_at_620[0xf];
3424         u8         cgs[0x1];
3425         u8         cs_req[0x8];
3426         u8         cs_res[0x8];
3427
3428         u8         dc_access_key[0x40];
3429
3430         u8         reserved_at_680[0x3];
3431         u8         dbr_umem_valid[0x1];
3432
3433         u8         reserved_at_684[0xbc];
3434 };
3435
3436 struct mlx5_ifc_roce_addr_layout_bits {
3437         u8         source_l3_address[16][0x8];
3438
3439         u8         reserved_at_80[0x3];
3440         u8         vlan_valid[0x1];
3441         u8         vlan_id[0xc];
3442         u8         source_mac_47_32[0x10];
3443
3444         u8         source_mac_31_0[0x20];
3445
3446         u8         reserved_at_c0[0x14];
3447         u8         roce_l3_type[0x4];
3448         u8         roce_version[0x8];
3449
3450         u8         reserved_at_e0[0x20];
3451 };
3452
3453 struct mlx5_ifc_crypto_cap_bits {
3454         u8    reserved_at_0[0x3];
3455         u8    synchronize_dek[0x1];
3456         u8    int_kek_manual[0x1];
3457         u8    int_kek_auto[0x1];
3458         u8    reserved_at_6[0x1a];
3459
3460         u8    reserved_at_20[0x3];
3461         u8    log_dek_max_alloc[0x5];
3462         u8    reserved_at_28[0x3];
3463         u8    log_max_num_deks[0x5];
3464         u8    reserved_at_30[0x10];
3465
3466         u8    reserved_at_40[0x20];
3467
3468         u8    reserved_at_60[0x3];
3469         u8    log_dek_granularity[0x5];
3470         u8    reserved_at_68[0x3];
3471         u8    log_max_num_int_kek[0x5];
3472         u8    sw_wrapped_dek[0x10];
3473
3474         u8    reserved_at_80[0x780];
3475 };
3476
3477 union mlx5_ifc_hca_cap_union_bits {
3478         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3479         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3480         struct mlx5_ifc_odp_cap_bits odp_cap;
3481         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3482         struct mlx5_ifc_roce_cap_bits roce_cap;
3483         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3484         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3485         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3486         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3487         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3488         struct mlx5_ifc_qos_cap_bits qos_cap;
3489         struct mlx5_ifc_debug_cap_bits debug_cap;
3490         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3491         struct mlx5_ifc_tls_cap_bits tls_cap;
3492         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3493         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3494         struct mlx5_ifc_macsec_cap_bits macsec_cap;
3495         struct mlx5_ifc_crypto_cap_bits crypto_cap;
3496         struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3497         u8         reserved_at_0[0x8000];
3498 };
3499
3500 enum {
3501         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3502         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3503         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3504         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3505         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3506         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3507         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3508         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3509         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3510         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3511         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3512         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3513         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3514         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3515 };
3516
3517 enum {
3518         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3519         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3520         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3521 };
3522
3523 enum {
3524         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3525         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3526 };
3527
3528 struct mlx5_ifc_vlan_bits {
3529         u8         ethtype[0x10];
3530         u8         prio[0x3];
3531         u8         cfi[0x1];
3532         u8         vid[0xc];
3533 };
3534
3535 enum {
3536         MLX5_FLOW_METER_COLOR_RED       = 0x0,
3537         MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
3538         MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
3539         MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3540 };
3541
3542 enum {
3543         MLX5_EXE_ASO_FLOW_METER         = 0x2,
3544 };
3545
3546 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3547         u8        return_reg_id[0x4];
3548         u8        aso_type[0x4];
3549         u8        reserved_at_8[0x14];
3550         u8        action[0x1];
3551         u8        init_color[0x2];
3552         u8        meter_id[0x1];
3553 };
3554
3555 union mlx5_ifc_exe_aso_ctrl {
3556         struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3557 };
3558
3559 struct mlx5_ifc_execute_aso_bits {
3560         u8        valid[0x1];
3561         u8        reserved_at_1[0x7];
3562         u8        aso_object_id[0x18];
3563
3564         union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3565 };
3566
3567 struct mlx5_ifc_flow_context_bits {
3568         struct mlx5_ifc_vlan_bits push_vlan;
3569
3570         u8         group_id[0x20];
3571
3572         u8         reserved_at_40[0x8];
3573         u8         flow_tag[0x18];
3574
3575         u8         reserved_at_60[0x10];
3576         u8         action[0x10];
3577
3578         u8         extended_destination[0x1];
3579         u8         reserved_at_81[0x1];
3580         u8         flow_source[0x2];
3581         u8         encrypt_decrypt_type[0x4];
3582         u8         destination_list_size[0x18];
3583
3584         u8         reserved_at_a0[0x8];
3585         u8         flow_counter_list_size[0x18];
3586
3587         u8         packet_reformat_id[0x20];
3588
3589         u8         modify_header_id[0x20];
3590
3591         struct mlx5_ifc_vlan_bits push_vlan_2;
3592
3593         u8         encrypt_decrypt_obj_id[0x20];
3594         u8         reserved_at_140[0xc0];
3595
3596         struct mlx5_ifc_fte_match_param_bits match_value;
3597
3598         struct mlx5_ifc_execute_aso_bits execute_aso[4];
3599
3600         u8         reserved_at_1300[0x500];
3601
3602         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3603 };
3604
3605 enum {
3606         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3607         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3608 };
3609
3610 struct mlx5_ifc_xrc_srqc_bits {
3611         u8         state[0x4];
3612         u8         log_xrc_srq_size[0x4];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         wq_signature[0x1];
3616         u8         cont_srq[0x1];
3617         u8         reserved_at_22[0x1];
3618         u8         rlky[0x1];
3619         u8         basic_cyclic_rcv_wqe[0x1];
3620         u8         log_rq_stride[0x3];
3621         u8         xrcd[0x18];
3622
3623         u8         page_offset[0x6];
3624         u8         reserved_at_46[0x1];
3625         u8         dbr_umem_valid[0x1];
3626         u8         cqn[0x18];
3627
3628         u8         reserved_at_60[0x20];
3629
3630         u8         user_index_equal_xrc_srqn[0x1];
3631         u8         reserved_at_81[0x1];
3632         u8         log_page_size[0x6];
3633         u8         user_index[0x18];
3634
3635         u8         reserved_at_a0[0x20];
3636
3637         u8         reserved_at_c0[0x8];
3638         u8         pd[0x18];
3639
3640         u8         lwm[0x10];
3641         u8         wqe_cnt[0x10];
3642
3643         u8         reserved_at_100[0x40];
3644
3645         u8         db_record_addr_h[0x20];
3646
3647         u8         db_record_addr_l[0x1e];
3648         u8         reserved_at_17e[0x2];
3649
3650         u8         reserved_at_180[0x80];
3651 };
3652
3653 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3654         u8         counter_error_queues[0x20];
3655
3656         u8         total_error_queues[0x20];
3657
3658         u8         send_queue_priority_update_flow[0x20];
3659
3660         u8         reserved_at_60[0x20];
3661
3662         u8         nic_receive_steering_discard[0x40];
3663
3664         u8         receive_discard_vport_down[0x40];
3665
3666         u8         transmit_discard_vport_down[0x40];
3667
3668         u8         async_eq_overrun[0x20];
3669
3670         u8         comp_eq_overrun[0x20];
3671
3672         u8         reserved_at_180[0x20];
3673
3674         u8         invalid_command[0x20];
3675
3676         u8         quota_exceeded_command[0x20];
3677
3678         u8         internal_rq_out_of_buffer[0x20];
3679
3680         u8         cq_overrun[0x20];
3681
3682         u8         eth_wqe_too_small[0x20];
3683
3684         u8         reserved_at_220[0xc0];
3685
3686         u8         generated_pkt_steering_fail[0x40];
3687
3688         u8         handled_pkt_steering_fail[0x40];
3689
3690         u8         reserved_at_360[0xc80];
3691 };
3692
3693 struct mlx5_ifc_traffic_counter_bits {
3694         u8         packets[0x40];
3695
3696         u8         octets[0x40];
3697 };
3698
3699 struct mlx5_ifc_tisc_bits {
3700         u8         strict_lag_tx_port_affinity[0x1];
3701         u8         tls_en[0x1];
3702         u8         reserved_at_2[0x2];
3703         u8         lag_tx_port_affinity[0x04];
3704
3705         u8         reserved_at_8[0x4];
3706         u8         prio[0x4];
3707         u8         reserved_at_10[0x10];
3708
3709         u8         reserved_at_20[0x100];
3710
3711         u8         reserved_at_120[0x8];
3712         u8         transport_domain[0x18];
3713
3714         u8         reserved_at_140[0x8];
3715         u8         underlay_qpn[0x18];
3716
3717         u8         reserved_at_160[0x8];
3718         u8         pd[0x18];
3719
3720         u8         reserved_at_180[0x380];
3721 };
3722
3723 enum {
3724         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3725         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3726 };
3727
3728 enum {
3729         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3730         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3731 };
3732
3733 enum {
3734         MLX5_RX_HASH_FN_NONE           = 0x0,
3735         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3736         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3737 };
3738
3739 enum {
3740         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3741         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3742 };
3743
3744 struct mlx5_ifc_tirc_bits {
3745         u8         reserved_at_0[0x20];
3746
3747         u8         disp_type[0x4];
3748         u8         tls_en[0x1];
3749         u8         reserved_at_25[0x1b];
3750
3751         u8         reserved_at_40[0x40];
3752
3753         u8         reserved_at_80[0x4];
3754         u8         lro_timeout_period_usecs[0x10];
3755         u8         packet_merge_mask[0x4];
3756         u8         lro_max_ip_payload_size[0x8];
3757
3758         u8         reserved_at_a0[0x40];
3759
3760         u8         reserved_at_e0[0x8];
3761         u8         inline_rqn[0x18];
3762
3763         u8         rx_hash_symmetric[0x1];
3764         u8         reserved_at_101[0x1];
3765         u8         tunneled_offload_en[0x1];
3766         u8         reserved_at_103[0x5];
3767         u8         indirect_table[0x18];
3768
3769         u8         rx_hash_fn[0x4];
3770         u8         reserved_at_124[0x2];
3771         u8         self_lb_block[0x2];
3772         u8         transport_domain[0x18];
3773
3774         u8         rx_hash_toeplitz_key[10][0x20];
3775
3776         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3777
3778         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3779
3780         u8         reserved_at_2c0[0x4c0];
3781 };
3782
3783 enum {
3784         MLX5_SRQC_STATE_GOOD   = 0x0,
3785         MLX5_SRQC_STATE_ERROR  = 0x1,
3786 };
3787
3788 struct mlx5_ifc_srqc_bits {
3789         u8         state[0x4];
3790         u8         log_srq_size[0x4];
3791         u8         reserved_at_8[0x18];
3792
3793         u8         wq_signature[0x1];
3794         u8         cont_srq[0x1];
3795         u8         reserved_at_22[0x1];
3796         u8         rlky[0x1];
3797         u8         reserved_at_24[0x1];
3798         u8         log_rq_stride[0x3];
3799         u8         xrcd[0x18];
3800
3801         u8         page_offset[0x6];
3802         u8         reserved_at_46[0x2];
3803         u8         cqn[0x18];
3804
3805         u8         reserved_at_60[0x20];
3806
3807         u8         reserved_at_80[0x2];
3808         u8         log_page_size[0x6];
3809         u8         reserved_at_88[0x18];
3810
3811         u8         reserved_at_a0[0x20];
3812
3813         u8         reserved_at_c0[0x8];
3814         u8         pd[0x18];
3815
3816         u8         lwm[0x10];
3817         u8         wqe_cnt[0x10];
3818
3819         u8         reserved_at_100[0x40];
3820
3821         u8         dbr_addr[0x40];
3822
3823         u8         reserved_at_180[0x80];
3824 };
3825
3826 enum {
3827         MLX5_SQC_STATE_RST  = 0x0,
3828         MLX5_SQC_STATE_RDY  = 0x1,
3829         MLX5_SQC_STATE_ERR  = 0x3,
3830 };
3831
3832 struct mlx5_ifc_sqc_bits {
3833         u8         rlky[0x1];
3834         u8         cd_master[0x1];
3835         u8         fre[0x1];
3836         u8         flush_in_error_en[0x1];
3837         u8         allow_multi_pkt_send_wqe[0x1];
3838         u8         min_wqe_inline_mode[0x3];
3839         u8         state[0x4];
3840         u8         reg_umr[0x1];
3841         u8         allow_swp[0x1];
3842         u8         hairpin[0x1];
3843         u8         reserved_at_f[0xb];
3844         u8         ts_format[0x2];
3845         u8         reserved_at_1c[0x4];
3846
3847         u8         reserved_at_20[0x8];
3848         u8         user_index[0x18];
3849
3850         u8         reserved_at_40[0x8];
3851         u8         cqn[0x18];
3852
3853         u8         reserved_at_60[0x8];
3854         u8         hairpin_peer_rq[0x18];
3855
3856         u8         reserved_at_80[0x10];
3857         u8         hairpin_peer_vhca[0x10];
3858
3859         u8         reserved_at_a0[0x20];
3860
3861         u8         reserved_at_c0[0x8];
3862         u8         ts_cqe_to_dest_cqn[0x18];
3863
3864         u8         reserved_at_e0[0x10];
3865         u8         packet_pacing_rate_limit_index[0x10];
3866         u8         tis_lst_sz[0x10];
3867         u8         qos_queue_group_id[0x10];
3868
3869         u8         reserved_at_120[0x40];
3870
3871         u8         reserved_at_160[0x8];
3872         u8         tis_num_0[0x18];
3873
3874         struct mlx5_ifc_wq_bits wq;
3875 };
3876
3877 enum {
3878         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3879         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3880         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3881         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3882         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3883 };
3884
3885 enum {
3886         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3887         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3888         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3889         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3890 };
3891
3892 struct mlx5_ifc_scheduling_context_bits {
3893         u8         element_type[0x8];
3894         u8         reserved_at_8[0x18];
3895
3896         u8         element_attributes[0x20];
3897
3898         u8         parent_element_id[0x20];
3899
3900         u8         reserved_at_60[0x40];
3901
3902         u8         bw_share[0x20];
3903
3904         u8         max_average_bw[0x20];
3905
3906         u8         reserved_at_e0[0x120];
3907 };
3908
3909 struct mlx5_ifc_rqtc_bits {
3910         u8    reserved_at_0[0xa0];
3911
3912         u8    reserved_at_a0[0x5];
3913         u8    list_q_type[0x3];
3914         u8    reserved_at_a8[0x8];
3915         u8    rqt_max_size[0x10];
3916
3917         u8    rq_vhca_id_format[0x1];
3918         u8    reserved_at_c1[0xf];
3919         u8    rqt_actual_size[0x10];
3920
3921         u8    reserved_at_e0[0x6a0];
3922
3923         union {
3924                 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
3925                 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
3926         };
3927 };
3928
3929 enum {
3930         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3931         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3932 };
3933
3934 enum {
3935         MLX5_RQC_STATE_RST  = 0x0,
3936         MLX5_RQC_STATE_RDY  = 0x1,
3937         MLX5_RQC_STATE_ERR  = 0x3,
3938 };
3939
3940 enum {
3941         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3942         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3943         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3944 };
3945
3946 enum {
3947         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3948         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3949         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3950 };
3951
3952 struct mlx5_ifc_rqc_bits {
3953         u8         rlky[0x1];
3954         u8         delay_drop_en[0x1];
3955         u8         scatter_fcs[0x1];
3956         u8         vsd[0x1];
3957         u8         mem_rq_type[0x4];
3958         u8         state[0x4];
3959         u8         reserved_at_c[0x1];
3960         u8         flush_in_error_en[0x1];
3961         u8         hairpin[0x1];
3962         u8         reserved_at_f[0xb];
3963         u8         ts_format[0x2];
3964         u8         reserved_at_1c[0x4];
3965
3966         u8         reserved_at_20[0x8];
3967         u8         user_index[0x18];
3968
3969         u8         reserved_at_40[0x8];
3970         u8         cqn[0x18];
3971
3972         u8         counter_set_id[0x8];
3973         u8         reserved_at_68[0x18];
3974
3975         u8         reserved_at_80[0x8];
3976         u8         rmpn[0x18];
3977
3978         u8         reserved_at_a0[0x8];
3979         u8         hairpin_peer_sq[0x18];
3980
3981         u8         reserved_at_c0[0x10];
3982         u8         hairpin_peer_vhca[0x10];
3983
3984         u8         reserved_at_e0[0x46];
3985         u8         shampo_no_match_alignment_granularity[0x2];
3986         u8         reserved_at_128[0x6];
3987         u8         shampo_match_criteria_type[0x2];
3988         u8         reservation_timeout[0x10];
3989
3990         u8         reserved_at_140[0x40];
3991
3992         struct mlx5_ifc_wq_bits wq;
3993 };
3994
3995 enum {
3996         MLX5_RMPC_STATE_RDY  = 0x1,
3997         MLX5_RMPC_STATE_ERR  = 0x3,
3998 };
3999
4000 struct mlx5_ifc_rmpc_bits {
4001         u8         reserved_at_0[0x8];
4002         u8         state[0x4];
4003         u8         reserved_at_c[0x14];
4004
4005         u8         basic_cyclic_rcv_wqe[0x1];
4006         u8         reserved_at_21[0x1f];
4007
4008         u8         reserved_at_40[0x140];
4009
4010         struct mlx5_ifc_wq_bits wq;
4011 };
4012
4013 enum {
4014         VHCA_ID_TYPE_HW = 0,
4015         VHCA_ID_TYPE_SW = 1,
4016 };
4017
4018 struct mlx5_ifc_nic_vport_context_bits {
4019         u8         reserved_at_0[0x5];
4020         u8         min_wqe_inline_mode[0x3];
4021         u8         reserved_at_8[0x15];
4022         u8         disable_mc_local_lb[0x1];
4023         u8         disable_uc_local_lb[0x1];
4024         u8         roce_en[0x1];
4025
4026         u8         arm_change_event[0x1];
4027         u8         reserved_at_21[0x1a];
4028         u8         event_on_mtu[0x1];
4029         u8         event_on_promisc_change[0x1];
4030         u8         event_on_vlan_change[0x1];
4031         u8         event_on_mc_address_change[0x1];
4032         u8         event_on_uc_address_change[0x1];
4033
4034         u8         vhca_id_type[0x1];
4035         u8         reserved_at_41[0xb];
4036         u8         affiliation_criteria[0x4];
4037         u8         affiliated_vhca_id[0x10];
4038
4039         u8         reserved_at_60[0xd0];
4040
4041         u8         mtu[0x10];
4042
4043         u8         system_image_guid[0x40];
4044         u8         port_guid[0x40];
4045         u8         node_guid[0x40];
4046
4047         u8         reserved_at_200[0x140];
4048         u8         qkey_violation_counter[0x10];
4049         u8         reserved_at_350[0x430];
4050
4051         u8         promisc_uc[0x1];
4052         u8         promisc_mc[0x1];
4053         u8         promisc_all[0x1];
4054         u8         reserved_at_783[0x2];
4055         u8         allowed_list_type[0x3];
4056         u8         reserved_at_788[0xc];
4057         u8         allowed_list_size[0xc];
4058
4059         struct mlx5_ifc_mac_address_layout_bits permanent_address;
4060
4061         u8         reserved_at_7e0[0x20];
4062
4063         u8         current_uc_mac_address[][0x40];
4064 };
4065
4066 enum {
4067         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4068         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4069         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4070         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4071         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4072         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4073 };
4074
4075 struct mlx5_ifc_mkc_bits {
4076         u8         reserved_at_0[0x1];
4077         u8         free[0x1];
4078         u8         reserved_at_2[0x1];
4079         u8         access_mode_4_2[0x3];
4080         u8         reserved_at_6[0x7];
4081         u8         relaxed_ordering_write[0x1];
4082         u8         reserved_at_e[0x1];
4083         u8         small_fence_on_rdma_read_response[0x1];
4084         u8         umr_en[0x1];
4085         u8         a[0x1];
4086         u8         rw[0x1];
4087         u8         rr[0x1];
4088         u8         lw[0x1];
4089         u8         lr[0x1];
4090         u8         access_mode_1_0[0x2];
4091         u8         reserved_at_18[0x2];
4092         u8         ma_translation_mode[0x2];
4093         u8         reserved_at_1c[0x4];
4094
4095         u8         qpn[0x18];
4096         u8         mkey_7_0[0x8];
4097
4098         u8         reserved_at_40[0x20];
4099
4100         u8         length64[0x1];
4101         u8         bsf_en[0x1];
4102         u8         sync_umr[0x1];
4103         u8         reserved_at_63[0x2];
4104         u8         expected_sigerr_count[0x1];
4105         u8         reserved_at_66[0x1];
4106         u8         en_rinval[0x1];
4107         u8         pd[0x18];
4108
4109         u8         start_addr[0x40];
4110
4111         u8         len[0x40];
4112
4113         u8         bsf_octword_size[0x20];
4114
4115         u8         reserved_at_120[0x80];
4116
4117         u8         translations_octword_size[0x20];
4118
4119         u8         reserved_at_1c0[0x19];
4120         u8         relaxed_ordering_read[0x1];
4121         u8         reserved_at_1d9[0x1];
4122         u8         log_page_size[0x5];
4123
4124         u8         reserved_at_1e0[0x20];
4125 };
4126
4127 struct mlx5_ifc_pkey_bits {
4128         u8         reserved_at_0[0x10];
4129         u8         pkey[0x10];
4130 };
4131
4132 struct mlx5_ifc_array128_auto_bits {
4133         u8         array128_auto[16][0x8];
4134 };
4135
4136 struct mlx5_ifc_hca_vport_context_bits {
4137         u8         field_select[0x20];
4138
4139         u8         reserved_at_20[0xe0];
4140
4141         u8         sm_virt_aware[0x1];
4142         u8         has_smi[0x1];
4143         u8         has_raw[0x1];
4144         u8         grh_required[0x1];
4145         u8         reserved_at_104[0xc];
4146         u8         port_physical_state[0x4];
4147         u8         vport_state_policy[0x4];
4148         u8         port_state[0x4];
4149         u8         vport_state[0x4];
4150
4151         u8         reserved_at_120[0x20];
4152
4153         u8         system_image_guid[0x40];
4154
4155         u8         port_guid[0x40];
4156
4157         u8         node_guid[0x40];
4158
4159         u8         cap_mask1[0x20];
4160
4161         u8         cap_mask1_field_select[0x20];
4162
4163         u8         cap_mask2[0x20];
4164
4165         u8         cap_mask2_field_select[0x20];
4166
4167         u8         reserved_at_280[0x80];
4168
4169         u8         lid[0x10];
4170         u8         reserved_at_310[0x4];
4171         u8         init_type_reply[0x4];
4172         u8         lmc[0x3];
4173         u8         subnet_timeout[0x5];
4174
4175         u8         sm_lid[0x10];
4176         u8         sm_sl[0x4];
4177         u8         reserved_at_334[0xc];
4178
4179         u8         qkey_violation_counter[0x10];
4180         u8         pkey_violation_counter[0x10];
4181
4182         u8         reserved_at_360[0xca0];
4183 };
4184
4185 struct mlx5_ifc_esw_vport_context_bits {
4186         u8         fdb_to_vport_reg_c[0x1];
4187         u8         reserved_at_1[0x2];
4188         u8         vport_svlan_strip[0x1];
4189         u8         vport_cvlan_strip[0x1];
4190         u8         vport_svlan_insert[0x1];
4191         u8         vport_cvlan_insert[0x2];
4192         u8         fdb_to_vport_reg_c_id[0x8];
4193         u8         reserved_at_10[0x10];
4194
4195         u8         reserved_at_20[0x20];
4196
4197         u8         svlan_cfi[0x1];
4198         u8         svlan_pcp[0x3];
4199         u8         svlan_id[0xc];
4200         u8         cvlan_cfi[0x1];
4201         u8         cvlan_pcp[0x3];
4202         u8         cvlan_id[0xc];
4203
4204         u8         reserved_at_60[0x720];
4205
4206         u8         sw_steering_vport_icm_address_rx[0x40];
4207
4208         u8         sw_steering_vport_icm_address_tx[0x40];
4209 };
4210
4211 enum {
4212         MLX5_EQC_STATUS_OK                = 0x0,
4213         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4214 };
4215
4216 enum {
4217         MLX5_EQC_ST_ARMED  = 0x9,
4218         MLX5_EQC_ST_FIRED  = 0xa,
4219 };
4220
4221 struct mlx5_ifc_eqc_bits {
4222         u8         status[0x4];
4223         u8         reserved_at_4[0x9];
4224         u8         ec[0x1];
4225         u8         oi[0x1];
4226         u8         reserved_at_f[0x5];
4227         u8         st[0x4];
4228         u8         reserved_at_18[0x8];
4229
4230         u8         reserved_at_20[0x20];
4231
4232         u8         reserved_at_40[0x14];
4233         u8         page_offset[0x6];
4234         u8         reserved_at_5a[0x6];
4235
4236         u8         reserved_at_60[0x3];
4237         u8         log_eq_size[0x5];
4238         u8         uar_page[0x18];
4239
4240         u8         reserved_at_80[0x20];
4241
4242         u8         reserved_at_a0[0x14];
4243         u8         intr[0xc];
4244
4245         u8         reserved_at_c0[0x3];
4246         u8         log_page_size[0x5];
4247         u8         reserved_at_c8[0x18];
4248
4249         u8         reserved_at_e0[0x60];
4250
4251         u8         reserved_at_140[0x8];
4252         u8         consumer_counter[0x18];
4253
4254         u8         reserved_at_160[0x8];
4255         u8         producer_counter[0x18];
4256
4257         u8         reserved_at_180[0x80];
4258 };
4259
4260 enum {
4261         MLX5_DCTC_STATE_ACTIVE    = 0x0,
4262         MLX5_DCTC_STATE_DRAINING  = 0x1,
4263         MLX5_DCTC_STATE_DRAINED   = 0x2,
4264 };
4265
4266 enum {
4267         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4268         MLX5_DCTC_CS_RES_NA         = 0x1,
4269         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4270 };
4271
4272 enum {
4273         MLX5_DCTC_MTU_256_BYTES  = 0x1,
4274         MLX5_DCTC_MTU_512_BYTES  = 0x2,
4275         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4276         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4277         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4278 };
4279
4280 struct mlx5_ifc_dctc_bits {
4281         u8         reserved_at_0[0x4];
4282         u8         state[0x4];
4283         u8         reserved_at_8[0x18];
4284
4285         u8         reserved_at_20[0x8];
4286         u8         user_index[0x18];
4287
4288         u8         reserved_at_40[0x8];
4289         u8         cqn[0x18];
4290
4291         u8         counter_set_id[0x8];
4292         u8         atomic_mode[0x4];
4293         u8         rre[0x1];
4294         u8         rwe[0x1];
4295         u8         rae[0x1];
4296         u8         atomic_like_write_en[0x1];
4297         u8         latency_sensitive[0x1];
4298         u8         rlky[0x1];
4299         u8         free_ar[0x1];
4300         u8         reserved_at_73[0xd];
4301
4302         u8         reserved_at_80[0x8];
4303         u8         cs_res[0x8];
4304         u8         reserved_at_90[0x3];
4305         u8         min_rnr_nak[0x5];
4306         u8         reserved_at_98[0x8];
4307
4308         u8         reserved_at_a0[0x8];
4309         u8         srqn_xrqn[0x18];
4310
4311         u8         reserved_at_c0[0x8];
4312         u8         pd[0x18];
4313
4314         u8         tclass[0x8];
4315         u8         reserved_at_e8[0x4];
4316         u8         flow_label[0x14];
4317
4318         u8         dc_access_key[0x40];
4319
4320         u8         reserved_at_140[0x5];
4321         u8         mtu[0x3];
4322         u8         port[0x8];
4323         u8         pkey_index[0x10];
4324
4325         u8         reserved_at_160[0x8];
4326         u8         my_addr_index[0x8];
4327         u8         reserved_at_170[0x8];
4328         u8         hop_limit[0x8];
4329
4330         u8         dc_access_key_violation_count[0x20];
4331
4332         u8         reserved_at_1a0[0x14];
4333         u8         dei_cfi[0x1];
4334         u8         eth_prio[0x3];
4335         u8         ecn[0x2];
4336         u8         dscp[0x6];
4337
4338         u8         reserved_at_1c0[0x20];
4339         u8         ece[0x20];
4340 };
4341
4342 enum {
4343         MLX5_CQC_STATUS_OK             = 0x0,
4344         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4345         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4346 };
4347
4348 enum {
4349         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4350         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4351 };
4352
4353 enum {
4354         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4355         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4356         MLX5_CQC_ST_FIRED                                 = 0xa,
4357 };
4358
4359 enum {
4360         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4361         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4362         MLX5_CQ_PERIOD_NUM_MODES
4363 };
4364
4365 struct mlx5_ifc_cqc_bits {
4366         u8         status[0x4];
4367         u8         reserved_at_4[0x2];
4368         u8         dbr_umem_valid[0x1];
4369         u8         apu_cq[0x1];
4370         u8         cqe_sz[0x3];
4371         u8         cc[0x1];
4372         u8         reserved_at_c[0x1];
4373         u8         scqe_break_moderation_en[0x1];
4374         u8         oi[0x1];
4375         u8         cq_period_mode[0x2];
4376         u8         cqe_comp_en[0x1];
4377         u8         mini_cqe_res_format[0x2];
4378         u8         st[0x4];
4379         u8         reserved_at_18[0x6];
4380         u8         cqe_compression_layout[0x2];
4381
4382         u8         reserved_at_20[0x20];
4383
4384         u8         reserved_at_40[0x14];
4385         u8         page_offset[0x6];
4386         u8         reserved_at_5a[0x6];
4387
4388         u8         reserved_at_60[0x3];
4389         u8         log_cq_size[0x5];
4390         u8         uar_page[0x18];
4391
4392         u8         reserved_at_80[0x4];
4393         u8         cq_period[0xc];
4394         u8         cq_max_count[0x10];
4395
4396         u8         c_eqn_or_apu_element[0x20];
4397
4398         u8         reserved_at_c0[0x3];
4399         u8         log_page_size[0x5];
4400         u8         reserved_at_c8[0x18];
4401
4402         u8         reserved_at_e0[0x20];
4403
4404         u8         reserved_at_100[0x8];
4405         u8         last_notified_index[0x18];
4406
4407         u8         reserved_at_120[0x8];
4408         u8         last_solicit_index[0x18];
4409
4410         u8         reserved_at_140[0x8];
4411         u8         consumer_counter[0x18];
4412
4413         u8         reserved_at_160[0x8];
4414         u8         producer_counter[0x18];
4415
4416         u8         reserved_at_180[0x40];
4417
4418         u8         dbr_addr[0x40];
4419 };
4420
4421 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4422         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4423         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4424         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4425         struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4426         u8         reserved_at_0[0x800];
4427 };
4428
4429 struct mlx5_ifc_query_adapter_param_block_bits {
4430         u8         reserved_at_0[0xc0];
4431
4432         u8         reserved_at_c0[0x8];
4433         u8         ieee_vendor_id[0x18];
4434
4435         u8         reserved_at_e0[0x10];
4436         u8         vsd_vendor_id[0x10];
4437
4438         u8         vsd[208][0x8];
4439
4440         u8         vsd_contd_psid[16][0x8];
4441 };
4442
4443 enum {
4444         MLX5_XRQC_STATE_GOOD   = 0x0,
4445         MLX5_XRQC_STATE_ERROR  = 0x1,
4446 };
4447
4448 enum {
4449         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4450         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4451 };
4452
4453 enum {
4454         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4455 };
4456
4457 struct mlx5_ifc_tag_matching_topology_context_bits {
4458         u8         log_matching_list_sz[0x4];
4459         u8         reserved_at_4[0xc];
4460         u8         append_next_index[0x10];
4461
4462         u8         sw_phase_cnt[0x10];
4463         u8         hw_phase_cnt[0x10];
4464
4465         u8         reserved_at_40[0x40];
4466 };
4467
4468 struct mlx5_ifc_xrqc_bits {
4469         u8         state[0x4];
4470         u8         rlkey[0x1];
4471         u8         reserved_at_5[0xf];
4472         u8         topology[0x4];
4473         u8         reserved_at_18[0x4];
4474         u8         offload[0x4];
4475
4476         u8         reserved_at_20[0x8];
4477         u8         user_index[0x18];
4478
4479         u8         reserved_at_40[0x8];
4480         u8         cqn[0x18];
4481
4482         u8         reserved_at_60[0xa0];
4483
4484         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4485
4486         u8         reserved_at_180[0x280];
4487
4488         struct mlx5_ifc_wq_bits wq;
4489 };
4490
4491 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4492         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4493         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4494         u8         reserved_at_0[0x20];
4495 };
4496
4497 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4498         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4499         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4500         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4501         u8         reserved_at_0[0x20];
4502 };
4503
4504 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4505         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4506         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4507         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4508         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4509         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4510         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4511         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4512         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4513         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4514         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4515         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4516         u8         reserved_at_0[0x7c0];
4517 };
4518
4519 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4520         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4521         u8         reserved_at_0[0x7c0];
4522 };
4523
4524 union mlx5_ifc_event_auto_bits {
4525         struct mlx5_ifc_comp_event_bits comp_event;
4526         struct mlx5_ifc_dct_events_bits dct_events;
4527         struct mlx5_ifc_qp_events_bits qp_events;
4528         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4529         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4530         struct mlx5_ifc_cq_error_bits cq_error;
4531         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4532         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4533         struct mlx5_ifc_gpio_event_bits gpio_event;
4534         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4535         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4536         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4537         u8         reserved_at_0[0xe0];
4538 };
4539
4540 struct mlx5_ifc_health_buffer_bits {
4541         u8         reserved_at_0[0x100];
4542
4543         u8         assert_existptr[0x20];
4544
4545         u8         assert_callra[0x20];
4546
4547         u8         reserved_at_140[0x20];
4548
4549         u8         time[0x20];
4550
4551         u8         fw_version[0x20];
4552
4553         u8         hw_id[0x20];
4554
4555         u8         rfr[0x1];
4556         u8         reserved_at_1c1[0x3];
4557         u8         valid[0x1];
4558         u8         severity[0x3];
4559         u8         reserved_at_1c8[0x18];
4560
4561         u8         irisc_index[0x8];
4562         u8         synd[0x8];
4563         u8         ext_synd[0x10];
4564 };
4565
4566 struct mlx5_ifc_register_loopback_control_bits {
4567         u8         no_lb[0x1];
4568         u8         reserved_at_1[0x7];
4569         u8         port[0x8];
4570         u8         reserved_at_10[0x10];
4571
4572         u8         reserved_at_20[0x60];
4573 };
4574
4575 struct mlx5_ifc_vport_tc_element_bits {
4576         u8         traffic_class[0x4];
4577         u8         reserved_at_4[0xc];
4578         u8         vport_number[0x10];
4579 };
4580
4581 struct mlx5_ifc_vport_element_bits {
4582         u8         reserved_at_0[0x10];
4583         u8         vport_number[0x10];
4584 };
4585
4586 enum {
4587         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4588         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4589         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4590 };
4591
4592 struct mlx5_ifc_tsar_element_bits {
4593         u8         reserved_at_0[0x8];
4594         u8         tsar_type[0x8];
4595         u8         reserved_at_10[0x10];
4596 };
4597
4598 enum {
4599         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4600         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4601 };
4602
4603 struct mlx5_ifc_teardown_hca_out_bits {
4604         u8         status[0x8];
4605         u8         reserved_at_8[0x18];
4606
4607         u8         syndrome[0x20];
4608
4609         u8         reserved_at_40[0x3f];
4610
4611         u8         state[0x1];
4612 };
4613
4614 enum {
4615         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4616         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4617         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4618 };
4619
4620 struct mlx5_ifc_teardown_hca_in_bits {
4621         u8         opcode[0x10];
4622         u8         reserved_at_10[0x10];
4623
4624         u8         reserved_at_20[0x10];
4625         u8         op_mod[0x10];
4626
4627         u8         reserved_at_40[0x10];
4628         u8         profile[0x10];
4629
4630         u8         reserved_at_60[0x20];
4631 };
4632
4633 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4634         u8         status[0x8];
4635         u8         reserved_at_8[0x18];
4636
4637         u8         syndrome[0x20];
4638
4639         u8         reserved_at_40[0x40];
4640 };
4641
4642 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4643         u8         opcode[0x10];
4644         u8         uid[0x10];
4645
4646         u8         reserved_at_20[0x10];
4647         u8         op_mod[0x10];
4648
4649         u8         reserved_at_40[0x8];
4650         u8         qpn[0x18];
4651
4652         u8         reserved_at_60[0x20];
4653
4654         u8         opt_param_mask[0x20];
4655
4656         u8         reserved_at_a0[0x20];
4657
4658         struct mlx5_ifc_qpc_bits qpc;
4659
4660         u8         reserved_at_800[0x80];
4661 };
4662
4663 struct mlx5_ifc_sqd2rts_qp_out_bits {
4664         u8         status[0x8];
4665         u8         reserved_at_8[0x18];
4666
4667         u8         syndrome[0x20];
4668
4669         u8         reserved_at_40[0x40];
4670 };
4671
4672 struct mlx5_ifc_sqd2rts_qp_in_bits {
4673         u8         opcode[0x10];
4674         u8         uid[0x10];
4675
4676         u8         reserved_at_20[0x10];
4677         u8         op_mod[0x10];
4678
4679         u8         reserved_at_40[0x8];
4680         u8         qpn[0x18];
4681
4682         u8         reserved_at_60[0x20];
4683
4684         u8         opt_param_mask[0x20];
4685
4686         u8         reserved_at_a0[0x20];
4687
4688         struct mlx5_ifc_qpc_bits qpc;
4689
4690         u8         reserved_at_800[0x80];
4691 };
4692
4693 struct mlx5_ifc_set_roce_address_out_bits {
4694         u8         status[0x8];
4695         u8         reserved_at_8[0x18];
4696
4697         u8         syndrome[0x20];
4698
4699         u8         reserved_at_40[0x40];
4700 };
4701
4702 struct mlx5_ifc_set_roce_address_in_bits {
4703         u8         opcode[0x10];
4704         u8         reserved_at_10[0x10];
4705
4706         u8         reserved_at_20[0x10];
4707         u8         op_mod[0x10];
4708
4709         u8         roce_address_index[0x10];
4710         u8         reserved_at_50[0xc];
4711         u8         vhca_port_num[0x4];
4712
4713         u8         reserved_at_60[0x20];
4714
4715         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4716 };
4717
4718 struct mlx5_ifc_set_mad_demux_out_bits {
4719         u8         status[0x8];
4720         u8         reserved_at_8[0x18];
4721
4722         u8         syndrome[0x20];
4723
4724         u8         reserved_at_40[0x40];
4725 };
4726
4727 enum {
4728         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4729         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4730 };
4731
4732 struct mlx5_ifc_set_mad_demux_in_bits {
4733         u8         opcode[0x10];
4734         u8         reserved_at_10[0x10];
4735
4736         u8         reserved_at_20[0x10];
4737         u8         op_mod[0x10];
4738
4739         u8         reserved_at_40[0x20];
4740
4741         u8         reserved_at_60[0x6];
4742         u8         demux_mode[0x2];
4743         u8         reserved_at_68[0x18];
4744 };
4745
4746 struct mlx5_ifc_set_l2_table_entry_out_bits {
4747         u8         status[0x8];
4748         u8         reserved_at_8[0x18];
4749
4750         u8         syndrome[0x20];
4751
4752         u8         reserved_at_40[0x40];
4753 };
4754
4755 struct mlx5_ifc_set_l2_table_entry_in_bits {
4756         u8         opcode[0x10];
4757         u8         reserved_at_10[0x10];
4758
4759         u8         reserved_at_20[0x10];
4760         u8         op_mod[0x10];
4761
4762         u8         reserved_at_40[0x60];
4763
4764         u8         reserved_at_a0[0x8];
4765         u8         table_index[0x18];
4766
4767         u8         reserved_at_c0[0x20];
4768
4769         u8         reserved_at_e0[0x10];
4770         u8         silent_mode_valid[0x1];
4771         u8         silent_mode[0x1];
4772         u8         reserved_at_f2[0x1];
4773         u8         vlan_valid[0x1];
4774         u8         vlan[0xc];
4775
4776         struct mlx5_ifc_mac_address_layout_bits mac_address;
4777
4778         u8         reserved_at_140[0xc0];
4779 };
4780
4781 struct mlx5_ifc_set_issi_out_bits {
4782         u8         status[0x8];
4783         u8         reserved_at_8[0x18];
4784
4785         u8         syndrome[0x20];
4786
4787         u8         reserved_at_40[0x40];
4788 };
4789
4790 struct mlx5_ifc_set_issi_in_bits {
4791         u8         opcode[0x10];
4792         u8         reserved_at_10[0x10];
4793
4794         u8         reserved_at_20[0x10];
4795         u8         op_mod[0x10];
4796
4797         u8         reserved_at_40[0x10];
4798         u8         current_issi[0x10];
4799
4800         u8         reserved_at_60[0x20];
4801 };
4802
4803 struct mlx5_ifc_set_hca_cap_out_bits {
4804         u8         status[0x8];
4805         u8         reserved_at_8[0x18];
4806
4807         u8         syndrome[0x20];
4808
4809         u8         reserved_at_40[0x40];
4810 };
4811
4812 struct mlx5_ifc_set_hca_cap_in_bits {
4813         u8         opcode[0x10];
4814         u8         reserved_at_10[0x10];
4815
4816         u8         reserved_at_20[0x10];
4817         u8         op_mod[0x10];
4818
4819         u8         other_function[0x1];
4820         u8         ec_vf_function[0x1];
4821         u8         reserved_at_42[0xe];
4822         u8         function_id[0x10];
4823
4824         u8         reserved_at_60[0x20];
4825
4826         union mlx5_ifc_hca_cap_union_bits capability;
4827 };
4828
4829 enum {
4830         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4831         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4832         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4833         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4834         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4835 };
4836
4837 struct mlx5_ifc_set_fte_out_bits {
4838         u8         status[0x8];
4839         u8         reserved_at_8[0x18];
4840
4841         u8         syndrome[0x20];
4842
4843         u8         reserved_at_40[0x40];
4844 };
4845
4846 struct mlx5_ifc_set_fte_in_bits {
4847         u8         opcode[0x10];
4848         u8         reserved_at_10[0x10];
4849
4850         u8         reserved_at_20[0x10];
4851         u8         op_mod[0x10];
4852
4853         u8         other_vport[0x1];
4854         u8         reserved_at_41[0xf];
4855         u8         vport_number[0x10];
4856
4857         u8         reserved_at_60[0x20];
4858
4859         u8         table_type[0x8];
4860         u8         reserved_at_88[0x18];
4861
4862         u8         reserved_at_a0[0x8];
4863         u8         table_id[0x18];
4864
4865         u8         ignore_flow_level[0x1];
4866         u8         reserved_at_c1[0x17];
4867         u8         modify_enable_mask[0x8];
4868
4869         u8         reserved_at_e0[0x20];
4870
4871         u8         flow_index[0x20];
4872
4873         u8         reserved_at_120[0xe0];
4874
4875         struct mlx5_ifc_flow_context_bits flow_context;
4876 };
4877
4878 struct mlx5_ifc_rts2rts_qp_out_bits {
4879         u8         status[0x8];
4880         u8         reserved_at_8[0x18];
4881
4882         u8         syndrome[0x20];
4883
4884         u8         reserved_at_40[0x20];
4885         u8         ece[0x20];
4886 };
4887
4888 struct mlx5_ifc_rts2rts_qp_in_bits {
4889         u8         opcode[0x10];
4890         u8         uid[0x10];
4891
4892         u8         reserved_at_20[0x10];
4893         u8         op_mod[0x10];
4894
4895         u8         reserved_at_40[0x8];
4896         u8         qpn[0x18];
4897
4898         u8         reserved_at_60[0x20];
4899
4900         u8         opt_param_mask[0x20];
4901
4902         u8         ece[0x20];
4903
4904         struct mlx5_ifc_qpc_bits qpc;
4905
4906         u8         reserved_at_800[0x80];
4907 };
4908
4909 struct mlx5_ifc_rtr2rts_qp_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_at_8[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_at_40[0x20];
4916         u8         ece[0x20];
4917 };
4918
4919 struct mlx5_ifc_rtr2rts_qp_in_bits {
4920         u8         opcode[0x10];
4921         u8         uid[0x10];
4922
4923         u8         reserved_at_20[0x10];
4924         u8         op_mod[0x10];
4925
4926         u8         reserved_at_40[0x8];
4927         u8         qpn[0x18];
4928
4929         u8         reserved_at_60[0x20];
4930
4931         u8         opt_param_mask[0x20];
4932
4933         u8         ece[0x20];
4934
4935         struct mlx5_ifc_qpc_bits qpc;
4936
4937         u8         reserved_at_800[0x80];
4938 };
4939
4940 struct mlx5_ifc_rst2init_qp_out_bits {
4941         u8         status[0x8];
4942         u8         reserved_at_8[0x18];
4943
4944         u8         syndrome[0x20];
4945
4946         u8         reserved_at_40[0x20];
4947         u8         ece[0x20];
4948 };
4949
4950 struct mlx5_ifc_rst2init_qp_in_bits {
4951         u8         opcode[0x10];
4952         u8         uid[0x10];
4953
4954         u8         reserved_at_20[0x10];
4955         u8         op_mod[0x10];
4956
4957         u8         reserved_at_40[0x8];
4958         u8         qpn[0x18];
4959
4960         u8         reserved_at_60[0x20];
4961
4962         u8         opt_param_mask[0x20];
4963
4964         u8         ece[0x20];
4965
4966         struct mlx5_ifc_qpc_bits qpc;
4967
4968         u8         reserved_at_800[0x80];
4969 };
4970
4971 struct mlx5_ifc_query_xrq_out_bits {
4972         u8         status[0x8];
4973         u8         reserved_at_8[0x18];
4974
4975         u8         syndrome[0x20];
4976
4977         u8         reserved_at_40[0x40];
4978
4979         struct mlx5_ifc_xrqc_bits xrq_context;
4980 };
4981
4982 struct mlx5_ifc_query_xrq_in_bits {
4983         u8         opcode[0x10];
4984         u8         reserved_at_10[0x10];
4985
4986         u8         reserved_at_20[0x10];
4987         u8         op_mod[0x10];
4988
4989         u8         reserved_at_40[0x8];
4990         u8         xrqn[0x18];
4991
4992         u8         reserved_at_60[0x20];
4993 };
4994
4995 struct mlx5_ifc_query_xrc_srq_out_bits {
4996         u8         status[0x8];
4997         u8         reserved_at_8[0x18];
4998
4999         u8         syndrome[0x20];
5000
5001         u8         reserved_at_40[0x40];
5002
5003         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5004
5005         u8         reserved_at_280[0x600];
5006
5007         u8         pas[][0x40];
5008 };
5009
5010 struct mlx5_ifc_query_xrc_srq_in_bits {
5011         u8         opcode[0x10];
5012         u8         reserved_at_10[0x10];
5013
5014         u8         reserved_at_20[0x10];
5015         u8         op_mod[0x10];
5016
5017         u8         reserved_at_40[0x8];
5018         u8         xrc_srqn[0x18];
5019
5020         u8         reserved_at_60[0x20];
5021 };
5022
5023 enum {
5024         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5025         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5026 };
5027
5028 struct mlx5_ifc_query_vport_state_out_bits {
5029         u8         status[0x8];
5030         u8         reserved_at_8[0x18];
5031
5032         u8         syndrome[0x20];
5033
5034         u8         reserved_at_40[0x20];
5035
5036         u8         reserved_at_60[0x18];
5037         u8         admin_state[0x4];
5038         u8         state[0x4];
5039 };
5040
5041 enum {
5042         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5043         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5044         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5045 };
5046
5047 struct mlx5_ifc_arm_monitor_counter_in_bits {
5048         u8         opcode[0x10];
5049         u8         uid[0x10];
5050
5051         u8         reserved_at_20[0x10];
5052         u8         op_mod[0x10];
5053
5054         u8         reserved_at_40[0x20];
5055
5056         u8         reserved_at_60[0x20];
5057 };
5058
5059 struct mlx5_ifc_arm_monitor_counter_out_bits {
5060         u8         status[0x8];
5061         u8         reserved_at_8[0x18];
5062
5063         u8         syndrome[0x20];
5064
5065         u8         reserved_at_40[0x40];
5066 };
5067
5068 enum {
5069         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5070         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5071 };
5072
5073 enum mlx5_monitor_counter_ppcnt {
5074         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5075         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5076         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5077         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5078         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5079         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5080 };
5081
5082 enum {
5083         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5084 };
5085
5086 struct mlx5_ifc_monitor_counter_output_bits {
5087         u8         reserved_at_0[0x4];
5088         u8         type[0x4];
5089         u8         reserved_at_8[0x8];
5090         u8         counter[0x10];
5091
5092         u8         counter_group_id[0x20];
5093 };
5094
5095 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5096 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5097 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5098                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5099
5100 struct mlx5_ifc_set_monitor_counter_in_bits {
5101         u8         opcode[0x10];
5102         u8         uid[0x10];
5103
5104         u8         reserved_at_20[0x10];
5105         u8         op_mod[0x10];
5106
5107         u8         reserved_at_40[0x10];
5108         u8         num_of_counters[0x10];
5109
5110         u8         reserved_at_60[0x20];
5111
5112         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5113 };
5114
5115 struct mlx5_ifc_set_monitor_counter_out_bits {
5116         u8         status[0x8];
5117         u8         reserved_at_8[0x18];
5118
5119         u8         syndrome[0x20];
5120
5121         u8         reserved_at_40[0x40];
5122 };
5123
5124 struct mlx5_ifc_query_vport_state_in_bits {
5125         u8         opcode[0x10];
5126         u8         reserved_at_10[0x10];
5127
5128         u8         reserved_at_20[0x10];
5129         u8         op_mod[0x10];
5130
5131         u8         other_vport[0x1];
5132         u8         reserved_at_41[0xf];
5133         u8         vport_number[0x10];
5134
5135         u8         reserved_at_60[0x20];
5136 };
5137
5138 struct mlx5_ifc_query_vnic_env_out_bits {
5139         u8         status[0x8];
5140         u8         reserved_at_8[0x18];
5141
5142         u8         syndrome[0x20];
5143
5144         u8         reserved_at_40[0x40];
5145
5146         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5147 };
5148
5149 enum {
5150         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5151 };
5152
5153 struct mlx5_ifc_query_vnic_env_in_bits {
5154         u8         opcode[0x10];
5155         u8         reserved_at_10[0x10];
5156
5157         u8         reserved_at_20[0x10];
5158         u8         op_mod[0x10];
5159
5160         u8         other_vport[0x1];
5161         u8         reserved_at_41[0xf];
5162         u8         vport_number[0x10];
5163
5164         u8         reserved_at_60[0x20];
5165 };
5166
5167 struct mlx5_ifc_query_vport_counter_out_bits {
5168         u8         status[0x8];
5169         u8         reserved_at_8[0x18];
5170
5171         u8         syndrome[0x20];
5172
5173         u8         reserved_at_40[0x40];
5174
5175         struct mlx5_ifc_traffic_counter_bits received_errors;
5176
5177         struct mlx5_ifc_traffic_counter_bits transmit_errors;
5178
5179         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5180
5181         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5182
5183         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5184
5185         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5186
5187         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5188
5189         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5190
5191         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5192
5193         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5194
5195         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5196
5197         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5198
5199         struct mlx5_ifc_traffic_counter_bits local_loopback;
5200
5201         u8         reserved_at_700[0x980];
5202 };
5203
5204 enum {
5205         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5206 };
5207
5208 struct mlx5_ifc_query_vport_counter_in_bits {
5209         u8         opcode[0x10];
5210         u8         reserved_at_10[0x10];
5211
5212         u8         reserved_at_20[0x10];
5213         u8         op_mod[0x10];
5214
5215         u8         other_vport[0x1];
5216         u8         reserved_at_41[0xb];
5217         u8         port_num[0x4];
5218         u8         vport_number[0x10];
5219
5220         u8         reserved_at_60[0x60];
5221
5222         u8         clear[0x1];
5223         u8         reserved_at_c1[0x1f];
5224
5225         u8         reserved_at_e0[0x20];
5226 };
5227
5228 struct mlx5_ifc_query_tis_out_bits {
5229         u8         status[0x8];
5230         u8         reserved_at_8[0x18];
5231
5232         u8         syndrome[0x20];
5233
5234         u8         reserved_at_40[0x40];
5235
5236         struct mlx5_ifc_tisc_bits tis_context;
5237 };
5238
5239 struct mlx5_ifc_query_tis_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x8];
5247         u8         tisn[0x18];
5248
5249         u8         reserved_at_60[0x20];
5250 };
5251
5252 struct mlx5_ifc_query_tir_out_bits {
5253         u8         status[0x8];
5254         u8         reserved_at_8[0x18];
5255
5256         u8         syndrome[0x20];
5257
5258         u8         reserved_at_40[0xc0];
5259
5260         struct mlx5_ifc_tirc_bits tir_context;
5261 };
5262
5263 struct mlx5_ifc_query_tir_in_bits {
5264         u8         opcode[0x10];
5265         u8         reserved_at_10[0x10];
5266
5267         u8         reserved_at_20[0x10];
5268         u8         op_mod[0x10];
5269
5270         u8         reserved_at_40[0x8];
5271         u8         tirn[0x18];
5272
5273         u8         reserved_at_60[0x20];
5274 };
5275
5276 struct mlx5_ifc_query_srq_out_bits {
5277         u8         status[0x8];
5278         u8         reserved_at_8[0x18];
5279
5280         u8         syndrome[0x20];
5281
5282         u8         reserved_at_40[0x40];
5283
5284         struct mlx5_ifc_srqc_bits srq_context_entry;
5285
5286         u8         reserved_at_280[0x600];
5287
5288         u8         pas[][0x40];
5289 };
5290
5291 struct mlx5_ifc_query_srq_in_bits {
5292         u8         opcode[0x10];
5293         u8         reserved_at_10[0x10];
5294
5295         u8         reserved_at_20[0x10];
5296         u8         op_mod[0x10];
5297
5298         u8         reserved_at_40[0x8];
5299         u8         srqn[0x18];
5300
5301         u8         reserved_at_60[0x20];
5302 };
5303
5304 struct mlx5_ifc_query_sq_out_bits {
5305         u8         status[0x8];
5306         u8         reserved_at_8[0x18];
5307
5308         u8         syndrome[0x20];
5309
5310         u8         reserved_at_40[0xc0];
5311
5312         struct mlx5_ifc_sqc_bits sq_context;
5313 };
5314
5315 struct mlx5_ifc_query_sq_in_bits {
5316         u8         opcode[0x10];
5317         u8         reserved_at_10[0x10];
5318
5319         u8         reserved_at_20[0x10];
5320         u8         op_mod[0x10];
5321
5322         u8         reserved_at_40[0x8];
5323         u8         sqn[0x18];
5324
5325         u8         reserved_at_60[0x20];
5326 };
5327
5328 struct mlx5_ifc_query_special_contexts_out_bits {
5329         u8         status[0x8];
5330         u8         reserved_at_8[0x18];
5331
5332         u8         syndrome[0x20];
5333
5334         u8         dump_fill_mkey[0x20];
5335
5336         u8         resd_lkey[0x20];
5337
5338         u8         null_mkey[0x20];
5339
5340         u8         terminate_scatter_list_mkey[0x20];
5341
5342         u8         repeated_mkey[0x20];
5343
5344         u8         reserved_at_a0[0x20];
5345 };
5346
5347 struct mlx5_ifc_query_special_contexts_in_bits {
5348         u8         opcode[0x10];
5349         u8         reserved_at_10[0x10];
5350
5351         u8         reserved_at_20[0x10];
5352         u8         op_mod[0x10];
5353
5354         u8         reserved_at_40[0x40];
5355 };
5356
5357 struct mlx5_ifc_query_scheduling_element_out_bits {
5358         u8         opcode[0x10];
5359         u8         reserved_at_10[0x10];
5360
5361         u8         reserved_at_20[0x10];
5362         u8         op_mod[0x10];
5363
5364         u8         reserved_at_40[0xc0];
5365
5366         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5367
5368         u8         reserved_at_300[0x100];
5369 };
5370
5371 enum {
5372         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5373         SCHEDULING_HIERARCHY_NIC = 0x3,
5374 };
5375
5376 struct mlx5_ifc_query_scheduling_element_in_bits {
5377         u8         opcode[0x10];
5378         u8         reserved_at_10[0x10];
5379
5380         u8         reserved_at_20[0x10];
5381         u8         op_mod[0x10];
5382
5383         u8         scheduling_hierarchy[0x8];
5384         u8         reserved_at_48[0x18];
5385
5386         u8         scheduling_element_id[0x20];
5387
5388         u8         reserved_at_80[0x180];
5389 };
5390
5391 struct mlx5_ifc_query_rqt_out_bits {
5392         u8         status[0x8];
5393         u8         reserved_at_8[0x18];
5394
5395         u8         syndrome[0x20];
5396
5397         u8         reserved_at_40[0xc0];
5398
5399         struct mlx5_ifc_rqtc_bits rqt_context;
5400 };
5401
5402 struct mlx5_ifc_query_rqt_in_bits {
5403         u8         opcode[0x10];
5404         u8         reserved_at_10[0x10];
5405
5406         u8         reserved_at_20[0x10];
5407         u8         op_mod[0x10];
5408
5409         u8         reserved_at_40[0x8];
5410         u8         rqtn[0x18];
5411
5412         u8         reserved_at_60[0x20];
5413 };
5414
5415 struct mlx5_ifc_query_rq_out_bits {
5416         u8         status[0x8];
5417         u8         reserved_at_8[0x18];
5418
5419         u8         syndrome[0x20];
5420
5421         u8         reserved_at_40[0xc0];
5422
5423         struct mlx5_ifc_rqc_bits rq_context;
5424 };
5425
5426 struct mlx5_ifc_query_rq_in_bits {
5427         u8         opcode[0x10];
5428         u8         reserved_at_10[0x10];
5429
5430         u8         reserved_at_20[0x10];
5431         u8         op_mod[0x10];
5432
5433         u8         reserved_at_40[0x8];
5434         u8         rqn[0x18];
5435
5436         u8         reserved_at_60[0x20];
5437 };
5438
5439 struct mlx5_ifc_query_roce_address_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x40];
5446
5447         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5448 };
5449
5450 struct mlx5_ifc_query_roce_address_in_bits {
5451         u8         opcode[0x10];
5452         u8         reserved_at_10[0x10];
5453
5454         u8         reserved_at_20[0x10];
5455         u8         op_mod[0x10];
5456
5457         u8         roce_address_index[0x10];
5458         u8         reserved_at_50[0xc];
5459         u8         vhca_port_num[0x4];
5460
5461         u8         reserved_at_60[0x20];
5462 };
5463
5464 struct mlx5_ifc_query_rmp_out_bits {
5465         u8         status[0x8];
5466         u8         reserved_at_8[0x18];
5467
5468         u8         syndrome[0x20];
5469
5470         u8         reserved_at_40[0xc0];
5471
5472         struct mlx5_ifc_rmpc_bits rmp_context;
5473 };
5474
5475 struct mlx5_ifc_query_rmp_in_bits {
5476         u8         opcode[0x10];
5477         u8         reserved_at_10[0x10];
5478
5479         u8         reserved_at_20[0x10];
5480         u8         op_mod[0x10];
5481
5482         u8         reserved_at_40[0x8];
5483         u8         rmpn[0x18];
5484
5485         u8         reserved_at_60[0x20];
5486 };
5487
5488 struct mlx5_ifc_cqe_error_syndrome_bits {
5489         u8         hw_error_syndrome[0x8];
5490         u8         hw_syndrome_type[0x4];
5491         u8         reserved_at_c[0x4];
5492         u8         vendor_error_syndrome[0x8];
5493         u8         syndrome[0x8];
5494 };
5495
5496 struct mlx5_ifc_qp_context_extension_bits {
5497         u8         reserved_at_0[0x60];
5498
5499         struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5500
5501         u8         reserved_at_80[0x580];
5502 };
5503
5504 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5505         struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5506
5507         u8         pas[0][0x40];
5508 };
5509
5510 struct mlx5_ifc_qp_pas_list_in_bits {
5511         struct mlx5_ifc_cmd_pas_bits pas[0];
5512 };
5513
5514 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5515         struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5516         struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5517 };
5518
5519 struct mlx5_ifc_query_qp_out_bits {
5520         u8         status[0x8];
5521         u8         reserved_at_8[0x18];
5522
5523         u8         syndrome[0x20];
5524
5525         u8         reserved_at_40[0x40];
5526
5527         u8         opt_param_mask[0x20];
5528
5529         u8         ece[0x20];
5530
5531         struct mlx5_ifc_qpc_bits qpc;
5532
5533         u8         reserved_at_800[0x80];
5534
5535         union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5536 };
5537
5538 struct mlx5_ifc_query_qp_in_bits {
5539         u8         opcode[0x10];
5540         u8         reserved_at_10[0x10];
5541
5542         u8         reserved_at_20[0x10];
5543         u8         op_mod[0x10];
5544
5545         u8         qpc_ext[0x1];
5546         u8         reserved_at_41[0x7];
5547         u8         qpn[0x18];
5548
5549         u8         reserved_at_60[0x20];
5550 };
5551
5552 struct mlx5_ifc_query_q_counter_out_bits {
5553         u8         status[0x8];
5554         u8         reserved_at_8[0x18];
5555
5556         u8         syndrome[0x20];
5557
5558         u8         reserved_at_40[0x40];
5559
5560         u8         rx_write_requests[0x20];
5561
5562         u8         reserved_at_a0[0x20];
5563
5564         u8         rx_read_requests[0x20];
5565
5566         u8         reserved_at_e0[0x20];
5567
5568         u8         rx_atomic_requests[0x20];
5569
5570         u8         reserved_at_120[0x20];
5571
5572         u8         rx_dct_connect[0x20];
5573
5574         u8         reserved_at_160[0x20];
5575
5576         u8         out_of_buffer[0x20];
5577
5578         u8         reserved_at_1a0[0x20];
5579
5580         u8         out_of_sequence[0x20];
5581
5582         u8         reserved_at_1e0[0x20];
5583
5584         u8         duplicate_request[0x20];
5585
5586         u8         reserved_at_220[0x20];
5587
5588         u8         rnr_nak_retry_err[0x20];
5589
5590         u8         reserved_at_260[0x20];
5591
5592         u8         packet_seq_err[0x20];
5593
5594         u8         reserved_at_2a0[0x20];
5595
5596         u8         implied_nak_seq_err[0x20];
5597
5598         u8         reserved_at_2e0[0x20];
5599
5600         u8         local_ack_timeout_err[0x20];
5601
5602         u8         reserved_at_320[0xa0];
5603
5604         u8         resp_local_length_error[0x20];
5605
5606         u8         req_local_length_error[0x20];
5607
5608         u8         resp_local_qp_error[0x20];
5609
5610         u8         local_operation_error[0x20];
5611
5612         u8         resp_local_protection[0x20];
5613
5614         u8         req_local_protection[0x20];
5615
5616         u8         resp_cqe_error[0x20];
5617
5618         u8         req_cqe_error[0x20];
5619
5620         u8         req_mw_binding[0x20];
5621
5622         u8         req_bad_response[0x20];
5623
5624         u8         req_remote_invalid_request[0x20];
5625
5626         u8         resp_remote_invalid_request[0x20];
5627
5628         u8         req_remote_access_errors[0x20];
5629
5630         u8         resp_remote_access_errors[0x20];
5631
5632         u8         req_remote_operation_errors[0x20];
5633
5634         u8         req_transport_retries_exceeded[0x20];
5635
5636         u8         cq_overflow[0x20];
5637
5638         u8         resp_cqe_flush_error[0x20];
5639
5640         u8         req_cqe_flush_error[0x20];
5641
5642         u8         reserved_at_620[0x20];
5643
5644         u8         roce_adp_retrans[0x20];
5645
5646         u8         roce_adp_retrans_to[0x20];
5647
5648         u8         roce_slow_restart[0x20];
5649
5650         u8         roce_slow_restart_cnps[0x20];
5651
5652         u8         roce_slow_restart_trans[0x20];
5653
5654         u8         reserved_at_6e0[0x120];
5655 };
5656
5657 struct mlx5_ifc_query_q_counter_in_bits {
5658         u8         opcode[0x10];
5659         u8         reserved_at_10[0x10];
5660
5661         u8         reserved_at_20[0x10];
5662         u8         op_mod[0x10];
5663
5664         u8         other_vport[0x1];
5665         u8         reserved_at_41[0xf];
5666         u8         vport_number[0x10];
5667
5668         u8         reserved_at_60[0x60];
5669
5670         u8         clear[0x1];
5671         u8         aggregate[0x1];
5672         u8         reserved_at_c2[0x1e];
5673
5674         u8         reserved_at_e0[0x18];
5675         u8         counter_set_id[0x8];
5676 };
5677
5678 struct mlx5_ifc_query_pages_out_bits {
5679         u8         status[0x8];
5680         u8         reserved_at_8[0x18];
5681
5682         u8         syndrome[0x20];
5683
5684         u8         embedded_cpu_function[0x1];
5685         u8         reserved_at_41[0xf];
5686         u8         function_id[0x10];
5687
5688         u8         num_pages[0x20];
5689 };
5690
5691 enum {
5692         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5693         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5694         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5695 };
5696
5697 struct mlx5_ifc_query_pages_in_bits {
5698         u8         opcode[0x10];
5699         u8         reserved_at_10[0x10];
5700
5701         u8         reserved_at_20[0x10];
5702         u8         op_mod[0x10];
5703
5704         u8         embedded_cpu_function[0x1];
5705         u8         reserved_at_41[0xf];
5706         u8         function_id[0x10];
5707
5708         u8         reserved_at_60[0x20];
5709 };
5710
5711 struct mlx5_ifc_query_nic_vport_context_out_bits {
5712         u8         status[0x8];
5713         u8         reserved_at_8[0x18];
5714
5715         u8         syndrome[0x20];
5716
5717         u8         reserved_at_40[0x40];
5718
5719         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5720 };
5721
5722 struct mlx5_ifc_query_nic_vport_context_in_bits {
5723         u8         opcode[0x10];
5724         u8         reserved_at_10[0x10];
5725
5726         u8         reserved_at_20[0x10];
5727         u8         op_mod[0x10];
5728
5729         u8         other_vport[0x1];
5730         u8         reserved_at_41[0xf];
5731         u8         vport_number[0x10];
5732
5733         u8         reserved_at_60[0x5];
5734         u8         allowed_list_type[0x3];
5735         u8         reserved_at_68[0x18];
5736 };
5737
5738 struct mlx5_ifc_query_mkey_out_bits {
5739         u8         status[0x8];
5740         u8         reserved_at_8[0x18];
5741
5742         u8         syndrome[0x20];
5743
5744         u8         reserved_at_40[0x40];
5745
5746         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5747
5748         u8         reserved_at_280[0x600];
5749
5750         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5751
5752         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5753 };
5754
5755 struct mlx5_ifc_query_mkey_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         reserved_at_40[0x8];
5763         u8         mkey_index[0x18];
5764
5765         u8         pg_access[0x1];
5766         u8         reserved_at_61[0x1f];
5767 };
5768
5769 struct mlx5_ifc_query_mad_demux_out_bits {
5770         u8         status[0x8];
5771         u8         reserved_at_8[0x18];
5772
5773         u8         syndrome[0x20];
5774
5775         u8         reserved_at_40[0x40];
5776
5777         u8         mad_dumux_parameters_block[0x20];
5778 };
5779
5780 struct mlx5_ifc_query_mad_demux_in_bits {
5781         u8         opcode[0x10];
5782         u8         reserved_at_10[0x10];
5783
5784         u8         reserved_at_20[0x10];
5785         u8         op_mod[0x10];
5786
5787         u8         reserved_at_40[0x40];
5788 };
5789
5790 struct mlx5_ifc_query_l2_table_entry_out_bits {
5791         u8         status[0x8];
5792         u8         reserved_at_8[0x18];
5793
5794         u8         syndrome[0x20];
5795
5796         u8         reserved_at_40[0xa0];
5797
5798         u8         reserved_at_e0[0x13];
5799         u8         vlan_valid[0x1];
5800         u8         vlan[0xc];
5801
5802         struct mlx5_ifc_mac_address_layout_bits mac_address;
5803
5804         u8         reserved_at_140[0xc0];
5805 };
5806
5807 struct mlx5_ifc_query_l2_table_entry_in_bits {
5808         u8         opcode[0x10];
5809         u8         reserved_at_10[0x10];
5810
5811         u8         reserved_at_20[0x10];
5812         u8         op_mod[0x10];
5813
5814         u8         reserved_at_40[0x60];
5815
5816         u8         reserved_at_a0[0x8];
5817         u8         table_index[0x18];
5818
5819         u8         reserved_at_c0[0x140];
5820 };
5821
5822 struct mlx5_ifc_query_issi_out_bits {
5823         u8         status[0x8];
5824         u8         reserved_at_8[0x18];
5825
5826         u8         syndrome[0x20];
5827
5828         u8         reserved_at_40[0x10];
5829         u8         current_issi[0x10];
5830
5831         u8         reserved_at_60[0xa0];
5832
5833         u8         reserved_at_100[76][0x8];
5834         u8         supported_issi_dw0[0x20];
5835 };
5836
5837 struct mlx5_ifc_query_issi_in_bits {
5838         u8         opcode[0x10];
5839         u8         reserved_at_10[0x10];
5840
5841         u8         reserved_at_20[0x10];
5842         u8         op_mod[0x10];
5843
5844         u8         reserved_at_40[0x40];
5845 };
5846
5847 struct mlx5_ifc_set_driver_version_out_bits {
5848         u8         status[0x8];
5849         u8         reserved_0[0x18];
5850
5851         u8         syndrome[0x20];
5852         u8         reserved_1[0x40];
5853 };
5854
5855 struct mlx5_ifc_set_driver_version_in_bits {
5856         u8         opcode[0x10];
5857         u8         reserved_0[0x10];
5858
5859         u8         reserved_1[0x10];
5860         u8         op_mod[0x10];
5861
5862         u8         reserved_2[0x40];
5863         u8         driver_version[64][0x8];
5864 };
5865
5866 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5867         u8         status[0x8];
5868         u8         reserved_at_8[0x18];
5869
5870         u8         syndrome[0x20];
5871
5872         u8         reserved_at_40[0x40];
5873
5874         struct mlx5_ifc_pkey_bits pkey[];
5875 };
5876
5877 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5878         u8         opcode[0x10];
5879         u8         reserved_at_10[0x10];
5880
5881         u8         reserved_at_20[0x10];
5882         u8         op_mod[0x10];
5883
5884         u8         other_vport[0x1];
5885         u8         reserved_at_41[0xb];
5886         u8         port_num[0x4];
5887         u8         vport_number[0x10];
5888
5889         u8         reserved_at_60[0x10];
5890         u8         pkey_index[0x10];
5891 };
5892
5893 enum {
5894         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5895         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5896         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5897 };
5898
5899 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5900         u8         status[0x8];
5901         u8         reserved_at_8[0x18];
5902
5903         u8         syndrome[0x20];
5904
5905         u8         reserved_at_40[0x20];
5906
5907         u8         gids_num[0x10];
5908         u8         reserved_at_70[0x10];
5909
5910         struct mlx5_ifc_array128_auto_bits gid[];
5911 };
5912
5913 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5914         u8         opcode[0x10];
5915         u8         reserved_at_10[0x10];
5916
5917         u8         reserved_at_20[0x10];
5918         u8         op_mod[0x10];
5919
5920         u8         other_vport[0x1];
5921         u8         reserved_at_41[0xb];
5922         u8         port_num[0x4];
5923         u8         vport_number[0x10];
5924
5925         u8         reserved_at_60[0x10];
5926         u8         gid_index[0x10];
5927 };
5928
5929 struct mlx5_ifc_query_hca_vport_context_out_bits {
5930         u8         status[0x8];
5931         u8         reserved_at_8[0x18];
5932
5933         u8         syndrome[0x20];
5934
5935         u8         reserved_at_40[0x40];
5936
5937         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5938 };
5939
5940 struct mlx5_ifc_query_hca_vport_context_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_at_10[0x10];
5943
5944         u8         reserved_at_20[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         other_vport[0x1];
5948         u8         reserved_at_41[0xb];
5949         u8         port_num[0x4];
5950         u8         vport_number[0x10];
5951
5952         u8         reserved_at_60[0x20];
5953 };
5954
5955 struct mlx5_ifc_query_hca_cap_out_bits {
5956         u8         status[0x8];
5957         u8         reserved_at_8[0x18];
5958
5959         u8         syndrome[0x20];
5960
5961         u8         reserved_at_40[0x40];
5962
5963         union mlx5_ifc_hca_cap_union_bits capability;
5964 };
5965
5966 struct mlx5_ifc_query_hca_cap_in_bits {
5967         u8         opcode[0x10];
5968         u8         reserved_at_10[0x10];
5969
5970         u8         reserved_at_20[0x10];
5971         u8         op_mod[0x10];
5972
5973         u8         other_function[0x1];
5974         u8         ec_vf_function[0x1];
5975         u8         reserved_at_42[0xe];
5976         u8         function_id[0x10];
5977
5978         u8         reserved_at_60[0x20];
5979 };
5980
5981 struct mlx5_ifc_other_hca_cap_bits {
5982         u8         roce[0x1];
5983         u8         reserved_at_1[0x27f];
5984 };
5985
5986 struct mlx5_ifc_query_other_hca_cap_out_bits {
5987         u8         status[0x8];
5988         u8         reserved_at_8[0x18];
5989
5990         u8         syndrome[0x20];
5991
5992         u8         reserved_at_40[0x40];
5993
5994         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5995 };
5996
5997 struct mlx5_ifc_query_other_hca_cap_in_bits {
5998         u8         opcode[0x10];
5999         u8         reserved_at_10[0x10];
6000
6001         u8         reserved_at_20[0x10];
6002         u8         op_mod[0x10];
6003
6004         u8         reserved_at_40[0x10];
6005         u8         function_id[0x10];
6006
6007         u8         reserved_at_60[0x20];
6008 };
6009
6010 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6011         u8         status[0x8];
6012         u8         reserved_at_8[0x18];
6013
6014         u8         syndrome[0x20];
6015
6016         u8         reserved_at_40[0x40];
6017 };
6018
6019 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6020         u8         opcode[0x10];
6021         u8         reserved_at_10[0x10];
6022
6023         u8         reserved_at_20[0x10];
6024         u8         op_mod[0x10];
6025
6026         u8         reserved_at_40[0x10];
6027         u8         function_id[0x10];
6028         u8         field_select[0x20];
6029
6030         struct     mlx5_ifc_other_hca_cap_bits other_capability;
6031 };
6032
6033 struct mlx5_ifc_flow_table_context_bits {
6034         u8         reformat_en[0x1];
6035         u8         decap_en[0x1];
6036         u8         sw_owner[0x1];
6037         u8         termination_table[0x1];
6038         u8         table_miss_action[0x4];
6039         u8         level[0x8];
6040         u8         reserved_at_10[0x8];
6041         u8         log_size[0x8];
6042
6043         u8         reserved_at_20[0x8];
6044         u8         table_miss_id[0x18];
6045
6046         u8         reserved_at_40[0x8];
6047         u8         lag_master_next_table_id[0x18];
6048
6049         u8         reserved_at_60[0x60];
6050
6051         u8         sw_owner_icm_root_1[0x40];
6052
6053         u8         sw_owner_icm_root_0[0x40];
6054
6055 };
6056
6057 struct mlx5_ifc_query_flow_table_out_bits {
6058         u8         status[0x8];
6059         u8         reserved_at_8[0x18];
6060
6061         u8         syndrome[0x20];
6062
6063         u8         reserved_at_40[0x80];
6064
6065         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6066 };
6067
6068 struct mlx5_ifc_query_flow_table_in_bits {
6069         u8         opcode[0x10];
6070         u8         reserved_at_10[0x10];
6071
6072         u8         reserved_at_20[0x10];
6073         u8         op_mod[0x10];
6074
6075         u8         reserved_at_40[0x40];
6076
6077         u8         table_type[0x8];
6078         u8         reserved_at_88[0x18];
6079
6080         u8         reserved_at_a0[0x8];
6081         u8         table_id[0x18];
6082
6083         u8         reserved_at_c0[0x140];
6084 };
6085
6086 struct mlx5_ifc_query_fte_out_bits {
6087         u8         status[0x8];
6088         u8         reserved_at_8[0x18];
6089
6090         u8         syndrome[0x20];
6091
6092         u8         reserved_at_40[0x1c0];
6093
6094         struct mlx5_ifc_flow_context_bits flow_context;
6095 };
6096
6097 struct mlx5_ifc_query_fte_in_bits {
6098         u8         opcode[0x10];
6099         u8         reserved_at_10[0x10];
6100
6101         u8         reserved_at_20[0x10];
6102         u8         op_mod[0x10];
6103
6104         u8         reserved_at_40[0x40];
6105
6106         u8         table_type[0x8];
6107         u8         reserved_at_88[0x18];
6108
6109         u8         reserved_at_a0[0x8];
6110         u8         table_id[0x18];
6111
6112         u8         reserved_at_c0[0x40];
6113
6114         u8         flow_index[0x20];
6115
6116         u8         reserved_at_120[0xe0];
6117 };
6118
6119 struct mlx5_ifc_match_definer_format_0_bits {
6120         u8         reserved_at_0[0x100];
6121
6122         u8         metadata_reg_c_0[0x20];
6123
6124         u8         metadata_reg_c_1[0x20];
6125
6126         u8         outer_dmac_47_16[0x20];
6127
6128         u8         outer_dmac_15_0[0x10];
6129         u8         outer_ethertype[0x10];
6130
6131         u8         reserved_at_180[0x1];
6132         u8         sx_sniffer[0x1];
6133         u8         functional_lb[0x1];
6134         u8         outer_ip_frag[0x1];
6135         u8         outer_qp_type[0x2];
6136         u8         outer_encap_type[0x2];
6137         u8         port_number[0x2];
6138         u8         outer_l3_type[0x2];
6139         u8         outer_l4_type[0x2];
6140         u8         outer_first_vlan_type[0x2];
6141         u8         outer_first_vlan_prio[0x3];
6142         u8         outer_first_vlan_cfi[0x1];
6143         u8         outer_first_vlan_vid[0xc];
6144
6145         u8         outer_l4_type_ext[0x4];
6146         u8         reserved_at_1a4[0x2];
6147         u8         outer_ipsec_layer[0x2];
6148         u8         outer_l2_type[0x2];
6149         u8         force_lb[0x1];
6150         u8         outer_l2_ok[0x1];
6151         u8         outer_l3_ok[0x1];
6152         u8         outer_l4_ok[0x1];
6153         u8         outer_second_vlan_type[0x2];
6154         u8         outer_second_vlan_prio[0x3];
6155         u8         outer_second_vlan_cfi[0x1];
6156         u8         outer_second_vlan_vid[0xc];
6157
6158         u8         outer_smac_47_16[0x20];
6159
6160         u8         outer_smac_15_0[0x10];
6161         u8         inner_ipv4_checksum_ok[0x1];
6162         u8         inner_l4_checksum_ok[0x1];
6163         u8         outer_ipv4_checksum_ok[0x1];
6164         u8         outer_l4_checksum_ok[0x1];
6165         u8         inner_l3_ok[0x1];
6166         u8         inner_l4_ok[0x1];
6167         u8         outer_l3_ok_duplicate[0x1];
6168         u8         outer_l4_ok_duplicate[0x1];
6169         u8         outer_tcp_cwr[0x1];
6170         u8         outer_tcp_ece[0x1];
6171         u8         outer_tcp_urg[0x1];
6172         u8         outer_tcp_ack[0x1];
6173         u8         outer_tcp_psh[0x1];
6174         u8         outer_tcp_rst[0x1];
6175         u8         outer_tcp_syn[0x1];
6176         u8         outer_tcp_fin[0x1];
6177 };
6178
6179 struct mlx5_ifc_match_definer_format_22_bits {
6180         u8         reserved_at_0[0x100];
6181
6182         u8         outer_ip_src_addr[0x20];
6183
6184         u8         outer_ip_dest_addr[0x20];
6185
6186         u8         outer_l4_sport[0x10];
6187         u8         outer_l4_dport[0x10];
6188
6189         u8         reserved_at_160[0x1];
6190         u8         sx_sniffer[0x1];
6191         u8         functional_lb[0x1];
6192         u8         outer_ip_frag[0x1];
6193         u8         outer_qp_type[0x2];
6194         u8         outer_encap_type[0x2];
6195         u8         port_number[0x2];
6196         u8         outer_l3_type[0x2];
6197         u8         outer_l4_type[0x2];
6198         u8         outer_first_vlan_type[0x2];
6199         u8         outer_first_vlan_prio[0x3];
6200         u8         outer_first_vlan_cfi[0x1];
6201         u8         outer_first_vlan_vid[0xc];
6202
6203         u8         metadata_reg_c_0[0x20];
6204
6205         u8         outer_dmac_47_16[0x20];
6206
6207         u8         outer_smac_47_16[0x20];
6208
6209         u8         outer_smac_15_0[0x10];
6210         u8         outer_dmac_15_0[0x10];
6211 };
6212
6213 struct mlx5_ifc_match_definer_format_23_bits {
6214         u8         reserved_at_0[0x100];
6215
6216         u8         inner_ip_src_addr[0x20];
6217
6218         u8         inner_ip_dest_addr[0x20];
6219
6220         u8         inner_l4_sport[0x10];
6221         u8         inner_l4_dport[0x10];
6222
6223         u8         reserved_at_160[0x1];
6224         u8         sx_sniffer[0x1];
6225         u8         functional_lb[0x1];
6226         u8         inner_ip_frag[0x1];
6227         u8         inner_qp_type[0x2];
6228         u8         inner_encap_type[0x2];
6229         u8         port_number[0x2];
6230         u8         inner_l3_type[0x2];
6231         u8         inner_l4_type[0x2];
6232         u8         inner_first_vlan_type[0x2];
6233         u8         inner_first_vlan_prio[0x3];
6234         u8         inner_first_vlan_cfi[0x1];
6235         u8         inner_first_vlan_vid[0xc];
6236
6237         u8         tunnel_header_0[0x20];
6238
6239         u8         inner_dmac_47_16[0x20];
6240
6241         u8         inner_smac_47_16[0x20];
6242
6243         u8         inner_smac_15_0[0x10];
6244         u8         inner_dmac_15_0[0x10];
6245 };
6246
6247 struct mlx5_ifc_match_definer_format_29_bits {
6248         u8         reserved_at_0[0xc0];
6249
6250         u8         outer_ip_dest_addr[0x80];
6251
6252         u8         outer_ip_src_addr[0x80];
6253
6254         u8         outer_l4_sport[0x10];
6255         u8         outer_l4_dport[0x10];
6256
6257         u8         reserved_at_1e0[0x20];
6258 };
6259
6260 struct mlx5_ifc_match_definer_format_30_bits {
6261         u8         reserved_at_0[0xa0];
6262
6263         u8         outer_ip_dest_addr[0x80];
6264
6265         u8         outer_ip_src_addr[0x80];
6266
6267         u8         outer_dmac_47_16[0x20];
6268
6269         u8         outer_smac_47_16[0x20];
6270
6271         u8         outer_smac_15_0[0x10];
6272         u8         outer_dmac_15_0[0x10];
6273 };
6274
6275 struct mlx5_ifc_match_definer_format_31_bits {
6276         u8         reserved_at_0[0xc0];
6277
6278         u8         inner_ip_dest_addr[0x80];
6279
6280         u8         inner_ip_src_addr[0x80];
6281
6282         u8         inner_l4_sport[0x10];
6283         u8         inner_l4_dport[0x10];
6284
6285         u8         reserved_at_1e0[0x20];
6286 };
6287
6288 struct mlx5_ifc_match_definer_format_32_bits {
6289         u8         reserved_at_0[0xa0];
6290
6291         u8         inner_ip_dest_addr[0x80];
6292
6293         u8         inner_ip_src_addr[0x80];
6294
6295         u8         inner_dmac_47_16[0x20];
6296
6297         u8         inner_smac_47_16[0x20];
6298
6299         u8         inner_smac_15_0[0x10];
6300         u8         inner_dmac_15_0[0x10];
6301 };
6302
6303 enum {
6304         MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6305 };
6306
6307 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6308 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6309 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6310 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6311
6312 struct mlx5_ifc_match_definer_match_mask_bits {
6313         u8         reserved_at_1c0[5][0x20];
6314         u8         match_dw_8[0x20];
6315         u8         match_dw_7[0x20];
6316         u8         match_dw_6[0x20];
6317         u8         match_dw_5[0x20];
6318         u8         match_dw_4[0x20];
6319         u8         match_dw_3[0x20];
6320         u8         match_dw_2[0x20];
6321         u8         match_dw_1[0x20];
6322         u8         match_dw_0[0x20];
6323
6324         u8         match_byte_7[0x8];
6325         u8         match_byte_6[0x8];
6326         u8         match_byte_5[0x8];
6327         u8         match_byte_4[0x8];
6328
6329         u8         match_byte_3[0x8];
6330         u8         match_byte_2[0x8];
6331         u8         match_byte_1[0x8];
6332         u8         match_byte_0[0x8];
6333 };
6334
6335 struct mlx5_ifc_match_definer_bits {
6336         u8         modify_field_select[0x40];
6337
6338         u8         reserved_at_40[0x40];
6339
6340         u8         reserved_at_80[0x10];
6341         u8         format_id[0x10];
6342
6343         u8         reserved_at_a0[0x60];
6344
6345         u8         format_select_dw3[0x8];
6346         u8         format_select_dw2[0x8];
6347         u8         format_select_dw1[0x8];
6348         u8         format_select_dw0[0x8];
6349
6350         u8         format_select_dw7[0x8];
6351         u8         format_select_dw6[0x8];
6352         u8         format_select_dw5[0x8];
6353         u8         format_select_dw4[0x8];
6354
6355         u8         reserved_at_100[0x18];
6356         u8         format_select_dw8[0x8];
6357
6358         u8         reserved_at_120[0x20];
6359
6360         u8         format_select_byte3[0x8];
6361         u8         format_select_byte2[0x8];
6362         u8         format_select_byte1[0x8];
6363         u8         format_select_byte0[0x8];
6364
6365         u8         format_select_byte7[0x8];
6366         u8         format_select_byte6[0x8];
6367         u8         format_select_byte5[0x8];
6368         u8         format_select_byte4[0x8];
6369
6370         u8         reserved_at_180[0x40];
6371
6372         union {
6373                 struct {
6374                         u8         match_mask[16][0x20];
6375                 };
6376                 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6377         };
6378 };
6379
6380 struct mlx5_ifc_general_obj_create_param_bits {
6381         u8         alias_object[0x1];
6382         u8         reserved_at_1[0x2];
6383         u8         log_obj_range[0x5];
6384         u8         reserved_at_8[0x18];
6385 };
6386
6387 struct mlx5_ifc_general_obj_query_param_bits {
6388         u8         alias_object[0x1];
6389         u8         obj_offset[0x1f];
6390 };
6391
6392 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6393         u8         opcode[0x10];
6394         u8         uid[0x10];
6395
6396         u8         vhca_tunnel_id[0x10];
6397         u8         obj_type[0x10];
6398
6399         u8         obj_id[0x20];
6400
6401         union {
6402                 struct mlx5_ifc_general_obj_create_param_bits create;
6403                 struct mlx5_ifc_general_obj_query_param_bits query;
6404         } op_param;
6405 };
6406
6407 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6408         u8         status[0x8];
6409         u8         reserved_at_8[0x18];
6410
6411         u8         syndrome[0x20];
6412
6413         u8         obj_id[0x20];
6414
6415         u8         reserved_at_60[0x20];
6416 };
6417
6418 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6419         u8 opcode[0x10];
6420         u8 uid[0x10];
6421         u8 reserved_at_20[0x10];
6422         u8 op_mod[0x10];
6423         u8 reserved_at_40[0x50];
6424         u8 object_type_to_be_accessed[0x10];
6425         u8 object_id_to_be_accessed[0x20];
6426         u8 reserved_at_c0[0x40];
6427         union {
6428                 u8 access_key_raw[0x100];
6429                 u8 access_key[8][0x20];
6430         };
6431 };
6432
6433 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6434         u8 status[0x8];
6435         u8 reserved_at_8[0x18];
6436         u8 syndrome[0x20];
6437         u8 reserved_at_40[0x40];
6438 };
6439
6440 struct mlx5_ifc_modify_header_arg_bits {
6441         u8         reserved_at_0[0x80];
6442
6443         u8         reserved_at_80[0x8];
6444         u8         access_pd[0x18];
6445 };
6446
6447 struct mlx5_ifc_create_modify_header_arg_in_bits {
6448         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6449         struct mlx5_ifc_modify_header_arg_bits arg;
6450 };
6451
6452 struct mlx5_ifc_create_match_definer_in_bits {
6453         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6454
6455         struct mlx5_ifc_match_definer_bits obj_context;
6456 };
6457
6458 struct mlx5_ifc_create_match_definer_out_bits {
6459         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6460 };
6461
6462 struct mlx5_ifc_alias_context_bits {
6463         u8 vhca_id_to_be_accessed[0x10];
6464         u8 reserved_at_10[0xd];
6465         u8 status[0x3];
6466         u8 object_id_to_be_accessed[0x20];
6467         u8 reserved_at_40[0x40];
6468         union {
6469                 u8 access_key_raw[0x100];
6470                 u8 access_key[8][0x20];
6471         };
6472         u8 metadata[0x80];
6473 };
6474
6475 struct mlx5_ifc_create_alias_obj_in_bits {
6476         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6477         struct mlx5_ifc_alias_context_bits alias_ctx;
6478 };
6479
6480 enum {
6481         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6482         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6483         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6484         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6485         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6486         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6487         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6488 };
6489
6490 struct mlx5_ifc_query_flow_group_out_bits {
6491         u8         status[0x8];
6492         u8         reserved_at_8[0x18];
6493
6494         u8         syndrome[0x20];
6495
6496         u8         reserved_at_40[0xa0];
6497
6498         u8         start_flow_index[0x20];
6499
6500         u8         reserved_at_100[0x20];
6501
6502         u8         end_flow_index[0x20];
6503
6504         u8         reserved_at_140[0xa0];
6505
6506         u8         reserved_at_1e0[0x18];
6507         u8         match_criteria_enable[0x8];
6508
6509         struct mlx5_ifc_fte_match_param_bits match_criteria;
6510
6511         u8         reserved_at_1200[0xe00];
6512 };
6513
6514 struct mlx5_ifc_query_flow_group_in_bits {
6515         u8         opcode[0x10];
6516         u8         reserved_at_10[0x10];
6517
6518         u8         reserved_at_20[0x10];
6519         u8         op_mod[0x10];
6520
6521         u8         reserved_at_40[0x40];
6522
6523         u8         table_type[0x8];
6524         u8         reserved_at_88[0x18];
6525
6526         u8         reserved_at_a0[0x8];
6527         u8         table_id[0x18];
6528
6529         u8         group_id[0x20];
6530
6531         u8         reserved_at_e0[0x120];
6532 };
6533
6534 struct mlx5_ifc_query_flow_counter_out_bits {
6535         u8         status[0x8];
6536         u8         reserved_at_8[0x18];
6537
6538         u8         syndrome[0x20];
6539
6540         u8         reserved_at_40[0x40];
6541
6542         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6543 };
6544
6545 struct mlx5_ifc_query_flow_counter_in_bits {
6546         u8         opcode[0x10];
6547         u8         reserved_at_10[0x10];
6548
6549         u8         reserved_at_20[0x10];
6550         u8         op_mod[0x10];
6551
6552         u8         reserved_at_40[0x80];
6553
6554         u8         clear[0x1];
6555         u8         reserved_at_c1[0xf];
6556         u8         num_of_counters[0x10];
6557
6558         u8         flow_counter_id[0x20];
6559 };
6560
6561 struct mlx5_ifc_query_esw_vport_context_out_bits {
6562         u8         status[0x8];
6563         u8         reserved_at_8[0x18];
6564
6565         u8         syndrome[0x20];
6566
6567         u8         reserved_at_40[0x40];
6568
6569         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6570 };
6571
6572 struct mlx5_ifc_query_esw_vport_context_in_bits {
6573         u8         opcode[0x10];
6574         u8         reserved_at_10[0x10];
6575
6576         u8         reserved_at_20[0x10];
6577         u8         op_mod[0x10];
6578
6579         u8         other_vport[0x1];
6580         u8         reserved_at_41[0xf];
6581         u8         vport_number[0x10];
6582
6583         u8         reserved_at_60[0x20];
6584 };
6585
6586 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6587         u8         status[0x8];
6588         u8         reserved_at_8[0x18];
6589
6590         u8         syndrome[0x20];
6591
6592         u8         reserved_at_40[0x40];
6593 };
6594
6595 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6596         u8         reserved_at_0[0x1b];
6597         u8         fdb_to_vport_reg_c_id[0x1];
6598         u8         vport_cvlan_insert[0x1];
6599         u8         vport_svlan_insert[0x1];
6600         u8         vport_cvlan_strip[0x1];
6601         u8         vport_svlan_strip[0x1];
6602 };
6603
6604 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6605         u8         opcode[0x10];
6606         u8         reserved_at_10[0x10];
6607
6608         u8         reserved_at_20[0x10];
6609         u8         op_mod[0x10];
6610
6611         u8         other_vport[0x1];
6612         u8         reserved_at_41[0xf];
6613         u8         vport_number[0x10];
6614
6615         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6616
6617         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6618 };
6619
6620 struct mlx5_ifc_query_eq_out_bits {
6621         u8         status[0x8];
6622         u8         reserved_at_8[0x18];
6623
6624         u8         syndrome[0x20];
6625
6626         u8         reserved_at_40[0x40];
6627
6628         struct mlx5_ifc_eqc_bits eq_context_entry;
6629
6630         u8         reserved_at_280[0x40];
6631
6632         u8         event_bitmask[0x40];
6633
6634         u8         reserved_at_300[0x580];
6635
6636         u8         pas[][0x40];
6637 };
6638
6639 struct mlx5_ifc_query_eq_in_bits {
6640         u8         opcode[0x10];
6641         u8         reserved_at_10[0x10];
6642
6643         u8         reserved_at_20[0x10];
6644         u8         op_mod[0x10];
6645
6646         u8         reserved_at_40[0x18];
6647         u8         eq_number[0x8];
6648
6649         u8         reserved_at_60[0x20];
6650 };
6651
6652 struct mlx5_ifc_packet_reformat_context_in_bits {
6653         u8         reformat_type[0x8];
6654         u8         reserved_at_8[0x4];
6655         u8         reformat_param_0[0x4];
6656         u8         reserved_at_10[0x6];
6657         u8         reformat_data_size[0xa];
6658
6659         u8         reformat_param_1[0x8];
6660         u8         reserved_at_28[0x8];
6661         u8         reformat_data[2][0x8];
6662
6663         u8         more_reformat_data[][0x8];
6664 };
6665
6666 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6667         u8         status[0x8];
6668         u8         reserved_at_8[0x18];
6669
6670         u8         syndrome[0x20];
6671
6672         u8         reserved_at_40[0xa0];
6673
6674         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6675 };
6676
6677 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6678         u8         opcode[0x10];
6679         u8         reserved_at_10[0x10];
6680
6681         u8         reserved_at_20[0x10];
6682         u8         op_mod[0x10];
6683
6684         u8         packet_reformat_id[0x20];
6685
6686         u8         reserved_at_60[0xa0];
6687 };
6688
6689 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_at_8[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         packet_reformat_id[0x20];
6696
6697         u8         reserved_at_60[0x20];
6698 };
6699
6700 enum {
6701         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6702         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6703         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6704 };
6705
6706 enum mlx5_reformat_ctx_type {
6707         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6708         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6709         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6710         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6711         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6712         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6713         MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6714         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6715         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6716         MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6717         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6718         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6719         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6720         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6721         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6722         MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6723         MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6724 };
6725
6726 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6727         u8         opcode[0x10];
6728         u8         reserved_at_10[0x10];
6729
6730         u8         reserved_at_20[0x10];
6731         u8         op_mod[0x10];
6732
6733         u8         reserved_at_40[0xa0];
6734
6735         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6736 };
6737
6738 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_at_8[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6748         u8         opcode[0x10];
6749         u8         reserved_at_10[0x10];
6750
6751         u8         reserved_20[0x10];
6752         u8         op_mod[0x10];
6753
6754         u8         packet_reformat_id[0x20];
6755
6756         u8         reserved_60[0x20];
6757 };
6758
6759 struct mlx5_ifc_set_action_in_bits {
6760         u8         action_type[0x4];
6761         u8         field[0xc];
6762         u8         reserved_at_10[0x3];
6763         u8         offset[0x5];
6764         u8         reserved_at_18[0x3];
6765         u8         length[0x5];
6766
6767         u8         data[0x20];
6768 };
6769
6770 struct mlx5_ifc_add_action_in_bits {
6771         u8         action_type[0x4];
6772         u8         field[0xc];
6773         u8         reserved_at_10[0x10];
6774
6775         u8         data[0x20];
6776 };
6777
6778 struct mlx5_ifc_copy_action_in_bits {
6779         u8         action_type[0x4];
6780         u8         src_field[0xc];
6781         u8         reserved_at_10[0x3];
6782         u8         src_offset[0x5];
6783         u8         reserved_at_18[0x3];
6784         u8         length[0x5];
6785
6786         u8         reserved_at_20[0x4];
6787         u8         dst_field[0xc];
6788         u8         reserved_at_30[0x3];
6789         u8         dst_offset[0x5];
6790         u8         reserved_at_38[0x8];
6791 };
6792
6793 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6794         struct mlx5_ifc_set_action_in_bits  set_action_in;
6795         struct mlx5_ifc_add_action_in_bits  add_action_in;
6796         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6797         u8         reserved_at_0[0x40];
6798 };
6799
6800 enum {
6801         MLX5_ACTION_TYPE_SET   = 0x1,
6802         MLX5_ACTION_TYPE_ADD   = 0x2,
6803         MLX5_ACTION_TYPE_COPY  = 0x3,
6804 };
6805
6806 enum {
6807         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6808         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6809         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6810         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6811         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6812         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6813         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6814         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6815         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6816         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6817         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6818         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6819         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6820         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6821         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6822         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6823         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6824         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6825         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6826         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6827         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6828         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6829         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6830         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6831         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6832         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6833         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6834         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6835         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6836         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6837         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6838         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6839         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6840         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6841         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6842         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6843         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6844         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6845         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6846 };
6847
6848 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6849         u8         status[0x8];
6850         u8         reserved_at_8[0x18];
6851
6852         u8         syndrome[0x20];
6853
6854         u8         modify_header_id[0x20];
6855
6856         u8         reserved_at_60[0x20];
6857 };
6858
6859 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6860         u8         opcode[0x10];
6861         u8         reserved_at_10[0x10];
6862
6863         u8         reserved_at_20[0x10];
6864         u8         op_mod[0x10];
6865
6866         u8         reserved_at_40[0x20];
6867
6868         u8         table_type[0x8];
6869         u8         reserved_at_68[0x10];
6870         u8         num_of_actions[0x8];
6871
6872         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6873 };
6874
6875 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6876         u8         status[0x8];
6877         u8         reserved_at_8[0x18];
6878
6879         u8         syndrome[0x20];
6880
6881         u8         reserved_at_40[0x40];
6882 };
6883
6884 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6885         u8         opcode[0x10];
6886         u8         reserved_at_10[0x10];
6887
6888         u8         reserved_at_20[0x10];
6889         u8         op_mod[0x10];
6890
6891         u8         modify_header_id[0x20];
6892
6893         u8         reserved_at_60[0x20];
6894 };
6895
6896 struct mlx5_ifc_query_modify_header_context_in_bits {
6897         u8         opcode[0x10];
6898         u8         uid[0x10];
6899
6900         u8         reserved_at_20[0x10];
6901         u8         op_mod[0x10];
6902
6903         u8         modify_header_id[0x20];
6904
6905         u8         reserved_at_60[0xa0];
6906 };
6907
6908 struct mlx5_ifc_query_dct_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x40];
6915
6916         struct mlx5_ifc_dctc_bits dct_context_entry;
6917
6918         u8         reserved_at_280[0x180];
6919 };
6920
6921 struct mlx5_ifc_query_dct_in_bits {
6922         u8         opcode[0x10];
6923         u8         reserved_at_10[0x10];
6924
6925         u8         reserved_at_20[0x10];
6926         u8         op_mod[0x10];
6927
6928         u8         reserved_at_40[0x8];
6929         u8         dctn[0x18];
6930
6931         u8         reserved_at_60[0x20];
6932 };
6933
6934 struct mlx5_ifc_query_cq_out_bits {
6935         u8         status[0x8];
6936         u8         reserved_at_8[0x18];
6937
6938         u8         syndrome[0x20];
6939
6940         u8         reserved_at_40[0x40];
6941
6942         struct mlx5_ifc_cqc_bits cq_context;
6943
6944         u8         reserved_at_280[0x600];
6945
6946         u8         pas[][0x40];
6947 };
6948
6949 struct mlx5_ifc_query_cq_in_bits {
6950         u8         opcode[0x10];
6951         u8         reserved_at_10[0x10];
6952
6953         u8         reserved_at_20[0x10];
6954         u8         op_mod[0x10];
6955
6956         u8         reserved_at_40[0x8];
6957         u8         cqn[0x18];
6958
6959         u8         reserved_at_60[0x20];
6960 };
6961
6962 struct mlx5_ifc_query_cong_status_out_bits {
6963         u8         status[0x8];
6964         u8         reserved_at_8[0x18];
6965
6966         u8         syndrome[0x20];
6967
6968         u8         reserved_at_40[0x20];
6969
6970         u8         enable[0x1];
6971         u8         tag_enable[0x1];
6972         u8         reserved_at_62[0x1e];
6973 };
6974
6975 struct mlx5_ifc_query_cong_status_in_bits {
6976         u8         opcode[0x10];
6977         u8         reserved_at_10[0x10];
6978
6979         u8         reserved_at_20[0x10];
6980         u8         op_mod[0x10];
6981
6982         u8         reserved_at_40[0x18];
6983         u8         priority[0x4];
6984         u8         cong_protocol[0x4];
6985
6986         u8         reserved_at_60[0x20];
6987 };
6988
6989 struct mlx5_ifc_query_cong_statistics_out_bits {
6990         u8         status[0x8];
6991         u8         reserved_at_8[0x18];
6992
6993         u8         syndrome[0x20];
6994
6995         u8         reserved_at_40[0x40];
6996
6997         u8         rp_cur_flows[0x20];
6998
6999         u8         sum_flows[0x20];
7000
7001         u8         rp_cnp_ignored_high[0x20];
7002
7003         u8         rp_cnp_ignored_low[0x20];
7004
7005         u8         rp_cnp_handled_high[0x20];
7006
7007         u8         rp_cnp_handled_low[0x20];
7008
7009         u8         reserved_at_140[0x100];
7010
7011         u8         time_stamp_high[0x20];
7012
7013         u8         time_stamp_low[0x20];
7014
7015         u8         accumulators_period[0x20];
7016
7017         u8         np_ecn_marked_roce_packets_high[0x20];
7018
7019         u8         np_ecn_marked_roce_packets_low[0x20];
7020
7021         u8         np_cnp_sent_high[0x20];
7022
7023         u8         np_cnp_sent_low[0x20];
7024
7025         u8         reserved_at_320[0x560];
7026 };
7027
7028 struct mlx5_ifc_query_cong_statistics_in_bits {
7029         u8         opcode[0x10];
7030         u8         reserved_at_10[0x10];
7031
7032         u8         reserved_at_20[0x10];
7033         u8         op_mod[0x10];
7034
7035         u8         clear[0x1];
7036         u8         reserved_at_41[0x1f];
7037
7038         u8         reserved_at_60[0x20];
7039 };
7040
7041 struct mlx5_ifc_query_cong_params_out_bits {
7042         u8         status[0x8];
7043         u8         reserved_at_8[0x18];
7044
7045         u8         syndrome[0x20];
7046
7047         u8         reserved_at_40[0x40];
7048
7049         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7050 };
7051
7052 struct mlx5_ifc_query_cong_params_in_bits {
7053         u8         opcode[0x10];
7054         u8         reserved_at_10[0x10];
7055
7056         u8         reserved_at_20[0x10];
7057         u8         op_mod[0x10];
7058
7059         u8         reserved_at_40[0x1c];
7060         u8         cong_protocol[0x4];
7061
7062         u8         reserved_at_60[0x20];
7063 };
7064
7065 struct mlx5_ifc_query_adapter_out_bits {
7066         u8         status[0x8];
7067         u8         reserved_at_8[0x18];
7068
7069         u8         syndrome[0x20];
7070
7071         u8         reserved_at_40[0x40];
7072
7073         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7074 };
7075
7076 struct mlx5_ifc_query_adapter_in_bits {
7077         u8         opcode[0x10];
7078         u8         reserved_at_10[0x10];
7079
7080         u8         reserved_at_20[0x10];
7081         u8         op_mod[0x10];
7082
7083         u8         reserved_at_40[0x40];
7084 };
7085
7086 struct mlx5_ifc_qp_2rst_out_bits {
7087         u8         status[0x8];
7088         u8         reserved_at_8[0x18];
7089
7090         u8         syndrome[0x20];
7091
7092         u8         reserved_at_40[0x40];
7093 };
7094
7095 struct mlx5_ifc_qp_2rst_in_bits {
7096         u8         opcode[0x10];
7097         u8         uid[0x10];
7098
7099         u8         reserved_at_20[0x10];
7100         u8         op_mod[0x10];
7101
7102         u8         reserved_at_40[0x8];
7103         u8         qpn[0x18];
7104
7105         u8         reserved_at_60[0x20];
7106 };
7107
7108 struct mlx5_ifc_qp_2err_out_bits {
7109         u8         status[0x8];
7110         u8         reserved_at_8[0x18];
7111
7112         u8         syndrome[0x20];
7113
7114         u8         reserved_at_40[0x40];
7115 };
7116
7117 struct mlx5_ifc_qp_2err_in_bits {
7118         u8         opcode[0x10];
7119         u8         uid[0x10];
7120
7121         u8         reserved_at_20[0x10];
7122         u8         op_mod[0x10];
7123
7124         u8         reserved_at_40[0x8];
7125         u8         qpn[0x18];
7126
7127         u8         reserved_at_60[0x20];
7128 };
7129
7130 struct mlx5_ifc_page_fault_resume_out_bits {
7131         u8         status[0x8];
7132         u8         reserved_at_8[0x18];
7133
7134         u8         syndrome[0x20];
7135
7136         u8         reserved_at_40[0x40];
7137 };
7138
7139 struct mlx5_ifc_page_fault_resume_in_bits {
7140         u8         opcode[0x10];
7141         u8         reserved_at_10[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         error[0x1];
7147         u8         reserved_at_41[0x4];
7148         u8         page_fault_type[0x3];
7149         u8         wq_number[0x18];
7150
7151         u8         reserved_at_60[0x8];
7152         u8         token[0x18];
7153 };
7154
7155 struct mlx5_ifc_nop_out_bits {
7156         u8         status[0x8];
7157         u8         reserved_at_8[0x18];
7158
7159         u8         syndrome[0x20];
7160
7161         u8         reserved_at_40[0x40];
7162 };
7163
7164 struct mlx5_ifc_nop_in_bits {
7165         u8         opcode[0x10];
7166         u8         reserved_at_10[0x10];
7167
7168         u8         reserved_at_20[0x10];
7169         u8         op_mod[0x10];
7170
7171         u8         reserved_at_40[0x40];
7172 };
7173
7174 struct mlx5_ifc_modify_vport_state_out_bits {
7175         u8         status[0x8];
7176         u8         reserved_at_8[0x18];
7177
7178         u8         syndrome[0x20];
7179
7180         u8         reserved_at_40[0x40];
7181 };
7182
7183 struct mlx5_ifc_modify_vport_state_in_bits {
7184         u8         opcode[0x10];
7185         u8         reserved_at_10[0x10];
7186
7187         u8         reserved_at_20[0x10];
7188         u8         op_mod[0x10];
7189
7190         u8         other_vport[0x1];
7191         u8         reserved_at_41[0xf];
7192         u8         vport_number[0x10];
7193
7194         u8         reserved_at_60[0x18];
7195         u8         admin_state[0x4];
7196         u8         reserved_at_7c[0x4];
7197 };
7198
7199 struct mlx5_ifc_modify_tis_out_bits {
7200         u8         status[0x8];
7201         u8         reserved_at_8[0x18];
7202
7203         u8         syndrome[0x20];
7204
7205         u8         reserved_at_40[0x40];
7206 };
7207
7208 struct mlx5_ifc_modify_tis_bitmask_bits {
7209         u8         reserved_at_0[0x20];
7210
7211         u8         reserved_at_20[0x1d];
7212         u8         lag_tx_port_affinity[0x1];
7213         u8         strict_lag_tx_port_affinity[0x1];
7214         u8         prio[0x1];
7215 };
7216
7217 struct mlx5_ifc_modify_tis_in_bits {
7218         u8         opcode[0x10];
7219         u8         uid[0x10];
7220
7221         u8         reserved_at_20[0x10];
7222         u8         op_mod[0x10];
7223
7224         u8         reserved_at_40[0x8];
7225         u8         tisn[0x18];
7226
7227         u8         reserved_at_60[0x20];
7228
7229         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7230
7231         u8         reserved_at_c0[0x40];
7232
7233         struct mlx5_ifc_tisc_bits ctx;
7234 };
7235
7236 struct mlx5_ifc_modify_tir_bitmask_bits {
7237         u8         reserved_at_0[0x20];
7238
7239         u8         reserved_at_20[0x1b];
7240         u8         self_lb_en[0x1];
7241         u8         reserved_at_3c[0x1];
7242         u8         hash[0x1];
7243         u8         reserved_at_3e[0x1];
7244         u8         packet_merge[0x1];
7245 };
7246
7247 struct mlx5_ifc_modify_tir_out_bits {
7248         u8         status[0x8];
7249         u8         reserved_at_8[0x18];
7250
7251         u8         syndrome[0x20];
7252
7253         u8         reserved_at_40[0x40];
7254 };
7255
7256 struct mlx5_ifc_modify_tir_in_bits {
7257         u8         opcode[0x10];
7258         u8         uid[0x10];
7259
7260         u8         reserved_at_20[0x10];
7261         u8         op_mod[0x10];
7262
7263         u8         reserved_at_40[0x8];
7264         u8         tirn[0x18];
7265
7266         u8         reserved_at_60[0x20];
7267
7268         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7269
7270         u8         reserved_at_c0[0x40];
7271
7272         struct mlx5_ifc_tirc_bits ctx;
7273 };
7274
7275 struct mlx5_ifc_modify_sq_out_bits {
7276         u8         status[0x8];
7277         u8         reserved_at_8[0x18];
7278
7279         u8         syndrome[0x20];
7280
7281         u8         reserved_at_40[0x40];
7282 };
7283
7284 struct mlx5_ifc_modify_sq_in_bits {
7285         u8         opcode[0x10];
7286         u8         uid[0x10];
7287
7288         u8         reserved_at_20[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         sq_state[0x4];
7292         u8         reserved_at_44[0x4];
7293         u8         sqn[0x18];
7294
7295         u8         reserved_at_60[0x20];
7296
7297         u8         modify_bitmask[0x40];
7298
7299         u8         reserved_at_c0[0x40];
7300
7301         struct mlx5_ifc_sqc_bits ctx;
7302 };
7303
7304 struct mlx5_ifc_modify_scheduling_element_out_bits {
7305         u8         status[0x8];
7306         u8         reserved_at_8[0x18];
7307
7308         u8         syndrome[0x20];
7309
7310         u8         reserved_at_40[0x1c0];
7311 };
7312
7313 enum {
7314         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7315         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7316 };
7317
7318 struct mlx5_ifc_modify_scheduling_element_in_bits {
7319         u8         opcode[0x10];
7320         u8         reserved_at_10[0x10];
7321
7322         u8         reserved_at_20[0x10];
7323         u8         op_mod[0x10];
7324
7325         u8         scheduling_hierarchy[0x8];
7326         u8         reserved_at_48[0x18];
7327
7328         u8         scheduling_element_id[0x20];
7329
7330         u8         reserved_at_80[0x20];
7331
7332         u8         modify_bitmask[0x20];
7333
7334         u8         reserved_at_c0[0x40];
7335
7336         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7337
7338         u8         reserved_at_300[0x100];
7339 };
7340
7341 struct mlx5_ifc_modify_rqt_out_bits {
7342         u8         status[0x8];
7343         u8         reserved_at_8[0x18];
7344
7345         u8         syndrome[0x20];
7346
7347         u8         reserved_at_40[0x40];
7348 };
7349
7350 struct mlx5_ifc_rqt_bitmask_bits {
7351         u8         reserved_at_0[0x20];
7352
7353         u8         reserved_at_20[0x1f];
7354         u8         rqn_list[0x1];
7355 };
7356
7357 struct mlx5_ifc_modify_rqt_in_bits {
7358         u8         opcode[0x10];
7359         u8         uid[0x10];
7360
7361         u8         reserved_at_20[0x10];
7362         u8         op_mod[0x10];
7363
7364         u8         reserved_at_40[0x8];
7365         u8         rqtn[0x18];
7366
7367         u8         reserved_at_60[0x20];
7368
7369         struct mlx5_ifc_rqt_bitmask_bits bitmask;
7370
7371         u8         reserved_at_c0[0x40];
7372
7373         struct mlx5_ifc_rqtc_bits ctx;
7374 };
7375
7376 struct mlx5_ifc_modify_rq_out_bits {
7377         u8         status[0x8];
7378         u8         reserved_at_8[0x18];
7379
7380         u8         syndrome[0x20];
7381
7382         u8         reserved_at_40[0x40];
7383 };
7384
7385 enum {
7386         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7387         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7388         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7389 };
7390
7391 struct mlx5_ifc_modify_rq_in_bits {
7392         u8         opcode[0x10];
7393         u8         uid[0x10];
7394
7395         u8         reserved_at_20[0x10];
7396         u8         op_mod[0x10];
7397
7398         u8         rq_state[0x4];
7399         u8         reserved_at_44[0x4];
7400         u8         rqn[0x18];
7401
7402         u8         reserved_at_60[0x20];
7403
7404         u8         modify_bitmask[0x40];
7405
7406         u8         reserved_at_c0[0x40];
7407
7408         struct mlx5_ifc_rqc_bits ctx;
7409 };
7410
7411 struct mlx5_ifc_modify_rmp_out_bits {
7412         u8         status[0x8];
7413         u8         reserved_at_8[0x18];
7414
7415         u8         syndrome[0x20];
7416
7417         u8         reserved_at_40[0x40];
7418 };
7419
7420 struct mlx5_ifc_rmp_bitmask_bits {
7421         u8         reserved_at_0[0x20];
7422
7423         u8         reserved_at_20[0x1f];
7424         u8         lwm[0x1];
7425 };
7426
7427 struct mlx5_ifc_modify_rmp_in_bits {
7428         u8         opcode[0x10];
7429         u8         uid[0x10];
7430
7431         u8         reserved_at_20[0x10];
7432         u8         op_mod[0x10];
7433
7434         u8         rmp_state[0x4];
7435         u8         reserved_at_44[0x4];
7436         u8         rmpn[0x18];
7437
7438         u8         reserved_at_60[0x20];
7439
7440         struct mlx5_ifc_rmp_bitmask_bits bitmask;
7441
7442         u8         reserved_at_c0[0x40];
7443
7444         struct mlx5_ifc_rmpc_bits ctx;
7445 };
7446
7447 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7448         u8         status[0x8];
7449         u8         reserved_at_8[0x18];
7450
7451         u8         syndrome[0x20];
7452
7453         u8         reserved_at_40[0x40];
7454 };
7455
7456 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7457         u8         reserved_at_0[0x12];
7458         u8         affiliation[0x1];
7459         u8         reserved_at_13[0x1];
7460         u8         disable_uc_local_lb[0x1];
7461         u8         disable_mc_local_lb[0x1];
7462         u8         node_guid[0x1];
7463         u8         port_guid[0x1];
7464         u8         min_inline[0x1];
7465         u8         mtu[0x1];
7466         u8         change_event[0x1];
7467         u8         promisc[0x1];
7468         u8         permanent_address[0x1];
7469         u8         addresses_list[0x1];
7470         u8         roce_en[0x1];
7471         u8         reserved_at_1f[0x1];
7472 };
7473
7474 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7475         u8         opcode[0x10];
7476         u8         reserved_at_10[0x10];
7477
7478         u8         reserved_at_20[0x10];
7479         u8         op_mod[0x10];
7480
7481         u8         other_vport[0x1];
7482         u8         reserved_at_41[0xf];
7483         u8         vport_number[0x10];
7484
7485         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7486
7487         u8         reserved_at_80[0x780];
7488
7489         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7490 };
7491
7492 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7493         u8         status[0x8];
7494         u8         reserved_at_8[0x18];
7495
7496         u8         syndrome[0x20];
7497
7498         u8         reserved_at_40[0x40];
7499 };
7500
7501 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7502         u8         opcode[0x10];
7503         u8         reserved_at_10[0x10];
7504
7505         u8         reserved_at_20[0x10];
7506         u8         op_mod[0x10];
7507
7508         u8         other_vport[0x1];
7509         u8         reserved_at_41[0xb];
7510         u8         port_num[0x4];
7511         u8         vport_number[0x10];
7512
7513         u8         reserved_at_60[0x20];
7514
7515         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7516 };
7517
7518 struct mlx5_ifc_modify_cq_out_bits {
7519         u8         status[0x8];
7520         u8         reserved_at_8[0x18];
7521
7522         u8         syndrome[0x20];
7523
7524         u8         reserved_at_40[0x40];
7525 };
7526
7527 enum {
7528         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7529         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7530 };
7531
7532 struct mlx5_ifc_modify_cq_in_bits {
7533         u8         opcode[0x10];
7534         u8         uid[0x10];
7535
7536         u8         reserved_at_20[0x10];
7537         u8         op_mod[0x10];
7538
7539         u8         reserved_at_40[0x8];
7540         u8         cqn[0x18];
7541
7542         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7543
7544         struct mlx5_ifc_cqc_bits cq_context;
7545
7546         u8         reserved_at_280[0x60];
7547
7548         u8         cq_umem_valid[0x1];
7549         u8         reserved_at_2e1[0x1f];
7550
7551         u8         reserved_at_300[0x580];
7552
7553         u8         pas[][0x40];
7554 };
7555
7556 struct mlx5_ifc_modify_cong_status_out_bits {
7557         u8         status[0x8];
7558         u8         reserved_at_8[0x18];
7559
7560         u8         syndrome[0x20];
7561
7562         u8         reserved_at_40[0x40];
7563 };
7564
7565 struct mlx5_ifc_modify_cong_status_in_bits {
7566         u8         opcode[0x10];
7567         u8         reserved_at_10[0x10];
7568
7569         u8         reserved_at_20[0x10];
7570         u8         op_mod[0x10];
7571
7572         u8         reserved_at_40[0x18];
7573         u8         priority[0x4];
7574         u8         cong_protocol[0x4];
7575
7576         u8         enable[0x1];
7577         u8         tag_enable[0x1];
7578         u8         reserved_at_62[0x1e];
7579 };
7580
7581 struct mlx5_ifc_modify_cong_params_out_bits {
7582         u8         status[0x8];
7583         u8         reserved_at_8[0x18];
7584
7585         u8         syndrome[0x20];
7586
7587         u8         reserved_at_40[0x40];
7588 };
7589
7590 struct mlx5_ifc_modify_cong_params_in_bits {
7591         u8         opcode[0x10];
7592         u8         reserved_at_10[0x10];
7593
7594         u8         reserved_at_20[0x10];
7595         u8         op_mod[0x10];
7596
7597         u8         reserved_at_40[0x1c];
7598         u8         cong_protocol[0x4];
7599
7600         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7601
7602         u8         reserved_at_80[0x80];
7603
7604         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7605 };
7606
7607 struct mlx5_ifc_manage_pages_out_bits {
7608         u8         status[0x8];
7609         u8         reserved_at_8[0x18];
7610
7611         u8         syndrome[0x20];
7612
7613         u8         output_num_entries[0x20];
7614
7615         u8         reserved_at_60[0x20];
7616
7617         u8         pas[][0x40];
7618 };
7619
7620 enum {
7621         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7622         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7623         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7624 };
7625
7626 struct mlx5_ifc_manage_pages_in_bits {
7627         u8         opcode[0x10];
7628         u8         reserved_at_10[0x10];
7629
7630         u8         reserved_at_20[0x10];
7631         u8         op_mod[0x10];
7632
7633         u8         embedded_cpu_function[0x1];
7634         u8         reserved_at_41[0xf];
7635         u8         function_id[0x10];
7636
7637         u8         input_num_entries[0x20];
7638
7639         u8         pas[][0x40];
7640 };
7641
7642 struct mlx5_ifc_mad_ifc_out_bits {
7643         u8         status[0x8];
7644         u8         reserved_at_8[0x18];
7645
7646         u8         syndrome[0x20];
7647
7648         u8         reserved_at_40[0x40];
7649
7650         u8         response_mad_packet[256][0x8];
7651 };
7652
7653 struct mlx5_ifc_mad_ifc_in_bits {
7654         u8         opcode[0x10];
7655         u8         reserved_at_10[0x10];
7656
7657         u8         reserved_at_20[0x10];
7658         u8         op_mod[0x10];
7659
7660         u8         remote_lid[0x10];
7661         u8         reserved_at_50[0x8];
7662         u8         port[0x8];
7663
7664         u8         reserved_at_60[0x20];
7665
7666         u8         mad[256][0x8];
7667 };
7668
7669 struct mlx5_ifc_init_hca_out_bits {
7670         u8         status[0x8];
7671         u8         reserved_at_8[0x18];
7672
7673         u8         syndrome[0x20];
7674
7675         u8         reserved_at_40[0x40];
7676 };
7677
7678 struct mlx5_ifc_init_hca_in_bits {
7679         u8         opcode[0x10];
7680         u8         reserved_at_10[0x10];
7681
7682         u8         reserved_at_20[0x10];
7683         u8         op_mod[0x10];
7684
7685         u8         reserved_at_40[0x20];
7686
7687         u8         reserved_at_60[0x2];
7688         u8         sw_vhca_id[0xe];
7689         u8         reserved_at_70[0x10];
7690
7691         u8         sw_owner_id[4][0x20];
7692 };
7693
7694 struct mlx5_ifc_init2rtr_qp_out_bits {
7695         u8         status[0x8];
7696         u8         reserved_at_8[0x18];
7697
7698         u8         syndrome[0x20];
7699
7700         u8         reserved_at_40[0x20];
7701         u8         ece[0x20];
7702 };
7703
7704 struct mlx5_ifc_init2rtr_qp_in_bits {
7705         u8         opcode[0x10];
7706         u8         uid[0x10];
7707
7708         u8         reserved_at_20[0x10];
7709         u8         op_mod[0x10];
7710
7711         u8         reserved_at_40[0x8];
7712         u8         qpn[0x18];
7713
7714         u8         reserved_at_60[0x20];
7715
7716         u8         opt_param_mask[0x20];
7717
7718         u8         ece[0x20];
7719
7720         struct mlx5_ifc_qpc_bits qpc;
7721
7722         u8         reserved_at_800[0x80];
7723 };
7724
7725 struct mlx5_ifc_init2init_qp_out_bits {
7726         u8         status[0x8];
7727         u8         reserved_at_8[0x18];
7728
7729         u8         syndrome[0x20];
7730
7731         u8         reserved_at_40[0x20];
7732         u8         ece[0x20];
7733 };
7734
7735 struct mlx5_ifc_init2init_qp_in_bits {
7736         u8         opcode[0x10];
7737         u8         uid[0x10];
7738
7739         u8         reserved_at_20[0x10];
7740         u8         op_mod[0x10];
7741
7742         u8         reserved_at_40[0x8];
7743         u8         qpn[0x18];
7744
7745         u8         reserved_at_60[0x20];
7746
7747         u8         opt_param_mask[0x20];
7748
7749         u8         ece[0x20];
7750
7751         struct mlx5_ifc_qpc_bits qpc;
7752
7753         u8         reserved_at_800[0x80];
7754 };
7755
7756 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7757         u8         status[0x8];
7758         u8         reserved_at_8[0x18];
7759
7760         u8         syndrome[0x20];
7761
7762         u8         reserved_at_40[0x40];
7763
7764         u8         packet_headers_log[128][0x8];
7765
7766         u8         packet_syndrome[64][0x8];
7767 };
7768
7769 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7770         u8         opcode[0x10];
7771         u8         reserved_at_10[0x10];
7772
7773         u8         reserved_at_20[0x10];
7774         u8         op_mod[0x10];
7775
7776         u8         reserved_at_40[0x40];
7777 };
7778
7779 struct mlx5_ifc_gen_eqe_in_bits {
7780         u8         opcode[0x10];
7781         u8         reserved_at_10[0x10];
7782
7783         u8         reserved_at_20[0x10];
7784         u8         op_mod[0x10];
7785
7786         u8         reserved_at_40[0x18];
7787         u8         eq_number[0x8];
7788
7789         u8         reserved_at_60[0x20];
7790
7791         u8         eqe[64][0x8];
7792 };
7793
7794 struct mlx5_ifc_gen_eq_out_bits {
7795         u8         status[0x8];
7796         u8         reserved_at_8[0x18];
7797
7798         u8         syndrome[0x20];
7799
7800         u8         reserved_at_40[0x40];
7801 };
7802
7803 struct mlx5_ifc_enable_hca_out_bits {
7804         u8         status[0x8];
7805         u8         reserved_at_8[0x18];
7806
7807         u8         syndrome[0x20];
7808
7809         u8         reserved_at_40[0x20];
7810 };
7811
7812 struct mlx5_ifc_enable_hca_in_bits {
7813         u8         opcode[0x10];
7814         u8         reserved_at_10[0x10];
7815
7816         u8         reserved_at_20[0x10];
7817         u8         op_mod[0x10];
7818
7819         u8         embedded_cpu_function[0x1];
7820         u8         reserved_at_41[0xf];
7821         u8         function_id[0x10];
7822
7823         u8         reserved_at_60[0x20];
7824 };
7825
7826 struct mlx5_ifc_drain_dct_out_bits {
7827         u8         status[0x8];
7828         u8         reserved_at_8[0x18];
7829
7830         u8         syndrome[0x20];
7831
7832         u8         reserved_at_40[0x40];
7833 };
7834
7835 struct mlx5_ifc_drain_dct_in_bits {
7836         u8         opcode[0x10];
7837         u8         uid[0x10];
7838
7839         u8         reserved_at_20[0x10];
7840         u8         op_mod[0x10];
7841
7842         u8         reserved_at_40[0x8];
7843         u8         dctn[0x18];
7844
7845         u8         reserved_at_60[0x20];
7846 };
7847
7848 struct mlx5_ifc_disable_hca_out_bits {
7849         u8         status[0x8];
7850         u8         reserved_at_8[0x18];
7851
7852         u8         syndrome[0x20];
7853
7854         u8         reserved_at_40[0x20];
7855 };
7856
7857 struct mlx5_ifc_disable_hca_in_bits {
7858         u8         opcode[0x10];
7859         u8         reserved_at_10[0x10];
7860
7861         u8         reserved_at_20[0x10];
7862         u8         op_mod[0x10];
7863
7864         u8         embedded_cpu_function[0x1];
7865         u8         reserved_at_41[0xf];
7866         u8         function_id[0x10];
7867
7868         u8         reserved_at_60[0x20];
7869 };
7870
7871 struct mlx5_ifc_detach_from_mcg_out_bits {
7872         u8         status[0x8];
7873         u8         reserved_at_8[0x18];
7874
7875         u8         syndrome[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878 };
7879
7880 struct mlx5_ifc_detach_from_mcg_in_bits {
7881         u8         opcode[0x10];
7882         u8         uid[0x10];
7883
7884         u8         reserved_at_20[0x10];
7885         u8         op_mod[0x10];
7886
7887         u8         reserved_at_40[0x8];
7888         u8         qpn[0x18];
7889
7890         u8         reserved_at_60[0x20];
7891
7892         u8         multicast_gid[16][0x8];
7893 };
7894
7895 struct mlx5_ifc_destroy_xrq_out_bits {
7896         u8         status[0x8];
7897         u8         reserved_at_8[0x18];
7898
7899         u8         syndrome[0x20];
7900
7901         u8         reserved_at_40[0x40];
7902 };
7903
7904 struct mlx5_ifc_destroy_xrq_in_bits {
7905         u8         opcode[0x10];
7906         u8         uid[0x10];
7907
7908         u8         reserved_at_20[0x10];
7909         u8         op_mod[0x10];
7910
7911         u8         reserved_at_40[0x8];
7912         u8         xrqn[0x18];
7913
7914         u8         reserved_at_60[0x20];
7915 };
7916
7917 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7918         u8         status[0x8];
7919         u8         reserved_at_8[0x18];
7920
7921         u8         syndrome[0x20];
7922
7923         u8         reserved_at_40[0x40];
7924 };
7925
7926 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7927         u8         opcode[0x10];
7928         u8         uid[0x10];
7929
7930         u8         reserved_at_20[0x10];
7931         u8         op_mod[0x10];
7932
7933         u8         reserved_at_40[0x8];
7934         u8         xrc_srqn[0x18];
7935
7936         u8         reserved_at_60[0x20];
7937 };
7938
7939 struct mlx5_ifc_destroy_tis_out_bits {
7940         u8         status[0x8];
7941         u8         reserved_at_8[0x18];
7942
7943         u8         syndrome[0x20];
7944
7945         u8         reserved_at_40[0x40];
7946 };
7947
7948 struct mlx5_ifc_destroy_tis_in_bits {
7949         u8         opcode[0x10];
7950         u8         uid[0x10];
7951
7952         u8         reserved_at_20[0x10];
7953         u8         op_mod[0x10];
7954
7955         u8         reserved_at_40[0x8];
7956         u8         tisn[0x18];
7957
7958         u8         reserved_at_60[0x20];
7959 };
7960
7961 struct mlx5_ifc_destroy_tir_out_bits {
7962         u8         status[0x8];
7963         u8         reserved_at_8[0x18];
7964
7965         u8         syndrome[0x20];
7966
7967         u8         reserved_at_40[0x40];
7968 };
7969
7970 struct mlx5_ifc_destroy_tir_in_bits {
7971         u8         opcode[0x10];
7972         u8         uid[0x10];
7973
7974         u8         reserved_at_20[0x10];
7975         u8         op_mod[0x10];
7976
7977         u8         reserved_at_40[0x8];
7978         u8         tirn[0x18];
7979
7980         u8         reserved_at_60[0x20];
7981 };
7982
7983 struct mlx5_ifc_destroy_srq_out_bits {
7984         u8         status[0x8];
7985         u8         reserved_at_8[0x18];
7986
7987         u8         syndrome[0x20];
7988
7989         u8         reserved_at_40[0x40];
7990 };
7991
7992 struct mlx5_ifc_destroy_srq_in_bits {
7993         u8         opcode[0x10];
7994         u8         uid[0x10];
7995
7996         u8         reserved_at_20[0x10];
7997         u8         op_mod[0x10];
7998
7999         u8         reserved_at_40[0x8];
8000         u8         srqn[0x18];
8001
8002         u8         reserved_at_60[0x20];
8003 };
8004
8005 struct mlx5_ifc_destroy_sq_out_bits {
8006         u8         status[0x8];
8007         u8         reserved_at_8[0x18];
8008
8009         u8         syndrome[0x20];
8010
8011         u8         reserved_at_40[0x40];
8012 };
8013
8014 struct mlx5_ifc_destroy_sq_in_bits {
8015         u8         opcode[0x10];
8016         u8         uid[0x10];
8017
8018         u8         reserved_at_20[0x10];
8019         u8         op_mod[0x10];
8020
8021         u8         reserved_at_40[0x8];
8022         u8         sqn[0x18];
8023
8024         u8         reserved_at_60[0x20];
8025 };
8026
8027 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8028         u8         status[0x8];
8029         u8         reserved_at_8[0x18];
8030
8031         u8         syndrome[0x20];
8032
8033         u8         reserved_at_40[0x1c0];
8034 };
8035
8036 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8037         u8         opcode[0x10];
8038         u8         reserved_at_10[0x10];
8039
8040         u8         reserved_at_20[0x10];
8041         u8         op_mod[0x10];
8042
8043         u8         scheduling_hierarchy[0x8];
8044         u8         reserved_at_48[0x18];
8045
8046         u8         scheduling_element_id[0x20];
8047
8048         u8         reserved_at_80[0x180];
8049 };
8050
8051 struct mlx5_ifc_destroy_rqt_out_bits {
8052         u8         status[0x8];
8053         u8         reserved_at_8[0x18];
8054
8055         u8         syndrome[0x20];
8056
8057         u8         reserved_at_40[0x40];
8058 };
8059
8060 struct mlx5_ifc_destroy_rqt_in_bits {
8061         u8         opcode[0x10];
8062         u8         uid[0x10];
8063
8064         u8         reserved_at_20[0x10];
8065         u8         op_mod[0x10];
8066
8067         u8         reserved_at_40[0x8];
8068         u8         rqtn[0x18];
8069
8070         u8         reserved_at_60[0x20];
8071 };
8072
8073 struct mlx5_ifc_destroy_rq_out_bits {
8074         u8         status[0x8];
8075         u8         reserved_at_8[0x18];
8076
8077         u8         syndrome[0x20];
8078
8079         u8         reserved_at_40[0x40];
8080 };
8081
8082 struct mlx5_ifc_destroy_rq_in_bits {
8083         u8         opcode[0x10];
8084         u8         uid[0x10];
8085
8086         u8         reserved_at_20[0x10];
8087         u8         op_mod[0x10];
8088
8089         u8         reserved_at_40[0x8];
8090         u8         rqn[0x18];
8091
8092         u8         reserved_at_60[0x20];
8093 };
8094
8095 struct mlx5_ifc_set_delay_drop_params_in_bits {
8096         u8         opcode[0x10];
8097         u8         reserved_at_10[0x10];
8098
8099         u8         reserved_at_20[0x10];
8100         u8         op_mod[0x10];
8101
8102         u8         reserved_at_40[0x20];
8103
8104         u8         reserved_at_60[0x10];
8105         u8         delay_drop_timeout[0x10];
8106 };
8107
8108 struct mlx5_ifc_set_delay_drop_params_out_bits {
8109         u8         status[0x8];
8110         u8         reserved_at_8[0x18];
8111
8112         u8         syndrome[0x20];
8113
8114         u8         reserved_at_40[0x40];
8115 };
8116
8117 struct mlx5_ifc_destroy_rmp_out_bits {
8118         u8         status[0x8];
8119         u8         reserved_at_8[0x18];
8120
8121         u8         syndrome[0x20];
8122
8123         u8         reserved_at_40[0x40];
8124 };
8125
8126 struct mlx5_ifc_destroy_rmp_in_bits {
8127         u8         opcode[0x10];
8128         u8         uid[0x10];
8129
8130         u8         reserved_at_20[0x10];
8131         u8         op_mod[0x10];
8132
8133         u8         reserved_at_40[0x8];
8134         u8         rmpn[0x18];
8135
8136         u8         reserved_at_60[0x20];
8137 };
8138
8139 struct mlx5_ifc_destroy_qp_out_bits {
8140         u8         status[0x8];
8141         u8         reserved_at_8[0x18];
8142
8143         u8         syndrome[0x20];
8144
8145         u8         reserved_at_40[0x40];
8146 };
8147
8148 struct mlx5_ifc_destroy_qp_in_bits {
8149         u8         opcode[0x10];
8150         u8         uid[0x10];
8151
8152         u8         reserved_at_20[0x10];
8153         u8         op_mod[0x10];
8154
8155         u8         reserved_at_40[0x8];
8156         u8         qpn[0x18];
8157
8158         u8         reserved_at_60[0x20];
8159 };
8160
8161 struct mlx5_ifc_destroy_psv_out_bits {
8162         u8         status[0x8];
8163         u8         reserved_at_8[0x18];
8164
8165         u8         syndrome[0x20];
8166
8167         u8         reserved_at_40[0x40];
8168 };
8169
8170 struct mlx5_ifc_destroy_psv_in_bits {
8171         u8         opcode[0x10];
8172         u8         reserved_at_10[0x10];
8173
8174         u8         reserved_at_20[0x10];
8175         u8         op_mod[0x10];
8176
8177         u8         reserved_at_40[0x8];
8178         u8         psvn[0x18];
8179
8180         u8         reserved_at_60[0x20];
8181 };
8182
8183 struct mlx5_ifc_destroy_mkey_out_bits {
8184         u8         status[0x8];
8185         u8         reserved_at_8[0x18];
8186
8187         u8         syndrome[0x20];
8188
8189         u8         reserved_at_40[0x40];
8190 };
8191
8192 struct mlx5_ifc_destroy_mkey_in_bits {
8193         u8         opcode[0x10];
8194         u8         uid[0x10];
8195
8196         u8         reserved_at_20[0x10];
8197         u8         op_mod[0x10];
8198
8199         u8         reserved_at_40[0x8];
8200         u8         mkey_index[0x18];
8201
8202         u8         reserved_at_60[0x20];
8203 };
8204
8205 struct mlx5_ifc_destroy_flow_table_out_bits {
8206         u8         status[0x8];
8207         u8         reserved_at_8[0x18];
8208
8209         u8         syndrome[0x20];
8210
8211         u8         reserved_at_40[0x40];
8212 };
8213
8214 struct mlx5_ifc_destroy_flow_table_in_bits {
8215         u8         opcode[0x10];
8216         u8         reserved_at_10[0x10];
8217
8218         u8         reserved_at_20[0x10];
8219         u8         op_mod[0x10];
8220
8221         u8         other_vport[0x1];
8222         u8         reserved_at_41[0xf];
8223         u8         vport_number[0x10];
8224
8225         u8         reserved_at_60[0x20];
8226
8227         u8         table_type[0x8];
8228         u8         reserved_at_88[0x18];
8229
8230         u8         reserved_at_a0[0x8];
8231         u8         table_id[0x18];
8232
8233         u8         reserved_at_c0[0x140];
8234 };
8235
8236 struct mlx5_ifc_destroy_flow_group_out_bits {
8237         u8         status[0x8];
8238         u8         reserved_at_8[0x18];
8239
8240         u8         syndrome[0x20];
8241
8242         u8         reserved_at_40[0x40];
8243 };
8244
8245 struct mlx5_ifc_destroy_flow_group_in_bits {
8246         u8         opcode[0x10];
8247         u8         reserved_at_10[0x10];
8248
8249         u8         reserved_at_20[0x10];
8250         u8         op_mod[0x10];
8251
8252         u8         other_vport[0x1];
8253         u8         reserved_at_41[0xf];
8254         u8         vport_number[0x10];
8255
8256         u8         reserved_at_60[0x20];
8257
8258         u8         table_type[0x8];
8259         u8         reserved_at_88[0x18];
8260
8261         u8         reserved_at_a0[0x8];
8262         u8         table_id[0x18];
8263
8264         u8         group_id[0x20];
8265
8266         u8         reserved_at_e0[0x120];
8267 };
8268
8269 struct mlx5_ifc_destroy_eq_out_bits {
8270         u8         status[0x8];
8271         u8         reserved_at_8[0x18];
8272
8273         u8         syndrome[0x20];
8274
8275         u8         reserved_at_40[0x40];
8276 };
8277
8278 struct mlx5_ifc_destroy_eq_in_bits {
8279         u8         opcode[0x10];
8280         u8         reserved_at_10[0x10];
8281
8282         u8         reserved_at_20[0x10];
8283         u8         op_mod[0x10];
8284
8285         u8         reserved_at_40[0x18];
8286         u8         eq_number[0x8];
8287
8288         u8         reserved_at_60[0x20];
8289 };
8290
8291 struct mlx5_ifc_destroy_dct_out_bits {
8292         u8         status[0x8];
8293         u8         reserved_at_8[0x18];
8294
8295         u8         syndrome[0x20];
8296
8297         u8         reserved_at_40[0x40];
8298 };
8299
8300 struct mlx5_ifc_destroy_dct_in_bits {
8301         u8         opcode[0x10];
8302         u8         uid[0x10];
8303
8304         u8         reserved_at_20[0x10];
8305         u8         op_mod[0x10];
8306
8307         u8         reserved_at_40[0x8];
8308         u8         dctn[0x18];
8309
8310         u8         reserved_at_60[0x20];
8311 };
8312
8313 struct mlx5_ifc_destroy_cq_out_bits {
8314         u8         status[0x8];
8315         u8         reserved_at_8[0x18];
8316
8317         u8         syndrome[0x20];
8318
8319         u8         reserved_at_40[0x40];
8320 };
8321
8322 struct mlx5_ifc_destroy_cq_in_bits {
8323         u8         opcode[0x10];
8324         u8         uid[0x10];
8325
8326         u8         reserved_at_20[0x10];
8327         u8         op_mod[0x10];
8328
8329         u8         reserved_at_40[0x8];
8330         u8         cqn[0x18];
8331
8332         u8         reserved_at_60[0x20];
8333 };
8334
8335 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8336         u8         status[0x8];
8337         u8         reserved_at_8[0x18];
8338
8339         u8         syndrome[0x20];
8340
8341         u8         reserved_at_40[0x40];
8342 };
8343
8344 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8345         u8         opcode[0x10];
8346         u8         reserved_at_10[0x10];
8347
8348         u8         reserved_at_20[0x10];
8349         u8         op_mod[0x10];
8350
8351         u8         reserved_at_40[0x20];
8352
8353         u8         reserved_at_60[0x10];
8354         u8         vxlan_udp_port[0x10];
8355 };
8356
8357 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8358         u8         status[0x8];
8359         u8         reserved_at_8[0x18];
8360
8361         u8         syndrome[0x20];
8362
8363         u8         reserved_at_40[0x40];
8364 };
8365
8366 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8367         u8         opcode[0x10];
8368         u8         reserved_at_10[0x10];
8369
8370         u8         reserved_at_20[0x10];
8371         u8         op_mod[0x10];
8372
8373         u8         reserved_at_40[0x60];
8374
8375         u8         reserved_at_a0[0x8];
8376         u8         table_index[0x18];
8377
8378         u8         reserved_at_c0[0x140];
8379 };
8380
8381 struct mlx5_ifc_delete_fte_out_bits {
8382         u8         status[0x8];
8383         u8         reserved_at_8[0x18];
8384
8385         u8         syndrome[0x20];
8386
8387         u8         reserved_at_40[0x40];
8388 };
8389
8390 struct mlx5_ifc_delete_fte_in_bits {
8391         u8         opcode[0x10];
8392         u8         reserved_at_10[0x10];
8393
8394         u8         reserved_at_20[0x10];
8395         u8         op_mod[0x10];
8396
8397         u8         other_vport[0x1];
8398         u8         reserved_at_41[0xf];
8399         u8         vport_number[0x10];
8400
8401         u8         reserved_at_60[0x20];
8402
8403         u8         table_type[0x8];
8404         u8         reserved_at_88[0x18];
8405
8406         u8         reserved_at_a0[0x8];
8407         u8         table_id[0x18];
8408
8409         u8         reserved_at_c0[0x40];
8410
8411         u8         flow_index[0x20];
8412
8413         u8         reserved_at_120[0xe0];
8414 };
8415
8416 struct mlx5_ifc_dealloc_xrcd_out_bits {
8417         u8         status[0x8];
8418         u8         reserved_at_8[0x18];
8419
8420         u8         syndrome[0x20];
8421
8422         u8         reserved_at_40[0x40];
8423 };
8424
8425 struct mlx5_ifc_dealloc_xrcd_in_bits {
8426         u8         opcode[0x10];
8427         u8         uid[0x10];
8428
8429         u8         reserved_at_20[0x10];
8430         u8         op_mod[0x10];
8431
8432         u8         reserved_at_40[0x8];
8433         u8         xrcd[0x18];
8434
8435         u8         reserved_at_60[0x20];
8436 };
8437
8438 struct mlx5_ifc_dealloc_uar_out_bits {
8439         u8         status[0x8];
8440         u8         reserved_at_8[0x18];
8441
8442         u8         syndrome[0x20];
8443
8444         u8         reserved_at_40[0x40];
8445 };
8446
8447 struct mlx5_ifc_dealloc_uar_in_bits {
8448         u8         opcode[0x10];
8449         u8         uid[0x10];
8450
8451         u8         reserved_at_20[0x10];
8452         u8         op_mod[0x10];
8453
8454         u8         reserved_at_40[0x8];
8455         u8         uar[0x18];
8456
8457         u8         reserved_at_60[0x20];
8458 };
8459
8460 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8461         u8         status[0x8];
8462         u8         reserved_at_8[0x18];
8463
8464         u8         syndrome[0x20];
8465
8466         u8         reserved_at_40[0x40];
8467 };
8468
8469 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8470         u8         opcode[0x10];
8471         u8         uid[0x10];
8472
8473         u8         reserved_at_20[0x10];
8474         u8         op_mod[0x10];
8475
8476         u8         reserved_at_40[0x8];
8477         u8         transport_domain[0x18];
8478
8479         u8         reserved_at_60[0x20];
8480 };
8481
8482 struct mlx5_ifc_dealloc_q_counter_out_bits {
8483         u8         status[0x8];
8484         u8         reserved_at_8[0x18];
8485
8486         u8         syndrome[0x20];
8487
8488         u8         reserved_at_40[0x40];
8489 };
8490
8491 struct mlx5_ifc_dealloc_q_counter_in_bits {
8492         u8         opcode[0x10];
8493         u8         reserved_at_10[0x10];
8494
8495         u8         reserved_at_20[0x10];
8496         u8         op_mod[0x10];
8497
8498         u8         reserved_at_40[0x18];
8499         u8         counter_set_id[0x8];
8500
8501         u8         reserved_at_60[0x20];
8502 };
8503
8504 struct mlx5_ifc_dealloc_pd_out_bits {
8505         u8         status[0x8];
8506         u8         reserved_at_8[0x18];
8507
8508         u8         syndrome[0x20];
8509
8510         u8         reserved_at_40[0x40];
8511 };
8512
8513 struct mlx5_ifc_dealloc_pd_in_bits {
8514         u8         opcode[0x10];
8515         u8         uid[0x10];
8516
8517         u8         reserved_at_20[0x10];
8518         u8         op_mod[0x10];
8519
8520         u8         reserved_at_40[0x8];
8521         u8         pd[0x18];
8522
8523         u8         reserved_at_60[0x20];
8524 };
8525
8526 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8527         u8         status[0x8];
8528         u8         reserved_at_8[0x18];
8529
8530         u8         syndrome[0x20];
8531
8532         u8         reserved_at_40[0x40];
8533 };
8534
8535 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8536         u8         opcode[0x10];
8537         u8         reserved_at_10[0x10];
8538
8539         u8         reserved_at_20[0x10];
8540         u8         op_mod[0x10];
8541
8542         u8         flow_counter_id[0x20];
8543
8544         u8         reserved_at_60[0x20];
8545 };
8546
8547 struct mlx5_ifc_create_xrq_out_bits {
8548         u8         status[0x8];
8549         u8         reserved_at_8[0x18];
8550
8551         u8         syndrome[0x20];
8552
8553         u8         reserved_at_40[0x8];
8554         u8         xrqn[0x18];
8555
8556         u8         reserved_at_60[0x20];
8557 };
8558
8559 struct mlx5_ifc_create_xrq_in_bits {
8560         u8         opcode[0x10];
8561         u8         uid[0x10];
8562
8563         u8         reserved_at_20[0x10];
8564         u8         op_mod[0x10];
8565
8566         u8         reserved_at_40[0x40];
8567
8568         struct mlx5_ifc_xrqc_bits xrq_context;
8569 };
8570
8571 struct mlx5_ifc_create_xrc_srq_out_bits {
8572         u8         status[0x8];
8573         u8         reserved_at_8[0x18];
8574
8575         u8         syndrome[0x20];
8576
8577         u8         reserved_at_40[0x8];
8578         u8         xrc_srqn[0x18];
8579
8580         u8         reserved_at_60[0x20];
8581 };
8582
8583 struct mlx5_ifc_create_xrc_srq_in_bits {
8584         u8         opcode[0x10];
8585         u8         uid[0x10];
8586
8587         u8         reserved_at_20[0x10];
8588         u8         op_mod[0x10];
8589
8590         u8         reserved_at_40[0x40];
8591
8592         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8593
8594         u8         reserved_at_280[0x60];
8595
8596         u8         xrc_srq_umem_valid[0x1];
8597         u8         reserved_at_2e1[0x1f];
8598
8599         u8         reserved_at_300[0x580];
8600
8601         u8         pas[][0x40];
8602 };
8603
8604 struct mlx5_ifc_create_tis_out_bits {
8605         u8         status[0x8];
8606         u8         reserved_at_8[0x18];
8607
8608         u8         syndrome[0x20];
8609
8610         u8         reserved_at_40[0x8];
8611         u8         tisn[0x18];
8612
8613         u8         reserved_at_60[0x20];
8614 };
8615
8616 struct mlx5_ifc_create_tis_in_bits {
8617         u8         opcode[0x10];
8618         u8         uid[0x10];
8619
8620         u8         reserved_at_20[0x10];
8621         u8         op_mod[0x10];
8622
8623         u8         reserved_at_40[0xc0];
8624
8625         struct mlx5_ifc_tisc_bits ctx;
8626 };
8627
8628 struct mlx5_ifc_create_tir_out_bits {
8629         u8         status[0x8];
8630         u8         icm_address_63_40[0x18];
8631
8632         u8         syndrome[0x20];
8633
8634         u8         icm_address_39_32[0x8];
8635         u8         tirn[0x18];
8636
8637         u8         icm_address_31_0[0x20];
8638 };
8639
8640 struct mlx5_ifc_create_tir_in_bits {
8641         u8         opcode[0x10];
8642         u8         uid[0x10];
8643
8644         u8         reserved_at_20[0x10];
8645         u8         op_mod[0x10];
8646
8647         u8         reserved_at_40[0xc0];
8648
8649         struct mlx5_ifc_tirc_bits ctx;
8650 };
8651
8652 struct mlx5_ifc_create_srq_out_bits {
8653         u8         status[0x8];
8654         u8         reserved_at_8[0x18];
8655
8656         u8         syndrome[0x20];
8657
8658         u8         reserved_at_40[0x8];
8659         u8         srqn[0x18];
8660
8661         u8         reserved_at_60[0x20];
8662 };
8663
8664 struct mlx5_ifc_create_srq_in_bits {
8665         u8         opcode[0x10];
8666         u8         uid[0x10];
8667
8668         u8         reserved_at_20[0x10];
8669         u8         op_mod[0x10];
8670
8671         u8         reserved_at_40[0x40];
8672
8673         struct mlx5_ifc_srqc_bits srq_context_entry;
8674
8675         u8         reserved_at_280[0x600];
8676
8677         u8         pas[][0x40];
8678 };
8679
8680 struct mlx5_ifc_create_sq_out_bits {
8681         u8         status[0x8];
8682         u8         reserved_at_8[0x18];
8683
8684         u8         syndrome[0x20];
8685
8686         u8         reserved_at_40[0x8];
8687         u8         sqn[0x18];
8688
8689         u8         reserved_at_60[0x20];
8690 };
8691
8692 struct mlx5_ifc_create_sq_in_bits {
8693         u8         opcode[0x10];
8694         u8         uid[0x10];
8695
8696         u8         reserved_at_20[0x10];
8697         u8         op_mod[0x10];
8698
8699         u8         reserved_at_40[0xc0];
8700
8701         struct mlx5_ifc_sqc_bits ctx;
8702 };
8703
8704 struct mlx5_ifc_create_scheduling_element_out_bits {
8705         u8         status[0x8];
8706         u8         reserved_at_8[0x18];
8707
8708         u8         syndrome[0x20];
8709
8710         u8         reserved_at_40[0x40];
8711
8712         u8         scheduling_element_id[0x20];
8713
8714         u8         reserved_at_a0[0x160];
8715 };
8716
8717 struct mlx5_ifc_create_scheduling_element_in_bits {
8718         u8         opcode[0x10];
8719         u8         reserved_at_10[0x10];
8720
8721         u8         reserved_at_20[0x10];
8722         u8         op_mod[0x10];
8723
8724         u8         scheduling_hierarchy[0x8];
8725         u8         reserved_at_48[0x18];
8726
8727         u8         reserved_at_60[0xa0];
8728
8729         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8730
8731         u8         reserved_at_300[0x100];
8732 };
8733
8734 struct mlx5_ifc_create_rqt_out_bits {
8735         u8         status[0x8];
8736         u8         reserved_at_8[0x18];
8737
8738         u8         syndrome[0x20];
8739
8740         u8         reserved_at_40[0x8];
8741         u8         rqtn[0x18];
8742
8743         u8         reserved_at_60[0x20];
8744 };
8745
8746 struct mlx5_ifc_create_rqt_in_bits {
8747         u8         opcode[0x10];
8748         u8         uid[0x10];
8749
8750         u8         reserved_at_20[0x10];
8751         u8         op_mod[0x10];
8752
8753         u8         reserved_at_40[0xc0];
8754
8755         struct mlx5_ifc_rqtc_bits rqt_context;
8756 };
8757
8758 struct mlx5_ifc_create_rq_out_bits {
8759         u8         status[0x8];
8760         u8         reserved_at_8[0x18];
8761
8762         u8         syndrome[0x20];
8763
8764         u8         reserved_at_40[0x8];
8765         u8         rqn[0x18];
8766
8767         u8         reserved_at_60[0x20];
8768 };
8769
8770 struct mlx5_ifc_create_rq_in_bits {
8771         u8         opcode[0x10];
8772         u8         uid[0x10];
8773
8774         u8         reserved_at_20[0x10];
8775         u8         op_mod[0x10];
8776
8777         u8         reserved_at_40[0xc0];
8778
8779         struct mlx5_ifc_rqc_bits ctx;
8780 };
8781
8782 struct mlx5_ifc_create_rmp_out_bits {
8783         u8         status[0x8];
8784         u8         reserved_at_8[0x18];
8785
8786         u8         syndrome[0x20];
8787
8788         u8         reserved_at_40[0x8];
8789         u8         rmpn[0x18];
8790
8791         u8         reserved_at_60[0x20];
8792 };
8793
8794 struct mlx5_ifc_create_rmp_in_bits {
8795         u8         opcode[0x10];
8796         u8         uid[0x10];
8797
8798         u8         reserved_at_20[0x10];
8799         u8         op_mod[0x10];
8800
8801         u8         reserved_at_40[0xc0];
8802
8803         struct mlx5_ifc_rmpc_bits ctx;
8804 };
8805
8806 struct mlx5_ifc_create_qp_out_bits {
8807         u8         status[0x8];
8808         u8         reserved_at_8[0x18];
8809
8810         u8         syndrome[0x20];
8811
8812         u8         reserved_at_40[0x8];
8813         u8         qpn[0x18];
8814
8815         u8         ece[0x20];
8816 };
8817
8818 struct mlx5_ifc_create_qp_in_bits {
8819         u8         opcode[0x10];
8820         u8         uid[0x10];
8821
8822         u8         reserved_at_20[0x10];
8823         u8         op_mod[0x10];
8824
8825         u8         qpc_ext[0x1];
8826         u8         reserved_at_41[0x7];
8827         u8         input_qpn[0x18];
8828
8829         u8         reserved_at_60[0x20];
8830         u8         opt_param_mask[0x20];
8831
8832         u8         ece[0x20];
8833
8834         struct mlx5_ifc_qpc_bits qpc;
8835
8836         u8         reserved_at_800[0x60];
8837
8838         u8         wq_umem_valid[0x1];
8839         u8         reserved_at_861[0x1f];
8840
8841         u8         pas[][0x40];
8842 };
8843
8844 struct mlx5_ifc_create_psv_out_bits {
8845         u8         status[0x8];
8846         u8         reserved_at_8[0x18];
8847
8848         u8         syndrome[0x20];
8849
8850         u8         reserved_at_40[0x40];
8851
8852         u8         reserved_at_80[0x8];
8853         u8         psv0_index[0x18];
8854
8855         u8         reserved_at_a0[0x8];
8856         u8         psv1_index[0x18];
8857
8858         u8         reserved_at_c0[0x8];
8859         u8         psv2_index[0x18];
8860
8861         u8         reserved_at_e0[0x8];
8862         u8         psv3_index[0x18];
8863 };
8864
8865 struct mlx5_ifc_create_psv_in_bits {
8866         u8         opcode[0x10];
8867         u8         reserved_at_10[0x10];
8868
8869         u8         reserved_at_20[0x10];
8870         u8         op_mod[0x10];
8871
8872         u8         num_psv[0x4];
8873         u8         reserved_at_44[0x4];
8874         u8         pd[0x18];
8875
8876         u8         reserved_at_60[0x20];
8877 };
8878
8879 struct mlx5_ifc_create_mkey_out_bits {
8880         u8         status[0x8];
8881         u8         reserved_at_8[0x18];
8882
8883         u8         syndrome[0x20];
8884
8885         u8         reserved_at_40[0x8];
8886         u8         mkey_index[0x18];
8887
8888         u8         reserved_at_60[0x20];
8889 };
8890
8891 struct mlx5_ifc_create_mkey_in_bits {
8892         u8         opcode[0x10];
8893         u8         uid[0x10];
8894
8895         u8         reserved_at_20[0x10];
8896         u8         op_mod[0x10];
8897
8898         u8         reserved_at_40[0x20];
8899
8900         u8         pg_access[0x1];
8901         u8         mkey_umem_valid[0x1];
8902         u8         reserved_at_62[0x1e];
8903
8904         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8905
8906         u8         reserved_at_280[0x80];
8907
8908         u8         translations_octword_actual_size[0x20];
8909
8910         u8         reserved_at_320[0x560];
8911
8912         u8         klm_pas_mtt[][0x20];
8913 };
8914
8915 enum {
8916         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8917         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8918         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8919         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8920         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8921         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8922         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8923 };
8924
8925 struct mlx5_ifc_create_flow_table_out_bits {
8926         u8         status[0x8];
8927         u8         icm_address_63_40[0x18];
8928
8929         u8         syndrome[0x20];
8930
8931         u8         icm_address_39_32[0x8];
8932         u8         table_id[0x18];
8933
8934         u8         icm_address_31_0[0x20];
8935 };
8936
8937 struct mlx5_ifc_create_flow_table_in_bits {
8938         u8         opcode[0x10];
8939         u8         uid[0x10];
8940
8941         u8         reserved_at_20[0x10];
8942         u8         op_mod[0x10];
8943
8944         u8         other_vport[0x1];
8945         u8         reserved_at_41[0xf];
8946         u8         vport_number[0x10];
8947
8948         u8         reserved_at_60[0x20];
8949
8950         u8         table_type[0x8];
8951         u8         reserved_at_88[0x18];
8952
8953         u8         reserved_at_a0[0x20];
8954
8955         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8956 };
8957
8958 struct mlx5_ifc_create_flow_group_out_bits {
8959         u8         status[0x8];
8960         u8         reserved_at_8[0x18];
8961
8962         u8         syndrome[0x20];
8963
8964         u8         reserved_at_40[0x8];
8965         u8         group_id[0x18];
8966
8967         u8         reserved_at_60[0x20];
8968 };
8969
8970 enum {
8971         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8972         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8973 };
8974
8975 enum {
8976         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8977         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8978         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8979         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8980 };
8981
8982 struct mlx5_ifc_create_flow_group_in_bits {
8983         u8         opcode[0x10];
8984         u8         reserved_at_10[0x10];
8985
8986         u8         reserved_at_20[0x10];
8987         u8         op_mod[0x10];
8988
8989         u8         other_vport[0x1];
8990         u8         reserved_at_41[0xf];
8991         u8         vport_number[0x10];
8992
8993         u8         reserved_at_60[0x20];
8994
8995         u8         table_type[0x8];
8996         u8         reserved_at_88[0x4];
8997         u8         group_type[0x4];
8998         u8         reserved_at_90[0x10];
8999
9000         u8         reserved_at_a0[0x8];
9001         u8         table_id[0x18];
9002
9003         u8         source_eswitch_owner_vhca_id_valid[0x1];
9004
9005         u8         reserved_at_c1[0x1f];
9006
9007         u8         start_flow_index[0x20];
9008
9009         u8         reserved_at_100[0x20];
9010
9011         u8         end_flow_index[0x20];
9012
9013         u8         reserved_at_140[0x10];
9014         u8         match_definer_id[0x10];
9015
9016         u8         reserved_at_160[0x80];
9017
9018         u8         reserved_at_1e0[0x18];
9019         u8         match_criteria_enable[0x8];
9020
9021         struct mlx5_ifc_fte_match_param_bits match_criteria;
9022
9023         u8         reserved_at_1200[0xe00];
9024 };
9025
9026 struct mlx5_ifc_create_eq_out_bits {
9027         u8         status[0x8];
9028         u8         reserved_at_8[0x18];
9029
9030         u8         syndrome[0x20];
9031
9032         u8         reserved_at_40[0x18];
9033         u8         eq_number[0x8];
9034
9035         u8         reserved_at_60[0x20];
9036 };
9037
9038 struct mlx5_ifc_create_eq_in_bits {
9039         u8         opcode[0x10];
9040         u8         uid[0x10];
9041
9042         u8         reserved_at_20[0x10];
9043         u8         op_mod[0x10];
9044
9045         u8         reserved_at_40[0x40];
9046
9047         struct mlx5_ifc_eqc_bits eq_context_entry;
9048
9049         u8         reserved_at_280[0x40];
9050
9051         u8         event_bitmask[4][0x40];
9052
9053         u8         reserved_at_3c0[0x4c0];
9054
9055         u8         pas[][0x40];
9056 };
9057
9058 struct mlx5_ifc_create_dct_out_bits {
9059         u8         status[0x8];
9060         u8         reserved_at_8[0x18];
9061
9062         u8         syndrome[0x20];
9063
9064         u8         reserved_at_40[0x8];
9065         u8         dctn[0x18];
9066
9067         u8         ece[0x20];
9068 };
9069
9070 struct mlx5_ifc_create_dct_in_bits {
9071         u8         opcode[0x10];
9072         u8         uid[0x10];
9073
9074         u8         reserved_at_20[0x10];
9075         u8         op_mod[0x10];
9076
9077         u8         reserved_at_40[0x40];
9078
9079         struct mlx5_ifc_dctc_bits dct_context_entry;
9080
9081         u8         reserved_at_280[0x180];
9082 };
9083
9084 struct mlx5_ifc_create_cq_out_bits {
9085         u8         status[0x8];
9086         u8         reserved_at_8[0x18];
9087
9088         u8         syndrome[0x20];
9089
9090         u8         reserved_at_40[0x8];
9091         u8         cqn[0x18];
9092
9093         u8         reserved_at_60[0x20];
9094 };
9095
9096 struct mlx5_ifc_create_cq_in_bits {
9097         u8         opcode[0x10];
9098         u8         uid[0x10];
9099
9100         u8         reserved_at_20[0x10];
9101         u8         op_mod[0x10];
9102
9103         u8         reserved_at_40[0x40];
9104
9105         struct mlx5_ifc_cqc_bits cq_context;
9106
9107         u8         reserved_at_280[0x60];
9108
9109         u8         cq_umem_valid[0x1];
9110         u8         reserved_at_2e1[0x59f];
9111
9112         u8         pas[][0x40];
9113 };
9114
9115 struct mlx5_ifc_config_int_moderation_out_bits {
9116         u8         status[0x8];
9117         u8         reserved_at_8[0x18];
9118
9119         u8         syndrome[0x20];
9120
9121         u8         reserved_at_40[0x4];
9122         u8         min_delay[0xc];
9123         u8         int_vector[0x10];
9124
9125         u8         reserved_at_60[0x20];
9126 };
9127
9128 enum {
9129         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9130         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9131 };
9132
9133 struct mlx5_ifc_config_int_moderation_in_bits {
9134         u8         opcode[0x10];
9135         u8         reserved_at_10[0x10];
9136
9137         u8         reserved_at_20[0x10];
9138         u8         op_mod[0x10];
9139
9140         u8         reserved_at_40[0x4];
9141         u8         min_delay[0xc];
9142         u8         int_vector[0x10];
9143
9144         u8         reserved_at_60[0x20];
9145 };
9146
9147 struct mlx5_ifc_attach_to_mcg_out_bits {
9148         u8         status[0x8];
9149         u8         reserved_at_8[0x18];
9150
9151         u8         syndrome[0x20];
9152
9153         u8         reserved_at_40[0x40];
9154 };
9155
9156 struct mlx5_ifc_attach_to_mcg_in_bits {
9157         u8         opcode[0x10];
9158         u8         uid[0x10];
9159
9160         u8         reserved_at_20[0x10];
9161         u8         op_mod[0x10];
9162
9163         u8         reserved_at_40[0x8];
9164         u8         qpn[0x18];
9165
9166         u8         reserved_at_60[0x20];
9167
9168         u8         multicast_gid[16][0x8];
9169 };
9170
9171 struct mlx5_ifc_arm_xrq_out_bits {
9172         u8         status[0x8];
9173         u8         reserved_at_8[0x18];
9174
9175         u8         syndrome[0x20];
9176
9177         u8         reserved_at_40[0x40];
9178 };
9179
9180 struct mlx5_ifc_arm_xrq_in_bits {
9181         u8         opcode[0x10];
9182         u8         reserved_at_10[0x10];
9183
9184         u8         reserved_at_20[0x10];
9185         u8         op_mod[0x10];
9186
9187         u8         reserved_at_40[0x8];
9188         u8         xrqn[0x18];
9189
9190         u8         reserved_at_60[0x10];
9191         u8         lwm[0x10];
9192 };
9193
9194 struct mlx5_ifc_arm_xrc_srq_out_bits {
9195         u8         status[0x8];
9196         u8         reserved_at_8[0x18];
9197
9198         u8         syndrome[0x20];
9199
9200         u8         reserved_at_40[0x40];
9201 };
9202
9203 enum {
9204         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9205 };
9206
9207 struct mlx5_ifc_arm_xrc_srq_in_bits {
9208         u8         opcode[0x10];
9209         u8         uid[0x10];
9210
9211         u8         reserved_at_20[0x10];
9212         u8         op_mod[0x10];
9213
9214         u8         reserved_at_40[0x8];
9215         u8         xrc_srqn[0x18];
9216
9217         u8         reserved_at_60[0x10];
9218         u8         lwm[0x10];
9219 };
9220
9221 struct mlx5_ifc_arm_rq_out_bits {
9222         u8         status[0x8];
9223         u8         reserved_at_8[0x18];
9224
9225         u8         syndrome[0x20];
9226
9227         u8         reserved_at_40[0x40];
9228 };
9229
9230 enum {
9231         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9232         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9233 };
9234
9235 struct mlx5_ifc_arm_rq_in_bits {
9236         u8         opcode[0x10];
9237         u8         uid[0x10];
9238
9239         u8         reserved_at_20[0x10];
9240         u8         op_mod[0x10];
9241
9242         u8         reserved_at_40[0x8];
9243         u8         srq_number[0x18];
9244
9245         u8         reserved_at_60[0x10];
9246         u8         lwm[0x10];
9247 };
9248
9249 struct mlx5_ifc_arm_dct_out_bits {
9250         u8         status[0x8];
9251         u8         reserved_at_8[0x18];
9252
9253         u8         syndrome[0x20];
9254
9255         u8         reserved_at_40[0x40];
9256 };
9257
9258 struct mlx5_ifc_arm_dct_in_bits {
9259         u8         opcode[0x10];
9260         u8         reserved_at_10[0x10];
9261
9262         u8         reserved_at_20[0x10];
9263         u8         op_mod[0x10];
9264
9265         u8         reserved_at_40[0x8];
9266         u8         dct_number[0x18];
9267
9268         u8         reserved_at_60[0x20];
9269 };
9270
9271 struct mlx5_ifc_alloc_xrcd_out_bits {
9272         u8         status[0x8];
9273         u8         reserved_at_8[0x18];
9274
9275         u8         syndrome[0x20];
9276
9277         u8         reserved_at_40[0x8];
9278         u8         xrcd[0x18];
9279
9280         u8         reserved_at_60[0x20];
9281 };
9282
9283 struct mlx5_ifc_alloc_xrcd_in_bits {
9284         u8         opcode[0x10];
9285         u8         uid[0x10];
9286
9287         u8         reserved_at_20[0x10];
9288         u8         op_mod[0x10];
9289
9290         u8         reserved_at_40[0x40];
9291 };
9292
9293 struct mlx5_ifc_alloc_uar_out_bits {
9294         u8         status[0x8];
9295         u8         reserved_at_8[0x18];
9296
9297         u8         syndrome[0x20];
9298
9299         u8         reserved_at_40[0x8];
9300         u8         uar[0x18];
9301
9302         u8         reserved_at_60[0x20];
9303 };
9304
9305 struct mlx5_ifc_alloc_uar_in_bits {
9306         u8         opcode[0x10];
9307         u8         uid[0x10];
9308
9309         u8         reserved_at_20[0x10];
9310         u8         op_mod[0x10];
9311
9312         u8         reserved_at_40[0x40];
9313 };
9314
9315 struct mlx5_ifc_alloc_transport_domain_out_bits {
9316         u8         status[0x8];
9317         u8         reserved_at_8[0x18];
9318
9319         u8         syndrome[0x20];
9320
9321         u8         reserved_at_40[0x8];
9322         u8         transport_domain[0x18];
9323
9324         u8         reserved_at_60[0x20];
9325 };
9326
9327 struct mlx5_ifc_alloc_transport_domain_in_bits {
9328         u8         opcode[0x10];
9329         u8         uid[0x10];
9330
9331         u8         reserved_at_20[0x10];
9332         u8         op_mod[0x10];
9333
9334         u8         reserved_at_40[0x40];
9335 };
9336
9337 struct mlx5_ifc_alloc_q_counter_out_bits {
9338         u8         status[0x8];
9339         u8         reserved_at_8[0x18];
9340
9341         u8         syndrome[0x20];
9342
9343         u8         reserved_at_40[0x18];
9344         u8         counter_set_id[0x8];
9345
9346         u8         reserved_at_60[0x20];
9347 };
9348
9349 struct mlx5_ifc_alloc_q_counter_in_bits {
9350         u8         opcode[0x10];
9351         u8         uid[0x10];
9352
9353         u8         reserved_at_20[0x10];
9354         u8         op_mod[0x10];
9355
9356         u8         reserved_at_40[0x40];
9357 };
9358
9359 struct mlx5_ifc_alloc_pd_out_bits {
9360         u8         status[0x8];
9361         u8         reserved_at_8[0x18];
9362
9363         u8         syndrome[0x20];
9364
9365         u8         reserved_at_40[0x8];
9366         u8         pd[0x18];
9367
9368         u8         reserved_at_60[0x20];
9369 };
9370
9371 struct mlx5_ifc_alloc_pd_in_bits {
9372         u8         opcode[0x10];
9373         u8         uid[0x10];
9374
9375         u8         reserved_at_20[0x10];
9376         u8         op_mod[0x10];
9377
9378         u8         reserved_at_40[0x40];
9379 };
9380
9381 struct mlx5_ifc_alloc_flow_counter_out_bits {
9382         u8         status[0x8];
9383         u8         reserved_at_8[0x18];
9384
9385         u8         syndrome[0x20];
9386
9387         u8         flow_counter_id[0x20];
9388
9389         u8         reserved_at_60[0x20];
9390 };
9391
9392 struct mlx5_ifc_alloc_flow_counter_in_bits {
9393         u8         opcode[0x10];
9394         u8         reserved_at_10[0x10];
9395
9396         u8         reserved_at_20[0x10];
9397         u8         op_mod[0x10];
9398
9399         u8         reserved_at_40[0x33];
9400         u8         flow_counter_bulk_log_size[0x5];
9401         u8         flow_counter_bulk[0x8];
9402 };
9403
9404 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9405         u8         status[0x8];
9406         u8         reserved_at_8[0x18];
9407
9408         u8         syndrome[0x20];
9409
9410         u8         reserved_at_40[0x40];
9411 };
9412
9413 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9414         u8         opcode[0x10];
9415         u8         reserved_at_10[0x10];
9416
9417         u8         reserved_at_20[0x10];
9418         u8         op_mod[0x10];
9419
9420         u8         reserved_at_40[0x20];
9421
9422         u8         reserved_at_60[0x10];
9423         u8         vxlan_udp_port[0x10];
9424 };
9425
9426 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9427         u8         status[0x8];
9428         u8         reserved_at_8[0x18];
9429
9430         u8         syndrome[0x20];
9431
9432         u8         reserved_at_40[0x40];
9433 };
9434
9435 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9436         u8         rate_limit[0x20];
9437
9438         u8         burst_upper_bound[0x20];
9439
9440         u8         reserved_at_40[0x10];
9441         u8         typical_packet_size[0x10];
9442
9443         u8         reserved_at_60[0x120];
9444 };
9445
9446 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9447         u8         opcode[0x10];
9448         u8         uid[0x10];
9449
9450         u8         reserved_at_20[0x10];
9451         u8         op_mod[0x10];
9452
9453         u8         reserved_at_40[0x10];
9454         u8         rate_limit_index[0x10];
9455
9456         u8         reserved_at_60[0x20];
9457
9458         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9459 };
9460
9461 struct mlx5_ifc_access_register_out_bits {
9462         u8         status[0x8];
9463         u8         reserved_at_8[0x18];
9464
9465         u8         syndrome[0x20];
9466
9467         u8         reserved_at_40[0x40];
9468
9469         u8         register_data[][0x20];
9470 };
9471
9472 enum {
9473         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9474         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9475 };
9476
9477 struct mlx5_ifc_access_register_in_bits {
9478         u8         opcode[0x10];
9479         u8         reserved_at_10[0x10];
9480
9481         u8         reserved_at_20[0x10];
9482         u8         op_mod[0x10];
9483
9484         u8         reserved_at_40[0x10];
9485         u8         register_id[0x10];
9486
9487         u8         argument[0x20];
9488
9489         u8         register_data[][0x20];
9490 };
9491
9492 struct mlx5_ifc_sltp_reg_bits {
9493         u8         status[0x4];
9494         u8         version[0x4];
9495         u8         local_port[0x8];
9496         u8         pnat[0x2];
9497         u8         reserved_at_12[0x2];
9498         u8         lane[0x4];
9499         u8         reserved_at_18[0x8];
9500
9501         u8         reserved_at_20[0x20];
9502
9503         u8         reserved_at_40[0x7];
9504         u8         polarity[0x1];
9505         u8         ob_tap0[0x8];
9506         u8         ob_tap1[0x8];
9507         u8         ob_tap2[0x8];
9508
9509         u8         reserved_at_60[0xc];
9510         u8         ob_preemp_mode[0x4];
9511         u8         ob_reg[0x8];
9512         u8         ob_bias[0x8];
9513
9514         u8         reserved_at_80[0x20];
9515 };
9516
9517 struct mlx5_ifc_slrg_reg_bits {
9518         u8         status[0x4];
9519         u8         version[0x4];
9520         u8         local_port[0x8];
9521         u8         pnat[0x2];
9522         u8         reserved_at_12[0x2];
9523         u8         lane[0x4];
9524         u8         reserved_at_18[0x8];
9525
9526         u8         time_to_link_up[0x10];
9527         u8         reserved_at_30[0xc];
9528         u8         grade_lane_speed[0x4];
9529
9530         u8         grade_version[0x8];
9531         u8         grade[0x18];
9532
9533         u8         reserved_at_60[0x4];
9534         u8         height_grade_type[0x4];
9535         u8         height_grade[0x18];
9536
9537         u8         height_dz[0x10];
9538         u8         height_dv[0x10];
9539
9540         u8         reserved_at_a0[0x10];
9541         u8         height_sigma[0x10];
9542
9543         u8         reserved_at_c0[0x20];
9544
9545         u8         reserved_at_e0[0x4];
9546         u8         phase_grade_type[0x4];
9547         u8         phase_grade[0x18];
9548
9549         u8         reserved_at_100[0x8];
9550         u8         phase_eo_pos[0x8];
9551         u8         reserved_at_110[0x8];
9552         u8         phase_eo_neg[0x8];
9553
9554         u8         ffe_set_tested[0x10];
9555         u8         test_errors_per_lane[0x10];
9556 };
9557
9558 struct mlx5_ifc_pvlc_reg_bits {
9559         u8         reserved_at_0[0x8];
9560         u8         local_port[0x8];
9561         u8         reserved_at_10[0x10];
9562
9563         u8         reserved_at_20[0x1c];
9564         u8         vl_hw_cap[0x4];
9565
9566         u8         reserved_at_40[0x1c];
9567         u8         vl_admin[0x4];
9568
9569         u8         reserved_at_60[0x1c];
9570         u8         vl_operational[0x4];
9571 };
9572
9573 struct mlx5_ifc_pude_reg_bits {
9574         u8         swid[0x8];
9575         u8         local_port[0x8];
9576         u8         reserved_at_10[0x4];
9577         u8         admin_status[0x4];
9578         u8         reserved_at_18[0x4];
9579         u8         oper_status[0x4];
9580
9581         u8         reserved_at_20[0x60];
9582 };
9583
9584 struct mlx5_ifc_ptys_reg_bits {
9585         u8         reserved_at_0[0x1];
9586         u8         an_disable_admin[0x1];
9587         u8         an_disable_cap[0x1];
9588         u8         reserved_at_3[0x5];
9589         u8         local_port[0x8];
9590         u8         reserved_at_10[0xd];
9591         u8         proto_mask[0x3];
9592
9593         u8         an_status[0x4];
9594         u8         reserved_at_24[0xc];
9595         u8         data_rate_oper[0x10];
9596
9597         u8         ext_eth_proto_capability[0x20];
9598
9599         u8         eth_proto_capability[0x20];
9600
9601         u8         ib_link_width_capability[0x10];
9602         u8         ib_proto_capability[0x10];
9603
9604         u8         ext_eth_proto_admin[0x20];
9605
9606         u8         eth_proto_admin[0x20];
9607
9608         u8         ib_link_width_admin[0x10];
9609         u8         ib_proto_admin[0x10];
9610
9611         u8         ext_eth_proto_oper[0x20];
9612
9613         u8         eth_proto_oper[0x20];
9614
9615         u8         ib_link_width_oper[0x10];
9616         u8         ib_proto_oper[0x10];
9617
9618         u8         reserved_at_160[0x1c];
9619         u8         connector_type[0x4];
9620
9621         u8         eth_proto_lp_advertise[0x20];
9622
9623         u8         reserved_at_1a0[0x60];
9624 };
9625
9626 struct mlx5_ifc_mlcr_reg_bits {
9627         u8         reserved_at_0[0x8];
9628         u8         local_port[0x8];
9629         u8         reserved_at_10[0x20];
9630
9631         u8         beacon_duration[0x10];
9632         u8         reserved_at_40[0x10];
9633
9634         u8         beacon_remain[0x10];
9635 };
9636
9637 struct mlx5_ifc_ptas_reg_bits {
9638         u8         reserved_at_0[0x20];
9639
9640         u8         algorithm_options[0x10];
9641         u8         reserved_at_30[0x4];
9642         u8         repetitions_mode[0x4];
9643         u8         num_of_repetitions[0x8];
9644
9645         u8         grade_version[0x8];
9646         u8         height_grade_type[0x4];
9647         u8         phase_grade_type[0x4];
9648         u8         height_grade_weight[0x8];
9649         u8         phase_grade_weight[0x8];
9650
9651         u8         gisim_measure_bits[0x10];
9652         u8         adaptive_tap_measure_bits[0x10];
9653
9654         u8         ber_bath_high_error_threshold[0x10];
9655         u8         ber_bath_mid_error_threshold[0x10];
9656
9657         u8         ber_bath_low_error_threshold[0x10];
9658         u8         one_ratio_high_threshold[0x10];
9659
9660         u8         one_ratio_high_mid_threshold[0x10];
9661         u8         one_ratio_low_mid_threshold[0x10];
9662
9663         u8         one_ratio_low_threshold[0x10];
9664         u8         ndeo_error_threshold[0x10];
9665
9666         u8         mixer_offset_step_size[0x10];
9667         u8         reserved_at_110[0x8];
9668         u8         mix90_phase_for_voltage_bath[0x8];
9669
9670         u8         mixer_offset_start[0x10];
9671         u8         mixer_offset_end[0x10];
9672
9673         u8         reserved_at_140[0x15];
9674         u8         ber_test_time[0xb];
9675 };
9676
9677 struct mlx5_ifc_pspa_reg_bits {
9678         u8         swid[0x8];
9679         u8         local_port[0x8];
9680         u8         sub_port[0x8];
9681         u8         reserved_at_18[0x8];
9682
9683         u8         reserved_at_20[0x20];
9684 };
9685
9686 struct mlx5_ifc_pqdr_reg_bits {
9687         u8         reserved_at_0[0x8];
9688         u8         local_port[0x8];
9689         u8         reserved_at_10[0x5];
9690         u8         prio[0x3];
9691         u8         reserved_at_18[0x6];
9692         u8         mode[0x2];
9693
9694         u8         reserved_at_20[0x20];
9695
9696         u8         reserved_at_40[0x10];
9697         u8         min_threshold[0x10];
9698
9699         u8         reserved_at_60[0x10];
9700         u8         max_threshold[0x10];
9701
9702         u8         reserved_at_80[0x10];
9703         u8         mark_probability_denominator[0x10];
9704
9705         u8         reserved_at_a0[0x60];
9706 };
9707
9708 struct mlx5_ifc_ppsc_reg_bits {
9709         u8         reserved_at_0[0x8];
9710         u8         local_port[0x8];
9711         u8         reserved_at_10[0x10];
9712
9713         u8         reserved_at_20[0x60];
9714
9715         u8         reserved_at_80[0x1c];
9716         u8         wrps_admin[0x4];
9717
9718         u8         reserved_at_a0[0x1c];
9719         u8         wrps_status[0x4];
9720
9721         u8         reserved_at_c0[0x8];
9722         u8         up_threshold[0x8];
9723         u8         reserved_at_d0[0x8];
9724         u8         down_threshold[0x8];
9725
9726         u8         reserved_at_e0[0x20];
9727
9728         u8         reserved_at_100[0x1c];
9729         u8         srps_admin[0x4];
9730
9731         u8         reserved_at_120[0x1c];
9732         u8         srps_status[0x4];
9733
9734         u8         reserved_at_140[0x40];
9735 };
9736
9737 struct mlx5_ifc_pplr_reg_bits {
9738         u8         reserved_at_0[0x8];
9739         u8         local_port[0x8];
9740         u8         reserved_at_10[0x10];
9741
9742         u8         reserved_at_20[0x8];
9743         u8         lb_cap[0x8];
9744         u8         reserved_at_30[0x8];
9745         u8         lb_en[0x8];
9746 };
9747
9748 struct mlx5_ifc_pplm_reg_bits {
9749         u8         reserved_at_0[0x8];
9750         u8         local_port[0x8];
9751         u8         reserved_at_10[0x10];
9752
9753         u8         reserved_at_20[0x20];
9754
9755         u8         port_profile_mode[0x8];
9756         u8         static_port_profile[0x8];
9757         u8         active_port_profile[0x8];
9758         u8         reserved_at_58[0x8];
9759
9760         u8         retransmission_active[0x8];
9761         u8         fec_mode_active[0x18];
9762
9763         u8         rs_fec_correction_bypass_cap[0x4];
9764         u8         reserved_at_84[0x8];
9765         u8         fec_override_cap_56g[0x4];
9766         u8         fec_override_cap_100g[0x4];
9767         u8         fec_override_cap_50g[0x4];
9768         u8         fec_override_cap_25g[0x4];
9769         u8         fec_override_cap_10g_40g[0x4];
9770
9771         u8         rs_fec_correction_bypass_admin[0x4];
9772         u8         reserved_at_a4[0x8];
9773         u8         fec_override_admin_56g[0x4];
9774         u8         fec_override_admin_100g[0x4];
9775         u8         fec_override_admin_50g[0x4];
9776         u8         fec_override_admin_25g[0x4];
9777         u8         fec_override_admin_10g_40g[0x4];
9778
9779         u8         fec_override_cap_400g_8x[0x10];
9780         u8         fec_override_cap_200g_4x[0x10];
9781
9782         u8         fec_override_cap_100g_2x[0x10];
9783         u8         fec_override_cap_50g_1x[0x10];
9784
9785         u8         fec_override_admin_400g_8x[0x10];
9786         u8         fec_override_admin_200g_4x[0x10];
9787
9788         u8         fec_override_admin_100g_2x[0x10];
9789         u8         fec_override_admin_50g_1x[0x10];
9790
9791         u8         reserved_at_140[0x140];
9792 };
9793
9794 struct mlx5_ifc_ppcnt_reg_bits {
9795         u8         swid[0x8];
9796         u8         local_port[0x8];
9797         u8         pnat[0x2];
9798         u8         reserved_at_12[0x8];
9799         u8         grp[0x6];
9800
9801         u8         clr[0x1];
9802         u8         reserved_at_21[0x1c];
9803         u8         prio_tc[0x3];
9804
9805         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9806 };
9807
9808 struct mlx5_ifc_mpein_reg_bits {
9809         u8         reserved_at_0[0x2];
9810         u8         depth[0x6];
9811         u8         pcie_index[0x8];
9812         u8         node[0x8];
9813         u8         reserved_at_18[0x8];
9814
9815         u8         capability_mask[0x20];
9816
9817         u8         reserved_at_40[0x8];
9818         u8         link_width_enabled[0x8];
9819         u8         link_speed_enabled[0x10];
9820
9821         u8         lane0_physical_position[0x8];
9822         u8         link_width_active[0x8];
9823         u8         link_speed_active[0x10];
9824
9825         u8         num_of_pfs[0x10];
9826         u8         num_of_vfs[0x10];
9827
9828         u8         bdf0[0x10];
9829         u8         reserved_at_b0[0x10];
9830
9831         u8         max_read_request_size[0x4];
9832         u8         max_payload_size[0x4];
9833         u8         reserved_at_c8[0x5];
9834         u8         pwr_status[0x3];
9835         u8         port_type[0x4];
9836         u8         reserved_at_d4[0xb];
9837         u8         lane_reversal[0x1];
9838
9839         u8         reserved_at_e0[0x14];
9840         u8         pci_power[0xc];
9841
9842         u8         reserved_at_100[0x20];
9843
9844         u8         device_status[0x10];
9845         u8         port_state[0x8];
9846         u8         reserved_at_138[0x8];
9847
9848         u8         reserved_at_140[0x10];
9849         u8         receiver_detect_result[0x10];
9850
9851         u8         reserved_at_160[0x20];
9852 };
9853
9854 struct mlx5_ifc_mpcnt_reg_bits {
9855         u8         reserved_at_0[0x8];
9856         u8         pcie_index[0x8];
9857         u8         reserved_at_10[0xa];
9858         u8         grp[0x6];
9859
9860         u8         clr[0x1];
9861         u8         reserved_at_21[0x1f];
9862
9863         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9864 };
9865
9866 struct mlx5_ifc_ppad_reg_bits {
9867         u8         reserved_at_0[0x3];
9868         u8         single_mac[0x1];
9869         u8         reserved_at_4[0x4];
9870         u8         local_port[0x8];
9871         u8         mac_47_32[0x10];
9872
9873         u8         mac_31_0[0x20];
9874
9875         u8         reserved_at_40[0x40];
9876 };
9877
9878 struct mlx5_ifc_pmtu_reg_bits {
9879         u8         reserved_at_0[0x8];
9880         u8         local_port[0x8];
9881         u8         reserved_at_10[0x10];
9882
9883         u8         max_mtu[0x10];
9884         u8         reserved_at_30[0x10];
9885
9886         u8         admin_mtu[0x10];
9887         u8         reserved_at_50[0x10];
9888
9889         u8         oper_mtu[0x10];
9890         u8         reserved_at_70[0x10];
9891 };
9892
9893 struct mlx5_ifc_pmpr_reg_bits {
9894         u8         reserved_at_0[0x8];
9895         u8         module[0x8];
9896         u8         reserved_at_10[0x10];
9897
9898         u8         reserved_at_20[0x18];
9899         u8         attenuation_5g[0x8];
9900
9901         u8         reserved_at_40[0x18];
9902         u8         attenuation_7g[0x8];
9903
9904         u8         reserved_at_60[0x18];
9905         u8         attenuation_12g[0x8];
9906 };
9907
9908 struct mlx5_ifc_pmpe_reg_bits {
9909         u8         reserved_at_0[0x8];
9910         u8         module[0x8];
9911         u8         reserved_at_10[0xc];
9912         u8         module_status[0x4];
9913
9914         u8         reserved_at_20[0x60];
9915 };
9916
9917 struct mlx5_ifc_pmpc_reg_bits {
9918         u8         module_state_updated[32][0x8];
9919 };
9920
9921 struct mlx5_ifc_pmlpn_reg_bits {
9922         u8         reserved_at_0[0x4];
9923         u8         mlpn_status[0x4];
9924         u8         local_port[0x8];
9925         u8         reserved_at_10[0x10];
9926
9927         u8         e[0x1];
9928         u8         reserved_at_21[0x1f];
9929 };
9930
9931 struct mlx5_ifc_pmlp_reg_bits {
9932         u8         rxtx[0x1];
9933         u8         reserved_at_1[0x7];
9934         u8         local_port[0x8];
9935         u8         reserved_at_10[0x8];
9936         u8         width[0x8];
9937
9938         u8         lane0_module_mapping[0x20];
9939
9940         u8         lane1_module_mapping[0x20];
9941
9942         u8         lane2_module_mapping[0x20];
9943
9944         u8         lane3_module_mapping[0x20];
9945
9946         u8         reserved_at_a0[0x160];
9947 };
9948
9949 struct mlx5_ifc_pmaos_reg_bits {
9950         u8         reserved_at_0[0x8];
9951         u8         module[0x8];
9952         u8         reserved_at_10[0x4];
9953         u8         admin_status[0x4];
9954         u8         reserved_at_18[0x4];
9955         u8         oper_status[0x4];
9956
9957         u8         ase[0x1];
9958         u8         ee[0x1];
9959         u8         reserved_at_22[0x1c];
9960         u8         e[0x2];
9961
9962         u8         reserved_at_40[0x40];
9963 };
9964
9965 struct mlx5_ifc_plpc_reg_bits {
9966         u8         reserved_at_0[0x4];
9967         u8         profile_id[0xc];
9968         u8         reserved_at_10[0x4];
9969         u8         proto_mask[0x4];
9970         u8         reserved_at_18[0x8];
9971
9972         u8         reserved_at_20[0x10];
9973         u8         lane_speed[0x10];
9974
9975         u8         reserved_at_40[0x17];
9976         u8         lpbf[0x1];
9977         u8         fec_mode_policy[0x8];
9978
9979         u8         retransmission_capability[0x8];
9980         u8         fec_mode_capability[0x18];
9981
9982         u8         retransmission_support_admin[0x8];
9983         u8         fec_mode_support_admin[0x18];
9984
9985         u8         retransmission_request_admin[0x8];
9986         u8         fec_mode_request_admin[0x18];
9987
9988         u8         reserved_at_c0[0x80];
9989 };
9990
9991 struct mlx5_ifc_plib_reg_bits {
9992         u8         reserved_at_0[0x8];
9993         u8         local_port[0x8];
9994         u8         reserved_at_10[0x8];
9995         u8         ib_port[0x8];
9996
9997         u8         reserved_at_20[0x60];
9998 };
9999
10000 struct mlx5_ifc_plbf_reg_bits {
10001         u8         reserved_at_0[0x8];
10002         u8         local_port[0x8];
10003         u8         reserved_at_10[0xd];
10004         u8         lbf_mode[0x3];
10005
10006         u8         reserved_at_20[0x20];
10007 };
10008
10009 struct mlx5_ifc_pipg_reg_bits {
10010         u8         reserved_at_0[0x8];
10011         u8         local_port[0x8];
10012         u8         reserved_at_10[0x10];
10013
10014         u8         dic[0x1];
10015         u8         reserved_at_21[0x19];
10016         u8         ipg[0x4];
10017         u8         reserved_at_3e[0x2];
10018 };
10019
10020 struct mlx5_ifc_pifr_reg_bits {
10021         u8         reserved_at_0[0x8];
10022         u8         local_port[0x8];
10023         u8         reserved_at_10[0x10];
10024
10025         u8         reserved_at_20[0xe0];
10026
10027         u8         port_filter[8][0x20];
10028
10029         u8         port_filter_update_en[8][0x20];
10030 };
10031
10032 struct mlx5_ifc_pfcc_reg_bits {
10033         u8         reserved_at_0[0x8];
10034         u8         local_port[0x8];
10035         u8         reserved_at_10[0xb];
10036         u8         ppan_mask_n[0x1];
10037         u8         minor_stall_mask[0x1];
10038         u8         critical_stall_mask[0x1];
10039         u8         reserved_at_1e[0x2];
10040
10041         u8         ppan[0x4];
10042         u8         reserved_at_24[0x4];
10043         u8         prio_mask_tx[0x8];
10044         u8         reserved_at_30[0x8];
10045         u8         prio_mask_rx[0x8];
10046
10047         u8         pptx[0x1];
10048         u8         aptx[0x1];
10049         u8         pptx_mask_n[0x1];
10050         u8         reserved_at_43[0x5];
10051         u8         pfctx[0x8];
10052         u8         reserved_at_50[0x10];
10053
10054         u8         pprx[0x1];
10055         u8         aprx[0x1];
10056         u8         pprx_mask_n[0x1];
10057         u8         reserved_at_63[0x5];
10058         u8         pfcrx[0x8];
10059         u8         reserved_at_70[0x10];
10060
10061         u8         device_stall_minor_watermark[0x10];
10062         u8         device_stall_critical_watermark[0x10];
10063
10064         u8         reserved_at_a0[0x60];
10065 };
10066
10067 struct mlx5_ifc_pelc_reg_bits {
10068         u8         op[0x4];
10069         u8         reserved_at_4[0x4];
10070         u8         local_port[0x8];
10071         u8         reserved_at_10[0x10];
10072
10073         u8         op_admin[0x8];
10074         u8         op_capability[0x8];
10075         u8         op_request[0x8];
10076         u8         op_active[0x8];
10077
10078         u8         admin[0x40];
10079
10080         u8         capability[0x40];
10081
10082         u8         request[0x40];
10083
10084         u8         active[0x40];
10085
10086         u8         reserved_at_140[0x80];
10087 };
10088
10089 struct mlx5_ifc_peir_reg_bits {
10090         u8         reserved_at_0[0x8];
10091         u8         local_port[0x8];
10092         u8         reserved_at_10[0x10];
10093
10094         u8         reserved_at_20[0xc];
10095         u8         error_count[0x4];
10096         u8         reserved_at_30[0x10];
10097
10098         u8         reserved_at_40[0xc];
10099         u8         lane[0x4];
10100         u8         reserved_at_50[0x8];
10101         u8         error_type[0x8];
10102 };
10103
10104 struct mlx5_ifc_mpegc_reg_bits {
10105         u8         reserved_at_0[0x30];
10106         u8         field_select[0x10];
10107
10108         u8         tx_overflow_sense[0x1];
10109         u8         mark_cqe[0x1];
10110         u8         mark_cnp[0x1];
10111         u8         reserved_at_43[0x1b];
10112         u8         tx_lossy_overflow_oper[0x2];
10113
10114         u8         reserved_at_60[0x100];
10115 };
10116
10117 struct mlx5_ifc_mpir_reg_bits {
10118         u8         sdm[0x1];
10119         u8         reserved_at_1[0x1b];
10120         u8         host_buses[0x4];
10121
10122         u8         reserved_at_20[0x20];
10123
10124         u8         local_port[0x8];
10125         u8         reserved_at_28[0x15];
10126         u8         sd_group[0x3];
10127
10128         u8         reserved_at_60[0x20];
10129 };
10130
10131 enum {
10132         MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10133         MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10134 };
10135
10136 enum {
10137         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10138         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10139         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10140 };
10141
10142 struct mlx5_ifc_mtutc_reg_bits {
10143         u8         reserved_at_0[0x5];
10144         u8         freq_adj_units[0x3];
10145         u8         reserved_at_8[0x3];
10146         u8         log_max_freq_adjustment[0x5];
10147
10148         u8         reserved_at_10[0xc];
10149         u8         operation[0x4];
10150
10151         u8         freq_adjustment[0x20];
10152
10153         u8         reserved_at_40[0x40];
10154
10155         u8         utc_sec[0x20];
10156
10157         u8         reserved_at_a0[0x2];
10158         u8         utc_nsec[0x1e];
10159
10160         u8         time_adjustment[0x20];
10161 };
10162
10163 struct mlx5_ifc_pcam_enhanced_features_bits {
10164         u8         reserved_at_0[0x68];
10165         u8         fec_50G_per_lane_in_pplm[0x1];
10166         u8         reserved_at_69[0x4];
10167         u8         rx_icrc_encapsulated_counter[0x1];
10168         u8         reserved_at_6e[0x4];
10169         u8         ptys_extended_ethernet[0x1];
10170         u8         reserved_at_73[0x3];
10171         u8         pfcc_mask[0x1];
10172         u8         reserved_at_77[0x3];
10173         u8         per_lane_error_counters[0x1];
10174         u8         rx_buffer_fullness_counters[0x1];
10175         u8         ptys_connector_type[0x1];
10176         u8         reserved_at_7d[0x1];
10177         u8         ppcnt_discard_group[0x1];
10178         u8         ppcnt_statistical_group[0x1];
10179 };
10180
10181 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10182         u8         port_access_reg_cap_mask_127_to_96[0x20];
10183         u8         port_access_reg_cap_mask_95_to_64[0x20];
10184
10185         u8         port_access_reg_cap_mask_63_to_36[0x1c];
10186         u8         pplm[0x1];
10187         u8         port_access_reg_cap_mask_34_to_32[0x3];
10188
10189         u8         port_access_reg_cap_mask_31_to_13[0x13];
10190         u8         pbmc[0x1];
10191         u8         pptb[0x1];
10192         u8         port_access_reg_cap_mask_10_to_09[0x2];
10193         u8         ppcnt[0x1];
10194         u8         port_access_reg_cap_mask_07_to_00[0x8];
10195 };
10196
10197 struct mlx5_ifc_pcam_reg_bits {
10198         u8         reserved_at_0[0x8];
10199         u8         feature_group[0x8];
10200         u8         reserved_at_10[0x8];
10201         u8         access_reg_group[0x8];
10202
10203         u8         reserved_at_20[0x20];
10204
10205         union {
10206                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10207                 u8         reserved_at_0[0x80];
10208         } port_access_reg_cap_mask;
10209
10210         u8         reserved_at_c0[0x80];
10211
10212         union {
10213                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10214                 u8         reserved_at_0[0x80];
10215         } feature_cap_mask;
10216
10217         u8         reserved_at_1c0[0xc0];
10218 };
10219
10220 struct mlx5_ifc_mcam_enhanced_features_bits {
10221         u8         reserved_at_0[0x50];
10222         u8         mtutc_freq_adj_units[0x1];
10223         u8         mtutc_time_adjustment_extended_range[0x1];
10224         u8         reserved_at_52[0xb];
10225         u8         mcia_32dwords[0x1];
10226         u8         out_pulse_duration_ns[0x1];
10227         u8         npps_period[0x1];
10228         u8         reserved_at_60[0xa];
10229         u8         reset_state[0x1];
10230         u8         ptpcyc2realtime_modify[0x1];
10231         u8         reserved_at_6c[0x2];
10232         u8         pci_status_and_power[0x1];
10233         u8         reserved_at_6f[0x5];
10234         u8         mark_tx_action_cnp[0x1];
10235         u8         mark_tx_action_cqe[0x1];
10236         u8         dynamic_tx_overflow[0x1];
10237         u8         reserved_at_77[0x4];
10238         u8         pcie_outbound_stalled[0x1];
10239         u8         tx_overflow_buffer_pkt[0x1];
10240         u8         mtpps_enh_out_per_adj[0x1];
10241         u8         mtpps_fs[0x1];
10242         u8         pcie_performance_group[0x1];
10243 };
10244
10245 struct mlx5_ifc_mcam_access_reg_bits {
10246         u8         reserved_at_0[0x1c];
10247         u8         mcda[0x1];
10248         u8         mcc[0x1];
10249         u8         mcqi[0x1];
10250         u8         mcqs[0x1];
10251
10252         u8         regs_95_to_87[0x9];
10253         u8         mpegc[0x1];
10254         u8         mtutc[0x1];
10255         u8         regs_84_to_68[0x11];
10256         u8         tracer_registers[0x4];
10257
10258         u8         regs_63_to_46[0x12];
10259         u8         mrtc[0x1];
10260         u8         regs_44_to_32[0xd];
10261
10262         u8         regs_31_to_10[0x16];
10263         u8         mtmp[0x1];
10264         u8         regs_8_to_0[0x9];
10265 };
10266
10267 struct mlx5_ifc_mcam_access_reg_bits1 {
10268         u8         regs_127_to_96[0x20];
10269
10270         u8         regs_95_to_64[0x20];
10271
10272         u8         regs_63_to_32[0x20];
10273
10274         u8         regs_31_to_0[0x20];
10275 };
10276
10277 struct mlx5_ifc_mcam_access_reg_bits2 {
10278         u8         regs_127_to_99[0x1d];
10279         u8         mirc[0x1];
10280         u8         regs_97_to_96[0x2];
10281
10282         u8         regs_95_to_87[0x09];
10283         u8         synce_registers[0x2];
10284         u8         regs_84_to_64[0x15];
10285
10286         u8         regs_63_to_32[0x20];
10287
10288         u8         regs_31_to_0[0x20];
10289 };
10290
10291 struct mlx5_ifc_mcam_reg_bits {
10292         u8         reserved_at_0[0x8];
10293         u8         feature_group[0x8];
10294         u8         reserved_at_10[0x8];
10295         u8         access_reg_group[0x8];
10296
10297         u8         reserved_at_20[0x20];
10298
10299         union {
10300                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
10301                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10302                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10303                 u8         reserved_at_0[0x80];
10304         } mng_access_reg_cap_mask;
10305
10306         u8         reserved_at_c0[0x80];
10307
10308         union {
10309                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10310                 u8         reserved_at_0[0x80];
10311         } mng_feature_cap_mask;
10312
10313         u8         reserved_at_1c0[0x80];
10314 };
10315
10316 struct mlx5_ifc_qcam_access_reg_cap_mask {
10317         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10318         u8         qpdpm[0x1];
10319         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10320         u8         qdpm[0x1];
10321         u8         qpts[0x1];
10322         u8         qcap[0x1];
10323         u8         qcam_access_reg_cap_mask_0[0x1];
10324 };
10325
10326 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10327         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10328         u8         qpts_trust_both[0x1];
10329 };
10330
10331 struct mlx5_ifc_qcam_reg_bits {
10332         u8         reserved_at_0[0x8];
10333         u8         feature_group[0x8];
10334         u8         reserved_at_10[0x8];
10335         u8         access_reg_group[0x8];
10336         u8         reserved_at_20[0x20];
10337
10338         union {
10339                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10340                 u8  reserved_at_0[0x80];
10341         } qos_access_reg_cap_mask;
10342
10343         u8         reserved_at_c0[0x80];
10344
10345         union {
10346                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10347                 u8  reserved_at_0[0x80];
10348         } qos_feature_cap_mask;
10349
10350         u8         reserved_at_1c0[0x80];
10351 };
10352
10353 struct mlx5_ifc_core_dump_reg_bits {
10354         u8         reserved_at_0[0x18];
10355         u8         core_dump_type[0x8];
10356
10357         u8         reserved_at_20[0x30];
10358         u8         vhca_id[0x10];
10359
10360         u8         reserved_at_60[0x8];
10361         u8         qpn[0x18];
10362         u8         reserved_at_80[0x180];
10363 };
10364
10365 struct mlx5_ifc_pcap_reg_bits {
10366         u8         reserved_at_0[0x8];
10367         u8         local_port[0x8];
10368         u8         reserved_at_10[0x10];
10369
10370         u8         port_capability_mask[4][0x20];
10371 };
10372
10373 struct mlx5_ifc_paos_reg_bits {
10374         u8         swid[0x8];
10375         u8         local_port[0x8];
10376         u8         reserved_at_10[0x4];
10377         u8         admin_status[0x4];
10378         u8         reserved_at_18[0x4];
10379         u8         oper_status[0x4];
10380
10381         u8         ase[0x1];
10382         u8         ee[0x1];
10383         u8         reserved_at_22[0x1c];
10384         u8         e[0x2];
10385
10386         u8         reserved_at_40[0x40];
10387 };
10388
10389 struct mlx5_ifc_pamp_reg_bits {
10390         u8         reserved_at_0[0x8];
10391         u8         opamp_group[0x8];
10392         u8         reserved_at_10[0xc];
10393         u8         opamp_group_type[0x4];
10394
10395         u8         start_index[0x10];
10396         u8         reserved_at_30[0x4];
10397         u8         num_of_indices[0xc];
10398
10399         u8         index_data[18][0x10];
10400 };
10401
10402 struct mlx5_ifc_pcmr_reg_bits {
10403         u8         reserved_at_0[0x8];
10404         u8         local_port[0x8];
10405         u8         reserved_at_10[0x10];
10406
10407         u8         entropy_force_cap[0x1];
10408         u8         entropy_calc_cap[0x1];
10409         u8         entropy_gre_calc_cap[0x1];
10410         u8         reserved_at_23[0xf];
10411         u8         rx_ts_over_crc_cap[0x1];
10412         u8         reserved_at_33[0xb];
10413         u8         fcs_cap[0x1];
10414         u8         reserved_at_3f[0x1];
10415
10416         u8         entropy_force[0x1];
10417         u8         entropy_calc[0x1];
10418         u8         entropy_gre_calc[0x1];
10419         u8         reserved_at_43[0xf];
10420         u8         rx_ts_over_crc[0x1];
10421         u8         reserved_at_53[0xb];
10422         u8         fcs_chk[0x1];
10423         u8         reserved_at_5f[0x1];
10424 };
10425
10426 struct mlx5_ifc_lane_2_module_mapping_bits {
10427         u8         reserved_at_0[0x4];
10428         u8         rx_lane[0x4];
10429         u8         reserved_at_8[0x4];
10430         u8         tx_lane[0x4];
10431         u8         reserved_at_10[0x8];
10432         u8         module[0x8];
10433 };
10434
10435 struct mlx5_ifc_bufferx_reg_bits {
10436         u8         reserved_at_0[0x6];
10437         u8         lossy[0x1];
10438         u8         epsb[0x1];
10439         u8         reserved_at_8[0x8];
10440         u8         size[0x10];
10441
10442         u8         xoff_threshold[0x10];
10443         u8         xon_threshold[0x10];
10444 };
10445
10446 struct mlx5_ifc_set_node_in_bits {
10447         u8         node_description[64][0x8];
10448 };
10449
10450 struct mlx5_ifc_register_power_settings_bits {
10451         u8         reserved_at_0[0x18];
10452         u8         power_settings_level[0x8];
10453
10454         u8         reserved_at_20[0x60];
10455 };
10456
10457 struct mlx5_ifc_register_host_endianness_bits {
10458         u8         he[0x1];
10459         u8         reserved_at_1[0x1f];
10460
10461         u8         reserved_at_20[0x60];
10462 };
10463
10464 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10465         u8         reserved_at_0[0x20];
10466
10467         u8         mkey[0x20];
10468
10469         u8         addressh_63_32[0x20];
10470
10471         u8         addressl_31_0[0x20];
10472 };
10473
10474 struct mlx5_ifc_ud_adrs_vector_bits {
10475         u8         dc_key[0x40];
10476
10477         u8         ext[0x1];
10478         u8         reserved_at_41[0x7];
10479         u8         destination_qp_dct[0x18];
10480
10481         u8         static_rate[0x4];
10482         u8         sl_eth_prio[0x4];
10483         u8         fl[0x1];
10484         u8         mlid[0x7];
10485         u8         rlid_udp_sport[0x10];
10486
10487         u8         reserved_at_80[0x20];
10488
10489         u8         rmac_47_16[0x20];
10490
10491         u8         rmac_15_0[0x10];
10492         u8         tclass[0x8];
10493         u8         hop_limit[0x8];
10494
10495         u8         reserved_at_e0[0x1];
10496         u8         grh[0x1];
10497         u8         reserved_at_e2[0x2];
10498         u8         src_addr_index[0x8];
10499         u8         flow_label[0x14];
10500
10501         u8         rgid_rip[16][0x8];
10502 };
10503
10504 struct mlx5_ifc_pages_req_event_bits {
10505         u8         reserved_at_0[0x10];
10506         u8         function_id[0x10];
10507
10508         u8         num_pages[0x20];
10509
10510         u8         reserved_at_40[0xa0];
10511 };
10512
10513 struct mlx5_ifc_eqe_bits {
10514         u8         reserved_at_0[0x8];
10515         u8         event_type[0x8];
10516         u8         reserved_at_10[0x8];
10517         u8         event_sub_type[0x8];
10518
10519         u8         reserved_at_20[0xe0];
10520
10521         union mlx5_ifc_event_auto_bits event_data;
10522
10523         u8         reserved_at_1e0[0x10];
10524         u8         signature[0x8];
10525         u8         reserved_at_1f8[0x7];
10526         u8         owner[0x1];
10527 };
10528
10529 enum {
10530         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10531 };
10532
10533 struct mlx5_ifc_cmd_queue_entry_bits {
10534         u8         type[0x8];
10535         u8         reserved_at_8[0x18];
10536
10537         u8         input_length[0x20];
10538
10539         u8         input_mailbox_pointer_63_32[0x20];
10540
10541         u8         input_mailbox_pointer_31_9[0x17];
10542         u8         reserved_at_77[0x9];
10543
10544         u8         command_input_inline_data[16][0x8];
10545
10546         u8         command_output_inline_data[16][0x8];
10547
10548         u8         output_mailbox_pointer_63_32[0x20];
10549
10550         u8         output_mailbox_pointer_31_9[0x17];
10551         u8         reserved_at_1b7[0x9];
10552
10553         u8         output_length[0x20];
10554
10555         u8         token[0x8];
10556         u8         signature[0x8];
10557         u8         reserved_at_1f0[0x8];
10558         u8         status[0x7];
10559         u8         ownership[0x1];
10560 };
10561
10562 struct mlx5_ifc_cmd_out_bits {
10563         u8         status[0x8];
10564         u8         reserved_at_8[0x18];
10565
10566         u8         syndrome[0x20];
10567
10568         u8         command_output[0x20];
10569 };
10570
10571 struct mlx5_ifc_cmd_in_bits {
10572         u8         opcode[0x10];
10573         u8         reserved_at_10[0x10];
10574
10575         u8         reserved_at_20[0x10];
10576         u8         op_mod[0x10];
10577
10578         u8         command[][0x20];
10579 };
10580
10581 struct mlx5_ifc_cmd_if_box_bits {
10582         u8         mailbox_data[512][0x8];
10583
10584         u8         reserved_at_1000[0x180];
10585
10586         u8         next_pointer_63_32[0x20];
10587
10588         u8         next_pointer_31_10[0x16];
10589         u8         reserved_at_11b6[0xa];
10590
10591         u8         block_number[0x20];
10592
10593         u8         reserved_at_11e0[0x8];
10594         u8         token[0x8];
10595         u8         ctrl_signature[0x8];
10596         u8         signature[0x8];
10597 };
10598
10599 struct mlx5_ifc_mtt_bits {
10600         u8         ptag_63_32[0x20];
10601
10602         u8         ptag_31_8[0x18];
10603         u8         reserved_at_38[0x6];
10604         u8         wr_en[0x1];
10605         u8         rd_en[0x1];
10606 };
10607
10608 struct mlx5_ifc_query_wol_rol_out_bits {
10609         u8         status[0x8];
10610         u8         reserved_at_8[0x18];
10611
10612         u8         syndrome[0x20];
10613
10614         u8         reserved_at_40[0x10];
10615         u8         rol_mode[0x8];
10616         u8         wol_mode[0x8];
10617
10618         u8         reserved_at_60[0x20];
10619 };
10620
10621 struct mlx5_ifc_query_wol_rol_in_bits {
10622         u8         opcode[0x10];
10623         u8         reserved_at_10[0x10];
10624
10625         u8         reserved_at_20[0x10];
10626         u8         op_mod[0x10];
10627
10628         u8         reserved_at_40[0x40];
10629 };
10630
10631 struct mlx5_ifc_set_wol_rol_out_bits {
10632         u8         status[0x8];
10633         u8         reserved_at_8[0x18];
10634
10635         u8         syndrome[0x20];
10636
10637         u8         reserved_at_40[0x40];
10638 };
10639
10640 struct mlx5_ifc_set_wol_rol_in_bits {
10641         u8         opcode[0x10];
10642         u8         reserved_at_10[0x10];
10643
10644         u8         reserved_at_20[0x10];
10645         u8         op_mod[0x10];
10646
10647         u8         rol_mode_valid[0x1];
10648         u8         wol_mode_valid[0x1];
10649         u8         reserved_at_42[0xe];
10650         u8         rol_mode[0x8];
10651         u8         wol_mode[0x8];
10652
10653         u8         reserved_at_60[0x20];
10654 };
10655
10656 enum {
10657         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10658         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10659         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10660 };
10661
10662 enum {
10663         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10664         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10665         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10666 };
10667
10668 enum {
10669         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10670         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10671         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10672         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10673         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10674         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10675         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10676         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10677         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10678         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10679         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10680         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
10681 };
10682
10683 struct mlx5_ifc_initial_seg_bits {
10684         u8         fw_rev_minor[0x10];
10685         u8         fw_rev_major[0x10];
10686
10687         u8         cmd_interface_rev[0x10];
10688         u8         fw_rev_subminor[0x10];
10689
10690         u8         reserved_at_40[0x40];
10691
10692         u8         cmdq_phy_addr_63_32[0x20];
10693
10694         u8         cmdq_phy_addr_31_12[0x14];
10695         u8         reserved_at_b4[0x2];
10696         u8         nic_interface[0x2];
10697         u8         log_cmdq_size[0x4];
10698         u8         log_cmdq_stride[0x4];
10699
10700         u8         command_doorbell_vector[0x20];
10701
10702         u8         reserved_at_e0[0xf00];
10703
10704         u8         initializing[0x1];
10705         u8         reserved_at_fe1[0x4];
10706         u8         nic_interface_supported[0x3];
10707         u8         embedded_cpu[0x1];
10708         u8         reserved_at_fe9[0x17];
10709
10710         struct mlx5_ifc_health_buffer_bits health_buffer;
10711
10712         u8         no_dram_nic_offset[0x20];
10713
10714         u8         reserved_at_1220[0x6e40];
10715
10716         u8         reserved_at_8060[0x1f];
10717         u8         clear_int[0x1];
10718
10719         u8         health_syndrome[0x8];
10720         u8         health_counter[0x18];
10721
10722         u8         reserved_at_80a0[0x17fc0];
10723 };
10724
10725 struct mlx5_ifc_mtpps_reg_bits {
10726         u8         reserved_at_0[0xc];
10727         u8         cap_number_of_pps_pins[0x4];
10728         u8         reserved_at_10[0x4];
10729         u8         cap_max_num_of_pps_in_pins[0x4];
10730         u8         reserved_at_18[0x4];
10731         u8         cap_max_num_of_pps_out_pins[0x4];
10732
10733         u8         reserved_at_20[0x13];
10734         u8         cap_log_min_npps_period[0x5];
10735         u8         reserved_at_38[0x3];
10736         u8         cap_log_min_out_pulse_duration_ns[0x5];
10737
10738         u8         reserved_at_40[0x4];
10739         u8         cap_pin_3_mode[0x4];
10740         u8         reserved_at_48[0x4];
10741         u8         cap_pin_2_mode[0x4];
10742         u8         reserved_at_50[0x4];
10743         u8         cap_pin_1_mode[0x4];
10744         u8         reserved_at_58[0x4];
10745         u8         cap_pin_0_mode[0x4];
10746
10747         u8         reserved_at_60[0x4];
10748         u8         cap_pin_7_mode[0x4];
10749         u8         reserved_at_68[0x4];
10750         u8         cap_pin_6_mode[0x4];
10751         u8         reserved_at_70[0x4];
10752         u8         cap_pin_5_mode[0x4];
10753         u8         reserved_at_78[0x4];
10754         u8         cap_pin_4_mode[0x4];
10755
10756         u8         field_select[0x20];
10757         u8         reserved_at_a0[0x20];
10758
10759         u8         npps_period[0x40];
10760
10761         u8         enable[0x1];
10762         u8         reserved_at_101[0xb];
10763         u8         pattern[0x4];
10764         u8         reserved_at_110[0x4];
10765         u8         pin_mode[0x4];
10766         u8         pin[0x8];
10767
10768         u8         reserved_at_120[0x2];
10769         u8         out_pulse_duration_ns[0x1e];
10770
10771         u8         time_stamp[0x40];
10772
10773         u8         out_pulse_duration[0x10];
10774         u8         out_periodic_adjustment[0x10];
10775         u8         enhanced_out_periodic_adjustment[0x20];
10776
10777         u8         reserved_at_1c0[0x20];
10778 };
10779
10780 struct mlx5_ifc_mtppse_reg_bits {
10781         u8         reserved_at_0[0x18];
10782         u8         pin[0x8];
10783         u8         event_arm[0x1];
10784         u8         reserved_at_21[0x1b];
10785         u8         event_generation_mode[0x4];
10786         u8         reserved_at_40[0x40];
10787 };
10788
10789 struct mlx5_ifc_mcqs_reg_bits {
10790         u8         last_index_flag[0x1];
10791         u8         reserved_at_1[0x7];
10792         u8         fw_device[0x8];
10793         u8         component_index[0x10];
10794
10795         u8         reserved_at_20[0x10];
10796         u8         identifier[0x10];
10797
10798         u8         reserved_at_40[0x17];
10799         u8         component_status[0x5];
10800         u8         component_update_state[0x4];
10801
10802         u8         last_update_state_changer_type[0x4];
10803         u8         last_update_state_changer_host_id[0x4];
10804         u8         reserved_at_68[0x18];
10805 };
10806
10807 struct mlx5_ifc_mcqi_cap_bits {
10808         u8         supported_info_bitmask[0x20];
10809
10810         u8         component_size[0x20];
10811
10812         u8         max_component_size[0x20];
10813
10814         u8         log_mcda_word_size[0x4];
10815         u8         reserved_at_64[0xc];
10816         u8         mcda_max_write_size[0x10];
10817
10818         u8         rd_en[0x1];
10819         u8         reserved_at_81[0x1];
10820         u8         match_chip_id[0x1];
10821         u8         match_psid[0x1];
10822         u8         check_user_timestamp[0x1];
10823         u8         match_base_guid_mac[0x1];
10824         u8         reserved_at_86[0x1a];
10825 };
10826
10827 struct mlx5_ifc_mcqi_version_bits {
10828         u8         reserved_at_0[0x2];
10829         u8         build_time_valid[0x1];
10830         u8         user_defined_time_valid[0x1];
10831         u8         reserved_at_4[0x14];
10832         u8         version_string_length[0x8];
10833
10834         u8         version[0x20];
10835
10836         u8         build_time[0x40];
10837
10838         u8         user_defined_time[0x40];
10839
10840         u8         build_tool_version[0x20];
10841
10842         u8         reserved_at_e0[0x20];
10843
10844         u8         version_string[92][0x8];
10845 };
10846
10847 struct mlx5_ifc_mcqi_activation_method_bits {
10848         u8         pending_server_ac_power_cycle[0x1];
10849         u8         pending_server_dc_power_cycle[0x1];
10850         u8         pending_server_reboot[0x1];
10851         u8         pending_fw_reset[0x1];
10852         u8         auto_activate[0x1];
10853         u8         all_hosts_sync[0x1];
10854         u8         device_hw_reset[0x1];
10855         u8         reserved_at_7[0x19];
10856 };
10857
10858 union mlx5_ifc_mcqi_reg_data_bits {
10859         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10860         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10861         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10862 };
10863
10864 struct mlx5_ifc_mcqi_reg_bits {
10865         u8         read_pending_component[0x1];
10866         u8         reserved_at_1[0xf];
10867         u8         component_index[0x10];
10868
10869         u8         reserved_at_20[0x20];
10870
10871         u8         reserved_at_40[0x1b];
10872         u8         info_type[0x5];
10873
10874         u8         info_size[0x20];
10875
10876         u8         offset[0x20];
10877
10878         u8         reserved_at_a0[0x10];
10879         u8         data_size[0x10];
10880
10881         union mlx5_ifc_mcqi_reg_data_bits data[];
10882 };
10883
10884 struct mlx5_ifc_mcc_reg_bits {
10885         u8         reserved_at_0[0x4];
10886         u8         time_elapsed_since_last_cmd[0xc];
10887         u8         reserved_at_10[0x8];
10888         u8         instruction[0x8];
10889
10890         u8         reserved_at_20[0x10];
10891         u8         component_index[0x10];
10892
10893         u8         reserved_at_40[0x8];
10894         u8         update_handle[0x18];
10895
10896         u8         handle_owner_type[0x4];
10897         u8         handle_owner_host_id[0x4];
10898         u8         reserved_at_68[0x1];
10899         u8         control_progress[0x7];
10900         u8         error_code[0x8];
10901         u8         reserved_at_78[0x4];
10902         u8         control_state[0x4];
10903
10904         u8         component_size[0x20];
10905
10906         u8         reserved_at_a0[0x60];
10907 };
10908
10909 struct mlx5_ifc_mcda_reg_bits {
10910         u8         reserved_at_0[0x8];
10911         u8         update_handle[0x18];
10912
10913         u8         offset[0x20];
10914
10915         u8         reserved_at_40[0x10];
10916         u8         size[0x10];
10917
10918         u8         reserved_at_60[0x20];
10919
10920         u8         data[][0x20];
10921 };
10922
10923 enum {
10924         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10925         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10926         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10927         MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10928         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10929         MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10930 };
10931
10932 enum {
10933         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10934         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10935 };
10936
10937 enum {
10938         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10939         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10940         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10941 };
10942
10943 struct mlx5_ifc_mfrl_reg_bits {
10944         u8         reserved_at_0[0x20];
10945
10946         u8         reserved_at_20[0x2];
10947         u8         pci_sync_for_fw_update_start[0x1];
10948         u8         pci_sync_for_fw_update_resp[0x2];
10949         u8         rst_type_sel[0x3];
10950         u8         reserved_at_28[0x4];
10951         u8         reset_state[0x4];
10952         u8         reset_type[0x8];
10953         u8         reset_level[0x8];
10954 };
10955
10956 struct mlx5_ifc_mirc_reg_bits {
10957         u8         reserved_at_0[0x18];
10958         u8         status_code[0x8];
10959
10960         u8         reserved_at_20[0x20];
10961 };
10962
10963 struct mlx5_ifc_pddr_monitor_opcode_bits {
10964         u8         reserved_at_0[0x10];
10965         u8         monitor_opcode[0x10];
10966 };
10967
10968 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10969         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10970         u8         reserved_at_0[0x20];
10971 };
10972
10973 enum {
10974         /* Monitor opcodes */
10975         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10976 };
10977
10978 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10979         u8         reserved_at_0[0x10];
10980         u8         group_opcode[0x10];
10981
10982         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10983
10984         u8         reserved_at_40[0x20];
10985
10986         u8         status_message[59][0x20];
10987 };
10988
10989 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10990         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10991         u8         reserved_at_0[0x7c0];
10992 };
10993
10994 enum {
10995         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10996 };
10997
10998 struct mlx5_ifc_pddr_reg_bits {
10999         u8         reserved_at_0[0x8];
11000         u8         local_port[0x8];
11001         u8         pnat[0x2];
11002         u8         reserved_at_12[0xe];
11003
11004         u8         reserved_at_20[0x18];
11005         u8         page_select[0x8];
11006
11007         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11008 };
11009
11010 struct mlx5_ifc_mrtc_reg_bits {
11011         u8         time_synced[0x1];
11012         u8         reserved_at_1[0x1f];
11013
11014         u8         reserved_at_20[0x20];
11015
11016         u8         time_h[0x20];
11017
11018         u8         time_l[0x20];
11019 };
11020
11021 struct mlx5_ifc_mtcap_reg_bits {
11022         u8         reserved_at_0[0x19];
11023         u8         sensor_count[0x7];
11024
11025         u8         reserved_at_20[0x20];
11026
11027         u8         sensor_map[0x40];
11028 };
11029
11030 struct mlx5_ifc_mtmp_reg_bits {
11031         u8         reserved_at_0[0x14];
11032         u8         sensor_index[0xc];
11033
11034         u8         reserved_at_20[0x10];
11035         u8         temperature[0x10];
11036
11037         u8         mte[0x1];
11038         u8         mtr[0x1];
11039         u8         reserved_at_42[0xe];
11040         u8         max_temperature[0x10];
11041
11042         u8         tee[0x2];
11043         u8         reserved_at_62[0xe];
11044         u8         temp_threshold_hi[0x10];
11045
11046         u8         reserved_at_80[0x10];
11047         u8         temp_threshold_lo[0x10];
11048
11049         u8         reserved_at_a0[0x20];
11050
11051         u8         sensor_name_hi[0x20];
11052         u8         sensor_name_lo[0x20];
11053 };
11054
11055 union mlx5_ifc_ports_control_registers_document_bits {
11056         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11057         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11058         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11059         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11060         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11061         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11062         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11063         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11064         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11065         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11066         struct mlx5_ifc_pamp_reg_bits pamp_reg;
11067         struct mlx5_ifc_paos_reg_bits paos_reg;
11068         struct mlx5_ifc_pcap_reg_bits pcap_reg;
11069         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11070         struct mlx5_ifc_pddr_reg_bits pddr_reg;
11071         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11072         struct mlx5_ifc_peir_reg_bits peir_reg;
11073         struct mlx5_ifc_pelc_reg_bits pelc_reg;
11074         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11075         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11076         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11077         struct mlx5_ifc_pifr_reg_bits pifr_reg;
11078         struct mlx5_ifc_pipg_reg_bits pipg_reg;
11079         struct mlx5_ifc_plbf_reg_bits plbf_reg;
11080         struct mlx5_ifc_plib_reg_bits plib_reg;
11081         struct mlx5_ifc_plpc_reg_bits plpc_reg;
11082         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11083         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11084         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11085         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11086         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11087         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11088         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11089         struct mlx5_ifc_ppad_reg_bits ppad_reg;
11090         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11091         struct mlx5_ifc_mpein_reg_bits mpein_reg;
11092         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11093         struct mlx5_ifc_pplm_reg_bits pplm_reg;
11094         struct mlx5_ifc_pplr_reg_bits pplr_reg;
11095         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11096         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11097         struct mlx5_ifc_pspa_reg_bits pspa_reg;
11098         struct mlx5_ifc_ptas_reg_bits ptas_reg;
11099         struct mlx5_ifc_ptys_reg_bits ptys_reg;
11100         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11101         struct mlx5_ifc_pude_reg_bits pude_reg;
11102         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11103         struct mlx5_ifc_slrg_reg_bits slrg_reg;
11104         struct mlx5_ifc_sltp_reg_bits sltp_reg;
11105         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11106         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11107         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11108         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11109         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11110         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11111         struct mlx5_ifc_mcc_reg_bits mcc_reg;
11112         struct mlx5_ifc_mcda_reg_bits mcda_reg;
11113         struct mlx5_ifc_mirc_reg_bits mirc_reg;
11114         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11115         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11116         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11117         struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11118         struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11119         u8         reserved_at_0[0x60e0];
11120 };
11121
11122 union mlx5_ifc_debug_enhancements_document_bits {
11123         struct mlx5_ifc_health_buffer_bits health_buffer;
11124         u8         reserved_at_0[0x200];
11125 };
11126
11127 union mlx5_ifc_uplink_pci_interface_document_bits {
11128         struct mlx5_ifc_initial_seg_bits initial_seg;
11129         u8         reserved_at_0[0x20060];
11130 };
11131
11132 struct mlx5_ifc_set_flow_table_root_out_bits {
11133         u8         status[0x8];
11134         u8         reserved_at_8[0x18];
11135
11136         u8         syndrome[0x20];
11137
11138         u8         reserved_at_40[0x40];
11139 };
11140
11141 struct mlx5_ifc_set_flow_table_root_in_bits {
11142         u8         opcode[0x10];
11143         u8         reserved_at_10[0x10];
11144
11145         u8         reserved_at_20[0x10];
11146         u8         op_mod[0x10];
11147
11148         u8         other_vport[0x1];
11149         u8         reserved_at_41[0xf];
11150         u8         vport_number[0x10];
11151
11152         u8         reserved_at_60[0x20];
11153
11154         u8         table_type[0x8];
11155         u8         reserved_at_88[0x7];
11156         u8         table_of_other_vport[0x1];
11157         u8         table_vport_number[0x10];
11158
11159         u8         reserved_at_a0[0x8];
11160         u8         table_id[0x18];
11161
11162         u8         reserved_at_c0[0x8];
11163         u8         underlay_qpn[0x18];
11164         u8         table_eswitch_owner_vhca_id_valid[0x1];
11165         u8         reserved_at_e1[0xf];
11166         u8         table_eswitch_owner_vhca_id[0x10];
11167         u8         reserved_at_100[0x100];
11168 };
11169
11170 enum {
11171         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11172         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11173 };
11174
11175 struct mlx5_ifc_modify_flow_table_out_bits {
11176         u8         status[0x8];
11177         u8         reserved_at_8[0x18];
11178
11179         u8         syndrome[0x20];
11180
11181         u8         reserved_at_40[0x40];
11182 };
11183
11184 struct mlx5_ifc_modify_flow_table_in_bits {
11185         u8         opcode[0x10];
11186         u8         reserved_at_10[0x10];
11187
11188         u8         reserved_at_20[0x10];
11189         u8         op_mod[0x10];
11190
11191         u8         other_vport[0x1];
11192         u8         reserved_at_41[0xf];
11193         u8         vport_number[0x10];
11194
11195         u8         reserved_at_60[0x10];
11196         u8         modify_field_select[0x10];
11197
11198         u8         table_type[0x8];
11199         u8         reserved_at_88[0x18];
11200
11201         u8         reserved_at_a0[0x8];
11202         u8         table_id[0x18];
11203
11204         struct mlx5_ifc_flow_table_context_bits flow_table_context;
11205 };
11206
11207 struct mlx5_ifc_ets_tcn_config_reg_bits {
11208         u8         g[0x1];
11209         u8         b[0x1];
11210         u8         r[0x1];
11211         u8         reserved_at_3[0x9];
11212         u8         group[0x4];
11213         u8         reserved_at_10[0x9];
11214         u8         bw_allocation[0x7];
11215
11216         u8         reserved_at_20[0xc];
11217         u8         max_bw_units[0x4];
11218         u8         reserved_at_30[0x8];
11219         u8         max_bw_value[0x8];
11220 };
11221
11222 struct mlx5_ifc_ets_global_config_reg_bits {
11223         u8         reserved_at_0[0x2];
11224         u8         r[0x1];
11225         u8         reserved_at_3[0x1d];
11226
11227         u8         reserved_at_20[0xc];
11228         u8         max_bw_units[0x4];
11229         u8         reserved_at_30[0x8];
11230         u8         max_bw_value[0x8];
11231 };
11232
11233 struct mlx5_ifc_qetc_reg_bits {
11234         u8                                         reserved_at_0[0x8];
11235         u8                                         port_number[0x8];
11236         u8                                         reserved_at_10[0x30];
11237
11238         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11239         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11240 };
11241
11242 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11243         u8         e[0x1];
11244         u8         reserved_at_01[0x0b];
11245         u8         prio[0x04];
11246 };
11247
11248 struct mlx5_ifc_qpdpm_reg_bits {
11249         u8                                     reserved_at_0[0x8];
11250         u8                                     local_port[0x8];
11251         u8                                     reserved_at_10[0x10];
11252         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11253 };
11254
11255 struct mlx5_ifc_qpts_reg_bits {
11256         u8         reserved_at_0[0x8];
11257         u8         local_port[0x8];
11258         u8         reserved_at_10[0x2d];
11259         u8         trust_state[0x3];
11260 };
11261
11262 struct mlx5_ifc_pptb_reg_bits {
11263         u8         reserved_at_0[0x2];
11264         u8         mm[0x2];
11265         u8         reserved_at_4[0x4];
11266         u8         local_port[0x8];
11267         u8         reserved_at_10[0x6];
11268         u8         cm[0x1];
11269         u8         um[0x1];
11270         u8         pm[0x8];
11271
11272         u8         prio_x_buff[0x20];
11273
11274         u8         pm_msb[0x8];
11275         u8         reserved_at_48[0x10];
11276         u8         ctrl_buff[0x4];
11277         u8         untagged_buff[0x4];
11278 };
11279
11280 struct mlx5_ifc_sbcam_reg_bits {
11281         u8         reserved_at_0[0x8];
11282         u8         feature_group[0x8];
11283         u8         reserved_at_10[0x8];
11284         u8         access_reg_group[0x8];
11285
11286         u8         reserved_at_20[0x20];
11287
11288         u8         sb_access_reg_cap_mask[4][0x20];
11289
11290         u8         reserved_at_c0[0x80];
11291
11292         u8         sb_feature_cap_mask[4][0x20];
11293
11294         u8         reserved_at_1c0[0x40];
11295
11296         u8         cap_total_buffer_size[0x20];
11297
11298         u8         cap_cell_size[0x10];
11299         u8         cap_max_pg_buffers[0x8];
11300         u8         cap_num_pool_supported[0x8];
11301
11302         u8         reserved_at_240[0x8];
11303         u8         cap_sbsr_stat_size[0x8];
11304         u8         cap_max_tclass_data[0x8];
11305         u8         cap_max_cpu_ingress_tclass_sb[0x8];
11306 };
11307
11308 struct mlx5_ifc_pbmc_reg_bits {
11309         u8         reserved_at_0[0x8];
11310         u8         local_port[0x8];
11311         u8         reserved_at_10[0x10];
11312
11313         u8         xoff_timer_value[0x10];
11314         u8         xoff_refresh[0x10];
11315
11316         u8         reserved_at_40[0x9];
11317         u8         fullness_threshold[0x7];
11318         u8         port_buffer_size[0x10];
11319
11320         struct mlx5_ifc_bufferx_reg_bits buffer[10];
11321
11322         u8         reserved_at_2e0[0x80];
11323 };
11324
11325 struct mlx5_ifc_sbpr_reg_bits {
11326         u8         desc[0x1];
11327         u8         snap[0x1];
11328         u8         reserved_at_2[0x4];
11329         u8         dir[0x2];
11330         u8         reserved_at_8[0x14];
11331         u8         pool[0x4];
11332
11333         u8         infi_size[0x1];
11334         u8         reserved_at_21[0x7];
11335         u8         size[0x18];
11336
11337         u8         reserved_at_40[0x1c];
11338         u8         mode[0x4];
11339
11340         u8         reserved_at_60[0x8];
11341         u8         buff_occupancy[0x18];
11342
11343         u8         clr[0x1];
11344         u8         reserved_at_81[0x7];
11345         u8         max_buff_occupancy[0x18];
11346
11347         u8         reserved_at_a0[0x8];
11348         u8         ext_buff_occupancy[0x18];
11349 };
11350
11351 struct mlx5_ifc_sbcm_reg_bits {
11352         u8         desc[0x1];
11353         u8         snap[0x1];
11354         u8         reserved_at_2[0x6];
11355         u8         local_port[0x8];
11356         u8         pnat[0x2];
11357         u8         pg_buff[0x6];
11358         u8         reserved_at_18[0x6];
11359         u8         dir[0x2];
11360
11361         u8         reserved_at_20[0x1f];
11362         u8         exc[0x1];
11363
11364         u8         reserved_at_40[0x40];
11365
11366         u8         reserved_at_80[0x8];
11367         u8         buff_occupancy[0x18];
11368
11369         u8         clr[0x1];
11370         u8         reserved_at_a1[0x7];
11371         u8         max_buff_occupancy[0x18];
11372
11373         u8         reserved_at_c0[0x8];
11374         u8         min_buff[0x18];
11375
11376         u8         infi_max[0x1];
11377         u8         reserved_at_e1[0x7];
11378         u8         max_buff[0x18];
11379
11380         u8         reserved_at_100[0x20];
11381
11382         u8         reserved_at_120[0x1c];
11383         u8         pool[0x4];
11384 };
11385
11386 struct mlx5_ifc_qtct_reg_bits {
11387         u8         reserved_at_0[0x8];
11388         u8         port_number[0x8];
11389         u8         reserved_at_10[0xd];
11390         u8         prio[0x3];
11391
11392         u8         reserved_at_20[0x1d];
11393         u8         tclass[0x3];
11394 };
11395
11396 struct mlx5_ifc_mcia_reg_bits {
11397         u8         l[0x1];
11398         u8         reserved_at_1[0x7];
11399         u8         module[0x8];
11400         u8         reserved_at_10[0x8];
11401         u8         status[0x8];
11402
11403         u8         i2c_device_address[0x8];
11404         u8         page_number[0x8];
11405         u8         device_address[0x10];
11406
11407         u8         reserved_at_40[0x10];
11408         u8         size[0x10];
11409
11410         u8         reserved_at_60[0x20];
11411
11412         u8         dword_0[0x20];
11413         u8         dword_1[0x20];
11414         u8         dword_2[0x20];
11415         u8         dword_3[0x20];
11416         u8         dword_4[0x20];
11417         u8         dword_5[0x20];
11418         u8         dword_6[0x20];
11419         u8         dword_7[0x20];
11420         u8         dword_8[0x20];
11421         u8         dword_9[0x20];
11422         u8         dword_10[0x20];
11423         u8         dword_11[0x20];
11424 };
11425
11426 struct mlx5_ifc_dcbx_param_bits {
11427         u8         dcbx_cee_cap[0x1];
11428         u8         dcbx_ieee_cap[0x1];
11429         u8         dcbx_standby_cap[0x1];
11430         u8         reserved_at_3[0x5];
11431         u8         port_number[0x8];
11432         u8         reserved_at_10[0xa];
11433         u8         max_application_table_size[6];
11434         u8         reserved_at_20[0x15];
11435         u8         version_oper[0x3];
11436         u8         reserved_at_38[5];
11437         u8         version_admin[0x3];
11438         u8         willing_admin[0x1];
11439         u8         reserved_at_41[0x3];
11440         u8         pfc_cap_oper[0x4];
11441         u8         reserved_at_48[0x4];
11442         u8         pfc_cap_admin[0x4];
11443         u8         reserved_at_50[0x4];
11444         u8         num_of_tc_oper[0x4];
11445         u8         reserved_at_58[0x4];
11446         u8         num_of_tc_admin[0x4];
11447         u8         remote_willing[0x1];
11448         u8         reserved_at_61[3];
11449         u8         remote_pfc_cap[4];
11450         u8         reserved_at_68[0x14];
11451         u8         remote_num_of_tc[0x4];
11452         u8         reserved_at_80[0x18];
11453         u8         error[0x8];
11454         u8         reserved_at_a0[0x160];
11455 };
11456
11457 enum {
11458         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11459         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11460         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11461 };
11462
11463 struct mlx5_ifc_lagc_bits {
11464         u8         fdb_selection_mode[0x1];
11465         u8         reserved_at_1[0x14];
11466         u8         port_select_mode[0x3];
11467         u8         reserved_at_18[0x5];
11468         u8         lag_state[0x3];
11469
11470         u8         reserved_at_20[0xc];
11471         u8         active_port[0x4];
11472         u8         reserved_at_30[0x4];
11473         u8         tx_remap_affinity_2[0x4];
11474         u8         reserved_at_38[0x4];
11475         u8         tx_remap_affinity_1[0x4];
11476 };
11477
11478 struct mlx5_ifc_create_lag_out_bits {
11479         u8         status[0x8];
11480         u8         reserved_at_8[0x18];
11481
11482         u8         syndrome[0x20];
11483
11484         u8         reserved_at_40[0x40];
11485 };
11486
11487 struct mlx5_ifc_create_lag_in_bits {
11488         u8         opcode[0x10];
11489         u8         reserved_at_10[0x10];
11490
11491         u8         reserved_at_20[0x10];
11492         u8         op_mod[0x10];
11493
11494         struct mlx5_ifc_lagc_bits ctx;
11495 };
11496
11497 struct mlx5_ifc_modify_lag_out_bits {
11498         u8         status[0x8];
11499         u8         reserved_at_8[0x18];
11500
11501         u8         syndrome[0x20];
11502
11503         u8         reserved_at_40[0x40];
11504 };
11505
11506 struct mlx5_ifc_modify_lag_in_bits {
11507         u8         opcode[0x10];
11508         u8         reserved_at_10[0x10];
11509
11510         u8         reserved_at_20[0x10];
11511         u8         op_mod[0x10];
11512
11513         u8         reserved_at_40[0x20];
11514         u8         field_select[0x20];
11515
11516         struct mlx5_ifc_lagc_bits ctx;
11517 };
11518
11519 struct mlx5_ifc_query_lag_out_bits {
11520         u8         status[0x8];
11521         u8         reserved_at_8[0x18];
11522
11523         u8         syndrome[0x20];
11524
11525         struct mlx5_ifc_lagc_bits ctx;
11526 };
11527
11528 struct mlx5_ifc_query_lag_in_bits {
11529         u8         opcode[0x10];
11530         u8         reserved_at_10[0x10];
11531
11532         u8         reserved_at_20[0x10];
11533         u8         op_mod[0x10];
11534
11535         u8         reserved_at_40[0x40];
11536 };
11537
11538 struct mlx5_ifc_destroy_lag_out_bits {
11539         u8         status[0x8];
11540         u8         reserved_at_8[0x18];
11541
11542         u8         syndrome[0x20];
11543
11544         u8         reserved_at_40[0x40];
11545 };
11546
11547 struct mlx5_ifc_destroy_lag_in_bits {
11548         u8         opcode[0x10];
11549         u8         reserved_at_10[0x10];
11550
11551         u8         reserved_at_20[0x10];
11552         u8         op_mod[0x10];
11553
11554         u8         reserved_at_40[0x40];
11555 };
11556
11557 struct mlx5_ifc_create_vport_lag_out_bits {
11558         u8         status[0x8];
11559         u8         reserved_at_8[0x18];
11560
11561         u8         syndrome[0x20];
11562
11563         u8         reserved_at_40[0x40];
11564 };
11565
11566 struct mlx5_ifc_create_vport_lag_in_bits {
11567         u8         opcode[0x10];
11568         u8         reserved_at_10[0x10];
11569
11570         u8         reserved_at_20[0x10];
11571         u8         op_mod[0x10];
11572
11573         u8         reserved_at_40[0x40];
11574 };
11575
11576 struct mlx5_ifc_destroy_vport_lag_out_bits {
11577         u8         status[0x8];
11578         u8         reserved_at_8[0x18];
11579
11580         u8         syndrome[0x20];
11581
11582         u8         reserved_at_40[0x40];
11583 };
11584
11585 struct mlx5_ifc_destroy_vport_lag_in_bits {
11586         u8         opcode[0x10];
11587         u8         reserved_at_10[0x10];
11588
11589         u8         reserved_at_20[0x10];
11590         u8         op_mod[0x10];
11591
11592         u8         reserved_at_40[0x40];
11593 };
11594
11595 enum {
11596         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11597         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11598 };
11599
11600 struct mlx5_ifc_modify_memic_in_bits {
11601         u8         opcode[0x10];
11602         u8         uid[0x10];
11603
11604         u8         reserved_at_20[0x10];
11605         u8         op_mod[0x10];
11606
11607         u8         reserved_at_40[0x20];
11608
11609         u8         reserved_at_60[0x18];
11610         u8         memic_operation_type[0x8];
11611
11612         u8         memic_start_addr[0x40];
11613
11614         u8         reserved_at_c0[0x140];
11615 };
11616
11617 struct mlx5_ifc_modify_memic_out_bits {
11618         u8         status[0x8];
11619         u8         reserved_at_8[0x18];
11620
11621         u8         syndrome[0x20];
11622
11623         u8         reserved_at_40[0x40];
11624
11625         u8         memic_operation_addr[0x40];
11626
11627         u8         reserved_at_c0[0x140];
11628 };
11629
11630 struct mlx5_ifc_alloc_memic_in_bits {
11631         u8         opcode[0x10];
11632         u8         reserved_at_10[0x10];
11633
11634         u8         reserved_at_20[0x10];
11635         u8         op_mod[0x10];
11636
11637         u8         reserved_at_30[0x20];
11638
11639         u8         reserved_at_40[0x18];
11640         u8         log_memic_addr_alignment[0x8];
11641
11642         u8         range_start_addr[0x40];
11643
11644         u8         range_size[0x20];
11645
11646         u8         memic_size[0x20];
11647 };
11648
11649 struct mlx5_ifc_alloc_memic_out_bits {
11650         u8         status[0x8];
11651         u8         reserved_at_8[0x18];
11652
11653         u8         syndrome[0x20];
11654
11655         u8         memic_start_addr[0x40];
11656 };
11657
11658 struct mlx5_ifc_dealloc_memic_in_bits {
11659         u8         opcode[0x10];
11660         u8         reserved_at_10[0x10];
11661
11662         u8         reserved_at_20[0x10];
11663         u8         op_mod[0x10];
11664
11665         u8         reserved_at_40[0x40];
11666
11667         u8         memic_start_addr[0x40];
11668
11669         u8         memic_size[0x20];
11670
11671         u8         reserved_at_e0[0x20];
11672 };
11673
11674 struct mlx5_ifc_dealloc_memic_out_bits {
11675         u8         status[0x8];
11676         u8         reserved_at_8[0x18];
11677
11678         u8         syndrome[0x20];
11679
11680         u8         reserved_at_40[0x40];
11681 };
11682
11683 struct mlx5_ifc_umem_bits {
11684         u8         reserved_at_0[0x80];
11685
11686         u8         ats[0x1];
11687         u8         reserved_at_81[0x1a];
11688         u8         log_page_size[0x5];
11689
11690         u8         page_offset[0x20];
11691
11692         u8         num_of_mtt[0x40];
11693
11694         struct mlx5_ifc_mtt_bits  mtt[];
11695 };
11696
11697 struct mlx5_ifc_uctx_bits {
11698         u8         cap[0x20];
11699
11700         u8         reserved_at_20[0x160];
11701 };
11702
11703 struct mlx5_ifc_sw_icm_bits {
11704         u8         modify_field_select[0x40];
11705
11706         u8         reserved_at_40[0x18];
11707         u8         log_sw_icm_size[0x8];
11708
11709         u8         reserved_at_60[0x20];
11710
11711         u8         sw_icm_start_addr[0x40];
11712
11713         u8         reserved_at_c0[0x140];
11714 };
11715
11716 struct mlx5_ifc_geneve_tlv_option_bits {
11717         u8         modify_field_select[0x40];
11718
11719         u8         reserved_at_40[0x18];
11720         u8         geneve_option_fte_index[0x8];
11721
11722         u8         option_class[0x10];
11723         u8         option_type[0x8];
11724         u8         reserved_at_78[0x3];
11725         u8         option_data_length[0x5];
11726
11727         u8         reserved_at_80[0x180];
11728 };
11729
11730 struct mlx5_ifc_create_umem_in_bits {
11731         u8         opcode[0x10];
11732         u8         uid[0x10];
11733
11734         u8         reserved_at_20[0x10];
11735         u8         op_mod[0x10];
11736
11737         u8         reserved_at_40[0x40];
11738
11739         struct mlx5_ifc_umem_bits  umem;
11740 };
11741
11742 struct mlx5_ifc_create_umem_out_bits {
11743         u8         status[0x8];
11744         u8         reserved_at_8[0x18];
11745
11746         u8         syndrome[0x20];
11747
11748         u8         reserved_at_40[0x8];
11749         u8         umem_id[0x18];
11750
11751         u8         reserved_at_60[0x20];
11752 };
11753
11754 struct mlx5_ifc_destroy_umem_in_bits {
11755         u8        opcode[0x10];
11756         u8        uid[0x10];
11757
11758         u8        reserved_at_20[0x10];
11759         u8        op_mod[0x10];
11760
11761         u8        reserved_at_40[0x8];
11762         u8        umem_id[0x18];
11763
11764         u8        reserved_at_60[0x20];
11765 };
11766
11767 struct mlx5_ifc_destroy_umem_out_bits {
11768         u8        status[0x8];
11769         u8        reserved_at_8[0x18];
11770
11771         u8        syndrome[0x20];
11772
11773         u8        reserved_at_40[0x40];
11774 };
11775
11776 struct mlx5_ifc_create_uctx_in_bits {
11777         u8         opcode[0x10];
11778         u8         reserved_at_10[0x10];
11779
11780         u8         reserved_at_20[0x10];
11781         u8         op_mod[0x10];
11782
11783         u8         reserved_at_40[0x40];
11784
11785         struct mlx5_ifc_uctx_bits  uctx;
11786 };
11787
11788 struct mlx5_ifc_create_uctx_out_bits {
11789         u8         status[0x8];
11790         u8         reserved_at_8[0x18];
11791
11792         u8         syndrome[0x20];
11793
11794         u8         reserved_at_40[0x10];
11795         u8         uid[0x10];
11796
11797         u8         reserved_at_60[0x20];
11798 };
11799
11800 struct mlx5_ifc_destroy_uctx_in_bits {
11801         u8         opcode[0x10];
11802         u8         reserved_at_10[0x10];
11803
11804         u8         reserved_at_20[0x10];
11805         u8         op_mod[0x10];
11806
11807         u8         reserved_at_40[0x10];
11808         u8         uid[0x10];
11809
11810         u8         reserved_at_60[0x20];
11811 };
11812
11813 struct mlx5_ifc_destroy_uctx_out_bits {
11814         u8         status[0x8];
11815         u8         reserved_at_8[0x18];
11816
11817         u8         syndrome[0x20];
11818
11819         u8          reserved_at_40[0x40];
11820 };
11821
11822 struct mlx5_ifc_create_sw_icm_in_bits {
11823         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11824         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11825 };
11826
11827 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11828         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11829         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11830 };
11831
11832 struct mlx5_ifc_mtrc_string_db_param_bits {
11833         u8         string_db_base_address[0x20];
11834
11835         u8         reserved_at_20[0x8];
11836         u8         string_db_size[0x18];
11837 };
11838
11839 struct mlx5_ifc_mtrc_cap_bits {
11840         u8         trace_owner[0x1];
11841         u8         trace_to_memory[0x1];
11842         u8         reserved_at_2[0x4];
11843         u8         trc_ver[0x2];
11844         u8         reserved_at_8[0x14];
11845         u8         num_string_db[0x4];
11846
11847         u8         first_string_trace[0x8];
11848         u8         num_string_trace[0x8];
11849         u8         reserved_at_30[0x28];
11850
11851         u8         log_max_trace_buffer_size[0x8];
11852
11853         u8         reserved_at_60[0x20];
11854
11855         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11856
11857         u8         reserved_at_280[0x180];
11858 };
11859
11860 struct mlx5_ifc_mtrc_conf_bits {
11861         u8         reserved_at_0[0x1c];
11862         u8         trace_mode[0x4];
11863         u8         reserved_at_20[0x18];
11864         u8         log_trace_buffer_size[0x8];
11865         u8         trace_mkey[0x20];
11866         u8         reserved_at_60[0x3a0];
11867 };
11868
11869 struct mlx5_ifc_mtrc_stdb_bits {
11870         u8         string_db_index[0x4];
11871         u8         reserved_at_4[0x4];
11872         u8         read_size[0x18];
11873         u8         start_offset[0x20];
11874         u8         string_db_data[];
11875 };
11876
11877 struct mlx5_ifc_mtrc_ctrl_bits {
11878         u8         trace_status[0x2];
11879         u8         reserved_at_2[0x2];
11880         u8         arm_event[0x1];
11881         u8         reserved_at_5[0xb];
11882         u8         modify_field_select[0x10];
11883         u8         reserved_at_20[0x2b];
11884         u8         current_timestamp52_32[0x15];
11885         u8         current_timestamp31_0[0x20];
11886         u8         reserved_at_80[0x180];
11887 };
11888
11889 struct mlx5_ifc_host_params_context_bits {
11890         u8         host_number[0x8];
11891         u8         reserved_at_8[0x7];
11892         u8         host_pf_disabled[0x1];
11893         u8         host_num_of_vfs[0x10];
11894
11895         u8         host_total_vfs[0x10];
11896         u8         host_pci_bus[0x10];
11897
11898         u8         reserved_at_40[0x10];
11899         u8         host_pci_device[0x10];
11900
11901         u8         reserved_at_60[0x10];
11902         u8         host_pci_function[0x10];
11903
11904         u8         reserved_at_80[0x180];
11905 };
11906
11907 struct mlx5_ifc_query_esw_functions_in_bits {
11908         u8         opcode[0x10];
11909         u8         reserved_at_10[0x10];
11910
11911         u8         reserved_at_20[0x10];
11912         u8         op_mod[0x10];
11913
11914         u8         reserved_at_40[0x40];
11915 };
11916
11917 struct mlx5_ifc_query_esw_functions_out_bits {
11918         u8         status[0x8];
11919         u8         reserved_at_8[0x18];
11920
11921         u8         syndrome[0x20];
11922
11923         u8         reserved_at_40[0x40];
11924
11925         struct mlx5_ifc_host_params_context_bits host_params_context;
11926
11927         u8         reserved_at_280[0x180];
11928         u8         host_sf_enable[][0x40];
11929 };
11930
11931 struct mlx5_ifc_sf_partition_bits {
11932         u8         reserved_at_0[0x10];
11933         u8         log_num_sf[0x8];
11934         u8         log_sf_bar_size[0x8];
11935 };
11936
11937 struct mlx5_ifc_query_sf_partitions_out_bits {
11938         u8         status[0x8];
11939         u8         reserved_at_8[0x18];
11940
11941         u8         syndrome[0x20];
11942
11943         u8         reserved_at_40[0x18];
11944         u8         num_sf_partitions[0x8];
11945
11946         u8         reserved_at_60[0x20];
11947
11948         struct mlx5_ifc_sf_partition_bits sf_partition[];
11949 };
11950
11951 struct mlx5_ifc_query_sf_partitions_in_bits {
11952         u8         opcode[0x10];
11953         u8         reserved_at_10[0x10];
11954
11955         u8         reserved_at_20[0x10];
11956         u8         op_mod[0x10];
11957
11958         u8         reserved_at_40[0x40];
11959 };
11960
11961 struct mlx5_ifc_dealloc_sf_out_bits {
11962         u8         status[0x8];
11963         u8         reserved_at_8[0x18];
11964
11965         u8         syndrome[0x20];
11966
11967         u8         reserved_at_40[0x40];
11968 };
11969
11970 struct mlx5_ifc_dealloc_sf_in_bits {
11971         u8         opcode[0x10];
11972         u8         reserved_at_10[0x10];
11973
11974         u8         reserved_at_20[0x10];
11975         u8         op_mod[0x10];
11976
11977         u8         reserved_at_40[0x10];
11978         u8         function_id[0x10];
11979
11980         u8         reserved_at_60[0x20];
11981 };
11982
11983 struct mlx5_ifc_alloc_sf_out_bits {
11984         u8         status[0x8];
11985         u8         reserved_at_8[0x18];
11986
11987         u8         syndrome[0x20];
11988
11989         u8         reserved_at_40[0x40];
11990 };
11991
11992 struct mlx5_ifc_alloc_sf_in_bits {
11993         u8         opcode[0x10];
11994         u8         reserved_at_10[0x10];
11995
11996         u8         reserved_at_20[0x10];
11997         u8         op_mod[0x10];
11998
11999         u8         reserved_at_40[0x10];
12000         u8         function_id[0x10];
12001
12002         u8         reserved_at_60[0x20];
12003 };
12004
12005 struct mlx5_ifc_affiliated_event_header_bits {
12006         u8         reserved_at_0[0x10];
12007         u8         obj_type[0x10];
12008
12009         u8         obj_id[0x20];
12010 };
12011
12012 enum {
12013         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12014         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12015         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12016         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12017 };
12018
12019 enum {
12020         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12021         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12022         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12023         MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12024         MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12025         MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12026         MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12027 };
12028
12029 enum {
12030         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12031 };
12032
12033 enum {
12034         MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12035         MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12036         MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12037         MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12038 };
12039
12040 enum {
12041         MLX5_IPSEC_ASO_MODE              = 0x0,
12042         MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12043         MLX5_IPSEC_ASO_INC_SN            = 0x2,
12044 };
12045
12046 enum {
12047         MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12048         MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12049         MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12050         MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12051 };
12052
12053 struct mlx5_ifc_ipsec_aso_bits {
12054         u8         valid[0x1];
12055         u8         reserved_at_201[0x1];
12056         u8         mode[0x2];
12057         u8         window_sz[0x2];
12058         u8         soft_lft_arm[0x1];
12059         u8         hard_lft_arm[0x1];
12060         u8         remove_flow_enable[0x1];
12061         u8         esn_event_arm[0x1];
12062         u8         reserved_at_20a[0x16];
12063
12064         u8         remove_flow_pkt_cnt[0x20];
12065
12066         u8         remove_flow_soft_lft[0x20];
12067
12068         u8         reserved_at_260[0x80];
12069
12070         u8         mode_parameter[0x20];
12071
12072         u8         replay_protection_window[0x100];
12073 };
12074
12075 struct mlx5_ifc_ipsec_obj_bits {
12076         u8         modify_field_select[0x40];
12077         u8         full_offload[0x1];
12078         u8         reserved_at_41[0x1];
12079         u8         esn_en[0x1];
12080         u8         esn_overlap[0x1];
12081         u8         reserved_at_44[0x2];
12082         u8         icv_length[0x2];
12083         u8         reserved_at_48[0x4];
12084         u8         aso_return_reg[0x4];
12085         u8         reserved_at_50[0x10];
12086
12087         u8         esn_msb[0x20];
12088
12089         u8         reserved_at_80[0x8];
12090         u8         dekn[0x18];
12091
12092         u8         salt[0x20];
12093
12094         u8         implicit_iv[0x40];
12095
12096         u8         reserved_at_100[0x8];
12097         u8         ipsec_aso_access_pd[0x18];
12098         u8         reserved_at_120[0xe0];
12099
12100         struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12101 };
12102
12103 struct mlx5_ifc_create_ipsec_obj_in_bits {
12104         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12105         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12106 };
12107
12108 enum {
12109         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12110         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12111 };
12112
12113 struct mlx5_ifc_query_ipsec_obj_out_bits {
12114         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12115         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12116 };
12117
12118 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12119         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12120         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12121 };
12122
12123 enum {
12124         MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12125 };
12126
12127 enum {
12128         MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12129         MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12130         MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12131         MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12132 };
12133
12134 #define MLX5_MACSEC_ASO_INC_SN  0x2
12135 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12136
12137 struct mlx5_ifc_macsec_aso_bits {
12138         u8    valid[0x1];
12139         u8    reserved_at_1[0x1];
12140         u8    mode[0x2];
12141         u8    window_size[0x2];
12142         u8    soft_lifetime_arm[0x1];
12143         u8    hard_lifetime_arm[0x1];
12144         u8    remove_flow_enable[0x1];
12145         u8    epn_event_arm[0x1];
12146         u8    reserved_at_a[0x16];
12147
12148         u8    remove_flow_packet_count[0x20];
12149
12150         u8    remove_flow_soft_lifetime[0x20];
12151
12152         u8    reserved_at_60[0x80];
12153
12154         u8    mode_parameter[0x20];
12155
12156         u8    replay_protection_window[8][0x20];
12157 };
12158
12159 struct mlx5_ifc_macsec_offload_obj_bits {
12160         u8    modify_field_select[0x40];
12161
12162         u8    confidentiality_en[0x1];
12163         u8    reserved_at_41[0x1];
12164         u8    epn_en[0x1];
12165         u8    epn_overlap[0x1];
12166         u8    reserved_at_44[0x2];
12167         u8    confidentiality_offset[0x2];
12168         u8    reserved_at_48[0x4];
12169         u8    aso_return_reg[0x4];
12170         u8    reserved_at_50[0x10];
12171
12172         u8    epn_msb[0x20];
12173
12174         u8    reserved_at_80[0x8];
12175         u8    dekn[0x18];
12176
12177         u8    reserved_at_a0[0x20];
12178
12179         u8    sci[0x40];
12180
12181         u8    reserved_at_100[0x8];
12182         u8    macsec_aso_access_pd[0x18];
12183
12184         u8    reserved_at_120[0x60];
12185
12186         u8    salt[3][0x20];
12187
12188         u8    reserved_at_1e0[0x20];
12189
12190         struct mlx5_ifc_macsec_aso_bits macsec_aso;
12191 };
12192
12193 struct mlx5_ifc_create_macsec_obj_in_bits {
12194         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12195         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12196 };
12197
12198 struct mlx5_ifc_modify_macsec_obj_in_bits {
12199         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12200         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12201 };
12202
12203 enum {
12204         MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12205         MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12206 };
12207
12208 struct mlx5_ifc_query_macsec_obj_out_bits {
12209         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12210         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12211 };
12212
12213 struct mlx5_ifc_wrapped_dek_bits {
12214         u8         gcm_iv[0x60];
12215
12216         u8         reserved_at_60[0x20];
12217
12218         u8         const0[0x1];
12219         u8         key_size[0x1];
12220         u8         reserved_at_82[0x2];
12221         u8         key2_invalid[0x1];
12222         u8         reserved_at_85[0x3];
12223         u8         pd[0x18];
12224
12225         u8         key_purpose[0x5];
12226         u8         reserved_at_a5[0x13];
12227         u8         kek_id[0x8];
12228
12229         u8         reserved_at_c0[0x40];
12230
12231         u8         key1[0x8][0x20];
12232
12233         u8         key2[0x8][0x20];
12234
12235         u8         reserved_at_300[0x40];
12236
12237         u8         const1[0x1];
12238         u8         reserved_at_341[0x1f];
12239
12240         u8         reserved_at_360[0x20];
12241
12242         u8         auth_tag[0x80];
12243 };
12244
12245 struct mlx5_ifc_encryption_key_obj_bits {
12246         u8         modify_field_select[0x40];
12247
12248         u8         state[0x8];
12249         u8         sw_wrapped[0x1];
12250         u8         reserved_at_49[0xb];
12251         u8         key_size[0x4];
12252         u8         reserved_at_58[0x4];
12253         u8         key_purpose[0x4];
12254
12255         u8         reserved_at_60[0x8];
12256         u8         pd[0x18];
12257
12258         u8         reserved_at_80[0x100];
12259
12260         u8         opaque[0x40];
12261
12262         u8         reserved_at_1c0[0x40];
12263
12264         u8         key[8][0x80];
12265
12266         u8         sw_wrapped_dek[8][0x80];
12267
12268         u8         reserved_at_a00[0x600];
12269 };
12270
12271 struct mlx5_ifc_create_encryption_key_in_bits {
12272         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12273         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12274 };
12275
12276 struct mlx5_ifc_modify_encryption_key_in_bits {
12277         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12278         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12279 };
12280
12281 enum {
12282         MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH            = 0x0,
12283         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2         = 0x1,
12284         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG     = 0x2,
12285         MLX5_FLOW_METER_MODE_NUM_PACKETS                = 0x3,
12286 };
12287
12288 struct mlx5_ifc_flow_meter_parameters_bits {
12289         u8         valid[0x1];
12290         u8         bucket_overflow[0x1];
12291         u8         start_color[0x2];
12292         u8         both_buckets_on_green[0x1];
12293         u8         reserved_at_5[0x1];
12294         u8         meter_mode[0x2];
12295         u8         reserved_at_8[0x18];
12296
12297         u8         reserved_at_20[0x20];
12298
12299         u8         reserved_at_40[0x3];
12300         u8         cbs_exponent[0x5];
12301         u8         cbs_mantissa[0x8];
12302         u8         reserved_at_50[0x3];
12303         u8         cir_exponent[0x5];
12304         u8         cir_mantissa[0x8];
12305
12306         u8         reserved_at_60[0x20];
12307
12308         u8         reserved_at_80[0x3];
12309         u8         ebs_exponent[0x5];
12310         u8         ebs_mantissa[0x8];
12311         u8         reserved_at_90[0x3];
12312         u8         eir_exponent[0x5];
12313         u8         eir_mantissa[0x8];
12314
12315         u8         reserved_at_a0[0x60];
12316 };
12317
12318 struct mlx5_ifc_flow_meter_aso_obj_bits {
12319         u8         modify_field_select[0x40];
12320
12321         u8         reserved_at_40[0x40];
12322
12323         u8         reserved_at_80[0x8];
12324         u8         meter_aso_access_pd[0x18];
12325
12326         u8         reserved_at_a0[0x160];
12327
12328         struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12329 };
12330
12331 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12332         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12333         struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12334 };
12335
12336 struct mlx5_ifc_int_kek_obj_bits {
12337         u8         modify_field_select[0x40];
12338
12339         u8         state[0x8];
12340         u8         auto_gen[0x1];
12341         u8         reserved_at_49[0xb];
12342         u8         key_size[0x4];
12343         u8         reserved_at_58[0x8];
12344
12345         u8         reserved_at_60[0x8];
12346         u8         pd[0x18];
12347
12348         u8         reserved_at_80[0x180];
12349         u8         key[8][0x80];
12350
12351         u8         reserved_at_600[0x200];
12352 };
12353
12354 struct mlx5_ifc_create_int_kek_obj_in_bits {
12355         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12356         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12357 };
12358
12359 struct mlx5_ifc_create_int_kek_obj_out_bits {
12360         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12361         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12362 };
12363
12364 struct mlx5_ifc_sampler_obj_bits {
12365         u8         modify_field_select[0x40];
12366
12367         u8         table_type[0x8];
12368         u8         level[0x8];
12369         u8         reserved_at_50[0xf];
12370         u8         ignore_flow_level[0x1];
12371
12372         u8         sample_ratio[0x20];
12373
12374         u8         reserved_at_80[0x8];
12375         u8         sample_table_id[0x18];
12376
12377         u8         reserved_at_a0[0x8];
12378         u8         default_table_id[0x18];
12379
12380         u8         sw_steering_icm_address_rx[0x40];
12381         u8         sw_steering_icm_address_tx[0x40];
12382
12383         u8         reserved_at_140[0xa0];
12384 };
12385
12386 struct mlx5_ifc_create_sampler_obj_in_bits {
12387         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12388         struct mlx5_ifc_sampler_obj_bits sampler_object;
12389 };
12390
12391 struct mlx5_ifc_query_sampler_obj_out_bits {
12392         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12393         struct mlx5_ifc_sampler_obj_bits sampler_object;
12394 };
12395
12396 enum {
12397         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12398         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12399 };
12400
12401 enum {
12402         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12403         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12404         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12405 };
12406
12407 struct mlx5_ifc_tls_static_params_bits {
12408         u8         const_2[0x2];
12409         u8         tls_version[0x4];
12410         u8         const_1[0x2];
12411         u8         reserved_at_8[0x14];
12412         u8         encryption_standard[0x4];
12413
12414         u8         reserved_at_20[0x20];
12415
12416         u8         initial_record_number[0x40];
12417
12418         u8         resync_tcp_sn[0x20];
12419
12420         u8         gcm_iv[0x20];
12421
12422         u8         implicit_iv[0x40];
12423
12424         u8         reserved_at_100[0x8];
12425         u8         dek_index[0x18];
12426
12427         u8         reserved_at_120[0xe0];
12428 };
12429
12430 struct mlx5_ifc_tls_progress_params_bits {
12431         u8         next_record_tcp_sn[0x20];
12432
12433         u8         hw_resync_tcp_sn[0x20];
12434
12435         u8         record_tracker_state[0x2];
12436         u8         auth_state[0x2];
12437         u8         reserved_at_44[0x4];
12438         u8         hw_offset_record_number[0x18];
12439 };
12440
12441 enum {
12442         MLX5_MTT_PERM_READ      = 1 << 0,
12443         MLX5_MTT_PERM_WRITE     = 1 << 1,
12444         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12445 };
12446
12447 enum {
12448         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12449         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12450 };
12451
12452 struct mlx5_ifc_suspend_vhca_in_bits {
12453         u8         opcode[0x10];
12454         u8         uid[0x10];
12455
12456         u8         reserved_at_20[0x10];
12457         u8         op_mod[0x10];
12458
12459         u8         reserved_at_40[0x10];
12460         u8         vhca_id[0x10];
12461
12462         u8         reserved_at_60[0x20];
12463 };
12464
12465 struct mlx5_ifc_suspend_vhca_out_bits {
12466         u8         status[0x8];
12467         u8         reserved_at_8[0x18];
12468
12469         u8         syndrome[0x20];
12470
12471         u8         reserved_at_40[0x40];
12472 };
12473
12474 enum {
12475         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12476         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12477 };
12478
12479 struct mlx5_ifc_resume_vhca_in_bits {
12480         u8         opcode[0x10];
12481         u8         uid[0x10];
12482
12483         u8         reserved_at_20[0x10];
12484         u8         op_mod[0x10];
12485
12486         u8         reserved_at_40[0x10];
12487         u8         vhca_id[0x10];
12488
12489         u8         reserved_at_60[0x20];
12490 };
12491
12492 struct mlx5_ifc_resume_vhca_out_bits {
12493         u8         status[0x8];
12494         u8         reserved_at_8[0x18];
12495
12496         u8         syndrome[0x20];
12497
12498         u8         reserved_at_40[0x40];
12499 };
12500
12501 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12502         u8         opcode[0x10];
12503         u8         uid[0x10];
12504
12505         u8         reserved_at_20[0x10];
12506         u8         op_mod[0x10];
12507
12508         u8         incremental[0x1];
12509         u8         chunk[0x1];
12510         u8         reserved_at_42[0xe];
12511         u8         vhca_id[0x10];
12512
12513         u8         reserved_at_60[0x20];
12514 };
12515
12516 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12517         u8         status[0x8];
12518         u8         reserved_at_8[0x18];
12519
12520         u8         syndrome[0x20];
12521
12522         u8         reserved_at_40[0x40];
12523
12524         u8         required_umem_size[0x20];
12525
12526         u8         reserved_at_a0[0x20];
12527
12528         u8         remaining_total_size[0x40];
12529
12530         u8         reserved_at_100[0x100];
12531 };
12532
12533 struct mlx5_ifc_save_vhca_state_in_bits {
12534         u8         opcode[0x10];
12535         u8         uid[0x10];
12536
12537         u8         reserved_at_20[0x10];
12538         u8         op_mod[0x10];
12539
12540         u8         incremental[0x1];
12541         u8         set_track[0x1];
12542         u8         reserved_at_42[0xe];
12543         u8         vhca_id[0x10];
12544
12545         u8         reserved_at_60[0x20];
12546
12547         u8         va[0x40];
12548
12549         u8         mkey[0x20];
12550
12551         u8         size[0x20];
12552 };
12553
12554 struct mlx5_ifc_save_vhca_state_out_bits {
12555         u8         status[0x8];
12556         u8         reserved_at_8[0x18];
12557
12558         u8         syndrome[0x20];
12559
12560         u8         actual_image_size[0x20];
12561
12562         u8         next_required_umem_size[0x20];
12563 };
12564
12565 struct mlx5_ifc_load_vhca_state_in_bits {
12566         u8         opcode[0x10];
12567         u8         uid[0x10];
12568
12569         u8         reserved_at_20[0x10];
12570         u8         op_mod[0x10];
12571
12572         u8         reserved_at_40[0x10];
12573         u8         vhca_id[0x10];
12574
12575         u8         reserved_at_60[0x20];
12576
12577         u8         va[0x40];
12578
12579         u8         mkey[0x20];
12580
12581         u8         size[0x20];
12582 };
12583
12584 struct mlx5_ifc_load_vhca_state_out_bits {
12585         u8         status[0x8];
12586         u8         reserved_at_8[0x18];
12587
12588         u8         syndrome[0x20];
12589
12590         u8         reserved_at_40[0x40];
12591 };
12592
12593 struct mlx5_ifc_adv_virtualization_cap_bits {
12594         u8         reserved_at_0[0x3];
12595         u8         pg_track_log_max_num[0x5];
12596         u8         pg_track_max_num_range[0x8];
12597         u8         pg_track_log_min_addr_space[0x8];
12598         u8         pg_track_log_max_addr_space[0x8];
12599
12600         u8         reserved_at_20[0x3];
12601         u8         pg_track_log_min_msg_size[0x5];
12602         u8         reserved_at_28[0x3];
12603         u8         pg_track_log_max_msg_size[0x5];
12604         u8         reserved_at_30[0x3];
12605         u8         pg_track_log_min_page_size[0x5];
12606         u8         reserved_at_38[0x3];
12607         u8         pg_track_log_max_page_size[0x5];
12608
12609         u8         reserved_at_40[0x7c0];
12610 };
12611
12612 struct mlx5_ifc_page_track_report_entry_bits {
12613         u8         dirty_address_high[0x20];
12614
12615         u8         dirty_address_low[0x20];
12616 };
12617
12618 enum {
12619         MLX5_PAGE_TRACK_STATE_TRACKING,
12620         MLX5_PAGE_TRACK_STATE_REPORTING,
12621         MLX5_PAGE_TRACK_STATE_ERROR,
12622 };
12623
12624 struct mlx5_ifc_page_track_range_bits {
12625         u8         start_address[0x40];
12626
12627         u8         length[0x40];
12628 };
12629
12630 struct mlx5_ifc_page_track_bits {
12631         u8         modify_field_select[0x40];
12632
12633         u8         reserved_at_40[0x10];
12634         u8         vhca_id[0x10];
12635
12636         u8         reserved_at_60[0x20];
12637
12638         u8         state[0x4];
12639         u8         track_type[0x4];
12640         u8         log_addr_space_size[0x8];
12641         u8         reserved_at_90[0x3];
12642         u8         log_page_size[0x5];
12643         u8         reserved_at_98[0x3];
12644         u8         log_msg_size[0x5];
12645
12646         u8         reserved_at_a0[0x8];
12647         u8         reporting_qpn[0x18];
12648
12649         u8         reserved_at_c0[0x18];
12650         u8         num_ranges[0x8];
12651
12652         u8         reserved_at_e0[0x20];
12653
12654         u8         range_start_address[0x40];
12655
12656         u8         length[0x40];
12657
12658         struct     mlx5_ifc_page_track_range_bits track_range[0];
12659 };
12660
12661 struct mlx5_ifc_create_page_track_obj_in_bits {
12662         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12663         struct mlx5_ifc_page_track_bits obj_context;
12664 };
12665
12666 struct mlx5_ifc_modify_page_track_obj_in_bits {
12667         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12668         struct mlx5_ifc_page_track_bits obj_context;
12669 };
12670
12671 struct mlx5_ifc_msecq_reg_bits {
12672         u8         reserved_at_0[0x20];
12673
12674         u8         reserved_at_20[0x12];
12675         u8         network_option[0x2];
12676         u8         local_ssm_code[0x4];
12677         u8         local_enhanced_ssm_code[0x8];
12678
12679         u8         local_clock_identity[0x40];
12680
12681         u8         reserved_at_80[0x180];
12682 };
12683
12684 enum {
12685         MLX5_MSEES_FIELD_SELECT_ENABLE                  = BIT(0),
12686         MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS            = BIT(1),
12687         MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE      = BIT(2),
12688 };
12689
12690 enum mlx5_msees_admin_status {
12691         MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING            = 0x0,
12692         MLX5_MSEES_ADMIN_STATUS_TRACK                   = 0x1,
12693 };
12694
12695 enum mlx5_msees_oper_status {
12696         MLX5_MSEES_OPER_STATUS_FREE_RUNNING             = 0x0,
12697         MLX5_MSEES_OPER_STATUS_SELF_TRACK               = 0x1,
12698         MLX5_MSEES_OPER_STATUS_OTHER_TRACK              = 0x2,
12699         MLX5_MSEES_OPER_STATUS_HOLDOVER                 = 0x3,
12700         MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER            = 0x4,
12701         MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING        = 0x5,
12702 };
12703
12704 struct mlx5_ifc_msees_reg_bits {
12705         u8         reserved_at_0[0x8];
12706         u8         local_port[0x8];
12707         u8         pnat[0x2];
12708         u8         lp_msb[0x2];
12709         u8         reserved_at_14[0xc];
12710
12711         u8         field_select[0x20];
12712
12713         u8         admin_status[0x4];
12714         u8         oper_status[0x4];
12715         u8         ho_acq[0x1];
12716         u8         reserved_at_49[0xc];
12717         u8         admin_freq_measure[0x1];
12718         u8         oper_freq_measure[0x1];
12719         u8         failure_reason[0x9];
12720
12721         u8         frequency_diff[0x20];
12722
12723         u8         reserved_at_80[0x180];
12724 };
12725
12726 #endif /* MLX5_IFC_H */