include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  97         MLX5_OBJ_TYPE_MKEY = 0xff01,
  98         MLX5_OBJ_TYPE_QP = 0xff02,
  99         MLX5_OBJ_TYPE_PSV = 0xff03,
 100         MLX5_OBJ_TYPE_RMP = 0xff04,
 101         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 102         MLX5_OBJ_TYPE_RQ = 0xff06,
 103         MLX5_OBJ_TYPE_SQ = 0xff07,
 104         MLX5_OBJ_TYPE_TIR = 0xff08,
 105         MLX5_OBJ_TYPE_TIS = 0xff09,
 106         MLX5_OBJ_TYPE_DCT = 0xff0a,
 107         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 108         MLX5_OBJ_TYPE_RQT = 0xff0e,
 109         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 110         MLX5_OBJ_TYPE_CQ = 0xff10,
 111 };
 112
 113 enum {
 114         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 115         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 116         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 117         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 118         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 119         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 120         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 121         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 122         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 123         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 124         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 125         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 126         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 127         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 128         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 129         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 130         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 131         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 132         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 133         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 134         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 135         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 136         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 137         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 138         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 139         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 140         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 141         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 142         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 143         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 144         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 145         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 146         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 147         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 148         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 149         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 150         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 151         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 152         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 153         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 154         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 155         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 156         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 157         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 158         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 159         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 160         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 161         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 162         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 163         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 164         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 165         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 166         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 167         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 168         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 169         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 170         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 171         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 172         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 173         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 174         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 175         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 176         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 177         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 178         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 179         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 180         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 181         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 182         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 183         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 184         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 185         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 186         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 187         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 188         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 189         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 191         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 192         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 193         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 194         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 195         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 196         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 197         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 198         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 199         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 200         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 201         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 202         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 203         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 204         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 205         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 206         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 207         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 208         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 209         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 210         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 211         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 212         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 213         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 214         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 215         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 216         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 217         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 218         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 219         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 220         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 221         MLX5_CMD_OP_NOP                           = 0x80d,
 222         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 223         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 224         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 225         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 226         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 227         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 228         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 229         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 230         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 231         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 232         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 233         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 234         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 235         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 236         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 237         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 238         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 239         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 240         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 241         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 242         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 243         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 244         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 245         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 246         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 247         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 248         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 249         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 250         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 251         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 252         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 253         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 254         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 255         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 256         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 257         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 258         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 259         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 260         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 261         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 262         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 263         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 264         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 265         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 266         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 267         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 268         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 269         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 270         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 271         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 272         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 273         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 274         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 275         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 276         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 277         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 278         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 279         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 280         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 281         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 282         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 283         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 284         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 285         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 286         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 287         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 288         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 289         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 290         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 291         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 292         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 293         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 294         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 295         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 296         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 297         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 298         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 299         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 300         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 301         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 302         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 303         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 304         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 305         MLX5_CMD_OP_MAX
 306 };
 307
 308 /* Valid range for general commands that don't work over an object */
 309 enum {
 310         MLX5_CMD_OP_GENERAL_START = 0xb00,
 311         MLX5_CMD_OP_GENERAL_END = 0xd00,
 312 };
 313
 314 struct mlx5_ifc_flow_table_fields_supported_bits {
 315         u8         outer_dmac[0x1];
 316         u8         outer_smac[0x1];
 317         u8         outer_ether_type[0x1];
 318         u8         outer_ip_version[0x1];
 319         u8         outer_first_prio[0x1];
 320         u8         outer_first_cfi[0x1];
 321         u8         outer_first_vid[0x1];
 322         u8         outer_ipv4_ttl[0x1];
 323         u8         outer_second_prio[0x1];
 324         u8         outer_second_cfi[0x1];
 325         u8         outer_second_vid[0x1];
 326         u8         reserved_at_b[0x1];
 327         u8         outer_sip[0x1];
 328         u8         outer_dip[0x1];
 329         u8         outer_frag[0x1];
 330         u8         outer_ip_protocol[0x1];
 331         u8         outer_ip_ecn[0x1];
 332         u8         outer_ip_dscp[0x1];
 333         u8         outer_udp_sport[0x1];
 334         u8         outer_udp_dport[0x1];
 335         u8         outer_tcp_sport[0x1];
 336         u8         outer_tcp_dport[0x1];
 337         u8         outer_tcp_flags[0x1];
 338         u8         outer_gre_protocol[0x1];
 339         u8         outer_gre_key[0x1];
 340         u8         outer_vxlan_vni[0x1];
 341         u8         outer_geneve_vni[0x1];
 342         u8         outer_geneve_oam[0x1];
 343         u8         outer_geneve_protocol_type[0x1];
 344         u8         outer_geneve_opt_len[0x1];
 345         u8         reserved_at_1e[0x1];
 346         u8         source_eswitch_port[0x1];
 347
 348         u8         inner_dmac[0x1];
 349         u8         inner_smac[0x1];
 350         u8         inner_ether_type[0x1];
 351         u8         inner_ip_version[0x1];
 352         u8         inner_first_prio[0x1];
 353         u8         inner_first_cfi[0x1];
 354         u8         inner_first_vid[0x1];
 355         u8         reserved_at_27[0x1];
 356         u8         inner_second_prio[0x1];
 357         u8         inner_second_cfi[0x1];
 358         u8         inner_second_vid[0x1];
 359         u8         reserved_at_2b[0x1];
 360         u8         inner_sip[0x1];
 361         u8         inner_dip[0x1];
 362         u8         inner_frag[0x1];
 363         u8         inner_ip_protocol[0x1];
 364         u8         inner_ip_ecn[0x1];
 365         u8         inner_ip_dscp[0x1];
 366         u8         inner_udp_sport[0x1];
 367         u8         inner_udp_dport[0x1];
 368         u8         inner_tcp_sport[0x1];
 369         u8         inner_tcp_dport[0x1];
 370         u8         inner_tcp_flags[0x1];
 371         u8         reserved_at_37[0x9];
 372
 373         u8         geneve_tlv_option_0_data[0x1];
 374         u8         reserved_at_41[0x4];
 375         u8         outer_first_mpls_over_udp[0x4];
 376         u8         outer_first_mpls_over_gre[0x4];
 377         u8         inner_first_mpls[0x4];
 378         u8         outer_first_mpls[0x4];
 379         u8         reserved_at_55[0x2];
 380         u8         outer_esp_spi[0x1];
 381         u8         reserved_at_58[0x2];
 382         u8         bth_dst_qp[0x1];
 383         u8         reserved_at_5b[0x5];
 384
 385         u8         reserved_at_60[0x18];
 386         u8         metadata_reg_c_7[0x1];
 387         u8         metadata_reg_c_6[0x1];
 388         u8         metadata_reg_c_5[0x1];
 389         u8         metadata_reg_c_4[0x1];
 390         u8         metadata_reg_c_3[0x1];
 391         u8         metadata_reg_c_2[0x1];
 392         u8         metadata_reg_c_1[0x1];
 393         u8         metadata_reg_c_0[0x1];
 394 };
 395
 396 struct mlx5_ifc_flow_table_prop_layout_bits {
 397         u8         ft_support[0x1];
 398         u8         reserved_at_1[0x1];
 399         u8         flow_counter[0x1];
 400         u8         flow_modify_en[0x1];
 401         u8         modify_root[0x1];
 402         u8         identified_miss_table_mode[0x1];
 403         u8         flow_table_modify[0x1];
 404         u8         reformat[0x1];
 405         u8         decap[0x1];
 406         u8         reserved_at_9[0x1];
 407         u8         pop_vlan[0x1];
 408         u8         push_vlan[0x1];
 409         u8         reserved_at_c[0x1];
 410         u8         pop_vlan_2[0x1];
 411         u8         push_vlan_2[0x1];
 412         u8         reformat_and_vlan_action[0x1];
 413         u8         reserved_at_10[0x1];
 414         u8         sw_owner[0x1];
 415         u8         reformat_l3_tunnel_to_l2[0x1];
 416         u8         reformat_l2_to_l3_tunnel[0x1];
 417         u8         reformat_and_modify_action[0x1];
 418         u8         ignore_flow_level[0x1];
 419         u8         reserved_at_16[0x1];
 420         u8         table_miss_action_domain[0x1];
 421         u8         termination_table[0x1];
 422         u8         reformat_and_fwd_to_table[0x1];
 423         u8         reserved_at_1a[0x2];
 424         u8         ipsec_encrypt[0x1];
 425         u8         ipsec_decrypt[0x1];
 426         u8         sw_owner_v2[0x1];
 427         u8         reserved_at_1f[0x1];
 428
 429         u8         termination_table_raw_traffic[0x1];
 430         u8         reserved_at_21[0x1];
 431         u8         log_max_ft_size[0x6];
 432         u8         log_max_modify_header_context[0x8];
 433         u8         max_modify_header_actions[0x8];
 434         u8         max_ft_level[0x8];
 435
 436         u8         reserved_at_40[0x20];
 437
 438         u8         reserved_at_60[0x2];
 439         u8         reformat_insert[0x1];
 440         u8         reformat_remove[0x1];
 441         u8         reserver_at_64[0x14];
 442         u8         log_max_ft_num[0x8];
 443
 444         u8         reserved_at_80[0x10];
 445         u8         log_max_flow_counter[0x8];
 446         u8         log_max_destination[0x8];
 447
 448         u8         reserved_at_a0[0x18];
 449         u8         log_max_flow[0x8];
 450
 451         u8         reserved_at_c0[0x40];
 452
 453         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 454
 455         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 456 };
 457
 458 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 459         u8         send[0x1];
 460         u8         receive[0x1];
 461         u8         write[0x1];
 462         u8         read[0x1];
 463         u8         atomic[0x1];
 464         u8         srq_receive[0x1];
 465         u8         reserved_at_6[0x1a];
 466 };
 467
 468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 469         u8         smac_47_16[0x20];
 470
 471         u8         smac_15_0[0x10];
 472         u8         ethertype[0x10];
 473
 474         u8         dmac_47_16[0x20];
 475
 476         u8         dmac_15_0[0x10];
 477         u8         first_prio[0x3];
 478         u8         first_cfi[0x1];
 479         u8         first_vid[0xc];
 480
 481         u8         ip_protocol[0x8];
 482         u8         ip_dscp[0x6];
 483         u8         ip_ecn[0x2];
 484         u8         cvlan_tag[0x1];
 485         u8         svlan_tag[0x1];
 486         u8         frag[0x1];
 487         u8         ip_version[0x4];
 488         u8         tcp_flags[0x9];
 489
 490         u8         tcp_sport[0x10];
 491         u8         tcp_dport[0x10];
 492
 493         u8         reserved_at_c0[0x18];
 494         u8         ttl_hoplimit[0x8];
 495
 496         u8         udp_sport[0x10];
 497         u8         udp_dport[0x10];
 498
 499         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 500
 501         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 502 };
 503
 504 struct mlx5_ifc_nvgre_key_bits {
 505         u8 hi[0x18];
 506         u8 lo[0x8];
 507 };
 508
 509 union mlx5_ifc_gre_key_bits {
 510         struct mlx5_ifc_nvgre_key_bits nvgre;
 511         u8 key[0x20];
 512 };
 513
 514 struct mlx5_ifc_fte_match_set_misc_bits {
 515         u8         gre_c_present[0x1];
 516         u8         reserved_at_1[0x1];
 517         u8         gre_k_present[0x1];
 518         u8         gre_s_present[0x1];
 519         u8         source_vhca_port[0x4];
 520         u8         source_sqn[0x18];
 521
 522         u8         source_eswitch_owner_vhca_id[0x10];
 523         u8         source_port[0x10];
 524
 525         u8         outer_second_prio[0x3];
 526         u8         outer_second_cfi[0x1];
 527         u8         outer_second_vid[0xc];
 528         u8         inner_second_prio[0x3];
 529         u8         inner_second_cfi[0x1];
 530         u8         inner_second_vid[0xc];
 531
 532         u8         outer_second_cvlan_tag[0x1];
 533         u8         inner_second_cvlan_tag[0x1];
 534         u8         outer_second_svlan_tag[0x1];
 535         u8         inner_second_svlan_tag[0x1];
 536         u8         reserved_at_64[0xc];
 537         u8         gre_protocol[0x10];
 538
 539         union mlx5_ifc_gre_key_bits gre_key;
 540
 541         u8         vxlan_vni[0x18];
 542         u8         reserved_at_b8[0x8];
 543
 544         u8         geneve_vni[0x18];
 545         u8         reserved_at_d8[0x7];
 546         u8         geneve_oam[0x1];
 547
 548         u8         reserved_at_e0[0xc];
 549         u8         outer_ipv6_flow_label[0x14];
 550
 551         u8         reserved_at_100[0xc];
 552         u8         inner_ipv6_flow_label[0x14];
 553
 554         u8         reserved_at_120[0xa];
 555         u8         geneve_opt_len[0x6];
 556         u8         geneve_protocol_type[0x10];
 557
 558         u8         reserved_at_140[0x8];
 559         u8         bth_dst_qp[0x18];
 560         u8         reserved_at_160[0x20];
 561         u8         outer_esp_spi[0x20];
 562         u8         reserved_at_1a0[0x60];
 563 };
 564
 565 struct mlx5_ifc_fte_match_mpls_bits {
 566         u8         mpls_label[0x14];
 567         u8         mpls_exp[0x3];
 568         u8         mpls_s_bos[0x1];
 569         u8         mpls_ttl[0x8];
 570 };
 571
 572 struct mlx5_ifc_fte_match_set_misc2_bits {
 573         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 574
 575         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 576
 577         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 578
 579         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 580
 581         u8         metadata_reg_c_7[0x20];
 582
 583         u8         metadata_reg_c_6[0x20];
 584
 585         u8         metadata_reg_c_5[0x20];
 586
 587         u8         metadata_reg_c_4[0x20];
 588
 589         u8         metadata_reg_c_3[0x20];
 590
 591         u8         metadata_reg_c_2[0x20];
 592
 593         u8         metadata_reg_c_1[0x20];
 594
 595         u8         metadata_reg_c_0[0x20];
 596
 597         u8         metadata_reg_a[0x20];
 598
 599         u8         reserved_at_1a0[0x60];
 600 };
 601
 602 struct mlx5_ifc_fte_match_set_misc3_bits {
 603         u8         inner_tcp_seq_num[0x20];
 604
 605         u8         outer_tcp_seq_num[0x20];
 606
 607         u8         inner_tcp_ack_num[0x20];
 608
 609         u8         outer_tcp_ack_num[0x20];
 610
 611         u8         reserved_at_80[0x8];
 612         u8         outer_vxlan_gpe_vni[0x18];
 613
 614         u8         outer_vxlan_gpe_next_protocol[0x8];
 615         u8         outer_vxlan_gpe_flags[0x8];
 616         u8         reserved_at_b0[0x10];
 617
 618         u8         icmp_header_data[0x20];
 619
 620         u8         icmpv6_header_data[0x20];
 621
 622         u8         icmp_type[0x8];
 623         u8         icmp_code[0x8];
 624         u8         icmpv6_type[0x8];
 625         u8         icmpv6_code[0x8];
 626
 627         u8         geneve_tlv_option_0_data[0x20];
 628
 629         u8         gtpu_teid[0x20];
 630
 631         u8         gtpu_msg_type[0x8];
 632         u8         gtpu_msg_flags[0x8];
 633         u8         reserved_at_170[0x10];
 634
 635         u8         gtpu_dw_2[0x20];
 636
 637         u8         gtpu_first_ext_dw_0[0x20];
 638
 639         u8         gtpu_dw_0[0x20];
 640
 641         u8         reserved_at_1e0[0x20];
 642 };
 643
 644 struct mlx5_ifc_fte_match_set_misc4_bits {
 645         u8         prog_sample_field_value_0[0x20];
 646
 647         u8         prog_sample_field_id_0[0x20];
 648
 649         u8         prog_sample_field_value_1[0x20];
 650
 651         u8         prog_sample_field_id_1[0x20];
 652
 653         u8         prog_sample_field_value_2[0x20];
 654
 655         u8         prog_sample_field_id_2[0x20];
 656
 657         u8         prog_sample_field_value_3[0x20];
 658
 659         u8         prog_sample_field_id_3[0x20];
 660
 661         u8         reserved_at_100[0x100];
 662 };
 663
 664 struct mlx5_ifc_cmd_pas_bits {
 665         u8         pa_h[0x20];
 666
 667         u8         pa_l[0x14];
 668         u8         reserved_at_34[0xc];
 669 };
 670
 671 struct mlx5_ifc_uint64_bits {
 672         u8         hi[0x20];
 673
 674         u8         lo[0x20];
 675 };
 676
 677 enum {
 678         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 679         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 680         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 681         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 682         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 683         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 684         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 685         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 686         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 687         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 688 };
 689
 690 struct mlx5_ifc_ads_bits {
 691         u8         fl[0x1];
 692         u8         free_ar[0x1];
 693         u8         reserved_at_2[0xe];
 694         u8         pkey_index[0x10];
 695
 696         u8         reserved_at_20[0x8];
 697         u8         grh[0x1];
 698         u8         mlid[0x7];
 699         u8         rlid[0x10];
 700
 701         u8         ack_timeout[0x5];
 702         u8         reserved_at_45[0x3];
 703         u8         src_addr_index[0x8];
 704         u8         reserved_at_50[0x4];
 705         u8         stat_rate[0x4];
 706         u8         hop_limit[0x8];
 707
 708         u8         reserved_at_60[0x4];
 709         u8         tclass[0x8];
 710         u8         flow_label[0x14];
 711
 712         u8         rgid_rip[16][0x8];
 713
 714         u8         reserved_at_100[0x4];
 715         u8         f_dscp[0x1];
 716         u8         f_ecn[0x1];
 717         u8         reserved_at_106[0x1];
 718         u8         f_eth_prio[0x1];
 719         u8         ecn[0x2];
 720         u8         dscp[0x6];
 721         u8         udp_sport[0x10];
 722
 723         u8         dei_cfi[0x1];
 724         u8         eth_prio[0x3];
 725         u8         sl[0x4];
 726         u8         vhca_port_num[0x8];
 727         u8         rmac_47_32[0x10];
 728
 729         u8         rmac_31_0[0x20];
 730 };
 731
 732 struct mlx5_ifc_flow_table_nic_cap_bits {
 733         u8         nic_rx_multi_path_tirs[0x1];
 734         u8         nic_rx_multi_path_tirs_fts[0x1];
 735         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 736         u8         reserved_at_3[0x4];
 737         u8         sw_owner_reformat_supported[0x1];
 738         u8         reserved_at_8[0x18];
 739
 740         u8         encap_general_header[0x1];
 741         u8         reserved_at_21[0xa];
 742         u8         log_max_packet_reformat_context[0x5];
 743         u8         reserved_at_30[0x6];
 744         u8         max_encap_header_size[0xa];
 745         u8         reserved_at_40[0x1c0];
 746
 747         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 748
 749         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 754
 755         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 756
 757         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 758
 759         u8         reserved_at_e00[0x1200];
 760
 761         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 762
 763         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 764
 765         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 766
 767         u8         reserved_at_20c0[0x5f40];
 768 };
 769
 770 enum {
 771         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 772         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 773         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 774         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 775         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 776         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 777         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 778         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 779 };
 780
 781 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 782         u8      fdb_to_vport_reg_c_id[0x8];
 783         u8      reserved_at_8[0xd];
 784         u8      fdb_modify_header_fwd_to_table[0x1];
 785         u8      reserved_at_16[0x1];
 786         u8      flow_source[0x1];
 787         u8      reserved_at_18[0x2];
 788         u8      multi_fdb_encap[0x1];
 789         u8      egress_acl_forward_to_vport[0x1];
 790         u8      fdb_multi_path_to_table[0x1];
 791         u8      reserved_at_1d[0x3];
 792
 793         u8      reserved_at_20[0x1e0];
 794
 795         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 796
 797         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 798
 799         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 800
 801         u8      reserved_at_800[0x1000];
 802
 803         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 804
 805         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 806
 807         u8      sw_steering_uplink_icm_address_rx[0x40];
 808
 809         u8      sw_steering_uplink_icm_address_tx[0x40];
 810
 811         u8      reserved_at_1900[0x6700];
 812 };
 813
 814 enum {
 815         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 816         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 817 };
 818
 819 struct mlx5_ifc_e_switch_cap_bits {
 820         u8         vport_svlan_strip[0x1];
 821         u8         vport_cvlan_strip[0x1];
 822         u8         vport_svlan_insert[0x1];
 823         u8         vport_cvlan_insert_if_not_exist[0x1];
 824         u8         vport_cvlan_insert_overwrite[0x1];
 825         u8         reserved_at_5[0x2];
 826         u8         esw_shared_ingress_acl[0x1];
 827         u8         esw_uplink_ingress_acl[0x1];
 828         u8         root_ft_on_other_esw[0x1];
 829         u8         reserved_at_a[0xf];
 830         u8         esw_functions_changed[0x1];
 831         u8         reserved_at_1a[0x1];
 832         u8         ecpf_vport_exists[0x1];
 833         u8         counter_eswitch_affinity[0x1];
 834         u8         merged_eswitch[0x1];
 835         u8         nic_vport_node_guid_modify[0x1];
 836         u8         nic_vport_port_guid_modify[0x1];
 837
 838         u8         vxlan_encap_decap[0x1];
 839         u8         nvgre_encap_decap[0x1];
 840         u8         reserved_at_22[0x1];
 841         u8         log_max_fdb_encap_uplink[0x5];
 842         u8         reserved_at_21[0x3];
 843         u8         log_max_packet_reformat_context[0x5];
 844         u8         reserved_2b[0x6];
 845         u8         max_encap_header_size[0xa];
 846
 847         u8         reserved_at_40[0xb];
 848         u8         log_max_esw_sf[0x5];
 849         u8         esw_sf_base_id[0x10];
 850
 851         u8         reserved_at_60[0x7a0];
 852
 853 };
 854
 855 struct mlx5_ifc_qos_cap_bits {
 856         u8         packet_pacing[0x1];
 857         u8         esw_scheduling[0x1];
 858         u8         esw_bw_share[0x1];
 859         u8         esw_rate_limit[0x1];
 860         u8         reserved_at_4[0x1];
 861         u8         packet_pacing_burst_bound[0x1];
 862         u8         packet_pacing_typical_size[0x1];
 863         u8         reserved_at_7[0x1];
 864         u8         nic_sq_scheduling[0x1];
 865         u8         nic_bw_share[0x1];
 866         u8         nic_rate_limit[0x1];
 867         u8         packet_pacing_uid[0x1];
 868         u8         log_esw_max_sched_depth[0x4];
 869         u8         reserved_at_10[0x10];
 870
 871         u8         reserved_at_20[0xb];
 872         u8         log_max_qos_nic_queue_group[0x5];
 873         u8         reserved_at_30[0x10];
 874
 875         u8         packet_pacing_max_rate[0x20];
 876
 877         u8         packet_pacing_min_rate[0x20];
 878
 879         u8         reserved_at_80[0x10];
 880         u8         packet_pacing_rate_table_size[0x10];
 881
 882         u8         esw_element_type[0x10];
 883         u8         esw_tsar_type[0x10];
 884
 885         u8         reserved_at_c0[0x10];
 886         u8         max_qos_para_vport[0x10];
 887
 888         u8         max_tsar_bw_share[0x20];
 889
 890         u8         reserved_at_100[0x700];
 891 };
 892
 893 struct mlx5_ifc_debug_cap_bits {
 894         u8         core_dump_general[0x1];
 895         u8         core_dump_qp[0x1];
 896         u8         reserved_at_2[0x7];
 897         u8         resource_dump[0x1];
 898         u8         reserved_at_a[0x16];
 899
 900         u8         reserved_at_20[0x2];
 901         u8         stall_detect[0x1];
 902         u8         reserved_at_23[0x1d];
 903
 904         u8         reserved_at_40[0x7c0];
 905 };
 906
 907 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 908         u8         csum_cap[0x1];
 909         u8         vlan_cap[0x1];
 910         u8         lro_cap[0x1];
 911         u8         lro_psh_flag[0x1];
 912         u8         lro_time_stamp[0x1];
 913         u8         reserved_at_5[0x2];
 914         u8         wqe_vlan_insert[0x1];
 915         u8         self_lb_en_modifiable[0x1];
 916         u8         reserved_at_9[0x2];
 917         u8         max_lso_cap[0x5];
 918         u8         multi_pkt_send_wqe[0x2];
 919         u8         wqe_inline_mode[0x2];
 920         u8         rss_ind_tbl_cap[0x4];
 921         u8         reg_umr_sq[0x1];
 922         u8         scatter_fcs[0x1];
 923         u8         enhanced_multi_pkt_send_wqe[0x1];
 924         u8         tunnel_lso_const_out_ip_id[0x1];
 925         u8         tunnel_lro_gre[0x1];
 926         u8         tunnel_lro_vxlan[0x1];
 927         u8         tunnel_stateless_gre[0x1];
 928         u8         tunnel_stateless_vxlan[0x1];
 929
 930         u8         swp[0x1];
 931         u8         swp_csum[0x1];
 932         u8         swp_lso[0x1];
 933         u8         cqe_checksum_full[0x1];
 934         u8         tunnel_stateless_geneve_tx[0x1];
 935         u8         tunnel_stateless_mpls_over_udp[0x1];
 936         u8         tunnel_stateless_mpls_over_gre[0x1];
 937         u8         tunnel_stateless_vxlan_gpe[0x1];
 938         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 939         u8         tunnel_stateless_ip_over_ip[0x1];
 940         u8         insert_trailer[0x1];
 941         u8         reserved_at_2b[0x1];
 942         u8         tunnel_stateless_ip_over_ip_rx[0x1];
 943         u8         tunnel_stateless_ip_over_ip_tx[0x1];
 944         u8         reserved_at_2e[0x2];
 945         u8         max_vxlan_udp_ports[0x8];
 946         u8         reserved_at_38[0x6];
 947         u8         max_geneve_opt_len[0x1];
 948         u8         tunnel_stateless_geneve_rx[0x1];
 949
 950         u8         reserved_at_40[0x10];
 951         u8         lro_min_mss_size[0x10];
 952
 953         u8         reserved_at_60[0x120];
 954
 955         u8         lro_timer_supported_periods[4][0x20];
 956
 957         u8         reserved_at_200[0x600];
 958 };
 959
 960 enum {
 961         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
 962         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
 963         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
 964 };
 965
 966 struct mlx5_ifc_roce_cap_bits {
 967         u8         roce_apm[0x1];
 968         u8         reserved_at_1[0x3];
 969         u8         sw_r_roce_src_udp_port[0x1];
 970         u8         fl_rc_qp_when_roce_disabled[0x1];
 971         u8         fl_rc_qp_when_roce_enabled[0x1];
 972         u8         reserved_at_7[0x17];
 973         u8         qp_ts_format[0x2];
 974
 975         u8         reserved_at_20[0x60];
 976
 977         u8         reserved_at_80[0xc];
 978         u8         l3_type[0x4];
 979         u8         reserved_at_90[0x8];
 980         u8         roce_version[0x8];
 981
 982         u8         reserved_at_a0[0x10];
 983         u8         r_roce_dest_udp_port[0x10];
 984
 985         u8         r_roce_max_src_udp_port[0x10];
 986         u8         r_roce_min_src_udp_port[0x10];
 987
 988         u8         reserved_at_e0[0x10];
 989         u8         roce_address_table_size[0x10];
 990
 991         u8         reserved_at_100[0x700];
 992 };
 993
 994 struct mlx5_ifc_sync_steering_in_bits {
 995         u8         opcode[0x10];
 996         u8         uid[0x10];
 997
 998         u8         reserved_at_20[0x10];
 999         u8         op_mod[0x10];
1000
1001         u8         reserved_at_40[0xc0];
1002 };
1003
1004 struct mlx5_ifc_sync_steering_out_bits {
1005         u8         status[0x8];
1006         u8         reserved_at_8[0x18];
1007
1008         u8         syndrome[0x20];
1009
1010         u8         reserved_at_40[0x40];
1011 };
1012
1013 struct mlx5_ifc_device_mem_cap_bits {
1014         u8         memic[0x1];
1015         u8         reserved_at_1[0x1f];
1016
1017         u8         reserved_at_20[0xb];
1018         u8         log_min_memic_alloc_size[0x5];
1019         u8         reserved_at_30[0x8];
1020         u8         log_max_memic_addr_alignment[0x8];
1021
1022         u8         memic_bar_start_addr[0x40];
1023
1024         u8         memic_bar_size[0x20];
1025
1026         u8         max_memic_size[0x20];
1027
1028         u8         steering_sw_icm_start_address[0x40];
1029
1030         u8         reserved_at_100[0x8];
1031         u8         log_header_modify_sw_icm_size[0x8];
1032         u8         reserved_at_110[0x2];
1033         u8         log_sw_icm_alloc_granularity[0x6];
1034         u8         log_steering_sw_icm_size[0x8];
1035
1036         u8         reserved_at_120[0x20];
1037
1038         u8         header_modify_sw_icm_start_address[0x40];
1039
1040         u8         reserved_at_180[0x80];
1041
1042         u8         memic_operations[0x20];
1043
1044         u8         reserved_at_220[0x5e0];
1045 };
1046
1047 struct mlx5_ifc_device_event_cap_bits {
1048         u8         user_affiliated_events[4][0x40];
1049
1050         u8         user_unaffiliated_events[4][0x40];
1051 };
1052
1053 struct mlx5_ifc_virtio_emulation_cap_bits {
1054         u8         desc_tunnel_offload_type[0x1];
1055         u8         eth_frame_offload_type[0x1];
1056         u8         virtio_version_1_0[0x1];
1057         u8         device_features_bits_mask[0xd];
1058         u8         event_mode[0x8];
1059         u8         virtio_queue_type[0x8];
1060
1061         u8         max_tunnel_desc[0x10];
1062         u8         reserved_at_30[0x3];
1063         u8         log_doorbell_stride[0x5];
1064         u8         reserved_at_38[0x3];
1065         u8         log_doorbell_bar_size[0x5];
1066
1067         u8         doorbell_bar_offset[0x40];
1068
1069         u8         max_emulated_devices[0x8];
1070         u8         max_num_virtio_queues[0x18];
1071
1072         u8         reserved_at_a0[0x60];
1073
1074         u8         umem_1_buffer_param_a[0x20];
1075
1076         u8         umem_1_buffer_param_b[0x20];
1077
1078         u8         umem_2_buffer_param_a[0x20];
1079
1080         u8         umem_2_buffer_param_b[0x20];
1081
1082         u8         umem_3_buffer_param_a[0x20];
1083
1084         u8         umem_3_buffer_param_b[0x20];
1085
1086         u8         reserved_at_1c0[0x640];
1087 };
1088
1089 enum {
1090         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1091         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1092         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1093         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1094         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1095         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1096         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1097         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1098         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1099 };
1100
1101 enum {
1102         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1103         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1104         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1105         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1106         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1107         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1108         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1109         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1110         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1111 };
1112
1113 struct mlx5_ifc_atomic_caps_bits {
1114         u8         reserved_at_0[0x40];
1115
1116         u8         atomic_req_8B_endianness_mode[0x2];
1117         u8         reserved_at_42[0x4];
1118         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1119
1120         u8         reserved_at_47[0x19];
1121
1122         u8         reserved_at_60[0x20];
1123
1124         u8         reserved_at_80[0x10];
1125         u8         atomic_operations[0x10];
1126
1127         u8         reserved_at_a0[0x10];
1128         u8         atomic_size_qp[0x10];
1129
1130         u8         reserved_at_c0[0x10];
1131         u8         atomic_size_dc[0x10];
1132
1133         u8         reserved_at_e0[0x720];
1134 };
1135
1136 struct mlx5_ifc_odp_cap_bits {
1137         u8         reserved_at_0[0x40];
1138
1139         u8         sig[0x1];
1140         u8         reserved_at_41[0x1f];
1141
1142         u8         reserved_at_60[0x20];
1143
1144         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1145
1146         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1147
1148         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1149
1150         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1151
1152         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1153
1154         u8         reserved_at_120[0x6E0];
1155 };
1156
1157 struct mlx5_ifc_calc_op {
1158         u8        reserved_at_0[0x10];
1159         u8        reserved_at_10[0x9];
1160         u8        op_swap_endianness[0x1];
1161         u8        op_min[0x1];
1162         u8        op_xor[0x1];
1163         u8        op_or[0x1];
1164         u8        op_and[0x1];
1165         u8        op_max[0x1];
1166         u8        op_add[0x1];
1167 };
1168
1169 struct mlx5_ifc_vector_calc_cap_bits {
1170         u8         calc_matrix[0x1];
1171         u8         reserved_at_1[0x1f];
1172         u8         reserved_at_20[0x8];
1173         u8         max_vec_count[0x8];
1174         u8         reserved_at_30[0xd];
1175         u8         max_chunk_size[0x3];
1176         struct mlx5_ifc_calc_op calc0;
1177         struct mlx5_ifc_calc_op calc1;
1178         struct mlx5_ifc_calc_op calc2;
1179         struct mlx5_ifc_calc_op calc3;
1180
1181         u8         reserved_at_c0[0x720];
1182 };
1183
1184 struct mlx5_ifc_tls_cap_bits {
1185         u8         tls_1_2_aes_gcm_128[0x1];
1186         u8         tls_1_3_aes_gcm_128[0x1];
1187         u8         tls_1_2_aes_gcm_256[0x1];
1188         u8         tls_1_3_aes_gcm_256[0x1];
1189         u8         reserved_at_4[0x1c];
1190
1191         u8         reserved_at_20[0x7e0];
1192 };
1193
1194 struct mlx5_ifc_ipsec_cap_bits {
1195         u8         ipsec_full_offload[0x1];
1196         u8         ipsec_crypto_offload[0x1];
1197         u8         ipsec_esn[0x1];
1198         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1199         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1200         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1201         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1202         u8         reserved_at_7[0x4];
1203         u8         log_max_ipsec_offload[0x5];
1204         u8         reserved_at_10[0x10];
1205
1206         u8         min_log_ipsec_full_replay_window[0x8];
1207         u8         max_log_ipsec_full_replay_window[0x8];
1208         u8         reserved_at_30[0x7d0];
1209 };
1210
1211 enum {
1212         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1213         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1214         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1215         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1216 };
1217
1218 enum {
1219         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1220         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1221 };
1222
1223 enum {
1224         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1225         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1226         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1227         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1228         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1229 };
1230
1231 enum {
1232         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1233         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1234         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1235         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1236         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1237         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1238 };
1239
1240 enum {
1241         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1242         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1243 };
1244
1245 enum {
1246         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1247         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1248         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1249 };
1250
1251 enum {
1252         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1253         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1254 };
1255
1256 enum {
1257         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1258         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1259         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1260 };
1261
1262 enum {
1263         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1264         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1265         mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1266         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1267         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1268         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1269         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1270         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1271         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1272         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1273         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1274         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1275 };
1276
1277 enum {
1278         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1279         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1280 };
1281
1282 #define MLX5_FC_BULK_SIZE_FACTOR 128
1283
1284 enum mlx5_fc_bulk_alloc_bitmask {
1285         MLX5_FC_BULK_128   = (1 << 0),
1286         MLX5_FC_BULK_256   = (1 << 1),
1287         MLX5_FC_BULK_512   = (1 << 2),
1288         MLX5_FC_BULK_1024  = (1 << 3),
1289         MLX5_FC_BULK_2048  = (1 << 4),
1290         MLX5_FC_BULK_4096  = (1 << 5),
1291         MLX5_FC_BULK_8192  = (1 << 6),
1292         MLX5_FC_BULK_16384 = (1 << 7),
1293 };
1294
1295 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1296
1297 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1298
1299 enum {
1300         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1301         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1302 };
1303
1304 struct mlx5_ifc_cmd_hca_cap_bits {
1305         u8         reserved_at_0[0x1f];
1306         u8         vhca_resource_manager[0x1];
1307
1308         u8         hca_cap_2[0x1];
1309         u8         reserved_at_21[0x1];
1310         u8         dtor[0x1];
1311         u8         event_on_vhca_state_teardown_request[0x1];
1312         u8         event_on_vhca_state_in_use[0x1];
1313         u8         event_on_vhca_state_active[0x1];
1314         u8         event_on_vhca_state_allocated[0x1];
1315         u8         event_on_vhca_state_invalid[0x1];
1316         u8         reserved_at_28[0x8];
1317         u8         vhca_id[0x10];
1318
1319         u8         reserved_at_40[0x40];
1320
1321         u8         log_max_srq_sz[0x8];
1322         u8         log_max_qp_sz[0x8];
1323         u8         event_cap[0x1];
1324         u8         reserved_at_91[0x2];
1325         u8         isolate_vl_tc_new[0x1];
1326         u8         reserved_at_94[0x4];
1327         u8         prio_tag_required[0x1];
1328         u8         reserved_at_99[0x2];
1329         u8         log_max_qp[0x5];
1330
1331         u8         reserved_at_a0[0x3];
1332         u8         ece_support[0x1];
1333         u8         reserved_at_a4[0x5];
1334         u8         reg_c_preserve[0x1];
1335         u8         reserved_at_aa[0x1];
1336         u8         log_max_srq[0x5];
1337         u8         reserved_at_b0[0x1];
1338         u8         uplink_follow[0x1];
1339         u8         ts_cqe_to_dest_cqn[0x1];
1340         u8         reserved_at_b3[0xd];
1341
1342         u8         max_sgl_for_optimized_performance[0x8];
1343         u8         log_max_cq_sz[0x8];
1344         u8         relaxed_ordering_write_umr[0x1];
1345         u8         relaxed_ordering_read_umr[0x1];
1346         u8         reserved_at_d2[0x7];
1347         u8         virtio_net_device_emualtion_manager[0x1];
1348         u8         virtio_blk_device_emualtion_manager[0x1];
1349         u8         log_max_cq[0x5];
1350
1351         u8         log_max_eq_sz[0x8];
1352         u8         relaxed_ordering_write[0x1];
1353         u8         relaxed_ordering_read[0x1];
1354         u8         log_max_mkey[0x6];
1355         u8         reserved_at_f0[0x8];
1356         u8         dump_fill_mkey[0x1];
1357         u8         reserved_at_f9[0x2];
1358         u8         fast_teardown[0x1];
1359         u8         log_max_eq[0x4];
1360
1361         u8         max_indirection[0x8];
1362         u8         fixed_buffer_size[0x1];
1363         u8         log_max_mrw_sz[0x7];
1364         u8         force_teardown[0x1];
1365         u8         reserved_at_111[0x1];
1366         u8         log_max_bsf_list_size[0x6];
1367         u8         umr_extended_translation_offset[0x1];
1368         u8         null_mkey[0x1];
1369         u8         log_max_klm_list_size[0x6];
1370
1371         u8         reserved_at_120[0xa];
1372         u8         log_max_ra_req_dc[0x6];
1373         u8         reserved_at_130[0xa];
1374         u8         log_max_ra_res_dc[0x6];
1375
1376         u8         reserved_at_140[0x6];
1377         u8         release_all_pages[0x1];
1378         u8         reserved_at_147[0x2];
1379         u8         roce_accl[0x1];
1380         u8         log_max_ra_req_qp[0x6];
1381         u8         reserved_at_150[0xa];
1382         u8         log_max_ra_res_qp[0x6];
1383
1384         u8         end_pad[0x1];
1385         u8         cc_query_allowed[0x1];
1386         u8         cc_modify_allowed[0x1];
1387         u8         start_pad[0x1];
1388         u8         cache_line_128byte[0x1];
1389         u8         reserved_at_165[0x4];
1390         u8         rts2rts_qp_counters_set_id[0x1];
1391         u8         reserved_at_16a[0x2];
1392         u8         vnic_env_int_rq_oob[0x1];
1393         u8         sbcam_reg[0x1];
1394         u8         reserved_at_16e[0x1];
1395         u8         qcam_reg[0x1];
1396         u8         gid_table_size[0x10];
1397
1398         u8         out_of_seq_cnt[0x1];
1399         u8         vport_counters[0x1];
1400         u8         retransmission_q_counters[0x1];
1401         u8         debug[0x1];
1402         u8         modify_rq_counter_set_id[0x1];
1403         u8         rq_delay_drop[0x1];
1404         u8         max_qp_cnt[0xa];
1405         u8         pkey_table_size[0x10];
1406
1407         u8         vport_group_manager[0x1];
1408         u8         vhca_group_manager[0x1];
1409         u8         ib_virt[0x1];
1410         u8         eth_virt[0x1];
1411         u8         vnic_env_queue_counters[0x1];
1412         u8         ets[0x1];
1413         u8         nic_flow_table[0x1];
1414         u8         eswitch_manager[0x1];
1415         u8         device_memory[0x1];
1416         u8         mcam_reg[0x1];
1417         u8         pcam_reg[0x1];
1418         u8         local_ca_ack_delay[0x5];
1419         u8         port_module_event[0x1];
1420         u8         enhanced_error_q_counters[0x1];
1421         u8         ports_check[0x1];
1422         u8         reserved_at_1b3[0x1];
1423         u8         disable_link_up[0x1];
1424         u8         beacon_led[0x1];
1425         u8         port_type[0x2];
1426         u8         num_ports[0x8];
1427
1428         u8         reserved_at_1c0[0x1];
1429         u8         pps[0x1];
1430         u8         pps_modify[0x1];
1431         u8         log_max_msg[0x5];
1432         u8         reserved_at_1c8[0x4];
1433         u8         max_tc[0x4];
1434         u8         temp_warn_event[0x1];
1435         u8         dcbx[0x1];
1436         u8         general_notification_event[0x1];
1437         u8         reserved_at_1d3[0x2];
1438         u8         fpga[0x1];
1439         u8         rol_s[0x1];
1440         u8         rol_g[0x1];
1441         u8         reserved_at_1d8[0x1];
1442         u8         wol_s[0x1];
1443         u8         wol_g[0x1];
1444         u8         wol_a[0x1];
1445         u8         wol_b[0x1];
1446         u8         wol_m[0x1];
1447         u8         wol_u[0x1];
1448         u8         wol_p[0x1];
1449
1450         u8         stat_rate_support[0x10];
1451         u8         reserved_at_1f0[0x1];
1452         u8         pci_sync_for_fw_update_event[0x1];
1453         u8         reserved_at_1f2[0x6];
1454         u8         init2_lag_tx_port_affinity[0x1];
1455         u8         reserved_at_1fa[0x3];
1456         u8         cqe_version[0x4];
1457
1458         u8         compact_address_vector[0x1];
1459         u8         striding_rq[0x1];
1460         u8         reserved_at_202[0x1];
1461         u8         ipoib_enhanced_offloads[0x1];
1462         u8         ipoib_basic_offloads[0x1];
1463         u8         reserved_at_205[0x1];
1464         u8         repeated_block_disabled[0x1];
1465         u8         umr_modify_entity_size_disabled[0x1];
1466         u8         umr_modify_atomic_disabled[0x1];
1467         u8         umr_indirect_mkey_disabled[0x1];
1468         u8         umr_fence[0x2];
1469         u8         dc_req_scat_data_cqe[0x1];
1470         u8         reserved_at_20d[0x2];
1471         u8         drain_sigerr[0x1];
1472         u8         cmdif_checksum[0x2];
1473         u8         sigerr_cqe[0x1];
1474         u8         reserved_at_213[0x1];
1475         u8         wq_signature[0x1];
1476         u8         sctr_data_cqe[0x1];
1477         u8         reserved_at_216[0x1];
1478         u8         sho[0x1];
1479         u8         tph[0x1];
1480         u8         rf[0x1];
1481         u8         dct[0x1];
1482         u8         qos[0x1];
1483         u8         eth_net_offloads[0x1];
1484         u8         roce[0x1];
1485         u8         atomic[0x1];
1486         u8         reserved_at_21f[0x1];
1487
1488         u8         cq_oi[0x1];
1489         u8         cq_resize[0x1];
1490         u8         cq_moderation[0x1];
1491         u8         reserved_at_223[0x3];
1492         u8         cq_eq_remap[0x1];
1493         u8         pg[0x1];
1494         u8         block_lb_mc[0x1];
1495         u8         reserved_at_229[0x1];
1496         u8         scqe_break_moderation[0x1];
1497         u8         cq_period_start_from_cqe[0x1];
1498         u8         cd[0x1];
1499         u8         reserved_at_22d[0x1];
1500         u8         apm[0x1];
1501         u8         vector_calc[0x1];
1502         u8         umr_ptr_rlky[0x1];
1503         u8         imaicl[0x1];
1504         u8         qp_packet_based[0x1];
1505         u8         reserved_at_233[0x3];
1506         u8         qkv[0x1];
1507         u8         pkv[0x1];
1508         u8         set_deth_sqpn[0x1];
1509         u8         reserved_at_239[0x3];
1510         u8         xrc[0x1];
1511         u8         ud[0x1];
1512         u8         uc[0x1];
1513         u8         rc[0x1];
1514
1515         u8         uar_4k[0x1];
1516         u8         reserved_at_241[0x9];
1517         u8         uar_sz[0x6];
1518         u8         reserved_at_248[0x2];
1519         u8         umem_uid_0[0x1];
1520         u8         reserved_at_250[0x5];
1521         u8         log_pg_sz[0x8];
1522
1523         u8         bf[0x1];
1524         u8         driver_version[0x1];
1525         u8         pad_tx_eth_packet[0x1];
1526         u8         reserved_at_263[0x3];
1527         u8         mkey_by_name[0x1];
1528         u8         reserved_at_267[0x4];
1529
1530         u8         log_bf_reg_size[0x5];
1531
1532         u8         reserved_at_270[0x6];
1533         u8         lag_dct[0x2];
1534         u8         lag_tx_port_affinity[0x1];
1535         u8         lag_native_fdb_selection[0x1];
1536         u8         reserved_at_27a[0x1];
1537         u8         lag_master[0x1];
1538         u8         num_lag_ports[0x4];
1539
1540         u8         reserved_at_280[0x10];
1541         u8         max_wqe_sz_sq[0x10];
1542
1543         u8         reserved_at_2a0[0x10];
1544         u8         max_wqe_sz_rq[0x10];
1545
1546         u8         max_flow_counter_31_16[0x10];
1547         u8         max_wqe_sz_sq_dc[0x10];
1548
1549         u8         reserved_at_2e0[0x7];
1550         u8         max_qp_mcg[0x19];
1551
1552         u8         reserved_at_300[0x10];
1553         u8         flow_counter_bulk_alloc[0x8];
1554         u8         log_max_mcg[0x8];
1555
1556         u8         reserved_at_320[0x3];
1557         u8         log_max_transport_domain[0x5];
1558         u8         reserved_at_328[0x3];
1559         u8         log_max_pd[0x5];
1560         u8         reserved_at_330[0xb];
1561         u8         log_max_xrcd[0x5];
1562
1563         u8         nic_receive_steering_discard[0x1];
1564         u8         receive_discard_vport_down[0x1];
1565         u8         transmit_discard_vport_down[0x1];
1566         u8         reserved_at_343[0x5];
1567         u8         log_max_flow_counter_bulk[0x8];
1568         u8         max_flow_counter_15_0[0x10];
1569
1570
1571         u8         reserved_at_360[0x3];
1572         u8         log_max_rq[0x5];
1573         u8         reserved_at_368[0x3];
1574         u8         log_max_sq[0x5];
1575         u8         reserved_at_370[0x3];
1576         u8         log_max_tir[0x5];
1577         u8         reserved_at_378[0x3];
1578         u8         log_max_tis[0x5];
1579
1580         u8         basic_cyclic_rcv_wqe[0x1];
1581         u8         reserved_at_381[0x2];
1582         u8         log_max_rmp[0x5];
1583         u8         reserved_at_388[0x3];
1584         u8         log_max_rqt[0x5];
1585         u8         reserved_at_390[0x3];
1586         u8         log_max_rqt_size[0x5];
1587         u8         reserved_at_398[0x3];
1588         u8         log_max_tis_per_sq[0x5];
1589
1590         u8         ext_stride_num_range[0x1];
1591         u8         reserved_at_3a1[0x2];
1592         u8         log_max_stride_sz_rq[0x5];
1593         u8         reserved_at_3a8[0x3];
1594         u8         log_min_stride_sz_rq[0x5];
1595         u8         reserved_at_3b0[0x3];
1596         u8         log_max_stride_sz_sq[0x5];
1597         u8         reserved_at_3b8[0x3];
1598         u8         log_min_stride_sz_sq[0x5];
1599
1600         u8         hairpin[0x1];
1601         u8         reserved_at_3c1[0x2];
1602         u8         log_max_hairpin_queues[0x5];
1603         u8         reserved_at_3c8[0x3];
1604         u8         log_max_hairpin_wq_data_sz[0x5];
1605         u8         reserved_at_3d0[0x3];
1606         u8         log_max_hairpin_num_packets[0x5];
1607         u8         reserved_at_3d8[0x3];
1608         u8         log_max_wq_sz[0x5];
1609
1610         u8         nic_vport_change_event[0x1];
1611         u8         disable_local_lb_uc[0x1];
1612         u8         disable_local_lb_mc[0x1];
1613         u8         log_min_hairpin_wq_data_sz[0x5];
1614         u8         reserved_at_3e8[0x2];
1615         u8         vhca_state[0x1];
1616         u8         log_max_vlan_list[0x5];
1617         u8         reserved_at_3f0[0x3];
1618         u8         log_max_current_mc_list[0x5];
1619         u8         reserved_at_3f8[0x3];
1620         u8         log_max_current_uc_list[0x5];
1621
1622         u8         general_obj_types[0x40];
1623
1624         u8         sq_ts_format[0x2];
1625         u8         rq_ts_format[0x2];
1626         u8         steering_format_version[0x4];
1627         u8         create_qp_start_hint[0x18];
1628
1629         u8         reserved_at_460[0x3];
1630         u8         log_max_uctx[0x5];
1631         u8         reserved_at_468[0x2];
1632         u8         ipsec_offload[0x1];
1633         u8         log_max_umem[0x5];
1634         u8         max_num_eqs[0x10];
1635
1636         u8         reserved_at_480[0x1];
1637         u8         tls_tx[0x1];
1638         u8         tls_rx[0x1];
1639         u8         log_max_l2_table[0x5];
1640         u8         reserved_at_488[0x8];
1641         u8         log_uar_page_sz[0x10];
1642
1643         u8         reserved_at_4a0[0x20];
1644         u8         device_frequency_mhz[0x20];
1645         u8         device_frequency_khz[0x20];
1646
1647         u8         reserved_at_500[0x20];
1648         u8         num_of_uars_per_page[0x20];
1649
1650         u8         flex_parser_protocols[0x20];
1651
1652         u8         max_geneve_tlv_options[0x8];
1653         u8         reserved_at_568[0x3];
1654         u8         max_geneve_tlv_option_data_len[0x5];
1655         u8         reserved_at_570[0x10];
1656
1657         u8         reserved_at_580[0xb];
1658         u8         log_max_dci_stream_channels[0x5];
1659         u8         reserved_at_590[0x3];
1660         u8         log_max_dci_errored_streams[0x5];
1661         u8         reserved_at_598[0x8];
1662
1663         u8         reserved_at_5a0[0x13];
1664         u8         log_max_dek[0x5];
1665         u8         reserved_at_5b8[0x4];
1666         u8         mini_cqe_resp_stride_index[0x1];
1667         u8         cqe_128_always[0x1];
1668         u8         cqe_compression_128[0x1];
1669         u8         cqe_compression[0x1];
1670
1671         u8         cqe_compression_timeout[0x10];
1672         u8         cqe_compression_max_num[0x10];
1673
1674         u8         reserved_at_5e0[0x8];
1675         u8         flex_parser_id_gtpu_dw_0[0x4];
1676         u8         reserved_at_5ec[0x4];
1677         u8         tag_matching[0x1];
1678         u8         rndv_offload_rc[0x1];
1679         u8         rndv_offload_dc[0x1];
1680         u8         log_tag_matching_list_sz[0x5];
1681         u8         reserved_at_5f8[0x3];
1682         u8         log_max_xrq[0x5];
1683
1684         u8         affiliate_nic_vport_criteria[0x8];
1685         u8         native_port_num[0x8];
1686         u8         num_vhca_ports[0x8];
1687         u8         flex_parser_id_gtpu_teid[0x4];
1688         u8         reserved_at_61c[0x2];
1689         u8         sw_owner_id[0x1];
1690         u8         reserved_at_61f[0x1];
1691
1692         u8         max_num_of_monitor_counters[0x10];
1693         u8         num_ppcnt_monitor_counters[0x10];
1694
1695         u8         max_num_sf[0x10];
1696         u8         num_q_monitor_counters[0x10];
1697
1698         u8         reserved_at_660[0x20];
1699
1700         u8         sf[0x1];
1701         u8         sf_set_partition[0x1];
1702         u8         reserved_at_682[0x1];
1703         u8         log_max_sf[0x5];
1704         u8         apu[0x1];
1705         u8         reserved_at_689[0x7];
1706         u8         log_min_sf_size[0x8];
1707         u8         max_num_sf_partitions[0x8];
1708
1709         u8         uctx_cap[0x20];
1710
1711         u8         reserved_at_6c0[0x4];
1712         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1713         u8         flex_parser_id_icmp_dw1[0x4];
1714         u8         flex_parser_id_icmp_dw0[0x4];
1715         u8         flex_parser_id_icmpv6_dw1[0x4];
1716         u8         flex_parser_id_icmpv6_dw0[0x4];
1717         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1718         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1719
1720         u8         reserved_at_6e0[0x10];
1721         u8         sf_base_id[0x10];
1722
1723         u8         flex_parser_id_gtpu_dw_2[0x4];
1724         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1725         u8         num_total_dynamic_vf_msix[0x18];
1726         u8         reserved_at_720[0x14];
1727         u8         dynamic_msix_table_size[0xc];
1728         u8         reserved_at_740[0xc];
1729         u8         min_dynamic_vf_msix_table_size[0x4];
1730         u8         reserved_at_750[0x4];
1731         u8         max_dynamic_vf_msix_table_size[0xc];
1732
1733         u8         reserved_at_760[0x20];
1734         u8         vhca_tunnel_commands[0x40];
1735         u8         reserved_at_7c0[0x40];
1736 };
1737
1738 struct mlx5_ifc_cmd_hca_cap_2_bits {
1739         u8         reserved_at_0[0xa0];
1740
1741         u8         max_reformat_insert_size[0x8];
1742         u8         max_reformat_insert_offset[0x8];
1743         u8         max_reformat_remove_size[0x8];
1744         u8         max_reformat_remove_offset[0x8];
1745
1746         u8         reserved_at_c0[0x740];
1747 };
1748
1749 enum mlx5_flow_destination_type {
1750         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1751         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1752         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1753         MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1754
1755         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1756         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1757         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1758 };
1759
1760 enum mlx5_flow_table_miss_action {
1761         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1762         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1763         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1764 };
1765
1766 struct mlx5_ifc_dest_format_struct_bits {
1767         u8         destination_type[0x8];
1768         u8         destination_id[0x18];
1769
1770         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1771         u8         packet_reformat[0x1];
1772         u8         reserved_at_22[0xe];
1773         u8         destination_eswitch_owner_vhca_id[0x10];
1774 };
1775
1776 struct mlx5_ifc_flow_counter_list_bits {
1777         u8         flow_counter_id[0x20];
1778
1779         u8         reserved_at_20[0x20];
1780 };
1781
1782 struct mlx5_ifc_extended_dest_format_bits {
1783         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1784
1785         u8         packet_reformat_id[0x20];
1786
1787         u8         reserved_at_60[0x20];
1788 };
1789
1790 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1791         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1792         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1793 };
1794
1795 struct mlx5_ifc_fte_match_param_bits {
1796         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1797
1798         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1799
1800         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1801
1802         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1803
1804         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1805
1806         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1807
1808         u8         reserved_at_c00[0x400];
1809 };
1810
1811 enum {
1812         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1813         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1814         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1815         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1816         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1817 };
1818
1819 struct mlx5_ifc_rx_hash_field_select_bits {
1820         u8         l3_prot_type[0x1];
1821         u8         l4_prot_type[0x1];
1822         u8         selected_fields[0x1e];
1823 };
1824
1825 enum {
1826         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1827         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1828 };
1829
1830 enum {
1831         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1832         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1833 };
1834
1835 struct mlx5_ifc_wq_bits {
1836         u8         wq_type[0x4];
1837         u8         wq_signature[0x1];
1838         u8         end_padding_mode[0x2];
1839         u8         cd_slave[0x1];
1840         u8         reserved_at_8[0x18];
1841
1842         u8         hds_skip_first_sge[0x1];
1843         u8         log2_hds_buf_size[0x3];
1844         u8         reserved_at_24[0x7];
1845         u8         page_offset[0x5];
1846         u8         lwm[0x10];
1847
1848         u8         reserved_at_40[0x8];
1849         u8         pd[0x18];
1850
1851         u8         reserved_at_60[0x8];
1852         u8         uar_page[0x18];
1853
1854         u8         dbr_addr[0x40];
1855
1856         u8         hw_counter[0x20];
1857
1858         u8         sw_counter[0x20];
1859
1860         u8         reserved_at_100[0xc];
1861         u8         log_wq_stride[0x4];
1862         u8         reserved_at_110[0x3];
1863         u8         log_wq_pg_sz[0x5];
1864         u8         reserved_at_118[0x3];
1865         u8         log_wq_sz[0x5];
1866
1867         u8         dbr_umem_valid[0x1];
1868         u8         wq_umem_valid[0x1];
1869         u8         reserved_at_122[0x1];
1870         u8         log_hairpin_num_packets[0x5];
1871         u8         reserved_at_128[0x3];
1872         u8         log_hairpin_data_sz[0x5];
1873
1874         u8         reserved_at_130[0x4];
1875         u8         log_wqe_num_of_strides[0x4];
1876         u8         two_byte_shift_en[0x1];
1877         u8         reserved_at_139[0x4];
1878         u8         log_wqe_stride_size[0x3];
1879
1880         u8         reserved_at_140[0x4c0];
1881
1882         struct mlx5_ifc_cmd_pas_bits pas[];
1883 };
1884
1885 struct mlx5_ifc_rq_num_bits {
1886         u8         reserved_at_0[0x8];
1887         u8         rq_num[0x18];
1888 };
1889
1890 struct mlx5_ifc_mac_address_layout_bits {
1891         u8         reserved_at_0[0x10];
1892         u8         mac_addr_47_32[0x10];
1893
1894         u8         mac_addr_31_0[0x20];
1895 };
1896
1897 struct mlx5_ifc_vlan_layout_bits {
1898         u8         reserved_at_0[0x14];
1899         u8         vlan[0x0c];
1900
1901         u8         reserved_at_20[0x20];
1902 };
1903
1904 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1905         u8         reserved_at_0[0xa0];
1906
1907         u8         min_time_between_cnps[0x20];
1908
1909         u8         reserved_at_c0[0x12];
1910         u8         cnp_dscp[0x6];
1911         u8         reserved_at_d8[0x4];
1912         u8         cnp_prio_mode[0x1];
1913         u8         cnp_802p_prio[0x3];
1914
1915         u8         reserved_at_e0[0x720];
1916 };
1917
1918 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1919         u8         reserved_at_0[0x60];
1920
1921         u8         reserved_at_60[0x4];
1922         u8         clamp_tgt_rate[0x1];
1923         u8         reserved_at_65[0x3];
1924         u8         clamp_tgt_rate_after_time_inc[0x1];
1925         u8         reserved_at_69[0x17];
1926
1927         u8         reserved_at_80[0x20];
1928
1929         u8         rpg_time_reset[0x20];
1930
1931         u8         rpg_byte_reset[0x20];
1932
1933         u8         rpg_threshold[0x20];
1934
1935         u8         rpg_max_rate[0x20];
1936
1937         u8         rpg_ai_rate[0x20];
1938
1939         u8         rpg_hai_rate[0x20];
1940
1941         u8         rpg_gd[0x20];
1942
1943         u8         rpg_min_dec_fac[0x20];
1944
1945         u8         rpg_min_rate[0x20];
1946
1947         u8         reserved_at_1c0[0xe0];
1948
1949         u8         rate_to_set_on_first_cnp[0x20];
1950
1951         u8         dce_tcp_g[0x20];
1952
1953         u8         dce_tcp_rtt[0x20];
1954
1955         u8         rate_reduce_monitor_period[0x20];
1956
1957         u8         reserved_at_320[0x20];
1958
1959         u8         initial_alpha_value[0x20];
1960
1961         u8         reserved_at_360[0x4a0];
1962 };
1963
1964 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1965         u8         reserved_at_0[0x80];
1966
1967         u8         rppp_max_rps[0x20];
1968
1969         u8         rpg_time_reset[0x20];
1970
1971         u8         rpg_byte_reset[0x20];
1972
1973         u8         rpg_threshold[0x20];
1974
1975         u8         rpg_max_rate[0x20];
1976
1977         u8         rpg_ai_rate[0x20];
1978
1979         u8         rpg_hai_rate[0x20];
1980
1981         u8         rpg_gd[0x20];
1982
1983         u8         rpg_min_dec_fac[0x20];
1984
1985         u8         rpg_min_rate[0x20];
1986
1987         u8         reserved_at_1c0[0x640];
1988 };
1989
1990 enum {
1991         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1992         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1993         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1994 };
1995
1996 struct mlx5_ifc_resize_field_select_bits {
1997         u8         resize_field_select[0x20];
1998 };
1999
2000 struct mlx5_ifc_resource_dump_bits {
2001         u8         more_dump[0x1];
2002         u8         inline_dump[0x1];
2003         u8         reserved_at_2[0xa];
2004         u8         seq_num[0x4];
2005         u8         segment_type[0x10];
2006
2007         u8         reserved_at_20[0x10];
2008         u8         vhca_id[0x10];
2009
2010         u8         index1[0x20];
2011
2012         u8         index2[0x20];
2013
2014         u8         num_of_obj1[0x10];
2015         u8         num_of_obj2[0x10];
2016
2017         u8         reserved_at_a0[0x20];
2018
2019         u8         device_opaque[0x40];
2020
2021         u8         mkey[0x20];
2022
2023         u8         size[0x20];
2024
2025         u8         address[0x40];
2026
2027         u8         inline_data[52][0x20];
2028 };
2029
2030 struct mlx5_ifc_resource_dump_menu_record_bits {
2031         u8         reserved_at_0[0x4];
2032         u8         num_of_obj2_supports_active[0x1];
2033         u8         num_of_obj2_supports_all[0x1];
2034         u8         must_have_num_of_obj2[0x1];
2035         u8         support_num_of_obj2[0x1];
2036         u8         num_of_obj1_supports_active[0x1];
2037         u8         num_of_obj1_supports_all[0x1];
2038         u8         must_have_num_of_obj1[0x1];
2039         u8         support_num_of_obj1[0x1];
2040         u8         must_have_index2[0x1];
2041         u8         support_index2[0x1];
2042         u8         must_have_index1[0x1];
2043         u8         support_index1[0x1];
2044         u8         segment_type[0x10];
2045
2046         u8         segment_name[4][0x20];
2047
2048         u8         index1_name[4][0x20];
2049
2050         u8         index2_name[4][0x20];
2051 };
2052
2053 struct mlx5_ifc_resource_dump_segment_header_bits {
2054         u8         length_dw[0x10];
2055         u8         segment_type[0x10];
2056 };
2057
2058 struct mlx5_ifc_resource_dump_command_segment_bits {
2059         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2060
2061         u8         segment_called[0x10];
2062         u8         vhca_id[0x10];
2063
2064         u8         index1[0x20];
2065
2066         u8         index2[0x20];
2067
2068         u8         num_of_obj1[0x10];
2069         u8         num_of_obj2[0x10];
2070 };
2071
2072 struct mlx5_ifc_resource_dump_error_segment_bits {
2073         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2074
2075         u8         reserved_at_20[0x10];
2076         u8         syndrome_id[0x10];
2077
2078         u8         reserved_at_40[0x40];
2079
2080         u8         error[8][0x20];
2081 };
2082
2083 struct mlx5_ifc_resource_dump_info_segment_bits {
2084         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2085
2086         u8         reserved_at_20[0x18];
2087         u8         dump_version[0x8];
2088
2089         u8         hw_version[0x20];
2090
2091         u8         fw_version[0x20];
2092 };
2093
2094 struct mlx5_ifc_resource_dump_menu_segment_bits {
2095         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2096
2097         u8         reserved_at_20[0x10];
2098         u8         num_of_records[0x10];
2099
2100         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2101 };
2102
2103 struct mlx5_ifc_resource_dump_resource_segment_bits {
2104         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2105
2106         u8         reserved_at_20[0x20];
2107
2108         u8         index1[0x20];
2109
2110         u8         index2[0x20];
2111
2112         u8         payload[][0x20];
2113 };
2114
2115 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2116         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2117 };
2118
2119 struct mlx5_ifc_menu_resource_dump_response_bits {
2120         struct mlx5_ifc_resource_dump_info_segment_bits info;
2121         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2122         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2123         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2124 };
2125
2126 enum {
2127         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2128         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2129         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2130         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2131 };
2132
2133 struct mlx5_ifc_modify_field_select_bits {
2134         u8         modify_field_select[0x20];
2135 };
2136
2137 struct mlx5_ifc_field_select_r_roce_np_bits {
2138         u8         field_select_r_roce_np[0x20];
2139 };
2140
2141 struct mlx5_ifc_field_select_r_roce_rp_bits {
2142         u8         field_select_r_roce_rp[0x20];
2143 };
2144
2145 enum {
2146         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2147         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2148         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2149         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2150         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2151         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2152         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2153         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2154         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2155         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2156 };
2157
2158 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2159         u8         field_select_8021qaurp[0x20];
2160 };
2161
2162 struct mlx5_ifc_phys_layer_cntrs_bits {
2163         u8         time_since_last_clear_high[0x20];
2164
2165         u8         time_since_last_clear_low[0x20];
2166
2167         u8         symbol_errors_high[0x20];
2168
2169         u8         symbol_errors_low[0x20];
2170
2171         u8         sync_headers_errors_high[0x20];
2172
2173         u8         sync_headers_errors_low[0x20];
2174
2175         u8         edpl_bip_errors_lane0_high[0x20];
2176
2177         u8         edpl_bip_errors_lane0_low[0x20];
2178
2179         u8         edpl_bip_errors_lane1_high[0x20];
2180
2181         u8         edpl_bip_errors_lane1_low[0x20];
2182
2183         u8         edpl_bip_errors_lane2_high[0x20];
2184
2185         u8         edpl_bip_errors_lane2_low[0x20];
2186
2187         u8         edpl_bip_errors_lane3_high[0x20];
2188
2189         u8         edpl_bip_errors_lane3_low[0x20];
2190
2191         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2192
2193         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2194
2195         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2196
2197         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2198
2199         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2200
2201         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2202
2203         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2204
2205         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2206
2207         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2208
2209         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2210
2211         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2212
2213         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2214
2215         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2216
2217         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2218
2219         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2220
2221         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2222
2223         u8         rs_fec_corrected_blocks_high[0x20];
2224
2225         u8         rs_fec_corrected_blocks_low[0x20];
2226
2227         u8         rs_fec_uncorrectable_blocks_high[0x20];
2228
2229         u8         rs_fec_uncorrectable_blocks_low[0x20];
2230
2231         u8         rs_fec_no_errors_blocks_high[0x20];
2232
2233         u8         rs_fec_no_errors_blocks_low[0x20];
2234
2235         u8         rs_fec_single_error_blocks_high[0x20];
2236
2237         u8         rs_fec_single_error_blocks_low[0x20];
2238
2239         u8         rs_fec_corrected_symbols_total_high[0x20];
2240
2241         u8         rs_fec_corrected_symbols_total_low[0x20];
2242
2243         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2244
2245         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2246
2247         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2248
2249         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2250
2251         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2252
2253         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2254
2255         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2256
2257         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2258
2259         u8         link_down_events[0x20];
2260
2261         u8         successful_recovery_events[0x20];
2262
2263         u8         reserved_at_640[0x180];
2264 };
2265
2266 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2267         u8         time_since_last_clear_high[0x20];
2268
2269         u8         time_since_last_clear_low[0x20];
2270
2271         u8         phy_received_bits_high[0x20];
2272
2273         u8         phy_received_bits_low[0x20];
2274
2275         u8         phy_symbol_errors_high[0x20];
2276
2277         u8         phy_symbol_errors_low[0x20];
2278
2279         u8         phy_corrected_bits_high[0x20];
2280
2281         u8         phy_corrected_bits_low[0x20];
2282
2283         u8         phy_corrected_bits_lane0_high[0x20];
2284
2285         u8         phy_corrected_bits_lane0_low[0x20];
2286
2287         u8         phy_corrected_bits_lane1_high[0x20];
2288
2289         u8         phy_corrected_bits_lane1_low[0x20];
2290
2291         u8         phy_corrected_bits_lane2_high[0x20];
2292
2293         u8         phy_corrected_bits_lane2_low[0x20];
2294
2295         u8         phy_corrected_bits_lane3_high[0x20];
2296
2297         u8         phy_corrected_bits_lane3_low[0x20];
2298
2299         u8         reserved_at_200[0x5c0];
2300 };
2301
2302 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2303         u8         symbol_error_counter[0x10];
2304
2305         u8         link_error_recovery_counter[0x8];
2306
2307         u8         link_downed_counter[0x8];
2308
2309         u8         port_rcv_errors[0x10];
2310
2311         u8         port_rcv_remote_physical_errors[0x10];
2312
2313         u8         port_rcv_switch_relay_errors[0x10];
2314
2315         u8         port_xmit_discards[0x10];
2316
2317         u8         port_xmit_constraint_errors[0x8];
2318
2319         u8         port_rcv_constraint_errors[0x8];
2320
2321         u8         reserved_at_70[0x8];
2322
2323         u8         link_overrun_errors[0x8];
2324
2325         u8         reserved_at_80[0x10];
2326
2327         u8         vl_15_dropped[0x10];
2328
2329         u8         reserved_at_a0[0x80];
2330
2331         u8         port_xmit_wait[0x20];
2332 };
2333
2334 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2335         u8         transmit_queue_high[0x20];
2336
2337         u8         transmit_queue_low[0x20];
2338
2339         u8         no_buffer_discard_uc_high[0x20];
2340
2341         u8         no_buffer_discard_uc_low[0x20];
2342
2343         u8         reserved_at_80[0x740];
2344 };
2345
2346 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2347         u8         wred_discard_high[0x20];
2348
2349         u8         wred_discard_low[0x20];
2350
2351         u8         ecn_marked_tc_high[0x20];
2352
2353         u8         ecn_marked_tc_low[0x20];
2354
2355         u8         reserved_at_80[0x740];
2356 };
2357
2358 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2359         u8         rx_octets_high[0x20];
2360
2361         u8         rx_octets_low[0x20];
2362
2363         u8         reserved_at_40[0xc0];
2364
2365         u8         rx_frames_high[0x20];
2366
2367         u8         rx_frames_low[0x20];
2368
2369         u8         tx_octets_high[0x20];
2370
2371         u8         tx_octets_low[0x20];
2372
2373         u8         reserved_at_180[0xc0];
2374
2375         u8         tx_frames_high[0x20];
2376
2377         u8         tx_frames_low[0x20];
2378
2379         u8         rx_pause_high[0x20];
2380
2381         u8         rx_pause_low[0x20];
2382
2383         u8         rx_pause_duration_high[0x20];
2384
2385         u8         rx_pause_duration_low[0x20];
2386
2387         u8         tx_pause_high[0x20];
2388
2389         u8         tx_pause_low[0x20];
2390
2391         u8         tx_pause_duration_high[0x20];
2392
2393         u8         tx_pause_duration_low[0x20];
2394
2395         u8         rx_pause_transition_high[0x20];
2396
2397         u8         rx_pause_transition_low[0x20];
2398
2399         u8         rx_discards_high[0x20];
2400
2401         u8         rx_discards_low[0x20];
2402
2403         u8         device_stall_minor_watermark_cnt_high[0x20];
2404
2405         u8         device_stall_minor_watermark_cnt_low[0x20];
2406
2407         u8         device_stall_critical_watermark_cnt_high[0x20];
2408
2409         u8         device_stall_critical_watermark_cnt_low[0x20];
2410
2411         u8         reserved_at_480[0x340];
2412 };
2413
2414 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2415         u8         port_transmit_wait_high[0x20];
2416
2417         u8         port_transmit_wait_low[0x20];
2418
2419         u8         reserved_at_40[0x100];
2420
2421         u8         rx_buffer_almost_full_high[0x20];
2422
2423         u8         rx_buffer_almost_full_low[0x20];
2424
2425         u8         rx_buffer_full_high[0x20];
2426
2427         u8         rx_buffer_full_low[0x20];
2428
2429         u8         rx_icrc_encapsulated_high[0x20];
2430
2431         u8         rx_icrc_encapsulated_low[0x20];
2432
2433         u8         reserved_at_200[0x5c0];
2434 };
2435
2436 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2437         u8         dot3stats_alignment_errors_high[0x20];
2438
2439         u8         dot3stats_alignment_errors_low[0x20];
2440
2441         u8         dot3stats_fcs_errors_high[0x20];
2442
2443         u8         dot3stats_fcs_errors_low[0x20];
2444
2445         u8         dot3stats_single_collision_frames_high[0x20];
2446
2447         u8         dot3stats_single_collision_frames_low[0x20];
2448
2449         u8         dot3stats_multiple_collision_frames_high[0x20];
2450
2451         u8         dot3stats_multiple_collision_frames_low[0x20];
2452
2453         u8         dot3stats_sqe_test_errors_high[0x20];
2454
2455         u8         dot3stats_sqe_test_errors_low[0x20];
2456
2457         u8         dot3stats_deferred_transmissions_high[0x20];
2458
2459         u8         dot3stats_deferred_transmissions_low[0x20];
2460
2461         u8         dot3stats_late_collisions_high[0x20];
2462
2463         u8         dot3stats_late_collisions_low[0x20];
2464
2465         u8         dot3stats_excessive_collisions_high[0x20];
2466
2467         u8         dot3stats_excessive_collisions_low[0x20];
2468
2469         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2470
2471         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2472
2473         u8         dot3stats_carrier_sense_errors_high[0x20];
2474
2475         u8         dot3stats_carrier_sense_errors_low[0x20];
2476
2477         u8         dot3stats_frame_too_longs_high[0x20];
2478
2479         u8         dot3stats_frame_too_longs_low[0x20];
2480
2481         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2482
2483         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2484
2485         u8         dot3stats_symbol_errors_high[0x20];
2486
2487         u8         dot3stats_symbol_errors_low[0x20];
2488
2489         u8         dot3control_in_unknown_opcodes_high[0x20];
2490
2491         u8         dot3control_in_unknown_opcodes_low[0x20];
2492
2493         u8         dot3in_pause_frames_high[0x20];
2494
2495         u8         dot3in_pause_frames_low[0x20];
2496
2497         u8         dot3out_pause_frames_high[0x20];
2498
2499         u8         dot3out_pause_frames_low[0x20];
2500
2501         u8         reserved_at_400[0x3c0];
2502 };
2503
2504 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2505         u8         ether_stats_drop_events_high[0x20];
2506
2507         u8         ether_stats_drop_events_low[0x20];
2508
2509         u8         ether_stats_octets_high[0x20];
2510
2511         u8         ether_stats_octets_low[0x20];
2512
2513         u8         ether_stats_pkts_high[0x20];
2514
2515         u8         ether_stats_pkts_low[0x20];
2516
2517         u8         ether_stats_broadcast_pkts_high[0x20];
2518
2519         u8         ether_stats_broadcast_pkts_low[0x20];
2520
2521         u8         ether_stats_multicast_pkts_high[0x20];
2522
2523         u8         ether_stats_multicast_pkts_low[0x20];
2524
2525         u8         ether_stats_crc_align_errors_high[0x20];
2526
2527         u8         ether_stats_crc_align_errors_low[0x20];
2528
2529         u8         ether_stats_undersize_pkts_high[0x20];
2530
2531         u8         ether_stats_undersize_pkts_low[0x20];
2532
2533         u8         ether_stats_oversize_pkts_high[0x20];
2534
2535         u8         ether_stats_oversize_pkts_low[0x20];
2536
2537         u8         ether_stats_fragments_high[0x20];
2538
2539         u8         ether_stats_fragments_low[0x20];
2540
2541         u8         ether_stats_jabbers_high[0x20];
2542
2543         u8         ether_stats_jabbers_low[0x20];
2544
2545         u8         ether_stats_collisions_high[0x20];
2546
2547         u8         ether_stats_collisions_low[0x20];
2548
2549         u8         ether_stats_pkts64octets_high[0x20];
2550
2551         u8         ether_stats_pkts64octets_low[0x20];
2552
2553         u8         ether_stats_pkts65to127octets_high[0x20];
2554
2555         u8         ether_stats_pkts65to127octets_low[0x20];
2556
2557         u8         ether_stats_pkts128to255octets_high[0x20];
2558
2559         u8         ether_stats_pkts128to255octets_low[0x20];
2560
2561         u8         ether_stats_pkts256to511octets_high[0x20];
2562
2563         u8         ether_stats_pkts256to511octets_low[0x20];
2564
2565         u8         ether_stats_pkts512to1023octets_high[0x20];
2566
2567         u8         ether_stats_pkts512to1023octets_low[0x20];
2568
2569         u8         ether_stats_pkts1024to1518octets_high[0x20];
2570
2571         u8         ether_stats_pkts1024to1518octets_low[0x20];
2572
2573         u8         ether_stats_pkts1519to2047octets_high[0x20];
2574
2575         u8         ether_stats_pkts1519to2047octets_low[0x20];
2576
2577         u8         ether_stats_pkts2048to4095octets_high[0x20];
2578
2579         u8         ether_stats_pkts2048to4095octets_low[0x20];
2580
2581         u8         ether_stats_pkts4096to8191octets_high[0x20];
2582
2583         u8         ether_stats_pkts4096to8191octets_low[0x20];
2584
2585         u8         ether_stats_pkts8192to10239octets_high[0x20];
2586
2587         u8         ether_stats_pkts8192to10239octets_low[0x20];
2588
2589         u8         reserved_at_540[0x280];
2590 };
2591
2592 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2593         u8         if_in_octets_high[0x20];
2594
2595         u8         if_in_octets_low[0x20];
2596
2597         u8         if_in_ucast_pkts_high[0x20];
2598
2599         u8         if_in_ucast_pkts_low[0x20];
2600
2601         u8         if_in_discards_high[0x20];
2602
2603         u8         if_in_discards_low[0x20];
2604
2605         u8         if_in_errors_high[0x20];
2606
2607         u8         if_in_errors_low[0x20];
2608
2609         u8         if_in_unknown_protos_high[0x20];
2610
2611         u8         if_in_unknown_protos_low[0x20];
2612
2613         u8         if_out_octets_high[0x20];
2614
2615         u8         if_out_octets_low[0x20];
2616
2617         u8         if_out_ucast_pkts_high[0x20];
2618
2619         u8         if_out_ucast_pkts_low[0x20];
2620
2621         u8         if_out_discards_high[0x20];
2622
2623         u8         if_out_discards_low[0x20];
2624
2625         u8         if_out_errors_high[0x20];
2626
2627         u8         if_out_errors_low[0x20];
2628
2629         u8         if_in_multicast_pkts_high[0x20];
2630
2631         u8         if_in_multicast_pkts_low[0x20];
2632
2633         u8         if_in_broadcast_pkts_high[0x20];
2634
2635         u8         if_in_broadcast_pkts_low[0x20];
2636
2637         u8         if_out_multicast_pkts_high[0x20];
2638
2639         u8         if_out_multicast_pkts_low[0x20];
2640
2641         u8         if_out_broadcast_pkts_high[0x20];
2642
2643         u8         if_out_broadcast_pkts_low[0x20];
2644
2645         u8         reserved_at_340[0x480];
2646 };
2647
2648 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2649         u8         a_frames_transmitted_ok_high[0x20];
2650
2651         u8         a_frames_transmitted_ok_low[0x20];
2652
2653         u8         a_frames_received_ok_high[0x20];
2654
2655         u8         a_frames_received_ok_low[0x20];
2656
2657         u8         a_frame_check_sequence_errors_high[0x20];
2658
2659         u8         a_frame_check_sequence_errors_low[0x20];
2660
2661         u8         a_alignment_errors_high[0x20];
2662
2663         u8         a_alignment_errors_low[0x20];
2664
2665         u8         a_octets_transmitted_ok_high[0x20];
2666
2667         u8         a_octets_transmitted_ok_low[0x20];
2668
2669         u8         a_octets_received_ok_high[0x20];
2670
2671         u8         a_octets_received_ok_low[0x20];
2672
2673         u8         a_multicast_frames_xmitted_ok_high[0x20];
2674
2675         u8         a_multicast_frames_xmitted_ok_low[0x20];
2676
2677         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2678
2679         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2680
2681         u8         a_multicast_frames_received_ok_high[0x20];
2682
2683         u8         a_multicast_frames_received_ok_low[0x20];
2684
2685         u8         a_broadcast_frames_received_ok_high[0x20];
2686
2687         u8         a_broadcast_frames_received_ok_low[0x20];
2688
2689         u8         a_in_range_length_errors_high[0x20];
2690
2691         u8         a_in_range_length_errors_low[0x20];
2692
2693         u8         a_out_of_range_length_field_high[0x20];
2694
2695         u8         a_out_of_range_length_field_low[0x20];
2696
2697         u8         a_frame_too_long_errors_high[0x20];
2698
2699         u8         a_frame_too_long_errors_low[0x20];
2700
2701         u8         a_symbol_error_during_carrier_high[0x20];
2702
2703         u8         a_symbol_error_during_carrier_low[0x20];
2704
2705         u8         a_mac_control_frames_transmitted_high[0x20];
2706
2707         u8         a_mac_control_frames_transmitted_low[0x20];
2708
2709         u8         a_mac_control_frames_received_high[0x20];
2710
2711         u8         a_mac_control_frames_received_low[0x20];
2712
2713         u8         a_unsupported_opcodes_received_high[0x20];
2714
2715         u8         a_unsupported_opcodes_received_low[0x20];
2716
2717         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2718
2719         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2720
2721         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2722
2723         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2724
2725         u8         reserved_at_4c0[0x300];
2726 };
2727
2728 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2729         u8         life_time_counter_high[0x20];
2730
2731         u8         life_time_counter_low[0x20];
2732
2733         u8         rx_errors[0x20];
2734
2735         u8         tx_errors[0x20];
2736
2737         u8         l0_to_recovery_eieos[0x20];
2738
2739         u8         l0_to_recovery_ts[0x20];
2740
2741         u8         l0_to_recovery_framing[0x20];
2742
2743         u8         l0_to_recovery_retrain[0x20];
2744
2745         u8         crc_error_dllp[0x20];
2746
2747         u8         crc_error_tlp[0x20];
2748
2749         u8         tx_overflow_buffer_pkt_high[0x20];
2750
2751         u8         tx_overflow_buffer_pkt_low[0x20];
2752
2753         u8         outbound_stalled_reads[0x20];
2754
2755         u8         outbound_stalled_writes[0x20];
2756
2757         u8         outbound_stalled_reads_events[0x20];
2758
2759         u8         outbound_stalled_writes_events[0x20];
2760
2761         u8         reserved_at_200[0x5c0];
2762 };
2763
2764 struct mlx5_ifc_cmd_inter_comp_event_bits {
2765         u8         command_completion_vector[0x20];
2766
2767         u8         reserved_at_20[0xc0];
2768 };
2769
2770 struct mlx5_ifc_stall_vl_event_bits {
2771         u8         reserved_at_0[0x18];
2772         u8         port_num[0x1];
2773         u8         reserved_at_19[0x3];
2774         u8         vl[0x4];
2775
2776         u8         reserved_at_20[0xa0];
2777 };
2778
2779 struct mlx5_ifc_db_bf_congestion_event_bits {
2780         u8         event_subtype[0x8];
2781         u8         reserved_at_8[0x8];
2782         u8         congestion_level[0x8];
2783         u8         reserved_at_18[0x8];
2784
2785         u8         reserved_at_20[0xa0];
2786 };
2787
2788 struct mlx5_ifc_gpio_event_bits {
2789         u8         reserved_at_0[0x60];
2790
2791         u8         gpio_event_hi[0x20];
2792
2793         u8         gpio_event_lo[0x20];
2794
2795         u8         reserved_at_a0[0x40];
2796 };
2797
2798 struct mlx5_ifc_port_state_change_event_bits {
2799         u8         reserved_at_0[0x40];
2800
2801         u8         port_num[0x4];
2802         u8         reserved_at_44[0x1c];
2803
2804         u8         reserved_at_60[0x80];
2805 };
2806
2807 struct mlx5_ifc_dropped_packet_logged_bits {
2808         u8         reserved_at_0[0xe0];
2809 };
2810
2811 struct mlx5_ifc_default_timeout_bits {
2812         u8         to_multiplier[0x3];
2813         u8         reserved_at_3[0x9];
2814         u8         to_value[0x14];
2815 };
2816
2817 struct mlx5_ifc_dtor_reg_bits {
2818         u8         reserved_at_0[0x20];
2819
2820         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2821
2822         u8         reserved_at_40[0x60];
2823
2824         struct mlx5_ifc_default_timeout_bits health_poll_to;
2825
2826         struct mlx5_ifc_default_timeout_bits full_crdump_to;
2827
2828         struct mlx5_ifc_default_timeout_bits fw_reset_to;
2829
2830         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2831
2832         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2833
2834         struct mlx5_ifc_default_timeout_bits tear_down_to;
2835
2836         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2837
2838         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2839
2840         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2841
2842         u8         reserved_at_1c0[0x40];
2843 };
2844
2845 enum {
2846         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2847         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2848 };
2849
2850 struct mlx5_ifc_cq_error_bits {
2851         u8         reserved_at_0[0x8];
2852         u8         cqn[0x18];
2853
2854         u8         reserved_at_20[0x20];
2855
2856         u8         reserved_at_40[0x18];
2857         u8         syndrome[0x8];
2858
2859         u8         reserved_at_60[0x80];
2860 };
2861
2862 struct mlx5_ifc_rdma_page_fault_event_bits {
2863         u8         bytes_committed[0x20];
2864
2865         u8         r_key[0x20];
2866
2867         u8         reserved_at_40[0x10];
2868         u8         packet_len[0x10];
2869
2870         u8         rdma_op_len[0x20];
2871
2872         u8         rdma_va[0x40];
2873
2874         u8         reserved_at_c0[0x5];
2875         u8         rdma[0x1];
2876         u8         write[0x1];
2877         u8         requestor[0x1];
2878         u8         qp_number[0x18];
2879 };
2880
2881 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2882         u8         bytes_committed[0x20];
2883
2884         u8         reserved_at_20[0x10];
2885         u8         wqe_index[0x10];
2886
2887         u8         reserved_at_40[0x10];
2888         u8         len[0x10];
2889
2890         u8         reserved_at_60[0x60];
2891
2892         u8         reserved_at_c0[0x5];
2893         u8         rdma[0x1];
2894         u8         write_read[0x1];
2895         u8         requestor[0x1];
2896         u8         qpn[0x18];
2897 };
2898
2899 struct mlx5_ifc_qp_events_bits {
2900         u8         reserved_at_0[0xa0];
2901
2902         u8         type[0x8];
2903         u8         reserved_at_a8[0x18];
2904
2905         u8         reserved_at_c0[0x8];
2906         u8         qpn_rqn_sqn[0x18];
2907 };
2908
2909 struct mlx5_ifc_dct_events_bits {
2910         u8         reserved_at_0[0xc0];
2911
2912         u8         reserved_at_c0[0x8];
2913         u8         dct_number[0x18];
2914 };
2915
2916 struct mlx5_ifc_comp_event_bits {
2917         u8         reserved_at_0[0xc0];
2918
2919         u8         reserved_at_c0[0x8];
2920         u8         cq_number[0x18];
2921 };
2922
2923 enum {
2924         MLX5_QPC_STATE_RST        = 0x0,
2925         MLX5_QPC_STATE_INIT       = 0x1,
2926         MLX5_QPC_STATE_RTR        = 0x2,
2927         MLX5_QPC_STATE_RTS        = 0x3,
2928         MLX5_QPC_STATE_SQER       = 0x4,
2929         MLX5_QPC_STATE_ERR        = 0x6,
2930         MLX5_QPC_STATE_SQD        = 0x7,
2931         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2932 };
2933
2934 enum {
2935         MLX5_QPC_ST_RC            = 0x0,
2936         MLX5_QPC_ST_UC            = 0x1,
2937         MLX5_QPC_ST_UD            = 0x2,
2938         MLX5_QPC_ST_XRC           = 0x3,
2939         MLX5_QPC_ST_DCI           = 0x5,
2940         MLX5_QPC_ST_QP0           = 0x7,
2941         MLX5_QPC_ST_QP1           = 0x8,
2942         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2943         MLX5_QPC_ST_REG_UMR       = 0xc,
2944 };
2945
2946 enum {
2947         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2948         MLX5_QPC_PM_STATE_REARM     = 0x1,
2949         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2950         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2951 };
2952
2953 enum {
2954         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2955 };
2956
2957 enum {
2958         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2959         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2960 };
2961
2962 enum {
2963         MLX5_QPC_MTU_256_BYTES        = 0x1,
2964         MLX5_QPC_MTU_512_BYTES        = 0x2,
2965         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2966         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2967         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2968         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2969 };
2970
2971 enum {
2972         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2973         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2974         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2975         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2976         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2977         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2978         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2979         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2980 };
2981
2982 enum {
2983         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2984         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2985         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2986 };
2987
2988 enum {
2989         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2990         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2991         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2992 };
2993
2994 enum {
2995         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2996         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2997         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2998 };
2999
3000 struct mlx5_ifc_qpc_bits {
3001         u8         state[0x4];
3002         u8         lag_tx_port_affinity[0x4];
3003         u8         st[0x8];
3004         u8         reserved_at_10[0x2];
3005         u8         isolate_vl_tc[0x1];
3006         u8         pm_state[0x2];
3007         u8         reserved_at_15[0x1];
3008         u8         req_e2e_credit_mode[0x2];
3009         u8         offload_type[0x4];
3010         u8         end_padding_mode[0x2];
3011         u8         reserved_at_1e[0x2];
3012
3013         u8         wq_signature[0x1];
3014         u8         block_lb_mc[0x1];
3015         u8         atomic_like_write_en[0x1];
3016         u8         latency_sensitive[0x1];
3017         u8         reserved_at_24[0x1];
3018         u8         drain_sigerr[0x1];
3019         u8         reserved_at_26[0x2];
3020         u8         pd[0x18];
3021
3022         u8         mtu[0x3];
3023         u8         log_msg_max[0x5];
3024         u8         reserved_at_48[0x1];
3025         u8         log_rq_size[0x4];
3026         u8         log_rq_stride[0x3];
3027         u8         no_sq[0x1];
3028         u8         log_sq_size[0x4];
3029         u8         reserved_at_55[0x3];
3030         u8         ts_format[0x2];
3031         u8         reserved_at_5a[0x1];
3032         u8         rlky[0x1];
3033         u8         ulp_stateless_offload_mode[0x4];
3034
3035         u8         counter_set_id[0x8];
3036         u8         uar_page[0x18];
3037
3038         u8         reserved_at_80[0x8];
3039         u8         user_index[0x18];
3040
3041         u8         reserved_at_a0[0x3];
3042         u8         log_page_size[0x5];
3043         u8         remote_qpn[0x18];
3044
3045         struct mlx5_ifc_ads_bits primary_address_path;
3046
3047         struct mlx5_ifc_ads_bits secondary_address_path;
3048
3049         u8         log_ack_req_freq[0x4];
3050         u8         reserved_at_384[0x4];
3051         u8         log_sra_max[0x3];
3052         u8         reserved_at_38b[0x2];
3053         u8         retry_count[0x3];
3054         u8         rnr_retry[0x3];
3055         u8         reserved_at_393[0x1];
3056         u8         fre[0x1];
3057         u8         cur_rnr_retry[0x3];
3058         u8         cur_retry_count[0x3];
3059         u8         reserved_at_39b[0x5];
3060
3061         u8         reserved_at_3a0[0x20];
3062
3063         u8         reserved_at_3c0[0x8];
3064         u8         next_send_psn[0x18];
3065
3066         u8         reserved_at_3e0[0x3];
3067         u8         log_num_dci_stream_channels[0x5];
3068         u8         cqn_snd[0x18];
3069
3070         u8         reserved_at_400[0x3];
3071         u8         log_num_dci_errored_streams[0x5];
3072         u8         deth_sqpn[0x18];
3073
3074         u8         reserved_at_420[0x20];
3075
3076         u8         reserved_at_440[0x8];
3077         u8         last_acked_psn[0x18];
3078
3079         u8         reserved_at_460[0x8];
3080         u8         ssn[0x18];
3081
3082         u8         reserved_at_480[0x8];
3083         u8         log_rra_max[0x3];
3084         u8         reserved_at_48b[0x1];
3085         u8         atomic_mode[0x4];
3086         u8         rre[0x1];
3087         u8         rwe[0x1];
3088         u8         rae[0x1];
3089         u8         reserved_at_493[0x1];
3090         u8         page_offset[0x6];
3091         u8         reserved_at_49a[0x3];
3092         u8         cd_slave_receive[0x1];
3093         u8         cd_slave_send[0x1];
3094         u8         cd_master[0x1];
3095
3096         u8         reserved_at_4a0[0x3];
3097         u8         min_rnr_nak[0x5];
3098         u8         next_rcv_psn[0x18];
3099
3100         u8         reserved_at_4c0[0x8];
3101         u8         xrcd[0x18];
3102
3103         u8         reserved_at_4e0[0x8];
3104         u8         cqn_rcv[0x18];
3105
3106         u8         dbr_addr[0x40];
3107
3108         u8         q_key[0x20];
3109
3110         u8         reserved_at_560[0x5];
3111         u8         rq_type[0x3];
3112         u8         srqn_rmpn_xrqn[0x18];
3113
3114         u8         reserved_at_580[0x8];
3115         u8         rmsn[0x18];
3116
3117         u8         hw_sq_wqebb_counter[0x10];
3118         u8         sw_sq_wqebb_counter[0x10];
3119
3120         u8         hw_rq_counter[0x20];
3121
3122         u8         sw_rq_counter[0x20];
3123
3124         u8         reserved_at_600[0x20];
3125
3126         u8         reserved_at_620[0xf];
3127         u8         cgs[0x1];
3128         u8         cs_req[0x8];
3129         u8         cs_res[0x8];
3130
3131         u8         dc_access_key[0x40];
3132
3133         u8         reserved_at_680[0x3];
3134         u8         dbr_umem_valid[0x1];
3135
3136         u8         reserved_at_684[0xbc];
3137 };
3138
3139 struct mlx5_ifc_roce_addr_layout_bits {
3140         u8         source_l3_address[16][0x8];
3141
3142         u8         reserved_at_80[0x3];
3143         u8         vlan_valid[0x1];
3144         u8         vlan_id[0xc];
3145         u8         source_mac_47_32[0x10];
3146
3147         u8         source_mac_31_0[0x20];
3148
3149         u8         reserved_at_c0[0x14];
3150         u8         roce_l3_type[0x4];
3151         u8         roce_version[0x8];
3152
3153         u8         reserved_at_e0[0x20];
3154 };
3155
3156 union mlx5_ifc_hca_cap_union_bits {
3157         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3158         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3159         struct mlx5_ifc_odp_cap_bits odp_cap;
3160         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3161         struct mlx5_ifc_roce_cap_bits roce_cap;
3162         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3163         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3164         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3165         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3166         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3167         struct mlx5_ifc_qos_cap_bits qos_cap;
3168         struct mlx5_ifc_debug_cap_bits debug_cap;
3169         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3170         struct mlx5_ifc_tls_cap_bits tls_cap;
3171         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3172         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3173         u8         reserved_at_0[0x8000];
3174 };
3175
3176 enum {
3177         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3178         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3179         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3180         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3181         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3182         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3183         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3184         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3185         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3186         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3187         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3188         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3189         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3190 };
3191
3192 enum {
3193         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3194         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3195         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3196 };
3197
3198 struct mlx5_ifc_vlan_bits {
3199         u8         ethtype[0x10];
3200         u8         prio[0x3];
3201         u8         cfi[0x1];
3202         u8         vid[0xc];
3203 };
3204
3205 struct mlx5_ifc_flow_context_bits {
3206         struct mlx5_ifc_vlan_bits push_vlan;
3207
3208         u8         group_id[0x20];
3209
3210         u8         reserved_at_40[0x8];
3211         u8         flow_tag[0x18];
3212
3213         u8         reserved_at_60[0x10];
3214         u8         action[0x10];
3215
3216         u8         extended_destination[0x1];
3217         u8         reserved_at_81[0x1];
3218         u8         flow_source[0x2];
3219         u8         reserved_at_84[0x4];
3220         u8         destination_list_size[0x18];
3221
3222         u8         reserved_at_a0[0x8];
3223         u8         flow_counter_list_size[0x18];
3224
3225         u8         packet_reformat_id[0x20];
3226
3227         u8         modify_header_id[0x20];
3228
3229         struct mlx5_ifc_vlan_bits push_vlan_2;
3230
3231         u8         ipsec_obj_id[0x20];
3232         u8         reserved_at_140[0xc0];
3233
3234         struct mlx5_ifc_fte_match_param_bits match_value;
3235
3236         u8         reserved_at_1200[0x600];
3237
3238         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3239 };
3240
3241 enum {
3242         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3243         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3244 };
3245
3246 struct mlx5_ifc_xrc_srqc_bits {
3247         u8         state[0x4];
3248         u8         log_xrc_srq_size[0x4];
3249         u8         reserved_at_8[0x18];
3250
3251         u8         wq_signature[0x1];
3252         u8         cont_srq[0x1];
3253         u8         reserved_at_22[0x1];
3254         u8         rlky[0x1];
3255         u8         basic_cyclic_rcv_wqe[0x1];
3256         u8         log_rq_stride[0x3];
3257         u8         xrcd[0x18];
3258
3259         u8         page_offset[0x6];
3260         u8         reserved_at_46[0x1];
3261         u8         dbr_umem_valid[0x1];
3262         u8         cqn[0x18];
3263
3264         u8         reserved_at_60[0x20];
3265
3266         u8         user_index_equal_xrc_srqn[0x1];
3267         u8         reserved_at_81[0x1];
3268         u8         log_page_size[0x6];
3269         u8         user_index[0x18];
3270
3271         u8         reserved_at_a0[0x20];
3272
3273         u8         reserved_at_c0[0x8];
3274         u8         pd[0x18];
3275
3276         u8         lwm[0x10];
3277         u8         wqe_cnt[0x10];
3278
3279         u8         reserved_at_100[0x40];
3280
3281         u8         db_record_addr_h[0x20];
3282
3283         u8         db_record_addr_l[0x1e];
3284         u8         reserved_at_17e[0x2];
3285
3286         u8         reserved_at_180[0x80];
3287 };
3288
3289 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3290         u8         counter_error_queues[0x20];
3291
3292         u8         total_error_queues[0x20];
3293
3294         u8         send_queue_priority_update_flow[0x20];
3295
3296         u8         reserved_at_60[0x20];
3297
3298         u8         nic_receive_steering_discard[0x40];
3299
3300         u8         receive_discard_vport_down[0x40];
3301
3302         u8         transmit_discard_vport_down[0x40];
3303
3304         u8         reserved_at_140[0xa0];
3305
3306         u8         internal_rq_out_of_buffer[0x20];
3307
3308         u8         reserved_at_200[0xe00];
3309 };
3310
3311 struct mlx5_ifc_traffic_counter_bits {
3312         u8         packets[0x40];
3313
3314         u8         octets[0x40];
3315 };
3316
3317 struct mlx5_ifc_tisc_bits {
3318         u8         strict_lag_tx_port_affinity[0x1];
3319         u8         tls_en[0x1];
3320         u8         reserved_at_2[0x2];
3321         u8         lag_tx_port_affinity[0x04];
3322
3323         u8         reserved_at_8[0x4];
3324         u8         prio[0x4];
3325         u8         reserved_at_10[0x10];
3326
3327         u8         reserved_at_20[0x100];
3328
3329         u8         reserved_at_120[0x8];
3330         u8         transport_domain[0x18];
3331
3332         u8         reserved_at_140[0x8];
3333         u8         underlay_qpn[0x18];
3334
3335         u8         reserved_at_160[0x8];
3336         u8         pd[0x18];
3337
3338         u8         reserved_at_180[0x380];
3339 };
3340
3341 enum {
3342         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3343         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3344 };
3345
3346 enum {
3347         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3348         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3349 };
3350
3351 enum {
3352         MLX5_RX_HASH_FN_NONE           = 0x0,
3353         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3354         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3355 };
3356
3357 enum {
3358         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3359         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3360 };
3361
3362 struct mlx5_ifc_tirc_bits {
3363         u8         reserved_at_0[0x20];
3364
3365         u8         disp_type[0x4];
3366         u8         tls_en[0x1];
3367         u8         reserved_at_25[0x1b];
3368
3369         u8         reserved_at_40[0x40];
3370
3371         u8         reserved_at_80[0x4];
3372         u8         lro_timeout_period_usecs[0x10];
3373         u8         lro_enable_mask[0x4];
3374         u8         lro_max_ip_payload_size[0x8];
3375
3376         u8         reserved_at_a0[0x40];
3377
3378         u8         reserved_at_e0[0x8];
3379         u8         inline_rqn[0x18];
3380
3381         u8         rx_hash_symmetric[0x1];
3382         u8         reserved_at_101[0x1];
3383         u8         tunneled_offload_en[0x1];
3384         u8         reserved_at_103[0x5];
3385         u8         indirect_table[0x18];
3386
3387         u8         rx_hash_fn[0x4];
3388         u8         reserved_at_124[0x2];
3389         u8         self_lb_block[0x2];
3390         u8         transport_domain[0x18];
3391
3392         u8         rx_hash_toeplitz_key[10][0x20];
3393
3394         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3395
3396         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3397
3398         u8         reserved_at_2c0[0x4c0];
3399 };
3400
3401 enum {
3402         MLX5_SRQC_STATE_GOOD   = 0x0,
3403         MLX5_SRQC_STATE_ERROR  = 0x1,
3404 };
3405
3406 struct mlx5_ifc_srqc_bits {
3407         u8         state[0x4];
3408         u8         log_srq_size[0x4];
3409         u8         reserved_at_8[0x18];
3410
3411         u8         wq_signature[0x1];
3412         u8         cont_srq[0x1];
3413         u8         reserved_at_22[0x1];
3414         u8         rlky[0x1];
3415         u8         reserved_at_24[0x1];
3416         u8         log_rq_stride[0x3];
3417         u8         xrcd[0x18];
3418
3419         u8         page_offset[0x6];
3420         u8         reserved_at_46[0x2];
3421         u8         cqn[0x18];
3422
3423         u8         reserved_at_60[0x20];
3424
3425         u8         reserved_at_80[0x2];
3426         u8         log_page_size[0x6];
3427         u8         reserved_at_88[0x18];
3428
3429         u8         reserved_at_a0[0x20];
3430
3431         u8         reserved_at_c0[0x8];
3432         u8         pd[0x18];
3433
3434         u8         lwm[0x10];
3435         u8         wqe_cnt[0x10];
3436
3437         u8         reserved_at_100[0x40];
3438
3439         u8         dbr_addr[0x40];
3440
3441         u8         reserved_at_180[0x80];
3442 };
3443
3444 enum {
3445         MLX5_SQC_STATE_RST  = 0x0,
3446         MLX5_SQC_STATE_RDY  = 0x1,
3447         MLX5_SQC_STATE_ERR  = 0x3,
3448 };
3449
3450 struct mlx5_ifc_sqc_bits {
3451         u8         rlky[0x1];
3452         u8         cd_master[0x1];
3453         u8         fre[0x1];
3454         u8         flush_in_error_en[0x1];
3455         u8         allow_multi_pkt_send_wqe[0x1];
3456         u8         min_wqe_inline_mode[0x3];
3457         u8         state[0x4];
3458         u8         reg_umr[0x1];
3459         u8         allow_swp[0x1];
3460         u8         hairpin[0x1];
3461         u8         reserved_at_f[0xb];
3462         u8         ts_format[0x2];
3463         u8         reserved_at_1c[0x4];
3464
3465         u8         reserved_at_20[0x8];
3466         u8         user_index[0x18];
3467
3468         u8         reserved_at_40[0x8];
3469         u8         cqn[0x18];
3470
3471         u8         reserved_at_60[0x8];
3472         u8         hairpin_peer_rq[0x18];
3473
3474         u8         reserved_at_80[0x10];
3475         u8         hairpin_peer_vhca[0x10];
3476
3477         u8         reserved_at_a0[0x20];
3478
3479         u8         reserved_at_c0[0x8];
3480         u8         ts_cqe_to_dest_cqn[0x18];
3481
3482         u8         reserved_at_e0[0x10];
3483         u8         packet_pacing_rate_limit_index[0x10];
3484         u8         tis_lst_sz[0x10];
3485         u8         qos_queue_group_id[0x10];
3486
3487         u8         reserved_at_120[0x40];
3488
3489         u8         reserved_at_160[0x8];
3490         u8         tis_num_0[0x18];
3491
3492         struct mlx5_ifc_wq_bits wq;
3493 };
3494
3495 enum {
3496         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3497         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3498         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3499         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3500         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3501 };
3502
3503 enum {
3504         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3505         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3506         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3507         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3508 };
3509
3510 struct mlx5_ifc_scheduling_context_bits {
3511         u8         element_type[0x8];
3512         u8         reserved_at_8[0x18];
3513
3514         u8         element_attributes[0x20];
3515
3516         u8         parent_element_id[0x20];
3517
3518         u8         reserved_at_60[0x40];
3519
3520         u8         bw_share[0x20];
3521
3522         u8         max_average_bw[0x20];
3523
3524         u8         reserved_at_e0[0x120];
3525 };
3526
3527 struct mlx5_ifc_rqtc_bits {
3528         u8    reserved_at_0[0xa0];
3529
3530         u8    reserved_at_a0[0x5];
3531         u8    list_q_type[0x3];
3532         u8    reserved_at_a8[0x8];
3533         u8    rqt_max_size[0x10];
3534
3535         u8    rq_vhca_id_format[0x1];
3536         u8    reserved_at_c1[0xf];
3537         u8    rqt_actual_size[0x10];
3538
3539         u8    reserved_at_e0[0x6a0];
3540
3541         struct mlx5_ifc_rq_num_bits rq_num[];
3542 };
3543
3544 enum {
3545         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3546         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3547 };
3548
3549 enum {
3550         MLX5_RQC_STATE_RST  = 0x0,
3551         MLX5_RQC_STATE_RDY  = 0x1,
3552         MLX5_RQC_STATE_ERR  = 0x3,
3553 };
3554
3555 struct mlx5_ifc_rqc_bits {
3556         u8         rlky[0x1];
3557         u8         delay_drop_en[0x1];
3558         u8         scatter_fcs[0x1];
3559         u8         vsd[0x1];
3560         u8         mem_rq_type[0x4];
3561         u8         state[0x4];
3562         u8         reserved_at_c[0x1];
3563         u8         flush_in_error_en[0x1];
3564         u8         hairpin[0x1];
3565         u8         reserved_at_f[0xb];
3566         u8         ts_format[0x2];
3567         u8         reserved_at_1c[0x4];
3568
3569         u8         reserved_at_20[0x8];
3570         u8         user_index[0x18];
3571
3572         u8         reserved_at_40[0x8];
3573         u8         cqn[0x18];
3574
3575         u8         counter_set_id[0x8];
3576         u8         reserved_at_68[0x18];
3577
3578         u8         reserved_at_80[0x8];
3579         u8         rmpn[0x18];
3580
3581         u8         reserved_at_a0[0x8];
3582         u8         hairpin_peer_sq[0x18];
3583
3584         u8         reserved_at_c0[0x10];
3585         u8         hairpin_peer_vhca[0x10];
3586
3587         u8         reserved_at_e0[0xa0];
3588
3589         struct mlx5_ifc_wq_bits wq;
3590 };
3591
3592 enum {
3593         MLX5_RMPC_STATE_RDY  = 0x1,
3594         MLX5_RMPC_STATE_ERR  = 0x3,
3595 };
3596
3597 struct mlx5_ifc_rmpc_bits {
3598         u8         reserved_at_0[0x8];
3599         u8         state[0x4];
3600         u8         reserved_at_c[0x14];
3601
3602         u8         basic_cyclic_rcv_wqe[0x1];
3603         u8         reserved_at_21[0x1f];
3604
3605         u8         reserved_at_40[0x140];
3606
3607         struct mlx5_ifc_wq_bits wq;
3608 };
3609
3610 struct mlx5_ifc_nic_vport_context_bits {
3611         u8         reserved_at_0[0x5];
3612         u8         min_wqe_inline_mode[0x3];
3613         u8         reserved_at_8[0x15];
3614         u8         disable_mc_local_lb[0x1];
3615         u8         disable_uc_local_lb[0x1];
3616         u8         roce_en[0x1];
3617
3618         u8         arm_change_event[0x1];
3619         u8         reserved_at_21[0x1a];
3620         u8         event_on_mtu[0x1];
3621         u8         event_on_promisc_change[0x1];
3622         u8         event_on_vlan_change[0x1];
3623         u8         event_on_mc_address_change[0x1];
3624         u8         event_on_uc_address_change[0x1];
3625
3626         u8         reserved_at_40[0xc];
3627
3628         u8         affiliation_criteria[0x4];
3629         u8         affiliated_vhca_id[0x10];
3630
3631         u8         reserved_at_60[0xd0];
3632
3633         u8         mtu[0x10];
3634
3635         u8         system_image_guid[0x40];
3636         u8         port_guid[0x40];
3637         u8         node_guid[0x40];
3638
3639         u8         reserved_at_200[0x140];
3640         u8         qkey_violation_counter[0x10];
3641         u8         reserved_at_350[0x430];
3642
3643         u8         promisc_uc[0x1];
3644         u8         promisc_mc[0x1];
3645         u8         promisc_all[0x1];
3646         u8         reserved_at_783[0x2];
3647         u8         allowed_list_type[0x3];
3648         u8         reserved_at_788[0xc];
3649         u8         allowed_list_size[0xc];
3650
3651         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3652
3653         u8         reserved_at_7e0[0x20];
3654
3655         u8         current_uc_mac_address[][0x40];
3656 };
3657
3658 enum {
3659         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3660         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3661         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3662         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3663         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3664         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3665 };
3666
3667 struct mlx5_ifc_mkc_bits {
3668         u8         reserved_at_0[0x1];
3669         u8         free[0x1];
3670         u8         reserved_at_2[0x1];
3671         u8         access_mode_4_2[0x3];
3672         u8         reserved_at_6[0x7];
3673         u8         relaxed_ordering_write[0x1];
3674         u8         reserved_at_e[0x1];
3675         u8         small_fence_on_rdma_read_response[0x1];
3676         u8         umr_en[0x1];
3677         u8         a[0x1];
3678         u8         rw[0x1];
3679         u8         rr[0x1];
3680         u8         lw[0x1];
3681         u8         lr[0x1];
3682         u8         access_mode_1_0[0x2];
3683         u8         reserved_at_18[0x8];
3684
3685         u8         qpn[0x18];
3686         u8         mkey_7_0[0x8];
3687
3688         u8         reserved_at_40[0x20];
3689
3690         u8         length64[0x1];
3691         u8         bsf_en[0x1];
3692         u8         sync_umr[0x1];
3693         u8         reserved_at_63[0x2];
3694         u8         expected_sigerr_count[0x1];
3695         u8         reserved_at_66[0x1];
3696         u8         en_rinval[0x1];
3697         u8         pd[0x18];
3698
3699         u8         start_addr[0x40];
3700
3701         u8         len[0x40];
3702
3703         u8         bsf_octword_size[0x20];
3704
3705         u8         reserved_at_120[0x80];
3706
3707         u8         translations_octword_size[0x20];
3708
3709         u8         reserved_at_1c0[0x19];
3710         u8         relaxed_ordering_read[0x1];
3711         u8         reserved_at_1d9[0x1];
3712         u8         log_page_size[0x5];
3713
3714         u8         reserved_at_1e0[0x20];
3715 };
3716
3717 struct mlx5_ifc_pkey_bits {
3718         u8         reserved_at_0[0x10];
3719         u8         pkey[0x10];
3720 };
3721
3722 struct mlx5_ifc_array128_auto_bits {
3723         u8         array128_auto[16][0x8];
3724 };
3725
3726 struct mlx5_ifc_hca_vport_context_bits {
3727         u8         field_select[0x20];
3728
3729         u8         reserved_at_20[0xe0];
3730
3731         u8         sm_virt_aware[0x1];
3732         u8         has_smi[0x1];
3733         u8         has_raw[0x1];
3734         u8         grh_required[0x1];
3735         u8         reserved_at_104[0xc];
3736         u8         port_physical_state[0x4];
3737         u8         vport_state_policy[0x4];
3738         u8         port_state[0x4];
3739         u8         vport_state[0x4];
3740
3741         u8         reserved_at_120[0x20];
3742
3743         u8         system_image_guid[0x40];
3744
3745         u8         port_guid[0x40];
3746
3747         u8         node_guid[0x40];
3748
3749         u8         cap_mask1[0x20];
3750
3751         u8         cap_mask1_field_select[0x20];
3752
3753         u8         cap_mask2[0x20];
3754
3755         u8         cap_mask2_field_select[0x20];
3756
3757         u8         reserved_at_280[0x80];
3758
3759         u8         lid[0x10];
3760         u8         reserved_at_310[0x4];
3761         u8         init_type_reply[0x4];
3762         u8         lmc[0x3];
3763         u8         subnet_timeout[0x5];
3764
3765         u8         sm_lid[0x10];
3766         u8         sm_sl[0x4];
3767         u8         reserved_at_334[0xc];
3768
3769         u8         qkey_violation_counter[0x10];
3770         u8         pkey_violation_counter[0x10];
3771
3772         u8         reserved_at_360[0xca0];
3773 };
3774
3775 struct mlx5_ifc_esw_vport_context_bits {
3776         u8         fdb_to_vport_reg_c[0x1];
3777         u8         reserved_at_1[0x2];
3778         u8         vport_svlan_strip[0x1];
3779         u8         vport_cvlan_strip[0x1];
3780         u8         vport_svlan_insert[0x1];
3781         u8         vport_cvlan_insert[0x2];
3782         u8         fdb_to_vport_reg_c_id[0x8];
3783         u8         reserved_at_10[0x10];
3784
3785         u8         reserved_at_20[0x20];
3786
3787         u8         svlan_cfi[0x1];
3788         u8         svlan_pcp[0x3];
3789         u8         svlan_id[0xc];
3790         u8         cvlan_cfi[0x1];
3791         u8         cvlan_pcp[0x3];
3792         u8         cvlan_id[0xc];
3793
3794         u8         reserved_at_60[0x720];
3795
3796         u8         sw_steering_vport_icm_address_rx[0x40];
3797
3798         u8         sw_steering_vport_icm_address_tx[0x40];
3799 };
3800
3801 enum {
3802         MLX5_EQC_STATUS_OK                = 0x0,
3803         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3804 };
3805
3806 enum {
3807         MLX5_EQC_ST_ARMED  = 0x9,
3808         MLX5_EQC_ST_FIRED  = 0xa,
3809 };
3810
3811 struct mlx5_ifc_eqc_bits {
3812         u8         status[0x4];
3813         u8         reserved_at_4[0x9];
3814         u8         ec[0x1];
3815         u8         oi[0x1];
3816         u8         reserved_at_f[0x5];
3817         u8         st[0x4];
3818         u8         reserved_at_18[0x8];
3819
3820         u8         reserved_at_20[0x20];
3821
3822         u8         reserved_at_40[0x14];
3823         u8         page_offset[0x6];
3824         u8         reserved_at_5a[0x6];
3825
3826         u8         reserved_at_60[0x3];
3827         u8         log_eq_size[0x5];
3828         u8         uar_page[0x18];
3829
3830         u8         reserved_at_80[0x20];
3831
3832         u8         reserved_at_a0[0x14];
3833         u8         intr[0xc];
3834
3835         u8         reserved_at_c0[0x3];
3836         u8         log_page_size[0x5];
3837         u8         reserved_at_c8[0x18];
3838
3839         u8         reserved_at_e0[0x60];
3840
3841         u8         reserved_at_140[0x8];
3842         u8         consumer_counter[0x18];
3843
3844         u8         reserved_at_160[0x8];
3845         u8         producer_counter[0x18];
3846
3847         u8         reserved_at_180[0x80];
3848 };
3849
3850 enum {
3851         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3852         MLX5_DCTC_STATE_DRAINING  = 0x1,
3853         MLX5_DCTC_STATE_DRAINED   = 0x2,
3854 };
3855
3856 enum {
3857         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3858         MLX5_DCTC_CS_RES_NA         = 0x1,
3859         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3860 };
3861
3862 enum {
3863         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3864         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3865         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3866         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3867         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3868 };
3869
3870 struct mlx5_ifc_dctc_bits {
3871         u8         reserved_at_0[0x4];
3872         u8         state[0x4];
3873         u8         reserved_at_8[0x18];
3874
3875         u8         reserved_at_20[0x8];
3876         u8         user_index[0x18];
3877
3878         u8         reserved_at_40[0x8];
3879         u8         cqn[0x18];
3880
3881         u8         counter_set_id[0x8];
3882         u8         atomic_mode[0x4];
3883         u8         rre[0x1];
3884         u8         rwe[0x1];
3885         u8         rae[0x1];
3886         u8         atomic_like_write_en[0x1];
3887         u8         latency_sensitive[0x1];
3888         u8         rlky[0x1];
3889         u8         free_ar[0x1];
3890         u8         reserved_at_73[0xd];
3891
3892         u8         reserved_at_80[0x8];
3893         u8         cs_res[0x8];
3894         u8         reserved_at_90[0x3];
3895         u8         min_rnr_nak[0x5];
3896         u8         reserved_at_98[0x8];
3897
3898         u8         reserved_at_a0[0x8];
3899         u8         srqn_xrqn[0x18];
3900
3901         u8         reserved_at_c0[0x8];
3902         u8         pd[0x18];
3903
3904         u8         tclass[0x8];
3905         u8         reserved_at_e8[0x4];
3906         u8         flow_label[0x14];
3907
3908         u8         dc_access_key[0x40];
3909
3910         u8         reserved_at_140[0x5];
3911         u8         mtu[0x3];
3912         u8         port[0x8];
3913         u8         pkey_index[0x10];
3914
3915         u8         reserved_at_160[0x8];
3916         u8         my_addr_index[0x8];
3917         u8         reserved_at_170[0x8];
3918         u8         hop_limit[0x8];
3919
3920         u8         dc_access_key_violation_count[0x20];
3921
3922         u8         reserved_at_1a0[0x14];
3923         u8         dei_cfi[0x1];
3924         u8         eth_prio[0x3];
3925         u8         ecn[0x2];
3926         u8         dscp[0x6];
3927
3928         u8         reserved_at_1c0[0x20];
3929         u8         ece[0x20];
3930 };
3931
3932 enum {
3933         MLX5_CQC_STATUS_OK             = 0x0,
3934         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3935         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3936 };
3937
3938 enum {
3939         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3940         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3941 };
3942
3943 enum {
3944         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3945         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3946         MLX5_CQC_ST_FIRED                                 = 0xa,
3947 };
3948
3949 enum {
3950         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3951         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3952         MLX5_CQ_PERIOD_NUM_MODES
3953 };
3954
3955 struct mlx5_ifc_cqc_bits {
3956         u8         status[0x4];
3957         u8         reserved_at_4[0x2];
3958         u8         dbr_umem_valid[0x1];
3959         u8         apu_cq[0x1];
3960         u8         cqe_sz[0x3];
3961         u8         cc[0x1];
3962         u8         reserved_at_c[0x1];
3963         u8         scqe_break_moderation_en[0x1];
3964         u8         oi[0x1];
3965         u8         cq_period_mode[0x2];
3966         u8         cqe_comp_en[0x1];
3967         u8         mini_cqe_res_format[0x2];
3968         u8         st[0x4];
3969         u8         reserved_at_18[0x8];
3970
3971         u8         reserved_at_20[0x20];
3972
3973         u8         reserved_at_40[0x14];
3974         u8         page_offset[0x6];
3975         u8         reserved_at_5a[0x6];
3976
3977         u8         reserved_at_60[0x3];
3978         u8         log_cq_size[0x5];
3979         u8         uar_page[0x18];
3980
3981         u8         reserved_at_80[0x4];
3982         u8         cq_period[0xc];
3983         u8         cq_max_count[0x10];
3984
3985         u8         c_eqn_or_apu_element[0x20];
3986
3987         u8         reserved_at_c0[0x3];
3988         u8         log_page_size[0x5];
3989         u8         reserved_at_c8[0x18];
3990
3991         u8         reserved_at_e0[0x20];
3992
3993         u8         reserved_at_100[0x8];
3994         u8         last_notified_index[0x18];
3995
3996         u8         reserved_at_120[0x8];
3997         u8         last_solicit_index[0x18];
3998
3999         u8         reserved_at_140[0x8];
4000         u8         consumer_counter[0x18];
4001
4002         u8         reserved_at_160[0x8];
4003         u8         producer_counter[0x18];
4004
4005         u8         reserved_at_180[0x40];
4006
4007         u8         dbr_addr[0x40];
4008 };
4009
4010 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4011         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4012         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4013         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4014         u8         reserved_at_0[0x800];
4015 };
4016
4017 struct mlx5_ifc_query_adapter_param_block_bits {
4018         u8         reserved_at_0[0xc0];
4019
4020         u8         reserved_at_c0[0x8];
4021         u8         ieee_vendor_id[0x18];
4022
4023         u8         reserved_at_e0[0x10];
4024         u8         vsd_vendor_id[0x10];
4025
4026         u8         vsd[208][0x8];
4027
4028         u8         vsd_contd_psid[16][0x8];
4029 };
4030
4031 enum {
4032         MLX5_XRQC_STATE_GOOD   = 0x0,
4033         MLX5_XRQC_STATE_ERROR  = 0x1,
4034 };
4035
4036 enum {
4037         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4038         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4039 };
4040
4041 enum {
4042         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4043 };
4044
4045 struct mlx5_ifc_tag_matching_topology_context_bits {
4046         u8         log_matching_list_sz[0x4];
4047         u8         reserved_at_4[0xc];
4048         u8         append_next_index[0x10];
4049
4050         u8         sw_phase_cnt[0x10];
4051         u8         hw_phase_cnt[0x10];
4052
4053         u8         reserved_at_40[0x40];
4054 };
4055
4056 struct mlx5_ifc_xrqc_bits {
4057         u8         state[0x4];
4058         u8         rlkey[0x1];
4059         u8         reserved_at_5[0xf];
4060         u8         topology[0x4];
4061         u8         reserved_at_18[0x4];
4062         u8         offload[0x4];
4063
4064         u8         reserved_at_20[0x8];
4065         u8         user_index[0x18];
4066
4067         u8         reserved_at_40[0x8];
4068         u8         cqn[0x18];
4069
4070         u8         reserved_at_60[0xa0];
4071
4072         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4073
4074         u8         reserved_at_180[0x280];
4075
4076         struct mlx5_ifc_wq_bits wq;
4077 };
4078
4079 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4080         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4081         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4082         u8         reserved_at_0[0x20];
4083 };
4084
4085 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4086         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4087         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4088         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4089         u8         reserved_at_0[0x20];
4090 };
4091
4092 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4093         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4094         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4095         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4096         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4097         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4098         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4099         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4100         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4101         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4102         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4103         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4104         u8         reserved_at_0[0x7c0];
4105 };
4106
4107 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4108         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4109         u8         reserved_at_0[0x7c0];
4110 };
4111
4112 union mlx5_ifc_event_auto_bits {
4113         struct mlx5_ifc_comp_event_bits comp_event;
4114         struct mlx5_ifc_dct_events_bits dct_events;
4115         struct mlx5_ifc_qp_events_bits qp_events;
4116         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4117         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4118         struct mlx5_ifc_cq_error_bits cq_error;
4119         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4120         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4121         struct mlx5_ifc_gpio_event_bits gpio_event;
4122         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4123         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4124         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4125         u8         reserved_at_0[0xe0];
4126 };
4127
4128 struct mlx5_ifc_health_buffer_bits {
4129         u8         reserved_at_0[0x100];
4130
4131         u8         assert_existptr[0x20];
4132
4133         u8         assert_callra[0x20];
4134
4135         u8         reserved_at_140[0x40];
4136
4137         u8         fw_version[0x20];
4138
4139         u8         hw_id[0x20];
4140
4141         u8         reserved_at_1c0[0x20];
4142
4143         u8         irisc_index[0x8];
4144         u8         synd[0x8];
4145         u8         ext_synd[0x10];
4146 };
4147
4148 struct mlx5_ifc_register_loopback_control_bits {
4149         u8         no_lb[0x1];
4150         u8         reserved_at_1[0x7];
4151         u8         port[0x8];
4152         u8         reserved_at_10[0x10];
4153
4154         u8         reserved_at_20[0x60];
4155 };
4156
4157 struct mlx5_ifc_vport_tc_element_bits {
4158         u8         traffic_class[0x4];
4159         u8         reserved_at_4[0xc];
4160         u8         vport_number[0x10];
4161 };
4162
4163 struct mlx5_ifc_vport_element_bits {
4164         u8         reserved_at_0[0x10];
4165         u8         vport_number[0x10];
4166 };
4167
4168 enum {
4169         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4170         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4171         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4172 };
4173
4174 struct mlx5_ifc_tsar_element_bits {
4175         u8         reserved_at_0[0x8];
4176         u8         tsar_type[0x8];
4177         u8         reserved_at_10[0x10];
4178 };
4179
4180 enum {
4181         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4182         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4183 };
4184
4185 struct mlx5_ifc_teardown_hca_out_bits {
4186         u8         status[0x8];
4187         u8         reserved_at_8[0x18];
4188
4189         u8         syndrome[0x20];
4190
4191         u8         reserved_at_40[0x3f];
4192
4193         u8         state[0x1];
4194 };
4195
4196 enum {
4197         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4198         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4199         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4200 };
4201
4202 struct mlx5_ifc_teardown_hca_in_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_at_10[0x10];
4205
4206         u8         reserved_at_20[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         reserved_at_40[0x10];
4210         u8         profile[0x10];
4211
4212         u8         reserved_at_60[0x20];
4213 };
4214
4215 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4216         u8         status[0x8];
4217         u8         reserved_at_8[0x18];
4218
4219         u8         syndrome[0x20];
4220
4221         u8         reserved_at_40[0x40];
4222 };
4223
4224 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4225         u8         opcode[0x10];
4226         u8         uid[0x10];
4227
4228         u8         reserved_at_20[0x10];
4229         u8         op_mod[0x10];
4230
4231         u8         reserved_at_40[0x8];
4232         u8         qpn[0x18];
4233
4234         u8         reserved_at_60[0x20];
4235
4236         u8         opt_param_mask[0x20];
4237
4238         u8         reserved_at_a0[0x20];
4239
4240         struct mlx5_ifc_qpc_bits qpc;
4241
4242         u8         reserved_at_800[0x80];
4243 };
4244
4245 struct mlx5_ifc_sqd2rts_qp_out_bits {
4246         u8         status[0x8];
4247         u8         reserved_at_8[0x18];
4248
4249         u8         syndrome[0x20];
4250
4251         u8         reserved_at_40[0x40];
4252 };
4253
4254 struct mlx5_ifc_sqd2rts_qp_in_bits {
4255         u8         opcode[0x10];
4256         u8         uid[0x10];
4257
4258         u8         reserved_at_20[0x10];
4259         u8         op_mod[0x10];
4260
4261         u8         reserved_at_40[0x8];
4262         u8         qpn[0x18];
4263
4264         u8         reserved_at_60[0x20];
4265
4266         u8         opt_param_mask[0x20];
4267
4268         u8         reserved_at_a0[0x20];
4269
4270         struct mlx5_ifc_qpc_bits qpc;
4271
4272         u8         reserved_at_800[0x80];
4273 };
4274
4275 struct mlx5_ifc_set_roce_address_out_bits {
4276         u8         status[0x8];
4277         u8         reserved_at_8[0x18];
4278
4279         u8         syndrome[0x20];
4280
4281         u8         reserved_at_40[0x40];
4282 };
4283
4284 struct mlx5_ifc_set_roce_address_in_bits {
4285         u8         opcode[0x10];
4286         u8         reserved_at_10[0x10];
4287
4288         u8         reserved_at_20[0x10];
4289         u8         op_mod[0x10];
4290
4291         u8         roce_address_index[0x10];
4292         u8         reserved_at_50[0xc];
4293         u8         vhca_port_num[0x4];
4294
4295         u8         reserved_at_60[0x20];
4296
4297         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4298 };
4299
4300 struct mlx5_ifc_set_mad_demux_out_bits {
4301         u8         status[0x8];
4302         u8         reserved_at_8[0x18];
4303
4304         u8         syndrome[0x20];
4305
4306         u8         reserved_at_40[0x40];
4307 };
4308
4309 enum {
4310         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4311         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4312 };
4313
4314 struct mlx5_ifc_set_mad_demux_in_bits {
4315         u8         opcode[0x10];
4316         u8         reserved_at_10[0x10];
4317
4318         u8         reserved_at_20[0x10];
4319         u8         op_mod[0x10];
4320
4321         u8         reserved_at_40[0x20];
4322
4323         u8         reserved_at_60[0x6];
4324         u8         demux_mode[0x2];
4325         u8         reserved_at_68[0x18];
4326 };
4327
4328 struct mlx5_ifc_set_l2_table_entry_out_bits {
4329         u8         status[0x8];
4330         u8         reserved_at_8[0x18];
4331
4332         u8         syndrome[0x20];
4333
4334         u8         reserved_at_40[0x40];
4335 };
4336
4337 struct mlx5_ifc_set_l2_table_entry_in_bits {
4338         u8         opcode[0x10];
4339         u8         reserved_at_10[0x10];
4340
4341         u8         reserved_at_20[0x10];
4342         u8         op_mod[0x10];
4343
4344         u8         reserved_at_40[0x60];
4345
4346         u8         reserved_at_a0[0x8];
4347         u8         table_index[0x18];
4348
4349         u8         reserved_at_c0[0x20];
4350
4351         u8         reserved_at_e0[0x13];
4352         u8         vlan_valid[0x1];
4353         u8         vlan[0xc];
4354
4355         struct mlx5_ifc_mac_address_layout_bits mac_address;
4356
4357         u8         reserved_at_140[0xc0];
4358 };
4359
4360 struct mlx5_ifc_set_issi_out_bits {
4361         u8         status[0x8];
4362         u8         reserved_at_8[0x18];
4363
4364         u8         syndrome[0x20];
4365
4366         u8         reserved_at_40[0x40];
4367 };
4368
4369 struct mlx5_ifc_set_issi_in_bits {
4370         u8         opcode[0x10];
4371         u8         reserved_at_10[0x10];
4372
4373         u8         reserved_at_20[0x10];
4374         u8         op_mod[0x10];
4375
4376         u8         reserved_at_40[0x10];
4377         u8         current_issi[0x10];
4378
4379         u8         reserved_at_60[0x20];
4380 };
4381
4382 struct mlx5_ifc_set_hca_cap_out_bits {
4383         u8         status[0x8];
4384         u8         reserved_at_8[0x18];
4385
4386         u8         syndrome[0x20];
4387
4388         u8         reserved_at_40[0x40];
4389 };
4390
4391 struct mlx5_ifc_set_hca_cap_in_bits {
4392         u8         opcode[0x10];
4393         u8         reserved_at_10[0x10];
4394
4395         u8         reserved_at_20[0x10];
4396         u8         op_mod[0x10];
4397
4398         u8         other_function[0x1];
4399         u8         reserved_at_41[0xf];
4400         u8         function_id[0x10];
4401
4402         u8         reserved_at_60[0x20];
4403
4404         union mlx5_ifc_hca_cap_union_bits capability;
4405 };
4406
4407 enum {
4408         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4409         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4410         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4411         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4412         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4413 };
4414
4415 struct mlx5_ifc_set_fte_out_bits {
4416         u8         status[0x8];
4417         u8         reserved_at_8[0x18];
4418
4419         u8         syndrome[0x20];
4420
4421         u8         reserved_at_40[0x40];
4422 };
4423
4424 struct mlx5_ifc_set_fte_in_bits {
4425         u8         opcode[0x10];
4426         u8         reserved_at_10[0x10];
4427
4428         u8         reserved_at_20[0x10];
4429         u8         op_mod[0x10];
4430
4431         u8         other_vport[0x1];
4432         u8         reserved_at_41[0xf];
4433         u8         vport_number[0x10];
4434
4435         u8         reserved_at_60[0x20];
4436
4437         u8         table_type[0x8];
4438         u8         reserved_at_88[0x18];
4439
4440         u8         reserved_at_a0[0x8];
4441         u8         table_id[0x18];
4442
4443         u8         ignore_flow_level[0x1];
4444         u8         reserved_at_c1[0x17];
4445         u8         modify_enable_mask[0x8];
4446
4447         u8         reserved_at_e0[0x20];
4448
4449         u8         flow_index[0x20];
4450
4451         u8         reserved_at_120[0xe0];
4452
4453         struct mlx5_ifc_flow_context_bits flow_context;
4454 };
4455
4456 struct mlx5_ifc_rts2rts_qp_out_bits {
4457         u8         status[0x8];
4458         u8         reserved_at_8[0x18];
4459
4460         u8         syndrome[0x20];
4461
4462         u8         reserved_at_40[0x20];
4463         u8         ece[0x20];
4464 };
4465
4466 struct mlx5_ifc_rts2rts_qp_in_bits {
4467         u8         opcode[0x10];
4468         u8         uid[0x10];
4469
4470         u8         reserved_at_20[0x10];
4471         u8         op_mod[0x10];
4472
4473         u8         reserved_at_40[0x8];
4474         u8         qpn[0x18];
4475
4476         u8         reserved_at_60[0x20];
4477
4478         u8         opt_param_mask[0x20];
4479
4480         u8         ece[0x20];
4481
4482         struct mlx5_ifc_qpc_bits qpc;
4483
4484         u8         reserved_at_800[0x80];
4485 };
4486
4487 struct mlx5_ifc_rtr2rts_qp_out_bits {
4488         u8         status[0x8];
4489         u8         reserved_at_8[0x18];
4490
4491         u8         syndrome[0x20];
4492
4493         u8         reserved_at_40[0x20];
4494         u8         ece[0x20];
4495 };
4496
4497 struct mlx5_ifc_rtr2rts_qp_in_bits {
4498         u8         opcode[0x10];
4499         u8         uid[0x10];
4500
4501         u8         reserved_at_20[0x10];
4502         u8         op_mod[0x10];
4503
4504         u8         reserved_at_40[0x8];
4505         u8         qpn[0x18];
4506
4507         u8         reserved_at_60[0x20];
4508
4509         u8         opt_param_mask[0x20];
4510
4511         u8         ece[0x20];
4512
4513         struct mlx5_ifc_qpc_bits qpc;
4514
4515         u8         reserved_at_800[0x80];
4516 };
4517
4518 struct mlx5_ifc_rst2init_qp_out_bits {
4519         u8         status[0x8];
4520         u8         reserved_at_8[0x18];
4521
4522         u8         syndrome[0x20];
4523
4524         u8         reserved_at_40[0x20];
4525         u8         ece[0x20];
4526 };
4527
4528 struct mlx5_ifc_rst2init_qp_in_bits {
4529         u8         opcode[0x10];
4530         u8         uid[0x10];
4531
4532         u8         reserved_at_20[0x10];
4533         u8         op_mod[0x10];
4534
4535         u8         reserved_at_40[0x8];
4536         u8         qpn[0x18];
4537
4538         u8         reserved_at_60[0x20];
4539
4540         u8         opt_param_mask[0x20];
4541
4542         u8         ece[0x20];
4543
4544         struct mlx5_ifc_qpc_bits qpc;
4545
4546         u8         reserved_at_800[0x80];
4547 };
4548
4549 struct mlx5_ifc_query_xrq_out_bits {
4550         u8         status[0x8];
4551         u8         reserved_at_8[0x18];
4552
4553         u8         syndrome[0x20];
4554
4555         u8         reserved_at_40[0x40];
4556
4557         struct mlx5_ifc_xrqc_bits xrq_context;
4558 };
4559
4560 struct mlx5_ifc_query_xrq_in_bits {
4561         u8         opcode[0x10];
4562         u8         reserved_at_10[0x10];
4563
4564         u8         reserved_at_20[0x10];
4565         u8         op_mod[0x10];
4566
4567         u8         reserved_at_40[0x8];
4568         u8         xrqn[0x18];
4569
4570         u8         reserved_at_60[0x20];
4571 };
4572
4573 struct mlx5_ifc_query_xrc_srq_out_bits {
4574         u8         status[0x8];
4575         u8         reserved_at_8[0x18];
4576
4577         u8         syndrome[0x20];
4578
4579         u8         reserved_at_40[0x40];
4580
4581         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4582
4583         u8         reserved_at_280[0x600];
4584
4585         u8         pas[][0x40];
4586 };
4587
4588 struct mlx5_ifc_query_xrc_srq_in_bits {
4589         u8         opcode[0x10];
4590         u8         reserved_at_10[0x10];
4591
4592         u8         reserved_at_20[0x10];
4593         u8         op_mod[0x10];
4594
4595         u8         reserved_at_40[0x8];
4596         u8         xrc_srqn[0x18];
4597
4598         u8         reserved_at_60[0x20];
4599 };
4600
4601 enum {
4602         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4603         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4604 };
4605
4606 struct mlx5_ifc_query_vport_state_out_bits {
4607         u8         status[0x8];
4608         u8         reserved_at_8[0x18];
4609
4610         u8         syndrome[0x20];
4611
4612         u8         reserved_at_40[0x20];
4613
4614         u8         reserved_at_60[0x18];
4615         u8         admin_state[0x4];
4616         u8         state[0x4];
4617 };
4618
4619 enum {
4620         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4621         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4622         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4623 };
4624
4625 struct mlx5_ifc_arm_monitor_counter_in_bits {
4626         u8         opcode[0x10];
4627         u8         uid[0x10];
4628
4629         u8         reserved_at_20[0x10];
4630         u8         op_mod[0x10];
4631
4632         u8         reserved_at_40[0x20];
4633
4634         u8         reserved_at_60[0x20];
4635 };
4636
4637 struct mlx5_ifc_arm_monitor_counter_out_bits {
4638         u8         status[0x8];
4639         u8         reserved_at_8[0x18];
4640
4641         u8         syndrome[0x20];
4642
4643         u8         reserved_at_40[0x40];
4644 };
4645
4646 enum {
4647         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4648         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4649 };
4650
4651 enum mlx5_monitor_counter_ppcnt {
4652         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4653         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4654         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4655         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4656         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4657         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4658 };
4659
4660 enum {
4661         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4662 };
4663
4664 struct mlx5_ifc_monitor_counter_output_bits {
4665         u8         reserved_at_0[0x4];
4666         u8         type[0x4];
4667         u8         reserved_at_8[0x8];
4668         u8         counter[0x10];
4669
4670         u8         counter_group_id[0x20];
4671 };
4672
4673 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4674 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4675 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4676                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4677
4678 struct mlx5_ifc_set_monitor_counter_in_bits {
4679         u8         opcode[0x10];
4680         u8         uid[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x10];
4686         u8         num_of_counters[0x10];
4687
4688         u8         reserved_at_60[0x20];
4689
4690         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4691 };
4692
4693 struct mlx5_ifc_set_monitor_counter_out_bits {
4694         u8         status[0x8];
4695         u8         reserved_at_8[0x18];
4696
4697         u8         syndrome[0x20];
4698
4699         u8         reserved_at_40[0x40];
4700 };
4701
4702 struct mlx5_ifc_query_vport_state_in_bits {
4703         u8         opcode[0x10];
4704         u8         reserved_at_10[0x10];
4705
4706         u8         reserved_at_20[0x10];
4707         u8         op_mod[0x10];
4708
4709         u8         other_vport[0x1];
4710         u8         reserved_at_41[0xf];
4711         u8         vport_number[0x10];
4712
4713         u8         reserved_at_60[0x20];
4714 };
4715
4716 struct mlx5_ifc_query_vnic_env_out_bits {
4717         u8         status[0x8];
4718         u8         reserved_at_8[0x18];
4719
4720         u8         syndrome[0x20];
4721
4722         u8         reserved_at_40[0x40];
4723
4724         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4725 };
4726
4727 enum {
4728         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4729 };
4730
4731 struct mlx5_ifc_query_vnic_env_in_bits {
4732         u8         opcode[0x10];
4733         u8         reserved_at_10[0x10];
4734
4735         u8         reserved_at_20[0x10];
4736         u8         op_mod[0x10];
4737
4738         u8         other_vport[0x1];
4739         u8         reserved_at_41[0xf];
4740         u8         vport_number[0x10];
4741
4742         u8         reserved_at_60[0x20];
4743 };
4744
4745 struct mlx5_ifc_query_vport_counter_out_bits {
4746         u8         status[0x8];
4747         u8         reserved_at_8[0x18];
4748
4749         u8         syndrome[0x20];
4750
4751         u8         reserved_at_40[0x40];
4752
4753         struct mlx5_ifc_traffic_counter_bits received_errors;
4754
4755         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4756
4757         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4758
4759         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4760
4761         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4762
4763         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4764
4765         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4766
4767         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4768
4769         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4770
4771         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4772
4773         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4774
4775         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4776
4777         u8         reserved_at_680[0xa00];
4778 };
4779
4780 enum {
4781         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4782 };
4783
4784 struct mlx5_ifc_query_vport_counter_in_bits {
4785         u8         opcode[0x10];
4786         u8         reserved_at_10[0x10];
4787
4788         u8         reserved_at_20[0x10];
4789         u8         op_mod[0x10];
4790
4791         u8         other_vport[0x1];
4792         u8         reserved_at_41[0xb];
4793         u8         port_num[0x4];
4794         u8         vport_number[0x10];
4795
4796         u8         reserved_at_60[0x60];
4797
4798         u8         clear[0x1];
4799         u8         reserved_at_c1[0x1f];
4800
4801         u8         reserved_at_e0[0x20];
4802 };
4803
4804 struct mlx5_ifc_query_tis_out_bits {
4805         u8         status[0x8];
4806         u8         reserved_at_8[0x18];
4807
4808         u8         syndrome[0x20];
4809
4810         u8         reserved_at_40[0x40];
4811
4812         struct mlx5_ifc_tisc_bits tis_context;
4813 };
4814
4815 struct mlx5_ifc_query_tis_in_bits {
4816         u8         opcode[0x10];
4817         u8         reserved_at_10[0x10];
4818
4819         u8         reserved_at_20[0x10];
4820         u8         op_mod[0x10];
4821
4822         u8         reserved_at_40[0x8];
4823         u8         tisn[0x18];
4824
4825         u8         reserved_at_60[0x20];
4826 };
4827
4828 struct mlx5_ifc_query_tir_out_bits {
4829         u8         status[0x8];
4830         u8         reserved_at_8[0x18];
4831
4832         u8         syndrome[0x20];
4833
4834         u8         reserved_at_40[0xc0];
4835
4836         struct mlx5_ifc_tirc_bits tir_context;
4837 };
4838
4839 struct mlx5_ifc_query_tir_in_bits {
4840         u8         opcode[0x10];
4841         u8         reserved_at_10[0x10];
4842
4843         u8         reserved_at_20[0x10];
4844         u8         op_mod[0x10];
4845
4846         u8         reserved_at_40[0x8];
4847         u8         tirn[0x18];
4848
4849         u8         reserved_at_60[0x20];
4850 };
4851
4852 struct mlx5_ifc_query_srq_out_bits {
4853         u8         status[0x8];
4854         u8         reserved_at_8[0x18];
4855
4856         u8         syndrome[0x20];
4857
4858         u8         reserved_at_40[0x40];
4859
4860         struct mlx5_ifc_srqc_bits srq_context_entry;
4861
4862         u8         reserved_at_280[0x600];
4863
4864         u8         pas[][0x40];
4865 };
4866
4867 struct mlx5_ifc_query_srq_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_at_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         reserved_at_40[0x8];
4875         u8         srqn[0x18];
4876
4877         u8         reserved_at_60[0x20];
4878 };
4879
4880 struct mlx5_ifc_query_sq_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         reserved_at_40[0xc0];
4887
4888         struct mlx5_ifc_sqc_bits sq_context;
4889 };
4890
4891 struct mlx5_ifc_query_sq_in_bits {
4892         u8         opcode[0x10];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         reserved_at_20[0x10];
4896         u8         op_mod[0x10];
4897
4898         u8         reserved_at_40[0x8];
4899         u8         sqn[0x18];
4900
4901         u8         reserved_at_60[0x20];
4902 };
4903
4904 struct mlx5_ifc_query_special_contexts_out_bits {
4905         u8         status[0x8];
4906         u8         reserved_at_8[0x18];
4907
4908         u8         syndrome[0x20];
4909
4910         u8         dump_fill_mkey[0x20];
4911
4912         u8         resd_lkey[0x20];
4913
4914         u8         null_mkey[0x20];
4915
4916         u8         reserved_at_a0[0x60];
4917 };
4918
4919 struct mlx5_ifc_query_special_contexts_in_bits {
4920         u8         opcode[0x10];
4921         u8         reserved_at_10[0x10];
4922
4923         u8         reserved_at_20[0x10];
4924         u8         op_mod[0x10];
4925
4926         u8         reserved_at_40[0x40];
4927 };
4928
4929 struct mlx5_ifc_query_scheduling_element_out_bits {
4930         u8         opcode[0x10];
4931         u8         reserved_at_10[0x10];
4932
4933         u8         reserved_at_20[0x10];
4934         u8         op_mod[0x10];
4935
4936         u8         reserved_at_40[0xc0];
4937
4938         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4939
4940         u8         reserved_at_300[0x100];
4941 };
4942
4943 enum {
4944         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4945         SCHEDULING_HIERARCHY_NIC = 0x3,
4946 };
4947
4948 struct mlx5_ifc_query_scheduling_element_in_bits {
4949         u8         opcode[0x10];
4950         u8         reserved_at_10[0x10];
4951
4952         u8         reserved_at_20[0x10];
4953         u8         op_mod[0x10];
4954
4955         u8         scheduling_hierarchy[0x8];
4956         u8         reserved_at_48[0x18];
4957
4958         u8         scheduling_element_id[0x20];
4959
4960         u8         reserved_at_80[0x180];
4961 };
4962
4963 struct mlx5_ifc_query_rqt_out_bits {
4964         u8         status[0x8];
4965         u8         reserved_at_8[0x18];
4966
4967         u8         syndrome[0x20];
4968
4969         u8         reserved_at_40[0xc0];
4970
4971         struct mlx5_ifc_rqtc_bits rqt_context;
4972 };
4973
4974 struct mlx5_ifc_query_rqt_in_bits {
4975         u8         opcode[0x10];
4976         u8         reserved_at_10[0x10];
4977
4978         u8         reserved_at_20[0x10];
4979         u8         op_mod[0x10];
4980
4981         u8         reserved_at_40[0x8];
4982         u8         rqtn[0x18];
4983
4984         u8         reserved_at_60[0x20];
4985 };
4986
4987 struct mlx5_ifc_query_rq_out_bits {
4988         u8         status[0x8];
4989         u8         reserved_at_8[0x18];
4990
4991         u8         syndrome[0x20];
4992
4993         u8         reserved_at_40[0xc0];
4994
4995         struct mlx5_ifc_rqc_bits rq_context;
4996 };
4997
4998 struct mlx5_ifc_query_rq_in_bits {
4999         u8         opcode[0x10];
5000         u8         reserved_at_10[0x10];
5001
5002         u8         reserved_at_20[0x10];
5003         u8         op_mod[0x10];
5004
5005         u8         reserved_at_40[0x8];
5006         u8         rqn[0x18];
5007
5008         u8         reserved_at_60[0x20];
5009 };
5010
5011 struct mlx5_ifc_query_roce_address_out_bits {
5012         u8         status[0x8];
5013         u8         reserved_at_8[0x18];
5014
5015         u8         syndrome[0x20];
5016
5017         u8         reserved_at_40[0x40];
5018
5019         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5020 };
5021
5022 struct mlx5_ifc_query_roce_address_in_bits {
5023         u8         opcode[0x10];
5024         u8         reserved_at_10[0x10];
5025
5026         u8         reserved_at_20[0x10];
5027         u8         op_mod[0x10];
5028
5029         u8         roce_address_index[0x10];
5030         u8         reserved_at_50[0xc];
5031         u8         vhca_port_num[0x4];
5032
5033         u8         reserved_at_60[0x20];
5034 };
5035
5036 struct mlx5_ifc_query_rmp_out_bits {
5037         u8         status[0x8];
5038         u8         reserved_at_8[0x18];
5039
5040         u8         syndrome[0x20];
5041
5042         u8         reserved_at_40[0xc0];
5043
5044         struct mlx5_ifc_rmpc_bits rmp_context;
5045 };
5046
5047 struct mlx5_ifc_query_rmp_in_bits {
5048         u8         opcode[0x10];
5049         u8         reserved_at_10[0x10];
5050
5051         u8         reserved_at_20[0x10];
5052         u8         op_mod[0x10];
5053
5054         u8         reserved_at_40[0x8];
5055         u8         rmpn[0x18];
5056
5057         u8         reserved_at_60[0x20];
5058 };
5059
5060 struct mlx5_ifc_query_qp_out_bits {
5061         u8         status[0x8];
5062         u8         reserved_at_8[0x18];
5063
5064         u8         syndrome[0x20];
5065
5066         u8         reserved_at_40[0x20];
5067         u8         ece[0x20];
5068
5069         u8         opt_param_mask[0x20];
5070
5071         u8         reserved_at_a0[0x20];
5072
5073         struct mlx5_ifc_qpc_bits qpc;
5074
5075         u8         reserved_at_800[0x80];
5076
5077         u8         pas[][0x40];
5078 };
5079
5080 struct mlx5_ifc_query_qp_in_bits {
5081         u8         opcode[0x10];
5082         u8         reserved_at_10[0x10];
5083
5084         u8         reserved_at_20[0x10];
5085         u8         op_mod[0x10];
5086
5087         u8         reserved_at_40[0x8];
5088         u8         qpn[0x18];
5089
5090         u8         reserved_at_60[0x20];
5091 };
5092
5093 struct mlx5_ifc_query_q_counter_out_bits {
5094         u8         status[0x8];
5095         u8         reserved_at_8[0x18];
5096
5097         u8         syndrome[0x20];
5098
5099         u8         reserved_at_40[0x40];
5100
5101         u8         rx_write_requests[0x20];
5102
5103         u8         reserved_at_a0[0x20];
5104
5105         u8         rx_read_requests[0x20];
5106
5107         u8         reserved_at_e0[0x20];
5108
5109         u8         rx_atomic_requests[0x20];
5110
5111         u8         reserved_at_120[0x20];
5112
5113         u8         rx_dct_connect[0x20];
5114
5115         u8         reserved_at_160[0x20];
5116
5117         u8         out_of_buffer[0x20];
5118
5119         u8         reserved_at_1a0[0x20];
5120
5121         u8         out_of_sequence[0x20];
5122
5123         u8         reserved_at_1e0[0x20];
5124
5125         u8         duplicate_request[0x20];
5126
5127         u8         reserved_at_220[0x20];
5128
5129         u8         rnr_nak_retry_err[0x20];
5130
5131         u8         reserved_at_260[0x20];
5132
5133         u8         packet_seq_err[0x20];
5134
5135         u8         reserved_at_2a0[0x20];
5136
5137         u8         implied_nak_seq_err[0x20];
5138
5139         u8         reserved_at_2e0[0x20];
5140
5141         u8         local_ack_timeout_err[0x20];
5142
5143         u8         reserved_at_320[0xa0];
5144
5145         u8         resp_local_length_error[0x20];
5146
5147         u8         req_local_length_error[0x20];
5148
5149         u8         resp_local_qp_error[0x20];
5150
5151         u8         local_operation_error[0x20];
5152
5153         u8         resp_local_protection[0x20];
5154
5155         u8         req_local_protection[0x20];
5156
5157         u8         resp_cqe_error[0x20];
5158
5159         u8         req_cqe_error[0x20];
5160
5161         u8         req_mw_binding[0x20];
5162
5163         u8         req_bad_response[0x20];
5164
5165         u8         req_remote_invalid_request[0x20];
5166
5167         u8         resp_remote_invalid_request[0x20];
5168
5169         u8         req_remote_access_errors[0x20];
5170
5171         u8         resp_remote_access_errors[0x20];
5172
5173         u8         req_remote_operation_errors[0x20];
5174
5175         u8         req_transport_retries_exceeded[0x20];
5176
5177         u8         cq_overflow[0x20];
5178
5179         u8         resp_cqe_flush_error[0x20];
5180
5181         u8         req_cqe_flush_error[0x20];
5182
5183         u8         reserved_at_620[0x20];
5184
5185         u8         roce_adp_retrans[0x20];
5186
5187         u8         roce_adp_retrans_to[0x20];
5188
5189         u8         roce_slow_restart[0x20];
5190
5191         u8         roce_slow_restart_cnps[0x20];
5192
5193         u8         roce_slow_restart_trans[0x20];
5194
5195         u8         reserved_at_6e0[0x120];
5196 };
5197
5198 struct mlx5_ifc_query_q_counter_in_bits {
5199         u8         opcode[0x10];
5200         u8         reserved_at_10[0x10];
5201
5202         u8         reserved_at_20[0x10];
5203         u8         op_mod[0x10];
5204
5205         u8         reserved_at_40[0x80];
5206
5207         u8         clear[0x1];
5208         u8         reserved_at_c1[0x1f];
5209
5210         u8         reserved_at_e0[0x18];
5211         u8         counter_set_id[0x8];
5212 };
5213
5214 struct mlx5_ifc_query_pages_out_bits {
5215         u8         status[0x8];
5216         u8         reserved_at_8[0x18];
5217
5218         u8         syndrome[0x20];
5219
5220         u8         embedded_cpu_function[0x1];
5221         u8         reserved_at_41[0xf];
5222         u8         function_id[0x10];
5223
5224         u8         num_pages[0x20];
5225 };
5226
5227 enum {
5228         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5229         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5230         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5231 };
5232
5233 struct mlx5_ifc_query_pages_in_bits {
5234         u8         opcode[0x10];
5235         u8         reserved_at_10[0x10];
5236
5237         u8         reserved_at_20[0x10];
5238         u8         op_mod[0x10];
5239
5240         u8         embedded_cpu_function[0x1];
5241         u8         reserved_at_41[0xf];
5242         u8         function_id[0x10];
5243
5244         u8         reserved_at_60[0x20];
5245 };
5246
5247 struct mlx5_ifc_query_nic_vport_context_out_bits {
5248         u8         status[0x8];
5249         u8         reserved_at_8[0x18];
5250
5251         u8         syndrome[0x20];
5252
5253         u8         reserved_at_40[0x40];
5254
5255         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5256 };
5257
5258 struct mlx5_ifc_query_nic_vport_context_in_bits {
5259         u8         opcode[0x10];
5260         u8         reserved_at_10[0x10];
5261
5262         u8         reserved_at_20[0x10];
5263         u8         op_mod[0x10];
5264
5265         u8         other_vport[0x1];
5266         u8         reserved_at_41[0xf];
5267         u8         vport_number[0x10];
5268
5269         u8         reserved_at_60[0x5];
5270         u8         allowed_list_type[0x3];
5271         u8         reserved_at_68[0x18];
5272 };
5273
5274 struct mlx5_ifc_query_mkey_out_bits {
5275         u8         status[0x8];
5276         u8         reserved_at_8[0x18];
5277
5278         u8         syndrome[0x20];
5279
5280         u8         reserved_at_40[0x40];
5281
5282         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5283
5284         u8         reserved_at_280[0x600];
5285
5286         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5287
5288         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5289 };
5290
5291 struct mlx5_ifc_query_mkey_in_bits {
5292         u8         opcode[0x10];
5293         u8         reserved_at_10[0x10];
5294
5295         u8         reserved_at_20[0x10];
5296         u8         op_mod[0x10];
5297
5298         u8         reserved_at_40[0x8];
5299         u8         mkey_index[0x18];
5300
5301         u8         pg_access[0x1];
5302         u8         reserved_at_61[0x1f];
5303 };
5304
5305 struct mlx5_ifc_query_mad_demux_out_bits {
5306         u8         status[0x8];
5307         u8         reserved_at_8[0x18];
5308
5309         u8         syndrome[0x20];
5310
5311         u8         reserved_at_40[0x40];
5312
5313         u8         mad_dumux_parameters_block[0x20];
5314 };
5315
5316 struct mlx5_ifc_query_mad_demux_in_bits {
5317         u8         opcode[0x10];
5318         u8         reserved_at_10[0x10];
5319
5320         u8         reserved_at_20[0x10];
5321         u8         op_mod[0x10];
5322
5323         u8         reserved_at_40[0x40];
5324 };
5325
5326 struct mlx5_ifc_query_l2_table_entry_out_bits {
5327         u8         status[0x8];
5328         u8         reserved_at_8[0x18];
5329
5330         u8         syndrome[0x20];
5331
5332         u8         reserved_at_40[0xa0];
5333
5334         u8         reserved_at_e0[0x13];
5335         u8         vlan_valid[0x1];
5336         u8         vlan[0xc];
5337
5338         struct mlx5_ifc_mac_address_layout_bits mac_address;
5339
5340         u8         reserved_at_140[0xc0];
5341 };
5342
5343 struct mlx5_ifc_query_l2_table_entry_in_bits {
5344         u8         opcode[0x10];
5345         u8         reserved_at_10[0x10];
5346
5347         u8         reserved_at_20[0x10];
5348         u8         op_mod[0x10];
5349
5350         u8         reserved_at_40[0x60];
5351
5352         u8         reserved_at_a0[0x8];
5353         u8         table_index[0x18];
5354
5355         u8         reserved_at_c0[0x140];
5356 };
5357
5358 struct mlx5_ifc_query_issi_out_bits {
5359         u8         status[0x8];
5360         u8         reserved_at_8[0x18];
5361
5362         u8         syndrome[0x20];
5363
5364         u8         reserved_at_40[0x10];
5365         u8         current_issi[0x10];
5366
5367         u8         reserved_at_60[0xa0];
5368
5369         u8         reserved_at_100[76][0x8];
5370         u8         supported_issi_dw0[0x20];
5371 };
5372
5373 struct mlx5_ifc_query_issi_in_bits {
5374         u8         opcode[0x10];
5375         u8         reserved_at_10[0x10];
5376
5377         u8         reserved_at_20[0x10];
5378         u8         op_mod[0x10];
5379
5380         u8         reserved_at_40[0x40];
5381 };
5382
5383 struct mlx5_ifc_set_driver_version_out_bits {
5384         u8         status[0x8];
5385         u8         reserved_0[0x18];
5386
5387         u8         syndrome[0x20];
5388         u8         reserved_1[0x40];
5389 };
5390
5391 struct mlx5_ifc_set_driver_version_in_bits {
5392         u8         opcode[0x10];
5393         u8         reserved_0[0x10];
5394
5395         u8         reserved_1[0x10];
5396         u8         op_mod[0x10];
5397
5398         u8         reserved_2[0x40];
5399         u8         driver_version[64][0x8];
5400 };
5401
5402 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5403         u8         status[0x8];
5404         u8         reserved_at_8[0x18];
5405
5406         u8         syndrome[0x20];
5407
5408         u8         reserved_at_40[0x40];
5409
5410         struct mlx5_ifc_pkey_bits pkey[];
5411 };
5412
5413 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5414         u8         opcode[0x10];
5415         u8         reserved_at_10[0x10];
5416
5417         u8         reserved_at_20[0x10];
5418         u8         op_mod[0x10];
5419
5420         u8         other_vport[0x1];
5421         u8         reserved_at_41[0xb];
5422         u8         port_num[0x4];
5423         u8         vport_number[0x10];
5424
5425         u8         reserved_at_60[0x10];
5426         u8         pkey_index[0x10];
5427 };
5428
5429 enum {
5430         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5431         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5432         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5433 };
5434
5435 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5436         u8         status[0x8];
5437         u8         reserved_at_8[0x18];
5438
5439         u8         syndrome[0x20];
5440
5441         u8         reserved_at_40[0x20];
5442
5443         u8         gids_num[0x10];
5444         u8         reserved_at_70[0x10];
5445
5446         struct mlx5_ifc_array128_auto_bits gid[];
5447 };
5448
5449 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5450         u8         opcode[0x10];
5451         u8         reserved_at_10[0x10];
5452
5453         u8         reserved_at_20[0x10];
5454         u8         op_mod[0x10];
5455
5456         u8         other_vport[0x1];
5457         u8         reserved_at_41[0xb];
5458         u8         port_num[0x4];
5459         u8         vport_number[0x10];
5460
5461         u8         reserved_at_60[0x10];
5462         u8         gid_index[0x10];
5463 };
5464
5465 struct mlx5_ifc_query_hca_vport_context_out_bits {
5466         u8         status[0x8];
5467         u8         reserved_at_8[0x18];
5468
5469         u8         syndrome[0x20];
5470
5471         u8         reserved_at_40[0x40];
5472
5473         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5474 };
5475
5476 struct mlx5_ifc_query_hca_vport_context_in_bits {
5477         u8         opcode[0x10];
5478         u8         reserved_at_10[0x10];
5479
5480         u8         reserved_at_20[0x10];
5481         u8         op_mod[0x10];
5482
5483         u8         other_vport[0x1];
5484         u8         reserved_at_41[0xb];
5485         u8         port_num[0x4];
5486         u8         vport_number[0x10];
5487
5488         u8         reserved_at_60[0x20];
5489 };
5490
5491 struct mlx5_ifc_query_hca_cap_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498
5499         union mlx5_ifc_hca_cap_union_bits capability;
5500 };
5501
5502 struct mlx5_ifc_query_hca_cap_in_bits {
5503         u8         opcode[0x10];
5504         u8         reserved_at_10[0x10];
5505
5506         u8         reserved_at_20[0x10];
5507         u8         op_mod[0x10];
5508
5509         u8         other_function[0x1];
5510         u8         reserved_at_41[0xf];
5511         u8         function_id[0x10];
5512
5513         u8         reserved_at_60[0x20];
5514 };
5515
5516 struct mlx5_ifc_other_hca_cap_bits {
5517         u8         roce[0x1];
5518         u8         reserved_at_1[0x27f];
5519 };
5520
5521 struct mlx5_ifc_query_other_hca_cap_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524
5525         u8         syndrome[0x20];
5526
5527         u8         reserved_at_40[0x40];
5528
5529         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5530 };
5531
5532 struct mlx5_ifc_query_other_hca_cap_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_at_10[0x10];
5535
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         reserved_at_40[0x10];
5540         u8         function_id[0x10];
5541
5542         u8         reserved_at_60[0x20];
5543 };
5544
5545 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5546         u8         status[0x8];
5547         u8         reserved_at_8[0x18];
5548
5549         u8         syndrome[0x20];
5550
5551         u8         reserved_at_40[0x40];
5552 };
5553
5554 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5555         u8         opcode[0x10];
5556         u8         reserved_at_10[0x10];
5557
5558         u8         reserved_at_20[0x10];
5559         u8         op_mod[0x10];
5560
5561         u8         reserved_at_40[0x10];
5562         u8         function_id[0x10];
5563         u8         field_select[0x20];
5564
5565         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5566 };
5567
5568 struct mlx5_ifc_flow_table_context_bits {
5569         u8         reformat_en[0x1];
5570         u8         decap_en[0x1];
5571         u8         sw_owner[0x1];
5572         u8         termination_table[0x1];
5573         u8         table_miss_action[0x4];
5574         u8         level[0x8];
5575         u8         reserved_at_10[0x8];
5576         u8         log_size[0x8];
5577
5578         u8         reserved_at_20[0x8];
5579         u8         table_miss_id[0x18];
5580
5581         u8         reserved_at_40[0x8];
5582         u8         lag_master_next_table_id[0x18];
5583
5584         u8         reserved_at_60[0x60];
5585
5586         u8         sw_owner_icm_root_1[0x40];
5587
5588         u8         sw_owner_icm_root_0[0x40];
5589
5590 };
5591
5592 struct mlx5_ifc_query_flow_table_out_bits {
5593         u8         status[0x8];
5594         u8         reserved_at_8[0x18];
5595
5596         u8         syndrome[0x20];
5597
5598         u8         reserved_at_40[0x80];
5599
5600         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5601 };
5602
5603 struct mlx5_ifc_query_flow_table_in_bits {
5604         u8         opcode[0x10];
5605         u8         reserved_at_10[0x10];
5606
5607         u8         reserved_at_20[0x10];
5608         u8         op_mod[0x10];
5609
5610         u8         reserved_at_40[0x40];
5611
5612         u8         table_type[0x8];
5613         u8         reserved_at_88[0x18];
5614
5615         u8         reserved_at_a0[0x8];
5616         u8         table_id[0x18];
5617
5618         u8         reserved_at_c0[0x140];
5619 };
5620
5621 struct mlx5_ifc_query_fte_out_bits {
5622         u8         status[0x8];
5623         u8         reserved_at_8[0x18];
5624
5625         u8         syndrome[0x20];
5626
5627         u8         reserved_at_40[0x1c0];
5628
5629         struct mlx5_ifc_flow_context_bits flow_context;
5630 };
5631
5632 struct mlx5_ifc_query_fte_in_bits {
5633         u8         opcode[0x10];
5634         u8         reserved_at_10[0x10];
5635
5636         u8         reserved_at_20[0x10];
5637         u8         op_mod[0x10];
5638
5639         u8         reserved_at_40[0x40];
5640
5641         u8         table_type[0x8];
5642         u8         reserved_at_88[0x18];
5643
5644         u8         reserved_at_a0[0x8];
5645         u8         table_id[0x18];
5646
5647         u8         reserved_at_c0[0x40];
5648
5649         u8         flow_index[0x20];
5650
5651         u8         reserved_at_120[0xe0];
5652 };
5653
5654 enum {
5655         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5656         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5657         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5658         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5659         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5660         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5661 };
5662
5663 struct mlx5_ifc_query_flow_group_out_bits {
5664         u8         status[0x8];
5665         u8         reserved_at_8[0x18];
5666
5667         u8         syndrome[0x20];
5668
5669         u8         reserved_at_40[0xa0];
5670
5671         u8         start_flow_index[0x20];
5672
5673         u8         reserved_at_100[0x20];
5674
5675         u8         end_flow_index[0x20];
5676
5677         u8         reserved_at_140[0xa0];
5678
5679         u8         reserved_at_1e0[0x18];
5680         u8         match_criteria_enable[0x8];
5681
5682         struct mlx5_ifc_fte_match_param_bits match_criteria;
5683
5684         u8         reserved_at_1200[0xe00];
5685 };
5686
5687 struct mlx5_ifc_query_flow_group_in_bits {
5688         u8         opcode[0x10];
5689         u8         reserved_at_10[0x10];
5690
5691         u8         reserved_at_20[0x10];
5692         u8         op_mod[0x10];
5693
5694         u8         reserved_at_40[0x40];
5695
5696         u8         table_type[0x8];
5697         u8         reserved_at_88[0x18];
5698
5699         u8         reserved_at_a0[0x8];
5700         u8         table_id[0x18];
5701
5702         u8         group_id[0x20];
5703
5704         u8         reserved_at_e0[0x120];
5705 };
5706
5707 struct mlx5_ifc_query_flow_counter_out_bits {
5708         u8         status[0x8];
5709         u8         reserved_at_8[0x18];
5710
5711         u8         syndrome[0x20];
5712
5713         u8         reserved_at_40[0x40];
5714
5715         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5716 };
5717
5718 struct mlx5_ifc_query_flow_counter_in_bits {
5719         u8         opcode[0x10];
5720         u8         reserved_at_10[0x10];
5721
5722         u8         reserved_at_20[0x10];
5723         u8         op_mod[0x10];
5724
5725         u8         reserved_at_40[0x80];
5726
5727         u8         clear[0x1];
5728         u8         reserved_at_c1[0xf];
5729         u8         num_of_counters[0x10];
5730
5731         u8         flow_counter_id[0x20];
5732 };
5733
5734 struct mlx5_ifc_query_esw_vport_context_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x40];
5741
5742         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5743 };
5744
5745 struct mlx5_ifc_query_esw_vport_context_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         other_vport[0x1];
5753         u8         reserved_at_41[0xf];
5754         u8         vport_number[0x10];
5755
5756         u8         reserved_at_60[0x20];
5757 };
5758
5759 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5760         u8         status[0x8];
5761         u8         reserved_at_8[0x18];
5762
5763         u8         syndrome[0x20];
5764
5765         u8         reserved_at_40[0x40];
5766 };
5767
5768 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5769         u8         reserved_at_0[0x1b];
5770         u8         fdb_to_vport_reg_c_id[0x1];
5771         u8         vport_cvlan_insert[0x1];
5772         u8         vport_svlan_insert[0x1];
5773         u8         vport_cvlan_strip[0x1];
5774         u8         vport_svlan_strip[0x1];
5775 };
5776
5777 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_at_10[0x10];
5780
5781         u8         reserved_at_20[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         other_vport[0x1];
5785         u8         reserved_at_41[0xf];
5786         u8         vport_number[0x10];
5787
5788         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5789
5790         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5791 };
5792
5793 struct mlx5_ifc_query_eq_out_bits {
5794         u8         status[0x8];
5795         u8         reserved_at_8[0x18];
5796
5797         u8         syndrome[0x20];
5798
5799         u8         reserved_at_40[0x40];
5800
5801         struct mlx5_ifc_eqc_bits eq_context_entry;
5802
5803         u8         reserved_at_280[0x40];
5804
5805         u8         event_bitmask[0x40];
5806
5807         u8         reserved_at_300[0x580];
5808
5809         u8         pas[][0x40];
5810 };
5811
5812 struct mlx5_ifc_query_eq_in_bits {
5813         u8         opcode[0x10];
5814         u8         reserved_at_10[0x10];
5815
5816         u8         reserved_at_20[0x10];
5817         u8         op_mod[0x10];
5818
5819         u8         reserved_at_40[0x18];
5820         u8         eq_number[0x8];
5821
5822         u8         reserved_at_60[0x20];
5823 };
5824
5825 struct mlx5_ifc_packet_reformat_context_in_bits {
5826         u8         reformat_type[0x8];
5827         u8         reserved_at_8[0x4];
5828         u8         reformat_param_0[0x4];
5829         u8         reserved_at_10[0x6];
5830         u8         reformat_data_size[0xa];
5831
5832         u8         reformat_param_1[0x8];
5833         u8         reserved_at_28[0x8];
5834         u8         reformat_data[2][0x8];
5835
5836         u8         more_reformat_data[][0x8];
5837 };
5838
5839 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5840         u8         status[0x8];
5841         u8         reserved_at_8[0x18];
5842
5843         u8         syndrome[0x20];
5844
5845         u8         reserved_at_40[0xa0];
5846
5847         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5848 };
5849
5850 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5851         u8         opcode[0x10];
5852         u8         reserved_at_10[0x10];
5853
5854         u8         reserved_at_20[0x10];
5855         u8         op_mod[0x10];
5856
5857         u8         packet_reformat_id[0x20];
5858
5859         u8         reserved_at_60[0xa0];
5860 };
5861
5862 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5863         u8         status[0x8];
5864         u8         reserved_at_8[0x18];
5865
5866         u8         syndrome[0x20];
5867
5868         u8         packet_reformat_id[0x20];
5869
5870         u8         reserved_at_60[0x20];
5871 };
5872
5873 enum {
5874         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
5875         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
5876         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
5877 };
5878
5879 enum mlx5_reformat_ctx_type {
5880         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5881         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5882         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5883         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5884         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5885         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
5886         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
5887 };
5888
5889 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5890         u8         opcode[0x10];
5891         u8         reserved_at_10[0x10];
5892
5893         u8         reserved_at_20[0x10];
5894         u8         op_mod[0x10];
5895
5896         u8         reserved_at_40[0xa0];
5897
5898         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5899 };
5900
5901 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5902         u8         status[0x8];
5903         u8         reserved_at_8[0x18];
5904
5905         u8         syndrome[0x20];
5906
5907         u8         reserved_at_40[0x40];
5908 };
5909
5910 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5911         u8         opcode[0x10];
5912         u8         reserved_at_10[0x10];
5913
5914         u8         reserved_20[0x10];
5915         u8         op_mod[0x10];
5916
5917         u8         packet_reformat_id[0x20];
5918
5919         u8         reserved_60[0x20];
5920 };
5921
5922 struct mlx5_ifc_set_action_in_bits {
5923         u8         action_type[0x4];
5924         u8         field[0xc];
5925         u8         reserved_at_10[0x3];
5926         u8         offset[0x5];
5927         u8         reserved_at_18[0x3];
5928         u8         length[0x5];
5929
5930         u8         data[0x20];
5931 };
5932
5933 struct mlx5_ifc_add_action_in_bits {
5934         u8         action_type[0x4];
5935         u8         field[0xc];
5936         u8         reserved_at_10[0x10];
5937
5938         u8         data[0x20];
5939 };
5940
5941 struct mlx5_ifc_copy_action_in_bits {
5942         u8         action_type[0x4];
5943         u8         src_field[0xc];
5944         u8         reserved_at_10[0x3];
5945         u8         src_offset[0x5];
5946         u8         reserved_at_18[0x3];
5947         u8         length[0x5];
5948
5949         u8         reserved_at_20[0x4];
5950         u8         dst_field[0xc];
5951         u8         reserved_at_30[0x3];
5952         u8         dst_offset[0x5];
5953         u8         reserved_at_38[0x8];
5954 };
5955
5956 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5957         struct mlx5_ifc_set_action_in_bits  set_action_in;
5958         struct mlx5_ifc_add_action_in_bits  add_action_in;
5959         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5960         u8         reserved_at_0[0x40];
5961 };
5962
5963 enum {
5964         MLX5_ACTION_TYPE_SET   = 0x1,
5965         MLX5_ACTION_TYPE_ADD   = 0x2,
5966         MLX5_ACTION_TYPE_COPY  = 0x3,
5967 };
5968
5969 enum {
5970         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5971         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5972         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5973         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5974         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5975         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5976         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5977         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5978         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5979         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5980         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5981         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5982         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5983         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5984         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5985         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5986         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5987         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5988         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5989         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5990         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5991         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5992         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5993         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5994         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5995         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5996         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5997         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5998         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5999         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6000         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6001         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6002         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6003         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6004         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6005         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6006         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6007         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6008         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6009 };
6010
6011 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6012         u8         status[0x8];
6013         u8         reserved_at_8[0x18];
6014
6015         u8         syndrome[0x20];
6016
6017         u8         modify_header_id[0x20];
6018
6019         u8         reserved_at_60[0x20];
6020 };
6021
6022 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6023         u8         opcode[0x10];
6024         u8         reserved_at_10[0x10];
6025
6026         u8         reserved_at_20[0x10];
6027         u8         op_mod[0x10];
6028
6029         u8         reserved_at_40[0x20];
6030
6031         u8         table_type[0x8];
6032         u8         reserved_at_68[0x10];
6033         u8         num_of_actions[0x8];
6034
6035         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6036 };
6037
6038 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6039         u8         status[0x8];
6040         u8         reserved_at_8[0x18];
6041
6042         u8         syndrome[0x20];
6043
6044         u8         reserved_at_40[0x40];
6045 };
6046
6047 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6048         u8         opcode[0x10];
6049         u8         reserved_at_10[0x10];
6050
6051         u8         reserved_at_20[0x10];
6052         u8         op_mod[0x10];
6053
6054         u8         modify_header_id[0x20];
6055
6056         u8         reserved_at_60[0x20];
6057 };
6058
6059 struct mlx5_ifc_query_modify_header_context_in_bits {
6060         u8         opcode[0x10];
6061         u8         uid[0x10];
6062
6063         u8         reserved_at_20[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         modify_header_id[0x20];
6067
6068         u8         reserved_at_60[0xa0];
6069 };
6070
6071 struct mlx5_ifc_query_dct_out_bits {
6072         u8         status[0x8];
6073         u8         reserved_at_8[0x18];
6074
6075         u8         syndrome[0x20];
6076
6077         u8         reserved_at_40[0x40];
6078
6079         struct mlx5_ifc_dctc_bits dct_context_entry;
6080
6081         u8         reserved_at_280[0x180];
6082 };
6083
6084 struct mlx5_ifc_query_dct_in_bits {
6085         u8         opcode[0x10];
6086         u8         reserved_at_10[0x10];
6087
6088         u8         reserved_at_20[0x10];
6089         u8         op_mod[0x10];
6090
6091         u8         reserved_at_40[0x8];
6092         u8         dctn[0x18];
6093
6094         u8         reserved_at_60[0x20];
6095 };
6096
6097 struct mlx5_ifc_query_cq_out_bits {
6098         u8         status[0x8];
6099         u8         reserved_at_8[0x18];
6100
6101         u8         syndrome[0x20];
6102
6103         u8         reserved_at_40[0x40];
6104
6105         struct mlx5_ifc_cqc_bits cq_context;
6106
6107         u8         reserved_at_280[0x600];
6108
6109         u8         pas[][0x40];
6110 };
6111
6112 struct mlx5_ifc_query_cq_in_bits {
6113         u8         opcode[0x10];
6114         u8         reserved_at_10[0x10];
6115
6116         u8         reserved_at_20[0x10];
6117         u8         op_mod[0x10];
6118
6119         u8         reserved_at_40[0x8];
6120         u8         cqn[0x18];
6121
6122         u8         reserved_at_60[0x20];
6123 };
6124
6125 struct mlx5_ifc_query_cong_status_out_bits {
6126         u8         status[0x8];
6127         u8         reserved_at_8[0x18];
6128
6129         u8         syndrome[0x20];
6130
6131         u8         reserved_at_40[0x20];
6132
6133         u8         enable[0x1];
6134         u8         tag_enable[0x1];
6135         u8         reserved_at_62[0x1e];
6136 };
6137
6138 struct mlx5_ifc_query_cong_status_in_bits {
6139         u8         opcode[0x10];
6140         u8         reserved_at_10[0x10];
6141
6142         u8         reserved_at_20[0x10];
6143         u8         op_mod[0x10];
6144
6145         u8         reserved_at_40[0x18];
6146         u8         priority[0x4];
6147         u8         cong_protocol[0x4];
6148
6149         u8         reserved_at_60[0x20];
6150 };
6151
6152 struct mlx5_ifc_query_cong_statistics_out_bits {
6153         u8         status[0x8];
6154         u8         reserved_at_8[0x18];
6155
6156         u8         syndrome[0x20];
6157
6158         u8         reserved_at_40[0x40];
6159
6160         u8         rp_cur_flows[0x20];
6161
6162         u8         sum_flows[0x20];
6163
6164         u8         rp_cnp_ignored_high[0x20];
6165
6166         u8         rp_cnp_ignored_low[0x20];
6167
6168         u8         rp_cnp_handled_high[0x20];
6169
6170         u8         rp_cnp_handled_low[0x20];
6171
6172         u8         reserved_at_140[0x100];
6173
6174         u8         time_stamp_high[0x20];
6175
6176         u8         time_stamp_low[0x20];
6177
6178         u8         accumulators_period[0x20];
6179
6180         u8         np_ecn_marked_roce_packets_high[0x20];
6181
6182         u8         np_ecn_marked_roce_packets_low[0x20];
6183
6184         u8         np_cnp_sent_high[0x20];
6185
6186         u8         np_cnp_sent_low[0x20];
6187
6188         u8         reserved_at_320[0x560];
6189 };
6190
6191 struct mlx5_ifc_query_cong_statistics_in_bits {
6192         u8         opcode[0x10];
6193         u8         reserved_at_10[0x10];
6194
6195         u8         reserved_at_20[0x10];
6196         u8         op_mod[0x10];
6197
6198         u8         clear[0x1];
6199         u8         reserved_at_41[0x1f];
6200
6201         u8         reserved_at_60[0x20];
6202 };
6203
6204 struct mlx5_ifc_query_cong_params_out_bits {
6205         u8         status[0x8];
6206         u8         reserved_at_8[0x18];
6207
6208         u8         syndrome[0x20];
6209
6210         u8         reserved_at_40[0x40];
6211
6212         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6213 };
6214
6215 struct mlx5_ifc_query_cong_params_in_bits {
6216         u8         opcode[0x10];
6217         u8         reserved_at_10[0x10];
6218
6219         u8         reserved_at_20[0x10];
6220         u8         op_mod[0x10];
6221
6222         u8         reserved_at_40[0x1c];
6223         u8         cong_protocol[0x4];
6224
6225         u8         reserved_at_60[0x20];
6226 };
6227
6228 struct mlx5_ifc_query_adapter_out_bits {
6229         u8         status[0x8];
6230         u8         reserved_at_8[0x18];
6231
6232         u8         syndrome[0x20];
6233
6234         u8         reserved_at_40[0x40];
6235
6236         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6237 };
6238
6239 struct mlx5_ifc_query_adapter_in_bits {
6240         u8         opcode[0x10];
6241         u8         reserved_at_10[0x10];
6242
6243         u8         reserved_at_20[0x10];
6244         u8         op_mod[0x10];
6245
6246         u8         reserved_at_40[0x40];
6247 };
6248
6249 struct mlx5_ifc_qp_2rst_out_bits {
6250         u8         status[0x8];
6251         u8         reserved_at_8[0x18];
6252
6253         u8         syndrome[0x20];
6254
6255         u8         reserved_at_40[0x40];
6256 };
6257
6258 struct mlx5_ifc_qp_2rst_in_bits {
6259         u8         opcode[0x10];
6260         u8         uid[0x10];
6261
6262         u8         reserved_at_20[0x10];
6263         u8         op_mod[0x10];
6264
6265         u8         reserved_at_40[0x8];
6266         u8         qpn[0x18];
6267
6268         u8         reserved_at_60[0x20];
6269 };
6270
6271 struct mlx5_ifc_qp_2err_out_bits {
6272         u8         status[0x8];
6273         u8         reserved_at_8[0x18];
6274
6275         u8         syndrome[0x20];
6276
6277         u8         reserved_at_40[0x40];
6278 };
6279
6280 struct mlx5_ifc_qp_2err_in_bits {
6281         u8         opcode[0x10];
6282         u8         uid[0x10];
6283
6284         u8         reserved_at_20[0x10];
6285         u8         op_mod[0x10];
6286
6287         u8         reserved_at_40[0x8];
6288         u8         qpn[0x18];
6289
6290         u8         reserved_at_60[0x20];
6291 };
6292
6293 struct mlx5_ifc_page_fault_resume_out_bits {
6294         u8         status[0x8];
6295         u8         reserved_at_8[0x18];
6296
6297         u8         syndrome[0x20];
6298
6299         u8         reserved_at_40[0x40];
6300 };
6301
6302 struct mlx5_ifc_page_fault_resume_in_bits {
6303         u8         opcode[0x10];
6304         u8         reserved_at_10[0x10];
6305
6306         u8         reserved_at_20[0x10];
6307         u8         op_mod[0x10];
6308
6309         u8         error[0x1];
6310         u8         reserved_at_41[0x4];
6311         u8         page_fault_type[0x3];
6312         u8         wq_number[0x18];
6313
6314         u8         reserved_at_60[0x8];
6315         u8         token[0x18];
6316 };
6317
6318 struct mlx5_ifc_nop_out_bits {
6319         u8         status[0x8];
6320         u8         reserved_at_8[0x18];
6321
6322         u8         syndrome[0x20];
6323
6324         u8         reserved_at_40[0x40];
6325 };
6326
6327 struct mlx5_ifc_nop_in_bits {
6328         u8         opcode[0x10];
6329         u8         reserved_at_10[0x10];
6330
6331         u8         reserved_at_20[0x10];
6332         u8         op_mod[0x10];
6333
6334         u8         reserved_at_40[0x40];
6335 };
6336
6337 struct mlx5_ifc_modify_vport_state_out_bits {
6338         u8         status[0x8];
6339         u8         reserved_at_8[0x18];
6340
6341         u8         syndrome[0x20];
6342
6343         u8         reserved_at_40[0x40];
6344 };
6345
6346 struct mlx5_ifc_modify_vport_state_in_bits {
6347         u8         opcode[0x10];
6348         u8         reserved_at_10[0x10];
6349
6350         u8         reserved_at_20[0x10];
6351         u8         op_mod[0x10];
6352
6353         u8         other_vport[0x1];
6354         u8         reserved_at_41[0xf];
6355         u8         vport_number[0x10];
6356
6357         u8         reserved_at_60[0x18];
6358         u8         admin_state[0x4];
6359         u8         reserved_at_7c[0x4];
6360 };
6361
6362 struct mlx5_ifc_modify_tis_out_bits {
6363         u8         status[0x8];
6364         u8         reserved_at_8[0x18];
6365
6366         u8         syndrome[0x20];
6367
6368         u8         reserved_at_40[0x40];
6369 };
6370
6371 struct mlx5_ifc_modify_tis_bitmask_bits {
6372         u8         reserved_at_0[0x20];
6373
6374         u8         reserved_at_20[0x1d];
6375         u8         lag_tx_port_affinity[0x1];
6376         u8         strict_lag_tx_port_affinity[0x1];
6377         u8         prio[0x1];
6378 };
6379
6380 struct mlx5_ifc_modify_tis_in_bits {
6381         u8         opcode[0x10];
6382         u8         uid[0x10];
6383
6384         u8         reserved_at_20[0x10];
6385         u8         op_mod[0x10];
6386
6387         u8         reserved_at_40[0x8];
6388         u8         tisn[0x18];
6389
6390         u8         reserved_at_60[0x20];
6391
6392         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6393
6394         u8         reserved_at_c0[0x40];
6395
6396         struct mlx5_ifc_tisc_bits ctx;
6397 };
6398
6399 struct mlx5_ifc_modify_tir_bitmask_bits {
6400         u8         reserved_at_0[0x20];
6401
6402         u8         reserved_at_20[0x1b];
6403         u8         self_lb_en[0x1];
6404         u8         reserved_at_3c[0x1];
6405         u8         hash[0x1];
6406         u8         reserved_at_3e[0x1];
6407         u8         lro[0x1];
6408 };
6409
6410 struct mlx5_ifc_modify_tir_out_bits {
6411         u8         status[0x8];
6412         u8         reserved_at_8[0x18];
6413
6414         u8         syndrome[0x20];
6415
6416         u8         reserved_at_40[0x40];
6417 };
6418
6419 struct mlx5_ifc_modify_tir_in_bits {
6420         u8         opcode[0x10];
6421         u8         uid[0x10];
6422
6423         u8         reserved_at_20[0x10];
6424         u8         op_mod[0x10];
6425
6426         u8         reserved_at_40[0x8];
6427         u8         tirn[0x18];
6428
6429         u8         reserved_at_60[0x20];
6430
6431         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6432
6433         u8         reserved_at_c0[0x40];
6434
6435         struct mlx5_ifc_tirc_bits ctx;
6436 };
6437
6438 struct mlx5_ifc_modify_sq_out_bits {
6439         u8         status[0x8];
6440         u8         reserved_at_8[0x18];
6441
6442         u8         syndrome[0x20];
6443
6444         u8         reserved_at_40[0x40];
6445 };
6446
6447 struct mlx5_ifc_modify_sq_in_bits {
6448         u8         opcode[0x10];
6449         u8         uid[0x10];
6450
6451         u8         reserved_at_20[0x10];
6452         u8         op_mod[0x10];
6453
6454         u8         sq_state[0x4];
6455         u8         reserved_at_44[0x4];
6456         u8         sqn[0x18];
6457
6458         u8         reserved_at_60[0x20];
6459
6460         u8         modify_bitmask[0x40];
6461
6462         u8         reserved_at_c0[0x40];
6463
6464         struct mlx5_ifc_sqc_bits ctx;
6465 };
6466
6467 struct mlx5_ifc_modify_scheduling_element_out_bits {
6468         u8         status[0x8];
6469         u8         reserved_at_8[0x18];
6470
6471         u8         syndrome[0x20];
6472
6473         u8         reserved_at_40[0x1c0];
6474 };
6475
6476 enum {
6477         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6478         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6479 };
6480
6481 struct mlx5_ifc_modify_scheduling_element_in_bits {
6482         u8         opcode[0x10];
6483         u8         reserved_at_10[0x10];
6484
6485         u8         reserved_at_20[0x10];
6486         u8         op_mod[0x10];
6487
6488         u8         scheduling_hierarchy[0x8];
6489         u8         reserved_at_48[0x18];
6490
6491         u8         scheduling_element_id[0x20];
6492
6493         u8         reserved_at_80[0x20];
6494
6495         u8         modify_bitmask[0x20];
6496
6497         u8         reserved_at_c0[0x40];
6498
6499         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6500
6501         u8         reserved_at_300[0x100];
6502 };
6503
6504 struct mlx5_ifc_modify_rqt_out_bits {
6505         u8         status[0x8];
6506         u8         reserved_at_8[0x18];
6507
6508         u8         syndrome[0x20];
6509
6510         u8         reserved_at_40[0x40];
6511 };
6512
6513 struct mlx5_ifc_rqt_bitmask_bits {
6514         u8         reserved_at_0[0x20];
6515
6516         u8         reserved_at_20[0x1f];
6517         u8         rqn_list[0x1];
6518 };
6519
6520 struct mlx5_ifc_modify_rqt_in_bits {
6521         u8         opcode[0x10];
6522         u8         uid[0x10];
6523
6524         u8         reserved_at_20[0x10];
6525         u8         op_mod[0x10];
6526
6527         u8         reserved_at_40[0x8];
6528         u8         rqtn[0x18];
6529
6530         u8         reserved_at_60[0x20];
6531
6532         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6533
6534         u8         reserved_at_c0[0x40];
6535
6536         struct mlx5_ifc_rqtc_bits ctx;
6537 };
6538
6539 struct mlx5_ifc_modify_rq_out_bits {
6540         u8         status[0x8];
6541         u8         reserved_at_8[0x18];
6542
6543         u8         syndrome[0x20];
6544
6545         u8         reserved_at_40[0x40];
6546 };
6547
6548 enum {
6549         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6550         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6551         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6552 };
6553
6554 struct mlx5_ifc_modify_rq_in_bits {
6555         u8         opcode[0x10];
6556         u8         uid[0x10];
6557
6558         u8         reserved_at_20[0x10];
6559         u8         op_mod[0x10];
6560
6561         u8         rq_state[0x4];
6562         u8         reserved_at_44[0x4];
6563         u8         rqn[0x18];
6564
6565         u8         reserved_at_60[0x20];
6566
6567         u8         modify_bitmask[0x40];
6568
6569         u8         reserved_at_c0[0x40];
6570
6571         struct mlx5_ifc_rqc_bits ctx;
6572 };
6573
6574 struct mlx5_ifc_modify_rmp_out_bits {
6575         u8         status[0x8];
6576         u8         reserved_at_8[0x18];
6577
6578         u8         syndrome[0x20];
6579
6580         u8         reserved_at_40[0x40];
6581 };
6582
6583 struct mlx5_ifc_rmp_bitmask_bits {
6584         u8         reserved_at_0[0x20];
6585
6586         u8         reserved_at_20[0x1f];
6587         u8         lwm[0x1];
6588 };
6589
6590 struct mlx5_ifc_modify_rmp_in_bits {
6591         u8         opcode[0x10];
6592         u8         uid[0x10];
6593
6594         u8         reserved_at_20[0x10];
6595         u8         op_mod[0x10];
6596
6597         u8         rmp_state[0x4];
6598         u8         reserved_at_44[0x4];
6599         u8         rmpn[0x18];
6600
6601         u8         reserved_at_60[0x20];
6602
6603         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6604
6605         u8         reserved_at_c0[0x40];
6606
6607         struct mlx5_ifc_rmpc_bits ctx;
6608 };
6609
6610 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6611         u8         status[0x8];
6612         u8         reserved_at_8[0x18];
6613
6614         u8         syndrome[0x20];
6615
6616         u8         reserved_at_40[0x40];
6617 };
6618
6619 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6620         u8         reserved_at_0[0x12];
6621         u8         affiliation[0x1];
6622         u8         reserved_at_13[0x1];
6623         u8         disable_uc_local_lb[0x1];
6624         u8         disable_mc_local_lb[0x1];
6625         u8         node_guid[0x1];
6626         u8         port_guid[0x1];
6627         u8         min_inline[0x1];
6628         u8         mtu[0x1];
6629         u8         change_event[0x1];
6630         u8         promisc[0x1];
6631         u8         permanent_address[0x1];
6632         u8         addresses_list[0x1];
6633         u8         roce_en[0x1];
6634         u8         reserved_at_1f[0x1];
6635 };
6636
6637 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6638         u8         opcode[0x10];
6639         u8         reserved_at_10[0x10];
6640
6641         u8         reserved_at_20[0x10];
6642         u8         op_mod[0x10];
6643
6644         u8         other_vport[0x1];
6645         u8         reserved_at_41[0xf];
6646         u8         vport_number[0x10];
6647
6648         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6649
6650         u8         reserved_at_80[0x780];
6651
6652         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6653 };
6654
6655 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6656         u8         status[0x8];
6657         u8         reserved_at_8[0x18];
6658
6659         u8         syndrome[0x20];
6660
6661         u8         reserved_at_40[0x40];
6662 };
6663
6664 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6665         u8         opcode[0x10];
6666         u8         reserved_at_10[0x10];
6667
6668         u8         reserved_at_20[0x10];
6669         u8         op_mod[0x10];
6670
6671         u8         other_vport[0x1];
6672         u8         reserved_at_41[0xb];
6673         u8         port_num[0x4];
6674         u8         vport_number[0x10];
6675
6676         u8         reserved_at_60[0x20];
6677
6678         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6679 };
6680
6681 struct mlx5_ifc_modify_cq_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_at_8[0x18];
6684
6685         u8         syndrome[0x20];
6686
6687         u8         reserved_at_40[0x40];
6688 };
6689
6690 enum {
6691         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6692         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6693 };
6694
6695 struct mlx5_ifc_modify_cq_in_bits {
6696         u8         opcode[0x10];
6697         u8         uid[0x10];
6698
6699         u8         reserved_at_20[0x10];
6700         u8         op_mod[0x10];
6701
6702         u8         reserved_at_40[0x8];
6703         u8         cqn[0x18];
6704
6705         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6706
6707         struct mlx5_ifc_cqc_bits cq_context;
6708
6709         u8         reserved_at_280[0x60];
6710
6711         u8         cq_umem_valid[0x1];
6712         u8         reserved_at_2e1[0x1f];
6713
6714         u8         reserved_at_300[0x580];
6715
6716         u8         pas[][0x40];
6717 };
6718
6719 struct mlx5_ifc_modify_cong_status_out_bits {
6720         u8         status[0x8];
6721         u8         reserved_at_8[0x18];
6722
6723         u8         syndrome[0x20];
6724
6725         u8         reserved_at_40[0x40];
6726 };
6727
6728 struct mlx5_ifc_modify_cong_status_in_bits {
6729         u8         opcode[0x10];
6730         u8         reserved_at_10[0x10];
6731
6732         u8         reserved_at_20[0x10];
6733         u8         op_mod[0x10];
6734
6735         u8         reserved_at_40[0x18];
6736         u8         priority[0x4];
6737         u8         cong_protocol[0x4];
6738
6739         u8         enable[0x1];
6740         u8         tag_enable[0x1];
6741         u8         reserved_at_62[0x1e];
6742 };
6743
6744 struct mlx5_ifc_modify_cong_params_out_bits {
6745         u8         status[0x8];
6746         u8         reserved_at_8[0x18];
6747
6748         u8         syndrome[0x20];
6749
6750         u8         reserved_at_40[0x40];
6751 };
6752
6753 struct mlx5_ifc_modify_cong_params_in_bits {
6754         u8         opcode[0x10];
6755         u8         reserved_at_10[0x10];
6756
6757         u8         reserved_at_20[0x10];
6758         u8         op_mod[0x10];
6759
6760         u8         reserved_at_40[0x1c];
6761         u8         cong_protocol[0x4];
6762
6763         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6764
6765         u8         reserved_at_80[0x80];
6766
6767         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6768 };
6769
6770 struct mlx5_ifc_manage_pages_out_bits {
6771         u8         status[0x8];
6772         u8         reserved_at_8[0x18];
6773
6774         u8         syndrome[0x20];
6775
6776         u8         output_num_entries[0x20];
6777
6778         u8         reserved_at_60[0x20];
6779
6780         u8         pas[][0x40];
6781 };
6782
6783 enum {
6784         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6785         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6786         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6787 };
6788
6789 struct mlx5_ifc_manage_pages_in_bits {
6790         u8         opcode[0x10];
6791         u8         reserved_at_10[0x10];
6792
6793         u8         reserved_at_20[0x10];
6794         u8         op_mod[0x10];
6795
6796         u8         embedded_cpu_function[0x1];
6797         u8         reserved_at_41[0xf];
6798         u8         function_id[0x10];
6799
6800         u8         input_num_entries[0x20];
6801
6802         u8         pas[][0x40];
6803 };
6804
6805 struct mlx5_ifc_mad_ifc_out_bits {
6806         u8         status[0x8];
6807         u8         reserved_at_8[0x18];
6808
6809         u8         syndrome[0x20];
6810
6811         u8         reserved_at_40[0x40];
6812
6813         u8         response_mad_packet[256][0x8];
6814 };
6815
6816 struct mlx5_ifc_mad_ifc_in_bits {
6817         u8         opcode[0x10];
6818         u8         reserved_at_10[0x10];
6819
6820         u8         reserved_at_20[0x10];
6821         u8         op_mod[0x10];
6822
6823         u8         remote_lid[0x10];
6824         u8         reserved_at_50[0x8];
6825         u8         port[0x8];
6826
6827         u8         reserved_at_60[0x20];
6828
6829         u8         mad[256][0x8];
6830 };
6831
6832 struct mlx5_ifc_init_hca_out_bits {
6833         u8         status[0x8];
6834         u8         reserved_at_8[0x18];
6835
6836         u8         syndrome[0x20];
6837
6838         u8         reserved_at_40[0x40];
6839 };
6840
6841 struct mlx5_ifc_init_hca_in_bits {
6842         u8         opcode[0x10];
6843         u8         reserved_at_10[0x10];
6844
6845         u8         reserved_at_20[0x10];
6846         u8         op_mod[0x10];
6847
6848         u8         reserved_at_40[0x40];
6849         u8         sw_owner_id[4][0x20];
6850 };
6851
6852 struct mlx5_ifc_init2rtr_qp_out_bits {
6853         u8         status[0x8];
6854         u8         reserved_at_8[0x18];
6855
6856         u8         syndrome[0x20];
6857
6858         u8         reserved_at_40[0x20];
6859         u8         ece[0x20];
6860 };
6861
6862 struct mlx5_ifc_init2rtr_qp_in_bits {
6863         u8         opcode[0x10];
6864         u8         uid[0x10];
6865
6866         u8         reserved_at_20[0x10];
6867         u8         op_mod[0x10];
6868
6869         u8         reserved_at_40[0x8];
6870         u8         qpn[0x18];
6871
6872         u8         reserved_at_60[0x20];
6873
6874         u8         opt_param_mask[0x20];
6875
6876         u8         ece[0x20];
6877
6878         struct mlx5_ifc_qpc_bits qpc;
6879
6880         u8         reserved_at_800[0x80];
6881 };
6882
6883 struct mlx5_ifc_init2init_qp_out_bits {
6884         u8         status[0x8];
6885         u8         reserved_at_8[0x18];
6886
6887         u8         syndrome[0x20];
6888
6889         u8         reserved_at_40[0x20];
6890         u8         ece[0x20];
6891 };
6892
6893 struct mlx5_ifc_init2init_qp_in_bits {
6894         u8         opcode[0x10];
6895         u8         uid[0x10];
6896
6897         u8         reserved_at_20[0x10];
6898         u8         op_mod[0x10];
6899
6900         u8         reserved_at_40[0x8];
6901         u8         qpn[0x18];
6902
6903         u8         reserved_at_60[0x20];
6904
6905         u8         opt_param_mask[0x20];
6906
6907         u8         ece[0x20];
6908
6909         struct mlx5_ifc_qpc_bits qpc;
6910
6911         u8         reserved_at_800[0x80];
6912 };
6913
6914 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6915         u8         status[0x8];
6916         u8         reserved_at_8[0x18];
6917
6918         u8         syndrome[0x20];
6919
6920         u8         reserved_at_40[0x40];
6921
6922         u8         packet_headers_log[128][0x8];
6923
6924         u8         packet_syndrome[64][0x8];
6925 };
6926
6927 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6928         u8         opcode[0x10];
6929         u8         reserved_at_10[0x10];
6930
6931         u8         reserved_at_20[0x10];
6932         u8         op_mod[0x10];
6933
6934         u8         reserved_at_40[0x40];
6935 };
6936
6937 struct mlx5_ifc_gen_eqe_in_bits {
6938         u8         opcode[0x10];
6939         u8         reserved_at_10[0x10];
6940
6941         u8         reserved_at_20[0x10];
6942         u8         op_mod[0x10];
6943
6944         u8         reserved_at_40[0x18];
6945         u8         eq_number[0x8];
6946
6947         u8         reserved_at_60[0x20];
6948
6949         u8         eqe[64][0x8];
6950 };
6951
6952 struct mlx5_ifc_gen_eq_out_bits {
6953         u8         status[0x8];
6954         u8         reserved_at_8[0x18];
6955
6956         u8         syndrome[0x20];
6957
6958         u8         reserved_at_40[0x40];
6959 };
6960
6961 struct mlx5_ifc_enable_hca_out_bits {
6962         u8         status[0x8];
6963         u8         reserved_at_8[0x18];
6964
6965         u8         syndrome[0x20];
6966
6967         u8         reserved_at_40[0x20];
6968 };
6969
6970 struct mlx5_ifc_enable_hca_in_bits {
6971         u8         opcode[0x10];
6972         u8         reserved_at_10[0x10];
6973
6974         u8         reserved_at_20[0x10];
6975         u8         op_mod[0x10];
6976
6977         u8         embedded_cpu_function[0x1];
6978         u8         reserved_at_41[0xf];
6979         u8         function_id[0x10];
6980
6981         u8         reserved_at_60[0x20];
6982 };
6983
6984 struct mlx5_ifc_drain_dct_out_bits {
6985         u8         status[0x8];
6986         u8         reserved_at_8[0x18];
6987
6988         u8         syndrome[0x20];
6989
6990         u8         reserved_at_40[0x40];
6991 };
6992
6993 struct mlx5_ifc_drain_dct_in_bits {
6994         u8         opcode[0x10];
6995         u8         uid[0x10];
6996
6997         u8         reserved_at_20[0x10];
6998         u8         op_mod[0x10];
6999
7000         u8         reserved_at_40[0x8];
7001         u8         dctn[0x18];
7002
7003         u8         reserved_at_60[0x20];
7004 };
7005
7006 struct mlx5_ifc_disable_hca_out_bits {
7007         u8         status[0x8];
7008         u8         reserved_at_8[0x18];
7009
7010         u8         syndrome[0x20];
7011
7012         u8         reserved_at_40[0x20];
7013 };
7014
7015 struct mlx5_ifc_disable_hca_in_bits {
7016         u8         opcode[0x10];
7017         u8         reserved_at_10[0x10];
7018
7019         u8         reserved_at_20[0x10];
7020         u8         op_mod[0x10];
7021
7022         u8         embedded_cpu_function[0x1];
7023         u8         reserved_at_41[0xf];
7024         u8         function_id[0x10];
7025
7026         u8         reserved_at_60[0x20];
7027 };
7028
7029 struct mlx5_ifc_detach_from_mcg_out_bits {
7030         u8         status[0x8];
7031         u8         reserved_at_8[0x18];
7032
7033         u8         syndrome[0x20];
7034
7035         u8         reserved_at_40[0x40];
7036 };
7037
7038 struct mlx5_ifc_detach_from_mcg_in_bits {
7039         u8         opcode[0x10];
7040         u8         uid[0x10];
7041
7042         u8         reserved_at_20[0x10];
7043         u8         op_mod[0x10];
7044
7045         u8         reserved_at_40[0x8];
7046         u8         qpn[0x18];
7047
7048         u8         reserved_at_60[0x20];
7049
7050         u8         multicast_gid[16][0x8];
7051 };
7052
7053 struct mlx5_ifc_destroy_xrq_out_bits {
7054         u8         status[0x8];
7055         u8         reserved_at_8[0x18];
7056
7057         u8         syndrome[0x20];
7058
7059         u8         reserved_at_40[0x40];
7060 };
7061
7062 struct mlx5_ifc_destroy_xrq_in_bits {
7063         u8         opcode[0x10];
7064         u8         uid[0x10];
7065
7066         u8         reserved_at_20[0x10];
7067         u8         op_mod[0x10];
7068
7069         u8         reserved_at_40[0x8];
7070         u8         xrqn[0x18];
7071
7072         u8         reserved_at_60[0x20];
7073 };
7074
7075 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7076         u8         status[0x8];
7077         u8         reserved_at_8[0x18];
7078
7079         u8         syndrome[0x20];
7080
7081         u8         reserved_at_40[0x40];
7082 };
7083
7084 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7085         u8         opcode[0x10];
7086         u8         uid[0x10];
7087
7088         u8         reserved_at_20[0x10];
7089         u8         op_mod[0x10];
7090
7091         u8         reserved_at_40[0x8];
7092         u8         xrc_srqn[0x18];
7093
7094         u8         reserved_at_60[0x20];
7095 };
7096
7097 struct mlx5_ifc_destroy_tis_out_bits {
7098         u8         status[0x8];
7099         u8         reserved_at_8[0x18];
7100
7101         u8         syndrome[0x20];
7102
7103         u8         reserved_at_40[0x40];
7104 };
7105
7106 struct mlx5_ifc_destroy_tis_in_bits {
7107         u8         opcode[0x10];
7108         u8         uid[0x10];
7109
7110         u8         reserved_at_20[0x10];
7111         u8         op_mod[0x10];
7112
7113         u8         reserved_at_40[0x8];
7114         u8         tisn[0x18];
7115
7116         u8         reserved_at_60[0x20];
7117 };
7118
7119 struct mlx5_ifc_destroy_tir_out_bits {
7120         u8         status[0x8];
7121         u8         reserved_at_8[0x18];
7122
7123         u8         syndrome[0x20];
7124
7125         u8         reserved_at_40[0x40];
7126 };
7127
7128 struct mlx5_ifc_destroy_tir_in_bits {
7129         u8         opcode[0x10];
7130         u8         uid[0x10];
7131
7132         u8         reserved_at_20[0x10];
7133         u8         op_mod[0x10];
7134
7135         u8         reserved_at_40[0x8];
7136         u8         tirn[0x18];
7137
7138         u8         reserved_at_60[0x20];
7139 };
7140
7141 struct mlx5_ifc_destroy_srq_out_bits {
7142         u8         status[0x8];
7143         u8         reserved_at_8[0x18];
7144
7145         u8         syndrome[0x20];
7146
7147         u8         reserved_at_40[0x40];
7148 };
7149
7150 struct mlx5_ifc_destroy_srq_in_bits {
7151         u8         opcode[0x10];
7152         u8         uid[0x10];
7153
7154         u8         reserved_at_20[0x10];
7155         u8         op_mod[0x10];
7156
7157         u8         reserved_at_40[0x8];
7158         u8         srqn[0x18];
7159
7160         u8         reserved_at_60[0x20];
7161 };
7162
7163 struct mlx5_ifc_destroy_sq_out_bits {
7164         u8         status[0x8];
7165         u8         reserved_at_8[0x18];
7166
7167         u8         syndrome[0x20];
7168
7169         u8         reserved_at_40[0x40];
7170 };
7171
7172 struct mlx5_ifc_destroy_sq_in_bits {
7173         u8         opcode[0x10];
7174         u8         uid[0x10];
7175
7176         u8         reserved_at_20[0x10];
7177         u8         op_mod[0x10];
7178
7179         u8         reserved_at_40[0x8];
7180         u8         sqn[0x18];
7181
7182         u8         reserved_at_60[0x20];
7183 };
7184
7185 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7186         u8         status[0x8];
7187         u8         reserved_at_8[0x18];
7188
7189         u8         syndrome[0x20];
7190
7191         u8         reserved_at_40[0x1c0];
7192 };
7193
7194 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7195         u8         opcode[0x10];
7196         u8         reserved_at_10[0x10];
7197
7198         u8         reserved_at_20[0x10];
7199         u8         op_mod[0x10];
7200
7201         u8         scheduling_hierarchy[0x8];
7202         u8         reserved_at_48[0x18];
7203
7204         u8         scheduling_element_id[0x20];
7205
7206         u8         reserved_at_80[0x180];
7207 };
7208
7209 struct mlx5_ifc_destroy_rqt_out_bits {
7210         u8         status[0x8];
7211         u8         reserved_at_8[0x18];
7212
7213         u8         syndrome[0x20];
7214
7215         u8         reserved_at_40[0x40];
7216 };
7217
7218 struct mlx5_ifc_destroy_rqt_in_bits {
7219         u8         opcode[0x10];
7220         u8         uid[0x10];
7221
7222         u8         reserved_at_20[0x10];
7223         u8         op_mod[0x10];
7224
7225         u8         reserved_at_40[0x8];
7226         u8         rqtn[0x18];
7227
7228         u8         reserved_at_60[0x20];
7229 };
7230
7231 struct mlx5_ifc_destroy_rq_out_bits {
7232         u8         status[0x8];
7233         u8         reserved_at_8[0x18];
7234
7235         u8         syndrome[0x20];
7236
7237         u8         reserved_at_40[0x40];
7238 };
7239
7240 struct mlx5_ifc_destroy_rq_in_bits {
7241         u8         opcode[0x10];
7242         u8         uid[0x10];
7243
7244         u8         reserved_at_20[0x10];
7245         u8         op_mod[0x10];
7246
7247         u8         reserved_at_40[0x8];
7248         u8         rqn[0x18];
7249
7250         u8         reserved_at_60[0x20];
7251 };
7252
7253 struct mlx5_ifc_set_delay_drop_params_in_bits {
7254         u8         opcode[0x10];
7255         u8         reserved_at_10[0x10];
7256
7257         u8         reserved_at_20[0x10];
7258         u8         op_mod[0x10];
7259
7260         u8         reserved_at_40[0x20];
7261
7262         u8         reserved_at_60[0x10];
7263         u8         delay_drop_timeout[0x10];
7264 };
7265
7266 struct mlx5_ifc_set_delay_drop_params_out_bits {
7267         u8         status[0x8];
7268         u8         reserved_at_8[0x18];
7269
7270         u8         syndrome[0x20];
7271
7272         u8         reserved_at_40[0x40];
7273 };
7274
7275 struct mlx5_ifc_destroy_rmp_out_bits {
7276         u8         status[0x8];
7277         u8         reserved_at_8[0x18];
7278
7279         u8         syndrome[0x20];
7280
7281         u8         reserved_at_40[0x40];
7282 };
7283
7284 struct mlx5_ifc_destroy_rmp_in_bits {
7285         u8         opcode[0x10];
7286         u8         uid[0x10];
7287
7288         u8         reserved_at_20[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         reserved_at_40[0x8];
7292         u8         rmpn[0x18];
7293
7294         u8         reserved_at_60[0x20];
7295 };
7296
7297 struct mlx5_ifc_destroy_qp_out_bits {
7298         u8         status[0x8];
7299         u8         reserved_at_8[0x18];
7300
7301         u8         syndrome[0x20];
7302
7303         u8         reserved_at_40[0x40];
7304 };
7305
7306 struct mlx5_ifc_destroy_qp_in_bits {
7307         u8         opcode[0x10];
7308         u8         uid[0x10];
7309
7310         u8         reserved_at_20[0x10];
7311         u8         op_mod[0x10];
7312
7313         u8         reserved_at_40[0x8];
7314         u8         qpn[0x18];
7315
7316         u8         reserved_at_60[0x20];
7317 };
7318
7319 struct mlx5_ifc_destroy_psv_out_bits {
7320         u8         status[0x8];
7321         u8         reserved_at_8[0x18];
7322
7323         u8         syndrome[0x20];
7324
7325         u8         reserved_at_40[0x40];
7326 };
7327
7328 struct mlx5_ifc_destroy_psv_in_bits {
7329         u8         opcode[0x10];
7330         u8         reserved_at_10[0x10];
7331
7332         u8         reserved_at_20[0x10];
7333         u8         op_mod[0x10];
7334
7335         u8         reserved_at_40[0x8];
7336         u8         psvn[0x18];
7337
7338         u8         reserved_at_60[0x20];
7339 };
7340
7341 struct mlx5_ifc_destroy_mkey_out_bits {
7342         u8         status[0x8];
7343         u8         reserved_at_8[0x18];
7344
7345         u8         syndrome[0x20];
7346
7347         u8         reserved_at_40[0x40];
7348 };
7349
7350 struct mlx5_ifc_destroy_mkey_in_bits {
7351         u8         opcode[0x10];
7352         u8         uid[0x10];
7353
7354         u8         reserved_at_20[0x10];
7355         u8         op_mod[0x10];
7356
7357         u8         reserved_at_40[0x8];
7358         u8         mkey_index[0x18];
7359
7360         u8         reserved_at_60[0x20];
7361 };
7362
7363 struct mlx5_ifc_destroy_flow_table_out_bits {
7364         u8         status[0x8];
7365         u8         reserved_at_8[0x18];
7366
7367         u8         syndrome[0x20];
7368
7369         u8         reserved_at_40[0x40];
7370 };
7371
7372 struct mlx5_ifc_destroy_flow_table_in_bits {
7373         u8         opcode[0x10];
7374         u8         reserved_at_10[0x10];
7375
7376         u8         reserved_at_20[0x10];
7377         u8         op_mod[0x10];
7378
7379         u8         other_vport[0x1];
7380         u8         reserved_at_41[0xf];
7381         u8         vport_number[0x10];
7382
7383         u8         reserved_at_60[0x20];
7384
7385         u8         table_type[0x8];
7386         u8         reserved_at_88[0x18];
7387
7388         u8         reserved_at_a0[0x8];
7389         u8         table_id[0x18];
7390
7391         u8         reserved_at_c0[0x140];
7392 };
7393
7394 struct mlx5_ifc_destroy_flow_group_out_bits {
7395         u8         status[0x8];
7396         u8         reserved_at_8[0x18];
7397
7398         u8         syndrome[0x20];
7399
7400         u8         reserved_at_40[0x40];
7401 };
7402
7403 struct mlx5_ifc_destroy_flow_group_in_bits {
7404         u8         opcode[0x10];
7405         u8         reserved_at_10[0x10];
7406
7407         u8         reserved_at_20[0x10];
7408         u8         op_mod[0x10];
7409
7410         u8         other_vport[0x1];
7411         u8         reserved_at_41[0xf];
7412         u8         vport_number[0x10];
7413
7414         u8         reserved_at_60[0x20];
7415
7416         u8         table_type[0x8];
7417         u8         reserved_at_88[0x18];
7418
7419         u8         reserved_at_a0[0x8];
7420         u8         table_id[0x18];
7421
7422         u8         group_id[0x20];
7423
7424         u8         reserved_at_e0[0x120];
7425 };
7426
7427 struct mlx5_ifc_destroy_eq_out_bits {
7428         u8         status[0x8];
7429         u8         reserved_at_8[0x18];
7430
7431         u8         syndrome[0x20];
7432
7433         u8         reserved_at_40[0x40];
7434 };
7435
7436 struct mlx5_ifc_destroy_eq_in_bits {
7437         u8         opcode[0x10];
7438         u8         reserved_at_10[0x10];
7439
7440         u8         reserved_at_20[0x10];
7441         u8         op_mod[0x10];
7442
7443         u8         reserved_at_40[0x18];
7444         u8         eq_number[0x8];
7445
7446         u8         reserved_at_60[0x20];
7447 };
7448
7449 struct mlx5_ifc_destroy_dct_out_bits {
7450         u8         status[0x8];
7451         u8         reserved_at_8[0x18];
7452
7453         u8         syndrome[0x20];
7454
7455         u8         reserved_at_40[0x40];
7456 };
7457
7458 struct mlx5_ifc_destroy_dct_in_bits {
7459         u8         opcode[0x10];
7460         u8         uid[0x10];
7461
7462         u8         reserved_at_20[0x10];
7463         u8         op_mod[0x10];
7464
7465         u8         reserved_at_40[0x8];
7466         u8         dctn[0x18];
7467
7468         u8         reserved_at_60[0x20];
7469 };
7470
7471 struct mlx5_ifc_destroy_cq_out_bits {
7472         u8         status[0x8];
7473         u8         reserved_at_8[0x18];
7474
7475         u8         syndrome[0x20];
7476
7477         u8         reserved_at_40[0x40];
7478 };
7479
7480 struct mlx5_ifc_destroy_cq_in_bits {
7481         u8         opcode[0x10];
7482         u8         uid[0x10];
7483
7484         u8         reserved_at_20[0x10];
7485         u8         op_mod[0x10];
7486
7487         u8         reserved_at_40[0x8];
7488         u8         cqn[0x18];
7489
7490         u8         reserved_at_60[0x20];
7491 };
7492
7493 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7494         u8         status[0x8];
7495         u8         reserved_at_8[0x18];
7496
7497         u8         syndrome[0x20];
7498
7499         u8         reserved_at_40[0x40];
7500 };
7501
7502 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7503         u8         opcode[0x10];
7504         u8         reserved_at_10[0x10];
7505
7506         u8         reserved_at_20[0x10];
7507         u8         op_mod[0x10];
7508
7509         u8         reserved_at_40[0x20];
7510
7511         u8         reserved_at_60[0x10];
7512         u8         vxlan_udp_port[0x10];
7513 };
7514
7515 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7516         u8         status[0x8];
7517         u8         reserved_at_8[0x18];
7518
7519         u8         syndrome[0x20];
7520
7521         u8         reserved_at_40[0x40];
7522 };
7523
7524 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7525         u8         opcode[0x10];
7526         u8         reserved_at_10[0x10];
7527
7528         u8         reserved_at_20[0x10];
7529         u8         op_mod[0x10];
7530
7531         u8         reserved_at_40[0x60];
7532
7533         u8         reserved_at_a0[0x8];
7534         u8         table_index[0x18];
7535
7536         u8         reserved_at_c0[0x140];
7537 };
7538
7539 struct mlx5_ifc_delete_fte_out_bits {
7540         u8         status[0x8];
7541         u8         reserved_at_8[0x18];
7542
7543         u8         syndrome[0x20];
7544
7545         u8         reserved_at_40[0x40];
7546 };
7547
7548 struct mlx5_ifc_delete_fte_in_bits {
7549         u8         opcode[0x10];
7550         u8         reserved_at_10[0x10];
7551
7552         u8         reserved_at_20[0x10];
7553         u8         op_mod[0x10];
7554
7555         u8         other_vport[0x1];
7556         u8         reserved_at_41[0xf];
7557         u8         vport_number[0x10];
7558
7559         u8         reserved_at_60[0x20];
7560
7561         u8         table_type[0x8];
7562         u8         reserved_at_88[0x18];
7563
7564         u8         reserved_at_a0[0x8];
7565         u8         table_id[0x18];
7566
7567         u8         reserved_at_c0[0x40];
7568
7569         u8         flow_index[0x20];
7570
7571         u8         reserved_at_120[0xe0];
7572 };
7573
7574 struct mlx5_ifc_dealloc_xrcd_out_bits {
7575         u8         status[0x8];
7576         u8         reserved_at_8[0x18];
7577
7578         u8         syndrome[0x20];
7579
7580         u8         reserved_at_40[0x40];
7581 };
7582
7583 struct mlx5_ifc_dealloc_xrcd_in_bits {
7584         u8         opcode[0x10];
7585         u8         uid[0x10];
7586
7587         u8         reserved_at_20[0x10];
7588         u8         op_mod[0x10];
7589
7590         u8         reserved_at_40[0x8];
7591         u8         xrcd[0x18];
7592
7593         u8         reserved_at_60[0x20];
7594 };
7595
7596 struct mlx5_ifc_dealloc_uar_out_bits {
7597         u8         status[0x8];
7598         u8         reserved_at_8[0x18];
7599
7600         u8         syndrome[0x20];
7601
7602         u8         reserved_at_40[0x40];
7603 };
7604
7605 struct mlx5_ifc_dealloc_uar_in_bits {
7606         u8         opcode[0x10];
7607         u8         reserved_at_10[0x10];
7608
7609         u8         reserved_at_20[0x10];
7610         u8         op_mod[0x10];
7611
7612         u8         reserved_at_40[0x8];
7613         u8         uar[0x18];
7614
7615         u8         reserved_at_60[0x20];
7616 };
7617
7618 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7619         u8         status[0x8];
7620         u8         reserved_at_8[0x18];
7621
7622         u8         syndrome[0x20];
7623
7624         u8         reserved_at_40[0x40];
7625 };
7626
7627 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7628         u8         opcode[0x10];
7629         u8         uid[0x10];
7630
7631         u8         reserved_at_20[0x10];
7632         u8         op_mod[0x10];
7633
7634         u8         reserved_at_40[0x8];
7635         u8         transport_domain[0x18];
7636
7637         u8         reserved_at_60[0x20];
7638 };
7639
7640 struct mlx5_ifc_dealloc_q_counter_out_bits {
7641         u8         status[0x8];
7642         u8         reserved_at_8[0x18];
7643
7644         u8         syndrome[0x20];
7645
7646         u8         reserved_at_40[0x40];
7647 };
7648
7649 struct mlx5_ifc_dealloc_q_counter_in_bits {
7650         u8         opcode[0x10];
7651         u8         reserved_at_10[0x10];
7652
7653         u8         reserved_at_20[0x10];
7654         u8         op_mod[0x10];
7655
7656         u8         reserved_at_40[0x18];
7657         u8         counter_set_id[0x8];
7658
7659         u8         reserved_at_60[0x20];
7660 };
7661
7662 struct mlx5_ifc_dealloc_pd_out_bits {
7663         u8         status[0x8];
7664         u8         reserved_at_8[0x18];
7665
7666         u8         syndrome[0x20];
7667
7668         u8         reserved_at_40[0x40];
7669 };
7670
7671 struct mlx5_ifc_dealloc_pd_in_bits {
7672         u8         opcode[0x10];
7673         u8         uid[0x10];
7674
7675         u8         reserved_at_20[0x10];
7676         u8         op_mod[0x10];
7677
7678         u8         reserved_at_40[0x8];
7679         u8         pd[0x18];
7680
7681         u8         reserved_at_60[0x20];
7682 };
7683
7684 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7685         u8         status[0x8];
7686         u8         reserved_at_8[0x18];
7687
7688         u8         syndrome[0x20];
7689
7690         u8         reserved_at_40[0x40];
7691 };
7692
7693 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7694         u8         opcode[0x10];
7695         u8         reserved_at_10[0x10];
7696
7697         u8         reserved_at_20[0x10];
7698         u8         op_mod[0x10];
7699
7700         u8         flow_counter_id[0x20];
7701
7702         u8         reserved_at_60[0x20];
7703 };
7704
7705 struct mlx5_ifc_create_xrq_out_bits {
7706         u8         status[0x8];
7707         u8         reserved_at_8[0x18];
7708
7709         u8         syndrome[0x20];
7710
7711         u8         reserved_at_40[0x8];
7712         u8         xrqn[0x18];
7713
7714         u8         reserved_at_60[0x20];
7715 };
7716
7717 struct mlx5_ifc_create_xrq_in_bits {
7718         u8         opcode[0x10];
7719         u8         uid[0x10];
7720
7721         u8         reserved_at_20[0x10];
7722         u8         op_mod[0x10];
7723
7724         u8         reserved_at_40[0x40];
7725
7726         struct mlx5_ifc_xrqc_bits xrq_context;
7727 };
7728
7729 struct mlx5_ifc_create_xrc_srq_out_bits {
7730         u8         status[0x8];
7731         u8         reserved_at_8[0x18];
7732
7733         u8         syndrome[0x20];
7734
7735         u8         reserved_at_40[0x8];
7736         u8         xrc_srqn[0x18];
7737
7738         u8         reserved_at_60[0x20];
7739 };
7740
7741 struct mlx5_ifc_create_xrc_srq_in_bits {
7742         u8         opcode[0x10];
7743         u8         uid[0x10];
7744
7745         u8         reserved_at_20[0x10];
7746         u8         op_mod[0x10];
7747
7748         u8         reserved_at_40[0x40];
7749
7750         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7751
7752         u8         reserved_at_280[0x60];
7753
7754         u8         xrc_srq_umem_valid[0x1];
7755         u8         reserved_at_2e1[0x1f];
7756
7757         u8         reserved_at_300[0x580];
7758
7759         u8         pas[][0x40];
7760 };
7761
7762 struct mlx5_ifc_create_tis_out_bits {
7763         u8         status[0x8];
7764         u8         reserved_at_8[0x18];
7765
7766         u8         syndrome[0x20];
7767
7768         u8         reserved_at_40[0x8];
7769         u8         tisn[0x18];
7770
7771         u8         reserved_at_60[0x20];
7772 };
7773
7774 struct mlx5_ifc_create_tis_in_bits {
7775         u8         opcode[0x10];
7776         u8         uid[0x10];
7777
7778         u8         reserved_at_20[0x10];
7779         u8         op_mod[0x10];
7780
7781         u8         reserved_at_40[0xc0];
7782
7783         struct mlx5_ifc_tisc_bits ctx;
7784 };
7785
7786 struct mlx5_ifc_create_tir_out_bits {
7787         u8         status[0x8];
7788         u8         icm_address_63_40[0x18];
7789
7790         u8         syndrome[0x20];
7791
7792         u8         icm_address_39_32[0x8];
7793         u8         tirn[0x18];
7794
7795         u8         icm_address_31_0[0x20];
7796 };
7797
7798 struct mlx5_ifc_create_tir_in_bits {
7799         u8         opcode[0x10];
7800         u8         uid[0x10];
7801
7802         u8         reserved_at_20[0x10];
7803         u8         op_mod[0x10];
7804
7805         u8         reserved_at_40[0xc0];
7806
7807         struct mlx5_ifc_tirc_bits ctx;
7808 };
7809
7810 struct mlx5_ifc_create_srq_out_bits {
7811         u8         status[0x8];
7812         u8         reserved_at_8[0x18];
7813
7814         u8         syndrome[0x20];
7815
7816         u8         reserved_at_40[0x8];
7817         u8         srqn[0x18];
7818
7819         u8         reserved_at_60[0x20];
7820 };
7821
7822 struct mlx5_ifc_create_srq_in_bits {
7823         u8         opcode[0x10];
7824         u8         uid[0x10];
7825
7826         u8         reserved_at_20[0x10];
7827         u8         op_mod[0x10];
7828
7829         u8         reserved_at_40[0x40];
7830
7831         struct mlx5_ifc_srqc_bits srq_context_entry;
7832
7833         u8         reserved_at_280[0x600];
7834
7835         u8         pas[][0x40];
7836 };
7837
7838 struct mlx5_ifc_create_sq_out_bits {
7839         u8         status[0x8];
7840         u8         reserved_at_8[0x18];
7841
7842         u8         syndrome[0x20];
7843
7844         u8         reserved_at_40[0x8];
7845         u8         sqn[0x18];
7846
7847         u8         reserved_at_60[0x20];
7848 };
7849
7850 struct mlx5_ifc_create_sq_in_bits {
7851         u8         opcode[0x10];
7852         u8         uid[0x10];
7853
7854         u8         reserved_at_20[0x10];
7855         u8         op_mod[0x10];
7856
7857         u8         reserved_at_40[0xc0];
7858
7859         struct mlx5_ifc_sqc_bits ctx;
7860 };
7861
7862 struct mlx5_ifc_create_scheduling_element_out_bits {
7863         u8         status[0x8];
7864         u8         reserved_at_8[0x18];
7865
7866         u8         syndrome[0x20];
7867
7868         u8         reserved_at_40[0x40];
7869
7870         u8         scheduling_element_id[0x20];
7871
7872         u8         reserved_at_a0[0x160];
7873 };
7874
7875 struct mlx5_ifc_create_scheduling_element_in_bits {
7876         u8         opcode[0x10];
7877         u8         reserved_at_10[0x10];
7878
7879         u8         reserved_at_20[0x10];
7880         u8         op_mod[0x10];
7881
7882         u8         scheduling_hierarchy[0x8];
7883         u8         reserved_at_48[0x18];
7884
7885         u8         reserved_at_60[0xa0];
7886
7887         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7888
7889         u8         reserved_at_300[0x100];
7890 };
7891
7892 struct mlx5_ifc_create_rqt_out_bits {
7893         u8         status[0x8];
7894         u8         reserved_at_8[0x18];
7895
7896         u8         syndrome[0x20];
7897
7898         u8         reserved_at_40[0x8];
7899         u8         rqtn[0x18];
7900
7901         u8         reserved_at_60[0x20];
7902 };
7903
7904 struct mlx5_ifc_create_rqt_in_bits {
7905         u8         opcode[0x10];
7906         u8         uid[0x10];
7907
7908         u8         reserved_at_20[0x10];
7909         u8         op_mod[0x10];
7910
7911         u8         reserved_at_40[0xc0];
7912
7913         struct mlx5_ifc_rqtc_bits rqt_context;
7914 };
7915
7916 struct mlx5_ifc_create_rq_out_bits {
7917         u8         status[0x8];
7918         u8         reserved_at_8[0x18];
7919
7920         u8         syndrome[0x20];
7921
7922         u8         reserved_at_40[0x8];
7923         u8         rqn[0x18];
7924
7925         u8         reserved_at_60[0x20];
7926 };
7927
7928 struct mlx5_ifc_create_rq_in_bits {
7929         u8         opcode[0x10];
7930         u8         uid[0x10];
7931
7932         u8         reserved_at_20[0x10];
7933         u8         op_mod[0x10];
7934
7935         u8         reserved_at_40[0xc0];
7936
7937         struct mlx5_ifc_rqc_bits ctx;
7938 };
7939
7940 struct mlx5_ifc_create_rmp_out_bits {
7941         u8         status[0x8];
7942         u8         reserved_at_8[0x18];
7943
7944         u8         syndrome[0x20];
7945
7946         u8         reserved_at_40[0x8];
7947         u8         rmpn[0x18];
7948
7949         u8         reserved_at_60[0x20];
7950 };
7951
7952 struct mlx5_ifc_create_rmp_in_bits {
7953         u8         opcode[0x10];
7954         u8         uid[0x10];
7955
7956         u8         reserved_at_20[0x10];
7957         u8         op_mod[0x10];
7958
7959         u8         reserved_at_40[0xc0];
7960
7961         struct mlx5_ifc_rmpc_bits ctx;
7962 };
7963
7964 struct mlx5_ifc_create_qp_out_bits {
7965         u8         status[0x8];
7966         u8         reserved_at_8[0x18];
7967
7968         u8         syndrome[0x20];
7969
7970         u8         reserved_at_40[0x8];
7971         u8         qpn[0x18];
7972
7973         u8         ece[0x20];
7974 };
7975
7976 struct mlx5_ifc_create_qp_in_bits {
7977         u8         opcode[0x10];
7978         u8         uid[0x10];
7979
7980         u8         reserved_at_20[0x10];
7981         u8         op_mod[0x10];
7982
7983         u8         reserved_at_40[0x8];
7984         u8         input_qpn[0x18];
7985
7986         u8         reserved_at_60[0x20];
7987         u8         opt_param_mask[0x20];
7988
7989         u8         ece[0x20];
7990
7991         struct mlx5_ifc_qpc_bits qpc;
7992
7993         u8         reserved_at_800[0x60];
7994
7995         u8         wq_umem_valid[0x1];
7996         u8         reserved_at_861[0x1f];
7997
7998         u8         pas[][0x40];
7999 };
8000
8001 struct mlx5_ifc_create_psv_out_bits {
8002         u8         status[0x8];
8003         u8         reserved_at_8[0x18];
8004
8005         u8         syndrome[0x20];
8006
8007         u8         reserved_at_40[0x40];
8008
8009         u8         reserved_at_80[0x8];
8010         u8         psv0_index[0x18];
8011
8012         u8         reserved_at_a0[0x8];
8013         u8         psv1_index[0x18];
8014
8015         u8         reserved_at_c0[0x8];
8016         u8         psv2_index[0x18];
8017
8018         u8         reserved_at_e0[0x8];
8019         u8         psv3_index[0x18];
8020 };
8021
8022 struct mlx5_ifc_create_psv_in_bits {
8023         u8         opcode[0x10];
8024         u8         reserved_at_10[0x10];
8025
8026         u8         reserved_at_20[0x10];
8027         u8         op_mod[0x10];
8028
8029         u8         num_psv[0x4];
8030         u8         reserved_at_44[0x4];
8031         u8         pd[0x18];
8032
8033         u8         reserved_at_60[0x20];
8034 };
8035
8036 struct mlx5_ifc_create_mkey_out_bits {
8037         u8         status[0x8];
8038         u8         reserved_at_8[0x18];
8039
8040         u8         syndrome[0x20];
8041
8042         u8         reserved_at_40[0x8];
8043         u8         mkey_index[0x18];
8044
8045         u8         reserved_at_60[0x20];
8046 };
8047
8048 struct mlx5_ifc_create_mkey_in_bits {
8049         u8         opcode[0x10];
8050         u8         uid[0x10];
8051
8052         u8         reserved_at_20[0x10];
8053         u8         op_mod[0x10];
8054
8055         u8         reserved_at_40[0x20];
8056
8057         u8         pg_access[0x1];
8058         u8         mkey_umem_valid[0x1];
8059         u8         reserved_at_62[0x1e];
8060
8061         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8062
8063         u8         reserved_at_280[0x80];
8064
8065         u8         translations_octword_actual_size[0x20];
8066
8067         u8         reserved_at_320[0x560];
8068
8069         u8         klm_pas_mtt[][0x20];
8070 };
8071
8072 enum {
8073         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8074         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8075         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8076         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8077         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8078         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8079         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8080 };
8081
8082 struct mlx5_ifc_create_flow_table_out_bits {
8083         u8         status[0x8];
8084         u8         icm_address_63_40[0x18];
8085
8086         u8         syndrome[0x20];
8087
8088         u8         icm_address_39_32[0x8];
8089         u8         table_id[0x18];
8090
8091         u8         icm_address_31_0[0x20];
8092 };
8093
8094 struct mlx5_ifc_create_flow_table_in_bits {
8095         u8         opcode[0x10];
8096         u8         reserved_at_10[0x10];
8097
8098         u8         reserved_at_20[0x10];
8099         u8         op_mod[0x10];
8100
8101         u8         other_vport[0x1];
8102         u8         reserved_at_41[0xf];
8103         u8         vport_number[0x10];
8104
8105         u8         reserved_at_60[0x20];
8106
8107         u8         table_type[0x8];
8108         u8         reserved_at_88[0x18];
8109
8110         u8         reserved_at_a0[0x20];
8111
8112         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8113 };
8114
8115 struct mlx5_ifc_create_flow_group_out_bits {
8116         u8         status[0x8];
8117         u8         reserved_at_8[0x18];
8118
8119         u8         syndrome[0x20];
8120
8121         u8         reserved_at_40[0x8];
8122         u8         group_id[0x18];
8123
8124         u8         reserved_at_60[0x20];
8125 };
8126
8127 enum {
8128         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8129         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8130         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8131         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8132 };
8133
8134 struct mlx5_ifc_create_flow_group_in_bits {
8135         u8         opcode[0x10];
8136         u8         reserved_at_10[0x10];
8137
8138         u8         reserved_at_20[0x10];
8139         u8         op_mod[0x10];
8140
8141         u8         other_vport[0x1];
8142         u8         reserved_at_41[0xf];
8143         u8         vport_number[0x10];
8144
8145         u8         reserved_at_60[0x20];
8146
8147         u8         table_type[0x8];
8148         u8         reserved_at_88[0x18];
8149
8150         u8         reserved_at_a0[0x8];
8151         u8         table_id[0x18];
8152
8153         u8         source_eswitch_owner_vhca_id_valid[0x1];
8154
8155         u8         reserved_at_c1[0x1f];
8156
8157         u8         start_flow_index[0x20];
8158
8159         u8         reserved_at_100[0x20];
8160
8161         u8         end_flow_index[0x20];
8162
8163         u8         reserved_at_140[0xa0];
8164
8165         u8         reserved_at_1e0[0x18];
8166         u8         match_criteria_enable[0x8];
8167
8168         struct mlx5_ifc_fte_match_param_bits match_criteria;
8169
8170         u8         reserved_at_1200[0xe00];
8171 };
8172
8173 struct mlx5_ifc_create_eq_out_bits {
8174         u8         status[0x8];
8175         u8         reserved_at_8[0x18];
8176
8177         u8         syndrome[0x20];
8178
8179         u8         reserved_at_40[0x18];
8180         u8         eq_number[0x8];
8181
8182         u8         reserved_at_60[0x20];
8183 };
8184
8185 struct mlx5_ifc_create_eq_in_bits {
8186         u8         opcode[0x10];
8187         u8         uid[0x10];
8188
8189         u8         reserved_at_20[0x10];
8190         u8         op_mod[0x10];
8191
8192         u8         reserved_at_40[0x40];
8193
8194         struct mlx5_ifc_eqc_bits eq_context_entry;
8195
8196         u8         reserved_at_280[0x40];
8197
8198         u8         event_bitmask[4][0x40];
8199
8200         u8         reserved_at_3c0[0x4c0];
8201
8202         u8         pas[][0x40];
8203 };
8204
8205 struct mlx5_ifc_create_dct_out_bits {
8206         u8         status[0x8];
8207         u8         reserved_at_8[0x18];
8208
8209         u8         syndrome[0x20];
8210
8211         u8         reserved_at_40[0x8];
8212         u8         dctn[0x18];
8213
8214         u8         ece[0x20];
8215 };
8216
8217 struct mlx5_ifc_create_dct_in_bits {
8218         u8         opcode[0x10];
8219         u8         uid[0x10];
8220
8221         u8         reserved_at_20[0x10];
8222         u8         op_mod[0x10];
8223
8224         u8         reserved_at_40[0x40];
8225
8226         struct mlx5_ifc_dctc_bits dct_context_entry;
8227
8228         u8         reserved_at_280[0x180];
8229 };
8230
8231 struct mlx5_ifc_create_cq_out_bits {
8232         u8         status[0x8];
8233         u8         reserved_at_8[0x18];
8234
8235         u8         syndrome[0x20];
8236
8237         u8         reserved_at_40[0x8];
8238         u8         cqn[0x18];
8239
8240         u8         reserved_at_60[0x20];
8241 };
8242
8243 struct mlx5_ifc_create_cq_in_bits {
8244         u8         opcode[0x10];
8245         u8         uid[0x10];
8246
8247         u8         reserved_at_20[0x10];
8248         u8         op_mod[0x10];
8249
8250         u8         reserved_at_40[0x40];
8251
8252         struct mlx5_ifc_cqc_bits cq_context;
8253
8254         u8         reserved_at_280[0x60];
8255
8256         u8         cq_umem_valid[0x1];
8257         u8         reserved_at_2e1[0x59f];
8258
8259         u8         pas[][0x40];
8260 };
8261
8262 struct mlx5_ifc_config_int_moderation_out_bits {
8263         u8         status[0x8];
8264         u8         reserved_at_8[0x18];
8265
8266         u8         syndrome[0x20];
8267
8268         u8         reserved_at_40[0x4];
8269         u8         min_delay[0xc];
8270         u8         int_vector[0x10];
8271
8272         u8         reserved_at_60[0x20];
8273 };
8274
8275 enum {
8276         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8277         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8278 };
8279
8280 struct mlx5_ifc_config_int_moderation_in_bits {
8281         u8         opcode[0x10];
8282         u8         reserved_at_10[0x10];
8283
8284         u8         reserved_at_20[0x10];
8285         u8         op_mod[0x10];
8286
8287         u8         reserved_at_40[0x4];
8288         u8         min_delay[0xc];
8289         u8         int_vector[0x10];
8290
8291         u8         reserved_at_60[0x20];
8292 };
8293
8294 struct mlx5_ifc_attach_to_mcg_out_bits {
8295         u8         status[0x8];
8296         u8         reserved_at_8[0x18];
8297
8298         u8         syndrome[0x20];
8299
8300         u8         reserved_at_40[0x40];
8301 };
8302
8303 struct mlx5_ifc_attach_to_mcg_in_bits {
8304         u8         opcode[0x10];
8305         u8         uid[0x10];
8306
8307         u8         reserved_at_20[0x10];
8308         u8         op_mod[0x10];
8309
8310         u8         reserved_at_40[0x8];
8311         u8         qpn[0x18];
8312
8313         u8         reserved_at_60[0x20];
8314
8315         u8         multicast_gid[16][0x8];
8316 };
8317
8318 struct mlx5_ifc_arm_xrq_out_bits {
8319         u8         status[0x8];
8320         u8         reserved_at_8[0x18];
8321
8322         u8         syndrome[0x20];
8323
8324         u8         reserved_at_40[0x40];
8325 };
8326
8327 struct mlx5_ifc_arm_xrq_in_bits {
8328         u8         opcode[0x10];
8329         u8         reserved_at_10[0x10];
8330
8331         u8         reserved_at_20[0x10];
8332         u8         op_mod[0x10];
8333
8334         u8         reserved_at_40[0x8];
8335         u8         xrqn[0x18];
8336
8337         u8         reserved_at_60[0x10];
8338         u8         lwm[0x10];
8339 };
8340
8341 struct mlx5_ifc_arm_xrc_srq_out_bits {
8342         u8         status[0x8];
8343         u8         reserved_at_8[0x18];
8344
8345         u8         syndrome[0x20];
8346
8347         u8         reserved_at_40[0x40];
8348 };
8349
8350 enum {
8351         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8352 };
8353
8354 struct mlx5_ifc_arm_xrc_srq_in_bits {
8355         u8         opcode[0x10];
8356         u8         uid[0x10];
8357
8358         u8         reserved_at_20[0x10];
8359         u8         op_mod[0x10];
8360
8361         u8         reserved_at_40[0x8];
8362         u8         xrc_srqn[0x18];
8363
8364         u8         reserved_at_60[0x10];
8365         u8         lwm[0x10];
8366 };
8367
8368 struct mlx5_ifc_arm_rq_out_bits {
8369         u8         status[0x8];
8370         u8         reserved_at_8[0x18];
8371
8372         u8         syndrome[0x20];
8373
8374         u8         reserved_at_40[0x40];
8375 };
8376
8377 enum {
8378         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8379         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8380 };
8381
8382 struct mlx5_ifc_arm_rq_in_bits {
8383         u8         opcode[0x10];
8384         u8         uid[0x10];
8385
8386         u8         reserved_at_20[0x10];
8387         u8         op_mod[0x10];
8388
8389         u8         reserved_at_40[0x8];
8390         u8         srq_number[0x18];
8391
8392         u8         reserved_at_60[0x10];
8393         u8         lwm[0x10];
8394 };
8395
8396 struct mlx5_ifc_arm_dct_out_bits {
8397         u8         status[0x8];
8398         u8         reserved_at_8[0x18];
8399
8400         u8         syndrome[0x20];
8401
8402         u8         reserved_at_40[0x40];
8403 };
8404
8405 struct mlx5_ifc_arm_dct_in_bits {
8406         u8         opcode[0x10];
8407         u8         reserved_at_10[0x10];
8408
8409         u8         reserved_at_20[0x10];
8410         u8         op_mod[0x10];
8411
8412         u8         reserved_at_40[0x8];
8413         u8         dct_number[0x18];
8414
8415         u8         reserved_at_60[0x20];
8416 };
8417
8418 struct mlx5_ifc_alloc_xrcd_out_bits {
8419         u8         status[0x8];
8420         u8         reserved_at_8[0x18];
8421
8422         u8         syndrome[0x20];
8423
8424         u8         reserved_at_40[0x8];
8425         u8         xrcd[0x18];
8426
8427         u8         reserved_at_60[0x20];
8428 };
8429
8430 struct mlx5_ifc_alloc_xrcd_in_bits {
8431         u8         opcode[0x10];
8432         u8         uid[0x10];
8433
8434         u8         reserved_at_20[0x10];
8435         u8         op_mod[0x10];
8436
8437         u8         reserved_at_40[0x40];
8438 };
8439
8440 struct mlx5_ifc_alloc_uar_out_bits {
8441         u8         status[0x8];
8442         u8         reserved_at_8[0x18];
8443
8444         u8         syndrome[0x20];
8445
8446         u8         reserved_at_40[0x8];
8447         u8         uar[0x18];
8448
8449         u8         reserved_at_60[0x20];
8450 };
8451
8452 struct mlx5_ifc_alloc_uar_in_bits {
8453         u8         opcode[0x10];
8454         u8         reserved_at_10[0x10];
8455
8456         u8         reserved_at_20[0x10];
8457         u8         op_mod[0x10];
8458
8459         u8         reserved_at_40[0x40];
8460 };
8461
8462 struct mlx5_ifc_alloc_transport_domain_out_bits {
8463         u8         status[0x8];
8464         u8         reserved_at_8[0x18];
8465
8466         u8         syndrome[0x20];
8467
8468         u8         reserved_at_40[0x8];
8469         u8         transport_domain[0x18];
8470
8471         u8         reserved_at_60[0x20];
8472 };
8473
8474 struct mlx5_ifc_alloc_transport_domain_in_bits {
8475         u8         opcode[0x10];
8476         u8         uid[0x10];
8477
8478         u8         reserved_at_20[0x10];
8479         u8         op_mod[0x10];
8480
8481         u8         reserved_at_40[0x40];
8482 };
8483
8484 struct mlx5_ifc_alloc_q_counter_out_bits {
8485         u8         status[0x8];
8486         u8         reserved_at_8[0x18];
8487
8488         u8         syndrome[0x20];
8489
8490         u8         reserved_at_40[0x18];
8491         u8         counter_set_id[0x8];
8492
8493         u8         reserved_at_60[0x20];
8494 };
8495
8496 struct mlx5_ifc_alloc_q_counter_in_bits {
8497         u8         opcode[0x10];
8498         u8         uid[0x10];
8499
8500         u8         reserved_at_20[0x10];
8501         u8         op_mod[0x10];
8502
8503         u8         reserved_at_40[0x40];
8504 };
8505
8506 struct mlx5_ifc_alloc_pd_out_bits {
8507         u8         status[0x8];
8508         u8         reserved_at_8[0x18];
8509
8510         u8         syndrome[0x20];
8511
8512         u8         reserved_at_40[0x8];
8513         u8         pd[0x18];
8514
8515         u8         reserved_at_60[0x20];
8516 };
8517
8518 struct mlx5_ifc_alloc_pd_in_bits {
8519         u8         opcode[0x10];
8520         u8         uid[0x10];
8521
8522         u8         reserved_at_20[0x10];
8523         u8         op_mod[0x10];
8524
8525         u8         reserved_at_40[0x40];
8526 };
8527
8528 struct mlx5_ifc_alloc_flow_counter_out_bits {
8529         u8         status[0x8];
8530         u8         reserved_at_8[0x18];
8531
8532         u8         syndrome[0x20];
8533
8534         u8         flow_counter_id[0x20];
8535
8536         u8         reserved_at_60[0x20];
8537 };
8538
8539 struct mlx5_ifc_alloc_flow_counter_in_bits {
8540         u8         opcode[0x10];
8541         u8         reserved_at_10[0x10];
8542
8543         u8         reserved_at_20[0x10];
8544         u8         op_mod[0x10];
8545
8546         u8         reserved_at_40[0x38];
8547         u8         flow_counter_bulk[0x8];
8548 };
8549
8550 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8551         u8         status[0x8];
8552         u8         reserved_at_8[0x18];
8553
8554         u8         syndrome[0x20];
8555
8556         u8         reserved_at_40[0x40];
8557 };
8558
8559 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8560         u8         opcode[0x10];
8561         u8         reserved_at_10[0x10];
8562
8563         u8         reserved_at_20[0x10];
8564         u8         op_mod[0x10];
8565
8566         u8         reserved_at_40[0x20];
8567
8568         u8         reserved_at_60[0x10];
8569         u8         vxlan_udp_port[0x10];
8570 };
8571
8572 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8573         u8         status[0x8];
8574         u8         reserved_at_8[0x18];
8575
8576         u8         syndrome[0x20];
8577
8578         u8         reserved_at_40[0x40];
8579 };
8580
8581 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8582         u8         rate_limit[0x20];
8583
8584         u8         burst_upper_bound[0x20];
8585
8586         u8         reserved_at_40[0x10];
8587         u8         typical_packet_size[0x10];
8588
8589         u8         reserved_at_60[0x120];
8590 };
8591
8592 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8593         u8         opcode[0x10];
8594         u8         uid[0x10];
8595
8596         u8         reserved_at_20[0x10];
8597         u8         op_mod[0x10];
8598
8599         u8         reserved_at_40[0x10];
8600         u8         rate_limit_index[0x10];
8601
8602         u8         reserved_at_60[0x20];
8603
8604         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8605 };
8606
8607 struct mlx5_ifc_access_register_out_bits {
8608         u8         status[0x8];
8609         u8         reserved_at_8[0x18];
8610
8611         u8         syndrome[0x20];
8612
8613         u8         reserved_at_40[0x40];
8614
8615         u8         register_data[][0x20];
8616 };
8617
8618 enum {
8619         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8620         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8621 };
8622
8623 struct mlx5_ifc_access_register_in_bits {
8624         u8         opcode[0x10];
8625         u8         reserved_at_10[0x10];
8626
8627         u8         reserved_at_20[0x10];
8628         u8         op_mod[0x10];
8629
8630         u8         reserved_at_40[0x10];
8631         u8         register_id[0x10];
8632
8633         u8         argument[0x20];
8634
8635         u8         register_data[][0x20];
8636 };
8637
8638 struct mlx5_ifc_sltp_reg_bits {
8639         u8         status[0x4];
8640         u8         version[0x4];
8641         u8         local_port[0x8];
8642         u8         pnat[0x2];
8643         u8         reserved_at_12[0x2];
8644         u8         lane[0x4];
8645         u8         reserved_at_18[0x8];
8646
8647         u8         reserved_at_20[0x20];
8648
8649         u8         reserved_at_40[0x7];
8650         u8         polarity[0x1];
8651         u8         ob_tap0[0x8];
8652         u8         ob_tap1[0x8];
8653         u8         ob_tap2[0x8];
8654
8655         u8         reserved_at_60[0xc];
8656         u8         ob_preemp_mode[0x4];
8657         u8         ob_reg[0x8];
8658         u8         ob_bias[0x8];
8659
8660         u8         reserved_at_80[0x20];
8661 };
8662
8663 struct mlx5_ifc_slrg_reg_bits {
8664         u8         status[0x4];
8665         u8         version[0x4];
8666         u8         local_port[0x8];
8667         u8         pnat[0x2];
8668         u8         reserved_at_12[0x2];
8669         u8         lane[0x4];
8670         u8         reserved_at_18[0x8];
8671
8672         u8         time_to_link_up[0x10];
8673         u8         reserved_at_30[0xc];
8674         u8         grade_lane_speed[0x4];
8675
8676         u8         grade_version[0x8];
8677         u8         grade[0x18];
8678
8679         u8         reserved_at_60[0x4];
8680         u8         height_grade_type[0x4];
8681         u8         height_grade[0x18];
8682
8683         u8         height_dz[0x10];
8684         u8         height_dv[0x10];
8685
8686         u8         reserved_at_a0[0x10];
8687         u8         height_sigma[0x10];
8688
8689         u8         reserved_at_c0[0x20];
8690
8691         u8         reserved_at_e0[0x4];
8692         u8         phase_grade_type[0x4];
8693         u8         phase_grade[0x18];
8694
8695         u8         reserved_at_100[0x8];
8696         u8         phase_eo_pos[0x8];
8697         u8         reserved_at_110[0x8];
8698         u8         phase_eo_neg[0x8];
8699
8700         u8         ffe_set_tested[0x10];
8701         u8         test_errors_per_lane[0x10];
8702 };
8703
8704 struct mlx5_ifc_pvlc_reg_bits {
8705         u8         reserved_at_0[0x8];
8706         u8         local_port[0x8];
8707         u8         reserved_at_10[0x10];
8708
8709         u8         reserved_at_20[0x1c];
8710         u8         vl_hw_cap[0x4];
8711
8712         u8         reserved_at_40[0x1c];
8713         u8         vl_admin[0x4];
8714
8715         u8         reserved_at_60[0x1c];
8716         u8         vl_operational[0x4];
8717 };
8718
8719 struct mlx5_ifc_pude_reg_bits {
8720         u8         swid[0x8];
8721         u8         local_port[0x8];
8722         u8         reserved_at_10[0x4];
8723         u8         admin_status[0x4];
8724         u8         reserved_at_18[0x4];
8725         u8         oper_status[0x4];
8726
8727         u8         reserved_at_20[0x60];
8728 };
8729
8730 struct mlx5_ifc_ptys_reg_bits {
8731         u8         reserved_at_0[0x1];
8732         u8         an_disable_admin[0x1];
8733         u8         an_disable_cap[0x1];
8734         u8         reserved_at_3[0x5];
8735         u8         local_port[0x8];
8736         u8         reserved_at_10[0xd];
8737         u8         proto_mask[0x3];
8738
8739         u8         an_status[0x4];
8740         u8         reserved_at_24[0xc];
8741         u8         data_rate_oper[0x10];
8742
8743         u8         ext_eth_proto_capability[0x20];
8744
8745         u8         eth_proto_capability[0x20];
8746
8747         u8         ib_link_width_capability[0x10];
8748         u8         ib_proto_capability[0x10];
8749
8750         u8         ext_eth_proto_admin[0x20];
8751
8752         u8         eth_proto_admin[0x20];
8753
8754         u8         ib_link_width_admin[0x10];
8755         u8         ib_proto_admin[0x10];
8756
8757         u8         ext_eth_proto_oper[0x20];
8758
8759         u8         eth_proto_oper[0x20];
8760
8761         u8         ib_link_width_oper[0x10];
8762         u8         ib_proto_oper[0x10];
8763
8764         u8         reserved_at_160[0x1c];
8765         u8         connector_type[0x4];
8766
8767         u8         eth_proto_lp_advertise[0x20];
8768
8769         u8         reserved_at_1a0[0x60];
8770 };
8771
8772 struct mlx5_ifc_mlcr_reg_bits {
8773         u8         reserved_at_0[0x8];
8774         u8         local_port[0x8];
8775         u8         reserved_at_10[0x20];
8776
8777         u8         beacon_duration[0x10];
8778         u8         reserved_at_40[0x10];
8779
8780         u8         beacon_remain[0x10];
8781 };
8782
8783 struct mlx5_ifc_ptas_reg_bits {
8784         u8         reserved_at_0[0x20];
8785
8786         u8         algorithm_options[0x10];
8787         u8         reserved_at_30[0x4];
8788         u8         repetitions_mode[0x4];
8789         u8         num_of_repetitions[0x8];
8790
8791         u8         grade_version[0x8];
8792         u8         height_grade_type[0x4];
8793         u8         phase_grade_type[0x4];
8794         u8         height_grade_weight[0x8];
8795         u8         phase_grade_weight[0x8];
8796
8797         u8         gisim_measure_bits[0x10];
8798         u8         adaptive_tap_measure_bits[0x10];
8799
8800         u8         ber_bath_high_error_threshold[0x10];
8801         u8         ber_bath_mid_error_threshold[0x10];
8802
8803         u8         ber_bath_low_error_threshold[0x10];
8804         u8         one_ratio_high_threshold[0x10];
8805
8806         u8         one_ratio_high_mid_threshold[0x10];
8807         u8         one_ratio_low_mid_threshold[0x10];
8808
8809         u8         one_ratio_low_threshold[0x10];
8810         u8         ndeo_error_threshold[0x10];
8811
8812         u8         mixer_offset_step_size[0x10];
8813         u8         reserved_at_110[0x8];
8814         u8         mix90_phase_for_voltage_bath[0x8];
8815
8816         u8         mixer_offset_start[0x10];
8817         u8         mixer_offset_end[0x10];
8818
8819         u8         reserved_at_140[0x15];
8820         u8         ber_test_time[0xb];
8821 };
8822
8823 struct mlx5_ifc_pspa_reg_bits {
8824         u8         swid[0x8];
8825         u8         local_port[0x8];
8826         u8         sub_port[0x8];
8827         u8         reserved_at_18[0x8];
8828
8829         u8         reserved_at_20[0x20];
8830 };
8831
8832 struct mlx5_ifc_pqdr_reg_bits {
8833         u8         reserved_at_0[0x8];
8834         u8         local_port[0x8];
8835         u8         reserved_at_10[0x5];
8836         u8         prio[0x3];
8837         u8         reserved_at_18[0x6];
8838         u8         mode[0x2];
8839
8840         u8         reserved_at_20[0x20];
8841
8842         u8         reserved_at_40[0x10];
8843         u8         min_threshold[0x10];
8844
8845         u8         reserved_at_60[0x10];
8846         u8         max_threshold[0x10];
8847
8848         u8         reserved_at_80[0x10];
8849         u8         mark_probability_denominator[0x10];
8850
8851         u8         reserved_at_a0[0x60];
8852 };
8853
8854 struct mlx5_ifc_ppsc_reg_bits {
8855         u8         reserved_at_0[0x8];
8856         u8         local_port[0x8];
8857         u8         reserved_at_10[0x10];
8858
8859         u8         reserved_at_20[0x60];
8860
8861         u8         reserved_at_80[0x1c];
8862         u8         wrps_admin[0x4];
8863
8864         u8         reserved_at_a0[0x1c];
8865         u8         wrps_status[0x4];
8866
8867         u8         reserved_at_c0[0x8];
8868         u8         up_threshold[0x8];
8869         u8         reserved_at_d0[0x8];
8870         u8         down_threshold[0x8];
8871
8872         u8         reserved_at_e0[0x20];
8873
8874         u8         reserved_at_100[0x1c];
8875         u8         srps_admin[0x4];
8876
8877         u8         reserved_at_120[0x1c];
8878         u8         srps_status[0x4];
8879
8880         u8         reserved_at_140[0x40];
8881 };
8882
8883 struct mlx5_ifc_pplr_reg_bits {
8884         u8         reserved_at_0[0x8];
8885         u8         local_port[0x8];
8886         u8         reserved_at_10[0x10];
8887
8888         u8         reserved_at_20[0x8];
8889         u8         lb_cap[0x8];
8890         u8         reserved_at_30[0x8];
8891         u8         lb_en[0x8];
8892 };
8893
8894 struct mlx5_ifc_pplm_reg_bits {
8895         u8         reserved_at_0[0x8];
8896         u8         local_port[0x8];
8897         u8         reserved_at_10[0x10];
8898
8899         u8         reserved_at_20[0x20];
8900
8901         u8         port_profile_mode[0x8];
8902         u8         static_port_profile[0x8];
8903         u8         active_port_profile[0x8];
8904         u8         reserved_at_58[0x8];
8905
8906         u8         retransmission_active[0x8];
8907         u8         fec_mode_active[0x18];
8908
8909         u8         rs_fec_correction_bypass_cap[0x4];
8910         u8         reserved_at_84[0x8];
8911         u8         fec_override_cap_56g[0x4];
8912         u8         fec_override_cap_100g[0x4];
8913         u8         fec_override_cap_50g[0x4];
8914         u8         fec_override_cap_25g[0x4];
8915         u8         fec_override_cap_10g_40g[0x4];
8916
8917         u8         rs_fec_correction_bypass_admin[0x4];
8918         u8         reserved_at_a4[0x8];
8919         u8         fec_override_admin_56g[0x4];
8920         u8         fec_override_admin_100g[0x4];
8921         u8         fec_override_admin_50g[0x4];
8922         u8         fec_override_admin_25g[0x4];
8923         u8         fec_override_admin_10g_40g[0x4];
8924
8925         u8         fec_override_cap_400g_8x[0x10];
8926         u8         fec_override_cap_200g_4x[0x10];
8927
8928         u8         fec_override_cap_100g_2x[0x10];
8929         u8         fec_override_cap_50g_1x[0x10];
8930
8931         u8         fec_override_admin_400g_8x[0x10];
8932         u8         fec_override_admin_200g_4x[0x10];
8933
8934         u8         fec_override_admin_100g_2x[0x10];
8935         u8         fec_override_admin_50g_1x[0x10];
8936
8937         u8         reserved_at_140[0x140];
8938 };
8939
8940 struct mlx5_ifc_ppcnt_reg_bits {
8941         u8         swid[0x8];
8942         u8         local_port[0x8];
8943         u8         pnat[0x2];
8944         u8         reserved_at_12[0x8];
8945         u8         grp[0x6];
8946
8947         u8         clr[0x1];
8948         u8         reserved_at_21[0x1c];
8949         u8         prio_tc[0x3];
8950
8951         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8952 };
8953
8954 struct mlx5_ifc_mpein_reg_bits {
8955         u8         reserved_at_0[0x2];
8956         u8         depth[0x6];
8957         u8         pcie_index[0x8];
8958         u8         node[0x8];
8959         u8         reserved_at_18[0x8];
8960
8961         u8         capability_mask[0x20];
8962
8963         u8         reserved_at_40[0x8];
8964         u8         link_width_enabled[0x8];
8965         u8         link_speed_enabled[0x10];
8966
8967         u8         lane0_physical_position[0x8];
8968         u8         link_width_active[0x8];
8969         u8         link_speed_active[0x10];
8970
8971         u8         num_of_pfs[0x10];
8972         u8         num_of_vfs[0x10];
8973
8974         u8         bdf0[0x10];
8975         u8         reserved_at_b0[0x10];
8976
8977         u8         max_read_request_size[0x4];
8978         u8         max_payload_size[0x4];
8979         u8         reserved_at_c8[0x5];
8980         u8         pwr_status[0x3];
8981         u8         port_type[0x4];
8982         u8         reserved_at_d4[0xb];
8983         u8         lane_reversal[0x1];
8984
8985         u8         reserved_at_e0[0x14];
8986         u8         pci_power[0xc];
8987
8988         u8         reserved_at_100[0x20];
8989
8990         u8         device_status[0x10];
8991         u8         port_state[0x8];
8992         u8         reserved_at_138[0x8];
8993
8994         u8         reserved_at_140[0x10];
8995         u8         receiver_detect_result[0x10];
8996
8997         u8         reserved_at_160[0x20];
8998 };
8999
9000 struct mlx5_ifc_mpcnt_reg_bits {
9001         u8         reserved_at_0[0x8];
9002         u8         pcie_index[0x8];
9003         u8         reserved_at_10[0xa];
9004         u8         grp[0x6];
9005
9006         u8         clr[0x1];
9007         u8         reserved_at_21[0x1f];
9008
9009         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9010 };
9011
9012 struct mlx5_ifc_ppad_reg_bits {
9013         u8         reserved_at_0[0x3];
9014         u8         single_mac[0x1];
9015         u8         reserved_at_4[0x4];
9016         u8         local_port[0x8];
9017         u8         mac_47_32[0x10];
9018
9019         u8         mac_31_0[0x20];
9020
9021         u8         reserved_at_40[0x40];
9022 };
9023
9024 struct mlx5_ifc_pmtu_reg_bits {
9025         u8         reserved_at_0[0x8];
9026         u8         local_port[0x8];
9027         u8         reserved_at_10[0x10];
9028
9029         u8         max_mtu[0x10];
9030         u8         reserved_at_30[0x10];
9031
9032         u8         admin_mtu[0x10];
9033         u8         reserved_at_50[0x10];
9034
9035         u8         oper_mtu[0x10];
9036         u8         reserved_at_70[0x10];
9037 };
9038
9039 struct mlx5_ifc_pmpr_reg_bits {
9040         u8         reserved_at_0[0x8];
9041         u8         module[0x8];
9042         u8         reserved_at_10[0x10];
9043
9044         u8         reserved_at_20[0x18];
9045         u8         attenuation_5g[0x8];
9046
9047         u8         reserved_at_40[0x18];
9048         u8         attenuation_7g[0x8];
9049
9050         u8         reserved_at_60[0x18];
9051         u8         attenuation_12g[0x8];
9052 };
9053
9054 struct mlx5_ifc_pmpe_reg_bits {
9055         u8         reserved_at_0[0x8];
9056         u8         module[0x8];
9057         u8         reserved_at_10[0xc];
9058         u8         module_status[0x4];
9059
9060         u8         reserved_at_20[0x60];
9061 };
9062
9063 struct mlx5_ifc_pmpc_reg_bits {
9064         u8         module_state_updated[32][0x8];
9065 };
9066
9067 struct mlx5_ifc_pmlpn_reg_bits {
9068         u8         reserved_at_0[0x4];
9069         u8         mlpn_status[0x4];
9070         u8         local_port[0x8];
9071         u8         reserved_at_10[0x10];
9072
9073         u8         e[0x1];
9074         u8         reserved_at_21[0x1f];
9075 };
9076
9077 struct mlx5_ifc_pmlp_reg_bits {
9078         u8         rxtx[0x1];
9079         u8         reserved_at_1[0x7];
9080         u8         local_port[0x8];
9081         u8         reserved_at_10[0x8];
9082         u8         width[0x8];
9083
9084         u8         lane0_module_mapping[0x20];
9085
9086         u8         lane1_module_mapping[0x20];
9087
9088         u8         lane2_module_mapping[0x20];
9089
9090         u8         lane3_module_mapping[0x20];
9091
9092         u8         reserved_at_a0[0x160];
9093 };
9094
9095 struct mlx5_ifc_pmaos_reg_bits {
9096         u8         reserved_at_0[0x8];
9097         u8         module[0x8];
9098         u8         reserved_at_10[0x4];
9099         u8         admin_status[0x4];
9100         u8         reserved_at_18[0x4];
9101         u8         oper_status[0x4];
9102
9103         u8         ase[0x1];
9104         u8         ee[0x1];
9105         u8         reserved_at_22[0x1c];
9106         u8         e[0x2];
9107
9108         u8         reserved_at_40[0x40];
9109 };
9110
9111 struct mlx5_ifc_plpc_reg_bits {
9112         u8         reserved_at_0[0x4];
9113         u8         profile_id[0xc];
9114         u8         reserved_at_10[0x4];
9115         u8         proto_mask[0x4];
9116         u8         reserved_at_18[0x8];
9117
9118         u8         reserved_at_20[0x10];
9119         u8         lane_speed[0x10];
9120
9121         u8         reserved_at_40[0x17];
9122         u8         lpbf[0x1];
9123         u8         fec_mode_policy[0x8];
9124
9125         u8         retransmission_capability[0x8];
9126         u8         fec_mode_capability[0x18];
9127
9128         u8         retransmission_support_admin[0x8];
9129         u8         fec_mode_support_admin[0x18];
9130
9131         u8         retransmission_request_admin[0x8];
9132         u8         fec_mode_request_admin[0x18];
9133
9134         u8         reserved_at_c0[0x80];
9135 };
9136
9137 struct mlx5_ifc_plib_reg_bits {
9138         u8         reserved_at_0[0x8];
9139         u8         local_port[0x8];
9140         u8         reserved_at_10[0x8];
9141         u8         ib_port[0x8];
9142
9143         u8         reserved_at_20[0x60];
9144 };
9145
9146 struct mlx5_ifc_plbf_reg_bits {
9147         u8         reserved_at_0[0x8];
9148         u8         local_port[0x8];
9149         u8         reserved_at_10[0xd];
9150         u8         lbf_mode[0x3];
9151
9152         u8         reserved_at_20[0x20];
9153 };
9154
9155 struct mlx5_ifc_pipg_reg_bits {
9156         u8         reserved_at_0[0x8];
9157         u8         local_port[0x8];
9158         u8         reserved_at_10[0x10];
9159
9160         u8         dic[0x1];
9161         u8         reserved_at_21[0x19];
9162         u8         ipg[0x4];
9163         u8         reserved_at_3e[0x2];
9164 };
9165
9166 struct mlx5_ifc_pifr_reg_bits {
9167         u8         reserved_at_0[0x8];
9168         u8         local_port[0x8];
9169         u8         reserved_at_10[0x10];
9170
9171         u8         reserved_at_20[0xe0];
9172
9173         u8         port_filter[8][0x20];
9174
9175         u8         port_filter_update_en[8][0x20];
9176 };
9177
9178 struct mlx5_ifc_pfcc_reg_bits {
9179         u8         reserved_at_0[0x8];
9180         u8         local_port[0x8];
9181         u8         reserved_at_10[0xb];
9182         u8         ppan_mask_n[0x1];
9183         u8         minor_stall_mask[0x1];
9184         u8         critical_stall_mask[0x1];
9185         u8         reserved_at_1e[0x2];
9186
9187         u8         ppan[0x4];
9188         u8         reserved_at_24[0x4];
9189         u8         prio_mask_tx[0x8];
9190         u8         reserved_at_30[0x8];
9191         u8         prio_mask_rx[0x8];
9192
9193         u8         pptx[0x1];
9194         u8         aptx[0x1];
9195         u8         pptx_mask_n[0x1];
9196         u8         reserved_at_43[0x5];
9197         u8         pfctx[0x8];
9198         u8         reserved_at_50[0x10];
9199
9200         u8         pprx[0x1];
9201         u8         aprx[0x1];
9202         u8         pprx_mask_n[0x1];
9203         u8         reserved_at_63[0x5];
9204         u8         pfcrx[0x8];
9205         u8         reserved_at_70[0x10];
9206
9207         u8         device_stall_minor_watermark[0x10];
9208         u8         device_stall_critical_watermark[0x10];
9209
9210         u8         reserved_at_a0[0x60];
9211 };
9212
9213 struct mlx5_ifc_pelc_reg_bits {
9214         u8         op[0x4];
9215         u8         reserved_at_4[0x4];
9216         u8         local_port[0x8];
9217         u8         reserved_at_10[0x10];
9218
9219         u8         op_admin[0x8];
9220         u8         op_capability[0x8];
9221         u8         op_request[0x8];
9222         u8         op_active[0x8];
9223
9224         u8         admin[0x40];
9225
9226         u8         capability[0x40];
9227
9228         u8         request[0x40];
9229
9230         u8         active[0x40];
9231
9232         u8         reserved_at_140[0x80];
9233 };
9234
9235 struct mlx5_ifc_peir_reg_bits {
9236         u8         reserved_at_0[0x8];
9237         u8         local_port[0x8];
9238         u8         reserved_at_10[0x10];
9239
9240         u8         reserved_at_20[0xc];
9241         u8         error_count[0x4];
9242         u8         reserved_at_30[0x10];
9243
9244         u8         reserved_at_40[0xc];
9245         u8         lane[0x4];
9246         u8         reserved_at_50[0x8];
9247         u8         error_type[0x8];
9248 };
9249
9250 struct mlx5_ifc_mpegc_reg_bits {
9251         u8         reserved_at_0[0x30];
9252         u8         field_select[0x10];
9253
9254         u8         tx_overflow_sense[0x1];
9255         u8         mark_cqe[0x1];
9256         u8         mark_cnp[0x1];
9257         u8         reserved_at_43[0x1b];
9258         u8         tx_lossy_overflow_oper[0x2];
9259
9260         u8         reserved_at_60[0x100];
9261 };
9262
9263 enum {
9264         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9265         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9266         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9267 };
9268
9269 struct mlx5_ifc_mtutc_reg_bits {
9270         u8         reserved_at_0[0x1c];
9271         u8         operation[0x4];
9272
9273         u8         freq_adjustment[0x20];
9274
9275         u8         reserved_at_40[0x40];
9276
9277         u8         utc_sec[0x20];
9278
9279         u8         reserved_at_a0[0x2];
9280         u8         utc_nsec[0x1e];
9281
9282         u8         time_adjustment[0x20];
9283 };
9284
9285 struct mlx5_ifc_pcam_enhanced_features_bits {
9286         u8         reserved_at_0[0x68];
9287         u8         fec_50G_per_lane_in_pplm[0x1];
9288         u8         reserved_at_69[0x4];
9289         u8         rx_icrc_encapsulated_counter[0x1];
9290         u8         reserved_at_6e[0x4];
9291         u8         ptys_extended_ethernet[0x1];
9292         u8         reserved_at_73[0x3];
9293         u8         pfcc_mask[0x1];
9294         u8         reserved_at_77[0x3];
9295         u8         per_lane_error_counters[0x1];
9296         u8         rx_buffer_fullness_counters[0x1];
9297         u8         ptys_connector_type[0x1];
9298         u8         reserved_at_7d[0x1];
9299         u8         ppcnt_discard_group[0x1];
9300         u8         ppcnt_statistical_group[0x1];
9301 };
9302
9303 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9304         u8         port_access_reg_cap_mask_127_to_96[0x20];
9305         u8         port_access_reg_cap_mask_95_to_64[0x20];
9306
9307         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9308         u8         pplm[0x1];
9309         u8         port_access_reg_cap_mask_34_to_32[0x3];
9310
9311         u8         port_access_reg_cap_mask_31_to_13[0x13];
9312         u8         pbmc[0x1];
9313         u8         pptb[0x1];
9314         u8         port_access_reg_cap_mask_10_to_09[0x2];
9315         u8         ppcnt[0x1];
9316         u8         port_access_reg_cap_mask_07_to_00[0x8];
9317 };
9318
9319 struct mlx5_ifc_pcam_reg_bits {
9320         u8         reserved_at_0[0x8];
9321         u8         feature_group[0x8];
9322         u8         reserved_at_10[0x8];
9323         u8         access_reg_group[0x8];
9324
9325         u8         reserved_at_20[0x20];
9326
9327         union {
9328                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9329                 u8         reserved_at_0[0x80];
9330         } port_access_reg_cap_mask;
9331
9332         u8         reserved_at_c0[0x80];
9333
9334         union {
9335                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9336                 u8         reserved_at_0[0x80];
9337         } feature_cap_mask;
9338
9339         u8         reserved_at_1c0[0xc0];
9340 };
9341
9342 struct mlx5_ifc_mcam_enhanced_features_bits {
9343         u8         reserved_at_0[0x6b];
9344         u8         ptpcyc2realtime_modify[0x1];
9345         u8         reserved_at_6c[0x2];
9346         u8         pci_status_and_power[0x1];
9347         u8         reserved_at_6f[0x5];
9348         u8         mark_tx_action_cnp[0x1];
9349         u8         mark_tx_action_cqe[0x1];
9350         u8         dynamic_tx_overflow[0x1];
9351         u8         reserved_at_77[0x4];
9352         u8         pcie_outbound_stalled[0x1];
9353         u8         tx_overflow_buffer_pkt[0x1];
9354         u8         mtpps_enh_out_per_adj[0x1];
9355         u8         mtpps_fs[0x1];
9356         u8         pcie_performance_group[0x1];
9357 };
9358
9359 struct mlx5_ifc_mcam_access_reg_bits {
9360         u8         reserved_at_0[0x1c];
9361         u8         mcda[0x1];
9362         u8         mcc[0x1];
9363         u8         mcqi[0x1];
9364         u8         mcqs[0x1];
9365
9366         u8         regs_95_to_87[0x9];
9367         u8         mpegc[0x1];
9368         u8         mtutc[0x1];
9369         u8         regs_84_to_68[0x11];
9370         u8         tracer_registers[0x4];
9371
9372         u8         regs_63_to_32[0x20];
9373         u8         regs_31_to_0[0x20];
9374 };
9375
9376 struct mlx5_ifc_mcam_access_reg_bits1 {
9377         u8         regs_127_to_96[0x20];
9378
9379         u8         regs_95_to_64[0x20];
9380
9381         u8         regs_63_to_32[0x20];
9382
9383         u8         regs_31_to_0[0x20];
9384 };
9385
9386 struct mlx5_ifc_mcam_access_reg_bits2 {
9387         u8         regs_127_to_99[0x1d];
9388         u8         mirc[0x1];
9389         u8         regs_97_to_96[0x2];
9390
9391         u8         regs_95_to_64[0x20];
9392
9393         u8         regs_63_to_32[0x20];
9394
9395         u8         regs_31_to_0[0x20];
9396 };
9397
9398 struct mlx5_ifc_mcam_reg_bits {
9399         u8         reserved_at_0[0x8];
9400         u8         feature_group[0x8];
9401         u8         reserved_at_10[0x8];
9402         u8         access_reg_group[0x8];
9403
9404         u8         reserved_at_20[0x20];
9405
9406         union {
9407                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9408                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9409                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9410                 u8         reserved_at_0[0x80];
9411         } mng_access_reg_cap_mask;
9412
9413         u8         reserved_at_c0[0x80];
9414
9415         union {
9416                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9417                 u8         reserved_at_0[0x80];
9418         } mng_feature_cap_mask;
9419
9420         u8         reserved_at_1c0[0x80];
9421 };
9422
9423 struct mlx5_ifc_qcam_access_reg_cap_mask {
9424         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9425         u8         qpdpm[0x1];
9426         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9427         u8         qdpm[0x1];
9428         u8         qpts[0x1];
9429         u8         qcap[0x1];
9430         u8         qcam_access_reg_cap_mask_0[0x1];
9431 };
9432
9433 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9434         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9435         u8         qpts_trust_both[0x1];
9436 };
9437
9438 struct mlx5_ifc_qcam_reg_bits {
9439         u8         reserved_at_0[0x8];
9440         u8         feature_group[0x8];
9441         u8         reserved_at_10[0x8];
9442         u8         access_reg_group[0x8];
9443         u8         reserved_at_20[0x20];
9444
9445         union {
9446                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9447                 u8  reserved_at_0[0x80];
9448         } qos_access_reg_cap_mask;
9449
9450         u8         reserved_at_c0[0x80];
9451
9452         union {
9453                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9454                 u8  reserved_at_0[0x80];
9455         } qos_feature_cap_mask;
9456
9457         u8         reserved_at_1c0[0x80];
9458 };
9459
9460 struct mlx5_ifc_core_dump_reg_bits {
9461         u8         reserved_at_0[0x18];
9462         u8         core_dump_type[0x8];
9463
9464         u8         reserved_at_20[0x30];
9465         u8         vhca_id[0x10];
9466
9467         u8         reserved_at_60[0x8];
9468         u8         qpn[0x18];
9469         u8         reserved_at_80[0x180];
9470 };
9471
9472 struct mlx5_ifc_pcap_reg_bits {
9473         u8         reserved_at_0[0x8];
9474         u8         local_port[0x8];
9475         u8         reserved_at_10[0x10];
9476
9477         u8         port_capability_mask[4][0x20];
9478 };
9479
9480 struct mlx5_ifc_paos_reg_bits {
9481         u8         swid[0x8];
9482         u8         local_port[0x8];
9483         u8         reserved_at_10[0x4];
9484         u8         admin_status[0x4];
9485         u8         reserved_at_18[0x4];
9486         u8         oper_status[0x4];
9487
9488         u8         ase[0x1];
9489         u8         ee[0x1];
9490         u8         reserved_at_22[0x1c];
9491         u8         e[0x2];
9492
9493         u8         reserved_at_40[0x40];
9494 };
9495
9496 struct mlx5_ifc_pamp_reg_bits {
9497         u8         reserved_at_0[0x8];
9498         u8         opamp_group[0x8];
9499         u8         reserved_at_10[0xc];
9500         u8         opamp_group_type[0x4];
9501
9502         u8         start_index[0x10];
9503         u8         reserved_at_30[0x4];
9504         u8         num_of_indices[0xc];
9505
9506         u8         index_data[18][0x10];
9507 };
9508
9509 struct mlx5_ifc_pcmr_reg_bits {
9510         u8         reserved_at_0[0x8];
9511         u8         local_port[0x8];
9512         u8         reserved_at_10[0x10];
9513
9514         u8         entropy_force_cap[0x1];
9515         u8         entropy_calc_cap[0x1];
9516         u8         entropy_gre_calc_cap[0x1];
9517         u8         reserved_at_23[0xf];
9518         u8         rx_ts_over_crc_cap[0x1];
9519         u8         reserved_at_33[0xb];
9520         u8         fcs_cap[0x1];
9521         u8         reserved_at_3f[0x1];
9522
9523         u8         entropy_force[0x1];
9524         u8         entropy_calc[0x1];
9525         u8         entropy_gre_calc[0x1];
9526         u8         reserved_at_43[0xf];
9527         u8         rx_ts_over_crc[0x1];
9528         u8         reserved_at_53[0xb];
9529         u8         fcs_chk[0x1];
9530         u8         reserved_at_5f[0x1];
9531 };
9532
9533 struct mlx5_ifc_lane_2_module_mapping_bits {
9534         u8         reserved_at_0[0x6];
9535         u8         rx_lane[0x2];
9536         u8         reserved_at_8[0x6];
9537         u8         tx_lane[0x2];
9538         u8         reserved_at_10[0x8];
9539         u8         module[0x8];
9540 };
9541
9542 struct mlx5_ifc_bufferx_reg_bits {
9543         u8         reserved_at_0[0x6];
9544         u8         lossy[0x1];
9545         u8         epsb[0x1];
9546         u8         reserved_at_8[0xc];
9547         u8         size[0xc];
9548
9549         u8         xoff_threshold[0x10];
9550         u8         xon_threshold[0x10];
9551 };
9552
9553 struct mlx5_ifc_set_node_in_bits {
9554         u8         node_description[64][0x8];
9555 };
9556
9557 struct mlx5_ifc_register_power_settings_bits {
9558         u8         reserved_at_0[0x18];
9559         u8         power_settings_level[0x8];
9560
9561         u8         reserved_at_20[0x60];
9562 };
9563
9564 struct mlx5_ifc_register_host_endianness_bits {
9565         u8         he[0x1];
9566         u8         reserved_at_1[0x1f];
9567
9568         u8         reserved_at_20[0x60];
9569 };
9570
9571 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9572         u8         reserved_at_0[0x20];
9573
9574         u8         mkey[0x20];
9575
9576         u8         addressh_63_32[0x20];
9577
9578         u8         addressl_31_0[0x20];
9579 };
9580
9581 struct mlx5_ifc_ud_adrs_vector_bits {
9582         u8         dc_key[0x40];
9583
9584         u8         ext[0x1];
9585         u8         reserved_at_41[0x7];
9586         u8         destination_qp_dct[0x18];
9587
9588         u8         static_rate[0x4];
9589         u8         sl_eth_prio[0x4];
9590         u8         fl[0x1];
9591         u8         mlid[0x7];
9592         u8         rlid_udp_sport[0x10];
9593
9594         u8         reserved_at_80[0x20];
9595
9596         u8         rmac_47_16[0x20];
9597
9598         u8         rmac_15_0[0x10];
9599         u8         tclass[0x8];
9600         u8         hop_limit[0x8];
9601
9602         u8         reserved_at_e0[0x1];
9603         u8         grh[0x1];
9604         u8         reserved_at_e2[0x2];
9605         u8         src_addr_index[0x8];
9606         u8         flow_label[0x14];
9607
9608         u8         rgid_rip[16][0x8];
9609 };
9610
9611 struct mlx5_ifc_pages_req_event_bits {
9612         u8         reserved_at_0[0x10];
9613         u8         function_id[0x10];
9614
9615         u8         num_pages[0x20];
9616
9617         u8         reserved_at_40[0xa0];
9618 };
9619
9620 struct mlx5_ifc_eqe_bits {
9621         u8         reserved_at_0[0x8];
9622         u8         event_type[0x8];
9623         u8         reserved_at_10[0x8];
9624         u8         event_sub_type[0x8];
9625
9626         u8         reserved_at_20[0xe0];
9627
9628         union mlx5_ifc_event_auto_bits event_data;
9629
9630         u8         reserved_at_1e0[0x10];
9631         u8         signature[0x8];
9632         u8         reserved_at_1f8[0x7];
9633         u8         owner[0x1];
9634 };
9635
9636 enum {
9637         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9638 };
9639
9640 struct mlx5_ifc_cmd_queue_entry_bits {
9641         u8         type[0x8];
9642         u8         reserved_at_8[0x18];
9643
9644         u8         input_length[0x20];
9645
9646         u8         input_mailbox_pointer_63_32[0x20];
9647
9648         u8         input_mailbox_pointer_31_9[0x17];
9649         u8         reserved_at_77[0x9];
9650
9651         u8         command_input_inline_data[16][0x8];
9652
9653         u8         command_output_inline_data[16][0x8];
9654
9655         u8         output_mailbox_pointer_63_32[0x20];
9656
9657         u8         output_mailbox_pointer_31_9[0x17];
9658         u8         reserved_at_1b7[0x9];
9659
9660         u8         output_length[0x20];
9661
9662         u8         token[0x8];
9663         u8         signature[0x8];
9664         u8         reserved_at_1f0[0x8];
9665         u8         status[0x7];
9666         u8         ownership[0x1];
9667 };
9668
9669 struct mlx5_ifc_cmd_out_bits {
9670         u8         status[0x8];
9671         u8         reserved_at_8[0x18];
9672
9673         u8         syndrome[0x20];
9674
9675         u8         command_output[0x20];
9676 };
9677
9678 struct mlx5_ifc_cmd_in_bits {
9679         u8         opcode[0x10];
9680         u8         reserved_at_10[0x10];
9681
9682         u8         reserved_at_20[0x10];
9683         u8         op_mod[0x10];
9684
9685         u8         command[][0x20];
9686 };
9687
9688 struct mlx5_ifc_cmd_if_box_bits {
9689         u8         mailbox_data[512][0x8];
9690
9691         u8         reserved_at_1000[0x180];
9692
9693         u8         next_pointer_63_32[0x20];
9694
9695         u8         next_pointer_31_10[0x16];
9696         u8         reserved_at_11b6[0xa];
9697
9698         u8         block_number[0x20];
9699
9700         u8         reserved_at_11e0[0x8];
9701         u8         token[0x8];
9702         u8         ctrl_signature[0x8];
9703         u8         signature[0x8];
9704 };
9705
9706 struct mlx5_ifc_mtt_bits {
9707         u8         ptag_63_32[0x20];
9708
9709         u8         ptag_31_8[0x18];
9710         u8         reserved_at_38[0x6];
9711         u8         wr_en[0x1];
9712         u8         rd_en[0x1];
9713 };
9714
9715 struct mlx5_ifc_query_wol_rol_out_bits {
9716         u8         status[0x8];
9717         u8         reserved_at_8[0x18];
9718
9719         u8         syndrome[0x20];
9720
9721         u8         reserved_at_40[0x10];
9722         u8         rol_mode[0x8];
9723         u8         wol_mode[0x8];
9724
9725         u8         reserved_at_60[0x20];
9726 };
9727
9728 struct mlx5_ifc_query_wol_rol_in_bits {
9729         u8         opcode[0x10];
9730         u8         reserved_at_10[0x10];
9731
9732         u8         reserved_at_20[0x10];
9733         u8         op_mod[0x10];
9734
9735         u8         reserved_at_40[0x40];
9736 };
9737
9738 struct mlx5_ifc_set_wol_rol_out_bits {
9739         u8         status[0x8];
9740         u8         reserved_at_8[0x18];
9741
9742         u8         syndrome[0x20];
9743
9744         u8         reserved_at_40[0x40];
9745 };
9746
9747 struct mlx5_ifc_set_wol_rol_in_bits {
9748         u8         opcode[0x10];
9749         u8         reserved_at_10[0x10];
9750
9751         u8         reserved_at_20[0x10];
9752         u8         op_mod[0x10];
9753
9754         u8         rol_mode_valid[0x1];
9755         u8         wol_mode_valid[0x1];
9756         u8         reserved_at_42[0xe];
9757         u8         rol_mode[0x8];
9758         u8         wol_mode[0x8];
9759
9760         u8         reserved_at_60[0x20];
9761 };
9762
9763 enum {
9764         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9765         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9766         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9767 };
9768
9769 enum {
9770         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9771         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9772         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9773 };
9774
9775 enum {
9776         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9777         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9778         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9779         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9780         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9781         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9782         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9783         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9784         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9785         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9786         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9787 };
9788
9789 struct mlx5_ifc_initial_seg_bits {
9790         u8         fw_rev_minor[0x10];
9791         u8         fw_rev_major[0x10];
9792
9793         u8         cmd_interface_rev[0x10];
9794         u8         fw_rev_subminor[0x10];
9795
9796         u8         reserved_at_40[0x40];
9797
9798         u8         cmdq_phy_addr_63_32[0x20];
9799
9800         u8         cmdq_phy_addr_31_12[0x14];
9801         u8         reserved_at_b4[0x2];
9802         u8         nic_interface[0x2];
9803         u8         log_cmdq_size[0x4];
9804         u8         log_cmdq_stride[0x4];
9805
9806         u8         command_doorbell_vector[0x20];
9807
9808         u8         reserved_at_e0[0xf00];
9809
9810         u8         initializing[0x1];
9811         u8         reserved_at_fe1[0x4];
9812         u8         nic_interface_supported[0x3];
9813         u8         embedded_cpu[0x1];
9814         u8         reserved_at_fe9[0x17];
9815
9816         struct mlx5_ifc_health_buffer_bits health_buffer;
9817
9818         u8         no_dram_nic_offset[0x20];
9819
9820         u8         reserved_at_1220[0x6e40];
9821
9822         u8         reserved_at_8060[0x1f];
9823         u8         clear_int[0x1];
9824
9825         u8         health_syndrome[0x8];
9826         u8         health_counter[0x18];
9827
9828         u8         reserved_at_80a0[0x17fc0];
9829 };
9830
9831 struct mlx5_ifc_mtpps_reg_bits {
9832         u8         reserved_at_0[0xc];
9833         u8         cap_number_of_pps_pins[0x4];
9834         u8         reserved_at_10[0x4];
9835         u8         cap_max_num_of_pps_in_pins[0x4];
9836         u8         reserved_at_18[0x4];
9837         u8         cap_max_num_of_pps_out_pins[0x4];
9838
9839         u8         reserved_at_20[0x24];
9840         u8         cap_pin_3_mode[0x4];
9841         u8         reserved_at_48[0x4];
9842         u8         cap_pin_2_mode[0x4];
9843         u8         reserved_at_50[0x4];
9844         u8         cap_pin_1_mode[0x4];
9845         u8         reserved_at_58[0x4];
9846         u8         cap_pin_0_mode[0x4];
9847
9848         u8         reserved_at_60[0x4];
9849         u8         cap_pin_7_mode[0x4];
9850         u8         reserved_at_68[0x4];
9851         u8         cap_pin_6_mode[0x4];
9852         u8         reserved_at_70[0x4];
9853         u8         cap_pin_5_mode[0x4];
9854         u8         reserved_at_78[0x4];
9855         u8         cap_pin_4_mode[0x4];
9856
9857         u8         field_select[0x20];
9858         u8         reserved_at_a0[0x60];
9859
9860         u8         enable[0x1];
9861         u8         reserved_at_101[0xb];
9862         u8         pattern[0x4];
9863         u8         reserved_at_110[0x4];
9864         u8         pin_mode[0x4];
9865         u8         pin[0x8];
9866
9867         u8         reserved_at_120[0x20];
9868
9869         u8         time_stamp[0x40];
9870
9871         u8         out_pulse_duration[0x10];
9872         u8         out_periodic_adjustment[0x10];
9873         u8         enhanced_out_periodic_adjustment[0x20];
9874
9875         u8         reserved_at_1c0[0x20];
9876 };
9877
9878 struct mlx5_ifc_mtppse_reg_bits {
9879         u8         reserved_at_0[0x18];
9880         u8         pin[0x8];
9881         u8         event_arm[0x1];
9882         u8         reserved_at_21[0x1b];
9883         u8         event_generation_mode[0x4];
9884         u8         reserved_at_40[0x40];
9885 };
9886
9887 struct mlx5_ifc_mcqs_reg_bits {
9888         u8         last_index_flag[0x1];
9889         u8         reserved_at_1[0x7];
9890         u8         fw_device[0x8];
9891         u8         component_index[0x10];
9892
9893         u8         reserved_at_20[0x10];
9894         u8         identifier[0x10];
9895
9896         u8         reserved_at_40[0x17];
9897         u8         component_status[0x5];
9898         u8         component_update_state[0x4];
9899
9900         u8         last_update_state_changer_type[0x4];
9901         u8         last_update_state_changer_host_id[0x4];
9902         u8         reserved_at_68[0x18];
9903 };
9904
9905 struct mlx5_ifc_mcqi_cap_bits {
9906         u8         supported_info_bitmask[0x20];
9907
9908         u8         component_size[0x20];
9909
9910         u8         max_component_size[0x20];
9911
9912         u8         log_mcda_word_size[0x4];
9913         u8         reserved_at_64[0xc];
9914         u8         mcda_max_write_size[0x10];
9915
9916         u8         rd_en[0x1];
9917         u8         reserved_at_81[0x1];
9918         u8         match_chip_id[0x1];
9919         u8         match_psid[0x1];
9920         u8         check_user_timestamp[0x1];
9921         u8         match_base_guid_mac[0x1];
9922         u8         reserved_at_86[0x1a];
9923 };
9924
9925 struct mlx5_ifc_mcqi_version_bits {
9926         u8         reserved_at_0[0x2];
9927         u8         build_time_valid[0x1];
9928         u8         user_defined_time_valid[0x1];
9929         u8         reserved_at_4[0x14];
9930         u8         version_string_length[0x8];
9931
9932         u8         version[0x20];
9933
9934         u8         build_time[0x40];
9935
9936         u8         user_defined_time[0x40];
9937
9938         u8         build_tool_version[0x20];
9939
9940         u8         reserved_at_e0[0x20];
9941
9942         u8         version_string[92][0x8];
9943 };
9944
9945 struct mlx5_ifc_mcqi_activation_method_bits {
9946         u8         pending_server_ac_power_cycle[0x1];
9947         u8         pending_server_dc_power_cycle[0x1];
9948         u8         pending_server_reboot[0x1];
9949         u8         pending_fw_reset[0x1];
9950         u8         auto_activate[0x1];
9951         u8         all_hosts_sync[0x1];
9952         u8         device_hw_reset[0x1];
9953         u8         reserved_at_7[0x19];
9954 };
9955
9956 union mlx5_ifc_mcqi_reg_data_bits {
9957         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9958         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9959         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9960 };
9961
9962 struct mlx5_ifc_mcqi_reg_bits {
9963         u8         read_pending_component[0x1];
9964         u8         reserved_at_1[0xf];
9965         u8         component_index[0x10];
9966
9967         u8         reserved_at_20[0x20];
9968
9969         u8         reserved_at_40[0x1b];
9970         u8         info_type[0x5];
9971
9972         u8         info_size[0x20];
9973
9974         u8         offset[0x20];
9975
9976         u8         reserved_at_a0[0x10];
9977         u8         data_size[0x10];
9978
9979         union mlx5_ifc_mcqi_reg_data_bits data[];
9980 };
9981
9982 struct mlx5_ifc_mcc_reg_bits {
9983         u8         reserved_at_0[0x4];
9984         u8         time_elapsed_since_last_cmd[0xc];
9985         u8         reserved_at_10[0x8];
9986         u8         instruction[0x8];
9987
9988         u8         reserved_at_20[0x10];
9989         u8         component_index[0x10];
9990
9991         u8         reserved_at_40[0x8];
9992         u8         update_handle[0x18];
9993
9994         u8         handle_owner_type[0x4];
9995         u8         handle_owner_host_id[0x4];
9996         u8         reserved_at_68[0x1];
9997         u8         control_progress[0x7];
9998         u8         error_code[0x8];
9999         u8         reserved_at_78[0x4];
10000         u8         control_state[0x4];
10001
10002         u8         component_size[0x20];
10003
10004         u8         reserved_at_a0[0x60];
10005 };
10006
10007 struct mlx5_ifc_mcda_reg_bits {
10008         u8         reserved_at_0[0x8];
10009         u8         update_handle[0x18];
10010
10011         u8         offset[0x20];
10012
10013         u8         reserved_at_40[0x10];
10014         u8         size[0x10];
10015
10016         u8         reserved_at_60[0x20];
10017
10018         u8         data[][0x20];
10019 };
10020
10021 enum {
10022         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10023         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10024 };
10025
10026 enum {
10027         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10028         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10029         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10030 };
10031
10032 struct mlx5_ifc_mfrl_reg_bits {
10033         u8         reserved_at_0[0x20];
10034
10035         u8         reserved_at_20[0x2];
10036         u8         pci_sync_for_fw_update_start[0x1];
10037         u8         pci_sync_for_fw_update_resp[0x2];
10038         u8         rst_type_sel[0x3];
10039         u8         reserved_at_28[0x8];
10040         u8         reset_type[0x8];
10041         u8         reset_level[0x8];
10042 };
10043
10044 struct mlx5_ifc_mirc_reg_bits {
10045         u8         reserved_at_0[0x18];
10046         u8         status_code[0x8];
10047
10048         u8         reserved_at_20[0x20];
10049 };
10050
10051 struct mlx5_ifc_pddr_monitor_opcode_bits {
10052         u8         reserved_at_0[0x10];
10053         u8         monitor_opcode[0x10];
10054 };
10055
10056 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10057         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10058         u8         reserved_at_0[0x20];
10059 };
10060
10061 enum {
10062         /* Monitor opcodes */
10063         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10064 };
10065
10066 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10067         u8         reserved_at_0[0x10];
10068         u8         group_opcode[0x10];
10069
10070         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10071
10072         u8         reserved_at_40[0x20];
10073
10074         u8         status_message[59][0x20];
10075 };
10076
10077 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10078         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10079         u8         reserved_at_0[0x7c0];
10080 };
10081
10082 enum {
10083         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10084 };
10085
10086 struct mlx5_ifc_pddr_reg_bits {
10087         u8         reserved_at_0[0x8];
10088         u8         local_port[0x8];
10089         u8         pnat[0x2];
10090         u8         reserved_at_12[0xe];
10091
10092         u8         reserved_at_20[0x18];
10093         u8         page_select[0x8];
10094
10095         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10096 };
10097
10098 union mlx5_ifc_ports_control_registers_document_bits {
10099         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10100         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10101         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10102         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10103         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10104         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10105         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10106         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10107         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10108         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10109         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10110         struct mlx5_ifc_paos_reg_bits paos_reg;
10111         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10112         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10113         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10114         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10115         struct mlx5_ifc_peir_reg_bits peir_reg;
10116         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10117         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10118         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10119         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10120         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10121         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10122         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10123         struct mlx5_ifc_plib_reg_bits plib_reg;
10124         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10125         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10126         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10127         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10128         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10129         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10130         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10131         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10132         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10133         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10134         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10135         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10136         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10137         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10138         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10139         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10140         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10141         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10142         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10143         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10144         struct mlx5_ifc_pude_reg_bits pude_reg;
10145         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10146         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10147         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10148         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10149         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10150         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10151         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10152         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10153         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10154         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10155         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10156         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10157         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10158         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10159         u8         reserved_at_0[0x60e0];
10160 };
10161
10162 union mlx5_ifc_debug_enhancements_document_bits {
10163         struct mlx5_ifc_health_buffer_bits health_buffer;
10164         u8         reserved_at_0[0x200];
10165 };
10166
10167 union mlx5_ifc_uplink_pci_interface_document_bits {
10168         struct mlx5_ifc_initial_seg_bits initial_seg;
10169         u8         reserved_at_0[0x20060];
10170 };
10171
10172 struct mlx5_ifc_set_flow_table_root_out_bits {
10173         u8         status[0x8];
10174         u8         reserved_at_8[0x18];
10175
10176         u8         syndrome[0x20];
10177
10178         u8         reserved_at_40[0x40];
10179 };
10180
10181 struct mlx5_ifc_set_flow_table_root_in_bits {
10182         u8         opcode[0x10];
10183         u8         reserved_at_10[0x10];
10184
10185         u8         reserved_at_20[0x10];
10186         u8         op_mod[0x10];
10187
10188         u8         other_vport[0x1];
10189         u8         reserved_at_41[0xf];
10190         u8         vport_number[0x10];
10191
10192         u8         reserved_at_60[0x20];
10193
10194         u8         table_type[0x8];
10195         u8         reserved_at_88[0x7];
10196         u8         table_of_other_vport[0x1];
10197         u8         table_vport_number[0x10];
10198
10199         u8         reserved_at_a0[0x8];
10200         u8         table_id[0x18];
10201
10202         u8         reserved_at_c0[0x8];
10203         u8         underlay_qpn[0x18];
10204         u8         table_eswitch_owner_vhca_id_valid[0x1];
10205         u8         reserved_at_e1[0xf];
10206         u8         table_eswitch_owner_vhca_id[0x10];
10207         u8         reserved_at_100[0x100];
10208 };
10209
10210 enum {
10211         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10212         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10213 };
10214
10215 struct mlx5_ifc_modify_flow_table_out_bits {
10216         u8         status[0x8];
10217         u8         reserved_at_8[0x18];
10218
10219         u8         syndrome[0x20];
10220
10221         u8         reserved_at_40[0x40];
10222 };
10223
10224 struct mlx5_ifc_modify_flow_table_in_bits {
10225         u8         opcode[0x10];
10226         u8         reserved_at_10[0x10];
10227
10228         u8         reserved_at_20[0x10];
10229         u8         op_mod[0x10];
10230
10231         u8         other_vport[0x1];
10232         u8         reserved_at_41[0xf];
10233         u8         vport_number[0x10];
10234
10235         u8         reserved_at_60[0x10];
10236         u8         modify_field_select[0x10];
10237
10238         u8         table_type[0x8];
10239         u8         reserved_at_88[0x18];
10240
10241         u8         reserved_at_a0[0x8];
10242         u8         table_id[0x18];
10243
10244         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10245 };
10246
10247 struct mlx5_ifc_ets_tcn_config_reg_bits {
10248         u8         g[0x1];
10249         u8         b[0x1];
10250         u8         r[0x1];
10251         u8         reserved_at_3[0x9];
10252         u8         group[0x4];
10253         u8         reserved_at_10[0x9];
10254         u8         bw_allocation[0x7];
10255
10256         u8         reserved_at_20[0xc];
10257         u8         max_bw_units[0x4];
10258         u8         reserved_at_30[0x8];
10259         u8         max_bw_value[0x8];
10260 };
10261
10262 struct mlx5_ifc_ets_global_config_reg_bits {
10263         u8         reserved_at_0[0x2];
10264         u8         r[0x1];
10265         u8         reserved_at_3[0x1d];
10266
10267         u8         reserved_at_20[0xc];
10268         u8         max_bw_units[0x4];
10269         u8         reserved_at_30[0x8];
10270         u8         max_bw_value[0x8];
10271 };
10272
10273 struct mlx5_ifc_qetc_reg_bits {
10274         u8                                         reserved_at_0[0x8];
10275         u8                                         port_number[0x8];
10276         u8                                         reserved_at_10[0x30];
10277
10278         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10279         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10280 };
10281
10282 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10283         u8         e[0x1];
10284         u8         reserved_at_01[0x0b];
10285         u8         prio[0x04];
10286 };
10287
10288 struct mlx5_ifc_qpdpm_reg_bits {
10289         u8                                     reserved_at_0[0x8];
10290         u8                                     local_port[0x8];
10291         u8                                     reserved_at_10[0x10];
10292         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10293 };
10294
10295 struct mlx5_ifc_qpts_reg_bits {
10296         u8         reserved_at_0[0x8];
10297         u8         local_port[0x8];
10298         u8         reserved_at_10[0x2d];
10299         u8         trust_state[0x3];
10300 };
10301
10302 struct mlx5_ifc_pptb_reg_bits {
10303         u8         reserved_at_0[0x2];
10304         u8         mm[0x2];
10305         u8         reserved_at_4[0x4];
10306         u8         local_port[0x8];
10307         u8         reserved_at_10[0x6];
10308         u8         cm[0x1];
10309         u8         um[0x1];
10310         u8         pm[0x8];
10311
10312         u8         prio_x_buff[0x20];
10313
10314         u8         pm_msb[0x8];
10315         u8         reserved_at_48[0x10];
10316         u8         ctrl_buff[0x4];
10317         u8         untagged_buff[0x4];
10318 };
10319
10320 struct mlx5_ifc_sbcam_reg_bits {
10321         u8         reserved_at_0[0x8];
10322         u8         feature_group[0x8];
10323         u8         reserved_at_10[0x8];
10324         u8         access_reg_group[0x8];
10325
10326         u8         reserved_at_20[0x20];
10327
10328         u8         sb_access_reg_cap_mask[4][0x20];
10329
10330         u8         reserved_at_c0[0x80];
10331
10332         u8         sb_feature_cap_mask[4][0x20];
10333
10334         u8         reserved_at_1c0[0x40];
10335
10336         u8         cap_total_buffer_size[0x20];
10337
10338         u8         cap_cell_size[0x10];
10339         u8         cap_max_pg_buffers[0x8];
10340         u8         cap_num_pool_supported[0x8];
10341
10342         u8         reserved_at_240[0x8];
10343         u8         cap_sbsr_stat_size[0x8];
10344         u8         cap_max_tclass_data[0x8];
10345         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10346 };
10347
10348 struct mlx5_ifc_pbmc_reg_bits {
10349         u8         reserved_at_0[0x8];
10350         u8         local_port[0x8];
10351         u8         reserved_at_10[0x10];
10352
10353         u8         xoff_timer_value[0x10];
10354         u8         xoff_refresh[0x10];
10355
10356         u8         reserved_at_40[0x9];
10357         u8         fullness_threshold[0x7];
10358         u8         port_buffer_size[0x10];
10359
10360         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10361
10362         u8         reserved_at_2e0[0x80];
10363 };
10364
10365 struct mlx5_ifc_qtct_reg_bits {
10366         u8         reserved_at_0[0x8];
10367         u8         port_number[0x8];
10368         u8         reserved_at_10[0xd];
10369         u8         prio[0x3];
10370
10371         u8         reserved_at_20[0x1d];
10372         u8         tclass[0x3];
10373 };
10374
10375 struct mlx5_ifc_mcia_reg_bits {
10376         u8         l[0x1];
10377         u8         reserved_at_1[0x7];
10378         u8         module[0x8];
10379         u8         reserved_at_10[0x8];
10380         u8         status[0x8];
10381
10382         u8         i2c_device_address[0x8];
10383         u8         page_number[0x8];
10384         u8         device_address[0x10];
10385
10386         u8         reserved_at_40[0x10];
10387         u8         size[0x10];
10388
10389         u8         reserved_at_60[0x20];
10390
10391         u8         dword_0[0x20];
10392         u8         dword_1[0x20];
10393         u8         dword_2[0x20];
10394         u8         dword_3[0x20];
10395         u8         dword_4[0x20];
10396         u8         dword_5[0x20];
10397         u8         dword_6[0x20];
10398         u8         dword_7[0x20];
10399         u8         dword_8[0x20];
10400         u8         dword_9[0x20];
10401         u8         dword_10[0x20];
10402         u8         dword_11[0x20];
10403 };
10404
10405 struct mlx5_ifc_dcbx_param_bits {
10406         u8         dcbx_cee_cap[0x1];
10407         u8         dcbx_ieee_cap[0x1];
10408         u8         dcbx_standby_cap[0x1];
10409         u8         reserved_at_3[0x5];
10410         u8         port_number[0x8];
10411         u8         reserved_at_10[0xa];
10412         u8         max_application_table_size[6];
10413         u8         reserved_at_20[0x15];
10414         u8         version_oper[0x3];
10415         u8         reserved_at_38[5];
10416         u8         version_admin[0x3];
10417         u8         willing_admin[0x1];
10418         u8         reserved_at_41[0x3];
10419         u8         pfc_cap_oper[0x4];
10420         u8         reserved_at_48[0x4];
10421         u8         pfc_cap_admin[0x4];
10422         u8         reserved_at_50[0x4];
10423         u8         num_of_tc_oper[0x4];
10424         u8         reserved_at_58[0x4];
10425         u8         num_of_tc_admin[0x4];
10426         u8         remote_willing[0x1];
10427         u8         reserved_at_61[3];
10428         u8         remote_pfc_cap[4];
10429         u8         reserved_at_68[0x14];
10430         u8         remote_num_of_tc[0x4];
10431         u8         reserved_at_80[0x18];
10432         u8         error[0x8];
10433         u8         reserved_at_a0[0x160];
10434 };
10435
10436 struct mlx5_ifc_lagc_bits {
10437         u8         fdb_selection_mode[0x1];
10438         u8         reserved_at_1[0x1c];
10439         u8         lag_state[0x3];
10440
10441         u8         reserved_at_20[0x14];
10442         u8         tx_remap_affinity_2[0x4];
10443         u8         reserved_at_38[0x4];
10444         u8         tx_remap_affinity_1[0x4];
10445 };
10446
10447 struct mlx5_ifc_create_lag_out_bits {
10448         u8         status[0x8];
10449         u8         reserved_at_8[0x18];
10450
10451         u8         syndrome[0x20];
10452
10453         u8         reserved_at_40[0x40];
10454 };
10455
10456 struct mlx5_ifc_create_lag_in_bits {
10457         u8         opcode[0x10];
10458         u8         reserved_at_10[0x10];
10459
10460         u8         reserved_at_20[0x10];
10461         u8         op_mod[0x10];
10462
10463         struct mlx5_ifc_lagc_bits ctx;
10464 };
10465
10466 struct mlx5_ifc_modify_lag_out_bits {
10467         u8         status[0x8];
10468         u8         reserved_at_8[0x18];
10469
10470         u8         syndrome[0x20];
10471
10472         u8         reserved_at_40[0x40];
10473 };
10474
10475 struct mlx5_ifc_modify_lag_in_bits {
10476         u8         opcode[0x10];
10477         u8         reserved_at_10[0x10];
10478
10479         u8         reserved_at_20[0x10];
10480         u8         op_mod[0x10];
10481
10482         u8         reserved_at_40[0x20];
10483         u8         field_select[0x20];
10484
10485         struct mlx5_ifc_lagc_bits ctx;
10486 };
10487
10488 struct mlx5_ifc_query_lag_out_bits {
10489         u8         status[0x8];
10490         u8         reserved_at_8[0x18];
10491
10492         u8         syndrome[0x20];
10493
10494         struct mlx5_ifc_lagc_bits ctx;
10495 };
10496
10497 struct mlx5_ifc_query_lag_in_bits {
10498         u8         opcode[0x10];
10499         u8         reserved_at_10[0x10];
10500
10501         u8         reserved_at_20[0x10];
10502         u8         op_mod[0x10];
10503
10504         u8         reserved_at_40[0x40];
10505 };
10506
10507 struct mlx5_ifc_destroy_lag_out_bits {
10508         u8         status[0x8];
10509         u8         reserved_at_8[0x18];
10510
10511         u8         syndrome[0x20];
10512
10513         u8         reserved_at_40[0x40];
10514 };
10515
10516 struct mlx5_ifc_destroy_lag_in_bits {
10517         u8         opcode[0x10];
10518         u8         reserved_at_10[0x10];
10519
10520         u8         reserved_at_20[0x10];
10521         u8         op_mod[0x10];
10522
10523         u8         reserved_at_40[0x40];
10524 };
10525
10526 struct mlx5_ifc_create_vport_lag_out_bits {
10527         u8         status[0x8];
10528         u8         reserved_at_8[0x18];
10529
10530         u8         syndrome[0x20];
10531
10532         u8         reserved_at_40[0x40];
10533 };
10534
10535 struct mlx5_ifc_create_vport_lag_in_bits {
10536         u8         opcode[0x10];
10537         u8         reserved_at_10[0x10];
10538
10539         u8         reserved_at_20[0x10];
10540         u8         op_mod[0x10];
10541
10542         u8         reserved_at_40[0x40];
10543 };
10544
10545 struct mlx5_ifc_destroy_vport_lag_out_bits {
10546         u8         status[0x8];
10547         u8         reserved_at_8[0x18];
10548
10549         u8         syndrome[0x20];
10550
10551         u8         reserved_at_40[0x40];
10552 };
10553
10554 struct mlx5_ifc_destroy_vport_lag_in_bits {
10555         u8         opcode[0x10];
10556         u8         reserved_at_10[0x10];
10557
10558         u8         reserved_at_20[0x10];
10559         u8         op_mod[0x10];
10560
10561         u8         reserved_at_40[0x40];
10562 };
10563
10564 enum {
10565         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10566         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10567 };
10568
10569 struct mlx5_ifc_modify_memic_in_bits {
10570         u8         opcode[0x10];
10571         u8         uid[0x10];
10572
10573         u8         reserved_at_20[0x10];
10574         u8         op_mod[0x10];
10575
10576         u8         reserved_at_40[0x20];
10577
10578         u8         reserved_at_60[0x18];
10579         u8         memic_operation_type[0x8];
10580
10581         u8         memic_start_addr[0x40];
10582
10583         u8         reserved_at_c0[0x140];
10584 };
10585
10586 struct mlx5_ifc_modify_memic_out_bits {
10587         u8         status[0x8];
10588         u8         reserved_at_8[0x18];
10589
10590         u8         syndrome[0x20];
10591
10592         u8         reserved_at_40[0x40];
10593
10594         u8         memic_operation_addr[0x40];
10595
10596         u8         reserved_at_c0[0x140];
10597 };
10598
10599 struct mlx5_ifc_alloc_memic_in_bits {
10600         u8         opcode[0x10];
10601         u8         reserved_at_10[0x10];
10602
10603         u8         reserved_at_20[0x10];
10604         u8         op_mod[0x10];
10605
10606         u8         reserved_at_30[0x20];
10607
10608         u8         reserved_at_40[0x18];
10609         u8         log_memic_addr_alignment[0x8];
10610
10611         u8         range_start_addr[0x40];
10612
10613         u8         range_size[0x20];
10614
10615         u8         memic_size[0x20];
10616 };
10617
10618 struct mlx5_ifc_alloc_memic_out_bits {
10619         u8         status[0x8];
10620         u8         reserved_at_8[0x18];
10621
10622         u8         syndrome[0x20];
10623
10624         u8         memic_start_addr[0x40];
10625 };
10626
10627 struct mlx5_ifc_dealloc_memic_in_bits {
10628         u8         opcode[0x10];
10629         u8         reserved_at_10[0x10];
10630
10631         u8         reserved_at_20[0x10];
10632         u8         op_mod[0x10];
10633
10634         u8         reserved_at_40[0x40];
10635
10636         u8         memic_start_addr[0x40];
10637
10638         u8         memic_size[0x20];
10639
10640         u8         reserved_at_e0[0x20];
10641 };
10642
10643 struct mlx5_ifc_dealloc_memic_out_bits {
10644         u8         status[0x8];
10645         u8         reserved_at_8[0x18];
10646
10647         u8         syndrome[0x20];
10648
10649         u8         reserved_at_40[0x40];
10650 };
10651
10652 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10653         u8         opcode[0x10];
10654         u8         uid[0x10];
10655
10656         u8         vhca_tunnel_id[0x10];
10657         u8         obj_type[0x10];
10658
10659         u8         obj_id[0x20];
10660
10661         u8         reserved_at_60[0x20];
10662 };
10663
10664 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10665         u8         status[0x8];
10666         u8         reserved_at_8[0x18];
10667
10668         u8         syndrome[0x20];
10669
10670         u8         obj_id[0x20];
10671
10672         u8         reserved_at_60[0x20];
10673 };
10674
10675 struct mlx5_ifc_umem_bits {
10676         u8         reserved_at_0[0x80];
10677
10678         u8         reserved_at_80[0x1b];
10679         u8         log_page_size[0x5];
10680
10681         u8         page_offset[0x20];
10682
10683         u8         num_of_mtt[0x40];
10684
10685         struct mlx5_ifc_mtt_bits  mtt[];
10686 };
10687
10688 struct mlx5_ifc_uctx_bits {
10689         u8         cap[0x20];
10690
10691         u8         reserved_at_20[0x160];
10692 };
10693
10694 struct mlx5_ifc_sw_icm_bits {
10695         u8         modify_field_select[0x40];
10696
10697         u8         reserved_at_40[0x18];
10698         u8         log_sw_icm_size[0x8];
10699
10700         u8         reserved_at_60[0x20];
10701
10702         u8         sw_icm_start_addr[0x40];
10703
10704         u8         reserved_at_c0[0x140];
10705 };
10706
10707 struct mlx5_ifc_geneve_tlv_option_bits {
10708         u8         modify_field_select[0x40];
10709
10710         u8         reserved_at_40[0x18];
10711         u8         geneve_option_fte_index[0x8];
10712
10713         u8         option_class[0x10];
10714         u8         option_type[0x8];
10715         u8         reserved_at_78[0x3];
10716         u8         option_data_length[0x5];
10717
10718         u8         reserved_at_80[0x180];
10719 };
10720
10721 struct mlx5_ifc_create_umem_in_bits {
10722         u8         opcode[0x10];
10723         u8         uid[0x10];
10724
10725         u8         reserved_at_20[0x10];
10726         u8         op_mod[0x10];
10727
10728         u8         reserved_at_40[0x40];
10729
10730         struct mlx5_ifc_umem_bits  umem;
10731 };
10732
10733 struct mlx5_ifc_create_umem_out_bits {
10734         u8         status[0x8];
10735         u8         reserved_at_8[0x18];
10736
10737         u8         syndrome[0x20];
10738
10739         u8         reserved_at_40[0x8];
10740         u8         umem_id[0x18];
10741
10742         u8         reserved_at_60[0x20];
10743 };
10744
10745 struct mlx5_ifc_destroy_umem_in_bits {
10746         u8        opcode[0x10];
10747         u8        uid[0x10];
10748
10749         u8        reserved_at_20[0x10];
10750         u8        op_mod[0x10];
10751
10752         u8        reserved_at_40[0x8];
10753         u8        umem_id[0x18];
10754
10755         u8        reserved_at_60[0x20];
10756 };
10757
10758 struct mlx5_ifc_destroy_umem_out_bits {
10759         u8        status[0x8];
10760         u8        reserved_at_8[0x18];
10761
10762         u8        syndrome[0x20];
10763
10764         u8        reserved_at_40[0x40];
10765 };
10766
10767 struct mlx5_ifc_create_uctx_in_bits {
10768         u8         opcode[0x10];
10769         u8         reserved_at_10[0x10];
10770
10771         u8         reserved_at_20[0x10];
10772         u8         op_mod[0x10];
10773
10774         u8         reserved_at_40[0x40];
10775
10776         struct mlx5_ifc_uctx_bits  uctx;
10777 };
10778
10779 struct mlx5_ifc_create_uctx_out_bits {
10780         u8         status[0x8];
10781         u8         reserved_at_8[0x18];
10782
10783         u8         syndrome[0x20];
10784
10785         u8         reserved_at_40[0x10];
10786         u8         uid[0x10];
10787
10788         u8         reserved_at_60[0x20];
10789 };
10790
10791 struct mlx5_ifc_destroy_uctx_in_bits {
10792         u8         opcode[0x10];
10793         u8         reserved_at_10[0x10];
10794
10795         u8         reserved_at_20[0x10];
10796         u8         op_mod[0x10];
10797
10798         u8         reserved_at_40[0x10];
10799         u8         uid[0x10];
10800
10801         u8         reserved_at_60[0x20];
10802 };
10803
10804 struct mlx5_ifc_destroy_uctx_out_bits {
10805         u8         status[0x8];
10806         u8         reserved_at_8[0x18];
10807
10808         u8         syndrome[0x20];
10809
10810         u8          reserved_at_40[0x40];
10811 };
10812
10813 struct mlx5_ifc_create_sw_icm_in_bits {
10814         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10815         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10816 };
10817
10818 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10819         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10820         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10821 };
10822
10823 struct mlx5_ifc_mtrc_string_db_param_bits {
10824         u8         string_db_base_address[0x20];
10825
10826         u8         reserved_at_20[0x8];
10827         u8         string_db_size[0x18];
10828 };
10829
10830 struct mlx5_ifc_mtrc_cap_bits {
10831         u8         trace_owner[0x1];
10832         u8         trace_to_memory[0x1];
10833         u8         reserved_at_2[0x4];
10834         u8         trc_ver[0x2];
10835         u8         reserved_at_8[0x14];
10836         u8         num_string_db[0x4];
10837
10838         u8         first_string_trace[0x8];
10839         u8         num_string_trace[0x8];
10840         u8         reserved_at_30[0x28];
10841
10842         u8         log_max_trace_buffer_size[0x8];
10843
10844         u8         reserved_at_60[0x20];
10845
10846         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10847
10848         u8         reserved_at_280[0x180];
10849 };
10850
10851 struct mlx5_ifc_mtrc_conf_bits {
10852         u8         reserved_at_0[0x1c];
10853         u8         trace_mode[0x4];
10854         u8         reserved_at_20[0x18];
10855         u8         log_trace_buffer_size[0x8];
10856         u8         trace_mkey[0x20];
10857         u8         reserved_at_60[0x3a0];
10858 };
10859
10860 struct mlx5_ifc_mtrc_stdb_bits {
10861         u8         string_db_index[0x4];
10862         u8         reserved_at_4[0x4];
10863         u8         read_size[0x18];
10864         u8         start_offset[0x20];
10865         u8         string_db_data[];
10866 };
10867
10868 struct mlx5_ifc_mtrc_ctrl_bits {
10869         u8         trace_status[0x2];
10870         u8         reserved_at_2[0x2];
10871         u8         arm_event[0x1];
10872         u8         reserved_at_5[0xb];
10873         u8         modify_field_select[0x10];
10874         u8         reserved_at_20[0x2b];
10875         u8         current_timestamp52_32[0x15];
10876         u8         current_timestamp31_0[0x20];
10877         u8         reserved_at_80[0x180];
10878 };
10879
10880 struct mlx5_ifc_host_params_context_bits {
10881         u8         host_number[0x8];
10882         u8         reserved_at_8[0x7];
10883         u8         host_pf_disabled[0x1];
10884         u8         host_num_of_vfs[0x10];
10885
10886         u8         host_total_vfs[0x10];
10887         u8         host_pci_bus[0x10];
10888
10889         u8         reserved_at_40[0x10];
10890         u8         host_pci_device[0x10];
10891
10892         u8         reserved_at_60[0x10];
10893         u8         host_pci_function[0x10];
10894
10895         u8         reserved_at_80[0x180];
10896 };
10897
10898 struct mlx5_ifc_query_esw_functions_in_bits {
10899         u8         opcode[0x10];
10900         u8         reserved_at_10[0x10];
10901
10902         u8         reserved_at_20[0x10];
10903         u8         op_mod[0x10];
10904
10905         u8         reserved_at_40[0x40];
10906 };
10907
10908 struct mlx5_ifc_query_esw_functions_out_bits {
10909         u8         status[0x8];
10910         u8         reserved_at_8[0x18];
10911
10912         u8         syndrome[0x20];
10913
10914         u8         reserved_at_40[0x40];
10915
10916         struct mlx5_ifc_host_params_context_bits host_params_context;
10917
10918         u8         reserved_at_280[0x180];
10919         u8         host_sf_enable[][0x40];
10920 };
10921
10922 struct mlx5_ifc_sf_partition_bits {
10923         u8         reserved_at_0[0x10];
10924         u8         log_num_sf[0x8];
10925         u8         log_sf_bar_size[0x8];
10926 };
10927
10928 struct mlx5_ifc_query_sf_partitions_out_bits {
10929         u8         status[0x8];
10930         u8         reserved_at_8[0x18];
10931
10932         u8         syndrome[0x20];
10933
10934         u8         reserved_at_40[0x18];
10935         u8         num_sf_partitions[0x8];
10936
10937         u8         reserved_at_60[0x20];
10938
10939         struct mlx5_ifc_sf_partition_bits sf_partition[];
10940 };
10941
10942 struct mlx5_ifc_query_sf_partitions_in_bits {
10943         u8         opcode[0x10];
10944         u8         reserved_at_10[0x10];
10945
10946         u8         reserved_at_20[0x10];
10947         u8         op_mod[0x10];
10948
10949         u8         reserved_at_40[0x40];
10950 };
10951
10952 struct mlx5_ifc_dealloc_sf_out_bits {
10953         u8         status[0x8];
10954         u8         reserved_at_8[0x18];
10955
10956         u8         syndrome[0x20];
10957
10958         u8         reserved_at_40[0x40];
10959 };
10960
10961 struct mlx5_ifc_dealloc_sf_in_bits {
10962         u8         opcode[0x10];
10963         u8         reserved_at_10[0x10];
10964
10965         u8         reserved_at_20[0x10];
10966         u8         op_mod[0x10];
10967
10968         u8         reserved_at_40[0x10];
10969         u8         function_id[0x10];
10970
10971         u8         reserved_at_60[0x20];
10972 };
10973
10974 struct mlx5_ifc_alloc_sf_out_bits {
10975         u8         status[0x8];
10976         u8         reserved_at_8[0x18];
10977
10978         u8         syndrome[0x20];
10979
10980         u8         reserved_at_40[0x40];
10981 };
10982
10983 struct mlx5_ifc_alloc_sf_in_bits {
10984         u8         opcode[0x10];
10985         u8         reserved_at_10[0x10];
10986
10987         u8         reserved_at_20[0x10];
10988         u8         op_mod[0x10];
10989
10990         u8         reserved_at_40[0x10];
10991         u8         function_id[0x10];
10992
10993         u8         reserved_at_60[0x20];
10994 };
10995
10996 struct mlx5_ifc_affiliated_event_header_bits {
10997         u8         reserved_at_0[0x10];
10998         u8         obj_type[0x10];
10999
11000         u8         obj_id[0x20];
11001 };
11002
11003 enum {
11004         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11005         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11006         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11007 };
11008
11009 enum {
11010         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11011         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11012         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11013 };
11014
11015 enum {
11016         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11017         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
11018         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
11019 };
11020
11021 struct mlx5_ifc_ipsec_obj_bits {
11022         u8         modify_field_select[0x40];
11023         u8         full_offload[0x1];
11024         u8         reserved_at_41[0x1];
11025         u8         esn_en[0x1];
11026         u8         esn_overlap[0x1];
11027         u8         reserved_at_44[0x2];
11028         u8         icv_length[0x2];
11029         u8         reserved_at_48[0x4];
11030         u8         aso_return_reg[0x4];
11031         u8         reserved_at_50[0x10];
11032
11033         u8         esn_msb[0x20];
11034
11035         u8         reserved_at_80[0x8];
11036         u8         dekn[0x18];
11037
11038         u8         salt[0x20];
11039
11040         u8         implicit_iv[0x40];
11041
11042         u8         reserved_at_100[0x700];
11043 };
11044
11045 struct mlx5_ifc_create_ipsec_obj_in_bits {
11046         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11047         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11048 };
11049
11050 enum {
11051         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11052         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11053 };
11054
11055 struct mlx5_ifc_query_ipsec_obj_out_bits {
11056         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11057         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11058 };
11059
11060 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11061         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11062         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11063 };
11064
11065 struct mlx5_ifc_encryption_key_obj_bits {
11066         u8         modify_field_select[0x40];
11067
11068         u8         reserved_at_40[0x14];
11069         u8         key_size[0x4];
11070         u8         reserved_at_58[0x4];
11071         u8         key_type[0x4];
11072
11073         u8         reserved_at_60[0x8];
11074         u8         pd[0x18];
11075
11076         u8         reserved_at_80[0x180];
11077         u8         key[8][0x20];
11078
11079         u8         reserved_at_300[0x500];
11080 };
11081
11082 struct mlx5_ifc_create_encryption_key_in_bits {
11083         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11084         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11085 };
11086
11087 struct mlx5_ifc_sampler_obj_bits {
11088         u8         modify_field_select[0x40];
11089
11090         u8         table_type[0x8];
11091         u8         level[0x8];
11092         u8         reserved_at_50[0xf];
11093         u8         ignore_flow_level[0x1];
11094
11095         u8         sample_ratio[0x20];
11096
11097         u8         reserved_at_80[0x8];
11098         u8         sample_table_id[0x18];
11099
11100         u8         reserved_at_a0[0x8];
11101         u8         default_table_id[0x18];
11102
11103         u8         sw_steering_icm_address_rx[0x40];
11104         u8         sw_steering_icm_address_tx[0x40];
11105
11106         u8         reserved_at_140[0xa0];
11107 };
11108
11109 struct mlx5_ifc_create_sampler_obj_in_bits {
11110         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11111         struct mlx5_ifc_sampler_obj_bits sampler_object;
11112 };
11113
11114 struct mlx5_ifc_query_sampler_obj_out_bits {
11115         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11116         struct mlx5_ifc_sampler_obj_bits sampler_object;
11117 };
11118
11119 enum {
11120         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11121         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11122 };
11123
11124 enum {
11125         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11126         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11127 };
11128
11129 struct mlx5_ifc_tls_static_params_bits {
11130         u8         const_2[0x2];
11131         u8         tls_version[0x4];
11132         u8         const_1[0x2];
11133         u8         reserved_at_8[0x14];
11134         u8         encryption_standard[0x4];
11135
11136         u8         reserved_at_20[0x20];
11137
11138         u8         initial_record_number[0x40];
11139
11140         u8         resync_tcp_sn[0x20];
11141
11142         u8         gcm_iv[0x20];
11143
11144         u8         implicit_iv[0x40];
11145
11146         u8         reserved_at_100[0x8];
11147         u8         dek_index[0x18];
11148
11149         u8         reserved_at_120[0xe0];
11150 };
11151
11152 struct mlx5_ifc_tls_progress_params_bits {
11153         u8         next_record_tcp_sn[0x20];
11154
11155         u8         hw_resync_tcp_sn[0x20];
11156
11157         u8         record_tracker_state[0x2];
11158         u8         auth_state[0x2];
11159         u8         reserved_at_44[0x4];
11160         u8         hw_offset_record_number[0x18];
11161 };
11162
11163 enum {
11164         MLX5_MTT_PERM_READ      = 1 << 0,
11165         MLX5_MTT_PERM_WRITE     = 1 << 1,
11166         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11167 };
11168
11169 #endif /* MLX5_IFC_H */