include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  97         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  98         MLX5_OBJ_TYPE_MKEY = 0xff01,
  99         MLX5_OBJ_TYPE_QP = 0xff02,
 100         MLX5_OBJ_TYPE_PSV = 0xff03,
 101         MLX5_OBJ_TYPE_RMP = 0xff04,
 102         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 103         MLX5_OBJ_TYPE_RQ = 0xff06,
 104         MLX5_OBJ_TYPE_SQ = 0xff07,
 105         MLX5_OBJ_TYPE_TIR = 0xff08,
 106         MLX5_OBJ_TYPE_TIS = 0xff09,
 107         MLX5_OBJ_TYPE_DCT = 0xff0a,
 108         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 109         MLX5_OBJ_TYPE_RQT = 0xff0e,
 110         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 111         MLX5_OBJ_TYPE_CQ = 0xff10,
 112 };
 113
 114 enum {
 115         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 116         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 117         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 118         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 119         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 120         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 121         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 122         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 123         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 124         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 125         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 126         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 127         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 128         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 129         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 130         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 131         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 132         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 133         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 134         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 135         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 136         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 137         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 138         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 139         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 140         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 141         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 142         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 143         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 144         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 145         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 146         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 147         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 148         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 149         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 150         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 151         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 152         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 153         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 154         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 155         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 156         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 157         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 158         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 159         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 160         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 161         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 162         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 163         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 164         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 165         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 166         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 167         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 168         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 169         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 170         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 171         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 172         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 173         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 174         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 175         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 176         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 177         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 178         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 179         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 180         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 181         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 182         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 183         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 184         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 185         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 186         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 187         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 188         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 189         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 190         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 191         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 192         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 193         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 194         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 195         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 196         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 197         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 198         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 199         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 200         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 201         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 202         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 203         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 204         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 205         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 206         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 207         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 208         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 209         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 210         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 211         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 212         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 213         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 214         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 215         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 216         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 217         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 218         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 219         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 220         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 221         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 222         MLX5_CMD_OP_NOP                           = 0x80d,
 223         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 224         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 225         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 226         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 227         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 228         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 229         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 230         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 231         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 232         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 233         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 234         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 235         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 236         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 237         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 238         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 239         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 240         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 241         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 242         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 243         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 244         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 245         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 246         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 247         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 248         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 249         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 250         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 251         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 252         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 253         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 254         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 255         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 256         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 257         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 258         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 259         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 260         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 261         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 262         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 263         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 264         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 265         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 266         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 267         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 268         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 269         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 270         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 271         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 272         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 273         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 274         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 275         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 276         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 277         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 278         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 279         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 280         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 281         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 282         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 283         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 284         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 285         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 286         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 287         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 288         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 289         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 290         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 291         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 292         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 293         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 294         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 295         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 296         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 297         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 298         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 299         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 300         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 301         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 302         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 303         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 304         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 305         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 306         MLX5_CMD_OP_MAX
 307 };
 308
 309 /* Valid range for general commands that don't work over an object */
 310 enum {
 311         MLX5_CMD_OP_GENERAL_START = 0xb00,
 312         MLX5_CMD_OP_GENERAL_END = 0xd00,
 313 };
 314
 315 struct mlx5_ifc_flow_table_fields_supported_bits {
 316         u8         outer_dmac[0x1];
 317         u8         outer_smac[0x1];
 318         u8         outer_ether_type[0x1];
 319         u8         outer_ip_version[0x1];
 320         u8         outer_first_prio[0x1];
 321         u8         outer_first_cfi[0x1];
 322         u8         outer_first_vid[0x1];
 323         u8         outer_ipv4_ttl[0x1];
 324         u8         outer_second_prio[0x1];
 325         u8         outer_second_cfi[0x1];
 326         u8         outer_second_vid[0x1];
 327         u8         reserved_at_b[0x1];
 328         u8         outer_sip[0x1];
 329         u8         outer_dip[0x1];
 330         u8         outer_frag[0x1];
 331         u8         outer_ip_protocol[0x1];
 332         u8         outer_ip_ecn[0x1];
 333         u8         outer_ip_dscp[0x1];
 334         u8         outer_udp_sport[0x1];
 335         u8         outer_udp_dport[0x1];
 336         u8         outer_tcp_sport[0x1];
 337         u8         outer_tcp_dport[0x1];
 338         u8         outer_tcp_flags[0x1];
 339         u8         outer_gre_protocol[0x1];
 340         u8         outer_gre_key[0x1];
 341         u8         outer_vxlan_vni[0x1];
 342         u8         outer_geneve_vni[0x1];
 343         u8         outer_geneve_oam[0x1];
 344         u8         outer_geneve_protocol_type[0x1];
 345         u8         outer_geneve_opt_len[0x1];
 346         u8         reserved_at_1e[0x1];
 347         u8         source_eswitch_port[0x1];
 348
 349         u8         inner_dmac[0x1];
 350         u8         inner_smac[0x1];
 351         u8         inner_ether_type[0x1];
 352         u8         inner_ip_version[0x1];
 353         u8         inner_first_prio[0x1];
 354         u8         inner_first_cfi[0x1];
 355         u8         inner_first_vid[0x1];
 356         u8         reserved_at_27[0x1];
 357         u8         inner_second_prio[0x1];
 358         u8         inner_second_cfi[0x1];
 359         u8         inner_second_vid[0x1];
 360         u8         reserved_at_2b[0x1];
 361         u8         inner_sip[0x1];
 362         u8         inner_dip[0x1];
 363         u8         inner_frag[0x1];
 364         u8         inner_ip_protocol[0x1];
 365         u8         inner_ip_ecn[0x1];
 366         u8         inner_ip_dscp[0x1];
 367         u8         inner_udp_sport[0x1];
 368         u8         inner_udp_dport[0x1];
 369         u8         inner_tcp_sport[0x1];
 370         u8         inner_tcp_dport[0x1];
 371         u8         inner_tcp_flags[0x1];
 372         u8         reserved_at_37[0x9];
 373
 374         u8         geneve_tlv_option_0_data[0x1];
 375         u8         reserved_at_41[0x4];
 376         u8         outer_first_mpls_over_udp[0x4];
 377         u8         outer_first_mpls_over_gre[0x4];
 378         u8         inner_first_mpls[0x4];
 379         u8         outer_first_mpls[0x4];
 380         u8         reserved_at_55[0x2];
 381         u8         outer_esp_spi[0x1];
 382         u8         reserved_at_58[0x2];
 383         u8         bth_dst_qp[0x1];
 384         u8         reserved_at_5b[0x5];
 385
 386         u8         reserved_at_60[0x18];
 387         u8         metadata_reg_c_7[0x1];
 388         u8         metadata_reg_c_6[0x1];
 389         u8         metadata_reg_c_5[0x1];
 390         u8         metadata_reg_c_4[0x1];
 391         u8         metadata_reg_c_3[0x1];
 392         u8         metadata_reg_c_2[0x1];
 393         u8         metadata_reg_c_1[0x1];
 394         u8         metadata_reg_c_0[0x1];
 395 };
 396
 397 struct mlx5_ifc_flow_table_prop_layout_bits {
 398         u8         ft_support[0x1];
 399         u8         reserved_at_1[0x1];
 400         u8         flow_counter[0x1];
 401         u8         flow_modify_en[0x1];
 402         u8         modify_root[0x1];
 403         u8         identified_miss_table_mode[0x1];
 404         u8         flow_table_modify[0x1];
 405         u8         reformat[0x1];
 406         u8         decap[0x1];
 407         u8         reserved_at_9[0x1];
 408         u8         pop_vlan[0x1];
 409         u8         push_vlan[0x1];
 410         u8         reserved_at_c[0x1];
 411         u8         pop_vlan_2[0x1];
 412         u8         push_vlan_2[0x1];
 413         u8         reformat_and_vlan_action[0x1];
 414         u8         reserved_at_10[0x1];
 415         u8         sw_owner[0x1];
 416         u8         reformat_l3_tunnel_to_l2[0x1];
 417         u8         reformat_l2_to_l3_tunnel[0x1];
 418         u8         reformat_and_modify_action[0x1];
 419         u8         ignore_flow_level[0x1];
 420         u8         reserved_at_16[0x1];
 421         u8         table_miss_action_domain[0x1];
 422         u8         termination_table[0x1];
 423         u8         reformat_and_fwd_to_table[0x1];
 424         u8         reserved_at_1a[0x2];
 425         u8         ipsec_encrypt[0x1];
 426         u8         ipsec_decrypt[0x1];
 427         u8         sw_owner_v2[0x1];
 428         u8         reserved_at_1f[0x1];
 429
 430         u8         termination_table_raw_traffic[0x1];
 431         u8         reserved_at_21[0x1];
 432         u8         log_max_ft_size[0x6];
 433         u8         log_max_modify_header_context[0x8];
 434         u8         max_modify_header_actions[0x8];
 435         u8         max_ft_level[0x8];
 436
 437         u8         reserved_at_40[0x20];
 438
 439         u8         reserved_at_60[0x2];
 440         u8         reformat_insert[0x1];
 441         u8         reformat_remove[0x1];
 442         u8         reserver_at_64[0x14];
 443         u8         log_max_ft_num[0x8];
 444
 445         u8         reserved_at_80[0x10];
 446         u8         log_max_flow_counter[0x8];
 447         u8         log_max_destination[0x8];
 448
 449         u8         reserved_at_a0[0x18];
 450         u8         log_max_flow[0x8];
 451
 452         u8         reserved_at_c0[0x40];
 453
 454         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 455
 456         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 457 };
 458
 459 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 460         u8         send[0x1];
 461         u8         receive[0x1];
 462         u8         write[0x1];
 463         u8         read[0x1];
 464         u8         atomic[0x1];
 465         u8         srq_receive[0x1];
 466         u8         reserved_at_6[0x1a];
 467 };
 468
 469 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 470         u8         smac_47_16[0x20];
 471
 472         u8         smac_15_0[0x10];
 473         u8         ethertype[0x10];
 474
 475         u8         dmac_47_16[0x20];
 476
 477         u8         dmac_15_0[0x10];
 478         u8         first_prio[0x3];
 479         u8         first_cfi[0x1];
 480         u8         first_vid[0xc];
 481
 482         u8         ip_protocol[0x8];
 483         u8         ip_dscp[0x6];
 484         u8         ip_ecn[0x2];
 485         u8         cvlan_tag[0x1];
 486         u8         svlan_tag[0x1];
 487         u8         frag[0x1];
 488         u8         ip_version[0x4];
 489         u8         tcp_flags[0x9];
 490
 491         u8         tcp_sport[0x10];
 492         u8         tcp_dport[0x10];
 493
 494         u8         reserved_at_c0[0x18];
 495         u8         ttl_hoplimit[0x8];
 496
 497         u8         udp_sport[0x10];
 498         u8         udp_dport[0x10];
 499
 500         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 501
 502         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 503 };
 504
 505 struct mlx5_ifc_nvgre_key_bits {
 506         u8 hi[0x18];
 507         u8 lo[0x8];
 508 };
 509
 510 union mlx5_ifc_gre_key_bits {
 511         struct mlx5_ifc_nvgre_key_bits nvgre;
 512         u8 key[0x20];
 513 };
 514
 515 struct mlx5_ifc_fte_match_set_misc_bits {
 516         u8         gre_c_present[0x1];
 517         u8         reserved_at_1[0x1];
 518         u8         gre_k_present[0x1];
 519         u8         gre_s_present[0x1];
 520         u8         source_vhca_port[0x4];
 521         u8         source_sqn[0x18];
 522
 523         u8         source_eswitch_owner_vhca_id[0x10];
 524         u8         source_port[0x10];
 525
 526         u8         outer_second_prio[0x3];
 527         u8         outer_second_cfi[0x1];
 528         u8         outer_second_vid[0xc];
 529         u8         inner_second_prio[0x3];
 530         u8         inner_second_cfi[0x1];
 531         u8         inner_second_vid[0xc];
 532
 533         u8         outer_second_cvlan_tag[0x1];
 534         u8         inner_second_cvlan_tag[0x1];
 535         u8         outer_second_svlan_tag[0x1];
 536         u8         inner_second_svlan_tag[0x1];
 537         u8         reserved_at_64[0xc];
 538         u8         gre_protocol[0x10];
 539
 540         union mlx5_ifc_gre_key_bits gre_key;
 541
 542         u8         vxlan_vni[0x18];
 543         u8         reserved_at_b8[0x8];
 544
 545         u8         geneve_vni[0x18];
 546         u8         reserved_at_d8[0x7];
 547         u8         geneve_oam[0x1];
 548
 549         u8         reserved_at_e0[0xc];
 550         u8         outer_ipv6_flow_label[0x14];
 551
 552         u8         reserved_at_100[0xc];
 553         u8         inner_ipv6_flow_label[0x14];
 554
 555         u8         reserved_at_120[0xa];
 556         u8         geneve_opt_len[0x6];
 557         u8         geneve_protocol_type[0x10];
 558
 559         u8         reserved_at_140[0x8];
 560         u8         bth_dst_qp[0x18];
 561         u8         reserved_at_160[0x20];
 562         u8         outer_esp_spi[0x20];
 563         u8         reserved_at_1a0[0x60];
 564 };
 565
 566 struct mlx5_ifc_fte_match_mpls_bits {
 567         u8         mpls_label[0x14];
 568         u8         mpls_exp[0x3];
 569         u8         mpls_s_bos[0x1];
 570         u8         mpls_ttl[0x8];
 571 };
 572
 573 struct mlx5_ifc_fte_match_set_misc2_bits {
 574         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 575
 576         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 577
 578         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 579
 580         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 581
 582         u8         metadata_reg_c_7[0x20];
 583
 584         u8         metadata_reg_c_6[0x20];
 585
 586         u8         metadata_reg_c_5[0x20];
 587
 588         u8         metadata_reg_c_4[0x20];
 589
 590         u8         metadata_reg_c_3[0x20];
 591
 592         u8         metadata_reg_c_2[0x20];
 593
 594         u8         metadata_reg_c_1[0x20];
 595
 596         u8         metadata_reg_c_0[0x20];
 597
 598         u8         metadata_reg_a[0x20];
 599
 600         u8         reserved_at_1a0[0x60];
 601 };
 602
 603 struct mlx5_ifc_fte_match_set_misc3_bits {
 604         u8         inner_tcp_seq_num[0x20];
 605
 606         u8         outer_tcp_seq_num[0x20];
 607
 608         u8         inner_tcp_ack_num[0x20];
 609
 610         u8         outer_tcp_ack_num[0x20];
 611
 612         u8         reserved_at_80[0x8];
 613         u8         outer_vxlan_gpe_vni[0x18];
 614
 615         u8         outer_vxlan_gpe_next_protocol[0x8];
 616         u8         outer_vxlan_gpe_flags[0x8];
 617         u8         reserved_at_b0[0x10];
 618
 619         u8         icmp_header_data[0x20];
 620
 621         u8         icmpv6_header_data[0x20];
 622
 623         u8         icmp_type[0x8];
 624         u8         icmp_code[0x8];
 625         u8         icmpv6_type[0x8];
 626         u8         icmpv6_code[0x8];
 627
 628         u8         geneve_tlv_option_0_data[0x20];
 629
 630         u8         gtpu_teid[0x20];
 631
 632         u8         gtpu_msg_type[0x8];
 633         u8         gtpu_msg_flags[0x8];
 634         u8         reserved_at_170[0x10];
 635
 636         u8         gtpu_dw_2[0x20];
 637
 638         u8         gtpu_first_ext_dw_0[0x20];
 639
 640         u8         gtpu_dw_0[0x20];
 641
 642         u8         reserved_at_1e0[0x20];
 643 };
 644
 645 struct mlx5_ifc_fte_match_set_misc4_bits {
 646         u8         prog_sample_field_value_0[0x20];
 647
 648         u8         prog_sample_field_id_0[0x20];
 649
 650         u8         prog_sample_field_value_1[0x20];
 651
 652         u8         prog_sample_field_id_1[0x20];
 653
 654         u8         prog_sample_field_value_2[0x20];
 655
 656         u8         prog_sample_field_id_2[0x20];
 657
 658         u8         prog_sample_field_value_3[0x20];
 659
 660         u8         prog_sample_field_id_3[0x20];
 661
 662         u8         reserved_at_100[0x100];
 663 };
 664
 665 struct mlx5_ifc_cmd_pas_bits {
 666         u8         pa_h[0x20];
 667
 668         u8         pa_l[0x14];
 669         u8         reserved_at_34[0xc];
 670 };
 671
 672 struct mlx5_ifc_uint64_bits {
 673         u8         hi[0x20];
 674
 675         u8         lo[0x20];
 676 };
 677
 678 enum {
 679         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 680         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 681         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 682         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 683         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 684         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 685         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 686         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 687         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 688         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 689 };
 690
 691 struct mlx5_ifc_ads_bits {
 692         u8         fl[0x1];
 693         u8         free_ar[0x1];
 694         u8         reserved_at_2[0xe];
 695         u8         pkey_index[0x10];
 696
 697         u8         reserved_at_20[0x8];
 698         u8         grh[0x1];
 699         u8         mlid[0x7];
 700         u8         rlid[0x10];
 701
 702         u8         ack_timeout[0x5];
 703         u8         reserved_at_45[0x3];
 704         u8         src_addr_index[0x8];
 705         u8         reserved_at_50[0x4];
 706         u8         stat_rate[0x4];
 707         u8         hop_limit[0x8];
 708
 709         u8         reserved_at_60[0x4];
 710         u8         tclass[0x8];
 711         u8         flow_label[0x14];
 712
 713         u8         rgid_rip[16][0x8];
 714
 715         u8         reserved_at_100[0x4];
 716         u8         f_dscp[0x1];
 717         u8         f_ecn[0x1];
 718         u8         reserved_at_106[0x1];
 719         u8         f_eth_prio[0x1];
 720         u8         ecn[0x2];
 721         u8         dscp[0x6];
 722         u8         udp_sport[0x10];
 723
 724         u8         dei_cfi[0x1];
 725         u8         eth_prio[0x3];
 726         u8         sl[0x4];
 727         u8         vhca_port_num[0x8];
 728         u8         rmac_47_32[0x10];
 729
 730         u8         rmac_31_0[0x20];
 731 };
 732
 733 struct mlx5_ifc_flow_table_nic_cap_bits {
 734         u8         nic_rx_multi_path_tirs[0x1];
 735         u8         nic_rx_multi_path_tirs_fts[0x1];
 736         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 737         u8         reserved_at_3[0x4];
 738         u8         sw_owner_reformat_supported[0x1];
 739         u8         reserved_at_8[0x18];
 740
 741         u8         encap_general_header[0x1];
 742         u8         reserved_at_21[0xa];
 743         u8         log_max_packet_reformat_context[0x5];
 744         u8         reserved_at_30[0x6];
 745         u8         max_encap_header_size[0xa];
 746         u8         reserved_at_40[0x1c0];
 747
 748         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 749
 750         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 757
 758         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 759
 760         u8         reserved_at_e00[0x1200];
 761
 762         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 763
 764         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 765
 766         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 767
 768         u8         reserved_at_20c0[0x5f40];
 769 };
 770
 771 struct mlx5_ifc_port_selection_cap_bits {
 772         u8         reserved_at_0[0x10];
 773         u8         port_select_flow_table[0x1];
 774         u8         reserved_at_11[0xf];
 775
 776         u8         reserved_at_20[0x1e0];
 777
 778         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 779
 780         u8         reserved_at_400[0x7c00];
 781 };
 782
 783 enum {
 784         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 785         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 786         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 787         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 788         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 789         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 790         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 791         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 792 };
 793
 794 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 795         u8      fdb_to_vport_reg_c_id[0x8];
 796         u8      reserved_at_8[0xd];
 797         u8      fdb_modify_header_fwd_to_table[0x1];
 798         u8      reserved_at_16[0x1];
 799         u8      flow_source[0x1];
 800         u8      reserved_at_18[0x2];
 801         u8      multi_fdb_encap[0x1];
 802         u8      egress_acl_forward_to_vport[0x1];
 803         u8      fdb_multi_path_to_table[0x1];
 804         u8      reserved_at_1d[0x3];
 805
 806         u8      reserved_at_20[0x1e0];
 807
 808         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 809
 810         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 811
 812         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 813
 814         u8      reserved_at_800[0x1000];
 815
 816         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 817
 818         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 819
 820         u8      sw_steering_uplink_icm_address_rx[0x40];
 821
 822         u8      sw_steering_uplink_icm_address_tx[0x40];
 823
 824         u8      reserved_at_1900[0x6700];
 825 };
 826
 827 enum {
 828         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 829         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 830 };
 831
 832 struct mlx5_ifc_e_switch_cap_bits {
 833         u8         vport_svlan_strip[0x1];
 834         u8         vport_cvlan_strip[0x1];
 835         u8         vport_svlan_insert[0x1];
 836         u8         vport_cvlan_insert_if_not_exist[0x1];
 837         u8         vport_cvlan_insert_overwrite[0x1];
 838         u8         reserved_at_5[0x2];
 839         u8         esw_shared_ingress_acl[0x1];
 840         u8         esw_uplink_ingress_acl[0x1];
 841         u8         root_ft_on_other_esw[0x1];
 842         u8         reserved_at_a[0xf];
 843         u8         esw_functions_changed[0x1];
 844         u8         reserved_at_1a[0x1];
 845         u8         ecpf_vport_exists[0x1];
 846         u8         counter_eswitch_affinity[0x1];
 847         u8         merged_eswitch[0x1];
 848         u8         nic_vport_node_guid_modify[0x1];
 849         u8         nic_vport_port_guid_modify[0x1];
 850
 851         u8         vxlan_encap_decap[0x1];
 852         u8         nvgre_encap_decap[0x1];
 853         u8         reserved_at_22[0x1];
 854         u8         log_max_fdb_encap_uplink[0x5];
 855         u8         reserved_at_21[0x3];
 856         u8         log_max_packet_reformat_context[0x5];
 857         u8         reserved_2b[0x6];
 858         u8         max_encap_header_size[0xa];
 859
 860         u8         reserved_at_40[0xb];
 861         u8         log_max_esw_sf[0x5];
 862         u8         esw_sf_base_id[0x10];
 863
 864         u8         reserved_at_60[0x7a0];
 865
 866 };
 867
 868 struct mlx5_ifc_qos_cap_bits {
 869         u8         packet_pacing[0x1];
 870         u8         esw_scheduling[0x1];
 871         u8         esw_bw_share[0x1];
 872         u8         esw_rate_limit[0x1];
 873         u8         reserved_at_4[0x1];
 874         u8         packet_pacing_burst_bound[0x1];
 875         u8         packet_pacing_typical_size[0x1];
 876         u8         reserved_at_7[0x1];
 877         u8         nic_sq_scheduling[0x1];
 878         u8         nic_bw_share[0x1];
 879         u8         nic_rate_limit[0x1];
 880         u8         packet_pacing_uid[0x1];
 881         u8         log_esw_max_sched_depth[0x4];
 882         u8         reserved_at_10[0x10];
 883
 884         u8         reserved_at_20[0xb];
 885         u8         log_max_qos_nic_queue_group[0x5];
 886         u8         reserved_at_30[0x10];
 887
 888         u8         packet_pacing_max_rate[0x20];
 889
 890         u8         packet_pacing_min_rate[0x20];
 891
 892         u8         reserved_at_80[0x10];
 893         u8         packet_pacing_rate_table_size[0x10];
 894
 895         u8         esw_element_type[0x10];
 896         u8         esw_tsar_type[0x10];
 897
 898         u8         reserved_at_c0[0x10];
 899         u8         max_qos_para_vport[0x10];
 900
 901         u8         max_tsar_bw_share[0x20];
 902
 903         u8         reserved_at_100[0x700];
 904 };
 905
 906 struct mlx5_ifc_debug_cap_bits {
 907         u8         core_dump_general[0x1];
 908         u8         core_dump_qp[0x1];
 909         u8         reserved_at_2[0x7];
 910         u8         resource_dump[0x1];
 911         u8         reserved_at_a[0x16];
 912
 913         u8         reserved_at_20[0x2];
 914         u8         stall_detect[0x1];
 915         u8         reserved_at_23[0x1d];
 916
 917         u8         reserved_at_40[0x7c0];
 918 };
 919
 920 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 921         u8         csum_cap[0x1];
 922         u8         vlan_cap[0x1];
 923         u8         lro_cap[0x1];
 924         u8         lro_psh_flag[0x1];
 925         u8         lro_time_stamp[0x1];
 926         u8         reserved_at_5[0x2];
 927         u8         wqe_vlan_insert[0x1];
 928         u8         self_lb_en_modifiable[0x1];
 929         u8         reserved_at_9[0x2];
 930         u8         max_lso_cap[0x5];
 931         u8         multi_pkt_send_wqe[0x2];
 932         u8         wqe_inline_mode[0x2];
 933         u8         rss_ind_tbl_cap[0x4];
 934         u8         reg_umr_sq[0x1];
 935         u8         scatter_fcs[0x1];
 936         u8         enhanced_multi_pkt_send_wqe[0x1];
 937         u8         tunnel_lso_const_out_ip_id[0x1];
 938         u8         tunnel_lro_gre[0x1];
 939         u8         tunnel_lro_vxlan[0x1];
 940         u8         tunnel_stateless_gre[0x1];
 941         u8         tunnel_stateless_vxlan[0x1];
 942
 943         u8         swp[0x1];
 944         u8         swp_csum[0x1];
 945         u8         swp_lso[0x1];
 946         u8         cqe_checksum_full[0x1];
 947         u8         tunnel_stateless_geneve_tx[0x1];
 948         u8         tunnel_stateless_mpls_over_udp[0x1];
 949         u8         tunnel_stateless_mpls_over_gre[0x1];
 950         u8         tunnel_stateless_vxlan_gpe[0x1];
 951         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 952         u8         tunnel_stateless_ip_over_ip[0x1];
 953         u8         insert_trailer[0x1];
 954         u8         reserved_at_2b[0x1];
 955         u8         tunnel_stateless_ip_over_ip_rx[0x1];
 956         u8         tunnel_stateless_ip_over_ip_tx[0x1];
 957         u8         reserved_at_2e[0x2];
 958         u8         max_vxlan_udp_ports[0x8];
 959         u8         reserved_at_38[0x6];
 960         u8         max_geneve_opt_len[0x1];
 961         u8         tunnel_stateless_geneve_rx[0x1];
 962
 963         u8         reserved_at_40[0x10];
 964         u8         lro_min_mss_size[0x10];
 965
 966         u8         reserved_at_60[0x120];
 967
 968         u8         lro_timer_supported_periods[4][0x20];
 969
 970         u8         reserved_at_200[0x600];
 971 };
 972
 973 enum {
 974         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
 975         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
 976         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
 977 };
 978
 979 struct mlx5_ifc_roce_cap_bits {
 980         u8         roce_apm[0x1];
 981         u8         reserved_at_1[0x3];
 982         u8         sw_r_roce_src_udp_port[0x1];
 983         u8         fl_rc_qp_when_roce_disabled[0x1];
 984         u8         fl_rc_qp_when_roce_enabled[0x1];
 985         u8         reserved_at_7[0x17];
 986         u8         qp_ts_format[0x2];
 987
 988         u8         reserved_at_20[0x60];
 989
 990         u8         reserved_at_80[0xc];
 991         u8         l3_type[0x4];
 992         u8         reserved_at_90[0x8];
 993         u8         roce_version[0x8];
 994
 995         u8         reserved_at_a0[0x10];
 996         u8         r_roce_dest_udp_port[0x10];
 997
 998         u8         r_roce_max_src_udp_port[0x10];
 999         u8         r_roce_min_src_udp_port[0x10];
1000
1001         u8         reserved_at_e0[0x10];
1002         u8         roce_address_table_size[0x10];
1003
1004         u8         reserved_at_100[0x700];
1005 };
1006
1007 struct mlx5_ifc_sync_steering_in_bits {
1008         u8         opcode[0x10];
1009         u8         uid[0x10];
1010
1011         u8         reserved_at_20[0x10];
1012         u8         op_mod[0x10];
1013
1014         u8         reserved_at_40[0xc0];
1015 };
1016
1017 struct mlx5_ifc_sync_steering_out_bits {
1018         u8         status[0x8];
1019         u8         reserved_at_8[0x18];
1020
1021         u8         syndrome[0x20];
1022
1023         u8         reserved_at_40[0x40];
1024 };
1025
1026 struct mlx5_ifc_device_mem_cap_bits {
1027         u8         memic[0x1];
1028         u8         reserved_at_1[0x1f];
1029
1030         u8         reserved_at_20[0xb];
1031         u8         log_min_memic_alloc_size[0x5];
1032         u8         reserved_at_30[0x8];
1033         u8         log_max_memic_addr_alignment[0x8];
1034
1035         u8         memic_bar_start_addr[0x40];
1036
1037         u8         memic_bar_size[0x20];
1038
1039         u8         max_memic_size[0x20];
1040
1041         u8         steering_sw_icm_start_address[0x40];
1042
1043         u8         reserved_at_100[0x8];
1044         u8         log_header_modify_sw_icm_size[0x8];
1045         u8         reserved_at_110[0x2];
1046         u8         log_sw_icm_alloc_granularity[0x6];
1047         u8         log_steering_sw_icm_size[0x8];
1048
1049         u8         reserved_at_120[0x20];
1050
1051         u8         header_modify_sw_icm_start_address[0x40];
1052
1053         u8         reserved_at_180[0x80];
1054
1055         u8         memic_operations[0x20];
1056
1057         u8         reserved_at_220[0x5e0];
1058 };
1059
1060 struct mlx5_ifc_device_event_cap_bits {
1061         u8         user_affiliated_events[4][0x40];
1062
1063         u8         user_unaffiliated_events[4][0x40];
1064 };
1065
1066 struct mlx5_ifc_virtio_emulation_cap_bits {
1067         u8         desc_tunnel_offload_type[0x1];
1068         u8         eth_frame_offload_type[0x1];
1069         u8         virtio_version_1_0[0x1];
1070         u8         device_features_bits_mask[0xd];
1071         u8         event_mode[0x8];
1072         u8         virtio_queue_type[0x8];
1073
1074         u8         max_tunnel_desc[0x10];
1075         u8         reserved_at_30[0x3];
1076         u8         log_doorbell_stride[0x5];
1077         u8         reserved_at_38[0x3];
1078         u8         log_doorbell_bar_size[0x5];
1079
1080         u8         doorbell_bar_offset[0x40];
1081
1082         u8         max_emulated_devices[0x8];
1083         u8         max_num_virtio_queues[0x18];
1084
1085         u8         reserved_at_a0[0x60];
1086
1087         u8         umem_1_buffer_param_a[0x20];
1088
1089         u8         umem_1_buffer_param_b[0x20];
1090
1091         u8         umem_2_buffer_param_a[0x20];
1092
1093         u8         umem_2_buffer_param_b[0x20];
1094
1095         u8         umem_3_buffer_param_a[0x20];
1096
1097         u8         umem_3_buffer_param_b[0x20];
1098
1099         u8         reserved_at_1c0[0x640];
1100 };
1101
1102 enum {
1103         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1104         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1105         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1106         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1107         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1108         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1109         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1110         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1111         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1112 };
1113
1114 enum {
1115         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1116         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1117         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1118         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1119         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1120         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1121         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1122         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1123         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1124 };
1125
1126 struct mlx5_ifc_atomic_caps_bits {
1127         u8         reserved_at_0[0x40];
1128
1129         u8         atomic_req_8B_endianness_mode[0x2];
1130         u8         reserved_at_42[0x4];
1131         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1132
1133         u8         reserved_at_47[0x19];
1134
1135         u8         reserved_at_60[0x20];
1136
1137         u8         reserved_at_80[0x10];
1138         u8         atomic_operations[0x10];
1139
1140         u8         reserved_at_a0[0x10];
1141         u8         atomic_size_qp[0x10];
1142
1143         u8         reserved_at_c0[0x10];
1144         u8         atomic_size_dc[0x10];
1145
1146         u8         reserved_at_e0[0x720];
1147 };
1148
1149 struct mlx5_ifc_odp_cap_bits {
1150         u8         reserved_at_0[0x40];
1151
1152         u8         sig[0x1];
1153         u8         reserved_at_41[0x1f];
1154
1155         u8         reserved_at_60[0x20];
1156
1157         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1158
1159         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1160
1161         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1162
1163         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1164
1165         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1166
1167         u8         reserved_at_120[0x6E0];
1168 };
1169
1170 struct mlx5_ifc_calc_op {
1171         u8        reserved_at_0[0x10];
1172         u8        reserved_at_10[0x9];
1173         u8        op_swap_endianness[0x1];
1174         u8        op_min[0x1];
1175         u8        op_xor[0x1];
1176         u8        op_or[0x1];
1177         u8        op_and[0x1];
1178         u8        op_max[0x1];
1179         u8        op_add[0x1];
1180 };
1181
1182 struct mlx5_ifc_vector_calc_cap_bits {
1183         u8         calc_matrix[0x1];
1184         u8         reserved_at_1[0x1f];
1185         u8         reserved_at_20[0x8];
1186         u8         max_vec_count[0x8];
1187         u8         reserved_at_30[0xd];
1188         u8         max_chunk_size[0x3];
1189         struct mlx5_ifc_calc_op calc0;
1190         struct mlx5_ifc_calc_op calc1;
1191         struct mlx5_ifc_calc_op calc2;
1192         struct mlx5_ifc_calc_op calc3;
1193
1194         u8         reserved_at_c0[0x720];
1195 };
1196
1197 struct mlx5_ifc_tls_cap_bits {
1198         u8         tls_1_2_aes_gcm_128[0x1];
1199         u8         tls_1_3_aes_gcm_128[0x1];
1200         u8         tls_1_2_aes_gcm_256[0x1];
1201         u8         tls_1_3_aes_gcm_256[0x1];
1202         u8         reserved_at_4[0x1c];
1203
1204         u8         reserved_at_20[0x7e0];
1205 };
1206
1207 struct mlx5_ifc_ipsec_cap_bits {
1208         u8         ipsec_full_offload[0x1];
1209         u8         ipsec_crypto_offload[0x1];
1210         u8         ipsec_esn[0x1];
1211         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1212         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1213         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1214         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1215         u8         reserved_at_7[0x4];
1216         u8         log_max_ipsec_offload[0x5];
1217         u8         reserved_at_10[0x10];
1218
1219         u8         min_log_ipsec_full_replay_window[0x8];
1220         u8         max_log_ipsec_full_replay_window[0x8];
1221         u8         reserved_at_30[0x7d0];
1222 };
1223
1224 enum {
1225         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1226         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1227         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1228         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1229 };
1230
1231 enum {
1232         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1233         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1234 };
1235
1236 enum {
1237         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1238         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1239         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1240         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1241         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1242 };
1243
1244 enum {
1245         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1246         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1247         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1248         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1249         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1250         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1251 };
1252
1253 enum {
1254         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1255         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1256 };
1257
1258 enum {
1259         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1260         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1261         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1262 };
1263
1264 enum {
1265         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1266         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1267 };
1268
1269 enum {
1270         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1271         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1272         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1273 };
1274
1275 enum {
1276         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1277         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1278         mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1279         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1280         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1281         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1282         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1283         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1284         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1285         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1286         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1287         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1288 };
1289
1290 enum {
1291         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1292         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1293 };
1294
1295 #define MLX5_FC_BULK_SIZE_FACTOR 128
1296
1297 enum mlx5_fc_bulk_alloc_bitmask {
1298         MLX5_FC_BULK_128   = (1 << 0),
1299         MLX5_FC_BULK_256   = (1 << 1),
1300         MLX5_FC_BULK_512   = (1 << 2),
1301         MLX5_FC_BULK_1024  = (1 << 3),
1302         MLX5_FC_BULK_2048  = (1 << 4),
1303         MLX5_FC_BULK_4096  = (1 << 5),
1304         MLX5_FC_BULK_8192  = (1 << 6),
1305         MLX5_FC_BULK_16384 = (1 << 7),
1306 };
1307
1308 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1309
1310 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1311
1312 enum {
1313         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1314         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1315 };
1316
1317 struct mlx5_ifc_cmd_hca_cap_bits {
1318         u8         reserved_at_0[0x1f];
1319         u8         vhca_resource_manager[0x1];
1320
1321         u8         hca_cap_2[0x1];
1322         u8         reserved_at_21[0x1];
1323         u8         dtor[0x1];
1324         u8         event_on_vhca_state_teardown_request[0x1];
1325         u8         event_on_vhca_state_in_use[0x1];
1326         u8         event_on_vhca_state_active[0x1];
1327         u8         event_on_vhca_state_allocated[0x1];
1328         u8         event_on_vhca_state_invalid[0x1];
1329         u8         reserved_at_28[0x8];
1330         u8         vhca_id[0x10];
1331
1332         u8         reserved_at_40[0x40];
1333
1334         u8         log_max_srq_sz[0x8];
1335         u8         log_max_qp_sz[0x8];
1336         u8         event_cap[0x1];
1337         u8         reserved_at_91[0x2];
1338         u8         isolate_vl_tc_new[0x1];
1339         u8         reserved_at_94[0x4];
1340         u8         prio_tag_required[0x1];
1341         u8         reserved_at_99[0x2];
1342         u8         log_max_qp[0x5];
1343
1344         u8         reserved_at_a0[0x3];
1345         u8         ece_support[0x1];
1346         u8         reserved_at_a4[0x5];
1347         u8         reg_c_preserve[0x1];
1348         u8         reserved_at_aa[0x1];
1349         u8         log_max_srq[0x5];
1350         u8         reserved_at_b0[0x1];
1351         u8         uplink_follow[0x1];
1352         u8         ts_cqe_to_dest_cqn[0x1];
1353         u8         reserved_at_b3[0xd];
1354
1355         u8         max_sgl_for_optimized_performance[0x8];
1356         u8         log_max_cq_sz[0x8];
1357         u8         relaxed_ordering_write_umr[0x1];
1358         u8         relaxed_ordering_read_umr[0x1];
1359         u8         reserved_at_d2[0x7];
1360         u8         virtio_net_device_emualtion_manager[0x1];
1361         u8         virtio_blk_device_emualtion_manager[0x1];
1362         u8         log_max_cq[0x5];
1363
1364         u8         log_max_eq_sz[0x8];
1365         u8         relaxed_ordering_write[0x1];
1366         u8         relaxed_ordering_read[0x1];
1367         u8         log_max_mkey[0x6];
1368         u8         reserved_at_f0[0x8];
1369         u8         dump_fill_mkey[0x1];
1370         u8         reserved_at_f9[0x2];
1371         u8         fast_teardown[0x1];
1372         u8         log_max_eq[0x4];
1373
1374         u8         max_indirection[0x8];
1375         u8         fixed_buffer_size[0x1];
1376         u8         log_max_mrw_sz[0x7];
1377         u8         force_teardown[0x1];
1378         u8         reserved_at_111[0x1];
1379         u8         log_max_bsf_list_size[0x6];
1380         u8         umr_extended_translation_offset[0x1];
1381         u8         null_mkey[0x1];
1382         u8         log_max_klm_list_size[0x6];
1383
1384         u8         reserved_at_120[0xa];
1385         u8         log_max_ra_req_dc[0x6];
1386         u8         reserved_at_130[0xa];
1387         u8         log_max_ra_res_dc[0x6];
1388
1389         u8         reserved_at_140[0x6];
1390         u8         release_all_pages[0x1];
1391         u8         reserved_at_147[0x2];
1392         u8         roce_accl[0x1];
1393         u8         log_max_ra_req_qp[0x6];
1394         u8         reserved_at_150[0xa];
1395         u8         log_max_ra_res_qp[0x6];
1396
1397         u8         end_pad[0x1];
1398         u8         cc_query_allowed[0x1];
1399         u8         cc_modify_allowed[0x1];
1400         u8         start_pad[0x1];
1401         u8         cache_line_128byte[0x1];
1402         u8         reserved_at_165[0x4];
1403         u8         rts2rts_qp_counters_set_id[0x1];
1404         u8         reserved_at_16a[0x2];
1405         u8         vnic_env_int_rq_oob[0x1];
1406         u8         sbcam_reg[0x1];
1407         u8         reserved_at_16e[0x1];
1408         u8         qcam_reg[0x1];
1409         u8         gid_table_size[0x10];
1410
1411         u8         out_of_seq_cnt[0x1];
1412         u8         vport_counters[0x1];
1413         u8         retransmission_q_counters[0x1];
1414         u8         debug[0x1];
1415         u8         modify_rq_counter_set_id[0x1];
1416         u8         rq_delay_drop[0x1];
1417         u8         max_qp_cnt[0xa];
1418         u8         pkey_table_size[0x10];
1419
1420         u8         vport_group_manager[0x1];
1421         u8         vhca_group_manager[0x1];
1422         u8         ib_virt[0x1];
1423         u8         eth_virt[0x1];
1424         u8         vnic_env_queue_counters[0x1];
1425         u8         ets[0x1];
1426         u8         nic_flow_table[0x1];
1427         u8         eswitch_manager[0x1];
1428         u8         device_memory[0x1];
1429         u8         mcam_reg[0x1];
1430         u8         pcam_reg[0x1];
1431         u8         local_ca_ack_delay[0x5];
1432         u8         port_module_event[0x1];
1433         u8         enhanced_error_q_counters[0x1];
1434         u8         ports_check[0x1];
1435         u8         reserved_at_1b3[0x1];
1436         u8         disable_link_up[0x1];
1437         u8         beacon_led[0x1];
1438         u8         port_type[0x2];
1439         u8         num_ports[0x8];
1440
1441         u8         reserved_at_1c0[0x1];
1442         u8         pps[0x1];
1443         u8         pps_modify[0x1];
1444         u8         log_max_msg[0x5];
1445         u8         reserved_at_1c8[0x4];
1446         u8         max_tc[0x4];
1447         u8         temp_warn_event[0x1];
1448         u8         dcbx[0x1];
1449         u8         general_notification_event[0x1];
1450         u8         reserved_at_1d3[0x2];
1451         u8         fpga[0x1];
1452         u8         rol_s[0x1];
1453         u8         rol_g[0x1];
1454         u8         reserved_at_1d8[0x1];
1455         u8         wol_s[0x1];
1456         u8         wol_g[0x1];
1457         u8         wol_a[0x1];
1458         u8         wol_b[0x1];
1459         u8         wol_m[0x1];
1460         u8         wol_u[0x1];
1461         u8         wol_p[0x1];
1462
1463         u8         stat_rate_support[0x10];
1464         u8         reserved_at_1f0[0x1];
1465         u8         pci_sync_for_fw_update_event[0x1];
1466         u8         reserved_at_1f2[0x6];
1467         u8         init2_lag_tx_port_affinity[0x1];
1468         u8         reserved_at_1fa[0x3];
1469         u8         cqe_version[0x4];
1470
1471         u8         compact_address_vector[0x1];
1472         u8         striding_rq[0x1];
1473         u8         reserved_at_202[0x1];
1474         u8         ipoib_enhanced_offloads[0x1];
1475         u8         ipoib_basic_offloads[0x1];
1476         u8         reserved_at_205[0x1];
1477         u8         repeated_block_disabled[0x1];
1478         u8         umr_modify_entity_size_disabled[0x1];
1479         u8         umr_modify_atomic_disabled[0x1];
1480         u8         umr_indirect_mkey_disabled[0x1];
1481         u8         umr_fence[0x2];
1482         u8         dc_req_scat_data_cqe[0x1];
1483         u8         reserved_at_20d[0x2];
1484         u8         drain_sigerr[0x1];
1485         u8         cmdif_checksum[0x2];
1486         u8         sigerr_cqe[0x1];
1487         u8         reserved_at_213[0x1];
1488         u8         wq_signature[0x1];
1489         u8         sctr_data_cqe[0x1];
1490         u8         reserved_at_216[0x1];
1491         u8         sho[0x1];
1492         u8         tph[0x1];
1493         u8         rf[0x1];
1494         u8         dct[0x1];
1495         u8         qos[0x1];
1496         u8         eth_net_offloads[0x1];
1497         u8         roce[0x1];
1498         u8         atomic[0x1];
1499         u8         reserved_at_21f[0x1];
1500
1501         u8         cq_oi[0x1];
1502         u8         cq_resize[0x1];
1503         u8         cq_moderation[0x1];
1504         u8         reserved_at_223[0x3];
1505         u8         cq_eq_remap[0x1];
1506         u8         pg[0x1];
1507         u8         block_lb_mc[0x1];
1508         u8         reserved_at_229[0x1];
1509         u8         scqe_break_moderation[0x1];
1510         u8         cq_period_start_from_cqe[0x1];
1511         u8         cd[0x1];
1512         u8         reserved_at_22d[0x1];
1513         u8         apm[0x1];
1514         u8         vector_calc[0x1];
1515         u8         umr_ptr_rlky[0x1];
1516         u8         imaicl[0x1];
1517         u8         qp_packet_based[0x1];
1518         u8         reserved_at_233[0x3];
1519         u8         qkv[0x1];
1520         u8         pkv[0x1];
1521         u8         set_deth_sqpn[0x1];
1522         u8         reserved_at_239[0x3];
1523         u8         xrc[0x1];
1524         u8         ud[0x1];
1525         u8         uc[0x1];
1526         u8         rc[0x1];
1527
1528         u8         uar_4k[0x1];
1529         u8         reserved_at_241[0x9];
1530         u8         uar_sz[0x6];
1531         u8         port_selection_cap[0x1];
1532         u8         reserved_at_248[0x1];
1533         u8         umem_uid_0[0x1];
1534         u8         reserved_at_250[0x5];
1535         u8         log_pg_sz[0x8];
1536
1537         u8         bf[0x1];
1538         u8         driver_version[0x1];
1539         u8         pad_tx_eth_packet[0x1];
1540         u8         reserved_at_263[0x3];
1541         u8         mkey_by_name[0x1];
1542         u8         reserved_at_267[0x4];
1543
1544         u8         log_bf_reg_size[0x5];
1545
1546         u8         reserved_at_270[0x6];
1547         u8         lag_dct[0x2];
1548         u8         lag_tx_port_affinity[0x1];
1549         u8         lag_native_fdb_selection[0x1];
1550         u8         reserved_at_27a[0x1];
1551         u8         lag_master[0x1];
1552         u8         num_lag_ports[0x4];
1553
1554         u8         reserved_at_280[0x10];
1555         u8         max_wqe_sz_sq[0x10];
1556
1557         u8         reserved_at_2a0[0x10];
1558         u8         max_wqe_sz_rq[0x10];
1559
1560         u8         max_flow_counter_31_16[0x10];
1561         u8         max_wqe_sz_sq_dc[0x10];
1562
1563         u8         reserved_at_2e0[0x7];
1564         u8         max_qp_mcg[0x19];
1565
1566         u8         reserved_at_300[0x10];
1567         u8         flow_counter_bulk_alloc[0x8];
1568         u8         log_max_mcg[0x8];
1569
1570         u8         reserved_at_320[0x3];
1571         u8         log_max_transport_domain[0x5];
1572         u8         reserved_at_328[0x3];
1573         u8         log_max_pd[0x5];
1574         u8         reserved_at_330[0xb];
1575         u8         log_max_xrcd[0x5];
1576
1577         u8         nic_receive_steering_discard[0x1];
1578         u8         receive_discard_vport_down[0x1];
1579         u8         transmit_discard_vport_down[0x1];
1580         u8         reserved_at_343[0x5];
1581         u8         log_max_flow_counter_bulk[0x8];
1582         u8         max_flow_counter_15_0[0x10];
1583
1584
1585         u8         reserved_at_360[0x3];
1586         u8         log_max_rq[0x5];
1587         u8         reserved_at_368[0x3];
1588         u8         log_max_sq[0x5];
1589         u8         reserved_at_370[0x3];
1590         u8         log_max_tir[0x5];
1591         u8         reserved_at_378[0x3];
1592         u8         log_max_tis[0x5];
1593
1594         u8         basic_cyclic_rcv_wqe[0x1];
1595         u8         reserved_at_381[0x2];
1596         u8         log_max_rmp[0x5];
1597         u8         reserved_at_388[0x3];
1598         u8         log_max_rqt[0x5];
1599         u8         reserved_at_390[0x3];
1600         u8         log_max_rqt_size[0x5];
1601         u8         reserved_at_398[0x3];
1602         u8         log_max_tis_per_sq[0x5];
1603
1604         u8         ext_stride_num_range[0x1];
1605         u8         roce_rw_supported[0x1];
1606         u8         reserved_at_3a2[0x1];
1607         u8         log_max_stride_sz_rq[0x5];
1608         u8         reserved_at_3a8[0x3];
1609         u8         log_min_stride_sz_rq[0x5];
1610         u8         reserved_at_3b0[0x3];
1611         u8         log_max_stride_sz_sq[0x5];
1612         u8         reserved_at_3b8[0x3];
1613         u8         log_min_stride_sz_sq[0x5];
1614
1615         u8         hairpin[0x1];
1616         u8         reserved_at_3c1[0x2];
1617         u8         log_max_hairpin_queues[0x5];
1618         u8         reserved_at_3c8[0x3];
1619         u8         log_max_hairpin_wq_data_sz[0x5];
1620         u8         reserved_at_3d0[0x3];
1621         u8         log_max_hairpin_num_packets[0x5];
1622         u8         reserved_at_3d8[0x3];
1623         u8         log_max_wq_sz[0x5];
1624
1625         u8         nic_vport_change_event[0x1];
1626         u8         disable_local_lb_uc[0x1];
1627         u8         disable_local_lb_mc[0x1];
1628         u8         log_min_hairpin_wq_data_sz[0x5];
1629         u8         reserved_at_3e8[0x2];
1630         u8         vhca_state[0x1];
1631         u8         log_max_vlan_list[0x5];
1632         u8         reserved_at_3f0[0x3];
1633         u8         log_max_current_mc_list[0x5];
1634         u8         reserved_at_3f8[0x3];
1635         u8         log_max_current_uc_list[0x5];
1636
1637         u8         general_obj_types[0x40];
1638
1639         u8         sq_ts_format[0x2];
1640         u8         rq_ts_format[0x2];
1641         u8         steering_format_version[0x4];
1642         u8         create_qp_start_hint[0x18];
1643
1644         u8         reserved_at_460[0x3];
1645         u8         log_max_uctx[0x5];
1646         u8         reserved_at_468[0x2];
1647         u8         ipsec_offload[0x1];
1648         u8         log_max_umem[0x5];
1649         u8         max_num_eqs[0x10];
1650
1651         u8         reserved_at_480[0x1];
1652         u8         tls_tx[0x1];
1653         u8         tls_rx[0x1];
1654         u8         log_max_l2_table[0x5];
1655         u8         reserved_at_488[0x8];
1656         u8         log_uar_page_sz[0x10];
1657
1658         u8         reserved_at_4a0[0x20];
1659         u8         device_frequency_mhz[0x20];
1660         u8         device_frequency_khz[0x20];
1661
1662         u8         reserved_at_500[0x20];
1663         u8         num_of_uars_per_page[0x20];
1664
1665         u8         flex_parser_protocols[0x20];
1666
1667         u8         max_geneve_tlv_options[0x8];
1668         u8         reserved_at_568[0x3];
1669         u8         max_geneve_tlv_option_data_len[0x5];
1670         u8         reserved_at_570[0x10];
1671
1672         u8         reserved_at_580[0xb];
1673         u8         log_max_dci_stream_channels[0x5];
1674         u8         reserved_at_590[0x3];
1675         u8         log_max_dci_errored_streams[0x5];
1676         u8         reserved_at_598[0x8];
1677
1678         u8         reserved_at_5a0[0x13];
1679         u8         log_max_dek[0x5];
1680         u8         reserved_at_5b8[0x4];
1681         u8         mini_cqe_resp_stride_index[0x1];
1682         u8         cqe_128_always[0x1];
1683         u8         cqe_compression_128[0x1];
1684         u8         cqe_compression[0x1];
1685
1686         u8         cqe_compression_timeout[0x10];
1687         u8         cqe_compression_max_num[0x10];
1688
1689         u8         reserved_at_5e0[0x8];
1690         u8         flex_parser_id_gtpu_dw_0[0x4];
1691         u8         reserved_at_5ec[0x4];
1692         u8         tag_matching[0x1];
1693         u8         rndv_offload_rc[0x1];
1694         u8         rndv_offload_dc[0x1];
1695         u8         log_tag_matching_list_sz[0x5];
1696         u8         reserved_at_5f8[0x3];
1697         u8         log_max_xrq[0x5];
1698
1699         u8         affiliate_nic_vport_criteria[0x8];
1700         u8         native_port_num[0x8];
1701         u8         num_vhca_ports[0x8];
1702         u8         flex_parser_id_gtpu_teid[0x4];
1703         u8         reserved_at_61c[0x2];
1704         u8         sw_owner_id[0x1];
1705         u8         reserved_at_61f[0x1];
1706
1707         u8         max_num_of_monitor_counters[0x10];
1708         u8         num_ppcnt_monitor_counters[0x10];
1709
1710         u8         max_num_sf[0x10];
1711         u8         num_q_monitor_counters[0x10];
1712
1713         u8         reserved_at_660[0x20];
1714
1715         u8         sf[0x1];
1716         u8         sf_set_partition[0x1];
1717         u8         reserved_at_682[0x1];
1718         u8         log_max_sf[0x5];
1719         u8         apu[0x1];
1720         u8         reserved_at_689[0x7];
1721         u8         log_min_sf_size[0x8];
1722         u8         max_num_sf_partitions[0x8];
1723
1724         u8         uctx_cap[0x20];
1725
1726         u8         reserved_at_6c0[0x4];
1727         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1728         u8         flex_parser_id_icmp_dw1[0x4];
1729         u8         flex_parser_id_icmp_dw0[0x4];
1730         u8         flex_parser_id_icmpv6_dw1[0x4];
1731         u8         flex_parser_id_icmpv6_dw0[0x4];
1732         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1733         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1734
1735         u8         max_num_match_definer[0x10];
1736         u8         sf_base_id[0x10];
1737
1738         u8         flex_parser_id_gtpu_dw_2[0x4];
1739         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1740         u8         num_total_dynamic_vf_msix[0x18];
1741         u8         reserved_at_720[0x14];
1742         u8         dynamic_msix_table_size[0xc];
1743         u8         reserved_at_740[0xc];
1744         u8         min_dynamic_vf_msix_table_size[0x4];
1745         u8         reserved_at_750[0x4];
1746         u8         max_dynamic_vf_msix_table_size[0xc];
1747
1748         u8         reserved_at_760[0x20];
1749         u8         vhca_tunnel_commands[0x40];
1750         u8         match_definer_format_supported[0x40];
1751 };
1752
1753 struct mlx5_ifc_cmd_hca_cap_2_bits {
1754         u8         reserved_at_0[0xa0];
1755
1756         u8         max_reformat_insert_size[0x8];
1757         u8         max_reformat_insert_offset[0x8];
1758         u8         max_reformat_remove_size[0x8];
1759         u8         max_reformat_remove_offset[0x8];
1760
1761         u8         reserved_at_c0[0x740];
1762 };
1763
1764 enum mlx5_flow_destination_type {
1765         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1766         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1767         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1768         MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1769
1770         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1771         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1772         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1773 };
1774
1775 enum mlx5_flow_table_miss_action {
1776         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1777         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1778         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1779 };
1780
1781 struct mlx5_ifc_dest_format_struct_bits {
1782         u8         destination_type[0x8];
1783         u8         destination_id[0x18];
1784
1785         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1786         u8         packet_reformat[0x1];
1787         u8         reserved_at_22[0xe];
1788         u8         destination_eswitch_owner_vhca_id[0x10];
1789 };
1790
1791 struct mlx5_ifc_flow_counter_list_bits {
1792         u8         flow_counter_id[0x20];
1793
1794         u8         reserved_at_20[0x20];
1795 };
1796
1797 struct mlx5_ifc_extended_dest_format_bits {
1798         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1799
1800         u8         packet_reformat_id[0x20];
1801
1802         u8         reserved_at_60[0x20];
1803 };
1804
1805 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1806         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1807         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1808 };
1809
1810 struct mlx5_ifc_fte_match_param_bits {
1811         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1812
1813         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1814
1815         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1816
1817         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1818
1819         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1820
1821         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1822
1823         u8         reserved_at_c00[0x400];
1824 };
1825
1826 enum {
1827         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1828         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1829         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1830         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1831         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1832 };
1833
1834 struct mlx5_ifc_rx_hash_field_select_bits {
1835         u8         l3_prot_type[0x1];
1836         u8         l4_prot_type[0x1];
1837         u8         selected_fields[0x1e];
1838 };
1839
1840 enum {
1841         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1842         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1843 };
1844
1845 enum {
1846         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1847         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1848 };
1849
1850 struct mlx5_ifc_wq_bits {
1851         u8         wq_type[0x4];
1852         u8         wq_signature[0x1];
1853         u8         end_padding_mode[0x2];
1854         u8         cd_slave[0x1];
1855         u8         reserved_at_8[0x18];
1856
1857         u8         hds_skip_first_sge[0x1];
1858         u8         log2_hds_buf_size[0x3];
1859         u8         reserved_at_24[0x7];
1860         u8         page_offset[0x5];
1861         u8         lwm[0x10];
1862
1863         u8         reserved_at_40[0x8];
1864         u8         pd[0x18];
1865
1866         u8         reserved_at_60[0x8];
1867         u8         uar_page[0x18];
1868
1869         u8         dbr_addr[0x40];
1870
1871         u8         hw_counter[0x20];
1872
1873         u8         sw_counter[0x20];
1874
1875         u8         reserved_at_100[0xc];
1876         u8         log_wq_stride[0x4];
1877         u8         reserved_at_110[0x3];
1878         u8         log_wq_pg_sz[0x5];
1879         u8         reserved_at_118[0x3];
1880         u8         log_wq_sz[0x5];
1881
1882         u8         dbr_umem_valid[0x1];
1883         u8         wq_umem_valid[0x1];
1884         u8         reserved_at_122[0x1];
1885         u8         log_hairpin_num_packets[0x5];
1886         u8         reserved_at_128[0x3];
1887         u8         log_hairpin_data_sz[0x5];
1888
1889         u8         reserved_at_130[0x4];
1890         u8         log_wqe_num_of_strides[0x4];
1891         u8         two_byte_shift_en[0x1];
1892         u8         reserved_at_139[0x4];
1893         u8         log_wqe_stride_size[0x3];
1894
1895         u8         reserved_at_140[0x4c0];
1896
1897         struct mlx5_ifc_cmd_pas_bits pas[];
1898 };
1899
1900 struct mlx5_ifc_rq_num_bits {
1901         u8         reserved_at_0[0x8];
1902         u8         rq_num[0x18];
1903 };
1904
1905 struct mlx5_ifc_mac_address_layout_bits {
1906         u8         reserved_at_0[0x10];
1907         u8         mac_addr_47_32[0x10];
1908
1909         u8         mac_addr_31_0[0x20];
1910 };
1911
1912 struct mlx5_ifc_vlan_layout_bits {
1913         u8         reserved_at_0[0x14];
1914         u8         vlan[0x0c];
1915
1916         u8         reserved_at_20[0x20];
1917 };
1918
1919 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1920         u8         reserved_at_0[0xa0];
1921
1922         u8         min_time_between_cnps[0x20];
1923
1924         u8         reserved_at_c0[0x12];
1925         u8         cnp_dscp[0x6];
1926         u8         reserved_at_d8[0x4];
1927         u8         cnp_prio_mode[0x1];
1928         u8         cnp_802p_prio[0x3];
1929
1930         u8         reserved_at_e0[0x720];
1931 };
1932
1933 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1934         u8         reserved_at_0[0x60];
1935
1936         u8         reserved_at_60[0x4];
1937         u8         clamp_tgt_rate[0x1];
1938         u8         reserved_at_65[0x3];
1939         u8         clamp_tgt_rate_after_time_inc[0x1];
1940         u8         reserved_at_69[0x17];
1941
1942         u8         reserved_at_80[0x20];
1943
1944         u8         rpg_time_reset[0x20];
1945
1946         u8         rpg_byte_reset[0x20];
1947
1948         u8         rpg_threshold[0x20];
1949
1950         u8         rpg_max_rate[0x20];
1951
1952         u8         rpg_ai_rate[0x20];
1953
1954         u8         rpg_hai_rate[0x20];
1955
1956         u8         rpg_gd[0x20];
1957
1958         u8         rpg_min_dec_fac[0x20];
1959
1960         u8         rpg_min_rate[0x20];
1961
1962         u8         reserved_at_1c0[0xe0];
1963
1964         u8         rate_to_set_on_first_cnp[0x20];
1965
1966         u8         dce_tcp_g[0x20];
1967
1968         u8         dce_tcp_rtt[0x20];
1969
1970         u8         rate_reduce_monitor_period[0x20];
1971
1972         u8         reserved_at_320[0x20];
1973
1974         u8         initial_alpha_value[0x20];
1975
1976         u8         reserved_at_360[0x4a0];
1977 };
1978
1979 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1980         u8         reserved_at_0[0x80];
1981
1982         u8         rppp_max_rps[0x20];
1983
1984         u8         rpg_time_reset[0x20];
1985
1986         u8         rpg_byte_reset[0x20];
1987
1988         u8         rpg_threshold[0x20];
1989
1990         u8         rpg_max_rate[0x20];
1991
1992         u8         rpg_ai_rate[0x20];
1993
1994         u8         rpg_hai_rate[0x20];
1995
1996         u8         rpg_gd[0x20];
1997
1998         u8         rpg_min_dec_fac[0x20];
1999
2000         u8         rpg_min_rate[0x20];
2001
2002         u8         reserved_at_1c0[0x640];
2003 };
2004
2005 enum {
2006         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2007         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2008         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2009 };
2010
2011 struct mlx5_ifc_resize_field_select_bits {
2012         u8         resize_field_select[0x20];
2013 };
2014
2015 struct mlx5_ifc_resource_dump_bits {
2016         u8         more_dump[0x1];
2017         u8         inline_dump[0x1];
2018         u8         reserved_at_2[0xa];
2019         u8         seq_num[0x4];
2020         u8         segment_type[0x10];
2021
2022         u8         reserved_at_20[0x10];
2023         u8         vhca_id[0x10];
2024
2025         u8         index1[0x20];
2026
2027         u8         index2[0x20];
2028
2029         u8         num_of_obj1[0x10];
2030         u8         num_of_obj2[0x10];
2031
2032         u8         reserved_at_a0[0x20];
2033
2034         u8         device_opaque[0x40];
2035
2036         u8         mkey[0x20];
2037
2038         u8         size[0x20];
2039
2040         u8         address[0x40];
2041
2042         u8         inline_data[52][0x20];
2043 };
2044
2045 struct mlx5_ifc_resource_dump_menu_record_bits {
2046         u8         reserved_at_0[0x4];
2047         u8         num_of_obj2_supports_active[0x1];
2048         u8         num_of_obj2_supports_all[0x1];
2049         u8         must_have_num_of_obj2[0x1];
2050         u8         support_num_of_obj2[0x1];
2051         u8         num_of_obj1_supports_active[0x1];
2052         u8         num_of_obj1_supports_all[0x1];
2053         u8         must_have_num_of_obj1[0x1];
2054         u8         support_num_of_obj1[0x1];
2055         u8         must_have_index2[0x1];
2056         u8         support_index2[0x1];
2057         u8         must_have_index1[0x1];
2058         u8         support_index1[0x1];
2059         u8         segment_type[0x10];
2060
2061         u8         segment_name[4][0x20];
2062
2063         u8         index1_name[4][0x20];
2064
2065         u8         index2_name[4][0x20];
2066 };
2067
2068 struct mlx5_ifc_resource_dump_segment_header_bits {
2069         u8         length_dw[0x10];
2070         u8         segment_type[0x10];
2071 };
2072
2073 struct mlx5_ifc_resource_dump_command_segment_bits {
2074         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2075
2076         u8         segment_called[0x10];
2077         u8         vhca_id[0x10];
2078
2079         u8         index1[0x20];
2080
2081         u8         index2[0x20];
2082
2083         u8         num_of_obj1[0x10];
2084         u8         num_of_obj2[0x10];
2085 };
2086
2087 struct mlx5_ifc_resource_dump_error_segment_bits {
2088         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2089
2090         u8         reserved_at_20[0x10];
2091         u8         syndrome_id[0x10];
2092
2093         u8         reserved_at_40[0x40];
2094
2095         u8         error[8][0x20];
2096 };
2097
2098 struct mlx5_ifc_resource_dump_info_segment_bits {
2099         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2100
2101         u8         reserved_at_20[0x18];
2102         u8         dump_version[0x8];
2103
2104         u8         hw_version[0x20];
2105
2106         u8         fw_version[0x20];
2107 };
2108
2109 struct mlx5_ifc_resource_dump_menu_segment_bits {
2110         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2111
2112         u8         reserved_at_20[0x10];
2113         u8         num_of_records[0x10];
2114
2115         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2116 };
2117
2118 struct mlx5_ifc_resource_dump_resource_segment_bits {
2119         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2120
2121         u8         reserved_at_20[0x20];
2122
2123         u8         index1[0x20];
2124
2125         u8         index2[0x20];
2126
2127         u8         payload[][0x20];
2128 };
2129
2130 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2131         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2132 };
2133
2134 struct mlx5_ifc_menu_resource_dump_response_bits {
2135         struct mlx5_ifc_resource_dump_info_segment_bits info;
2136         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2137         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2138         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2139 };
2140
2141 enum {
2142         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2143         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2144         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2145         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2146 };
2147
2148 struct mlx5_ifc_modify_field_select_bits {
2149         u8         modify_field_select[0x20];
2150 };
2151
2152 struct mlx5_ifc_field_select_r_roce_np_bits {
2153         u8         field_select_r_roce_np[0x20];
2154 };
2155
2156 struct mlx5_ifc_field_select_r_roce_rp_bits {
2157         u8         field_select_r_roce_rp[0x20];
2158 };
2159
2160 enum {
2161         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2162         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2163         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2164         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2165         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2166         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2167         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2168         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2169         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2170         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2171 };
2172
2173 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2174         u8         field_select_8021qaurp[0x20];
2175 };
2176
2177 struct mlx5_ifc_phys_layer_cntrs_bits {
2178         u8         time_since_last_clear_high[0x20];
2179
2180         u8         time_since_last_clear_low[0x20];
2181
2182         u8         symbol_errors_high[0x20];
2183
2184         u8         symbol_errors_low[0x20];
2185
2186         u8         sync_headers_errors_high[0x20];
2187
2188         u8         sync_headers_errors_low[0x20];
2189
2190         u8         edpl_bip_errors_lane0_high[0x20];
2191
2192         u8         edpl_bip_errors_lane0_low[0x20];
2193
2194         u8         edpl_bip_errors_lane1_high[0x20];
2195
2196         u8         edpl_bip_errors_lane1_low[0x20];
2197
2198         u8         edpl_bip_errors_lane2_high[0x20];
2199
2200         u8         edpl_bip_errors_lane2_low[0x20];
2201
2202         u8         edpl_bip_errors_lane3_high[0x20];
2203
2204         u8         edpl_bip_errors_lane3_low[0x20];
2205
2206         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2207
2208         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2209
2210         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2211
2212         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2213
2214         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2215
2216         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2217
2218         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2219
2220         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2221
2222         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2223
2224         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2225
2226         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2227
2228         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2229
2230         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2231
2232         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2233
2234         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2235
2236         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2237
2238         u8         rs_fec_corrected_blocks_high[0x20];
2239
2240         u8         rs_fec_corrected_blocks_low[0x20];
2241
2242         u8         rs_fec_uncorrectable_blocks_high[0x20];
2243
2244         u8         rs_fec_uncorrectable_blocks_low[0x20];
2245
2246         u8         rs_fec_no_errors_blocks_high[0x20];
2247
2248         u8         rs_fec_no_errors_blocks_low[0x20];
2249
2250         u8         rs_fec_single_error_blocks_high[0x20];
2251
2252         u8         rs_fec_single_error_blocks_low[0x20];
2253
2254         u8         rs_fec_corrected_symbols_total_high[0x20];
2255
2256         u8         rs_fec_corrected_symbols_total_low[0x20];
2257
2258         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2259
2260         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2261
2262         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2263
2264         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2265
2266         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2267
2268         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2269
2270         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2271
2272         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2273
2274         u8         link_down_events[0x20];
2275
2276         u8         successful_recovery_events[0x20];
2277
2278         u8         reserved_at_640[0x180];
2279 };
2280
2281 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2282         u8         time_since_last_clear_high[0x20];
2283
2284         u8         time_since_last_clear_low[0x20];
2285
2286         u8         phy_received_bits_high[0x20];
2287
2288         u8         phy_received_bits_low[0x20];
2289
2290         u8         phy_symbol_errors_high[0x20];
2291
2292         u8         phy_symbol_errors_low[0x20];
2293
2294         u8         phy_corrected_bits_high[0x20];
2295
2296         u8         phy_corrected_bits_low[0x20];
2297
2298         u8         phy_corrected_bits_lane0_high[0x20];
2299
2300         u8         phy_corrected_bits_lane0_low[0x20];
2301
2302         u8         phy_corrected_bits_lane1_high[0x20];
2303
2304         u8         phy_corrected_bits_lane1_low[0x20];
2305
2306         u8         phy_corrected_bits_lane2_high[0x20];
2307
2308         u8         phy_corrected_bits_lane2_low[0x20];
2309
2310         u8         phy_corrected_bits_lane3_high[0x20];
2311
2312         u8         phy_corrected_bits_lane3_low[0x20];
2313
2314         u8         reserved_at_200[0x5c0];
2315 };
2316
2317 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2318         u8         symbol_error_counter[0x10];
2319
2320         u8         link_error_recovery_counter[0x8];
2321
2322         u8         link_downed_counter[0x8];
2323
2324         u8         port_rcv_errors[0x10];
2325
2326         u8         port_rcv_remote_physical_errors[0x10];
2327
2328         u8         port_rcv_switch_relay_errors[0x10];
2329
2330         u8         port_xmit_discards[0x10];
2331
2332         u8         port_xmit_constraint_errors[0x8];
2333
2334         u8         port_rcv_constraint_errors[0x8];
2335
2336         u8         reserved_at_70[0x8];
2337
2338         u8         link_overrun_errors[0x8];
2339
2340         u8         reserved_at_80[0x10];
2341
2342         u8         vl_15_dropped[0x10];
2343
2344         u8         reserved_at_a0[0x80];
2345
2346         u8         port_xmit_wait[0x20];
2347 };
2348
2349 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2350         u8         transmit_queue_high[0x20];
2351
2352         u8         transmit_queue_low[0x20];
2353
2354         u8         no_buffer_discard_uc_high[0x20];
2355
2356         u8         no_buffer_discard_uc_low[0x20];
2357
2358         u8         reserved_at_80[0x740];
2359 };
2360
2361 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2362         u8         wred_discard_high[0x20];
2363
2364         u8         wred_discard_low[0x20];
2365
2366         u8         ecn_marked_tc_high[0x20];
2367
2368         u8         ecn_marked_tc_low[0x20];
2369
2370         u8         reserved_at_80[0x740];
2371 };
2372
2373 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2374         u8         rx_octets_high[0x20];
2375
2376         u8         rx_octets_low[0x20];
2377
2378         u8         reserved_at_40[0xc0];
2379
2380         u8         rx_frames_high[0x20];
2381
2382         u8         rx_frames_low[0x20];
2383
2384         u8         tx_octets_high[0x20];
2385
2386         u8         tx_octets_low[0x20];
2387
2388         u8         reserved_at_180[0xc0];
2389
2390         u8         tx_frames_high[0x20];
2391
2392         u8         tx_frames_low[0x20];
2393
2394         u8         rx_pause_high[0x20];
2395
2396         u8         rx_pause_low[0x20];
2397
2398         u8         rx_pause_duration_high[0x20];
2399
2400         u8         rx_pause_duration_low[0x20];
2401
2402         u8         tx_pause_high[0x20];
2403
2404         u8         tx_pause_low[0x20];
2405
2406         u8         tx_pause_duration_high[0x20];
2407
2408         u8         tx_pause_duration_low[0x20];
2409
2410         u8         rx_pause_transition_high[0x20];
2411
2412         u8         rx_pause_transition_low[0x20];
2413
2414         u8         rx_discards_high[0x20];
2415
2416         u8         rx_discards_low[0x20];
2417
2418         u8         device_stall_minor_watermark_cnt_high[0x20];
2419
2420         u8         device_stall_minor_watermark_cnt_low[0x20];
2421
2422         u8         device_stall_critical_watermark_cnt_high[0x20];
2423
2424         u8         device_stall_critical_watermark_cnt_low[0x20];
2425
2426         u8         reserved_at_480[0x340];
2427 };
2428
2429 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2430         u8         port_transmit_wait_high[0x20];
2431
2432         u8         port_transmit_wait_low[0x20];
2433
2434         u8         reserved_at_40[0x100];
2435
2436         u8         rx_buffer_almost_full_high[0x20];
2437
2438         u8         rx_buffer_almost_full_low[0x20];
2439
2440         u8         rx_buffer_full_high[0x20];
2441
2442         u8         rx_buffer_full_low[0x20];
2443
2444         u8         rx_icrc_encapsulated_high[0x20];
2445
2446         u8         rx_icrc_encapsulated_low[0x20];
2447
2448         u8         reserved_at_200[0x5c0];
2449 };
2450
2451 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2452         u8         dot3stats_alignment_errors_high[0x20];
2453
2454         u8         dot3stats_alignment_errors_low[0x20];
2455
2456         u8         dot3stats_fcs_errors_high[0x20];
2457
2458         u8         dot3stats_fcs_errors_low[0x20];
2459
2460         u8         dot3stats_single_collision_frames_high[0x20];
2461
2462         u8         dot3stats_single_collision_frames_low[0x20];
2463
2464         u8         dot3stats_multiple_collision_frames_high[0x20];
2465
2466         u8         dot3stats_multiple_collision_frames_low[0x20];
2467
2468         u8         dot3stats_sqe_test_errors_high[0x20];
2469
2470         u8         dot3stats_sqe_test_errors_low[0x20];
2471
2472         u8         dot3stats_deferred_transmissions_high[0x20];
2473
2474         u8         dot3stats_deferred_transmissions_low[0x20];
2475
2476         u8         dot3stats_late_collisions_high[0x20];
2477
2478         u8         dot3stats_late_collisions_low[0x20];
2479
2480         u8         dot3stats_excessive_collisions_high[0x20];
2481
2482         u8         dot3stats_excessive_collisions_low[0x20];
2483
2484         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2485
2486         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2487
2488         u8         dot3stats_carrier_sense_errors_high[0x20];
2489
2490         u8         dot3stats_carrier_sense_errors_low[0x20];
2491
2492         u8         dot3stats_frame_too_longs_high[0x20];
2493
2494         u8         dot3stats_frame_too_longs_low[0x20];
2495
2496         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2497
2498         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2499
2500         u8         dot3stats_symbol_errors_high[0x20];
2501
2502         u8         dot3stats_symbol_errors_low[0x20];
2503
2504         u8         dot3control_in_unknown_opcodes_high[0x20];
2505
2506         u8         dot3control_in_unknown_opcodes_low[0x20];
2507
2508         u8         dot3in_pause_frames_high[0x20];
2509
2510         u8         dot3in_pause_frames_low[0x20];
2511
2512         u8         dot3out_pause_frames_high[0x20];
2513
2514         u8         dot3out_pause_frames_low[0x20];
2515
2516         u8         reserved_at_400[0x3c0];
2517 };
2518
2519 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2520         u8         ether_stats_drop_events_high[0x20];
2521
2522         u8         ether_stats_drop_events_low[0x20];
2523
2524         u8         ether_stats_octets_high[0x20];
2525
2526         u8         ether_stats_octets_low[0x20];
2527
2528         u8         ether_stats_pkts_high[0x20];
2529
2530         u8         ether_stats_pkts_low[0x20];
2531
2532         u8         ether_stats_broadcast_pkts_high[0x20];
2533
2534         u8         ether_stats_broadcast_pkts_low[0x20];
2535
2536         u8         ether_stats_multicast_pkts_high[0x20];
2537
2538         u8         ether_stats_multicast_pkts_low[0x20];
2539
2540         u8         ether_stats_crc_align_errors_high[0x20];
2541
2542         u8         ether_stats_crc_align_errors_low[0x20];
2543
2544         u8         ether_stats_undersize_pkts_high[0x20];
2545
2546         u8         ether_stats_undersize_pkts_low[0x20];
2547
2548         u8         ether_stats_oversize_pkts_high[0x20];
2549
2550         u8         ether_stats_oversize_pkts_low[0x20];
2551
2552         u8         ether_stats_fragments_high[0x20];
2553
2554         u8         ether_stats_fragments_low[0x20];
2555
2556         u8         ether_stats_jabbers_high[0x20];
2557
2558         u8         ether_stats_jabbers_low[0x20];
2559
2560         u8         ether_stats_collisions_high[0x20];
2561
2562         u8         ether_stats_collisions_low[0x20];
2563
2564         u8         ether_stats_pkts64octets_high[0x20];
2565
2566         u8         ether_stats_pkts64octets_low[0x20];
2567
2568         u8         ether_stats_pkts65to127octets_high[0x20];
2569
2570         u8         ether_stats_pkts65to127octets_low[0x20];
2571
2572         u8         ether_stats_pkts128to255octets_high[0x20];
2573
2574         u8         ether_stats_pkts128to255octets_low[0x20];
2575
2576         u8         ether_stats_pkts256to511octets_high[0x20];
2577
2578         u8         ether_stats_pkts256to511octets_low[0x20];
2579
2580         u8         ether_stats_pkts512to1023octets_high[0x20];
2581
2582         u8         ether_stats_pkts512to1023octets_low[0x20];
2583
2584         u8         ether_stats_pkts1024to1518octets_high[0x20];
2585
2586         u8         ether_stats_pkts1024to1518octets_low[0x20];
2587
2588         u8         ether_stats_pkts1519to2047octets_high[0x20];
2589
2590         u8         ether_stats_pkts1519to2047octets_low[0x20];
2591
2592         u8         ether_stats_pkts2048to4095octets_high[0x20];
2593
2594         u8         ether_stats_pkts2048to4095octets_low[0x20];
2595
2596         u8         ether_stats_pkts4096to8191octets_high[0x20];
2597
2598         u8         ether_stats_pkts4096to8191octets_low[0x20];
2599
2600         u8         ether_stats_pkts8192to10239octets_high[0x20];
2601
2602         u8         ether_stats_pkts8192to10239octets_low[0x20];
2603
2604         u8         reserved_at_540[0x280];
2605 };
2606
2607 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2608         u8         if_in_octets_high[0x20];
2609
2610         u8         if_in_octets_low[0x20];
2611
2612         u8         if_in_ucast_pkts_high[0x20];
2613
2614         u8         if_in_ucast_pkts_low[0x20];
2615
2616         u8         if_in_discards_high[0x20];
2617
2618         u8         if_in_discards_low[0x20];
2619
2620         u8         if_in_errors_high[0x20];
2621
2622         u8         if_in_errors_low[0x20];
2623
2624         u8         if_in_unknown_protos_high[0x20];
2625
2626         u8         if_in_unknown_protos_low[0x20];
2627
2628         u8         if_out_octets_high[0x20];
2629
2630         u8         if_out_octets_low[0x20];
2631
2632         u8         if_out_ucast_pkts_high[0x20];
2633
2634         u8         if_out_ucast_pkts_low[0x20];
2635
2636         u8         if_out_discards_high[0x20];
2637
2638         u8         if_out_discards_low[0x20];
2639
2640         u8         if_out_errors_high[0x20];
2641
2642         u8         if_out_errors_low[0x20];
2643
2644         u8         if_in_multicast_pkts_high[0x20];
2645
2646         u8         if_in_multicast_pkts_low[0x20];
2647
2648         u8         if_in_broadcast_pkts_high[0x20];
2649
2650         u8         if_in_broadcast_pkts_low[0x20];
2651
2652         u8         if_out_multicast_pkts_high[0x20];
2653
2654         u8         if_out_multicast_pkts_low[0x20];
2655
2656         u8         if_out_broadcast_pkts_high[0x20];
2657
2658         u8         if_out_broadcast_pkts_low[0x20];
2659
2660         u8         reserved_at_340[0x480];
2661 };
2662
2663 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2664         u8         a_frames_transmitted_ok_high[0x20];
2665
2666         u8         a_frames_transmitted_ok_low[0x20];
2667
2668         u8         a_frames_received_ok_high[0x20];
2669
2670         u8         a_frames_received_ok_low[0x20];
2671
2672         u8         a_frame_check_sequence_errors_high[0x20];
2673
2674         u8         a_frame_check_sequence_errors_low[0x20];
2675
2676         u8         a_alignment_errors_high[0x20];
2677
2678         u8         a_alignment_errors_low[0x20];
2679
2680         u8         a_octets_transmitted_ok_high[0x20];
2681
2682         u8         a_octets_transmitted_ok_low[0x20];
2683
2684         u8         a_octets_received_ok_high[0x20];
2685
2686         u8         a_octets_received_ok_low[0x20];
2687
2688         u8         a_multicast_frames_xmitted_ok_high[0x20];
2689
2690         u8         a_multicast_frames_xmitted_ok_low[0x20];
2691
2692         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2693
2694         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2695
2696         u8         a_multicast_frames_received_ok_high[0x20];
2697
2698         u8         a_multicast_frames_received_ok_low[0x20];
2699
2700         u8         a_broadcast_frames_received_ok_high[0x20];
2701
2702         u8         a_broadcast_frames_received_ok_low[0x20];
2703
2704         u8         a_in_range_length_errors_high[0x20];
2705
2706         u8         a_in_range_length_errors_low[0x20];
2707
2708         u8         a_out_of_range_length_field_high[0x20];
2709
2710         u8         a_out_of_range_length_field_low[0x20];
2711
2712         u8         a_frame_too_long_errors_high[0x20];
2713
2714         u8         a_frame_too_long_errors_low[0x20];
2715
2716         u8         a_symbol_error_during_carrier_high[0x20];
2717
2718         u8         a_symbol_error_during_carrier_low[0x20];
2719
2720         u8         a_mac_control_frames_transmitted_high[0x20];
2721
2722         u8         a_mac_control_frames_transmitted_low[0x20];
2723
2724         u8         a_mac_control_frames_received_high[0x20];
2725
2726         u8         a_mac_control_frames_received_low[0x20];
2727
2728         u8         a_unsupported_opcodes_received_high[0x20];
2729
2730         u8         a_unsupported_opcodes_received_low[0x20];
2731
2732         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2733
2734         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2735
2736         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2737
2738         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2739
2740         u8         reserved_at_4c0[0x300];
2741 };
2742
2743 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2744         u8         life_time_counter_high[0x20];
2745
2746         u8         life_time_counter_low[0x20];
2747
2748         u8         rx_errors[0x20];
2749
2750         u8         tx_errors[0x20];
2751
2752         u8         l0_to_recovery_eieos[0x20];
2753
2754         u8         l0_to_recovery_ts[0x20];
2755
2756         u8         l0_to_recovery_framing[0x20];
2757
2758         u8         l0_to_recovery_retrain[0x20];
2759
2760         u8         crc_error_dllp[0x20];
2761
2762         u8         crc_error_tlp[0x20];
2763
2764         u8         tx_overflow_buffer_pkt_high[0x20];
2765
2766         u8         tx_overflow_buffer_pkt_low[0x20];
2767
2768         u8         outbound_stalled_reads[0x20];
2769
2770         u8         outbound_stalled_writes[0x20];
2771
2772         u8         outbound_stalled_reads_events[0x20];
2773
2774         u8         outbound_stalled_writes_events[0x20];
2775
2776         u8         reserved_at_200[0x5c0];
2777 };
2778
2779 struct mlx5_ifc_cmd_inter_comp_event_bits {
2780         u8         command_completion_vector[0x20];
2781
2782         u8         reserved_at_20[0xc0];
2783 };
2784
2785 struct mlx5_ifc_stall_vl_event_bits {
2786         u8         reserved_at_0[0x18];
2787         u8         port_num[0x1];
2788         u8         reserved_at_19[0x3];
2789         u8         vl[0x4];
2790
2791         u8         reserved_at_20[0xa0];
2792 };
2793
2794 struct mlx5_ifc_db_bf_congestion_event_bits {
2795         u8         event_subtype[0x8];
2796         u8         reserved_at_8[0x8];
2797         u8         congestion_level[0x8];
2798         u8         reserved_at_18[0x8];
2799
2800         u8         reserved_at_20[0xa0];
2801 };
2802
2803 struct mlx5_ifc_gpio_event_bits {
2804         u8         reserved_at_0[0x60];
2805
2806         u8         gpio_event_hi[0x20];
2807
2808         u8         gpio_event_lo[0x20];
2809
2810         u8         reserved_at_a0[0x40];
2811 };
2812
2813 struct mlx5_ifc_port_state_change_event_bits {
2814         u8         reserved_at_0[0x40];
2815
2816         u8         port_num[0x4];
2817         u8         reserved_at_44[0x1c];
2818
2819         u8         reserved_at_60[0x80];
2820 };
2821
2822 struct mlx5_ifc_dropped_packet_logged_bits {
2823         u8         reserved_at_0[0xe0];
2824 };
2825
2826 struct mlx5_ifc_default_timeout_bits {
2827         u8         to_multiplier[0x3];
2828         u8         reserved_at_3[0x9];
2829         u8         to_value[0x14];
2830 };
2831
2832 struct mlx5_ifc_dtor_reg_bits {
2833         u8         reserved_at_0[0x20];
2834
2835         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2836
2837         u8         reserved_at_40[0x60];
2838
2839         struct mlx5_ifc_default_timeout_bits health_poll_to;
2840
2841         struct mlx5_ifc_default_timeout_bits full_crdump_to;
2842
2843         struct mlx5_ifc_default_timeout_bits fw_reset_to;
2844
2845         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2846
2847         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2848
2849         struct mlx5_ifc_default_timeout_bits tear_down_to;
2850
2851         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2852
2853         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2854
2855         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2856
2857         u8         reserved_at_1c0[0x40];
2858 };
2859
2860 enum {
2861         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2862         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2863 };
2864
2865 struct mlx5_ifc_cq_error_bits {
2866         u8         reserved_at_0[0x8];
2867         u8         cqn[0x18];
2868
2869         u8         reserved_at_20[0x20];
2870
2871         u8         reserved_at_40[0x18];
2872         u8         syndrome[0x8];
2873
2874         u8         reserved_at_60[0x80];
2875 };
2876
2877 struct mlx5_ifc_rdma_page_fault_event_bits {
2878         u8         bytes_committed[0x20];
2879
2880         u8         r_key[0x20];
2881
2882         u8         reserved_at_40[0x10];
2883         u8         packet_len[0x10];
2884
2885         u8         rdma_op_len[0x20];
2886
2887         u8         rdma_va[0x40];
2888
2889         u8         reserved_at_c0[0x5];
2890         u8         rdma[0x1];
2891         u8         write[0x1];
2892         u8         requestor[0x1];
2893         u8         qp_number[0x18];
2894 };
2895
2896 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2897         u8         bytes_committed[0x20];
2898
2899         u8         reserved_at_20[0x10];
2900         u8         wqe_index[0x10];
2901
2902         u8         reserved_at_40[0x10];
2903         u8         len[0x10];
2904
2905         u8         reserved_at_60[0x60];
2906
2907         u8         reserved_at_c0[0x5];
2908         u8         rdma[0x1];
2909         u8         write_read[0x1];
2910         u8         requestor[0x1];
2911         u8         qpn[0x18];
2912 };
2913
2914 struct mlx5_ifc_qp_events_bits {
2915         u8         reserved_at_0[0xa0];
2916
2917         u8         type[0x8];
2918         u8         reserved_at_a8[0x18];
2919
2920         u8         reserved_at_c0[0x8];
2921         u8         qpn_rqn_sqn[0x18];
2922 };
2923
2924 struct mlx5_ifc_dct_events_bits {
2925         u8         reserved_at_0[0xc0];
2926
2927         u8         reserved_at_c0[0x8];
2928         u8         dct_number[0x18];
2929 };
2930
2931 struct mlx5_ifc_comp_event_bits {
2932         u8         reserved_at_0[0xc0];
2933
2934         u8         reserved_at_c0[0x8];
2935         u8         cq_number[0x18];
2936 };
2937
2938 enum {
2939         MLX5_QPC_STATE_RST        = 0x0,
2940         MLX5_QPC_STATE_INIT       = 0x1,
2941         MLX5_QPC_STATE_RTR        = 0x2,
2942         MLX5_QPC_STATE_RTS        = 0x3,
2943         MLX5_QPC_STATE_SQER       = 0x4,
2944         MLX5_QPC_STATE_ERR        = 0x6,
2945         MLX5_QPC_STATE_SQD        = 0x7,
2946         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2947 };
2948
2949 enum {
2950         MLX5_QPC_ST_RC            = 0x0,
2951         MLX5_QPC_ST_UC            = 0x1,
2952         MLX5_QPC_ST_UD            = 0x2,
2953         MLX5_QPC_ST_XRC           = 0x3,
2954         MLX5_QPC_ST_DCI           = 0x5,
2955         MLX5_QPC_ST_QP0           = 0x7,
2956         MLX5_QPC_ST_QP1           = 0x8,
2957         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2958         MLX5_QPC_ST_REG_UMR       = 0xc,
2959 };
2960
2961 enum {
2962         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2963         MLX5_QPC_PM_STATE_REARM     = 0x1,
2964         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2965         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2966 };
2967
2968 enum {
2969         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2970 };
2971
2972 enum {
2973         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2974         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2975 };
2976
2977 enum {
2978         MLX5_QPC_MTU_256_BYTES        = 0x1,
2979         MLX5_QPC_MTU_512_BYTES        = 0x2,
2980         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2981         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2982         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2983         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2984 };
2985
2986 enum {
2987         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2988         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2989         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2990         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2991         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2992         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2993         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2994         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2995 };
2996
2997 enum {
2998         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2999         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3000         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3001 };
3002
3003 enum {
3004         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3005         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3006         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3007 };
3008
3009 enum {
3010         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3011         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3012         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3013 };
3014
3015 struct mlx5_ifc_qpc_bits {
3016         u8         state[0x4];
3017         u8         lag_tx_port_affinity[0x4];
3018         u8         st[0x8];
3019         u8         reserved_at_10[0x2];
3020         u8         isolate_vl_tc[0x1];
3021         u8         pm_state[0x2];
3022         u8         reserved_at_15[0x1];
3023         u8         req_e2e_credit_mode[0x2];
3024         u8         offload_type[0x4];
3025         u8         end_padding_mode[0x2];
3026         u8         reserved_at_1e[0x2];
3027
3028         u8         wq_signature[0x1];
3029         u8         block_lb_mc[0x1];
3030         u8         atomic_like_write_en[0x1];
3031         u8         latency_sensitive[0x1];
3032         u8         reserved_at_24[0x1];
3033         u8         drain_sigerr[0x1];
3034         u8         reserved_at_26[0x2];
3035         u8         pd[0x18];
3036
3037         u8         mtu[0x3];
3038         u8         log_msg_max[0x5];
3039         u8         reserved_at_48[0x1];
3040         u8         log_rq_size[0x4];
3041         u8         log_rq_stride[0x3];
3042         u8         no_sq[0x1];
3043         u8         log_sq_size[0x4];
3044         u8         reserved_at_55[0x3];
3045         u8         ts_format[0x2];
3046         u8         reserved_at_5a[0x1];
3047         u8         rlky[0x1];
3048         u8         ulp_stateless_offload_mode[0x4];
3049
3050         u8         counter_set_id[0x8];
3051         u8         uar_page[0x18];
3052
3053         u8         reserved_at_80[0x8];
3054         u8         user_index[0x18];
3055
3056         u8         reserved_at_a0[0x3];
3057         u8         log_page_size[0x5];
3058         u8         remote_qpn[0x18];
3059
3060         struct mlx5_ifc_ads_bits primary_address_path;
3061
3062         struct mlx5_ifc_ads_bits secondary_address_path;
3063
3064         u8         log_ack_req_freq[0x4];
3065         u8         reserved_at_384[0x4];
3066         u8         log_sra_max[0x3];
3067         u8         reserved_at_38b[0x2];
3068         u8         retry_count[0x3];
3069         u8         rnr_retry[0x3];
3070         u8         reserved_at_393[0x1];
3071         u8         fre[0x1];
3072         u8         cur_rnr_retry[0x3];
3073         u8         cur_retry_count[0x3];
3074         u8         reserved_at_39b[0x5];
3075
3076         u8         reserved_at_3a0[0x20];
3077
3078         u8         reserved_at_3c0[0x8];
3079         u8         next_send_psn[0x18];
3080
3081         u8         reserved_at_3e0[0x3];
3082         u8         log_num_dci_stream_channels[0x5];
3083         u8         cqn_snd[0x18];
3084
3085         u8         reserved_at_400[0x3];
3086         u8         log_num_dci_errored_streams[0x5];
3087         u8         deth_sqpn[0x18];
3088
3089         u8         reserved_at_420[0x20];
3090
3091         u8         reserved_at_440[0x8];
3092         u8         last_acked_psn[0x18];
3093
3094         u8         reserved_at_460[0x8];
3095         u8         ssn[0x18];
3096
3097         u8         reserved_at_480[0x8];
3098         u8         log_rra_max[0x3];
3099         u8         reserved_at_48b[0x1];
3100         u8         atomic_mode[0x4];
3101         u8         rre[0x1];
3102         u8         rwe[0x1];
3103         u8         rae[0x1];
3104         u8         reserved_at_493[0x1];
3105         u8         page_offset[0x6];
3106         u8         reserved_at_49a[0x3];
3107         u8         cd_slave_receive[0x1];
3108         u8         cd_slave_send[0x1];
3109         u8         cd_master[0x1];
3110
3111         u8         reserved_at_4a0[0x3];
3112         u8         min_rnr_nak[0x5];
3113         u8         next_rcv_psn[0x18];
3114
3115         u8         reserved_at_4c0[0x8];
3116         u8         xrcd[0x18];
3117
3118         u8         reserved_at_4e0[0x8];
3119         u8         cqn_rcv[0x18];
3120
3121         u8         dbr_addr[0x40];
3122
3123         u8         q_key[0x20];
3124
3125         u8         reserved_at_560[0x5];
3126         u8         rq_type[0x3];
3127         u8         srqn_rmpn_xrqn[0x18];
3128
3129         u8         reserved_at_580[0x8];
3130         u8         rmsn[0x18];
3131
3132         u8         hw_sq_wqebb_counter[0x10];
3133         u8         sw_sq_wqebb_counter[0x10];
3134
3135         u8         hw_rq_counter[0x20];
3136
3137         u8         sw_rq_counter[0x20];
3138
3139         u8         reserved_at_600[0x20];
3140
3141         u8         reserved_at_620[0xf];
3142         u8         cgs[0x1];
3143         u8         cs_req[0x8];
3144         u8         cs_res[0x8];
3145
3146         u8         dc_access_key[0x40];
3147
3148         u8         reserved_at_680[0x3];
3149         u8         dbr_umem_valid[0x1];
3150
3151         u8         reserved_at_684[0xbc];
3152 };
3153
3154 struct mlx5_ifc_roce_addr_layout_bits {
3155         u8         source_l3_address[16][0x8];
3156
3157         u8         reserved_at_80[0x3];
3158         u8         vlan_valid[0x1];
3159         u8         vlan_id[0xc];
3160         u8         source_mac_47_32[0x10];
3161
3162         u8         source_mac_31_0[0x20];
3163
3164         u8         reserved_at_c0[0x14];
3165         u8         roce_l3_type[0x4];
3166         u8         roce_version[0x8];
3167
3168         u8         reserved_at_e0[0x20];
3169 };
3170
3171 union mlx5_ifc_hca_cap_union_bits {
3172         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3173         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3174         struct mlx5_ifc_odp_cap_bits odp_cap;
3175         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3176         struct mlx5_ifc_roce_cap_bits roce_cap;
3177         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3178         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3179         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3180         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3181         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3182         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3183         struct mlx5_ifc_qos_cap_bits qos_cap;
3184         struct mlx5_ifc_debug_cap_bits debug_cap;
3185         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3186         struct mlx5_ifc_tls_cap_bits tls_cap;
3187         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3188         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3189         u8         reserved_at_0[0x8000];
3190 };
3191
3192 enum {
3193         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3194         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3195         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3196         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3197         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3198         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3199         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3200         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3201         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3202         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3203         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3204         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3205         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3206 };
3207
3208 enum {
3209         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3210         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3211         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3212 };
3213
3214 struct mlx5_ifc_vlan_bits {
3215         u8         ethtype[0x10];
3216         u8         prio[0x3];
3217         u8         cfi[0x1];
3218         u8         vid[0xc];
3219 };
3220
3221 struct mlx5_ifc_flow_context_bits {
3222         struct mlx5_ifc_vlan_bits push_vlan;
3223
3224         u8         group_id[0x20];
3225
3226         u8         reserved_at_40[0x8];
3227         u8         flow_tag[0x18];
3228
3229         u8         reserved_at_60[0x10];
3230         u8         action[0x10];
3231
3232         u8         extended_destination[0x1];
3233         u8         reserved_at_81[0x1];
3234         u8         flow_source[0x2];
3235         u8         reserved_at_84[0x4];
3236         u8         destination_list_size[0x18];
3237
3238         u8         reserved_at_a0[0x8];
3239         u8         flow_counter_list_size[0x18];
3240
3241         u8         packet_reformat_id[0x20];
3242
3243         u8         modify_header_id[0x20];
3244
3245         struct mlx5_ifc_vlan_bits push_vlan_2;
3246
3247         u8         ipsec_obj_id[0x20];
3248         u8         reserved_at_140[0xc0];
3249
3250         struct mlx5_ifc_fte_match_param_bits match_value;
3251
3252         u8         reserved_at_1200[0x600];
3253
3254         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3255 };
3256
3257 enum {
3258         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3259         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3260 };
3261
3262 struct mlx5_ifc_xrc_srqc_bits {
3263         u8         state[0x4];
3264         u8         log_xrc_srq_size[0x4];
3265         u8         reserved_at_8[0x18];
3266
3267         u8         wq_signature[0x1];
3268         u8         cont_srq[0x1];
3269         u8         reserved_at_22[0x1];
3270         u8         rlky[0x1];
3271         u8         basic_cyclic_rcv_wqe[0x1];
3272         u8         log_rq_stride[0x3];
3273         u8         xrcd[0x18];
3274
3275         u8         page_offset[0x6];
3276         u8         reserved_at_46[0x1];
3277         u8         dbr_umem_valid[0x1];
3278         u8         cqn[0x18];
3279
3280         u8         reserved_at_60[0x20];
3281
3282         u8         user_index_equal_xrc_srqn[0x1];
3283         u8         reserved_at_81[0x1];
3284         u8         log_page_size[0x6];
3285         u8         user_index[0x18];
3286
3287         u8         reserved_at_a0[0x20];
3288
3289         u8         reserved_at_c0[0x8];
3290         u8         pd[0x18];
3291
3292         u8         lwm[0x10];
3293         u8         wqe_cnt[0x10];
3294
3295         u8         reserved_at_100[0x40];
3296
3297         u8         db_record_addr_h[0x20];
3298
3299         u8         db_record_addr_l[0x1e];
3300         u8         reserved_at_17e[0x2];
3301
3302         u8         reserved_at_180[0x80];
3303 };
3304
3305 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3306         u8         counter_error_queues[0x20];
3307
3308         u8         total_error_queues[0x20];
3309
3310         u8         send_queue_priority_update_flow[0x20];
3311
3312         u8         reserved_at_60[0x20];
3313
3314         u8         nic_receive_steering_discard[0x40];
3315
3316         u8         receive_discard_vport_down[0x40];
3317
3318         u8         transmit_discard_vport_down[0x40];
3319
3320         u8         reserved_at_140[0xa0];
3321
3322         u8         internal_rq_out_of_buffer[0x20];
3323
3324         u8         reserved_at_200[0xe00];
3325 };
3326
3327 struct mlx5_ifc_traffic_counter_bits {
3328         u8         packets[0x40];
3329
3330         u8         octets[0x40];
3331 };
3332
3333 struct mlx5_ifc_tisc_bits {
3334         u8         strict_lag_tx_port_affinity[0x1];
3335         u8         tls_en[0x1];
3336         u8         reserved_at_2[0x2];
3337         u8         lag_tx_port_affinity[0x04];
3338
3339         u8         reserved_at_8[0x4];
3340         u8         prio[0x4];
3341         u8         reserved_at_10[0x10];
3342
3343         u8         reserved_at_20[0x100];
3344
3345         u8         reserved_at_120[0x8];
3346         u8         transport_domain[0x18];
3347
3348         u8         reserved_at_140[0x8];
3349         u8         underlay_qpn[0x18];
3350
3351         u8         reserved_at_160[0x8];
3352         u8         pd[0x18];
3353
3354         u8         reserved_at_180[0x380];
3355 };
3356
3357 enum {
3358         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3359         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3360 };
3361
3362 enum {
3363         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3364         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3365 };
3366
3367 enum {
3368         MLX5_RX_HASH_FN_NONE           = 0x0,
3369         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3370         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3371 };
3372
3373 enum {
3374         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3375         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3376 };
3377
3378 struct mlx5_ifc_tirc_bits {
3379         u8         reserved_at_0[0x20];
3380
3381         u8         disp_type[0x4];
3382         u8         tls_en[0x1];
3383         u8         reserved_at_25[0x1b];
3384
3385         u8         reserved_at_40[0x40];
3386
3387         u8         reserved_at_80[0x4];
3388         u8         lro_timeout_period_usecs[0x10];
3389         u8         lro_enable_mask[0x4];
3390         u8         lro_max_ip_payload_size[0x8];
3391
3392         u8         reserved_at_a0[0x40];
3393
3394         u8         reserved_at_e0[0x8];
3395         u8         inline_rqn[0x18];
3396
3397         u8         rx_hash_symmetric[0x1];
3398         u8         reserved_at_101[0x1];
3399         u8         tunneled_offload_en[0x1];
3400         u8         reserved_at_103[0x5];
3401         u8         indirect_table[0x18];
3402
3403         u8         rx_hash_fn[0x4];
3404         u8         reserved_at_124[0x2];
3405         u8         self_lb_block[0x2];
3406         u8         transport_domain[0x18];
3407
3408         u8         rx_hash_toeplitz_key[10][0x20];
3409
3410         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3411
3412         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3413
3414         u8         reserved_at_2c0[0x4c0];
3415 };
3416
3417 enum {
3418         MLX5_SRQC_STATE_GOOD   = 0x0,
3419         MLX5_SRQC_STATE_ERROR  = 0x1,
3420 };
3421
3422 struct mlx5_ifc_srqc_bits {
3423         u8         state[0x4];
3424         u8         log_srq_size[0x4];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         wq_signature[0x1];
3428         u8         cont_srq[0x1];
3429         u8         reserved_at_22[0x1];
3430         u8         rlky[0x1];
3431         u8         reserved_at_24[0x1];
3432         u8         log_rq_stride[0x3];
3433         u8         xrcd[0x18];
3434
3435         u8         page_offset[0x6];
3436         u8         reserved_at_46[0x2];
3437         u8         cqn[0x18];
3438
3439         u8         reserved_at_60[0x20];
3440
3441         u8         reserved_at_80[0x2];
3442         u8         log_page_size[0x6];
3443         u8         reserved_at_88[0x18];
3444
3445         u8         reserved_at_a0[0x20];
3446
3447         u8         reserved_at_c0[0x8];
3448         u8         pd[0x18];
3449
3450         u8         lwm[0x10];
3451         u8         wqe_cnt[0x10];
3452
3453         u8         reserved_at_100[0x40];
3454
3455         u8         dbr_addr[0x40];
3456
3457         u8         reserved_at_180[0x80];
3458 };
3459
3460 enum {
3461         MLX5_SQC_STATE_RST  = 0x0,
3462         MLX5_SQC_STATE_RDY  = 0x1,
3463         MLX5_SQC_STATE_ERR  = 0x3,
3464 };
3465
3466 struct mlx5_ifc_sqc_bits {
3467         u8         rlky[0x1];
3468         u8         cd_master[0x1];
3469         u8         fre[0x1];
3470         u8         flush_in_error_en[0x1];
3471         u8         allow_multi_pkt_send_wqe[0x1];
3472         u8         min_wqe_inline_mode[0x3];
3473         u8         state[0x4];
3474         u8         reg_umr[0x1];
3475         u8         allow_swp[0x1];
3476         u8         hairpin[0x1];
3477         u8         reserved_at_f[0xb];
3478         u8         ts_format[0x2];
3479         u8         reserved_at_1c[0x4];
3480
3481         u8         reserved_at_20[0x8];
3482         u8         user_index[0x18];
3483
3484         u8         reserved_at_40[0x8];
3485         u8         cqn[0x18];
3486
3487         u8         reserved_at_60[0x8];
3488         u8         hairpin_peer_rq[0x18];
3489
3490         u8         reserved_at_80[0x10];
3491         u8         hairpin_peer_vhca[0x10];
3492
3493         u8         reserved_at_a0[0x20];
3494
3495         u8         reserved_at_c0[0x8];
3496         u8         ts_cqe_to_dest_cqn[0x18];
3497
3498         u8         reserved_at_e0[0x10];
3499         u8         packet_pacing_rate_limit_index[0x10];
3500         u8         tis_lst_sz[0x10];
3501         u8         qos_queue_group_id[0x10];
3502
3503         u8         reserved_at_120[0x40];
3504
3505         u8         reserved_at_160[0x8];
3506         u8         tis_num_0[0x18];
3507
3508         struct mlx5_ifc_wq_bits wq;
3509 };
3510
3511 enum {
3512         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3513         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3514         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3515         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3516         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3517 };
3518
3519 enum {
3520         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3521         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3522         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3523         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3524 };
3525
3526 struct mlx5_ifc_scheduling_context_bits {
3527         u8         element_type[0x8];
3528         u8         reserved_at_8[0x18];
3529
3530         u8         element_attributes[0x20];
3531
3532         u8         parent_element_id[0x20];
3533
3534         u8         reserved_at_60[0x40];
3535
3536         u8         bw_share[0x20];
3537
3538         u8         max_average_bw[0x20];
3539
3540         u8         reserved_at_e0[0x120];
3541 };
3542
3543 struct mlx5_ifc_rqtc_bits {
3544         u8    reserved_at_0[0xa0];
3545
3546         u8    reserved_at_a0[0x5];
3547         u8    list_q_type[0x3];
3548         u8    reserved_at_a8[0x8];
3549         u8    rqt_max_size[0x10];
3550
3551         u8    rq_vhca_id_format[0x1];
3552         u8    reserved_at_c1[0xf];
3553         u8    rqt_actual_size[0x10];
3554
3555         u8    reserved_at_e0[0x6a0];
3556
3557         struct mlx5_ifc_rq_num_bits rq_num[];
3558 };
3559
3560 enum {
3561         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3562         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3563 };
3564
3565 enum {
3566         MLX5_RQC_STATE_RST  = 0x0,
3567         MLX5_RQC_STATE_RDY  = 0x1,
3568         MLX5_RQC_STATE_ERR  = 0x3,
3569 };
3570
3571 struct mlx5_ifc_rqc_bits {
3572         u8         rlky[0x1];
3573         u8         delay_drop_en[0x1];
3574         u8         scatter_fcs[0x1];
3575         u8         vsd[0x1];
3576         u8         mem_rq_type[0x4];
3577         u8         state[0x4];
3578         u8         reserved_at_c[0x1];
3579         u8         flush_in_error_en[0x1];
3580         u8         hairpin[0x1];
3581         u8         reserved_at_f[0xb];
3582         u8         ts_format[0x2];
3583         u8         reserved_at_1c[0x4];
3584
3585         u8         reserved_at_20[0x8];
3586         u8         user_index[0x18];
3587
3588         u8         reserved_at_40[0x8];
3589         u8         cqn[0x18];
3590
3591         u8         counter_set_id[0x8];
3592         u8         reserved_at_68[0x18];
3593
3594         u8         reserved_at_80[0x8];
3595         u8         rmpn[0x18];
3596
3597         u8         reserved_at_a0[0x8];
3598         u8         hairpin_peer_sq[0x18];
3599
3600         u8         reserved_at_c0[0x10];
3601         u8         hairpin_peer_vhca[0x10];
3602
3603         u8         reserved_at_e0[0xa0];
3604
3605         struct mlx5_ifc_wq_bits wq;
3606 };
3607
3608 enum {
3609         MLX5_RMPC_STATE_RDY  = 0x1,
3610         MLX5_RMPC_STATE_ERR  = 0x3,
3611 };
3612
3613 struct mlx5_ifc_rmpc_bits {
3614         u8         reserved_at_0[0x8];
3615         u8         state[0x4];
3616         u8         reserved_at_c[0x14];
3617
3618         u8         basic_cyclic_rcv_wqe[0x1];
3619         u8         reserved_at_21[0x1f];
3620
3621         u8         reserved_at_40[0x140];
3622
3623         struct mlx5_ifc_wq_bits wq;
3624 };
3625
3626 struct mlx5_ifc_nic_vport_context_bits {
3627         u8         reserved_at_0[0x5];
3628         u8         min_wqe_inline_mode[0x3];
3629         u8         reserved_at_8[0x15];
3630         u8         disable_mc_local_lb[0x1];
3631         u8         disable_uc_local_lb[0x1];
3632         u8         roce_en[0x1];
3633
3634         u8         arm_change_event[0x1];
3635         u8         reserved_at_21[0x1a];
3636         u8         event_on_mtu[0x1];
3637         u8         event_on_promisc_change[0x1];
3638         u8         event_on_vlan_change[0x1];
3639         u8         event_on_mc_address_change[0x1];
3640         u8         event_on_uc_address_change[0x1];
3641
3642         u8         reserved_at_40[0xc];
3643
3644         u8         affiliation_criteria[0x4];
3645         u8         affiliated_vhca_id[0x10];
3646
3647         u8         reserved_at_60[0xd0];
3648
3649         u8         mtu[0x10];
3650
3651         u8         system_image_guid[0x40];
3652         u8         port_guid[0x40];
3653         u8         node_guid[0x40];
3654
3655         u8         reserved_at_200[0x140];
3656         u8         qkey_violation_counter[0x10];
3657         u8         reserved_at_350[0x430];
3658
3659         u8         promisc_uc[0x1];
3660         u8         promisc_mc[0x1];
3661         u8         promisc_all[0x1];
3662         u8         reserved_at_783[0x2];
3663         u8         allowed_list_type[0x3];
3664         u8         reserved_at_788[0xc];
3665         u8         allowed_list_size[0xc];
3666
3667         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3668
3669         u8         reserved_at_7e0[0x20];
3670
3671         u8         current_uc_mac_address[][0x40];
3672 };
3673
3674 enum {
3675         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3676         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3677         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3678         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3679         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3680         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3681 };
3682
3683 struct mlx5_ifc_mkc_bits {
3684         u8         reserved_at_0[0x1];
3685         u8         free[0x1];
3686         u8         reserved_at_2[0x1];
3687         u8         access_mode_4_2[0x3];
3688         u8         reserved_at_6[0x7];
3689         u8         relaxed_ordering_write[0x1];
3690         u8         reserved_at_e[0x1];
3691         u8         small_fence_on_rdma_read_response[0x1];
3692         u8         umr_en[0x1];
3693         u8         a[0x1];
3694         u8         rw[0x1];
3695         u8         rr[0x1];
3696         u8         lw[0x1];
3697         u8         lr[0x1];
3698         u8         access_mode_1_0[0x2];
3699         u8         reserved_at_18[0x8];
3700
3701         u8         qpn[0x18];
3702         u8         mkey_7_0[0x8];
3703
3704         u8         reserved_at_40[0x20];
3705
3706         u8         length64[0x1];
3707         u8         bsf_en[0x1];
3708         u8         sync_umr[0x1];
3709         u8         reserved_at_63[0x2];
3710         u8         expected_sigerr_count[0x1];
3711         u8         reserved_at_66[0x1];
3712         u8         en_rinval[0x1];
3713         u8         pd[0x18];
3714
3715         u8         start_addr[0x40];
3716
3717         u8         len[0x40];
3718
3719         u8         bsf_octword_size[0x20];
3720
3721         u8         reserved_at_120[0x80];
3722
3723         u8         translations_octword_size[0x20];
3724
3725         u8         reserved_at_1c0[0x19];
3726         u8         relaxed_ordering_read[0x1];
3727         u8         reserved_at_1d9[0x1];
3728         u8         log_page_size[0x5];
3729
3730         u8         reserved_at_1e0[0x20];
3731 };
3732
3733 struct mlx5_ifc_pkey_bits {
3734         u8         reserved_at_0[0x10];
3735         u8         pkey[0x10];
3736 };
3737
3738 struct mlx5_ifc_array128_auto_bits {
3739         u8         array128_auto[16][0x8];
3740 };
3741
3742 struct mlx5_ifc_hca_vport_context_bits {
3743         u8         field_select[0x20];
3744
3745         u8         reserved_at_20[0xe0];
3746
3747         u8         sm_virt_aware[0x1];
3748         u8         has_smi[0x1];
3749         u8         has_raw[0x1];
3750         u8         grh_required[0x1];
3751         u8         reserved_at_104[0xc];
3752         u8         port_physical_state[0x4];
3753         u8         vport_state_policy[0x4];
3754         u8         port_state[0x4];
3755         u8         vport_state[0x4];
3756
3757         u8         reserved_at_120[0x20];
3758
3759         u8         system_image_guid[0x40];
3760
3761         u8         port_guid[0x40];
3762
3763         u8         node_guid[0x40];
3764
3765         u8         cap_mask1[0x20];
3766
3767         u8         cap_mask1_field_select[0x20];
3768
3769         u8         cap_mask2[0x20];
3770
3771         u8         cap_mask2_field_select[0x20];
3772
3773         u8         reserved_at_280[0x80];
3774
3775         u8         lid[0x10];
3776         u8         reserved_at_310[0x4];
3777         u8         init_type_reply[0x4];
3778         u8         lmc[0x3];
3779         u8         subnet_timeout[0x5];
3780
3781         u8         sm_lid[0x10];
3782         u8         sm_sl[0x4];
3783         u8         reserved_at_334[0xc];
3784
3785         u8         qkey_violation_counter[0x10];
3786         u8         pkey_violation_counter[0x10];
3787
3788         u8         reserved_at_360[0xca0];
3789 };
3790
3791 struct mlx5_ifc_esw_vport_context_bits {
3792         u8         fdb_to_vport_reg_c[0x1];
3793         u8         reserved_at_1[0x2];
3794         u8         vport_svlan_strip[0x1];
3795         u8         vport_cvlan_strip[0x1];
3796         u8         vport_svlan_insert[0x1];
3797         u8         vport_cvlan_insert[0x2];
3798         u8         fdb_to_vport_reg_c_id[0x8];
3799         u8         reserved_at_10[0x10];
3800
3801         u8         reserved_at_20[0x20];
3802
3803         u8         svlan_cfi[0x1];
3804         u8         svlan_pcp[0x3];
3805         u8         svlan_id[0xc];
3806         u8         cvlan_cfi[0x1];
3807         u8         cvlan_pcp[0x3];
3808         u8         cvlan_id[0xc];
3809
3810         u8         reserved_at_60[0x720];
3811
3812         u8         sw_steering_vport_icm_address_rx[0x40];
3813
3814         u8         sw_steering_vport_icm_address_tx[0x40];
3815 };
3816
3817 enum {
3818         MLX5_EQC_STATUS_OK                = 0x0,
3819         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3820 };
3821
3822 enum {
3823         MLX5_EQC_ST_ARMED  = 0x9,
3824         MLX5_EQC_ST_FIRED  = 0xa,
3825 };
3826
3827 struct mlx5_ifc_eqc_bits {
3828         u8         status[0x4];
3829         u8         reserved_at_4[0x9];
3830         u8         ec[0x1];
3831         u8         oi[0x1];
3832         u8         reserved_at_f[0x5];
3833         u8         st[0x4];
3834         u8         reserved_at_18[0x8];
3835
3836         u8         reserved_at_20[0x20];
3837
3838         u8         reserved_at_40[0x14];
3839         u8         page_offset[0x6];
3840         u8         reserved_at_5a[0x6];
3841
3842         u8         reserved_at_60[0x3];
3843         u8         log_eq_size[0x5];
3844         u8         uar_page[0x18];
3845
3846         u8         reserved_at_80[0x20];
3847
3848         u8         reserved_at_a0[0x14];
3849         u8         intr[0xc];
3850
3851         u8         reserved_at_c0[0x3];
3852         u8         log_page_size[0x5];
3853         u8         reserved_at_c8[0x18];
3854
3855         u8         reserved_at_e0[0x60];
3856
3857         u8         reserved_at_140[0x8];
3858         u8         consumer_counter[0x18];
3859
3860         u8         reserved_at_160[0x8];
3861         u8         producer_counter[0x18];
3862
3863         u8         reserved_at_180[0x80];
3864 };
3865
3866 enum {
3867         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3868         MLX5_DCTC_STATE_DRAINING  = 0x1,
3869         MLX5_DCTC_STATE_DRAINED   = 0x2,
3870 };
3871
3872 enum {
3873         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3874         MLX5_DCTC_CS_RES_NA         = 0x1,
3875         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3876 };
3877
3878 enum {
3879         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3880         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3881         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3882         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3883         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3884 };
3885
3886 struct mlx5_ifc_dctc_bits {
3887         u8         reserved_at_0[0x4];
3888         u8         state[0x4];
3889         u8         reserved_at_8[0x18];
3890
3891         u8         reserved_at_20[0x8];
3892         u8         user_index[0x18];
3893
3894         u8         reserved_at_40[0x8];
3895         u8         cqn[0x18];
3896
3897         u8         counter_set_id[0x8];
3898         u8         atomic_mode[0x4];
3899         u8         rre[0x1];
3900         u8         rwe[0x1];
3901         u8         rae[0x1];
3902         u8         atomic_like_write_en[0x1];
3903         u8         latency_sensitive[0x1];
3904         u8         rlky[0x1];
3905         u8         free_ar[0x1];
3906         u8         reserved_at_73[0xd];
3907
3908         u8         reserved_at_80[0x8];
3909         u8         cs_res[0x8];
3910         u8         reserved_at_90[0x3];
3911         u8         min_rnr_nak[0x5];
3912         u8         reserved_at_98[0x8];
3913
3914         u8         reserved_at_a0[0x8];
3915         u8         srqn_xrqn[0x18];
3916
3917         u8         reserved_at_c0[0x8];
3918         u8         pd[0x18];
3919
3920         u8         tclass[0x8];
3921         u8         reserved_at_e8[0x4];
3922         u8         flow_label[0x14];
3923
3924         u8         dc_access_key[0x40];
3925
3926         u8         reserved_at_140[0x5];
3927         u8         mtu[0x3];
3928         u8         port[0x8];
3929         u8         pkey_index[0x10];
3930
3931         u8         reserved_at_160[0x8];
3932         u8         my_addr_index[0x8];
3933         u8         reserved_at_170[0x8];
3934         u8         hop_limit[0x8];
3935
3936         u8         dc_access_key_violation_count[0x20];
3937
3938         u8         reserved_at_1a0[0x14];
3939         u8         dei_cfi[0x1];
3940         u8         eth_prio[0x3];
3941         u8         ecn[0x2];
3942         u8         dscp[0x6];
3943
3944         u8         reserved_at_1c0[0x20];
3945         u8         ece[0x20];
3946 };
3947
3948 enum {
3949         MLX5_CQC_STATUS_OK             = 0x0,
3950         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3951         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3952 };
3953
3954 enum {
3955         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3956         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3957 };
3958
3959 enum {
3960         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3961         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3962         MLX5_CQC_ST_FIRED                                 = 0xa,
3963 };
3964
3965 enum {
3966         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3967         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3968         MLX5_CQ_PERIOD_NUM_MODES
3969 };
3970
3971 struct mlx5_ifc_cqc_bits {
3972         u8         status[0x4];
3973         u8         reserved_at_4[0x2];
3974         u8         dbr_umem_valid[0x1];
3975         u8         apu_cq[0x1];
3976         u8         cqe_sz[0x3];
3977         u8         cc[0x1];
3978         u8         reserved_at_c[0x1];
3979         u8         scqe_break_moderation_en[0x1];
3980         u8         oi[0x1];
3981         u8         cq_period_mode[0x2];
3982         u8         cqe_comp_en[0x1];
3983         u8         mini_cqe_res_format[0x2];
3984         u8         st[0x4];
3985         u8         reserved_at_18[0x8];
3986
3987         u8         reserved_at_20[0x20];
3988
3989         u8         reserved_at_40[0x14];
3990         u8         page_offset[0x6];
3991         u8         reserved_at_5a[0x6];
3992
3993         u8         reserved_at_60[0x3];
3994         u8         log_cq_size[0x5];
3995         u8         uar_page[0x18];
3996
3997         u8         reserved_at_80[0x4];
3998         u8         cq_period[0xc];
3999         u8         cq_max_count[0x10];
4000
4001         u8         c_eqn_or_apu_element[0x20];
4002
4003         u8         reserved_at_c0[0x3];
4004         u8         log_page_size[0x5];
4005         u8         reserved_at_c8[0x18];
4006
4007         u8         reserved_at_e0[0x20];
4008
4009         u8         reserved_at_100[0x8];
4010         u8         last_notified_index[0x18];
4011
4012         u8         reserved_at_120[0x8];
4013         u8         last_solicit_index[0x18];
4014
4015         u8         reserved_at_140[0x8];
4016         u8         consumer_counter[0x18];
4017
4018         u8         reserved_at_160[0x8];
4019         u8         producer_counter[0x18];
4020
4021         u8         reserved_at_180[0x40];
4022
4023         u8         dbr_addr[0x40];
4024 };
4025
4026 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4027         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4028         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4029         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4030         u8         reserved_at_0[0x800];
4031 };
4032
4033 struct mlx5_ifc_query_adapter_param_block_bits {
4034         u8         reserved_at_0[0xc0];
4035
4036         u8         reserved_at_c0[0x8];
4037         u8         ieee_vendor_id[0x18];
4038
4039         u8         reserved_at_e0[0x10];
4040         u8         vsd_vendor_id[0x10];
4041
4042         u8         vsd[208][0x8];
4043
4044         u8         vsd_contd_psid[16][0x8];
4045 };
4046
4047 enum {
4048         MLX5_XRQC_STATE_GOOD   = 0x0,
4049         MLX5_XRQC_STATE_ERROR  = 0x1,
4050 };
4051
4052 enum {
4053         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4054         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4055 };
4056
4057 enum {
4058         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4059 };
4060
4061 struct mlx5_ifc_tag_matching_topology_context_bits {
4062         u8         log_matching_list_sz[0x4];
4063         u8         reserved_at_4[0xc];
4064         u8         append_next_index[0x10];
4065
4066         u8         sw_phase_cnt[0x10];
4067         u8         hw_phase_cnt[0x10];
4068
4069         u8         reserved_at_40[0x40];
4070 };
4071
4072 struct mlx5_ifc_xrqc_bits {
4073         u8         state[0x4];
4074         u8         rlkey[0x1];
4075         u8         reserved_at_5[0xf];
4076         u8         topology[0x4];
4077         u8         reserved_at_18[0x4];
4078         u8         offload[0x4];
4079
4080         u8         reserved_at_20[0x8];
4081         u8         user_index[0x18];
4082
4083         u8         reserved_at_40[0x8];
4084         u8         cqn[0x18];
4085
4086         u8         reserved_at_60[0xa0];
4087
4088         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4089
4090         u8         reserved_at_180[0x280];
4091
4092         struct mlx5_ifc_wq_bits wq;
4093 };
4094
4095 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4096         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4097         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4098         u8         reserved_at_0[0x20];
4099 };
4100
4101 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4102         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4103         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4104         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4105         u8         reserved_at_0[0x20];
4106 };
4107
4108 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4109         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4110         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4111         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4112         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4113         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4114         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4115         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4116         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4117         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4118         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4119         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4120         u8         reserved_at_0[0x7c0];
4121 };
4122
4123 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4124         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4125         u8         reserved_at_0[0x7c0];
4126 };
4127
4128 union mlx5_ifc_event_auto_bits {
4129         struct mlx5_ifc_comp_event_bits comp_event;
4130         struct mlx5_ifc_dct_events_bits dct_events;
4131         struct mlx5_ifc_qp_events_bits qp_events;
4132         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4133         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4134         struct mlx5_ifc_cq_error_bits cq_error;
4135         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4136         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4137         struct mlx5_ifc_gpio_event_bits gpio_event;
4138         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4139         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4140         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4141         u8         reserved_at_0[0xe0];
4142 };
4143
4144 struct mlx5_ifc_health_buffer_bits {
4145         u8         reserved_at_0[0x100];
4146
4147         u8         assert_existptr[0x20];
4148
4149         u8         assert_callra[0x20];
4150
4151         u8         reserved_at_140[0x40];
4152
4153         u8         fw_version[0x20];
4154
4155         u8         hw_id[0x20];
4156
4157         u8         reserved_at_1c0[0x20];
4158
4159         u8         irisc_index[0x8];
4160         u8         synd[0x8];
4161         u8         ext_synd[0x10];
4162 };
4163
4164 struct mlx5_ifc_register_loopback_control_bits {
4165         u8         no_lb[0x1];
4166         u8         reserved_at_1[0x7];
4167         u8         port[0x8];
4168         u8         reserved_at_10[0x10];
4169
4170         u8         reserved_at_20[0x60];
4171 };
4172
4173 struct mlx5_ifc_vport_tc_element_bits {
4174         u8         traffic_class[0x4];
4175         u8         reserved_at_4[0xc];
4176         u8         vport_number[0x10];
4177 };
4178
4179 struct mlx5_ifc_vport_element_bits {
4180         u8         reserved_at_0[0x10];
4181         u8         vport_number[0x10];
4182 };
4183
4184 enum {
4185         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4186         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4187         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4188 };
4189
4190 struct mlx5_ifc_tsar_element_bits {
4191         u8         reserved_at_0[0x8];
4192         u8         tsar_type[0x8];
4193         u8         reserved_at_10[0x10];
4194 };
4195
4196 enum {
4197         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4198         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4199 };
4200
4201 struct mlx5_ifc_teardown_hca_out_bits {
4202         u8         status[0x8];
4203         u8         reserved_at_8[0x18];
4204
4205         u8         syndrome[0x20];
4206
4207         u8         reserved_at_40[0x3f];
4208
4209         u8         state[0x1];
4210 };
4211
4212 enum {
4213         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4214         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4215         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4216 };
4217
4218 struct mlx5_ifc_teardown_hca_in_bits {
4219         u8         opcode[0x10];
4220         u8         reserved_at_10[0x10];
4221
4222         u8         reserved_at_20[0x10];
4223         u8         op_mod[0x10];
4224
4225         u8         reserved_at_40[0x10];
4226         u8         profile[0x10];
4227
4228         u8         reserved_at_60[0x20];
4229 };
4230
4231 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4232         u8         status[0x8];
4233         u8         reserved_at_8[0x18];
4234
4235         u8         syndrome[0x20];
4236
4237         u8         reserved_at_40[0x40];
4238 };
4239
4240 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4241         u8         opcode[0x10];
4242         u8         uid[0x10];
4243
4244         u8         reserved_at_20[0x10];
4245         u8         op_mod[0x10];
4246
4247         u8         reserved_at_40[0x8];
4248         u8         qpn[0x18];
4249
4250         u8         reserved_at_60[0x20];
4251
4252         u8         opt_param_mask[0x20];
4253
4254         u8         reserved_at_a0[0x20];
4255
4256         struct mlx5_ifc_qpc_bits qpc;
4257
4258         u8         reserved_at_800[0x80];
4259 };
4260
4261 struct mlx5_ifc_sqd2rts_qp_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_at_8[0x18];
4264
4265         u8         syndrome[0x20];
4266
4267         u8         reserved_at_40[0x40];
4268 };
4269
4270 struct mlx5_ifc_sqd2rts_qp_in_bits {
4271         u8         opcode[0x10];
4272         u8         uid[0x10];
4273
4274         u8         reserved_at_20[0x10];
4275         u8         op_mod[0x10];
4276
4277         u8         reserved_at_40[0x8];
4278         u8         qpn[0x18];
4279
4280         u8         reserved_at_60[0x20];
4281
4282         u8         opt_param_mask[0x20];
4283
4284         u8         reserved_at_a0[0x20];
4285
4286         struct mlx5_ifc_qpc_bits qpc;
4287
4288         u8         reserved_at_800[0x80];
4289 };
4290
4291 struct mlx5_ifc_set_roce_address_out_bits {
4292         u8         status[0x8];
4293         u8         reserved_at_8[0x18];
4294
4295         u8         syndrome[0x20];
4296
4297         u8         reserved_at_40[0x40];
4298 };
4299
4300 struct mlx5_ifc_set_roce_address_in_bits {
4301         u8         opcode[0x10];
4302         u8         reserved_at_10[0x10];
4303
4304         u8         reserved_at_20[0x10];
4305         u8         op_mod[0x10];
4306
4307         u8         roce_address_index[0x10];
4308         u8         reserved_at_50[0xc];
4309         u8         vhca_port_num[0x4];
4310
4311         u8         reserved_at_60[0x20];
4312
4313         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4314 };
4315
4316 struct mlx5_ifc_set_mad_demux_out_bits {
4317         u8         status[0x8];
4318         u8         reserved_at_8[0x18];
4319
4320         u8         syndrome[0x20];
4321
4322         u8         reserved_at_40[0x40];
4323 };
4324
4325 enum {
4326         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4327         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4328 };
4329
4330 struct mlx5_ifc_set_mad_demux_in_bits {
4331         u8         opcode[0x10];
4332         u8         reserved_at_10[0x10];
4333
4334         u8         reserved_at_20[0x10];
4335         u8         op_mod[0x10];
4336
4337         u8         reserved_at_40[0x20];
4338
4339         u8         reserved_at_60[0x6];
4340         u8         demux_mode[0x2];
4341         u8         reserved_at_68[0x18];
4342 };
4343
4344 struct mlx5_ifc_set_l2_table_entry_out_bits {
4345         u8         status[0x8];
4346         u8         reserved_at_8[0x18];
4347
4348         u8         syndrome[0x20];
4349
4350         u8         reserved_at_40[0x40];
4351 };
4352
4353 struct mlx5_ifc_set_l2_table_entry_in_bits {
4354         u8         opcode[0x10];
4355         u8         reserved_at_10[0x10];
4356
4357         u8         reserved_at_20[0x10];
4358         u8         op_mod[0x10];
4359
4360         u8         reserved_at_40[0x60];
4361
4362         u8         reserved_at_a0[0x8];
4363         u8         table_index[0x18];
4364
4365         u8         reserved_at_c0[0x20];
4366
4367         u8         reserved_at_e0[0x13];
4368         u8         vlan_valid[0x1];
4369         u8         vlan[0xc];
4370
4371         struct mlx5_ifc_mac_address_layout_bits mac_address;
4372
4373         u8         reserved_at_140[0xc0];
4374 };
4375
4376 struct mlx5_ifc_set_issi_out_bits {
4377         u8         status[0x8];
4378         u8         reserved_at_8[0x18];
4379
4380         u8         syndrome[0x20];
4381
4382         u8         reserved_at_40[0x40];
4383 };
4384
4385 struct mlx5_ifc_set_issi_in_bits {
4386         u8         opcode[0x10];
4387         u8         reserved_at_10[0x10];
4388
4389         u8         reserved_at_20[0x10];
4390         u8         op_mod[0x10];
4391
4392         u8         reserved_at_40[0x10];
4393         u8         current_issi[0x10];
4394
4395         u8         reserved_at_60[0x20];
4396 };
4397
4398 struct mlx5_ifc_set_hca_cap_out_bits {
4399         u8         status[0x8];
4400         u8         reserved_at_8[0x18];
4401
4402         u8         syndrome[0x20];
4403
4404         u8         reserved_at_40[0x40];
4405 };
4406
4407 struct mlx5_ifc_set_hca_cap_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_at_10[0x10];
4410
4411         u8         reserved_at_20[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         other_function[0x1];
4415         u8         reserved_at_41[0xf];
4416         u8         function_id[0x10];
4417
4418         u8         reserved_at_60[0x20];
4419
4420         union mlx5_ifc_hca_cap_union_bits capability;
4421 };
4422
4423 enum {
4424         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4425         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4426         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4427         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4428         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4429 };
4430
4431 struct mlx5_ifc_set_fte_out_bits {
4432         u8         status[0x8];
4433         u8         reserved_at_8[0x18];
4434
4435         u8         syndrome[0x20];
4436
4437         u8         reserved_at_40[0x40];
4438 };
4439
4440 struct mlx5_ifc_set_fte_in_bits {
4441         u8         opcode[0x10];
4442         u8         reserved_at_10[0x10];
4443
4444         u8         reserved_at_20[0x10];
4445         u8         op_mod[0x10];
4446
4447         u8         other_vport[0x1];
4448         u8         reserved_at_41[0xf];
4449         u8         vport_number[0x10];
4450
4451         u8         reserved_at_60[0x20];
4452
4453         u8         table_type[0x8];
4454         u8         reserved_at_88[0x18];
4455
4456         u8         reserved_at_a0[0x8];
4457         u8         table_id[0x18];
4458
4459         u8         ignore_flow_level[0x1];
4460         u8         reserved_at_c1[0x17];
4461         u8         modify_enable_mask[0x8];
4462
4463         u8         reserved_at_e0[0x20];
4464
4465         u8         flow_index[0x20];
4466
4467         u8         reserved_at_120[0xe0];
4468
4469         struct mlx5_ifc_flow_context_bits flow_context;
4470 };
4471
4472 struct mlx5_ifc_rts2rts_qp_out_bits {
4473         u8         status[0x8];
4474         u8         reserved_at_8[0x18];
4475
4476         u8         syndrome[0x20];
4477
4478         u8         reserved_at_40[0x20];
4479         u8         ece[0x20];
4480 };
4481
4482 struct mlx5_ifc_rts2rts_qp_in_bits {
4483         u8         opcode[0x10];
4484         u8         uid[0x10];
4485
4486         u8         reserved_at_20[0x10];
4487         u8         op_mod[0x10];
4488
4489         u8         reserved_at_40[0x8];
4490         u8         qpn[0x18];
4491
4492         u8         reserved_at_60[0x20];
4493
4494         u8         opt_param_mask[0x20];
4495
4496         u8         ece[0x20];
4497
4498         struct mlx5_ifc_qpc_bits qpc;
4499
4500         u8         reserved_at_800[0x80];
4501 };
4502
4503 struct mlx5_ifc_rtr2rts_qp_out_bits {
4504         u8         status[0x8];
4505         u8         reserved_at_8[0x18];
4506
4507         u8         syndrome[0x20];
4508
4509         u8         reserved_at_40[0x20];
4510         u8         ece[0x20];
4511 };
4512
4513 struct mlx5_ifc_rtr2rts_qp_in_bits {
4514         u8         opcode[0x10];
4515         u8         uid[0x10];
4516
4517         u8         reserved_at_20[0x10];
4518         u8         op_mod[0x10];
4519
4520         u8         reserved_at_40[0x8];
4521         u8         qpn[0x18];
4522
4523         u8         reserved_at_60[0x20];
4524
4525         u8         opt_param_mask[0x20];
4526
4527         u8         ece[0x20];
4528
4529         struct mlx5_ifc_qpc_bits qpc;
4530
4531         u8         reserved_at_800[0x80];
4532 };
4533
4534 struct mlx5_ifc_rst2init_qp_out_bits {
4535         u8         status[0x8];
4536         u8         reserved_at_8[0x18];
4537
4538         u8         syndrome[0x20];
4539
4540         u8         reserved_at_40[0x20];
4541         u8         ece[0x20];
4542 };
4543
4544 struct mlx5_ifc_rst2init_qp_in_bits {
4545         u8         opcode[0x10];
4546         u8         uid[0x10];
4547
4548         u8         reserved_at_20[0x10];
4549         u8         op_mod[0x10];
4550
4551         u8         reserved_at_40[0x8];
4552         u8         qpn[0x18];
4553
4554         u8         reserved_at_60[0x20];
4555
4556         u8         opt_param_mask[0x20];
4557
4558         u8         ece[0x20];
4559
4560         struct mlx5_ifc_qpc_bits qpc;
4561
4562         u8         reserved_at_800[0x80];
4563 };
4564
4565 struct mlx5_ifc_query_xrq_out_bits {
4566         u8         status[0x8];
4567         u8         reserved_at_8[0x18];
4568
4569         u8         syndrome[0x20];
4570
4571         u8         reserved_at_40[0x40];
4572
4573         struct mlx5_ifc_xrqc_bits xrq_context;
4574 };
4575
4576 struct mlx5_ifc_query_xrq_in_bits {
4577         u8         opcode[0x10];
4578         u8         reserved_at_10[0x10];
4579
4580         u8         reserved_at_20[0x10];
4581         u8         op_mod[0x10];
4582
4583         u8         reserved_at_40[0x8];
4584         u8         xrqn[0x18];
4585
4586         u8         reserved_at_60[0x20];
4587 };
4588
4589 struct mlx5_ifc_query_xrc_srq_out_bits {
4590         u8         status[0x8];
4591         u8         reserved_at_8[0x18];
4592
4593         u8         syndrome[0x20];
4594
4595         u8         reserved_at_40[0x40];
4596
4597         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4598
4599         u8         reserved_at_280[0x600];
4600
4601         u8         pas[][0x40];
4602 };
4603
4604 struct mlx5_ifc_query_xrc_srq_in_bits {
4605         u8         opcode[0x10];
4606         u8         reserved_at_10[0x10];
4607
4608         u8         reserved_at_20[0x10];
4609         u8         op_mod[0x10];
4610
4611         u8         reserved_at_40[0x8];
4612         u8         xrc_srqn[0x18];
4613
4614         u8         reserved_at_60[0x20];
4615 };
4616
4617 enum {
4618         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4619         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4620 };
4621
4622 struct mlx5_ifc_query_vport_state_out_bits {
4623         u8         status[0x8];
4624         u8         reserved_at_8[0x18];
4625
4626         u8         syndrome[0x20];
4627
4628         u8         reserved_at_40[0x20];
4629
4630         u8         reserved_at_60[0x18];
4631         u8         admin_state[0x4];
4632         u8         state[0x4];
4633 };
4634
4635 enum {
4636         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4637         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4638         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4639 };
4640
4641 struct mlx5_ifc_arm_monitor_counter_in_bits {
4642         u8         opcode[0x10];
4643         u8         uid[0x10];
4644
4645         u8         reserved_at_20[0x10];
4646         u8         op_mod[0x10];
4647
4648         u8         reserved_at_40[0x20];
4649
4650         u8         reserved_at_60[0x20];
4651 };
4652
4653 struct mlx5_ifc_arm_monitor_counter_out_bits {
4654         u8         status[0x8];
4655         u8         reserved_at_8[0x18];
4656
4657         u8         syndrome[0x20];
4658
4659         u8         reserved_at_40[0x40];
4660 };
4661
4662 enum {
4663         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4664         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4665 };
4666
4667 enum mlx5_monitor_counter_ppcnt {
4668         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4669         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4670         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4671         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4672         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4673         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4674 };
4675
4676 enum {
4677         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4678 };
4679
4680 struct mlx5_ifc_monitor_counter_output_bits {
4681         u8         reserved_at_0[0x4];
4682         u8         type[0x4];
4683         u8         reserved_at_8[0x8];
4684         u8         counter[0x10];
4685
4686         u8         counter_group_id[0x20];
4687 };
4688
4689 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4690 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4691 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4692                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4693
4694 struct mlx5_ifc_set_monitor_counter_in_bits {
4695         u8         opcode[0x10];
4696         u8         uid[0x10];
4697
4698         u8         reserved_at_20[0x10];
4699         u8         op_mod[0x10];
4700
4701         u8         reserved_at_40[0x10];
4702         u8         num_of_counters[0x10];
4703
4704         u8         reserved_at_60[0x20];
4705
4706         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4707 };
4708
4709 struct mlx5_ifc_set_monitor_counter_out_bits {
4710         u8         status[0x8];
4711         u8         reserved_at_8[0x18];
4712
4713         u8         syndrome[0x20];
4714
4715         u8         reserved_at_40[0x40];
4716 };
4717
4718 struct mlx5_ifc_query_vport_state_in_bits {
4719         u8         opcode[0x10];
4720         u8         reserved_at_10[0x10];
4721
4722         u8         reserved_at_20[0x10];
4723         u8         op_mod[0x10];
4724
4725         u8         other_vport[0x1];
4726         u8         reserved_at_41[0xf];
4727         u8         vport_number[0x10];
4728
4729         u8         reserved_at_60[0x20];
4730 };
4731
4732 struct mlx5_ifc_query_vnic_env_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_at_8[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_at_40[0x40];
4739
4740         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4741 };
4742
4743 enum {
4744         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4745 };
4746
4747 struct mlx5_ifc_query_vnic_env_in_bits {
4748         u8         opcode[0x10];
4749         u8         reserved_at_10[0x10];
4750
4751         u8         reserved_at_20[0x10];
4752         u8         op_mod[0x10];
4753
4754         u8         other_vport[0x1];
4755         u8         reserved_at_41[0xf];
4756         u8         vport_number[0x10];
4757
4758         u8         reserved_at_60[0x20];
4759 };
4760
4761 struct mlx5_ifc_query_vport_counter_out_bits {
4762         u8         status[0x8];
4763         u8         reserved_at_8[0x18];
4764
4765         u8         syndrome[0x20];
4766
4767         u8         reserved_at_40[0x40];
4768
4769         struct mlx5_ifc_traffic_counter_bits received_errors;
4770
4771         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4772
4773         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4774
4775         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4776
4777         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4778
4779         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4780
4781         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4782
4783         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4784
4785         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4786
4787         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4788
4789         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4790
4791         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4792
4793         u8         reserved_at_680[0xa00];
4794 };
4795
4796 enum {
4797         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4798 };
4799
4800 struct mlx5_ifc_query_vport_counter_in_bits {
4801         u8         opcode[0x10];
4802         u8         reserved_at_10[0x10];
4803
4804         u8         reserved_at_20[0x10];
4805         u8         op_mod[0x10];
4806
4807         u8         other_vport[0x1];
4808         u8         reserved_at_41[0xb];
4809         u8         port_num[0x4];
4810         u8         vport_number[0x10];
4811
4812         u8         reserved_at_60[0x60];
4813
4814         u8         clear[0x1];
4815         u8         reserved_at_c1[0x1f];
4816
4817         u8         reserved_at_e0[0x20];
4818 };
4819
4820 struct mlx5_ifc_query_tis_out_bits {
4821         u8         status[0x8];
4822         u8         reserved_at_8[0x18];
4823
4824         u8         syndrome[0x20];
4825
4826         u8         reserved_at_40[0x40];
4827
4828         struct mlx5_ifc_tisc_bits tis_context;
4829 };
4830
4831 struct mlx5_ifc_query_tis_in_bits {
4832         u8         opcode[0x10];
4833         u8         reserved_at_10[0x10];
4834
4835         u8         reserved_at_20[0x10];
4836         u8         op_mod[0x10];
4837
4838         u8         reserved_at_40[0x8];
4839         u8         tisn[0x18];
4840
4841         u8         reserved_at_60[0x20];
4842 };
4843
4844 struct mlx5_ifc_query_tir_out_bits {
4845         u8         status[0x8];
4846         u8         reserved_at_8[0x18];
4847
4848         u8         syndrome[0x20];
4849
4850         u8         reserved_at_40[0xc0];
4851
4852         struct mlx5_ifc_tirc_bits tir_context;
4853 };
4854
4855 struct mlx5_ifc_query_tir_in_bits {
4856         u8         opcode[0x10];
4857         u8         reserved_at_10[0x10];
4858
4859         u8         reserved_at_20[0x10];
4860         u8         op_mod[0x10];
4861
4862         u8         reserved_at_40[0x8];
4863         u8         tirn[0x18];
4864
4865         u8         reserved_at_60[0x20];
4866 };
4867
4868 struct mlx5_ifc_query_srq_out_bits {
4869         u8         status[0x8];
4870         u8         reserved_at_8[0x18];
4871
4872         u8         syndrome[0x20];
4873
4874         u8         reserved_at_40[0x40];
4875
4876         struct mlx5_ifc_srqc_bits srq_context_entry;
4877
4878         u8         reserved_at_280[0x600];
4879
4880         u8         pas[][0x40];
4881 };
4882
4883 struct mlx5_ifc_query_srq_in_bits {
4884         u8         opcode[0x10];
4885         u8         reserved_at_10[0x10];
4886
4887         u8         reserved_at_20[0x10];
4888         u8         op_mod[0x10];
4889
4890         u8         reserved_at_40[0x8];
4891         u8         srqn[0x18];
4892
4893         u8         reserved_at_60[0x20];
4894 };
4895
4896 struct mlx5_ifc_query_sq_out_bits {
4897         u8         status[0x8];
4898         u8         reserved_at_8[0x18];
4899
4900         u8         syndrome[0x20];
4901
4902         u8         reserved_at_40[0xc0];
4903
4904         struct mlx5_ifc_sqc_bits sq_context;
4905 };
4906
4907 struct mlx5_ifc_query_sq_in_bits {
4908         u8         opcode[0x10];
4909         u8         reserved_at_10[0x10];
4910
4911         u8         reserved_at_20[0x10];
4912         u8         op_mod[0x10];
4913
4914         u8         reserved_at_40[0x8];
4915         u8         sqn[0x18];
4916
4917         u8         reserved_at_60[0x20];
4918 };
4919
4920 struct mlx5_ifc_query_special_contexts_out_bits {
4921         u8         status[0x8];
4922         u8         reserved_at_8[0x18];
4923
4924         u8         syndrome[0x20];
4925
4926         u8         dump_fill_mkey[0x20];
4927
4928         u8         resd_lkey[0x20];
4929
4930         u8         null_mkey[0x20];
4931
4932         u8         reserved_at_a0[0x60];
4933 };
4934
4935 struct mlx5_ifc_query_special_contexts_in_bits {
4936         u8         opcode[0x10];
4937         u8         reserved_at_10[0x10];
4938
4939         u8         reserved_at_20[0x10];
4940         u8         op_mod[0x10];
4941
4942         u8         reserved_at_40[0x40];
4943 };
4944
4945 struct mlx5_ifc_query_scheduling_element_out_bits {
4946         u8         opcode[0x10];
4947         u8         reserved_at_10[0x10];
4948
4949         u8         reserved_at_20[0x10];
4950         u8         op_mod[0x10];
4951
4952         u8         reserved_at_40[0xc0];
4953
4954         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4955
4956         u8         reserved_at_300[0x100];
4957 };
4958
4959 enum {
4960         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4961         SCHEDULING_HIERARCHY_NIC = 0x3,
4962 };
4963
4964 struct mlx5_ifc_query_scheduling_element_in_bits {
4965         u8         opcode[0x10];
4966         u8         reserved_at_10[0x10];
4967
4968         u8         reserved_at_20[0x10];
4969         u8         op_mod[0x10];
4970
4971         u8         scheduling_hierarchy[0x8];
4972         u8         reserved_at_48[0x18];
4973
4974         u8         scheduling_element_id[0x20];
4975
4976         u8         reserved_at_80[0x180];
4977 };
4978
4979 struct mlx5_ifc_query_rqt_out_bits {
4980         u8         status[0x8];
4981         u8         reserved_at_8[0x18];
4982
4983         u8         syndrome[0x20];
4984
4985         u8         reserved_at_40[0xc0];
4986
4987         struct mlx5_ifc_rqtc_bits rqt_context;
4988 };
4989
4990 struct mlx5_ifc_query_rqt_in_bits {
4991         u8         opcode[0x10];
4992         u8         reserved_at_10[0x10];
4993
4994         u8         reserved_at_20[0x10];
4995         u8         op_mod[0x10];
4996
4997         u8         reserved_at_40[0x8];
4998         u8         rqtn[0x18];
4999
5000         u8         reserved_at_60[0x20];
5001 };
5002
5003 struct mlx5_ifc_query_rq_out_bits {
5004         u8         status[0x8];
5005         u8         reserved_at_8[0x18];
5006
5007         u8         syndrome[0x20];
5008
5009         u8         reserved_at_40[0xc0];
5010
5011         struct mlx5_ifc_rqc_bits rq_context;
5012 };
5013
5014 struct mlx5_ifc_query_rq_in_bits {
5015         u8         opcode[0x10];
5016         u8         reserved_at_10[0x10];
5017
5018         u8         reserved_at_20[0x10];
5019         u8         op_mod[0x10];
5020
5021         u8         reserved_at_40[0x8];
5022         u8         rqn[0x18];
5023
5024         u8         reserved_at_60[0x20];
5025 };
5026
5027 struct mlx5_ifc_query_roce_address_out_bits {
5028         u8         status[0x8];
5029         u8         reserved_at_8[0x18];
5030
5031         u8         syndrome[0x20];
5032
5033         u8         reserved_at_40[0x40];
5034
5035         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5036 };
5037
5038 struct mlx5_ifc_query_roce_address_in_bits {
5039         u8         opcode[0x10];
5040         u8         reserved_at_10[0x10];
5041
5042         u8         reserved_at_20[0x10];
5043         u8         op_mod[0x10];
5044
5045         u8         roce_address_index[0x10];
5046         u8         reserved_at_50[0xc];
5047         u8         vhca_port_num[0x4];
5048
5049         u8         reserved_at_60[0x20];
5050 };
5051
5052 struct mlx5_ifc_query_rmp_out_bits {
5053         u8         status[0x8];
5054         u8         reserved_at_8[0x18];
5055
5056         u8         syndrome[0x20];
5057
5058         u8         reserved_at_40[0xc0];
5059
5060         struct mlx5_ifc_rmpc_bits rmp_context;
5061 };
5062
5063 struct mlx5_ifc_query_rmp_in_bits {
5064         u8         opcode[0x10];
5065         u8         reserved_at_10[0x10];
5066
5067         u8         reserved_at_20[0x10];
5068         u8         op_mod[0x10];
5069
5070         u8         reserved_at_40[0x8];
5071         u8         rmpn[0x18];
5072
5073         u8         reserved_at_60[0x20];
5074 };
5075
5076 struct mlx5_ifc_query_qp_out_bits {
5077         u8         status[0x8];
5078         u8         reserved_at_8[0x18];
5079
5080         u8         syndrome[0x20];
5081
5082         u8         reserved_at_40[0x20];
5083         u8         ece[0x20];
5084
5085         u8         opt_param_mask[0x20];
5086
5087         u8         reserved_at_a0[0x20];
5088
5089         struct mlx5_ifc_qpc_bits qpc;
5090
5091         u8         reserved_at_800[0x80];
5092
5093         u8         pas[][0x40];
5094 };
5095
5096 struct mlx5_ifc_query_qp_in_bits {
5097         u8         opcode[0x10];
5098         u8         reserved_at_10[0x10];
5099
5100         u8         reserved_at_20[0x10];
5101         u8         op_mod[0x10];
5102
5103         u8         reserved_at_40[0x8];
5104         u8         qpn[0x18];
5105
5106         u8         reserved_at_60[0x20];
5107 };
5108
5109 struct mlx5_ifc_query_q_counter_out_bits {
5110         u8         status[0x8];
5111         u8         reserved_at_8[0x18];
5112
5113         u8         syndrome[0x20];
5114
5115         u8         reserved_at_40[0x40];
5116
5117         u8         rx_write_requests[0x20];
5118
5119         u8         reserved_at_a0[0x20];
5120
5121         u8         rx_read_requests[0x20];
5122
5123         u8         reserved_at_e0[0x20];
5124
5125         u8         rx_atomic_requests[0x20];
5126
5127         u8         reserved_at_120[0x20];
5128
5129         u8         rx_dct_connect[0x20];
5130
5131         u8         reserved_at_160[0x20];
5132
5133         u8         out_of_buffer[0x20];
5134
5135         u8         reserved_at_1a0[0x20];
5136
5137         u8         out_of_sequence[0x20];
5138
5139         u8         reserved_at_1e0[0x20];
5140
5141         u8         duplicate_request[0x20];
5142
5143         u8         reserved_at_220[0x20];
5144
5145         u8         rnr_nak_retry_err[0x20];
5146
5147         u8         reserved_at_260[0x20];
5148
5149         u8         packet_seq_err[0x20];
5150
5151         u8         reserved_at_2a0[0x20];
5152
5153         u8         implied_nak_seq_err[0x20];
5154
5155         u8         reserved_at_2e0[0x20];
5156
5157         u8         local_ack_timeout_err[0x20];
5158
5159         u8         reserved_at_320[0xa0];
5160
5161         u8         resp_local_length_error[0x20];
5162
5163         u8         req_local_length_error[0x20];
5164
5165         u8         resp_local_qp_error[0x20];
5166
5167         u8         local_operation_error[0x20];
5168
5169         u8         resp_local_protection[0x20];
5170
5171         u8         req_local_protection[0x20];
5172
5173         u8         resp_cqe_error[0x20];
5174
5175         u8         req_cqe_error[0x20];
5176
5177         u8         req_mw_binding[0x20];
5178
5179         u8         req_bad_response[0x20];
5180
5181         u8         req_remote_invalid_request[0x20];
5182
5183         u8         resp_remote_invalid_request[0x20];
5184
5185         u8         req_remote_access_errors[0x20];
5186
5187         u8         resp_remote_access_errors[0x20];
5188
5189         u8         req_remote_operation_errors[0x20];
5190
5191         u8         req_transport_retries_exceeded[0x20];
5192
5193         u8         cq_overflow[0x20];
5194
5195         u8         resp_cqe_flush_error[0x20];
5196
5197         u8         req_cqe_flush_error[0x20];
5198
5199         u8         reserved_at_620[0x20];
5200
5201         u8         roce_adp_retrans[0x20];
5202
5203         u8         roce_adp_retrans_to[0x20];
5204
5205         u8         roce_slow_restart[0x20];
5206
5207         u8         roce_slow_restart_cnps[0x20];
5208
5209         u8         roce_slow_restart_trans[0x20];
5210
5211         u8         reserved_at_6e0[0x120];
5212 };
5213
5214 struct mlx5_ifc_query_q_counter_in_bits {
5215         u8         opcode[0x10];
5216         u8         reserved_at_10[0x10];
5217
5218         u8         reserved_at_20[0x10];
5219         u8         op_mod[0x10];
5220
5221         u8         reserved_at_40[0x80];
5222
5223         u8         clear[0x1];
5224         u8         reserved_at_c1[0x1f];
5225
5226         u8         reserved_at_e0[0x18];
5227         u8         counter_set_id[0x8];
5228 };
5229
5230 struct mlx5_ifc_query_pages_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         embedded_cpu_function[0x1];
5237         u8         reserved_at_41[0xf];
5238         u8         function_id[0x10];
5239
5240         u8         num_pages[0x20];
5241 };
5242
5243 enum {
5244         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5245         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5246         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5247 };
5248
5249 struct mlx5_ifc_query_pages_in_bits {
5250         u8         opcode[0x10];
5251         u8         reserved_at_10[0x10];
5252
5253         u8         reserved_at_20[0x10];
5254         u8         op_mod[0x10];
5255
5256         u8         embedded_cpu_function[0x1];
5257         u8         reserved_at_41[0xf];
5258         u8         function_id[0x10];
5259
5260         u8         reserved_at_60[0x20];
5261 };
5262
5263 struct mlx5_ifc_query_nic_vport_context_out_bits {
5264         u8         status[0x8];
5265         u8         reserved_at_8[0x18];
5266
5267         u8         syndrome[0x20];
5268
5269         u8         reserved_at_40[0x40];
5270
5271         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5272 };
5273
5274 struct mlx5_ifc_query_nic_vport_context_in_bits {
5275         u8         opcode[0x10];
5276         u8         reserved_at_10[0x10];
5277
5278         u8         reserved_at_20[0x10];
5279         u8         op_mod[0x10];
5280
5281         u8         other_vport[0x1];
5282         u8         reserved_at_41[0xf];
5283         u8         vport_number[0x10];
5284
5285         u8         reserved_at_60[0x5];
5286         u8         allowed_list_type[0x3];
5287         u8         reserved_at_68[0x18];
5288 };
5289
5290 struct mlx5_ifc_query_mkey_out_bits {
5291         u8         status[0x8];
5292         u8         reserved_at_8[0x18];
5293
5294         u8         syndrome[0x20];
5295
5296         u8         reserved_at_40[0x40];
5297
5298         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5299
5300         u8         reserved_at_280[0x600];
5301
5302         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5303
5304         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5305 };
5306
5307 struct mlx5_ifc_query_mkey_in_bits {
5308         u8         opcode[0x10];
5309         u8         reserved_at_10[0x10];
5310
5311         u8         reserved_at_20[0x10];
5312         u8         op_mod[0x10];
5313
5314         u8         reserved_at_40[0x8];
5315         u8         mkey_index[0x18];
5316
5317         u8         pg_access[0x1];
5318         u8         reserved_at_61[0x1f];
5319 };
5320
5321 struct mlx5_ifc_query_mad_demux_out_bits {
5322         u8         status[0x8];
5323         u8         reserved_at_8[0x18];
5324
5325         u8         syndrome[0x20];
5326
5327         u8         reserved_at_40[0x40];
5328
5329         u8         mad_dumux_parameters_block[0x20];
5330 };
5331
5332 struct mlx5_ifc_query_mad_demux_in_bits {
5333         u8         opcode[0x10];
5334         u8         reserved_at_10[0x10];
5335
5336         u8         reserved_at_20[0x10];
5337         u8         op_mod[0x10];
5338
5339         u8         reserved_at_40[0x40];
5340 };
5341
5342 struct mlx5_ifc_query_l2_table_entry_out_bits {
5343         u8         status[0x8];
5344         u8         reserved_at_8[0x18];
5345
5346         u8         syndrome[0x20];
5347
5348         u8         reserved_at_40[0xa0];
5349
5350         u8         reserved_at_e0[0x13];
5351         u8         vlan_valid[0x1];
5352         u8         vlan[0xc];
5353
5354         struct mlx5_ifc_mac_address_layout_bits mac_address;
5355
5356         u8         reserved_at_140[0xc0];
5357 };
5358
5359 struct mlx5_ifc_query_l2_table_entry_in_bits {
5360         u8         opcode[0x10];
5361         u8         reserved_at_10[0x10];
5362
5363         u8         reserved_at_20[0x10];
5364         u8         op_mod[0x10];
5365
5366         u8         reserved_at_40[0x60];
5367
5368         u8         reserved_at_a0[0x8];
5369         u8         table_index[0x18];
5370
5371         u8         reserved_at_c0[0x140];
5372 };
5373
5374 struct mlx5_ifc_query_issi_out_bits {
5375         u8         status[0x8];
5376         u8         reserved_at_8[0x18];
5377
5378         u8         syndrome[0x20];
5379
5380         u8         reserved_at_40[0x10];
5381         u8         current_issi[0x10];
5382
5383         u8         reserved_at_60[0xa0];
5384
5385         u8         reserved_at_100[76][0x8];
5386         u8         supported_issi_dw0[0x20];
5387 };
5388
5389 struct mlx5_ifc_query_issi_in_bits {
5390         u8         opcode[0x10];
5391         u8         reserved_at_10[0x10];
5392
5393         u8         reserved_at_20[0x10];
5394         u8         op_mod[0x10];
5395
5396         u8         reserved_at_40[0x40];
5397 };
5398
5399 struct mlx5_ifc_set_driver_version_out_bits {
5400         u8         status[0x8];
5401         u8         reserved_0[0x18];
5402
5403         u8         syndrome[0x20];
5404         u8         reserved_1[0x40];
5405 };
5406
5407 struct mlx5_ifc_set_driver_version_in_bits {
5408         u8         opcode[0x10];
5409         u8         reserved_0[0x10];
5410
5411         u8         reserved_1[0x10];
5412         u8         op_mod[0x10];
5413
5414         u8         reserved_2[0x40];
5415         u8         driver_version[64][0x8];
5416 };
5417
5418 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5419         u8         status[0x8];
5420         u8         reserved_at_8[0x18];
5421
5422         u8         syndrome[0x20];
5423
5424         u8         reserved_at_40[0x40];
5425
5426         struct mlx5_ifc_pkey_bits pkey[];
5427 };
5428
5429 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5430         u8         opcode[0x10];
5431         u8         reserved_at_10[0x10];
5432
5433         u8         reserved_at_20[0x10];
5434         u8         op_mod[0x10];
5435
5436         u8         other_vport[0x1];
5437         u8         reserved_at_41[0xb];
5438         u8         port_num[0x4];
5439         u8         vport_number[0x10];
5440
5441         u8         reserved_at_60[0x10];
5442         u8         pkey_index[0x10];
5443 };
5444
5445 enum {
5446         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5447         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5448         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5449 };
5450
5451 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5452         u8         status[0x8];
5453         u8         reserved_at_8[0x18];
5454
5455         u8         syndrome[0x20];
5456
5457         u8         reserved_at_40[0x20];
5458
5459         u8         gids_num[0x10];
5460         u8         reserved_at_70[0x10];
5461
5462         struct mlx5_ifc_array128_auto_bits gid[];
5463 };
5464
5465 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5466         u8         opcode[0x10];
5467         u8         reserved_at_10[0x10];
5468
5469         u8         reserved_at_20[0x10];
5470         u8         op_mod[0x10];
5471
5472         u8         other_vport[0x1];
5473         u8         reserved_at_41[0xb];
5474         u8         port_num[0x4];
5475         u8         vport_number[0x10];
5476
5477         u8         reserved_at_60[0x10];
5478         u8         gid_index[0x10];
5479 };
5480
5481 struct mlx5_ifc_query_hca_vport_context_out_bits {
5482         u8         status[0x8];
5483         u8         reserved_at_8[0x18];
5484
5485         u8         syndrome[0x20];
5486
5487         u8         reserved_at_40[0x40];
5488
5489         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5490 };
5491
5492 struct mlx5_ifc_query_hca_vport_context_in_bits {
5493         u8         opcode[0x10];
5494         u8         reserved_at_10[0x10];
5495
5496         u8         reserved_at_20[0x10];
5497         u8         op_mod[0x10];
5498
5499         u8         other_vport[0x1];
5500         u8         reserved_at_41[0xb];
5501         u8         port_num[0x4];
5502         u8         vport_number[0x10];
5503
5504         u8         reserved_at_60[0x20];
5505 };
5506
5507 struct mlx5_ifc_query_hca_cap_out_bits {
5508         u8         status[0x8];
5509         u8         reserved_at_8[0x18];
5510
5511         u8         syndrome[0x20];
5512
5513         u8         reserved_at_40[0x40];
5514
5515         union mlx5_ifc_hca_cap_union_bits capability;
5516 };
5517
5518 struct mlx5_ifc_query_hca_cap_in_bits {
5519         u8         opcode[0x10];
5520         u8         reserved_at_10[0x10];
5521
5522         u8         reserved_at_20[0x10];
5523         u8         op_mod[0x10];
5524
5525         u8         other_function[0x1];
5526         u8         reserved_at_41[0xf];
5527         u8         function_id[0x10];
5528
5529         u8         reserved_at_60[0x20];
5530 };
5531
5532 struct mlx5_ifc_other_hca_cap_bits {
5533         u8         roce[0x1];
5534         u8         reserved_at_1[0x27f];
5535 };
5536
5537 struct mlx5_ifc_query_other_hca_cap_out_bits {
5538         u8         status[0x8];
5539         u8         reserved_at_8[0x18];
5540
5541         u8         syndrome[0x20];
5542
5543         u8         reserved_at_40[0x40];
5544
5545         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5546 };
5547
5548 struct mlx5_ifc_query_other_hca_cap_in_bits {
5549         u8         opcode[0x10];
5550         u8         reserved_at_10[0x10];
5551
5552         u8         reserved_at_20[0x10];
5553         u8         op_mod[0x10];
5554
5555         u8         reserved_at_40[0x10];
5556         u8         function_id[0x10];
5557
5558         u8         reserved_at_60[0x20];
5559 };
5560
5561 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5562         u8         status[0x8];
5563         u8         reserved_at_8[0x18];
5564
5565         u8         syndrome[0x20];
5566
5567         u8         reserved_at_40[0x40];
5568 };
5569
5570 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5571         u8         opcode[0x10];
5572         u8         reserved_at_10[0x10];
5573
5574         u8         reserved_at_20[0x10];
5575         u8         op_mod[0x10];
5576
5577         u8         reserved_at_40[0x10];
5578         u8         function_id[0x10];
5579         u8         field_select[0x20];
5580
5581         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5582 };
5583
5584 struct mlx5_ifc_flow_table_context_bits {
5585         u8         reformat_en[0x1];
5586         u8         decap_en[0x1];
5587         u8         sw_owner[0x1];
5588         u8         termination_table[0x1];
5589         u8         table_miss_action[0x4];
5590         u8         level[0x8];
5591         u8         reserved_at_10[0x8];
5592         u8         log_size[0x8];
5593
5594         u8         reserved_at_20[0x8];
5595         u8         table_miss_id[0x18];
5596
5597         u8         reserved_at_40[0x8];
5598         u8         lag_master_next_table_id[0x18];
5599
5600         u8         reserved_at_60[0x60];
5601
5602         u8         sw_owner_icm_root_1[0x40];
5603
5604         u8         sw_owner_icm_root_0[0x40];
5605
5606 };
5607
5608 struct mlx5_ifc_query_flow_table_out_bits {
5609         u8         status[0x8];
5610         u8         reserved_at_8[0x18];
5611
5612         u8         syndrome[0x20];
5613
5614         u8         reserved_at_40[0x80];
5615
5616         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5617 };
5618
5619 struct mlx5_ifc_query_flow_table_in_bits {
5620         u8         opcode[0x10];
5621         u8         reserved_at_10[0x10];
5622
5623         u8         reserved_at_20[0x10];
5624         u8         op_mod[0x10];
5625
5626         u8         reserved_at_40[0x40];
5627
5628         u8         table_type[0x8];
5629         u8         reserved_at_88[0x18];
5630
5631         u8         reserved_at_a0[0x8];
5632         u8         table_id[0x18];
5633
5634         u8         reserved_at_c0[0x140];
5635 };
5636
5637 struct mlx5_ifc_query_fte_out_bits {
5638         u8         status[0x8];
5639         u8         reserved_at_8[0x18];
5640
5641         u8         syndrome[0x20];
5642
5643         u8         reserved_at_40[0x1c0];
5644
5645         struct mlx5_ifc_flow_context_bits flow_context;
5646 };
5647
5648 struct mlx5_ifc_query_fte_in_bits {
5649         u8         opcode[0x10];
5650         u8         reserved_at_10[0x10];
5651
5652         u8         reserved_at_20[0x10];
5653         u8         op_mod[0x10];
5654
5655         u8         reserved_at_40[0x40];
5656
5657         u8         table_type[0x8];
5658         u8         reserved_at_88[0x18];
5659
5660         u8         reserved_at_a0[0x8];
5661         u8         table_id[0x18];
5662
5663         u8         reserved_at_c0[0x40];
5664
5665         u8         flow_index[0x20];
5666
5667         u8         reserved_at_120[0xe0];
5668 };
5669
5670 struct mlx5_ifc_match_definer_format_0_bits {
5671         u8         reserved_at_0[0x100];
5672
5673         u8         metadata_reg_c_0[0x20];
5674
5675         u8         metadata_reg_c_1[0x20];
5676
5677         u8         outer_dmac_47_16[0x20];
5678
5679         u8         outer_dmac_15_0[0x10];
5680         u8         outer_ethertype[0x10];
5681
5682         u8         reserved_at_180[0x1];
5683         u8         sx_sniffer[0x1];
5684         u8         functional_lb[0x1];
5685         u8         outer_ip_frag[0x1];
5686         u8         outer_qp_type[0x2];
5687         u8         outer_encap_type[0x2];
5688         u8         port_number[0x2];
5689         u8         outer_l3_type[0x2];
5690         u8         outer_l4_type[0x2];
5691         u8         outer_first_vlan_type[0x2];
5692         u8         outer_first_vlan_prio[0x3];
5693         u8         outer_first_vlan_cfi[0x1];
5694         u8         outer_first_vlan_vid[0xc];
5695
5696         u8         outer_l4_type_ext[0x4];
5697         u8         reserved_at_1a4[0x2];
5698         u8         outer_ipsec_layer[0x2];
5699         u8         outer_l2_type[0x2];
5700         u8         force_lb[0x1];
5701         u8         outer_l2_ok[0x1];
5702         u8         outer_l3_ok[0x1];
5703         u8         outer_l4_ok[0x1];
5704         u8         outer_second_vlan_type[0x2];
5705         u8         outer_second_vlan_prio[0x3];
5706         u8         outer_second_vlan_cfi[0x1];
5707         u8         outer_second_vlan_vid[0xc];
5708
5709         u8         outer_smac_47_16[0x20];
5710
5711         u8         outer_smac_15_0[0x10];
5712         u8         inner_ipv4_checksum_ok[0x1];
5713         u8         inner_l4_checksum_ok[0x1];
5714         u8         outer_ipv4_checksum_ok[0x1];
5715         u8         outer_l4_checksum_ok[0x1];
5716         u8         inner_l3_ok[0x1];
5717         u8         inner_l4_ok[0x1];
5718         u8         outer_l3_ok_duplicate[0x1];
5719         u8         outer_l4_ok_duplicate[0x1];
5720         u8         outer_tcp_cwr[0x1];
5721         u8         outer_tcp_ece[0x1];
5722         u8         outer_tcp_urg[0x1];
5723         u8         outer_tcp_ack[0x1];
5724         u8         outer_tcp_psh[0x1];
5725         u8         outer_tcp_rst[0x1];
5726         u8         outer_tcp_syn[0x1];
5727         u8         outer_tcp_fin[0x1];
5728 };
5729
5730 struct mlx5_ifc_match_definer_format_22_bits {
5731         u8         reserved_at_0[0x100];
5732
5733         u8         outer_ip_src_addr[0x20];
5734
5735         u8         outer_ip_dest_addr[0x20];
5736
5737         u8         outer_l4_sport[0x10];
5738         u8         outer_l4_dport[0x10];
5739
5740         u8         reserved_at_160[0x1];
5741         u8         sx_sniffer[0x1];
5742         u8         functional_lb[0x1];
5743         u8         outer_ip_frag[0x1];
5744         u8         outer_qp_type[0x2];
5745         u8         outer_encap_type[0x2];
5746         u8         port_number[0x2];
5747         u8         outer_l3_type[0x2];
5748         u8         outer_l4_type[0x2];
5749         u8         outer_first_vlan_type[0x2];
5750         u8         outer_first_vlan_prio[0x3];
5751         u8         outer_first_vlan_cfi[0x1];
5752         u8         outer_first_vlan_vid[0xc];
5753
5754         u8         metadata_reg_c_0[0x20];
5755
5756         u8         outer_dmac_47_16[0x20];
5757
5758         u8         outer_smac_47_16[0x20];
5759
5760         u8         outer_smac_15_0[0x10];
5761         u8         outer_dmac_15_0[0x10];
5762 };
5763
5764 struct mlx5_ifc_match_definer_format_23_bits {
5765         u8         reserved_at_0[0x100];
5766
5767         u8         inner_ip_src_addr[0x20];
5768
5769         u8         inner_ip_dest_addr[0x20];
5770
5771         u8         inner_l4_sport[0x10];
5772         u8         inner_l4_dport[0x10];
5773
5774         u8         reserved_at_160[0x1];
5775         u8         sx_sniffer[0x1];
5776         u8         functional_lb[0x1];
5777         u8         inner_ip_frag[0x1];
5778         u8         inner_qp_type[0x2];
5779         u8         inner_encap_type[0x2];
5780         u8         port_number[0x2];
5781         u8         inner_l3_type[0x2];
5782         u8         inner_l4_type[0x2];
5783         u8         inner_first_vlan_type[0x2];
5784         u8         inner_first_vlan_prio[0x3];
5785         u8         inner_first_vlan_cfi[0x1];
5786         u8         inner_first_vlan_vid[0xc];
5787
5788         u8         tunnel_header_0[0x20];
5789
5790         u8         inner_dmac_47_16[0x20];
5791
5792         u8         inner_smac_47_16[0x20];
5793
5794         u8         inner_smac_15_0[0x10];
5795         u8         inner_dmac_15_0[0x10];
5796 };
5797
5798 struct mlx5_ifc_match_definer_format_29_bits {
5799         u8         reserved_at_0[0xc0];
5800
5801         u8         outer_ip_dest_addr[0x80];
5802
5803         u8         outer_ip_src_addr[0x80];
5804
5805         u8         outer_l4_sport[0x10];
5806         u8         outer_l4_dport[0x10];
5807
5808         u8         reserved_at_1e0[0x20];
5809 };
5810
5811 struct mlx5_ifc_match_definer_format_30_bits {
5812         u8         reserved_at_0[0xa0];
5813
5814         u8         outer_ip_dest_addr[0x80];
5815
5816         u8         outer_ip_src_addr[0x80];
5817
5818         u8         outer_dmac_47_16[0x20];
5819
5820         u8         outer_smac_47_16[0x20];
5821
5822         u8         outer_smac_15_0[0x10];
5823         u8         outer_dmac_15_0[0x10];
5824 };
5825
5826 struct mlx5_ifc_match_definer_format_31_bits {
5827         u8         reserved_at_0[0xc0];
5828
5829         u8         inner_ip_dest_addr[0x80];
5830
5831         u8         inner_ip_src_addr[0x80];
5832
5833         u8         inner_l4_sport[0x10];
5834         u8         inner_l4_dport[0x10];
5835
5836         u8         reserved_at_1e0[0x20];
5837 };
5838
5839 struct mlx5_ifc_match_definer_format_32_bits {
5840         u8         reserved_at_0[0xa0];
5841
5842         u8         inner_ip_dest_addr[0x80];
5843
5844         u8         inner_ip_src_addr[0x80];
5845
5846         u8         inner_dmac_47_16[0x20];
5847
5848         u8         inner_smac_47_16[0x20];
5849
5850         u8         inner_smac_15_0[0x10];
5851         u8         inner_dmac_15_0[0x10];
5852 };
5853
5854 struct mlx5_ifc_match_definer_bits {
5855         u8         modify_field_select[0x40];
5856
5857         u8         reserved_at_40[0x40];
5858
5859         u8         reserved_at_80[0x10];
5860         u8         format_id[0x10];
5861
5862         u8         reserved_at_a0[0x160];
5863
5864         u8         match_mask[16][0x20];
5865 };
5866
5867 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
5868         u8         opcode[0x10];
5869         u8         uid[0x10];
5870
5871         u8         vhca_tunnel_id[0x10];
5872         u8         obj_type[0x10];
5873
5874         u8         obj_id[0x20];
5875
5876         u8         reserved_at_60[0x20];
5877 };
5878
5879 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
5880         u8         status[0x8];
5881         u8         reserved_at_8[0x18];
5882
5883         u8         syndrome[0x20];
5884
5885         u8         obj_id[0x20];
5886
5887         u8         reserved_at_60[0x20];
5888 };
5889
5890 struct mlx5_ifc_create_match_definer_in_bits {
5891         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
5892
5893         struct mlx5_ifc_match_definer_bits obj_context;
5894 };
5895
5896 struct mlx5_ifc_create_match_definer_out_bits {
5897         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
5898 };
5899
5900 enum {
5901         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5902         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5903         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5904         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5905         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5906         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5907 };
5908
5909 struct mlx5_ifc_query_flow_group_out_bits {
5910         u8         status[0x8];
5911         u8         reserved_at_8[0x18];
5912
5913         u8         syndrome[0x20];
5914
5915         u8         reserved_at_40[0xa0];
5916
5917         u8         start_flow_index[0x20];
5918
5919         u8         reserved_at_100[0x20];
5920
5921         u8         end_flow_index[0x20];
5922
5923         u8         reserved_at_140[0xa0];
5924
5925         u8         reserved_at_1e0[0x18];
5926         u8         match_criteria_enable[0x8];
5927
5928         struct mlx5_ifc_fte_match_param_bits match_criteria;
5929
5930         u8         reserved_at_1200[0xe00];
5931 };
5932
5933 struct mlx5_ifc_query_flow_group_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x40];
5941
5942         u8         table_type[0x8];
5943         u8         reserved_at_88[0x18];
5944
5945         u8         reserved_at_a0[0x8];
5946         u8         table_id[0x18];
5947
5948         u8         group_id[0x20];
5949
5950         u8         reserved_at_e0[0x120];
5951 };
5952
5953 struct mlx5_ifc_query_flow_counter_out_bits {
5954         u8         status[0x8];
5955         u8         reserved_at_8[0x18];
5956
5957         u8         syndrome[0x20];
5958
5959         u8         reserved_at_40[0x40];
5960
5961         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5962 };
5963
5964 struct mlx5_ifc_query_flow_counter_in_bits {
5965         u8         opcode[0x10];
5966         u8         reserved_at_10[0x10];
5967
5968         u8         reserved_at_20[0x10];
5969         u8         op_mod[0x10];
5970
5971         u8         reserved_at_40[0x80];
5972
5973         u8         clear[0x1];
5974         u8         reserved_at_c1[0xf];
5975         u8         num_of_counters[0x10];
5976
5977         u8         flow_counter_id[0x20];
5978 };
5979
5980 struct mlx5_ifc_query_esw_vport_context_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_at_8[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_at_40[0x40];
5987
5988         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5989 };
5990
5991 struct mlx5_ifc_query_esw_vport_context_in_bits {
5992         u8         opcode[0x10];
5993         u8         reserved_at_10[0x10];
5994
5995         u8         reserved_at_20[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         other_vport[0x1];
5999         u8         reserved_at_41[0xf];
6000         u8         vport_number[0x10];
6001
6002         u8         reserved_at_60[0x20];
6003 };
6004
6005 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6006         u8         status[0x8];
6007         u8         reserved_at_8[0x18];
6008
6009         u8         syndrome[0x20];
6010
6011         u8         reserved_at_40[0x40];
6012 };
6013
6014 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6015         u8         reserved_at_0[0x1b];
6016         u8         fdb_to_vport_reg_c_id[0x1];
6017         u8         vport_cvlan_insert[0x1];
6018         u8         vport_svlan_insert[0x1];
6019         u8         vport_cvlan_strip[0x1];
6020         u8         vport_svlan_strip[0x1];
6021 };
6022
6023 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6024         u8         opcode[0x10];
6025         u8         reserved_at_10[0x10];
6026
6027         u8         reserved_at_20[0x10];
6028         u8         op_mod[0x10];
6029
6030         u8         other_vport[0x1];
6031         u8         reserved_at_41[0xf];
6032         u8         vport_number[0x10];
6033
6034         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6035
6036         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6037 };
6038
6039 struct mlx5_ifc_query_eq_out_bits {
6040         u8         status[0x8];
6041         u8         reserved_at_8[0x18];
6042
6043         u8         syndrome[0x20];
6044
6045         u8         reserved_at_40[0x40];
6046
6047         struct mlx5_ifc_eqc_bits eq_context_entry;
6048
6049         u8         reserved_at_280[0x40];
6050
6051         u8         event_bitmask[0x40];
6052
6053         u8         reserved_at_300[0x580];
6054
6055         u8         pas[][0x40];
6056 };
6057
6058 struct mlx5_ifc_query_eq_in_bits {
6059         u8         opcode[0x10];
6060         u8         reserved_at_10[0x10];
6061
6062         u8         reserved_at_20[0x10];
6063         u8         op_mod[0x10];
6064
6065         u8         reserved_at_40[0x18];
6066         u8         eq_number[0x8];
6067
6068         u8         reserved_at_60[0x20];
6069 };
6070
6071 struct mlx5_ifc_packet_reformat_context_in_bits {
6072         u8         reformat_type[0x8];
6073         u8         reserved_at_8[0x4];
6074         u8         reformat_param_0[0x4];
6075         u8         reserved_at_10[0x6];
6076         u8         reformat_data_size[0xa];
6077
6078         u8         reformat_param_1[0x8];
6079         u8         reserved_at_28[0x8];
6080         u8         reformat_data[2][0x8];
6081
6082         u8         more_reformat_data[][0x8];
6083 };
6084
6085 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6086         u8         status[0x8];
6087         u8         reserved_at_8[0x18];
6088
6089         u8         syndrome[0x20];
6090
6091         u8         reserved_at_40[0xa0];
6092
6093         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6094 };
6095
6096 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6097         u8         opcode[0x10];
6098         u8         reserved_at_10[0x10];
6099
6100         u8         reserved_at_20[0x10];
6101         u8         op_mod[0x10];
6102
6103         u8         packet_reformat_id[0x20];
6104
6105         u8         reserved_at_60[0xa0];
6106 };
6107
6108 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6109         u8         status[0x8];
6110         u8         reserved_at_8[0x18];
6111
6112         u8         syndrome[0x20];
6113
6114         u8         packet_reformat_id[0x20];
6115
6116         u8         reserved_at_60[0x20];
6117 };
6118
6119 enum {
6120         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6121         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6122         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6123 };
6124
6125 enum mlx5_reformat_ctx_type {
6126         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6127         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6128         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6129         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6130         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6131         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6132         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6133 };
6134
6135 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6136         u8         opcode[0x10];
6137         u8         reserved_at_10[0x10];
6138
6139         u8         reserved_at_20[0x10];
6140         u8         op_mod[0x10];
6141
6142         u8         reserved_at_40[0xa0];
6143
6144         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6145 };
6146
6147 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6148         u8         status[0x8];
6149         u8         reserved_at_8[0x18];
6150
6151         u8         syndrome[0x20];
6152
6153         u8         reserved_at_40[0x40];
6154 };
6155
6156 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6157         u8         opcode[0x10];
6158         u8         reserved_at_10[0x10];
6159
6160         u8         reserved_20[0x10];
6161         u8         op_mod[0x10];
6162
6163         u8         packet_reformat_id[0x20];
6164
6165         u8         reserved_60[0x20];
6166 };
6167
6168 struct mlx5_ifc_set_action_in_bits {
6169         u8         action_type[0x4];
6170         u8         field[0xc];
6171         u8         reserved_at_10[0x3];
6172         u8         offset[0x5];
6173         u8         reserved_at_18[0x3];
6174         u8         length[0x5];
6175
6176         u8         data[0x20];
6177 };
6178
6179 struct mlx5_ifc_add_action_in_bits {
6180         u8         action_type[0x4];
6181         u8         field[0xc];
6182         u8         reserved_at_10[0x10];
6183
6184         u8         data[0x20];
6185 };
6186
6187 struct mlx5_ifc_copy_action_in_bits {
6188         u8         action_type[0x4];
6189         u8         src_field[0xc];
6190         u8         reserved_at_10[0x3];
6191         u8         src_offset[0x5];
6192         u8         reserved_at_18[0x3];
6193         u8         length[0x5];
6194
6195         u8         reserved_at_20[0x4];
6196         u8         dst_field[0xc];
6197         u8         reserved_at_30[0x3];
6198         u8         dst_offset[0x5];
6199         u8         reserved_at_38[0x8];
6200 };
6201
6202 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6203         struct mlx5_ifc_set_action_in_bits  set_action_in;
6204         struct mlx5_ifc_add_action_in_bits  add_action_in;
6205         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6206         u8         reserved_at_0[0x40];
6207 };
6208
6209 enum {
6210         MLX5_ACTION_TYPE_SET   = 0x1,
6211         MLX5_ACTION_TYPE_ADD   = 0x2,
6212         MLX5_ACTION_TYPE_COPY  = 0x3,
6213 };
6214
6215 enum {
6216         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6217         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6218         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6219         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6220         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6221         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6222         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6223         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6224         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6225         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6226         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6227         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6228         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6229         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6230         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6231         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6232         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6233         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6234         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6235         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6236         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6237         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6238         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6239         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6240         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6241         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6242         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6243         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6244         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6245         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6246         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6247         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6248         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6249         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6250         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6251         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6252         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6253         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6254         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6255 };
6256
6257 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6258         u8         status[0x8];
6259         u8         reserved_at_8[0x18];
6260
6261         u8         syndrome[0x20];
6262
6263         u8         modify_header_id[0x20];
6264
6265         u8         reserved_at_60[0x20];
6266 };
6267
6268 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6269         u8         opcode[0x10];
6270         u8         reserved_at_10[0x10];
6271
6272         u8         reserved_at_20[0x10];
6273         u8         op_mod[0x10];
6274
6275         u8         reserved_at_40[0x20];
6276
6277         u8         table_type[0x8];
6278         u8         reserved_at_68[0x10];
6279         u8         num_of_actions[0x8];
6280
6281         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6282 };
6283
6284 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6285         u8         status[0x8];
6286         u8         reserved_at_8[0x18];
6287
6288         u8         syndrome[0x20];
6289
6290         u8         reserved_at_40[0x40];
6291 };
6292
6293 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6294         u8         opcode[0x10];
6295         u8         reserved_at_10[0x10];
6296
6297         u8         reserved_at_20[0x10];
6298         u8         op_mod[0x10];
6299
6300         u8         modify_header_id[0x20];
6301
6302         u8         reserved_at_60[0x20];
6303 };
6304
6305 struct mlx5_ifc_query_modify_header_context_in_bits {
6306         u8         opcode[0x10];
6307         u8         uid[0x10];
6308
6309         u8         reserved_at_20[0x10];
6310         u8         op_mod[0x10];
6311
6312         u8         modify_header_id[0x20];
6313
6314         u8         reserved_at_60[0xa0];
6315 };
6316
6317 struct mlx5_ifc_query_dct_out_bits {
6318         u8         status[0x8];
6319         u8         reserved_at_8[0x18];
6320
6321         u8         syndrome[0x20];
6322
6323         u8         reserved_at_40[0x40];
6324
6325         struct mlx5_ifc_dctc_bits dct_context_entry;
6326
6327         u8         reserved_at_280[0x180];
6328 };
6329
6330 struct mlx5_ifc_query_dct_in_bits {
6331         u8         opcode[0x10];
6332         u8         reserved_at_10[0x10];
6333
6334         u8         reserved_at_20[0x10];
6335         u8         op_mod[0x10];
6336
6337         u8         reserved_at_40[0x8];
6338         u8         dctn[0x18];
6339
6340         u8         reserved_at_60[0x20];
6341 };
6342
6343 struct mlx5_ifc_query_cq_out_bits {
6344         u8         status[0x8];
6345         u8         reserved_at_8[0x18];
6346
6347         u8         syndrome[0x20];
6348
6349         u8         reserved_at_40[0x40];
6350
6351         struct mlx5_ifc_cqc_bits cq_context;
6352
6353         u8         reserved_at_280[0x600];
6354
6355         u8         pas[][0x40];
6356 };
6357
6358 struct mlx5_ifc_query_cq_in_bits {
6359         u8         opcode[0x10];
6360         u8         reserved_at_10[0x10];
6361
6362         u8         reserved_at_20[0x10];
6363         u8         op_mod[0x10];
6364
6365         u8         reserved_at_40[0x8];
6366         u8         cqn[0x18];
6367
6368         u8         reserved_at_60[0x20];
6369 };
6370
6371 struct mlx5_ifc_query_cong_status_out_bits {
6372         u8         status[0x8];
6373         u8         reserved_at_8[0x18];
6374
6375         u8         syndrome[0x20];
6376
6377         u8         reserved_at_40[0x20];
6378
6379         u8         enable[0x1];
6380         u8         tag_enable[0x1];
6381         u8         reserved_at_62[0x1e];
6382 };
6383
6384 struct mlx5_ifc_query_cong_status_in_bits {
6385         u8         opcode[0x10];
6386         u8         reserved_at_10[0x10];
6387
6388         u8         reserved_at_20[0x10];
6389         u8         op_mod[0x10];
6390
6391         u8         reserved_at_40[0x18];
6392         u8         priority[0x4];
6393         u8         cong_protocol[0x4];
6394
6395         u8         reserved_at_60[0x20];
6396 };
6397
6398 struct mlx5_ifc_query_cong_statistics_out_bits {
6399         u8         status[0x8];
6400         u8         reserved_at_8[0x18];
6401
6402         u8         syndrome[0x20];
6403
6404         u8         reserved_at_40[0x40];
6405
6406         u8         rp_cur_flows[0x20];
6407
6408         u8         sum_flows[0x20];
6409
6410         u8         rp_cnp_ignored_high[0x20];
6411
6412         u8         rp_cnp_ignored_low[0x20];
6413
6414         u8         rp_cnp_handled_high[0x20];
6415
6416         u8         rp_cnp_handled_low[0x20];
6417
6418         u8         reserved_at_140[0x100];
6419
6420         u8         time_stamp_high[0x20];
6421
6422         u8         time_stamp_low[0x20];
6423
6424         u8         accumulators_period[0x20];
6425
6426         u8         np_ecn_marked_roce_packets_high[0x20];
6427
6428         u8         np_ecn_marked_roce_packets_low[0x20];
6429
6430         u8         np_cnp_sent_high[0x20];
6431
6432         u8         np_cnp_sent_low[0x20];
6433
6434         u8         reserved_at_320[0x560];
6435 };
6436
6437 struct mlx5_ifc_query_cong_statistics_in_bits {
6438         u8         opcode[0x10];
6439         u8         reserved_at_10[0x10];
6440
6441         u8         reserved_at_20[0x10];
6442         u8         op_mod[0x10];
6443
6444         u8         clear[0x1];
6445         u8         reserved_at_41[0x1f];
6446
6447         u8         reserved_at_60[0x20];
6448 };
6449
6450 struct mlx5_ifc_query_cong_params_out_bits {
6451         u8         status[0x8];
6452         u8         reserved_at_8[0x18];
6453
6454         u8         syndrome[0x20];
6455
6456         u8         reserved_at_40[0x40];
6457
6458         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6459 };
6460
6461 struct mlx5_ifc_query_cong_params_in_bits {
6462         u8         opcode[0x10];
6463         u8         reserved_at_10[0x10];
6464
6465         u8         reserved_at_20[0x10];
6466         u8         op_mod[0x10];
6467
6468         u8         reserved_at_40[0x1c];
6469         u8         cong_protocol[0x4];
6470
6471         u8         reserved_at_60[0x20];
6472 };
6473
6474 struct mlx5_ifc_query_adapter_out_bits {
6475         u8         status[0x8];
6476         u8         reserved_at_8[0x18];
6477
6478         u8         syndrome[0x20];
6479
6480         u8         reserved_at_40[0x40];
6481
6482         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6483 };
6484
6485 struct mlx5_ifc_query_adapter_in_bits {
6486         u8         opcode[0x10];
6487         u8         reserved_at_10[0x10];
6488
6489         u8         reserved_at_20[0x10];
6490         u8         op_mod[0x10];
6491
6492         u8         reserved_at_40[0x40];
6493 };
6494
6495 struct mlx5_ifc_qp_2rst_out_bits {
6496         u8         status[0x8];
6497         u8         reserved_at_8[0x18];
6498
6499         u8         syndrome[0x20];
6500
6501         u8         reserved_at_40[0x40];
6502 };
6503
6504 struct mlx5_ifc_qp_2rst_in_bits {
6505         u8         opcode[0x10];
6506         u8         uid[0x10];
6507
6508         u8         reserved_at_20[0x10];
6509         u8         op_mod[0x10];
6510
6511         u8         reserved_at_40[0x8];
6512         u8         qpn[0x18];
6513
6514         u8         reserved_at_60[0x20];
6515 };
6516
6517 struct mlx5_ifc_qp_2err_out_bits {
6518         u8         status[0x8];
6519         u8         reserved_at_8[0x18];
6520
6521         u8         syndrome[0x20];
6522
6523         u8         reserved_at_40[0x40];
6524 };
6525
6526 struct mlx5_ifc_qp_2err_in_bits {
6527         u8         opcode[0x10];
6528         u8         uid[0x10];
6529
6530         u8         reserved_at_20[0x10];
6531         u8         op_mod[0x10];
6532
6533         u8         reserved_at_40[0x8];
6534         u8         qpn[0x18];
6535
6536         u8         reserved_at_60[0x20];
6537 };
6538
6539 struct mlx5_ifc_page_fault_resume_out_bits {
6540         u8         status[0x8];
6541         u8         reserved_at_8[0x18];
6542
6543         u8         syndrome[0x20];
6544
6545         u8         reserved_at_40[0x40];
6546 };
6547
6548 struct mlx5_ifc_page_fault_resume_in_bits {
6549         u8         opcode[0x10];
6550         u8         reserved_at_10[0x10];
6551
6552         u8         reserved_at_20[0x10];
6553         u8         op_mod[0x10];
6554
6555         u8         error[0x1];
6556         u8         reserved_at_41[0x4];
6557         u8         page_fault_type[0x3];
6558         u8         wq_number[0x18];
6559
6560         u8         reserved_at_60[0x8];
6561         u8         token[0x18];
6562 };
6563
6564 struct mlx5_ifc_nop_out_bits {
6565         u8         status[0x8];
6566         u8         reserved_at_8[0x18];
6567
6568         u8         syndrome[0x20];
6569
6570         u8         reserved_at_40[0x40];
6571 };
6572
6573 struct mlx5_ifc_nop_in_bits {
6574         u8         opcode[0x10];
6575         u8         reserved_at_10[0x10];
6576
6577         u8         reserved_at_20[0x10];
6578         u8         op_mod[0x10];
6579
6580         u8         reserved_at_40[0x40];
6581 };
6582
6583 struct mlx5_ifc_modify_vport_state_out_bits {
6584         u8         status[0x8];
6585         u8         reserved_at_8[0x18];
6586
6587         u8         syndrome[0x20];
6588
6589         u8         reserved_at_40[0x40];
6590 };
6591
6592 struct mlx5_ifc_modify_vport_state_in_bits {
6593         u8         opcode[0x10];
6594         u8         reserved_at_10[0x10];
6595
6596         u8         reserved_at_20[0x10];
6597         u8         op_mod[0x10];
6598
6599         u8         other_vport[0x1];
6600         u8         reserved_at_41[0xf];
6601         u8         vport_number[0x10];
6602
6603         u8         reserved_at_60[0x18];
6604         u8         admin_state[0x4];
6605         u8         reserved_at_7c[0x4];
6606 };
6607
6608 struct mlx5_ifc_modify_tis_out_bits {
6609         u8         status[0x8];
6610         u8         reserved_at_8[0x18];
6611
6612         u8         syndrome[0x20];
6613
6614         u8         reserved_at_40[0x40];
6615 };
6616
6617 struct mlx5_ifc_modify_tis_bitmask_bits {
6618         u8         reserved_at_0[0x20];
6619
6620         u8         reserved_at_20[0x1d];
6621         u8         lag_tx_port_affinity[0x1];
6622         u8         strict_lag_tx_port_affinity[0x1];
6623         u8         prio[0x1];
6624 };
6625
6626 struct mlx5_ifc_modify_tis_in_bits {
6627         u8         opcode[0x10];
6628         u8         uid[0x10];
6629
6630         u8         reserved_at_20[0x10];
6631         u8         op_mod[0x10];
6632
6633         u8         reserved_at_40[0x8];
6634         u8         tisn[0x18];
6635
6636         u8         reserved_at_60[0x20];
6637
6638         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6639
6640         u8         reserved_at_c0[0x40];
6641
6642         struct mlx5_ifc_tisc_bits ctx;
6643 };
6644
6645 struct mlx5_ifc_modify_tir_bitmask_bits {
6646         u8         reserved_at_0[0x20];
6647
6648         u8         reserved_at_20[0x1b];
6649         u8         self_lb_en[0x1];
6650         u8         reserved_at_3c[0x1];
6651         u8         hash[0x1];
6652         u8         reserved_at_3e[0x1];
6653         u8         lro[0x1];
6654 };
6655
6656 struct mlx5_ifc_modify_tir_out_bits {
6657         u8         status[0x8];
6658         u8         reserved_at_8[0x18];
6659
6660         u8         syndrome[0x20];
6661
6662         u8         reserved_at_40[0x40];
6663 };
6664
6665 struct mlx5_ifc_modify_tir_in_bits {
6666         u8         opcode[0x10];
6667         u8         uid[0x10];
6668
6669         u8         reserved_at_20[0x10];
6670         u8         op_mod[0x10];
6671
6672         u8         reserved_at_40[0x8];
6673         u8         tirn[0x18];
6674
6675         u8         reserved_at_60[0x20];
6676
6677         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6678
6679         u8         reserved_at_c0[0x40];
6680
6681         struct mlx5_ifc_tirc_bits ctx;
6682 };
6683
6684 struct mlx5_ifc_modify_sq_out_bits {
6685         u8         status[0x8];
6686         u8         reserved_at_8[0x18];
6687
6688         u8         syndrome[0x20];
6689
6690         u8         reserved_at_40[0x40];
6691 };
6692
6693 struct mlx5_ifc_modify_sq_in_bits {
6694         u8         opcode[0x10];
6695         u8         uid[0x10];
6696
6697         u8         reserved_at_20[0x10];
6698         u8         op_mod[0x10];
6699
6700         u8         sq_state[0x4];
6701         u8         reserved_at_44[0x4];
6702         u8         sqn[0x18];
6703
6704         u8         reserved_at_60[0x20];
6705
6706         u8         modify_bitmask[0x40];
6707
6708         u8         reserved_at_c0[0x40];
6709
6710         struct mlx5_ifc_sqc_bits ctx;
6711 };
6712
6713 struct mlx5_ifc_modify_scheduling_element_out_bits {
6714         u8         status[0x8];
6715         u8         reserved_at_8[0x18];
6716
6717         u8         syndrome[0x20];
6718
6719         u8         reserved_at_40[0x1c0];
6720 };
6721
6722 enum {
6723         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6724         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6725 };
6726
6727 struct mlx5_ifc_modify_scheduling_element_in_bits {
6728         u8         opcode[0x10];
6729         u8         reserved_at_10[0x10];
6730
6731         u8         reserved_at_20[0x10];
6732         u8         op_mod[0x10];
6733
6734         u8         scheduling_hierarchy[0x8];
6735         u8         reserved_at_48[0x18];
6736
6737         u8         scheduling_element_id[0x20];
6738
6739         u8         reserved_at_80[0x20];
6740
6741         u8         modify_bitmask[0x20];
6742
6743         u8         reserved_at_c0[0x40];
6744
6745         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6746
6747         u8         reserved_at_300[0x100];
6748 };
6749
6750 struct mlx5_ifc_modify_rqt_out_bits {
6751         u8         status[0x8];
6752         u8         reserved_at_8[0x18];
6753
6754         u8         syndrome[0x20];
6755
6756         u8         reserved_at_40[0x40];
6757 };
6758
6759 struct mlx5_ifc_rqt_bitmask_bits {
6760         u8         reserved_at_0[0x20];
6761
6762         u8         reserved_at_20[0x1f];
6763         u8         rqn_list[0x1];
6764 };
6765
6766 struct mlx5_ifc_modify_rqt_in_bits {
6767         u8         opcode[0x10];
6768         u8         uid[0x10];
6769
6770         u8         reserved_at_20[0x10];
6771         u8         op_mod[0x10];
6772
6773         u8         reserved_at_40[0x8];
6774         u8         rqtn[0x18];
6775
6776         u8         reserved_at_60[0x20];
6777
6778         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6779
6780         u8         reserved_at_c0[0x40];
6781
6782         struct mlx5_ifc_rqtc_bits ctx;
6783 };
6784
6785 struct mlx5_ifc_modify_rq_out_bits {
6786         u8         status[0x8];
6787         u8         reserved_at_8[0x18];
6788
6789         u8         syndrome[0x20];
6790
6791         u8         reserved_at_40[0x40];
6792 };
6793
6794 enum {
6795         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6796         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6797         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6798 };
6799
6800 struct mlx5_ifc_modify_rq_in_bits {
6801         u8         opcode[0x10];
6802         u8         uid[0x10];
6803
6804         u8         reserved_at_20[0x10];
6805         u8         op_mod[0x10];
6806
6807         u8         rq_state[0x4];
6808         u8         reserved_at_44[0x4];
6809         u8         rqn[0x18];
6810
6811         u8         reserved_at_60[0x20];
6812
6813         u8         modify_bitmask[0x40];
6814
6815         u8         reserved_at_c0[0x40];
6816
6817         struct mlx5_ifc_rqc_bits ctx;
6818 };
6819
6820 struct mlx5_ifc_modify_rmp_out_bits {
6821         u8         status[0x8];
6822         u8         reserved_at_8[0x18];
6823
6824         u8         syndrome[0x20];
6825
6826         u8         reserved_at_40[0x40];
6827 };
6828
6829 struct mlx5_ifc_rmp_bitmask_bits {
6830         u8         reserved_at_0[0x20];
6831
6832         u8         reserved_at_20[0x1f];
6833         u8         lwm[0x1];
6834 };
6835
6836 struct mlx5_ifc_modify_rmp_in_bits {
6837         u8         opcode[0x10];
6838         u8         uid[0x10];
6839
6840         u8         reserved_at_20[0x10];
6841         u8         op_mod[0x10];
6842
6843         u8         rmp_state[0x4];
6844         u8         reserved_at_44[0x4];
6845         u8         rmpn[0x18];
6846
6847         u8         reserved_at_60[0x20];
6848
6849         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6850
6851         u8         reserved_at_c0[0x40];
6852
6853         struct mlx5_ifc_rmpc_bits ctx;
6854 };
6855
6856 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6857         u8         status[0x8];
6858         u8         reserved_at_8[0x18];
6859
6860         u8         syndrome[0x20];
6861
6862         u8         reserved_at_40[0x40];
6863 };
6864
6865 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6866         u8         reserved_at_0[0x12];
6867         u8         affiliation[0x1];
6868         u8         reserved_at_13[0x1];
6869         u8         disable_uc_local_lb[0x1];
6870         u8         disable_mc_local_lb[0x1];
6871         u8         node_guid[0x1];
6872         u8         port_guid[0x1];
6873         u8         min_inline[0x1];
6874         u8         mtu[0x1];
6875         u8         change_event[0x1];
6876         u8         promisc[0x1];
6877         u8         permanent_address[0x1];
6878         u8         addresses_list[0x1];
6879         u8         roce_en[0x1];
6880         u8         reserved_at_1f[0x1];
6881 };
6882
6883 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6884         u8         opcode[0x10];
6885         u8         reserved_at_10[0x10];
6886
6887         u8         reserved_at_20[0x10];
6888         u8         op_mod[0x10];
6889
6890         u8         other_vport[0x1];
6891         u8         reserved_at_41[0xf];
6892         u8         vport_number[0x10];
6893
6894         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6895
6896         u8         reserved_at_80[0x780];
6897
6898         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6899 };
6900
6901 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6902         u8         status[0x8];
6903         u8         reserved_at_8[0x18];
6904
6905         u8         syndrome[0x20];
6906
6907         u8         reserved_at_40[0x40];
6908 };
6909
6910 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6911         u8         opcode[0x10];
6912         u8         reserved_at_10[0x10];
6913
6914         u8         reserved_at_20[0x10];
6915         u8         op_mod[0x10];
6916
6917         u8         other_vport[0x1];
6918         u8         reserved_at_41[0xb];
6919         u8         port_num[0x4];
6920         u8         vport_number[0x10];
6921
6922         u8         reserved_at_60[0x20];
6923
6924         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6925 };
6926
6927 struct mlx5_ifc_modify_cq_out_bits {
6928         u8         status[0x8];
6929         u8         reserved_at_8[0x18];
6930
6931         u8         syndrome[0x20];
6932
6933         u8         reserved_at_40[0x40];
6934 };
6935
6936 enum {
6937         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6938         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6939 };
6940
6941 struct mlx5_ifc_modify_cq_in_bits {
6942         u8         opcode[0x10];
6943         u8         uid[0x10];
6944
6945         u8         reserved_at_20[0x10];
6946         u8         op_mod[0x10];
6947
6948         u8         reserved_at_40[0x8];
6949         u8         cqn[0x18];
6950
6951         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6952
6953         struct mlx5_ifc_cqc_bits cq_context;
6954
6955         u8         reserved_at_280[0x60];
6956
6957         u8         cq_umem_valid[0x1];
6958         u8         reserved_at_2e1[0x1f];
6959
6960         u8         reserved_at_300[0x580];
6961
6962         u8         pas[][0x40];
6963 };
6964
6965 struct mlx5_ifc_modify_cong_status_out_bits {
6966         u8         status[0x8];
6967         u8         reserved_at_8[0x18];
6968
6969         u8         syndrome[0x20];
6970
6971         u8         reserved_at_40[0x40];
6972 };
6973
6974 struct mlx5_ifc_modify_cong_status_in_bits {
6975         u8         opcode[0x10];
6976         u8         reserved_at_10[0x10];
6977
6978         u8         reserved_at_20[0x10];
6979         u8         op_mod[0x10];
6980
6981         u8         reserved_at_40[0x18];
6982         u8         priority[0x4];
6983         u8         cong_protocol[0x4];
6984
6985         u8         enable[0x1];
6986         u8         tag_enable[0x1];
6987         u8         reserved_at_62[0x1e];
6988 };
6989
6990 struct mlx5_ifc_modify_cong_params_out_bits {
6991         u8         status[0x8];
6992         u8         reserved_at_8[0x18];
6993
6994         u8         syndrome[0x20];
6995
6996         u8         reserved_at_40[0x40];
6997 };
6998
6999 struct mlx5_ifc_modify_cong_params_in_bits {
7000         u8         opcode[0x10];
7001         u8         reserved_at_10[0x10];
7002
7003         u8         reserved_at_20[0x10];
7004         u8         op_mod[0x10];
7005
7006         u8         reserved_at_40[0x1c];
7007         u8         cong_protocol[0x4];
7008
7009         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7010
7011         u8         reserved_at_80[0x80];
7012
7013         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7014 };
7015
7016 struct mlx5_ifc_manage_pages_out_bits {
7017         u8         status[0x8];
7018         u8         reserved_at_8[0x18];
7019
7020         u8         syndrome[0x20];
7021
7022         u8         output_num_entries[0x20];
7023
7024         u8         reserved_at_60[0x20];
7025
7026         u8         pas[][0x40];
7027 };
7028
7029 enum {
7030         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7031         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7032         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7033 };
7034
7035 struct mlx5_ifc_manage_pages_in_bits {
7036         u8         opcode[0x10];
7037         u8         reserved_at_10[0x10];
7038
7039         u8         reserved_at_20[0x10];
7040         u8         op_mod[0x10];
7041
7042         u8         embedded_cpu_function[0x1];
7043         u8         reserved_at_41[0xf];
7044         u8         function_id[0x10];
7045
7046         u8         input_num_entries[0x20];
7047
7048         u8         pas[][0x40];
7049 };
7050
7051 struct mlx5_ifc_mad_ifc_out_bits {
7052         u8         status[0x8];
7053         u8         reserved_at_8[0x18];
7054
7055         u8         syndrome[0x20];
7056
7057         u8         reserved_at_40[0x40];
7058
7059         u8         response_mad_packet[256][0x8];
7060 };
7061
7062 struct mlx5_ifc_mad_ifc_in_bits {
7063         u8         opcode[0x10];
7064         u8         reserved_at_10[0x10];
7065
7066         u8         reserved_at_20[0x10];
7067         u8         op_mod[0x10];
7068
7069         u8         remote_lid[0x10];
7070         u8         reserved_at_50[0x8];
7071         u8         port[0x8];
7072
7073         u8         reserved_at_60[0x20];
7074
7075         u8         mad[256][0x8];
7076 };
7077
7078 struct mlx5_ifc_init_hca_out_bits {
7079         u8         status[0x8];
7080         u8         reserved_at_8[0x18];
7081
7082         u8         syndrome[0x20];
7083
7084         u8         reserved_at_40[0x40];
7085 };
7086
7087 struct mlx5_ifc_init_hca_in_bits {
7088         u8         opcode[0x10];
7089         u8         reserved_at_10[0x10];
7090
7091         u8         reserved_at_20[0x10];
7092         u8         op_mod[0x10];
7093
7094         u8         reserved_at_40[0x40];
7095         u8         sw_owner_id[4][0x20];
7096 };
7097
7098 struct mlx5_ifc_init2rtr_qp_out_bits {
7099         u8         status[0x8];
7100         u8         reserved_at_8[0x18];
7101
7102         u8         syndrome[0x20];
7103
7104         u8         reserved_at_40[0x20];
7105         u8         ece[0x20];
7106 };
7107
7108 struct mlx5_ifc_init2rtr_qp_in_bits {
7109         u8         opcode[0x10];
7110         u8         uid[0x10];
7111
7112         u8         reserved_at_20[0x10];
7113         u8         op_mod[0x10];
7114
7115         u8         reserved_at_40[0x8];
7116         u8         qpn[0x18];
7117
7118         u8         reserved_at_60[0x20];
7119
7120         u8         opt_param_mask[0x20];
7121
7122         u8         ece[0x20];
7123
7124         struct mlx5_ifc_qpc_bits qpc;
7125
7126         u8         reserved_at_800[0x80];
7127 };
7128
7129 struct mlx5_ifc_init2init_qp_out_bits {
7130         u8         status[0x8];
7131         u8         reserved_at_8[0x18];
7132
7133         u8         syndrome[0x20];
7134
7135         u8         reserved_at_40[0x20];
7136         u8         ece[0x20];
7137 };
7138
7139 struct mlx5_ifc_init2init_qp_in_bits {
7140         u8         opcode[0x10];
7141         u8         uid[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         reserved_at_40[0x8];
7147         u8         qpn[0x18];
7148
7149         u8         reserved_at_60[0x20];
7150
7151         u8         opt_param_mask[0x20];
7152
7153         u8         ece[0x20];
7154
7155         struct mlx5_ifc_qpc_bits qpc;
7156
7157         u8         reserved_at_800[0x80];
7158 };
7159
7160 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7161         u8         status[0x8];
7162         u8         reserved_at_8[0x18];
7163
7164         u8         syndrome[0x20];
7165
7166         u8         reserved_at_40[0x40];
7167
7168         u8         packet_headers_log[128][0x8];
7169
7170         u8         packet_syndrome[64][0x8];
7171 };
7172
7173 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7174         u8         opcode[0x10];
7175         u8         reserved_at_10[0x10];
7176
7177         u8         reserved_at_20[0x10];
7178         u8         op_mod[0x10];
7179
7180         u8         reserved_at_40[0x40];
7181 };
7182
7183 struct mlx5_ifc_gen_eqe_in_bits {
7184         u8         opcode[0x10];
7185         u8         reserved_at_10[0x10];
7186
7187         u8         reserved_at_20[0x10];
7188         u8         op_mod[0x10];
7189
7190         u8         reserved_at_40[0x18];
7191         u8         eq_number[0x8];
7192
7193         u8         reserved_at_60[0x20];
7194
7195         u8         eqe[64][0x8];
7196 };
7197
7198 struct mlx5_ifc_gen_eq_out_bits {
7199         u8         status[0x8];
7200         u8         reserved_at_8[0x18];
7201
7202         u8         syndrome[0x20];
7203
7204         u8         reserved_at_40[0x40];
7205 };
7206
7207 struct mlx5_ifc_enable_hca_out_bits {
7208         u8         status[0x8];
7209         u8         reserved_at_8[0x18];
7210
7211         u8         syndrome[0x20];
7212
7213         u8         reserved_at_40[0x20];
7214 };
7215
7216 struct mlx5_ifc_enable_hca_in_bits {
7217         u8         opcode[0x10];
7218         u8         reserved_at_10[0x10];
7219
7220         u8         reserved_at_20[0x10];
7221         u8         op_mod[0x10];
7222
7223         u8         embedded_cpu_function[0x1];
7224         u8         reserved_at_41[0xf];
7225         u8         function_id[0x10];
7226
7227         u8         reserved_at_60[0x20];
7228 };
7229
7230 struct mlx5_ifc_drain_dct_out_bits {
7231         u8         status[0x8];
7232         u8         reserved_at_8[0x18];
7233
7234         u8         syndrome[0x20];
7235
7236         u8         reserved_at_40[0x40];
7237 };
7238
7239 struct mlx5_ifc_drain_dct_in_bits {
7240         u8         opcode[0x10];
7241         u8         uid[0x10];
7242
7243         u8         reserved_at_20[0x10];
7244         u8         op_mod[0x10];
7245
7246         u8         reserved_at_40[0x8];
7247         u8         dctn[0x18];
7248
7249         u8         reserved_at_60[0x20];
7250 };
7251
7252 struct mlx5_ifc_disable_hca_out_bits {
7253         u8         status[0x8];
7254         u8         reserved_at_8[0x18];
7255
7256         u8         syndrome[0x20];
7257
7258         u8         reserved_at_40[0x20];
7259 };
7260
7261 struct mlx5_ifc_disable_hca_in_bits {
7262         u8         opcode[0x10];
7263         u8         reserved_at_10[0x10];
7264
7265         u8         reserved_at_20[0x10];
7266         u8         op_mod[0x10];
7267
7268         u8         embedded_cpu_function[0x1];
7269         u8         reserved_at_41[0xf];
7270         u8         function_id[0x10];
7271
7272         u8         reserved_at_60[0x20];
7273 };
7274
7275 struct mlx5_ifc_detach_from_mcg_out_bits {
7276         u8         status[0x8];
7277         u8         reserved_at_8[0x18];
7278
7279         u8         syndrome[0x20];
7280
7281         u8         reserved_at_40[0x40];
7282 };
7283
7284 struct mlx5_ifc_detach_from_mcg_in_bits {
7285         u8         opcode[0x10];
7286         u8         uid[0x10];
7287
7288         u8         reserved_at_20[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         reserved_at_40[0x8];
7292         u8         qpn[0x18];
7293
7294         u8         reserved_at_60[0x20];
7295
7296         u8         multicast_gid[16][0x8];
7297 };
7298
7299 struct mlx5_ifc_destroy_xrq_out_bits {
7300         u8         status[0x8];
7301         u8         reserved_at_8[0x18];
7302
7303         u8         syndrome[0x20];
7304
7305         u8         reserved_at_40[0x40];
7306 };
7307
7308 struct mlx5_ifc_destroy_xrq_in_bits {
7309         u8         opcode[0x10];
7310         u8         uid[0x10];
7311
7312         u8         reserved_at_20[0x10];
7313         u8         op_mod[0x10];
7314
7315         u8         reserved_at_40[0x8];
7316         u8         xrqn[0x18];
7317
7318         u8         reserved_at_60[0x20];
7319 };
7320
7321 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7322         u8         status[0x8];
7323         u8         reserved_at_8[0x18];
7324
7325         u8         syndrome[0x20];
7326
7327         u8         reserved_at_40[0x40];
7328 };
7329
7330 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7331         u8         opcode[0x10];
7332         u8         uid[0x10];
7333
7334         u8         reserved_at_20[0x10];
7335         u8         op_mod[0x10];
7336
7337         u8         reserved_at_40[0x8];
7338         u8         xrc_srqn[0x18];
7339
7340         u8         reserved_at_60[0x20];
7341 };
7342
7343 struct mlx5_ifc_destroy_tis_out_bits {
7344         u8         status[0x8];
7345         u8         reserved_at_8[0x18];
7346
7347         u8         syndrome[0x20];
7348
7349         u8         reserved_at_40[0x40];
7350 };
7351
7352 struct mlx5_ifc_destroy_tis_in_bits {
7353         u8         opcode[0x10];
7354         u8         uid[0x10];
7355
7356         u8         reserved_at_20[0x10];
7357         u8         op_mod[0x10];
7358
7359         u8         reserved_at_40[0x8];
7360         u8         tisn[0x18];
7361
7362         u8         reserved_at_60[0x20];
7363 };
7364
7365 struct mlx5_ifc_destroy_tir_out_bits {
7366         u8         status[0x8];
7367         u8         reserved_at_8[0x18];
7368
7369         u8         syndrome[0x20];
7370
7371         u8         reserved_at_40[0x40];
7372 };
7373
7374 struct mlx5_ifc_destroy_tir_in_bits {
7375         u8         opcode[0x10];
7376         u8         uid[0x10];
7377
7378         u8         reserved_at_20[0x10];
7379         u8         op_mod[0x10];
7380
7381         u8         reserved_at_40[0x8];
7382         u8         tirn[0x18];
7383
7384         u8         reserved_at_60[0x20];
7385 };
7386
7387 struct mlx5_ifc_destroy_srq_out_bits {
7388         u8         status[0x8];
7389         u8         reserved_at_8[0x18];
7390
7391         u8         syndrome[0x20];
7392
7393         u8         reserved_at_40[0x40];
7394 };
7395
7396 struct mlx5_ifc_destroy_srq_in_bits {
7397         u8         opcode[0x10];
7398         u8         uid[0x10];
7399
7400         u8         reserved_at_20[0x10];
7401         u8         op_mod[0x10];
7402
7403         u8         reserved_at_40[0x8];
7404         u8         srqn[0x18];
7405
7406         u8         reserved_at_60[0x20];
7407 };
7408
7409 struct mlx5_ifc_destroy_sq_out_bits {
7410         u8         status[0x8];
7411         u8         reserved_at_8[0x18];
7412
7413         u8         syndrome[0x20];
7414
7415         u8         reserved_at_40[0x40];
7416 };
7417
7418 struct mlx5_ifc_destroy_sq_in_bits {
7419         u8         opcode[0x10];
7420         u8         uid[0x10];
7421
7422         u8         reserved_at_20[0x10];
7423         u8         op_mod[0x10];
7424
7425         u8         reserved_at_40[0x8];
7426         u8         sqn[0x18];
7427
7428         u8         reserved_at_60[0x20];
7429 };
7430
7431 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7432         u8         status[0x8];
7433         u8         reserved_at_8[0x18];
7434
7435         u8         syndrome[0x20];
7436
7437         u8         reserved_at_40[0x1c0];
7438 };
7439
7440 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7441         u8         opcode[0x10];
7442         u8         reserved_at_10[0x10];
7443
7444         u8         reserved_at_20[0x10];
7445         u8         op_mod[0x10];
7446
7447         u8         scheduling_hierarchy[0x8];
7448         u8         reserved_at_48[0x18];
7449
7450         u8         scheduling_element_id[0x20];
7451
7452         u8         reserved_at_80[0x180];
7453 };
7454
7455 struct mlx5_ifc_destroy_rqt_out_bits {
7456         u8         status[0x8];
7457         u8         reserved_at_8[0x18];
7458
7459         u8         syndrome[0x20];
7460
7461         u8         reserved_at_40[0x40];
7462 };
7463
7464 struct mlx5_ifc_destroy_rqt_in_bits {
7465         u8         opcode[0x10];
7466         u8         uid[0x10];
7467
7468         u8         reserved_at_20[0x10];
7469         u8         op_mod[0x10];
7470
7471         u8         reserved_at_40[0x8];
7472         u8         rqtn[0x18];
7473
7474         u8         reserved_at_60[0x20];
7475 };
7476
7477 struct mlx5_ifc_destroy_rq_out_bits {
7478         u8         status[0x8];
7479         u8         reserved_at_8[0x18];
7480
7481         u8         syndrome[0x20];
7482
7483         u8         reserved_at_40[0x40];
7484 };
7485
7486 struct mlx5_ifc_destroy_rq_in_bits {
7487         u8         opcode[0x10];
7488         u8         uid[0x10];
7489
7490         u8         reserved_at_20[0x10];
7491         u8         op_mod[0x10];
7492
7493         u8         reserved_at_40[0x8];
7494         u8         rqn[0x18];
7495
7496         u8         reserved_at_60[0x20];
7497 };
7498
7499 struct mlx5_ifc_set_delay_drop_params_in_bits {
7500         u8         opcode[0x10];
7501         u8         reserved_at_10[0x10];
7502
7503         u8         reserved_at_20[0x10];
7504         u8         op_mod[0x10];
7505
7506         u8         reserved_at_40[0x20];
7507
7508         u8         reserved_at_60[0x10];
7509         u8         delay_drop_timeout[0x10];
7510 };
7511
7512 struct mlx5_ifc_set_delay_drop_params_out_bits {
7513         u8         status[0x8];
7514         u8         reserved_at_8[0x18];
7515
7516         u8         syndrome[0x20];
7517
7518         u8         reserved_at_40[0x40];
7519 };
7520
7521 struct mlx5_ifc_destroy_rmp_out_bits {
7522         u8         status[0x8];
7523         u8         reserved_at_8[0x18];
7524
7525         u8         syndrome[0x20];
7526
7527         u8         reserved_at_40[0x40];
7528 };
7529
7530 struct mlx5_ifc_destroy_rmp_in_bits {
7531         u8         opcode[0x10];
7532         u8         uid[0x10];
7533
7534         u8         reserved_at_20[0x10];
7535         u8         op_mod[0x10];
7536
7537         u8         reserved_at_40[0x8];
7538         u8         rmpn[0x18];
7539
7540         u8         reserved_at_60[0x20];
7541 };
7542
7543 struct mlx5_ifc_destroy_qp_out_bits {
7544         u8         status[0x8];
7545         u8         reserved_at_8[0x18];
7546
7547         u8         syndrome[0x20];
7548
7549         u8         reserved_at_40[0x40];
7550 };
7551
7552 struct mlx5_ifc_destroy_qp_in_bits {
7553         u8         opcode[0x10];
7554         u8         uid[0x10];
7555
7556         u8         reserved_at_20[0x10];
7557         u8         op_mod[0x10];
7558
7559         u8         reserved_at_40[0x8];
7560         u8         qpn[0x18];
7561
7562         u8         reserved_at_60[0x20];
7563 };
7564
7565 struct mlx5_ifc_destroy_psv_out_bits {
7566         u8         status[0x8];
7567         u8         reserved_at_8[0x18];
7568
7569         u8         syndrome[0x20];
7570
7571         u8         reserved_at_40[0x40];
7572 };
7573
7574 struct mlx5_ifc_destroy_psv_in_bits {
7575         u8         opcode[0x10];
7576         u8         reserved_at_10[0x10];
7577
7578         u8         reserved_at_20[0x10];
7579         u8         op_mod[0x10];
7580
7581         u8         reserved_at_40[0x8];
7582         u8         psvn[0x18];
7583
7584         u8         reserved_at_60[0x20];
7585 };
7586
7587 struct mlx5_ifc_destroy_mkey_out_bits {
7588         u8         status[0x8];
7589         u8         reserved_at_8[0x18];
7590
7591         u8         syndrome[0x20];
7592
7593         u8         reserved_at_40[0x40];
7594 };
7595
7596 struct mlx5_ifc_destroy_mkey_in_bits {
7597         u8         opcode[0x10];
7598         u8         uid[0x10];
7599
7600         u8         reserved_at_20[0x10];
7601         u8         op_mod[0x10];
7602
7603         u8         reserved_at_40[0x8];
7604         u8         mkey_index[0x18];
7605
7606         u8         reserved_at_60[0x20];
7607 };
7608
7609 struct mlx5_ifc_destroy_flow_table_out_bits {
7610         u8         status[0x8];
7611         u8         reserved_at_8[0x18];
7612
7613         u8         syndrome[0x20];
7614
7615         u8         reserved_at_40[0x40];
7616 };
7617
7618 struct mlx5_ifc_destroy_flow_table_in_bits {
7619         u8         opcode[0x10];
7620         u8         reserved_at_10[0x10];
7621
7622         u8         reserved_at_20[0x10];
7623         u8         op_mod[0x10];
7624
7625         u8         other_vport[0x1];
7626         u8         reserved_at_41[0xf];
7627         u8         vport_number[0x10];
7628
7629         u8         reserved_at_60[0x20];
7630
7631         u8         table_type[0x8];
7632         u8         reserved_at_88[0x18];
7633
7634         u8         reserved_at_a0[0x8];
7635         u8         table_id[0x18];
7636
7637         u8         reserved_at_c0[0x140];
7638 };
7639
7640 struct mlx5_ifc_destroy_flow_group_out_bits {
7641         u8         status[0x8];
7642         u8         reserved_at_8[0x18];
7643
7644         u8         syndrome[0x20];
7645
7646         u8         reserved_at_40[0x40];
7647 };
7648
7649 struct mlx5_ifc_destroy_flow_group_in_bits {
7650         u8         opcode[0x10];
7651         u8         reserved_at_10[0x10];
7652
7653         u8         reserved_at_20[0x10];
7654         u8         op_mod[0x10];
7655
7656         u8         other_vport[0x1];
7657         u8         reserved_at_41[0xf];
7658         u8         vport_number[0x10];
7659
7660         u8         reserved_at_60[0x20];
7661
7662         u8         table_type[0x8];
7663         u8         reserved_at_88[0x18];
7664
7665         u8         reserved_at_a0[0x8];
7666         u8         table_id[0x18];
7667
7668         u8         group_id[0x20];
7669
7670         u8         reserved_at_e0[0x120];
7671 };
7672
7673 struct mlx5_ifc_destroy_eq_out_bits {
7674         u8         status[0x8];
7675         u8         reserved_at_8[0x18];
7676
7677         u8         syndrome[0x20];
7678
7679         u8         reserved_at_40[0x40];
7680 };
7681
7682 struct mlx5_ifc_destroy_eq_in_bits {
7683         u8         opcode[0x10];
7684         u8         reserved_at_10[0x10];
7685
7686         u8         reserved_at_20[0x10];
7687         u8         op_mod[0x10];
7688
7689         u8         reserved_at_40[0x18];
7690         u8         eq_number[0x8];
7691
7692         u8         reserved_at_60[0x20];
7693 };
7694
7695 struct mlx5_ifc_destroy_dct_out_bits {
7696         u8         status[0x8];
7697         u8         reserved_at_8[0x18];
7698
7699         u8         syndrome[0x20];
7700
7701         u8         reserved_at_40[0x40];
7702 };
7703
7704 struct mlx5_ifc_destroy_dct_in_bits {
7705         u8         opcode[0x10];
7706         u8         uid[0x10];
7707
7708         u8         reserved_at_20[0x10];
7709         u8         op_mod[0x10];
7710
7711         u8         reserved_at_40[0x8];
7712         u8         dctn[0x18];
7713
7714         u8         reserved_at_60[0x20];
7715 };
7716
7717 struct mlx5_ifc_destroy_cq_out_bits {
7718         u8         status[0x8];
7719         u8         reserved_at_8[0x18];
7720
7721         u8         syndrome[0x20];
7722
7723         u8         reserved_at_40[0x40];
7724 };
7725
7726 struct mlx5_ifc_destroy_cq_in_bits {
7727         u8         opcode[0x10];
7728         u8         uid[0x10];
7729
7730         u8         reserved_at_20[0x10];
7731         u8         op_mod[0x10];
7732
7733         u8         reserved_at_40[0x8];
7734         u8         cqn[0x18];
7735
7736         u8         reserved_at_60[0x20];
7737 };
7738
7739 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7740         u8         status[0x8];
7741         u8         reserved_at_8[0x18];
7742
7743         u8         syndrome[0x20];
7744
7745         u8         reserved_at_40[0x40];
7746 };
7747
7748 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7749         u8         opcode[0x10];
7750         u8         reserved_at_10[0x10];
7751
7752         u8         reserved_at_20[0x10];
7753         u8         op_mod[0x10];
7754
7755         u8         reserved_at_40[0x20];
7756
7757         u8         reserved_at_60[0x10];
7758         u8         vxlan_udp_port[0x10];
7759 };
7760
7761 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7762         u8         status[0x8];
7763         u8         reserved_at_8[0x18];
7764
7765         u8         syndrome[0x20];
7766
7767         u8         reserved_at_40[0x40];
7768 };
7769
7770 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7771         u8         opcode[0x10];
7772         u8         reserved_at_10[0x10];
7773
7774         u8         reserved_at_20[0x10];
7775         u8         op_mod[0x10];
7776
7777         u8         reserved_at_40[0x60];
7778
7779         u8         reserved_at_a0[0x8];
7780         u8         table_index[0x18];
7781
7782         u8         reserved_at_c0[0x140];
7783 };
7784
7785 struct mlx5_ifc_delete_fte_out_bits {
7786         u8         status[0x8];
7787         u8         reserved_at_8[0x18];
7788
7789         u8         syndrome[0x20];
7790
7791         u8         reserved_at_40[0x40];
7792 };
7793
7794 struct mlx5_ifc_delete_fte_in_bits {
7795         u8         opcode[0x10];
7796         u8         reserved_at_10[0x10];
7797
7798         u8         reserved_at_20[0x10];
7799         u8         op_mod[0x10];
7800
7801         u8         other_vport[0x1];
7802         u8         reserved_at_41[0xf];
7803         u8         vport_number[0x10];
7804
7805         u8         reserved_at_60[0x20];
7806
7807         u8         table_type[0x8];
7808         u8         reserved_at_88[0x18];
7809
7810         u8         reserved_at_a0[0x8];
7811         u8         table_id[0x18];
7812
7813         u8         reserved_at_c0[0x40];
7814
7815         u8         flow_index[0x20];
7816
7817         u8         reserved_at_120[0xe0];
7818 };
7819
7820 struct mlx5_ifc_dealloc_xrcd_out_bits {
7821         u8         status[0x8];
7822         u8         reserved_at_8[0x18];
7823
7824         u8         syndrome[0x20];
7825
7826         u8         reserved_at_40[0x40];
7827 };
7828
7829 struct mlx5_ifc_dealloc_xrcd_in_bits {
7830         u8         opcode[0x10];
7831         u8         uid[0x10];
7832
7833         u8         reserved_at_20[0x10];
7834         u8         op_mod[0x10];
7835
7836         u8         reserved_at_40[0x8];
7837         u8         xrcd[0x18];
7838
7839         u8         reserved_at_60[0x20];
7840 };
7841
7842 struct mlx5_ifc_dealloc_uar_out_bits {
7843         u8         status[0x8];
7844         u8         reserved_at_8[0x18];
7845
7846         u8         syndrome[0x20];
7847
7848         u8         reserved_at_40[0x40];
7849 };
7850
7851 struct mlx5_ifc_dealloc_uar_in_bits {
7852         u8         opcode[0x10];
7853         u8         reserved_at_10[0x10];
7854
7855         u8         reserved_at_20[0x10];
7856         u8         op_mod[0x10];
7857
7858         u8         reserved_at_40[0x8];
7859         u8         uar[0x18];
7860
7861         u8         reserved_at_60[0x20];
7862 };
7863
7864 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7865         u8         status[0x8];
7866         u8         reserved_at_8[0x18];
7867
7868         u8         syndrome[0x20];
7869
7870         u8         reserved_at_40[0x40];
7871 };
7872
7873 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7874         u8         opcode[0x10];
7875         u8         uid[0x10];
7876
7877         u8         reserved_at_20[0x10];
7878         u8         op_mod[0x10];
7879
7880         u8         reserved_at_40[0x8];
7881         u8         transport_domain[0x18];
7882
7883         u8         reserved_at_60[0x20];
7884 };
7885
7886 struct mlx5_ifc_dealloc_q_counter_out_bits {
7887         u8         status[0x8];
7888         u8         reserved_at_8[0x18];
7889
7890         u8         syndrome[0x20];
7891
7892         u8         reserved_at_40[0x40];
7893 };
7894
7895 struct mlx5_ifc_dealloc_q_counter_in_bits {
7896         u8         opcode[0x10];
7897         u8         reserved_at_10[0x10];
7898
7899         u8         reserved_at_20[0x10];
7900         u8         op_mod[0x10];
7901
7902         u8         reserved_at_40[0x18];
7903         u8         counter_set_id[0x8];
7904
7905         u8         reserved_at_60[0x20];
7906 };
7907
7908 struct mlx5_ifc_dealloc_pd_out_bits {
7909         u8         status[0x8];
7910         u8         reserved_at_8[0x18];
7911
7912         u8         syndrome[0x20];
7913
7914         u8         reserved_at_40[0x40];
7915 };
7916
7917 struct mlx5_ifc_dealloc_pd_in_bits {
7918         u8         opcode[0x10];
7919         u8         uid[0x10];
7920
7921         u8         reserved_at_20[0x10];
7922         u8         op_mod[0x10];
7923
7924         u8         reserved_at_40[0x8];
7925         u8         pd[0x18];
7926
7927         u8         reserved_at_60[0x20];
7928 };
7929
7930 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7931         u8         status[0x8];
7932         u8         reserved_at_8[0x18];
7933
7934         u8         syndrome[0x20];
7935
7936         u8         reserved_at_40[0x40];
7937 };
7938
7939 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7940         u8         opcode[0x10];
7941         u8         reserved_at_10[0x10];
7942
7943         u8         reserved_at_20[0x10];
7944         u8         op_mod[0x10];
7945
7946         u8         flow_counter_id[0x20];
7947
7948         u8         reserved_at_60[0x20];
7949 };
7950
7951 struct mlx5_ifc_create_xrq_out_bits {
7952         u8         status[0x8];
7953         u8         reserved_at_8[0x18];
7954
7955         u8         syndrome[0x20];
7956
7957         u8         reserved_at_40[0x8];
7958         u8         xrqn[0x18];
7959
7960         u8         reserved_at_60[0x20];
7961 };
7962
7963 struct mlx5_ifc_create_xrq_in_bits {
7964         u8         opcode[0x10];
7965         u8         uid[0x10];
7966
7967         u8         reserved_at_20[0x10];
7968         u8         op_mod[0x10];
7969
7970         u8         reserved_at_40[0x40];
7971
7972         struct mlx5_ifc_xrqc_bits xrq_context;
7973 };
7974
7975 struct mlx5_ifc_create_xrc_srq_out_bits {
7976         u8         status[0x8];
7977         u8         reserved_at_8[0x18];
7978
7979         u8         syndrome[0x20];
7980
7981         u8         reserved_at_40[0x8];
7982         u8         xrc_srqn[0x18];
7983
7984         u8         reserved_at_60[0x20];
7985 };
7986
7987 struct mlx5_ifc_create_xrc_srq_in_bits {
7988         u8         opcode[0x10];
7989         u8         uid[0x10];
7990
7991         u8         reserved_at_20[0x10];
7992         u8         op_mod[0x10];
7993
7994         u8         reserved_at_40[0x40];
7995
7996         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7997
7998         u8         reserved_at_280[0x60];
7999
8000         u8         xrc_srq_umem_valid[0x1];
8001         u8         reserved_at_2e1[0x1f];
8002
8003         u8         reserved_at_300[0x580];
8004
8005         u8         pas[][0x40];
8006 };
8007
8008 struct mlx5_ifc_create_tis_out_bits {
8009         u8         status[0x8];
8010         u8         reserved_at_8[0x18];
8011
8012         u8         syndrome[0x20];
8013
8014         u8         reserved_at_40[0x8];
8015         u8         tisn[0x18];
8016
8017         u8         reserved_at_60[0x20];
8018 };
8019
8020 struct mlx5_ifc_create_tis_in_bits {
8021         u8         opcode[0x10];
8022         u8         uid[0x10];
8023
8024         u8         reserved_at_20[0x10];
8025         u8         op_mod[0x10];
8026
8027         u8         reserved_at_40[0xc0];
8028
8029         struct mlx5_ifc_tisc_bits ctx;
8030 };
8031
8032 struct mlx5_ifc_create_tir_out_bits {
8033         u8         status[0x8];
8034         u8         icm_address_63_40[0x18];
8035
8036         u8         syndrome[0x20];
8037
8038         u8         icm_address_39_32[0x8];
8039         u8         tirn[0x18];
8040
8041         u8         icm_address_31_0[0x20];
8042 };
8043
8044 struct mlx5_ifc_create_tir_in_bits {
8045         u8         opcode[0x10];
8046         u8         uid[0x10];
8047
8048         u8         reserved_at_20[0x10];
8049         u8         op_mod[0x10];
8050
8051         u8         reserved_at_40[0xc0];
8052
8053         struct mlx5_ifc_tirc_bits ctx;
8054 };
8055
8056 struct mlx5_ifc_create_srq_out_bits {
8057         u8         status[0x8];
8058         u8         reserved_at_8[0x18];
8059
8060         u8         syndrome[0x20];
8061
8062         u8         reserved_at_40[0x8];
8063         u8         srqn[0x18];
8064
8065         u8         reserved_at_60[0x20];
8066 };
8067
8068 struct mlx5_ifc_create_srq_in_bits {
8069         u8         opcode[0x10];
8070         u8         uid[0x10];
8071
8072         u8         reserved_at_20[0x10];
8073         u8         op_mod[0x10];
8074
8075         u8         reserved_at_40[0x40];
8076
8077         struct mlx5_ifc_srqc_bits srq_context_entry;
8078
8079         u8         reserved_at_280[0x600];
8080
8081         u8         pas[][0x40];
8082 };
8083
8084 struct mlx5_ifc_create_sq_out_bits {
8085         u8         status[0x8];
8086         u8         reserved_at_8[0x18];
8087
8088         u8         syndrome[0x20];
8089
8090         u8         reserved_at_40[0x8];
8091         u8         sqn[0x18];
8092
8093         u8         reserved_at_60[0x20];
8094 };
8095
8096 struct mlx5_ifc_create_sq_in_bits {
8097         u8         opcode[0x10];
8098         u8         uid[0x10];
8099
8100         u8         reserved_at_20[0x10];
8101         u8         op_mod[0x10];
8102
8103         u8         reserved_at_40[0xc0];
8104
8105         struct mlx5_ifc_sqc_bits ctx;
8106 };
8107
8108 struct mlx5_ifc_create_scheduling_element_out_bits {
8109         u8         status[0x8];
8110         u8         reserved_at_8[0x18];
8111
8112         u8         syndrome[0x20];
8113
8114         u8         reserved_at_40[0x40];
8115
8116         u8         scheduling_element_id[0x20];
8117
8118         u8         reserved_at_a0[0x160];
8119 };
8120
8121 struct mlx5_ifc_create_scheduling_element_in_bits {
8122         u8         opcode[0x10];
8123         u8         reserved_at_10[0x10];
8124
8125         u8         reserved_at_20[0x10];
8126         u8         op_mod[0x10];
8127
8128         u8         scheduling_hierarchy[0x8];
8129         u8         reserved_at_48[0x18];
8130
8131         u8         reserved_at_60[0xa0];
8132
8133         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8134
8135         u8         reserved_at_300[0x100];
8136 };
8137
8138 struct mlx5_ifc_create_rqt_out_bits {
8139         u8         status[0x8];
8140         u8         reserved_at_8[0x18];
8141
8142         u8         syndrome[0x20];
8143
8144         u8         reserved_at_40[0x8];
8145         u8         rqtn[0x18];
8146
8147         u8         reserved_at_60[0x20];
8148 };
8149
8150 struct mlx5_ifc_create_rqt_in_bits {
8151         u8         opcode[0x10];
8152         u8         uid[0x10];
8153
8154         u8         reserved_at_20[0x10];
8155         u8         op_mod[0x10];
8156
8157         u8         reserved_at_40[0xc0];
8158
8159         struct mlx5_ifc_rqtc_bits rqt_context;
8160 };
8161
8162 struct mlx5_ifc_create_rq_out_bits {
8163         u8         status[0x8];
8164         u8         reserved_at_8[0x18];
8165
8166         u8         syndrome[0x20];
8167
8168         u8         reserved_at_40[0x8];
8169         u8         rqn[0x18];
8170
8171         u8         reserved_at_60[0x20];
8172 };
8173
8174 struct mlx5_ifc_create_rq_in_bits {
8175         u8         opcode[0x10];
8176         u8         uid[0x10];
8177
8178         u8         reserved_at_20[0x10];
8179         u8         op_mod[0x10];
8180
8181         u8         reserved_at_40[0xc0];
8182
8183         struct mlx5_ifc_rqc_bits ctx;
8184 };
8185
8186 struct mlx5_ifc_create_rmp_out_bits {
8187         u8         status[0x8];
8188         u8         reserved_at_8[0x18];
8189
8190         u8         syndrome[0x20];
8191
8192         u8         reserved_at_40[0x8];
8193         u8         rmpn[0x18];
8194
8195         u8         reserved_at_60[0x20];
8196 };
8197
8198 struct mlx5_ifc_create_rmp_in_bits {
8199         u8         opcode[0x10];
8200         u8         uid[0x10];
8201
8202         u8         reserved_at_20[0x10];
8203         u8         op_mod[0x10];
8204
8205         u8         reserved_at_40[0xc0];
8206
8207         struct mlx5_ifc_rmpc_bits ctx;
8208 };
8209
8210 struct mlx5_ifc_create_qp_out_bits {
8211         u8         status[0x8];
8212         u8         reserved_at_8[0x18];
8213
8214         u8         syndrome[0x20];
8215
8216         u8         reserved_at_40[0x8];
8217         u8         qpn[0x18];
8218
8219         u8         ece[0x20];
8220 };
8221
8222 struct mlx5_ifc_create_qp_in_bits {
8223         u8         opcode[0x10];
8224         u8         uid[0x10];
8225
8226         u8         reserved_at_20[0x10];
8227         u8         op_mod[0x10];
8228
8229         u8         reserved_at_40[0x8];
8230         u8         input_qpn[0x18];
8231
8232         u8         reserved_at_60[0x20];
8233         u8         opt_param_mask[0x20];
8234
8235         u8         ece[0x20];
8236
8237         struct mlx5_ifc_qpc_bits qpc;
8238
8239         u8         reserved_at_800[0x60];
8240
8241         u8         wq_umem_valid[0x1];
8242         u8         reserved_at_861[0x1f];
8243
8244         u8         pas[][0x40];
8245 };
8246
8247 struct mlx5_ifc_create_psv_out_bits {
8248         u8         status[0x8];
8249         u8         reserved_at_8[0x18];
8250
8251         u8         syndrome[0x20];
8252
8253         u8         reserved_at_40[0x40];
8254
8255         u8         reserved_at_80[0x8];
8256         u8         psv0_index[0x18];
8257
8258         u8         reserved_at_a0[0x8];
8259         u8         psv1_index[0x18];
8260
8261         u8         reserved_at_c0[0x8];
8262         u8         psv2_index[0x18];
8263
8264         u8         reserved_at_e0[0x8];
8265         u8         psv3_index[0x18];
8266 };
8267
8268 struct mlx5_ifc_create_psv_in_bits {
8269         u8         opcode[0x10];
8270         u8         reserved_at_10[0x10];
8271
8272         u8         reserved_at_20[0x10];
8273         u8         op_mod[0x10];
8274
8275         u8         num_psv[0x4];
8276         u8         reserved_at_44[0x4];
8277         u8         pd[0x18];
8278
8279         u8         reserved_at_60[0x20];
8280 };
8281
8282 struct mlx5_ifc_create_mkey_out_bits {
8283         u8         status[0x8];
8284         u8         reserved_at_8[0x18];
8285
8286         u8         syndrome[0x20];
8287
8288         u8         reserved_at_40[0x8];
8289         u8         mkey_index[0x18];
8290
8291         u8         reserved_at_60[0x20];
8292 };
8293
8294 struct mlx5_ifc_create_mkey_in_bits {
8295         u8         opcode[0x10];
8296         u8         uid[0x10];
8297
8298         u8         reserved_at_20[0x10];
8299         u8         op_mod[0x10];
8300
8301         u8         reserved_at_40[0x20];
8302
8303         u8         pg_access[0x1];
8304         u8         mkey_umem_valid[0x1];
8305         u8         reserved_at_62[0x1e];
8306
8307         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8308
8309         u8         reserved_at_280[0x80];
8310
8311         u8         translations_octword_actual_size[0x20];
8312
8313         u8         reserved_at_320[0x560];
8314
8315         u8         klm_pas_mtt[][0x20];
8316 };
8317
8318 enum {
8319         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8320         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8321         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8322         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8323         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8324         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8325         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8326 };
8327
8328 struct mlx5_ifc_create_flow_table_out_bits {
8329         u8         status[0x8];
8330         u8         icm_address_63_40[0x18];
8331
8332         u8         syndrome[0x20];
8333
8334         u8         icm_address_39_32[0x8];
8335         u8         table_id[0x18];
8336
8337         u8         icm_address_31_0[0x20];
8338 };
8339
8340 struct mlx5_ifc_create_flow_table_in_bits {
8341         u8         opcode[0x10];
8342         u8         reserved_at_10[0x10];
8343
8344         u8         reserved_at_20[0x10];
8345         u8         op_mod[0x10];
8346
8347         u8         other_vport[0x1];
8348         u8         reserved_at_41[0xf];
8349         u8         vport_number[0x10];
8350
8351         u8         reserved_at_60[0x20];
8352
8353         u8         table_type[0x8];
8354         u8         reserved_at_88[0x18];
8355
8356         u8         reserved_at_a0[0x20];
8357
8358         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8359 };
8360
8361 struct mlx5_ifc_create_flow_group_out_bits {
8362         u8         status[0x8];
8363         u8         reserved_at_8[0x18];
8364
8365         u8         syndrome[0x20];
8366
8367         u8         reserved_at_40[0x8];
8368         u8         group_id[0x18];
8369
8370         u8         reserved_at_60[0x20];
8371 };
8372
8373 enum {
8374         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8375         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8376 };
8377
8378 enum {
8379         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8380         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8381         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8382         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8383 };
8384
8385 struct mlx5_ifc_create_flow_group_in_bits {
8386         u8         opcode[0x10];
8387         u8         reserved_at_10[0x10];
8388
8389         u8         reserved_at_20[0x10];
8390         u8         op_mod[0x10];
8391
8392         u8         other_vport[0x1];
8393         u8         reserved_at_41[0xf];
8394         u8         vport_number[0x10];
8395
8396         u8         reserved_at_60[0x20];
8397
8398         u8         table_type[0x8];
8399         u8         reserved_at_88[0x4];
8400         u8         group_type[0x4];
8401         u8         reserved_at_90[0x10];
8402
8403         u8         reserved_at_a0[0x8];
8404         u8         table_id[0x18];
8405
8406         u8         source_eswitch_owner_vhca_id_valid[0x1];
8407
8408         u8         reserved_at_c1[0x1f];
8409
8410         u8         start_flow_index[0x20];
8411
8412         u8         reserved_at_100[0x20];
8413
8414         u8         end_flow_index[0x20];
8415
8416         u8         reserved_at_140[0x10];
8417         u8         match_definer_id[0x10];
8418
8419         u8         reserved_at_160[0x80];
8420
8421         u8         reserved_at_1e0[0x18];
8422         u8         match_criteria_enable[0x8];
8423
8424         struct mlx5_ifc_fte_match_param_bits match_criteria;
8425
8426         u8         reserved_at_1200[0xe00];
8427 };
8428
8429 struct mlx5_ifc_create_eq_out_bits {
8430         u8         status[0x8];
8431         u8         reserved_at_8[0x18];
8432
8433         u8         syndrome[0x20];
8434
8435         u8         reserved_at_40[0x18];
8436         u8         eq_number[0x8];
8437
8438         u8         reserved_at_60[0x20];
8439 };
8440
8441 struct mlx5_ifc_create_eq_in_bits {
8442         u8         opcode[0x10];
8443         u8         uid[0x10];
8444
8445         u8         reserved_at_20[0x10];
8446         u8         op_mod[0x10];
8447
8448         u8         reserved_at_40[0x40];
8449
8450         struct mlx5_ifc_eqc_bits eq_context_entry;
8451
8452         u8         reserved_at_280[0x40];
8453
8454         u8         event_bitmask[4][0x40];
8455
8456         u8         reserved_at_3c0[0x4c0];
8457
8458         u8         pas[][0x40];
8459 };
8460
8461 struct mlx5_ifc_create_dct_out_bits {
8462         u8         status[0x8];
8463         u8         reserved_at_8[0x18];
8464
8465         u8         syndrome[0x20];
8466
8467         u8         reserved_at_40[0x8];
8468         u8         dctn[0x18];
8469
8470         u8         ece[0x20];
8471 };
8472
8473 struct mlx5_ifc_create_dct_in_bits {
8474         u8         opcode[0x10];
8475         u8         uid[0x10];
8476
8477         u8         reserved_at_20[0x10];
8478         u8         op_mod[0x10];
8479
8480         u8         reserved_at_40[0x40];
8481
8482         struct mlx5_ifc_dctc_bits dct_context_entry;
8483
8484         u8         reserved_at_280[0x180];
8485 };
8486
8487 struct mlx5_ifc_create_cq_out_bits {
8488         u8         status[0x8];
8489         u8         reserved_at_8[0x18];
8490
8491         u8         syndrome[0x20];
8492
8493         u8         reserved_at_40[0x8];
8494         u8         cqn[0x18];
8495
8496         u8         reserved_at_60[0x20];
8497 };
8498
8499 struct mlx5_ifc_create_cq_in_bits {
8500         u8         opcode[0x10];
8501         u8         uid[0x10];
8502
8503         u8         reserved_at_20[0x10];
8504         u8         op_mod[0x10];
8505
8506         u8         reserved_at_40[0x40];
8507
8508         struct mlx5_ifc_cqc_bits cq_context;
8509
8510         u8         reserved_at_280[0x60];
8511
8512         u8         cq_umem_valid[0x1];
8513         u8         reserved_at_2e1[0x59f];
8514
8515         u8         pas[][0x40];
8516 };
8517
8518 struct mlx5_ifc_config_int_moderation_out_bits {
8519         u8         status[0x8];
8520         u8         reserved_at_8[0x18];
8521
8522         u8         syndrome[0x20];
8523
8524         u8         reserved_at_40[0x4];
8525         u8         min_delay[0xc];
8526         u8         int_vector[0x10];
8527
8528         u8         reserved_at_60[0x20];
8529 };
8530
8531 enum {
8532         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8533         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8534 };
8535
8536 struct mlx5_ifc_config_int_moderation_in_bits {
8537         u8         opcode[0x10];
8538         u8         reserved_at_10[0x10];
8539
8540         u8         reserved_at_20[0x10];
8541         u8         op_mod[0x10];
8542
8543         u8         reserved_at_40[0x4];
8544         u8         min_delay[0xc];
8545         u8         int_vector[0x10];
8546
8547         u8         reserved_at_60[0x20];
8548 };
8549
8550 struct mlx5_ifc_attach_to_mcg_out_bits {
8551         u8         status[0x8];
8552         u8         reserved_at_8[0x18];
8553
8554         u8         syndrome[0x20];
8555
8556         u8         reserved_at_40[0x40];
8557 };
8558
8559 struct mlx5_ifc_attach_to_mcg_in_bits {
8560         u8         opcode[0x10];
8561         u8         uid[0x10];
8562
8563         u8         reserved_at_20[0x10];
8564         u8         op_mod[0x10];
8565
8566         u8         reserved_at_40[0x8];
8567         u8         qpn[0x18];
8568
8569         u8         reserved_at_60[0x20];
8570
8571         u8         multicast_gid[16][0x8];
8572 };
8573
8574 struct mlx5_ifc_arm_xrq_out_bits {
8575         u8         status[0x8];
8576         u8         reserved_at_8[0x18];
8577
8578         u8         syndrome[0x20];
8579
8580         u8         reserved_at_40[0x40];
8581 };
8582
8583 struct mlx5_ifc_arm_xrq_in_bits {
8584         u8         opcode[0x10];
8585         u8         reserved_at_10[0x10];
8586
8587         u8         reserved_at_20[0x10];
8588         u8         op_mod[0x10];
8589
8590         u8         reserved_at_40[0x8];
8591         u8         xrqn[0x18];
8592
8593         u8         reserved_at_60[0x10];
8594         u8         lwm[0x10];
8595 };
8596
8597 struct mlx5_ifc_arm_xrc_srq_out_bits {
8598         u8         status[0x8];
8599         u8         reserved_at_8[0x18];
8600
8601         u8         syndrome[0x20];
8602
8603         u8         reserved_at_40[0x40];
8604 };
8605
8606 enum {
8607         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8608 };
8609
8610 struct mlx5_ifc_arm_xrc_srq_in_bits {
8611         u8         opcode[0x10];
8612         u8         uid[0x10];
8613
8614         u8         reserved_at_20[0x10];
8615         u8         op_mod[0x10];
8616
8617         u8         reserved_at_40[0x8];
8618         u8         xrc_srqn[0x18];
8619
8620         u8         reserved_at_60[0x10];
8621         u8         lwm[0x10];
8622 };
8623
8624 struct mlx5_ifc_arm_rq_out_bits {
8625         u8         status[0x8];
8626         u8         reserved_at_8[0x18];
8627
8628         u8         syndrome[0x20];
8629
8630         u8         reserved_at_40[0x40];
8631 };
8632
8633 enum {
8634         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8635         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8636 };
8637
8638 struct mlx5_ifc_arm_rq_in_bits {
8639         u8         opcode[0x10];
8640         u8         uid[0x10];
8641
8642         u8         reserved_at_20[0x10];
8643         u8         op_mod[0x10];
8644
8645         u8         reserved_at_40[0x8];
8646         u8         srq_number[0x18];
8647
8648         u8         reserved_at_60[0x10];
8649         u8         lwm[0x10];
8650 };
8651
8652 struct mlx5_ifc_arm_dct_out_bits {
8653         u8         status[0x8];
8654         u8         reserved_at_8[0x18];
8655
8656         u8         syndrome[0x20];
8657
8658         u8         reserved_at_40[0x40];
8659 };
8660
8661 struct mlx5_ifc_arm_dct_in_bits {
8662         u8         opcode[0x10];
8663         u8         reserved_at_10[0x10];
8664
8665         u8         reserved_at_20[0x10];
8666         u8         op_mod[0x10];
8667
8668         u8         reserved_at_40[0x8];
8669         u8         dct_number[0x18];
8670
8671         u8         reserved_at_60[0x20];
8672 };
8673
8674 struct mlx5_ifc_alloc_xrcd_out_bits {
8675         u8         status[0x8];
8676         u8         reserved_at_8[0x18];
8677
8678         u8         syndrome[0x20];
8679
8680         u8         reserved_at_40[0x8];
8681         u8         xrcd[0x18];
8682
8683         u8         reserved_at_60[0x20];
8684 };
8685
8686 struct mlx5_ifc_alloc_xrcd_in_bits {
8687         u8         opcode[0x10];
8688         u8         uid[0x10];
8689
8690         u8         reserved_at_20[0x10];
8691         u8         op_mod[0x10];
8692
8693         u8         reserved_at_40[0x40];
8694 };
8695
8696 struct mlx5_ifc_alloc_uar_out_bits {
8697         u8         status[0x8];
8698         u8         reserved_at_8[0x18];
8699
8700         u8         syndrome[0x20];
8701
8702         u8         reserved_at_40[0x8];
8703         u8         uar[0x18];
8704
8705         u8         reserved_at_60[0x20];
8706 };
8707
8708 struct mlx5_ifc_alloc_uar_in_bits {
8709         u8         opcode[0x10];
8710         u8         reserved_at_10[0x10];
8711
8712         u8         reserved_at_20[0x10];
8713         u8         op_mod[0x10];
8714
8715         u8         reserved_at_40[0x40];
8716 };
8717
8718 struct mlx5_ifc_alloc_transport_domain_out_bits {
8719         u8         status[0x8];
8720         u8         reserved_at_8[0x18];
8721
8722         u8         syndrome[0x20];
8723
8724         u8         reserved_at_40[0x8];
8725         u8         transport_domain[0x18];
8726
8727         u8         reserved_at_60[0x20];
8728 };
8729
8730 struct mlx5_ifc_alloc_transport_domain_in_bits {
8731         u8         opcode[0x10];
8732         u8         uid[0x10];
8733
8734         u8         reserved_at_20[0x10];
8735         u8         op_mod[0x10];
8736
8737         u8         reserved_at_40[0x40];
8738 };
8739
8740 struct mlx5_ifc_alloc_q_counter_out_bits {
8741         u8         status[0x8];
8742         u8         reserved_at_8[0x18];
8743
8744         u8         syndrome[0x20];
8745
8746         u8         reserved_at_40[0x18];
8747         u8         counter_set_id[0x8];
8748
8749         u8         reserved_at_60[0x20];
8750 };
8751
8752 struct mlx5_ifc_alloc_q_counter_in_bits {
8753         u8         opcode[0x10];
8754         u8         uid[0x10];
8755
8756         u8         reserved_at_20[0x10];
8757         u8         op_mod[0x10];
8758
8759         u8         reserved_at_40[0x40];
8760 };
8761
8762 struct mlx5_ifc_alloc_pd_out_bits {
8763         u8         status[0x8];
8764         u8         reserved_at_8[0x18];
8765
8766         u8         syndrome[0x20];
8767
8768         u8         reserved_at_40[0x8];
8769         u8         pd[0x18];
8770
8771         u8         reserved_at_60[0x20];
8772 };
8773
8774 struct mlx5_ifc_alloc_pd_in_bits {
8775         u8         opcode[0x10];
8776         u8         uid[0x10];
8777
8778         u8         reserved_at_20[0x10];
8779         u8         op_mod[0x10];
8780
8781         u8         reserved_at_40[0x40];
8782 };
8783
8784 struct mlx5_ifc_alloc_flow_counter_out_bits {
8785         u8         status[0x8];
8786         u8         reserved_at_8[0x18];
8787
8788         u8         syndrome[0x20];
8789
8790         u8         flow_counter_id[0x20];
8791
8792         u8         reserved_at_60[0x20];
8793 };
8794
8795 struct mlx5_ifc_alloc_flow_counter_in_bits {
8796         u8         opcode[0x10];
8797         u8         reserved_at_10[0x10];
8798
8799         u8         reserved_at_20[0x10];
8800         u8         op_mod[0x10];
8801
8802         u8         reserved_at_40[0x38];
8803         u8         flow_counter_bulk[0x8];
8804 };
8805
8806 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8807         u8         status[0x8];
8808         u8         reserved_at_8[0x18];
8809
8810         u8         syndrome[0x20];
8811
8812         u8         reserved_at_40[0x40];
8813 };
8814
8815 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8816         u8         opcode[0x10];
8817         u8         reserved_at_10[0x10];
8818
8819         u8         reserved_at_20[0x10];
8820         u8         op_mod[0x10];
8821
8822         u8         reserved_at_40[0x20];
8823
8824         u8         reserved_at_60[0x10];
8825         u8         vxlan_udp_port[0x10];
8826 };
8827
8828 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8829         u8         status[0x8];
8830         u8         reserved_at_8[0x18];
8831
8832         u8         syndrome[0x20];
8833
8834         u8         reserved_at_40[0x40];
8835 };
8836
8837 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8838         u8         rate_limit[0x20];
8839
8840         u8         burst_upper_bound[0x20];
8841
8842         u8         reserved_at_40[0x10];
8843         u8         typical_packet_size[0x10];
8844
8845         u8         reserved_at_60[0x120];
8846 };
8847
8848 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8849         u8         opcode[0x10];
8850         u8         uid[0x10];
8851
8852         u8         reserved_at_20[0x10];
8853         u8         op_mod[0x10];
8854
8855         u8         reserved_at_40[0x10];
8856         u8         rate_limit_index[0x10];
8857
8858         u8         reserved_at_60[0x20];
8859
8860         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8861 };
8862
8863 struct mlx5_ifc_access_register_out_bits {
8864         u8         status[0x8];
8865         u8         reserved_at_8[0x18];
8866
8867         u8         syndrome[0x20];
8868
8869         u8         reserved_at_40[0x40];
8870
8871         u8         register_data[][0x20];
8872 };
8873
8874 enum {
8875         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8876         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8877 };
8878
8879 struct mlx5_ifc_access_register_in_bits {
8880         u8         opcode[0x10];
8881         u8         reserved_at_10[0x10];
8882
8883         u8         reserved_at_20[0x10];
8884         u8         op_mod[0x10];
8885
8886         u8         reserved_at_40[0x10];
8887         u8         register_id[0x10];
8888
8889         u8         argument[0x20];
8890
8891         u8         register_data[][0x20];
8892 };
8893
8894 struct mlx5_ifc_sltp_reg_bits {
8895         u8         status[0x4];
8896         u8         version[0x4];
8897         u8         local_port[0x8];
8898         u8         pnat[0x2];
8899         u8         reserved_at_12[0x2];
8900         u8         lane[0x4];
8901         u8         reserved_at_18[0x8];
8902
8903         u8         reserved_at_20[0x20];
8904
8905         u8         reserved_at_40[0x7];
8906         u8         polarity[0x1];
8907         u8         ob_tap0[0x8];
8908         u8         ob_tap1[0x8];
8909         u8         ob_tap2[0x8];
8910
8911         u8         reserved_at_60[0xc];
8912         u8         ob_preemp_mode[0x4];
8913         u8         ob_reg[0x8];
8914         u8         ob_bias[0x8];
8915
8916         u8         reserved_at_80[0x20];
8917 };
8918
8919 struct mlx5_ifc_slrg_reg_bits {
8920         u8         status[0x4];
8921         u8         version[0x4];
8922         u8         local_port[0x8];
8923         u8         pnat[0x2];
8924         u8         reserved_at_12[0x2];
8925         u8         lane[0x4];
8926         u8         reserved_at_18[0x8];
8927
8928         u8         time_to_link_up[0x10];
8929         u8         reserved_at_30[0xc];
8930         u8         grade_lane_speed[0x4];
8931
8932         u8         grade_version[0x8];
8933         u8         grade[0x18];
8934
8935         u8         reserved_at_60[0x4];
8936         u8         height_grade_type[0x4];
8937         u8         height_grade[0x18];
8938
8939         u8         height_dz[0x10];
8940         u8         height_dv[0x10];
8941
8942         u8         reserved_at_a0[0x10];
8943         u8         height_sigma[0x10];
8944
8945         u8         reserved_at_c0[0x20];
8946
8947         u8         reserved_at_e0[0x4];
8948         u8         phase_grade_type[0x4];
8949         u8         phase_grade[0x18];
8950
8951         u8         reserved_at_100[0x8];
8952         u8         phase_eo_pos[0x8];
8953         u8         reserved_at_110[0x8];
8954         u8         phase_eo_neg[0x8];
8955
8956         u8         ffe_set_tested[0x10];
8957         u8         test_errors_per_lane[0x10];
8958 };
8959
8960 struct mlx5_ifc_pvlc_reg_bits {
8961         u8         reserved_at_0[0x8];
8962         u8         local_port[0x8];
8963         u8         reserved_at_10[0x10];
8964
8965         u8         reserved_at_20[0x1c];
8966         u8         vl_hw_cap[0x4];
8967
8968         u8         reserved_at_40[0x1c];
8969         u8         vl_admin[0x4];
8970
8971         u8         reserved_at_60[0x1c];
8972         u8         vl_operational[0x4];
8973 };
8974
8975 struct mlx5_ifc_pude_reg_bits {
8976         u8         swid[0x8];
8977         u8         local_port[0x8];
8978         u8         reserved_at_10[0x4];
8979         u8         admin_status[0x4];
8980         u8         reserved_at_18[0x4];
8981         u8         oper_status[0x4];
8982
8983         u8         reserved_at_20[0x60];
8984 };
8985
8986 struct mlx5_ifc_ptys_reg_bits {
8987         u8         reserved_at_0[0x1];
8988         u8         an_disable_admin[0x1];
8989         u8         an_disable_cap[0x1];
8990         u8         reserved_at_3[0x5];
8991         u8         local_port[0x8];
8992         u8         reserved_at_10[0xd];
8993         u8         proto_mask[0x3];
8994
8995         u8         an_status[0x4];
8996         u8         reserved_at_24[0xc];
8997         u8         data_rate_oper[0x10];
8998
8999         u8         ext_eth_proto_capability[0x20];
9000
9001         u8         eth_proto_capability[0x20];
9002
9003         u8         ib_link_width_capability[0x10];
9004         u8         ib_proto_capability[0x10];
9005
9006         u8         ext_eth_proto_admin[0x20];
9007
9008         u8         eth_proto_admin[0x20];
9009
9010         u8         ib_link_width_admin[0x10];
9011         u8         ib_proto_admin[0x10];
9012
9013         u8         ext_eth_proto_oper[0x20];
9014
9015         u8         eth_proto_oper[0x20];
9016
9017         u8         ib_link_width_oper[0x10];
9018         u8         ib_proto_oper[0x10];
9019
9020         u8         reserved_at_160[0x1c];
9021         u8         connector_type[0x4];
9022
9023         u8         eth_proto_lp_advertise[0x20];
9024
9025         u8         reserved_at_1a0[0x60];
9026 };
9027
9028 struct mlx5_ifc_mlcr_reg_bits {
9029         u8         reserved_at_0[0x8];
9030         u8         local_port[0x8];
9031         u8         reserved_at_10[0x20];
9032
9033         u8         beacon_duration[0x10];
9034         u8         reserved_at_40[0x10];
9035
9036         u8         beacon_remain[0x10];
9037 };
9038
9039 struct mlx5_ifc_ptas_reg_bits {
9040         u8         reserved_at_0[0x20];
9041
9042         u8         algorithm_options[0x10];
9043         u8         reserved_at_30[0x4];
9044         u8         repetitions_mode[0x4];
9045         u8         num_of_repetitions[0x8];
9046
9047         u8         grade_version[0x8];
9048         u8         height_grade_type[0x4];
9049         u8         phase_grade_type[0x4];
9050         u8         height_grade_weight[0x8];
9051         u8         phase_grade_weight[0x8];
9052
9053         u8         gisim_measure_bits[0x10];
9054         u8         adaptive_tap_measure_bits[0x10];
9055
9056         u8         ber_bath_high_error_threshold[0x10];
9057         u8         ber_bath_mid_error_threshold[0x10];
9058
9059         u8         ber_bath_low_error_threshold[0x10];
9060         u8         one_ratio_high_threshold[0x10];
9061
9062         u8         one_ratio_high_mid_threshold[0x10];
9063         u8         one_ratio_low_mid_threshold[0x10];
9064
9065         u8         one_ratio_low_threshold[0x10];
9066         u8         ndeo_error_threshold[0x10];
9067
9068         u8         mixer_offset_step_size[0x10];
9069         u8         reserved_at_110[0x8];
9070         u8         mix90_phase_for_voltage_bath[0x8];
9071
9072         u8         mixer_offset_start[0x10];
9073         u8         mixer_offset_end[0x10];
9074
9075         u8         reserved_at_140[0x15];
9076         u8         ber_test_time[0xb];
9077 };
9078
9079 struct mlx5_ifc_pspa_reg_bits {
9080         u8         swid[0x8];
9081         u8         local_port[0x8];
9082         u8         sub_port[0x8];
9083         u8         reserved_at_18[0x8];
9084
9085         u8         reserved_at_20[0x20];
9086 };
9087
9088 struct mlx5_ifc_pqdr_reg_bits {
9089         u8         reserved_at_0[0x8];
9090         u8         local_port[0x8];
9091         u8         reserved_at_10[0x5];
9092         u8         prio[0x3];
9093         u8         reserved_at_18[0x6];
9094         u8         mode[0x2];
9095
9096         u8         reserved_at_20[0x20];
9097
9098         u8         reserved_at_40[0x10];
9099         u8         min_threshold[0x10];
9100
9101         u8         reserved_at_60[0x10];
9102         u8         max_threshold[0x10];
9103
9104         u8         reserved_at_80[0x10];
9105         u8         mark_probability_denominator[0x10];
9106
9107         u8         reserved_at_a0[0x60];
9108 };
9109
9110 struct mlx5_ifc_ppsc_reg_bits {
9111         u8         reserved_at_0[0x8];
9112         u8         local_port[0x8];
9113         u8         reserved_at_10[0x10];
9114
9115         u8         reserved_at_20[0x60];
9116
9117         u8         reserved_at_80[0x1c];
9118         u8         wrps_admin[0x4];
9119
9120         u8         reserved_at_a0[0x1c];
9121         u8         wrps_status[0x4];
9122
9123         u8         reserved_at_c0[0x8];
9124         u8         up_threshold[0x8];
9125         u8         reserved_at_d0[0x8];
9126         u8         down_threshold[0x8];
9127
9128         u8         reserved_at_e0[0x20];
9129
9130         u8         reserved_at_100[0x1c];
9131         u8         srps_admin[0x4];
9132
9133         u8         reserved_at_120[0x1c];
9134         u8         srps_status[0x4];
9135
9136         u8         reserved_at_140[0x40];
9137 };
9138
9139 struct mlx5_ifc_pplr_reg_bits {
9140         u8         reserved_at_0[0x8];
9141         u8         local_port[0x8];
9142         u8         reserved_at_10[0x10];
9143
9144         u8         reserved_at_20[0x8];
9145         u8         lb_cap[0x8];
9146         u8         reserved_at_30[0x8];
9147         u8         lb_en[0x8];
9148 };
9149
9150 struct mlx5_ifc_pplm_reg_bits {
9151         u8         reserved_at_0[0x8];
9152         u8         local_port[0x8];
9153         u8         reserved_at_10[0x10];
9154
9155         u8         reserved_at_20[0x20];
9156
9157         u8         port_profile_mode[0x8];
9158         u8         static_port_profile[0x8];
9159         u8         active_port_profile[0x8];
9160         u8         reserved_at_58[0x8];
9161
9162         u8         retransmission_active[0x8];
9163         u8         fec_mode_active[0x18];
9164
9165         u8         rs_fec_correction_bypass_cap[0x4];
9166         u8         reserved_at_84[0x8];
9167         u8         fec_override_cap_56g[0x4];
9168         u8         fec_override_cap_100g[0x4];
9169         u8         fec_override_cap_50g[0x4];
9170         u8         fec_override_cap_25g[0x4];
9171         u8         fec_override_cap_10g_40g[0x4];
9172
9173         u8         rs_fec_correction_bypass_admin[0x4];
9174         u8         reserved_at_a4[0x8];
9175         u8         fec_override_admin_56g[0x4];
9176         u8         fec_override_admin_100g[0x4];
9177         u8         fec_override_admin_50g[0x4];
9178         u8         fec_override_admin_25g[0x4];
9179         u8         fec_override_admin_10g_40g[0x4];
9180
9181         u8         fec_override_cap_400g_8x[0x10];
9182         u8         fec_override_cap_200g_4x[0x10];
9183
9184         u8         fec_override_cap_100g_2x[0x10];
9185         u8         fec_override_cap_50g_1x[0x10];
9186
9187         u8         fec_override_admin_400g_8x[0x10];
9188         u8         fec_override_admin_200g_4x[0x10];
9189
9190         u8         fec_override_admin_100g_2x[0x10];
9191         u8         fec_override_admin_50g_1x[0x10];
9192
9193         u8         reserved_at_140[0x140];
9194 };
9195
9196 struct mlx5_ifc_ppcnt_reg_bits {
9197         u8         swid[0x8];
9198         u8         local_port[0x8];
9199         u8         pnat[0x2];
9200         u8         reserved_at_12[0x8];
9201         u8         grp[0x6];
9202
9203         u8         clr[0x1];
9204         u8         reserved_at_21[0x1c];
9205         u8         prio_tc[0x3];
9206
9207         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9208 };
9209
9210 struct mlx5_ifc_mpein_reg_bits {
9211         u8         reserved_at_0[0x2];
9212         u8         depth[0x6];
9213         u8         pcie_index[0x8];
9214         u8         node[0x8];
9215         u8         reserved_at_18[0x8];
9216
9217         u8         capability_mask[0x20];
9218
9219         u8         reserved_at_40[0x8];
9220         u8         link_width_enabled[0x8];
9221         u8         link_speed_enabled[0x10];
9222
9223         u8         lane0_physical_position[0x8];
9224         u8         link_width_active[0x8];
9225         u8         link_speed_active[0x10];
9226
9227         u8         num_of_pfs[0x10];
9228         u8         num_of_vfs[0x10];
9229
9230         u8         bdf0[0x10];
9231         u8         reserved_at_b0[0x10];
9232
9233         u8         max_read_request_size[0x4];
9234         u8         max_payload_size[0x4];
9235         u8         reserved_at_c8[0x5];
9236         u8         pwr_status[0x3];
9237         u8         port_type[0x4];
9238         u8         reserved_at_d4[0xb];
9239         u8         lane_reversal[0x1];
9240
9241         u8         reserved_at_e0[0x14];
9242         u8         pci_power[0xc];
9243
9244         u8         reserved_at_100[0x20];
9245
9246         u8         device_status[0x10];
9247         u8         port_state[0x8];
9248         u8         reserved_at_138[0x8];
9249
9250         u8         reserved_at_140[0x10];
9251         u8         receiver_detect_result[0x10];
9252
9253         u8         reserved_at_160[0x20];
9254 };
9255
9256 struct mlx5_ifc_mpcnt_reg_bits {
9257         u8         reserved_at_0[0x8];
9258         u8         pcie_index[0x8];
9259         u8         reserved_at_10[0xa];
9260         u8         grp[0x6];
9261
9262         u8         clr[0x1];
9263         u8         reserved_at_21[0x1f];
9264
9265         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9266 };
9267
9268 struct mlx5_ifc_ppad_reg_bits {
9269         u8         reserved_at_0[0x3];
9270         u8         single_mac[0x1];
9271         u8         reserved_at_4[0x4];
9272         u8         local_port[0x8];
9273         u8         mac_47_32[0x10];
9274
9275         u8         mac_31_0[0x20];
9276
9277         u8         reserved_at_40[0x40];
9278 };
9279
9280 struct mlx5_ifc_pmtu_reg_bits {
9281         u8         reserved_at_0[0x8];
9282         u8         local_port[0x8];
9283         u8         reserved_at_10[0x10];
9284
9285         u8         max_mtu[0x10];
9286         u8         reserved_at_30[0x10];
9287
9288         u8         admin_mtu[0x10];
9289         u8         reserved_at_50[0x10];
9290
9291         u8         oper_mtu[0x10];
9292         u8         reserved_at_70[0x10];
9293 };
9294
9295 struct mlx5_ifc_pmpr_reg_bits {
9296         u8         reserved_at_0[0x8];
9297         u8         module[0x8];
9298         u8         reserved_at_10[0x10];
9299
9300         u8         reserved_at_20[0x18];
9301         u8         attenuation_5g[0x8];
9302
9303         u8         reserved_at_40[0x18];
9304         u8         attenuation_7g[0x8];
9305
9306         u8         reserved_at_60[0x18];
9307         u8         attenuation_12g[0x8];
9308 };
9309
9310 struct mlx5_ifc_pmpe_reg_bits {
9311         u8         reserved_at_0[0x8];
9312         u8         module[0x8];
9313         u8         reserved_at_10[0xc];
9314         u8         module_status[0x4];
9315
9316         u8         reserved_at_20[0x60];
9317 };
9318
9319 struct mlx5_ifc_pmpc_reg_bits {
9320         u8         module_state_updated[32][0x8];
9321 };
9322
9323 struct mlx5_ifc_pmlpn_reg_bits {
9324         u8         reserved_at_0[0x4];
9325         u8         mlpn_status[0x4];
9326         u8         local_port[0x8];
9327         u8         reserved_at_10[0x10];
9328
9329         u8         e[0x1];
9330         u8         reserved_at_21[0x1f];
9331 };
9332
9333 struct mlx5_ifc_pmlp_reg_bits {
9334         u8         rxtx[0x1];
9335         u8         reserved_at_1[0x7];
9336         u8         local_port[0x8];
9337         u8         reserved_at_10[0x8];
9338         u8         width[0x8];
9339
9340         u8         lane0_module_mapping[0x20];
9341
9342         u8         lane1_module_mapping[0x20];
9343
9344         u8         lane2_module_mapping[0x20];
9345
9346         u8         lane3_module_mapping[0x20];
9347
9348         u8         reserved_at_a0[0x160];
9349 };
9350
9351 struct mlx5_ifc_pmaos_reg_bits {
9352         u8         reserved_at_0[0x8];
9353         u8         module[0x8];
9354         u8         reserved_at_10[0x4];
9355         u8         admin_status[0x4];
9356         u8         reserved_at_18[0x4];
9357         u8         oper_status[0x4];
9358
9359         u8         ase[0x1];
9360         u8         ee[0x1];
9361         u8         reserved_at_22[0x1c];
9362         u8         e[0x2];
9363
9364         u8         reserved_at_40[0x40];
9365 };
9366
9367 struct mlx5_ifc_plpc_reg_bits {
9368         u8         reserved_at_0[0x4];
9369         u8         profile_id[0xc];
9370         u8         reserved_at_10[0x4];
9371         u8         proto_mask[0x4];
9372         u8         reserved_at_18[0x8];
9373
9374         u8         reserved_at_20[0x10];
9375         u8         lane_speed[0x10];
9376
9377         u8         reserved_at_40[0x17];
9378         u8         lpbf[0x1];
9379         u8         fec_mode_policy[0x8];
9380
9381         u8         retransmission_capability[0x8];
9382         u8         fec_mode_capability[0x18];
9383
9384         u8         retransmission_support_admin[0x8];
9385         u8         fec_mode_support_admin[0x18];
9386
9387         u8         retransmission_request_admin[0x8];
9388         u8         fec_mode_request_admin[0x18];
9389
9390         u8         reserved_at_c0[0x80];
9391 };
9392
9393 struct mlx5_ifc_plib_reg_bits {
9394         u8         reserved_at_0[0x8];
9395         u8         local_port[0x8];
9396         u8         reserved_at_10[0x8];
9397         u8         ib_port[0x8];
9398
9399         u8         reserved_at_20[0x60];
9400 };
9401
9402 struct mlx5_ifc_plbf_reg_bits {
9403         u8         reserved_at_0[0x8];
9404         u8         local_port[0x8];
9405         u8         reserved_at_10[0xd];
9406         u8         lbf_mode[0x3];
9407
9408         u8         reserved_at_20[0x20];
9409 };
9410
9411 struct mlx5_ifc_pipg_reg_bits {
9412         u8         reserved_at_0[0x8];
9413         u8         local_port[0x8];
9414         u8         reserved_at_10[0x10];
9415
9416         u8         dic[0x1];
9417         u8         reserved_at_21[0x19];
9418         u8         ipg[0x4];
9419         u8         reserved_at_3e[0x2];
9420 };
9421
9422 struct mlx5_ifc_pifr_reg_bits {
9423         u8         reserved_at_0[0x8];
9424         u8         local_port[0x8];
9425         u8         reserved_at_10[0x10];
9426
9427         u8         reserved_at_20[0xe0];
9428
9429         u8         port_filter[8][0x20];
9430
9431         u8         port_filter_update_en[8][0x20];
9432 };
9433
9434 struct mlx5_ifc_pfcc_reg_bits {
9435         u8         reserved_at_0[0x8];
9436         u8         local_port[0x8];
9437         u8         reserved_at_10[0xb];
9438         u8         ppan_mask_n[0x1];
9439         u8         minor_stall_mask[0x1];
9440         u8         critical_stall_mask[0x1];
9441         u8         reserved_at_1e[0x2];
9442
9443         u8         ppan[0x4];
9444         u8         reserved_at_24[0x4];
9445         u8         prio_mask_tx[0x8];
9446         u8         reserved_at_30[0x8];
9447         u8         prio_mask_rx[0x8];
9448
9449         u8         pptx[0x1];
9450         u8         aptx[0x1];
9451         u8         pptx_mask_n[0x1];
9452         u8         reserved_at_43[0x5];
9453         u8         pfctx[0x8];
9454         u8         reserved_at_50[0x10];
9455
9456         u8         pprx[0x1];
9457         u8         aprx[0x1];
9458         u8         pprx_mask_n[0x1];
9459         u8         reserved_at_63[0x5];
9460         u8         pfcrx[0x8];
9461         u8         reserved_at_70[0x10];
9462
9463         u8         device_stall_minor_watermark[0x10];
9464         u8         device_stall_critical_watermark[0x10];
9465
9466         u8         reserved_at_a0[0x60];
9467 };
9468
9469 struct mlx5_ifc_pelc_reg_bits {
9470         u8         op[0x4];
9471         u8         reserved_at_4[0x4];
9472         u8         local_port[0x8];
9473         u8         reserved_at_10[0x10];
9474
9475         u8         op_admin[0x8];
9476         u8         op_capability[0x8];
9477         u8         op_request[0x8];
9478         u8         op_active[0x8];
9479
9480         u8         admin[0x40];
9481
9482         u8         capability[0x40];
9483
9484         u8         request[0x40];
9485
9486         u8         active[0x40];
9487
9488         u8         reserved_at_140[0x80];
9489 };
9490
9491 struct mlx5_ifc_peir_reg_bits {
9492         u8         reserved_at_0[0x8];
9493         u8         local_port[0x8];
9494         u8         reserved_at_10[0x10];
9495
9496         u8         reserved_at_20[0xc];
9497         u8         error_count[0x4];
9498         u8         reserved_at_30[0x10];
9499
9500         u8         reserved_at_40[0xc];
9501         u8         lane[0x4];
9502         u8         reserved_at_50[0x8];
9503         u8         error_type[0x8];
9504 };
9505
9506 struct mlx5_ifc_mpegc_reg_bits {
9507         u8         reserved_at_0[0x30];
9508         u8         field_select[0x10];
9509
9510         u8         tx_overflow_sense[0x1];
9511         u8         mark_cqe[0x1];
9512         u8         mark_cnp[0x1];
9513         u8         reserved_at_43[0x1b];
9514         u8         tx_lossy_overflow_oper[0x2];
9515
9516         u8         reserved_at_60[0x100];
9517 };
9518
9519 enum {
9520         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9521         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9522         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9523 };
9524
9525 struct mlx5_ifc_mtutc_reg_bits {
9526         u8         reserved_at_0[0x1c];
9527         u8         operation[0x4];
9528
9529         u8         freq_adjustment[0x20];
9530
9531         u8         reserved_at_40[0x40];
9532
9533         u8         utc_sec[0x20];
9534
9535         u8         reserved_at_a0[0x2];
9536         u8         utc_nsec[0x1e];
9537
9538         u8         time_adjustment[0x20];
9539 };
9540
9541 struct mlx5_ifc_pcam_enhanced_features_bits {
9542         u8         reserved_at_0[0x68];
9543         u8         fec_50G_per_lane_in_pplm[0x1];
9544         u8         reserved_at_69[0x4];
9545         u8         rx_icrc_encapsulated_counter[0x1];
9546         u8         reserved_at_6e[0x4];
9547         u8         ptys_extended_ethernet[0x1];
9548         u8         reserved_at_73[0x3];
9549         u8         pfcc_mask[0x1];
9550         u8         reserved_at_77[0x3];
9551         u8         per_lane_error_counters[0x1];
9552         u8         rx_buffer_fullness_counters[0x1];
9553         u8         ptys_connector_type[0x1];
9554         u8         reserved_at_7d[0x1];
9555         u8         ppcnt_discard_group[0x1];
9556         u8         ppcnt_statistical_group[0x1];
9557 };
9558
9559 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9560         u8         port_access_reg_cap_mask_127_to_96[0x20];
9561         u8         port_access_reg_cap_mask_95_to_64[0x20];
9562
9563         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9564         u8         pplm[0x1];
9565         u8         port_access_reg_cap_mask_34_to_32[0x3];
9566
9567         u8         port_access_reg_cap_mask_31_to_13[0x13];
9568         u8         pbmc[0x1];
9569         u8         pptb[0x1];
9570         u8         port_access_reg_cap_mask_10_to_09[0x2];
9571         u8         ppcnt[0x1];
9572         u8         port_access_reg_cap_mask_07_to_00[0x8];
9573 };
9574
9575 struct mlx5_ifc_pcam_reg_bits {
9576         u8         reserved_at_0[0x8];
9577         u8         feature_group[0x8];
9578         u8         reserved_at_10[0x8];
9579         u8         access_reg_group[0x8];
9580
9581         u8         reserved_at_20[0x20];
9582
9583         union {
9584                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9585                 u8         reserved_at_0[0x80];
9586         } port_access_reg_cap_mask;
9587
9588         u8         reserved_at_c0[0x80];
9589
9590         union {
9591                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9592                 u8         reserved_at_0[0x80];
9593         } feature_cap_mask;
9594
9595         u8         reserved_at_1c0[0xc0];
9596 };
9597
9598 struct mlx5_ifc_mcam_enhanced_features_bits {
9599         u8         reserved_at_0[0x6b];
9600         u8         ptpcyc2realtime_modify[0x1];
9601         u8         reserved_at_6c[0x2];
9602         u8         pci_status_and_power[0x1];
9603         u8         reserved_at_6f[0x5];
9604         u8         mark_tx_action_cnp[0x1];
9605         u8         mark_tx_action_cqe[0x1];
9606         u8         dynamic_tx_overflow[0x1];
9607         u8         reserved_at_77[0x4];
9608         u8         pcie_outbound_stalled[0x1];
9609         u8         tx_overflow_buffer_pkt[0x1];
9610         u8         mtpps_enh_out_per_adj[0x1];
9611         u8         mtpps_fs[0x1];
9612         u8         pcie_performance_group[0x1];
9613 };
9614
9615 struct mlx5_ifc_mcam_access_reg_bits {
9616         u8         reserved_at_0[0x1c];
9617         u8         mcda[0x1];
9618         u8         mcc[0x1];
9619         u8         mcqi[0x1];
9620         u8         mcqs[0x1];
9621
9622         u8         regs_95_to_87[0x9];
9623         u8         mpegc[0x1];
9624         u8         mtutc[0x1];
9625         u8         regs_84_to_68[0x11];
9626         u8         tracer_registers[0x4];
9627
9628         u8         regs_63_to_32[0x20];
9629         u8         regs_31_to_0[0x20];
9630 };
9631
9632 struct mlx5_ifc_mcam_access_reg_bits1 {
9633         u8         regs_127_to_96[0x20];
9634
9635         u8         regs_95_to_64[0x20];
9636
9637         u8         regs_63_to_32[0x20];
9638
9639         u8         regs_31_to_0[0x20];
9640 };
9641
9642 struct mlx5_ifc_mcam_access_reg_bits2 {
9643         u8         regs_127_to_99[0x1d];
9644         u8         mirc[0x1];
9645         u8         regs_97_to_96[0x2];
9646
9647         u8         regs_95_to_64[0x20];
9648
9649         u8         regs_63_to_32[0x20];
9650
9651         u8         regs_31_to_0[0x20];
9652 };
9653
9654 struct mlx5_ifc_mcam_reg_bits {
9655         u8         reserved_at_0[0x8];
9656         u8         feature_group[0x8];
9657         u8         reserved_at_10[0x8];
9658         u8         access_reg_group[0x8];
9659
9660         u8         reserved_at_20[0x20];
9661
9662         union {
9663                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9664                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9665                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9666                 u8         reserved_at_0[0x80];
9667         } mng_access_reg_cap_mask;
9668
9669         u8         reserved_at_c0[0x80];
9670
9671         union {
9672                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9673                 u8         reserved_at_0[0x80];
9674         } mng_feature_cap_mask;
9675
9676         u8         reserved_at_1c0[0x80];
9677 };
9678
9679 struct mlx5_ifc_qcam_access_reg_cap_mask {
9680         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9681         u8         qpdpm[0x1];
9682         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9683         u8         qdpm[0x1];
9684         u8         qpts[0x1];
9685         u8         qcap[0x1];
9686         u8         qcam_access_reg_cap_mask_0[0x1];
9687 };
9688
9689 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9690         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9691         u8         qpts_trust_both[0x1];
9692 };
9693
9694 struct mlx5_ifc_qcam_reg_bits {
9695         u8         reserved_at_0[0x8];
9696         u8         feature_group[0x8];
9697         u8         reserved_at_10[0x8];
9698         u8         access_reg_group[0x8];
9699         u8         reserved_at_20[0x20];
9700
9701         union {
9702                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9703                 u8  reserved_at_0[0x80];
9704         } qos_access_reg_cap_mask;
9705
9706         u8         reserved_at_c0[0x80];
9707
9708         union {
9709                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9710                 u8  reserved_at_0[0x80];
9711         } qos_feature_cap_mask;
9712
9713         u8         reserved_at_1c0[0x80];
9714 };
9715
9716 struct mlx5_ifc_core_dump_reg_bits {
9717         u8         reserved_at_0[0x18];
9718         u8         core_dump_type[0x8];
9719
9720         u8         reserved_at_20[0x30];
9721         u8         vhca_id[0x10];
9722
9723         u8         reserved_at_60[0x8];
9724         u8         qpn[0x18];
9725         u8         reserved_at_80[0x180];
9726 };
9727
9728 struct mlx5_ifc_pcap_reg_bits {
9729         u8         reserved_at_0[0x8];
9730         u8         local_port[0x8];
9731         u8         reserved_at_10[0x10];
9732
9733         u8         port_capability_mask[4][0x20];
9734 };
9735
9736 struct mlx5_ifc_paos_reg_bits {
9737         u8         swid[0x8];
9738         u8         local_port[0x8];
9739         u8         reserved_at_10[0x4];
9740         u8         admin_status[0x4];
9741         u8         reserved_at_18[0x4];
9742         u8         oper_status[0x4];
9743
9744         u8         ase[0x1];
9745         u8         ee[0x1];
9746         u8         reserved_at_22[0x1c];
9747         u8         e[0x2];
9748
9749         u8         reserved_at_40[0x40];
9750 };
9751
9752 struct mlx5_ifc_pamp_reg_bits {
9753         u8         reserved_at_0[0x8];
9754         u8         opamp_group[0x8];
9755         u8         reserved_at_10[0xc];
9756         u8         opamp_group_type[0x4];
9757
9758         u8         start_index[0x10];
9759         u8         reserved_at_30[0x4];
9760         u8         num_of_indices[0xc];
9761
9762         u8         index_data[18][0x10];
9763 };
9764
9765 struct mlx5_ifc_pcmr_reg_bits {
9766         u8         reserved_at_0[0x8];
9767         u8         local_port[0x8];
9768         u8         reserved_at_10[0x10];
9769
9770         u8         entropy_force_cap[0x1];
9771         u8         entropy_calc_cap[0x1];
9772         u8         entropy_gre_calc_cap[0x1];
9773         u8         reserved_at_23[0xf];
9774         u8         rx_ts_over_crc_cap[0x1];
9775         u8         reserved_at_33[0xb];
9776         u8         fcs_cap[0x1];
9777         u8         reserved_at_3f[0x1];
9778
9779         u8         entropy_force[0x1];
9780         u8         entropy_calc[0x1];
9781         u8         entropy_gre_calc[0x1];
9782         u8         reserved_at_43[0xf];
9783         u8         rx_ts_over_crc[0x1];
9784         u8         reserved_at_53[0xb];
9785         u8         fcs_chk[0x1];
9786         u8         reserved_at_5f[0x1];
9787 };
9788
9789 struct mlx5_ifc_lane_2_module_mapping_bits {
9790         u8         reserved_at_0[0x6];
9791         u8         rx_lane[0x2];
9792         u8         reserved_at_8[0x6];
9793         u8         tx_lane[0x2];
9794         u8         reserved_at_10[0x8];
9795         u8         module[0x8];
9796 };
9797
9798 struct mlx5_ifc_bufferx_reg_bits {
9799         u8         reserved_at_0[0x6];
9800         u8         lossy[0x1];
9801         u8         epsb[0x1];
9802         u8         reserved_at_8[0xc];
9803         u8         size[0xc];
9804
9805         u8         xoff_threshold[0x10];
9806         u8         xon_threshold[0x10];
9807 };
9808
9809 struct mlx5_ifc_set_node_in_bits {
9810         u8         node_description[64][0x8];
9811 };
9812
9813 struct mlx5_ifc_register_power_settings_bits {
9814         u8         reserved_at_0[0x18];
9815         u8         power_settings_level[0x8];
9816
9817         u8         reserved_at_20[0x60];
9818 };
9819
9820 struct mlx5_ifc_register_host_endianness_bits {
9821         u8         he[0x1];
9822         u8         reserved_at_1[0x1f];
9823
9824         u8         reserved_at_20[0x60];
9825 };
9826
9827 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9828         u8         reserved_at_0[0x20];
9829
9830         u8         mkey[0x20];
9831
9832         u8         addressh_63_32[0x20];
9833
9834         u8         addressl_31_0[0x20];
9835 };
9836
9837 struct mlx5_ifc_ud_adrs_vector_bits {
9838         u8         dc_key[0x40];
9839
9840         u8         ext[0x1];
9841         u8         reserved_at_41[0x7];
9842         u8         destination_qp_dct[0x18];
9843
9844         u8         static_rate[0x4];
9845         u8         sl_eth_prio[0x4];
9846         u8         fl[0x1];
9847         u8         mlid[0x7];
9848         u8         rlid_udp_sport[0x10];
9849
9850         u8         reserved_at_80[0x20];
9851
9852         u8         rmac_47_16[0x20];
9853
9854         u8         rmac_15_0[0x10];
9855         u8         tclass[0x8];
9856         u8         hop_limit[0x8];
9857
9858         u8         reserved_at_e0[0x1];
9859         u8         grh[0x1];
9860         u8         reserved_at_e2[0x2];
9861         u8         src_addr_index[0x8];
9862         u8         flow_label[0x14];
9863
9864         u8         rgid_rip[16][0x8];
9865 };
9866
9867 struct mlx5_ifc_pages_req_event_bits {
9868         u8         reserved_at_0[0x10];
9869         u8         function_id[0x10];
9870
9871         u8         num_pages[0x20];
9872
9873         u8         reserved_at_40[0xa0];
9874 };
9875
9876 struct mlx5_ifc_eqe_bits {
9877         u8         reserved_at_0[0x8];
9878         u8         event_type[0x8];
9879         u8         reserved_at_10[0x8];
9880         u8         event_sub_type[0x8];
9881
9882         u8         reserved_at_20[0xe0];
9883
9884         union mlx5_ifc_event_auto_bits event_data;
9885
9886         u8         reserved_at_1e0[0x10];
9887         u8         signature[0x8];
9888         u8         reserved_at_1f8[0x7];
9889         u8         owner[0x1];
9890 };
9891
9892 enum {
9893         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9894 };
9895
9896 struct mlx5_ifc_cmd_queue_entry_bits {
9897         u8         type[0x8];
9898         u8         reserved_at_8[0x18];
9899
9900         u8         input_length[0x20];
9901
9902         u8         input_mailbox_pointer_63_32[0x20];
9903
9904         u8         input_mailbox_pointer_31_9[0x17];
9905         u8         reserved_at_77[0x9];
9906
9907         u8         command_input_inline_data[16][0x8];
9908
9909         u8         command_output_inline_data[16][0x8];
9910
9911         u8         output_mailbox_pointer_63_32[0x20];
9912
9913         u8         output_mailbox_pointer_31_9[0x17];
9914         u8         reserved_at_1b7[0x9];
9915
9916         u8         output_length[0x20];
9917
9918         u8         token[0x8];
9919         u8         signature[0x8];
9920         u8         reserved_at_1f0[0x8];
9921         u8         status[0x7];
9922         u8         ownership[0x1];
9923 };
9924
9925 struct mlx5_ifc_cmd_out_bits {
9926         u8         status[0x8];
9927         u8         reserved_at_8[0x18];
9928
9929         u8         syndrome[0x20];
9930
9931         u8         command_output[0x20];
9932 };
9933
9934 struct mlx5_ifc_cmd_in_bits {
9935         u8         opcode[0x10];
9936         u8         reserved_at_10[0x10];
9937
9938         u8         reserved_at_20[0x10];
9939         u8         op_mod[0x10];
9940
9941         u8         command[][0x20];
9942 };
9943
9944 struct mlx5_ifc_cmd_if_box_bits {
9945         u8         mailbox_data[512][0x8];
9946
9947         u8         reserved_at_1000[0x180];
9948
9949         u8         next_pointer_63_32[0x20];
9950
9951         u8         next_pointer_31_10[0x16];
9952         u8         reserved_at_11b6[0xa];
9953
9954         u8         block_number[0x20];
9955
9956         u8         reserved_at_11e0[0x8];
9957         u8         token[0x8];
9958         u8         ctrl_signature[0x8];
9959         u8         signature[0x8];
9960 };
9961
9962 struct mlx5_ifc_mtt_bits {
9963         u8         ptag_63_32[0x20];
9964
9965         u8         ptag_31_8[0x18];
9966         u8         reserved_at_38[0x6];
9967         u8         wr_en[0x1];
9968         u8         rd_en[0x1];
9969 };
9970
9971 struct mlx5_ifc_query_wol_rol_out_bits {
9972         u8         status[0x8];
9973         u8         reserved_at_8[0x18];
9974
9975         u8         syndrome[0x20];
9976
9977         u8         reserved_at_40[0x10];
9978         u8         rol_mode[0x8];
9979         u8         wol_mode[0x8];
9980
9981         u8         reserved_at_60[0x20];
9982 };
9983
9984 struct mlx5_ifc_query_wol_rol_in_bits {
9985         u8         opcode[0x10];
9986         u8         reserved_at_10[0x10];
9987
9988         u8         reserved_at_20[0x10];
9989         u8         op_mod[0x10];
9990
9991         u8         reserved_at_40[0x40];
9992 };
9993
9994 struct mlx5_ifc_set_wol_rol_out_bits {
9995         u8         status[0x8];
9996         u8         reserved_at_8[0x18];
9997
9998         u8         syndrome[0x20];
9999
10000         u8         reserved_at_40[0x40];
10001 };
10002
10003 struct mlx5_ifc_set_wol_rol_in_bits {
10004         u8         opcode[0x10];
10005         u8         reserved_at_10[0x10];
10006
10007         u8         reserved_at_20[0x10];
10008         u8         op_mod[0x10];
10009
10010         u8         rol_mode_valid[0x1];
10011         u8         wol_mode_valid[0x1];
10012         u8         reserved_at_42[0xe];
10013         u8         rol_mode[0x8];
10014         u8         wol_mode[0x8];
10015
10016         u8         reserved_at_60[0x20];
10017 };
10018
10019 enum {
10020         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10021         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10022         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10023 };
10024
10025 enum {
10026         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10027         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10028         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10029 };
10030
10031 enum {
10032         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10033         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10034         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10035         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10036         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10037         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10038         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10039         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10040         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10041         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10042         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10043 };
10044
10045 struct mlx5_ifc_initial_seg_bits {
10046         u8         fw_rev_minor[0x10];
10047         u8         fw_rev_major[0x10];
10048
10049         u8         cmd_interface_rev[0x10];
10050         u8         fw_rev_subminor[0x10];
10051
10052         u8         reserved_at_40[0x40];
10053
10054         u8         cmdq_phy_addr_63_32[0x20];
10055
10056         u8         cmdq_phy_addr_31_12[0x14];
10057         u8         reserved_at_b4[0x2];
10058         u8         nic_interface[0x2];
10059         u8         log_cmdq_size[0x4];
10060         u8         log_cmdq_stride[0x4];
10061
10062         u8         command_doorbell_vector[0x20];
10063
10064         u8         reserved_at_e0[0xf00];
10065
10066         u8         initializing[0x1];
10067         u8         reserved_at_fe1[0x4];
10068         u8         nic_interface_supported[0x3];
10069         u8         embedded_cpu[0x1];
10070         u8         reserved_at_fe9[0x17];
10071
10072         struct mlx5_ifc_health_buffer_bits health_buffer;
10073
10074         u8         no_dram_nic_offset[0x20];
10075
10076         u8         reserved_at_1220[0x6e40];
10077
10078         u8         reserved_at_8060[0x1f];
10079         u8         clear_int[0x1];
10080
10081         u8         health_syndrome[0x8];
10082         u8         health_counter[0x18];
10083
10084         u8         reserved_at_80a0[0x17fc0];
10085 };
10086
10087 struct mlx5_ifc_mtpps_reg_bits {
10088         u8         reserved_at_0[0xc];
10089         u8         cap_number_of_pps_pins[0x4];
10090         u8         reserved_at_10[0x4];
10091         u8         cap_max_num_of_pps_in_pins[0x4];
10092         u8         reserved_at_18[0x4];
10093         u8         cap_max_num_of_pps_out_pins[0x4];
10094
10095         u8         reserved_at_20[0x24];
10096         u8         cap_pin_3_mode[0x4];
10097         u8         reserved_at_48[0x4];
10098         u8         cap_pin_2_mode[0x4];
10099         u8         reserved_at_50[0x4];
10100         u8         cap_pin_1_mode[0x4];
10101         u8         reserved_at_58[0x4];
10102         u8         cap_pin_0_mode[0x4];
10103
10104         u8         reserved_at_60[0x4];
10105         u8         cap_pin_7_mode[0x4];
10106         u8         reserved_at_68[0x4];
10107         u8         cap_pin_6_mode[0x4];
10108         u8         reserved_at_70[0x4];
10109         u8         cap_pin_5_mode[0x4];
10110         u8         reserved_at_78[0x4];
10111         u8         cap_pin_4_mode[0x4];
10112
10113         u8         field_select[0x20];
10114         u8         reserved_at_a0[0x60];
10115
10116         u8         enable[0x1];
10117         u8         reserved_at_101[0xb];
10118         u8         pattern[0x4];
10119         u8         reserved_at_110[0x4];
10120         u8         pin_mode[0x4];
10121         u8         pin[0x8];
10122
10123         u8         reserved_at_120[0x20];
10124
10125         u8         time_stamp[0x40];
10126
10127         u8         out_pulse_duration[0x10];
10128         u8         out_periodic_adjustment[0x10];
10129         u8         enhanced_out_periodic_adjustment[0x20];
10130
10131         u8         reserved_at_1c0[0x20];
10132 };
10133
10134 struct mlx5_ifc_mtppse_reg_bits {
10135         u8         reserved_at_0[0x18];
10136         u8         pin[0x8];
10137         u8         event_arm[0x1];
10138         u8         reserved_at_21[0x1b];
10139         u8         event_generation_mode[0x4];
10140         u8         reserved_at_40[0x40];
10141 };
10142
10143 struct mlx5_ifc_mcqs_reg_bits {
10144         u8         last_index_flag[0x1];
10145         u8         reserved_at_1[0x7];
10146         u8         fw_device[0x8];
10147         u8         component_index[0x10];
10148
10149         u8         reserved_at_20[0x10];
10150         u8         identifier[0x10];
10151
10152         u8         reserved_at_40[0x17];
10153         u8         component_status[0x5];
10154         u8         component_update_state[0x4];
10155
10156         u8         last_update_state_changer_type[0x4];
10157         u8         last_update_state_changer_host_id[0x4];
10158         u8         reserved_at_68[0x18];
10159 };
10160
10161 struct mlx5_ifc_mcqi_cap_bits {
10162         u8         supported_info_bitmask[0x20];
10163
10164         u8         component_size[0x20];
10165
10166         u8         max_component_size[0x20];
10167
10168         u8         log_mcda_word_size[0x4];
10169         u8         reserved_at_64[0xc];
10170         u8         mcda_max_write_size[0x10];
10171
10172         u8         rd_en[0x1];
10173         u8         reserved_at_81[0x1];
10174         u8         match_chip_id[0x1];
10175         u8         match_psid[0x1];
10176         u8         check_user_timestamp[0x1];
10177         u8         match_base_guid_mac[0x1];
10178         u8         reserved_at_86[0x1a];
10179 };
10180
10181 struct mlx5_ifc_mcqi_version_bits {
10182         u8         reserved_at_0[0x2];
10183         u8         build_time_valid[0x1];
10184         u8         user_defined_time_valid[0x1];
10185         u8         reserved_at_4[0x14];
10186         u8         version_string_length[0x8];
10187
10188         u8         version[0x20];
10189
10190         u8         build_time[0x40];
10191
10192         u8         user_defined_time[0x40];
10193
10194         u8         build_tool_version[0x20];
10195
10196         u8         reserved_at_e0[0x20];
10197
10198         u8         version_string[92][0x8];
10199 };
10200
10201 struct mlx5_ifc_mcqi_activation_method_bits {
10202         u8         pending_server_ac_power_cycle[0x1];
10203         u8         pending_server_dc_power_cycle[0x1];
10204         u8         pending_server_reboot[0x1];
10205         u8         pending_fw_reset[0x1];
10206         u8         auto_activate[0x1];
10207         u8         all_hosts_sync[0x1];
10208         u8         device_hw_reset[0x1];
10209         u8         reserved_at_7[0x19];
10210 };
10211
10212 union mlx5_ifc_mcqi_reg_data_bits {
10213         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10214         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10215         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10216 };
10217
10218 struct mlx5_ifc_mcqi_reg_bits {
10219         u8         read_pending_component[0x1];
10220         u8         reserved_at_1[0xf];
10221         u8         component_index[0x10];
10222
10223         u8         reserved_at_20[0x20];
10224
10225         u8         reserved_at_40[0x1b];
10226         u8         info_type[0x5];
10227
10228         u8         info_size[0x20];
10229
10230         u8         offset[0x20];
10231
10232         u8         reserved_at_a0[0x10];
10233         u8         data_size[0x10];
10234
10235         union mlx5_ifc_mcqi_reg_data_bits data[];
10236 };
10237
10238 struct mlx5_ifc_mcc_reg_bits {
10239         u8         reserved_at_0[0x4];
10240         u8         time_elapsed_since_last_cmd[0xc];
10241         u8         reserved_at_10[0x8];
10242         u8         instruction[0x8];
10243
10244         u8         reserved_at_20[0x10];
10245         u8         component_index[0x10];
10246
10247         u8         reserved_at_40[0x8];
10248         u8         update_handle[0x18];
10249
10250         u8         handle_owner_type[0x4];
10251         u8         handle_owner_host_id[0x4];
10252         u8         reserved_at_68[0x1];
10253         u8         control_progress[0x7];
10254         u8         error_code[0x8];
10255         u8         reserved_at_78[0x4];
10256         u8         control_state[0x4];
10257
10258         u8         component_size[0x20];
10259
10260         u8         reserved_at_a0[0x60];
10261 };
10262
10263 struct mlx5_ifc_mcda_reg_bits {
10264         u8         reserved_at_0[0x8];
10265         u8         update_handle[0x18];
10266
10267         u8         offset[0x20];
10268
10269         u8         reserved_at_40[0x10];
10270         u8         size[0x10];
10271
10272         u8         reserved_at_60[0x20];
10273
10274         u8         data[][0x20];
10275 };
10276
10277 enum {
10278         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10279         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10280 };
10281
10282 enum {
10283         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10284         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10285         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10286 };
10287
10288 struct mlx5_ifc_mfrl_reg_bits {
10289         u8         reserved_at_0[0x20];
10290
10291         u8         reserved_at_20[0x2];
10292         u8         pci_sync_for_fw_update_start[0x1];
10293         u8         pci_sync_for_fw_update_resp[0x2];
10294         u8         rst_type_sel[0x3];
10295         u8         reserved_at_28[0x8];
10296         u8         reset_type[0x8];
10297         u8         reset_level[0x8];
10298 };
10299
10300 struct mlx5_ifc_mirc_reg_bits {
10301         u8         reserved_at_0[0x18];
10302         u8         status_code[0x8];
10303
10304         u8         reserved_at_20[0x20];
10305 };
10306
10307 struct mlx5_ifc_pddr_monitor_opcode_bits {
10308         u8         reserved_at_0[0x10];
10309         u8         monitor_opcode[0x10];
10310 };
10311
10312 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10313         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10314         u8         reserved_at_0[0x20];
10315 };
10316
10317 enum {
10318         /* Monitor opcodes */
10319         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10320 };
10321
10322 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10323         u8         reserved_at_0[0x10];
10324         u8         group_opcode[0x10];
10325
10326         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10327
10328         u8         reserved_at_40[0x20];
10329
10330         u8         status_message[59][0x20];
10331 };
10332
10333 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10334         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10335         u8         reserved_at_0[0x7c0];
10336 };
10337
10338 enum {
10339         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10340 };
10341
10342 struct mlx5_ifc_pddr_reg_bits {
10343         u8         reserved_at_0[0x8];
10344         u8         local_port[0x8];
10345         u8         pnat[0x2];
10346         u8         reserved_at_12[0xe];
10347
10348         u8         reserved_at_20[0x18];
10349         u8         page_select[0x8];
10350
10351         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10352 };
10353
10354 union mlx5_ifc_ports_control_registers_document_bits {
10355         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10356         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10357         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10358         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10359         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10360         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10361         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10362         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10363         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10364         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10365         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10366         struct mlx5_ifc_paos_reg_bits paos_reg;
10367         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10368         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10369         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10370         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10371         struct mlx5_ifc_peir_reg_bits peir_reg;
10372         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10373         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10374         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10375         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10376         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10377         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10378         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10379         struct mlx5_ifc_plib_reg_bits plib_reg;
10380         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10381         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10382         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10383         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10384         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10385         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10386         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10387         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10388         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10389         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10390         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10391         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10392         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10393         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10394         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10395         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10396         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10397         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10398         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10399         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10400         struct mlx5_ifc_pude_reg_bits pude_reg;
10401         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10402         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10403         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10404         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10405         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10406         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10407         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10408         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10409         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10410         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10411         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10412         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10413         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10414         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10415         u8         reserved_at_0[0x60e0];
10416 };
10417
10418 union mlx5_ifc_debug_enhancements_document_bits {
10419         struct mlx5_ifc_health_buffer_bits health_buffer;
10420         u8         reserved_at_0[0x200];
10421 };
10422
10423 union mlx5_ifc_uplink_pci_interface_document_bits {
10424         struct mlx5_ifc_initial_seg_bits initial_seg;
10425         u8         reserved_at_0[0x20060];
10426 };
10427
10428 struct mlx5_ifc_set_flow_table_root_out_bits {
10429         u8         status[0x8];
10430         u8         reserved_at_8[0x18];
10431
10432         u8         syndrome[0x20];
10433
10434         u8         reserved_at_40[0x40];
10435 };
10436
10437 struct mlx5_ifc_set_flow_table_root_in_bits {
10438         u8         opcode[0x10];
10439         u8         reserved_at_10[0x10];
10440
10441         u8         reserved_at_20[0x10];
10442         u8         op_mod[0x10];
10443
10444         u8         other_vport[0x1];
10445         u8         reserved_at_41[0xf];
10446         u8         vport_number[0x10];
10447
10448         u8         reserved_at_60[0x20];
10449
10450         u8         table_type[0x8];
10451         u8         reserved_at_88[0x7];
10452         u8         table_of_other_vport[0x1];
10453         u8         table_vport_number[0x10];
10454
10455         u8         reserved_at_a0[0x8];
10456         u8         table_id[0x18];
10457
10458         u8         reserved_at_c0[0x8];
10459         u8         underlay_qpn[0x18];
10460         u8         table_eswitch_owner_vhca_id_valid[0x1];
10461         u8         reserved_at_e1[0xf];
10462         u8         table_eswitch_owner_vhca_id[0x10];
10463         u8         reserved_at_100[0x100];
10464 };
10465
10466 enum {
10467         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10468         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10469 };
10470
10471 struct mlx5_ifc_modify_flow_table_out_bits {
10472         u8         status[0x8];
10473         u8         reserved_at_8[0x18];
10474
10475         u8         syndrome[0x20];
10476
10477         u8         reserved_at_40[0x40];
10478 };
10479
10480 struct mlx5_ifc_modify_flow_table_in_bits {
10481         u8         opcode[0x10];
10482         u8         reserved_at_10[0x10];
10483
10484         u8         reserved_at_20[0x10];
10485         u8         op_mod[0x10];
10486
10487         u8         other_vport[0x1];
10488         u8         reserved_at_41[0xf];
10489         u8         vport_number[0x10];
10490
10491         u8         reserved_at_60[0x10];
10492         u8         modify_field_select[0x10];
10493
10494         u8         table_type[0x8];
10495         u8         reserved_at_88[0x18];
10496
10497         u8         reserved_at_a0[0x8];
10498         u8         table_id[0x18];
10499
10500         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10501 };
10502
10503 struct mlx5_ifc_ets_tcn_config_reg_bits {
10504         u8         g[0x1];
10505         u8         b[0x1];
10506         u8         r[0x1];
10507         u8         reserved_at_3[0x9];
10508         u8         group[0x4];
10509         u8         reserved_at_10[0x9];
10510         u8         bw_allocation[0x7];
10511
10512         u8         reserved_at_20[0xc];
10513         u8         max_bw_units[0x4];
10514         u8         reserved_at_30[0x8];
10515         u8         max_bw_value[0x8];
10516 };
10517
10518 struct mlx5_ifc_ets_global_config_reg_bits {
10519         u8         reserved_at_0[0x2];
10520         u8         r[0x1];
10521         u8         reserved_at_3[0x1d];
10522
10523         u8         reserved_at_20[0xc];
10524         u8         max_bw_units[0x4];
10525         u8         reserved_at_30[0x8];
10526         u8         max_bw_value[0x8];
10527 };
10528
10529 struct mlx5_ifc_qetc_reg_bits {
10530         u8                                         reserved_at_0[0x8];
10531         u8                                         port_number[0x8];
10532         u8                                         reserved_at_10[0x30];
10533
10534         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10535         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10536 };
10537
10538 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10539         u8         e[0x1];
10540         u8         reserved_at_01[0x0b];
10541         u8         prio[0x04];
10542 };
10543
10544 struct mlx5_ifc_qpdpm_reg_bits {
10545         u8                                     reserved_at_0[0x8];
10546         u8                                     local_port[0x8];
10547         u8                                     reserved_at_10[0x10];
10548         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10549 };
10550
10551 struct mlx5_ifc_qpts_reg_bits {
10552         u8         reserved_at_0[0x8];
10553         u8         local_port[0x8];
10554         u8         reserved_at_10[0x2d];
10555         u8         trust_state[0x3];
10556 };
10557
10558 struct mlx5_ifc_pptb_reg_bits {
10559         u8         reserved_at_0[0x2];
10560         u8         mm[0x2];
10561         u8         reserved_at_4[0x4];
10562         u8         local_port[0x8];
10563         u8         reserved_at_10[0x6];
10564         u8         cm[0x1];
10565         u8         um[0x1];
10566         u8         pm[0x8];
10567
10568         u8         prio_x_buff[0x20];
10569
10570         u8         pm_msb[0x8];
10571         u8         reserved_at_48[0x10];
10572         u8         ctrl_buff[0x4];
10573         u8         untagged_buff[0x4];
10574 };
10575
10576 struct mlx5_ifc_sbcam_reg_bits {
10577         u8         reserved_at_0[0x8];
10578         u8         feature_group[0x8];
10579         u8         reserved_at_10[0x8];
10580         u8         access_reg_group[0x8];
10581
10582         u8         reserved_at_20[0x20];
10583
10584         u8         sb_access_reg_cap_mask[4][0x20];
10585
10586         u8         reserved_at_c0[0x80];
10587
10588         u8         sb_feature_cap_mask[4][0x20];
10589
10590         u8         reserved_at_1c0[0x40];
10591
10592         u8         cap_total_buffer_size[0x20];
10593
10594         u8         cap_cell_size[0x10];
10595         u8         cap_max_pg_buffers[0x8];
10596         u8         cap_num_pool_supported[0x8];
10597
10598         u8         reserved_at_240[0x8];
10599         u8         cap_sbsr_stat_size[0x8];
10600         u8         cap_max_tclass_data[0x8];
10601         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10602 };
10603
10604 struct mlx5_ifc_pbmc_reg_bits {
10605         u8         reserved_at_0[0x8];
10606         u8         local_port[0x8];
10607         u8         reserved_at_10[0x10];
10608
10609         u8         xoff_timer_value[0x10];
10610         u8         xoff_refresh[0x10];
10611
10612         u8         reserved_at_40[0x9];
10613         u8         fullness_threshold[0x7];
10614         u8         port_buffer_size[0x10];
10615
10616         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10617
10618         u8         reserved_at_2e0[0x80];
10619 };
10620
10621 struct mlx5_ifc_qtct_reg_bits {
10622         u8         reserved_at_0[0x8];
10623         u8         port_number[0x8];
10624         u8         reserved_at_10[0xd];
10625         u8         prio[0x3];
10626
10627         u8         reserved_at_20[0x1d];
10628         u8         tclass[0x3];
10629 };
10630
10631 struct mlx5_ifc_mcia_reg_bits {
10632         u8         l[0x1];
10633         u8         reserved_at_1[0x7];
10634         u8         module[0x8];
10635         u8         reserved_at_10[0x8];
10636         u8         status[0x8];
10637
10638         u8         i2c_device_address[0x8];
10639         u8         page_number[0x8];
10640         u8         device_address[0x10];
10641
10642         u8         reserved_at_40[0x10];
10643         u8         size[0x10];
10644
10645         u8         reserved_at_60[0x20];
10646
10647         u8         dword_0[0x20];
10648         u8         dword_1[0x20];
10649         u8         dword_2[0x20];
10650         u8         dword_3[0x20];
10651         u8         dword_4[0x20];
10652         u8         dword_5[0x20];
10653         u8         dword_6[0x20];
10654         u8         dword_7[0x20];
10655         u8         dword_8[0x20];
10656         u8         dword_9[0x20];
10657         u8         dword_10[0x20];
10658         u8         dword_11[0x20];
10659 };
10660
10661 struct mlx5_ifc_dcbx_param_bits {
10662         u8         dcbx_cee_cap[0x1];
10663         u8         dcbx_ieee_cap[0x1];
10664         u8         dcbx_standby_cap[0x1];
10665         u8         reserved_at_3[0x5];
10666         u8         port_number[0x8];
10667         u8         reserved_at_10[0xa];
10668         u8         max_application_table_size[6];
10669         u8         reserved_at_20[0x15];
10670         u8         version_oper[0x3];
10671         u8         reserved_at_38[5];
10672         u8         version_admin[0x3];
10673         u8         willing_admin[0x1];
10674         u8         reserved_at_41[0x3];
10675         u8         pfc_cap_oper[0x4];
10676         u8         reserved_at_48[0x4];
10677         u8         pfc_cap_admin[0x4];
10678         u8         reserved_at_50[0x4];
10679         u8         num_of_tc_oper[0x4];
10680         u8         reserved_at_58[0x4];
10681         u8         num_of_tc_admin[0x4];
10682         u8         remote_willing[0x1];
10683         u8         reserved_at_61[3];
10684         u8         remote_pfc_cap[4];
10685         u8         reserved_at_68[0x14];
10686         u8         remote_num_of_tc[0x4];
10687         u8         reserved_at_80[0x18];
10688         u8         error[0x8];
10689         u8         reserved_at_a0[0x160];
10690 };
10691
10692 enum {
10693         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10694         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT,
10695 };
10696
10697 struct mlx5_ifc_lagc_bits {
10698         u8         fdb_selection_mode[0x1];
10699         u8         reserved_at_1[0x14];
10700         u8         port_select_mode[0x3];
10701         u8         reserved_at_18[0x5];
10702         u8         lag_state[0x3];
10703
10704         u8         reserved_at_20[0x14];
10705         u8         tx_remap_affinity_2[0x4];
10706         u8         reserved_at_38[0x4];
10707         u8         tx_remap_affinity_1[0x4];
10708 };
10709
10710 struct mlx5_ifc_create_lag_out_bits {
10711         u8         status[0x8];
10712         u8         reserved_at_8[0x18];
10713
10714         u8         syndrome[0x20];
10715
10716         u8         reserved_at_40[0x40];
10717 };
10718
10719 struct mlx5_ifc_create_lag_in_bits {
10720         u8         opcode[0x10];
10721         u8         reserved_at_10[0x10];
10722
10723         u8         reserved_at_20[0x10];
10724         u8         op_mod[0x10];
10725
10726         struct mlx5_ifc_lagc_bits ctx;
10727 };
10728
10729 struct mlx5_ifc_modify_lag_out_bits {
10730         u8         status[0x8];
10731         u8         reserved_at_8[0x18];
10732
10733         u8         syndrome[0x20];
10734
10735         u8         reserved_at_40[0x40];
10736 };
10737
10738 struct mlx5_ifc_modify_lag_in_bits {
10739         u8         opcode[0x10];
10740         u8         reserved_at_10[0x10];
10741
10742         u8         reserved_at_20[0x10];
10743         u8         op_mod[0x10];
10744
10745         u8         reserved_at_40[0x20];
10746         u8         field_select[0x20];
10747
10748         struct mlx5_ifc_lagc_bits ctx;
10749 };
10750
10751 struct mlx5_ifc_query_lag_out_bits {
10752         u8         status[0x8];
10753         u8         reserved_at_8[0x18];
10754
10755         u8         syndrome[0x20];
10756
10757         struct mlx5_ifc_lagc_bits ctx;
10758 };
10759
10760 struct mlx5_ifc_query_lag_in_bits {
10761         u8         opcode[0x10];
10762         u8         reserved_at_10[0x10];
10763
10764         u8         reserved_at_20[0x10];
10765         u8         op_mod[0x10];
10766
10767         u8         reserved_at_40[0x40];
10768 };
10769
10770 struct mlx5_ifc_destroy_lag_out_bits {
10771         u8         status[0x8];
10772         u8         reserved_at_8[0x18];
10773
10774         u8         syndrome[0x20];
10775
10776         u8         reserved_at_40[0x40];
10777 };
10778
10779 struct mlx5_ifc_destroy_lag_in_bits {
10780         u8         opcode[0x10];
10781         u8         reserved_at_10[0x10];
10782
10783         u8         reserved_at_20[0x10];
10784         u8         op_mod[0x10];
10785
10786         u8         reserved_at_40[0x40];
10787 };
10788
10789 struct mlx5_ifc_create_vport_lag_out_bits {
10790         u8         status[0x8];
10791         u8         reserved_at_8[0x18];
10792
10793         u8         syndrome[0x20];
10794
10795         u8         reserved_at_40[0x40];
10796 };
10797
10798 struct mlx5_ifc_create_vport_lag_in_bits {
10799         u8         opcode[0x10];
10800         u8         reserved_at_10[0x10];
10801
10802         u8         reserved_at_20[0x10];
10803         u8         op_mod[0x10];
10804
10805         u8         reserved_at_40[0x40];
10806 };
10807
10808 struct mlx5_ifc_destroy_vport_lag_out_bits {
10809         u8         status[0x8];
10810         u8         reserved_at_8[0x18];
10811
10812         u8         syndrome[0x20];
10813
10814         u8         reserved_at_40[0x40];
10815 };
10816
10817 struct mlx5_ifc_destroy_vport_lag_in_bits {
10818         u8         opcode[0x10];
10819         u8         reserved_at_10[0x10];
10820
10821         u8         reserved_at_20[0x10];
10822         u8         op_mod[0x10];
10823
10824         u8         reserved_at_40[0x40];
10825 };
10826
10827 enum {
10828         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10829         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10830 };
10831
10832 struct mlx5_ifc_modify_memic_in_bits {
10833         u8         opcode[0x10];
10834         u8         uid[0x10];
10835
10836         u8         reserved_at_20[0x10];
10837         u8         op_mod[0x10];
10838
10839         u8         reserved_at_40[0x20];
10840
10841         u8         reserved_at_60[0x18];
10842         u8         memic_operation_type[0x8];
10843
10844         u8         memic_start_addr[0x40];
10845
10846         u8         reserved_at_c0[0x140];
10847 };
10848
10849 struct mlx5_ifc_modify_memic_out_bits {
10850         u8         status[0x8];
10851         u8         reserved_at_8[0x18];
10852
10853         u8         syndrome[0x20];
10854
10855         u8         reserved_at_40[0x40];
10856
10857         u8         memic_operation_addr[0x40];
10858
10859         u8         reserved_at_c0[0x140];
10860 };
10861
10862 struct mlx5_ifc_alloc_memic_in_bits {
10863         u8         opcode[0x10];
10864         u8         reserved_at_10[0x10];
10865
10866         u8         reserved_at_20[0x10];
10867         u8         op_mod[0x10];
10868
10869         u8         reserved_at_30[0x20];
10870
10871         u8         reserved_at_40[0x18];
10872         u8         log_memic_addr_alignment[0x8];
10873
10874         u8         range_start_addr[0x40];
10875
10876         u8         range_size[0x20];
10877
10878         u8         memic_size[0x20];
10879 };
10880
10881 struct mlx5_ifc_alloc_memic_out_bits {
10882         u8         status[0x8];
10883         u8         reserved_at_8[0x18];
10884
10885         u8         syndrome[0x20];
10886
10887         u8         memic_start_addr[0x40];
10888 };
10889
10890 struct mlx5_ifc_dealloc_memic_in_bits {
10891         u8         opcode[0x10];
10892         u8         reserved_at_10[0x10];
10893
10894         u8         reserved_at_20[0x10];
10895         u8         op_mod[0x10];
10896
10897         u8         reserved_at_40[0x40];
10898
10899         u8         memic_start_addr[0x40];
10900
10901         u8         memic_size[0x20];
10902
10903         u8         reserved_at_e0[0x20];
10904 };
10905
10906 struct mlx5_ifc_dealloc_memic_out_bits {
10907         u8         status[0x8];
10908         u8         reserved_at_8[0x18];
10909
10910         u8         syndrome[0x20];
10911
10912         u8         reserved_at_40[0x40];
10913 };
10914
10915 struct mlx5_ifc_umem_bits {
10916         u8         reserved_at_0[0x80];
10917
10918         u8         reserved_at_80[0x1b];
10919         u8         log_page_size[0x5];
10920
10921         u8         page_offset[0x20];
10922
10923         u8         num_of_mtt[0x40];
10924
10925         struct mlx5_ifc_mtt_bits  mtt[];
10926 };
10927
10928 struct mlx5_ifc_uctx_bits {
10929         u8         cap[0x20];
10930
10931         u8         reserved_at_20[0x160];
10932 };
10933
10934 struct mlx5_ifc_sw_icm_bits {
10935         u8         modify_field_select[0x40];
10936
10937         u8         reserved_at_40[0x18];
10938         u8         log_sw_icm_size[0x8];
10939
10940         u8         reserved_at_60[0x20];
10941
10942         u8         sw_icm_start_addr[0x40];
10943
10944         u8         reserved_at_c0[0x140];
10945 };
10946
10947 struct mlx5_ifc_geneve_tlv_option_bits {
10948         u8         modify_field_select[0x40];
10949
10950         u8         reserved_at_40[0x18];
10951         u8         geneve_option_fte_index[0x8];
10952
10953         u8         option_class[0x10];
10954         u8         option_type[0x8];
10955         u8         reserved_at_78[0x3];
10956         u8         option_data_length[0x5];
10957
10958         u8         reserved_at_80[0x180];
10959 };
10960
10961 struct mlx5_ifc_create_umem_in_bits {
10962         u8         opcode[0x10];
10963         u8         uid[0x10];
10964
10965         u8         reserved_at_20[0x10];
10966         u8         op_mod[0x10];
10967
10968         u8         reserved_at_40[0x40];
10969
10970         struct mlx5_ifc_umem_bits  umem;
10971 };
10972
10973 struct mlx5_ifc_create_umem_out_bits {
10974         u8         status[0x8];
10975         u8         reserved_at_8[0x18];
10976
10977         u8         syndrome[0x20];
10978
10979         u8         reserved_at_40[0x8];
10980         u8         umem_id[0x18];
10981
10982         u8         reserved_at_60[0x20];
10983 };
10984
10985 struct mlx5_ifc_destroy_umem_in_bits {
10986         u8        opcode[0x10];
10987         u8        uid[0x10];
10988
10989         u8        reserved_at_20[0x10];
10990         u8        op_mod[0x10];
10991
10992         u8        reserved_at_40[0x8];
10993         u8        umem_id[0x18];
10994
10995         u8        reserved_at_60[0x20];
10996 };
10997
10998 struct mlx5_ifc_destroy_umem_out_bits {
10999         u8        status[0x8];
11000         u8        reserved_at_8[0x18];
11001
11002         u8        syndrome[0x20];
11003
11004         u8        reserved_at_40[0x40];
11005 };
11006
11007 struct mlx5_ifc_create_uctx_in_bits {
11008         u8         opcode[0x10];
11009         u8         reserved_at_10[0x10];
11010
11011         u8         reserved_at_20[0x10];
11012         u8         op_mod[0x10];
11013
11014         u8         reserved_at_40[0x40];
11015
11016         struct mlx5_ifc_uctx_bits  uctx;
11017 };
11018
11019 struct mlx5_ifc_create_uctx_out_bits {
11020         u8         status[0x8];
11021         u8         reserved_at_8[0x18];
11022
11023         u8         syndrome[0x20];
11024
11025         u8         reserved_at_40[0x10];
11026         u8         uid[0x10];
11027
11028         u8         reserved_at_60[0x20];
11029 };
11030
11031 struct mlx5_ifc_destroy_uctx_in_bits {
11032         u8         opcode[0x10];
11033         u8         reserved_at_10[0x10];
11034
11035         u8         reserved_at_20[0x10];
11036         u8         op_mod[0x10];
11037
11038         u8         reserved_at_40[0x10];
11039         u8         uid[0x10];
11040
11041         u8         reserved_at_60[0x20];
11042 };
11043
11044 struct mlx5_ifc_destroy_uctx_out_bits {
11045         u8         status[0x8];
11046         u8         reserved_at_8[0x18];
11047
11048         u8         syndrome[0x20];
11049
11050         u8          reserved_at_40[0x40];
11051 };
11052
11053 struct mlx5_ifc_create_sw_icm_in_bits {
11054         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11055         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11056 };
11057
11058 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11059         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11060         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11061 };
11062
11063 struct mlx5_ifc_mtrc_string_db_param_bits {
11064         u8         string_db_base_address[0x20];
11065
11066         u8         reserved_at_20[0x8];
11067         u8         string_db_size[0x18];
11068 };
11069
11070 struct mlx5_ifc_mtrc_cap_bits {
11071         u8         trace_owner[0x1];
11072         u8         trace_to_memory[0x1];
11073         u8         reserved_at_2[0x4];
11074         u8         trc_ver[0x2];
11075         u8         reserved_at_8[0x14];
11076         u8         num_string_db[0x4];
11077
11078         u8         first_string_trace[0x8];
11079         u8         num_string_trace[0x8];
11080         u8         reserved_at_30[0x28];
11081
11082         u8         log_max_trace_buffer_size[0x8];
11083
11084         u8         reserved_at_60[0x20];
11085
11086         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11087
11088         u8         reserved_at_280[0x180];
11089 };
11090
11091 struct mlx5_ifc_mtrc_conf_bits {
11092         u8         reserved_at_0[0x1c];
11093         u8         trace_mode[0x4];
11094         u8         reserved_at_20[0x18];
11095         u8         log_trace_buffer_size[0x8];
11096         u8         trace_mkey[0x20];
11097         u8         reserved_at_60[0x3a0];
11098 };
11099
11100 struct mlx5_ifc_mtrc_stdb_bits {
11101         u8         string_db_index[0x4];
11102         u8         reserved_at_4[0x4];
11103         u8         read_size[0x18];
11104         u8         start_offset[0x20];
11105         u8         string_db_data[];
11106 };
11107
11108 struct mlx5_ifc_mtrc_ctrl_bits {
11109         u8         trace_status[0x2];
11110         u8         reserved_at_2[0x2];
11111         u8         arm_event[0x1];
11112         u8         reserved_at_5[0xb];
11113         u8         modify_field_select[0x10];
11114         u8         reserved_at_20[0x2b];
11115         u8         current_timestamp52_32[0x15];
11116         u8         current_timestamp31_0[0x20];
11117         u8         reserved_at_80[0x180];
11118 };
11119
11120 struct mlx5_ifc_host_params_context_bits {
11121         u8         host_number[0x8];
11122         u8         reserved_at_8[0x7];
11123         u8         host_pf_disabled[0x1];
11124         u8         host_num_of_vfs[0x10];
11125
11126         u8         host_total_vfs[0x10];
11127         u8         host_pci_bus[0x10];
11128
11129         u8         reserved_at_40[0x10];
11130         u8         host_pci_device[0x10];
11131
11132         u8         reserved_at_60[0x10];
11133         u8         host_pci_function[0x10];
11134
11135         u8         reserved_at_80[0x180];
11136 };
11137
11138 struct mlx5_ifc_query_esw_functions_in_bits {
11139         u8         opcode[0x10];
11140         u8         reserved_at_10[0x10];
11141
11142         u8         reserved_at_20[0x10];
11143         u8         op_mod[0x10];
11144
11145         u8         reserved_at_40[0x40];
11146 };
11147
11148 struct mlx5_ifc_query_esw_functions_out_bits {
11149         u8         status[0x8];
11150         u8         reserved_at_8[0x18];
11151
11152         u8         syndrome[0x20];
11153
11154         u8         reserved_at_40[0x40];
11155
11156         struct mlx5_ifc_host_params_context_bits host_params_context;
11157
11158         u8         reserved_at_280[0x180];
11159         u8         host_sf_enable[][0x40];
11160 };
11161
11162 struct mlx5_ifc_sf_partition_bits {
11163         u8         reserved_at_0[0x10];
11164         u8         log_num_sf[0x8];
11165         u8         log_sf_bar_size[0x8];
11166 };
11167
11168 struct mlx5_ifc_query_sf_partitions_out_bits {
11169         u8         status[0x8];
11170         u8         reserved_at_8[0x18];
11171
11172         u8         syndrome[0x20];
11173
11174         u8         reserved_at_40[0x18];
11175         u8         num_sf_partitions[0x8];
11176
11177         u8         reserved_at_60[0x20];
11178
11179         struct mlx5_ifc_sf_partition_bits sf_partition[];
11180 };
11181
11182 struct mlx5_ifc_query_sf_partitions_in_bits {
11183         u8         opcode[0x10];
11184         u8         reserved_at_10[0x10];
11185
11186         u8         reserved_at_20[0x10];
11187         u8         op_mod[0x10];
11188
11189         u8         reserved_at_40[0x40];
11190 };
11191
11192 struct mlx5_ifc_dealloc_sf_out_bits {
11193         u8         status[0x8];
11194         u8         reserved_at_8[0x18];
11195
11196         u8         syndrome[0x20];
11197
11198         u8         reserved_at_40[0x40];
11199 };
11200
11201 struct mlx5_ifc_dealloc_sf_in_bits {
11202         u8         opcode[0x10];
11203         u8         reserved_at_10[0x10];
11204
11205         u8         reserved_at_20[0x10];
11206         u8         op_mod[0x10];
11207
11208         u8         reserved_at_40[0x10];
11209         u8         function_id[0x10];
11210
11211         u8         reserved_at_60[0x20];
11212 };
11213
11214 struct mlx5_ifc_alloc_sf_out_bits {
11215         u8         status[0x8];
11216         u8         reserved_at_8[0x18];
11217
11218         u8         syndrome[0x20];
11219
11220         u8         reserved_at_40[0x40];
11221 };
11222
11223 struct mlx5_ifc_alloc_sf_in_bits {
11224         u8         opcode[0x10];
11225         u8         reserved_at_10[0x10];
11226
11227         u8         reserved_at_20[0x10];
11228         u8         op_mod[0x10];
11229
11230         u8         reserved_at_40[0x10];
11231         u8         function_id[0x10];
11232
11233         u8         reserved_at_60[0x20];
11234 };
11235
11236 struct mlx5_ifc_affiliated_event_header_bits {
11237         u8         reserved_at_0[0x10];
11238         u8         obj_type[0x10];
11239
11240         u8         obj_id[0x20];
11241 };
11242
11243 enum {
11244         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11245         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11246         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11247 };
11248
11249 enum {
11250         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11251         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11252         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11253 };
11254
11255 enum {
11256         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11257         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
11258         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
11259 };
11260
11261 struct mlx5_ifc_ipsec_obj_bits {
11262         u8         modify_field_select[0x40];
11263         u8         full_offload[0x1];
11264         u8         reserved_at_41[0x1];
11265         u8         esn_en[0x1];
11266         u8         esn_overlap[0x1];
11267         u8         reserved_at_44[0x2];
11268         u8         icv_length[0x2];
11269         u8         reserved_at_48[0x4];
11270         u8         aso_return_reg[0x4];
11271         u8         reserved_at_50[0x10];
11272
11273         u8         esn_msb[0x20];
11274
11275         u8         reserved_at_80[0x8];
11276         u8         dekn[0x18];
11277
11278         u8         salt[0x20];
11279
11280         u8         implicit_iv[0x40];
11281
11282         u8         reserved_at_100[0x700];
11283 };
11284
11285 struct mlx5_ifc_create_ipsec_obj_in_bits {
11286         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11287         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11288 };
11289
11290 enum {
11291         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11292         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11293 };
11294
11295 struct mlx5_ifc_query_ipsec_obj_out_bits {
11296         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11297         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11298 };
11299
11300 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11301         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11302         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11303 };
11304
11305 struct mlx5_ifc_encryption_key_obj_bits {
11306         u8         modify_field_select[0x40];
11307
11308         u8         reserved_at_40[0x14];
11309         u8         key_size[0x4];
11310         u8         reserved_at_58[0x4];
11311         u8         key_type[0x4];
11312
11313         u8         reserved_at_60[0x8];
11314         u8         pd[0x18];
11315
11316         u8         reserved_at_80[0x180];
11317         u8         key[8][0x20];
11318
11319         u8         reserved_at_300[0x500];
11320 };
11321
11322 struct mlx5_ifc_create_encryption_key_in_bits {
11323         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11324         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11325 };
11326
11327 struct mlx5_ifc_sampler_obj_bits {
11328         u8         modify_field_select[0x40];
11329
11330         u8         table_type[0x8];
11331         u8         level[0x8];
11332         u8         reserved_at_50[0xf];
11333         u8         ignore_flow_level[0x1];
11334
11335         u8         sample_ratio[0x20];
11336
11337         u8         reserved_at_80[0x8];
11338         u8         sample_table_id[0x18];
11339
11340         u8         reserved_at_a0[0x8];
11341         u8         default_table_id[0x18];
11342
11343         u8         sw_steering_icm_address_rx[0x40];
11344         u8         sw_steering_icm_address_tx[0x40];
11345
11346         u8         reserved_at_140[0xa0];
11347 };
11348
11349 struct mlx5_ifc_create_sampler_obj_in_bits {
11350         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11351         struct mlx5_ifc_sampler_obj_bits sampler_object;
11352 };
11353
11354 struct mlx5_ifc_query_sampler_obj_out_bits {
11355         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11356         struct mlx5_ifc_sampler_obj_bits sampler_object;
11357 };
11358
11359 enum {
11360         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11361         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11362 };
11363
11364 enum {
11365         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11366         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11367 };
11368
11369 struct mlx5_ifc_tls_static_params_bits {
11370         u8         const_2[0x2];
11371         u8         tls_version[0x4];
11372         u8         const_1[0x2];
11373         u8         reserved_at_8[0x14];
11374         u8         encryption_standard[0x4];
11375
11376         u8         reserved_at_20[0x20];
11377
11378         u8         initial_record_number[0x40];
11379
11380         u8         resync_tcp_sn[0x20];
11381
11382         u8         gcm_iv[0x20];
11383
11384         u8         implicit_iv[0x40];
11385
11386         u8         reserved_at_100[0x8];
11387         u8         dek_index[0x18];
11388
11389         u8         reserved_at_120[0xe0];
11390 };
11391
11392 struct mlx5_ifc_tls_progress_params_bits {
11393         u8         next_record_tcp_sn[0x20];
11394
11395         u8         hw_resync_tcp_sn[0x20];
11396
11397         u8         record_tracker_state[0x2];
11398         u8         auth_state[0x2];
11399         u8         reserved_at_44[0x4];
11400         u8         hw_offset_record_number[0x18];
11401 };
11402
11403 enum {
11404         MLX5_MTT_PERM_READ      = 1 << 0,
11405         MLX5_MTT_PERM_WRITE     = 1 << 1,
11406         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11407 };
11408
11409 #endif /* MLX5_IFC_H */