2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
26 #include <linux/types.h>
29 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
30 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
31 * 1.0 devices basically don't exist in the wild.
33 * Abbreviations, in chronological order:
35 * eDP: Embedded DisplayPort version 1
36 * DPI: DisplayPort Interoperability Guideline v1.1a
37 * 1.2: DisplayPort 1.2
38 * MST: Multistream Transport - part of DP 1.2a
40 * 1.2 formally includes both eDP and DPI definitions.
43 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
45 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
47 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
48 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
49 /* bits per component for non-RAW */
50 #define DP_MSA_MISC_6_BPC (0 << 5)
51 #define DP_MSA_MISC_8_BPC (1 << 5)
52 #define DP_MSA_MISC_10_BPC (2 << 5)
53 #define DP_MSA_MISC_12_BPC (3 << 5)
54 #define DP_MSA_MISC_16_BPC (4 << 5)
55 /* bits per component for RAW */
56 #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
57 #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
58 #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
59 #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
60 #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
61 #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
62 #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
63 /* pixel encoding/colorimetry format */
64 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
65 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
74 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
76 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
78 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
80 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
81 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
82 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
83 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
85 #define DP_AUX_MAX_PAYLOAD_BYTES 16
87 #define DP_AUX_I2C_WRITE 0x0
88 #define DP_AUX_I2C_READ 0x1
89 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
90 #define DP_AUX_I2C_MOT 0x4
91 #define DP_AUX_NATIVE_WRITE 0x8
92 #define DP_AUX_NATIVE_READ 0x9
94 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
95 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
96 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
97 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
99 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
100 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
101 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
102 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
104 /* DPCD Field Address Mapping */
106 /* Receiver Capability */
107 #define DP_DPCD_REV 0x000
108 # define DP_DPCD_REV_10 0x10
109 # define DP_DPCD_REV_11 0x11
110 # define DP_DPCD_REV_12 0x12
111 # define DP_DPCD_REV_13 0x13
112 # define DP_DPCD_REV_14 0x14
114 #define DP_MAX_LINK_RATE 0x001
116 #define DP_MAX_LANE_COUNT 0x002
117 # define DP_MAX_LANE_COUNT_MASK 0x1f
118 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
119 # define DP_ENHANCED_FRAME_CAP (1 << 7)
121 #define DP_MAX_DOWNSPREAD 0x003
122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
123 # define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
124 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
125 # define DP_TPS4_SUPPORTED (1 << 7)
127 #define DP_NORP 0x004
129 #define DP_DOWNSTREAMPORT_PRESENT 0x005
130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
133 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
134 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
135 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
136 # define DP_FORMAT_CONVERSION (1 << 3)
137 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
140 # define DP_CAP_ANSI_8B10B (1 << 0)
141 # define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
143 #define DP_DOWN_STREAM_PORT_COUNT 0x007
144 # define DP_PORT_COUNT_MASK 0x0f
145 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
146 # define DP_OUI_SUPPORT (1 << 7)
148 #define DP_RECEIVE_PORT_0_CAP_0 0x008
149 # define DP_LOCAL_EDID_PRESENT (1 << 1)
150 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
152 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
154 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
155 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
157 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
158 # define DP_I2C_SPEED_1K 0x01
159 # define DP_I2C_SPEED_5K 0x02
160 # define DP_I2C_SPEED_10K 0x04
161 # define DP_I2C_SPEED_100K 0x08
162 # define DP_I2C_SPEED_400K 0x10
163 # define DP_I2C_SPEED_1M 0x20
165 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
166 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
167 # define DP_FRAMING_CHANGE_CAP (1 << 1)
168 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
170 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
171 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
172 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
174 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
175 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
176 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
178 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
179 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
181 /* Multiple stream transport */
182 #define DP_FAUX_CAP 0x020 /* 1.2 */
183 # define DP_FAUX_CAP_1 (1 << 0)
185 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
186 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
187 # define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
188 # define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
190 #define DP_MSTM_CAP 0x021 /* 1.2 */
191 # define DP_MST_CAP (1 << 0)
192 # define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
194 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
196 /* AV_SYNC_DATA_BLOCK 1.2 */
197 #define DP_AV_GRANULARITY 0x023
198 # define DP_AG_FACTOR_MASK (0xf << 0)
199 # define DP_AG_FACTOR_3MS (0 << 0)
200 # define DP_AG_FACTOR_2MS (1 << 0)
201 # define DP_AG_FACTOR_1MS (2 << 0)
202 # define DP_AG_FACTOR_500US (3 << 0)
203 # define DP_AG_FACTOR_200US (4 << 0)
204 # define DP_AG_FACTOR_100US (5 << 0)
205 # define DP_AG_FACTOR_10US (6 << 0)
206 # define DP_AG_FACTOR_1US (7 << 0)
207 # define DP_VG_FACTOR_MASK (0xf << 4)
208 # define DP_VG_FACTOR_3MS (0 << 4)
209 # define DP_VG_FACTOR_2MS (1 << 4)
210 # define DP_VG_FACTOR_1MS (2 << 4)
211 # define DP_VG_FACTOR_500US (3 << 4)
212 # define DP_VG_FACTOR_200US (4 << 4)
213 # define DP_VG_FACTOR_100US (5 << 4)
215 #define DP_AUD_DEC_LAT0 0x024
216 #define DP_AUD_DEC_LAT1 0x025
218 #define DP_AUD_PP_LAT0 0x026
219 #define DP_AUD_PP_LAT1 0x027
221 #define DP_VID_INTER_LAT 0x028
223 #define DP_VID_PROG_LAT 0x029
225 #define DP_REP_LAT 0x02a
227 #define DP_AUD_DEL_INS0 0x02b
228 #define DP_AUD_DEL_INS1 0x02c
229 #define DP_AUD_DEL_INS2 0x02d
230 /* End of AV_SYNC_DATA_BLOCK */
232 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
233 # define DP_ALPM_CAP (1 << 0)
235 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
236 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
238 #define DP_GUID 0x030 /* 1.2 */
240 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
241 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
242 # define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1)
244 #define DP_DSC_REV 0x061
245 # define DP_DSC_MAJOR_MASK (0xf << 0)
246 # define DP_DSC_MINOR_MASK (0xf << 4)
247 # define DP_DSC_MAJOR_SHIFT 0
248 # define DP_DSC_MINOR_SHIFT 4
250 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
251 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
252 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
253 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
254 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
256 #define DP_DSC_RC_BUF_SIZE 0x063
258 #define DP_DSC_SLICE_CAP_1 0x064
259 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
260 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
261 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
262 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
263 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
264 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
265 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
267 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
268 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
269 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
270 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
271 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
272 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
273 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
274 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
275 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
276 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
277 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
279 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
280 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
282 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
284 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
285 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
286 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
288 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
289 # define DP_DSC_RGB (1 << 0)
290 # define DP_DSC_YCbCr444 (1 << 1)
291 # define DP_DSC_YCbCr422_Simple (1 << 2)
292 # define DP_DSC_YCbCr422_Native (1 << 3)
293 # define DP_DSC_YCbCr420_Native (1 << 4)
295 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
296 # define DP_DSC_8_BPC (1 << 1)
297 # define DP_DSC_10_BPC (1 << 2)
298 # define DP_DSC_12_BPC (1 << 3)
300 #define DP_DSC_PEAK_THROUGHPUT 0x06B
301 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
302 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
303 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
304 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
305 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
306 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
307 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
308 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
310 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
311 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
314 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
315 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
316 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
317 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
318 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
319 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
320 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
321 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
322 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
323 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
324 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
325 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
326 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
327 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
328 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
329 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
330 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
331 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
332 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
333 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
334 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
335 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
336 # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
338 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
339 #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
340 #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
342 #define DP_DSC_SLICE_CAP_2 0x06D
343 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
344 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
345 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
347 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
348 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
349 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
350 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
351 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
352 # define DP_DSC_BITS_PER_PIXEL_1 0x4
354 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
355 # define DP_PSR_IS_SUPPORTED 1
356 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
357 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
358 # define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */
360 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
361 # define DP_PSR_NO_TRAIN_ON_EXIT 1
362 # define DP_PSR_SETUP_TIME_330 (0 << 1)
363 # define DP_PSR_SETUP_TIME_275 (1 << 1)
364 # define DP_PSR_SETUP_TIME_220 (2 << 1)
365 # define DP_PSR_SETUP_TIME_165 (3 << 1)
366 # define DP_PSR_SETUP_TIME_110 (4 << 1)
367 # define DP_PSR_SETUP_TIME_55 (5 << 1)
368 # define DP_PSR_SETUP_TIME_0 (6 << 1)
369 # define DP_PSR_SETUP_TIME_MASK (7 << 1)
370 # define DP_PSR_SETUP_TIME_SHIFT 1
371 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
372 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
373 # define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */
375 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
376 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
379 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
380 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
381 * each port's descriptor is one byte wide. If it was set, each port's is
382 * four bytes wide, starting with the one byte from the base info. As of
383 * DP interop v1.1a only VGA defines additional detail.
387 #define DP_DOWNSTREAM_PORT_0 0x80
388 # define DP_DS_PORT_TYPE_MASK (7 << 0)
389 # define DP_DS_PORT_TYPE_DP 0
390 # define DP_DS_PORT_TYPE_VGA 1
391 # define DP_DS_PORT_TYPE_DVI 2
392 # define DP_DS_PORT_TYPE_HDMI 3
393 # define DP_DS_PORT_TYPE_NON_EDID 4
394 # define DP_DS_PORT_TYPE_DP_DUALMODE 5
395 # define DP_DS_PORT_TYPE_WIRELESS 6
396 # define DP_DS_PORT_HPD (1 << 3)
397 # define DP_DS_NON_EDID_MASK (0xf << 4)
398 # define DP_DS_NON_EDID_720x480i_60 (1 << 4)
399 # define DP_DS_NON_EDID_720x480i_50 (2 << 4)
400 # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
401 # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
402 # define DP_DS_NON_EDID_1280x720_60 (5 << 4)
403 # define DP_DS_NON_EDID_1280x720_50 (7 << 4)
404 /* offset 1 for VGA is maximum megapixels per second / 8 */
405 /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
406 /* offset 2 for VGA/DVI/HDMI */
407 # define DP_DS_MAX_BPC_MASK (3 << 0)
408 # define DP_DS_8BPC 0
409 # define DP_DS_10BPC 1
410 # define DP_DS_12BPC 2
411 # define DP_DS_16BPC 3
412 /* HDMI2.1 PCON FRL CONFIGURATION */
413 # define DP_PCON_MAX_FRL_BW (7 << 2)
414 # define DP_PCON_MAX_0GBPS (0 << 2)
415 # define DP_PCON_MAX_9GBPS (1 << 2)
416 # define DP_PCON_MAX_18GBPS (2 << 2)
417 # define DP_PCON_MAX_24GBPS (3 << 2)
418 # define DP_PCON_MAX_32GBPS (4 << 2)
419 # define DP_PCON_MAX_40GBPS (5 << 2)
420 # define DP_PCON_MAX_48GBPS (6 << 2)
421 # define DP_PCON_SOURCE_CTL_MODE (1 << 5)
423 /* offset 3 for DVI */
424 # define DP_DS_DVI_DUAL_LINK (1 << 1)
425 # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
426 /* offset 3 for HDMI */
427 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
428 # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
429 # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
430 # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
431 # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
434 * VESA DP-to-HDMI PCON Specification adds caps for colorspace
435 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
436 * Based on the available support the source can enable
437 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
440 # define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
441 # define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
442 # define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
444 #define DP_MAX_DOWNSTREAM_PORTS 0x10
446 /* DP Forward error Correction Registers */
447 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
448 # define DP_FEC_CAPABLE (1 << 0)
449 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
450 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
451 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
452 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
454 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
455 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
456 #define DP_PCON_DSC_ENCODER 0x092
457 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
458 # define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
460 /* DP-HDMI2.1 PCON DSC Version */
461 #define DP_PCON_DSC_VERSION 0x093
462 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
463 # define DP_PCON_DSC_MINOR_MASK (0xF << 4)
464 # define DP_PCON_DSC_MAJOR_SHIFT 0
465 # define DP_PCON_DSC_MINOR_SHIFT 4
467 /* DP-HDMI2.1 PCON DSC RC Buffer block size */
468 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
469 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
470 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0
471 # define DP_PCON_DSC_RC_BUF_BLK_4KB 1
472 # define DP_PCON_DSC_RC_BUF_BLK_16KB 2
473 # define DP_PCON_DSC_RC_BUF_BLK_64KB 3
475 /* DP-HDMI2.1 PCON DSC RC Buffer size */
476 #define DP_PCON_DSC_RC_BUF_SIZE 0x095
478 /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
479 #define DP_PCON_DSC_SLICE_CAP_1 0x096
480 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
481 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
482 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
483 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
484 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
485 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
486 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
488 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
489 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
490 # define DP_PCON_DSC_DEPTH_9_BITS 0
491 # define DP_PCON_DSC_DEPTH_10_BITS 1
492 # define DP_PCON_DSC_DEPTH_11_BITS 2
493 # define DP_PCON_DSC_DEPTH_12_BITS 3
494 # define DP_PCON_DSC_DEPTH_13_BITS 4
495 # define DP_PCON_DSC_DEPTH_14_BITS 5
496 # define DP_PCON_DSC_DEPTH_15_BITS 6
497 # define DP_PCON_DSC_DEPTH_16_BITS 7
498 # define DP_PCON_DSC_DEPTH_8_BITS 8
500 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098
501 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
503 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
504 # define DP_PCON_DSC_ENC_RGB (0x1 << 0)
505 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
506 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
507 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
508 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
510 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
511 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
512 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
513 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
515 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
517 /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
518 #define DP_PCON_DSC_SLICE_CAP_2 0x09C
519 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
520 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
521 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
523 /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
524 #define DP_PCON_DSC_BPP_INCR 0x09E
525 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
526 # define DP_PCON_DSC_ONE_16TH_BPP 0
527 # define DP_PCON_DSC_ONE_8TH_BPP 1
528 # define DP_PCON_DSC_ONE_4TH_BPP 2
529 # define DP_PCON_DSC_ONE_HALF_BPP 3
530 # define DP_PCON_DSC_ONE_BPP 4
532 /* DP Extended DSC Capabilities */
533 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
534 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
535 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
537 /* DFP Capability Extension */
538 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
540 /* Link Configuration */
541 #define DP_LINK_BW_SET 0x100
542 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
543 # define DP_LINK_BW_1_62 0x06
544 # define DP_LINK_BW_2_7 0x0a
545 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
546 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
547 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
548 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
549 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
551 #define DP_LANE_COUNT_SET 0x101
552 # define DP_LANE_COUNT_MASK 0x0f
553 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
555 #define DP_TRAINING_PATTERN_SET 0x102
556 # define DP_TRAINING_PATTERN_DISABLE 0
557 # define DP_TRAINING_PATTERN_1 1
558 # define DP_TRAINING_PATTERN_2 2
559 # define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
560 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
561 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
562 # define DP_TRAINING_PATTERN_MASK 0x3
563 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
565 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
566 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
567 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
568 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
569 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
570 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
572 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
573 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
575 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
576 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
577 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
578 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
580 #define DP_TRAINING_LANE0_SET 0x103
581 #define DP_TRAINING_LANE1_SET 0x104
582 #define DP_TRAINING_LANE2_SET 0x105
583 #define DP_TRAINING_LANE3_SET 0x106
585 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
586 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
587 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
588 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
589 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
590 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
591 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
593 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
594 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
595 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
596 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
597 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
599 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
600 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
602 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
604 #define DP_DOWNSPREAD_CTRL 0x107
605 # define DP_SPREAD_AMP_0_5 (1 << 4)
606 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
608 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
609 # define DP_SET_ANSI_8B10B (1 << 0)
610 # define DP_SET_ANSI_128B132B (1 << 1)
612 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
613 /* bitmask as for DP_I2C_SPEED_CAP */
615 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
616 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
617 # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
618 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
620 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
621 #define DP_LINK_QUAL_LANE1_SET 0x10c
622 #define DP_LINK_QUAL_LANE2_SET 0x10d
623 #define DP_LINK_QUAL_LANE3_SET 0x10e
624 # define DP_LINK_QUAL_PATTERN_DISABLE 0
625 # define DP_LINK_QUAL_PATTERN_D10_2 1
626 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
627 # define DP_LINK_QUAL_PATTERN_PRBS7 3
628 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
629 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
630 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
631 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
632 /* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
633 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
634 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
635 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
636 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
637 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
638 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
639 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
640 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
641 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48
643 #define DP_TRAINING_LANE0_1_SET2 0x10f
644 #define DP_TRAINING_LANE2_3_SET2 0x110
645 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
646 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
647 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
648 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
650 #define DP_MSTM_CTRL 0x111 /* 1.2 */
651 # define DP_MST_EN (1 << 0)
652 # define DP_UP_REQ_EN (1 << 1)
653 # define DP_UPSTREAM_IS_SRC (1 << 2)
655 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
656 #define DP_AUDIO_DELAY1 0x113
657 #define DP_AUDIO_DELAY2 0x114
659 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
660 # define DP_LINK_RATE_SET_SHIFT 0
661 # define DP_LINK_RATE_SET_MASK (7 << 0)
663 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
664 # define DP_ALPM_ENABLE (1 << 0)
665 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
667 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
668 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
669 # define DP_IRQ_HPD_ENABLE (1 << 1)
671 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
672 # define DP_PWR_NOT_NEEDED (1 << 0)
674 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
675 # define DP_FEC_READY (1 << 0)
676 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
677 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
678 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
679 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
680 # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
681 # define DP_FEC_LANE_SELECT_MASK (3 << 4)
682 # define DP_FEC_LANE_0_SELECT (0 << 4)
683 # define DP_FEC_LANE_1_SELECT (1 << 4)
684 # define DP_FEC_LANE_2_SELECT (2 << 4)
685 # define DP_FEC_LANE_3_SELECT (3 << 4)
687 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
688 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
690 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
691 # define DP_DECOMPRESSION_EN (1 << 0)
692 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
694 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
695 # define DP_PSR_ENABLE BIT(0)
696 # define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
697 # define DP_PSR_CRC_VERIFICATION BIT(2)
698 # define DP_PSR_FRAME_CAPTURE BIT(3)
699 # define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
700 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
701 # define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
703 #define DP_ADAPTER_CTRL 0x1a0
704 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
706 #define DP_BRANCH_DEVICE_CTRL 0x1a1
707 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
709 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
710 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
711 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
713 /* Link/Sink Device Status */
714 #define DP_SINK_COUNT 0x200
715 /* prior to 1.2 bit 7 was reserved mbz */
716 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
717 # define DP_SINK_CP_READY (1 << 6)
719 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
720 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
721 # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
722 # define DP_CP_IRQ (1 << 2)
723 # define DP_MCCS_IRQ (1 << 3)
724 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
725 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
726 # define DP_SINK_SPECIFIC_IRQ (1 << 6)
728 #define DP_LANE0_1_STATUS 0x202
729 #define DP_LANE2_3_STATUS 0x203
730 # define DP_LANE_CR_DONE (1 << 0)
731 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
732 # define DP_LANE_SYMBOL_LOCKED (1 << 2)
734 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
735 DP_LANE_CHANNEL_EQ_DONE | \
736 DP_LANE_SYMBOL_LOCKED)
738 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
739 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
740 #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
741 #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
742 #define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
743 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
744 #define DP_LINK_STATUS_UPDATED (1 << 7)
746 #define DP_SINK_STATUS 0x205
747 # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
748 # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
749 # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
750 # define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
752 #define DP_ADJUST_REQUEST_LANE0_1 0x206
753 #define DP_ADJUST_REQUEST_LANE2_3 0x207
754 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
755 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
756 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
757 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
758 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
759 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
760 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
761 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
763 /* DP 2.0 128b/132b Link Layer */
764 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
765 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
766 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
767 # define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
769 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
770 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
771 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
772 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
773 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
774 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
775 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
776 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
777 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
779 #define DP_TEST_REQUEST 0x218
780 # define DP_TEST_LINK_TRAINING (1 << 0)
781 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
782 # define DP_TEST_LINK_EDID_READ (1 << 2)
783 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
784 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
785 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
786 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
788 #define DP_TEST_LINK_RATE 0x219
789 # define DP_LINK_RATE_162 (0x6)
790 # define DP_LINK_RATE_27 (0xa)
792 #define DP_TEST_LANE_COUNT 0x220
794 #define DP_TEST_PATTERN 0x221
795 # define DP_NO_TEST_PATTERN 0x0
796 # define DP_COLOR_RAMP 0x1
797 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
798 # define DP_COLOR_SQUARE 0x3
800 #define DP_TEST_H_TOTAL_HI 0x222
801 #define DP_TEST_H_TOTAL_LO 0x223
803 #define DP_TEST_V_TOTAL_HI 0x224
804 #define DP_TEST_V_TOTAL_LO 0x225
806 #define DP_TEST_H_START_HI 0x226
807 #define DP_TEST_H_START_LO 0x227
809 #define DP_TEST_V_START_HI 0x228
810 #define DP_TEST_V_START_LO 0x229
812 #define DP_TEST_HSYNC_HI 0x22A
813 # define DP_TEST_HSYNC_POLARITY (1 << 7)
814 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
815 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
817 #define DP_TEST_VSYNC_HI 0x22C
818 # define DP_TEST_VSYNC_POLARITY (1 << 7)
819 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
820 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
822 #define DP_TEST_H_WIDTH_HI 0x22E
823 #define DP_TEST_H_WIDTH_LO 0x22F
825 #define DP_TEST_V_HEIGHT_HI 0x230
826 #define DP_TEST_V_HEIGHT_LO 0x231
828 #define DP_TEST_MISC0 0x232
829 # define DP_TEST_SYNC_CLOCK (1 << 0)
830 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
831 # define DP_TEST_COLOR_FORMAT_SHIFT 1
832 # define DP_COLOR_FORMAT_RGB (0 << 1)
833 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
834 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
835 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
836 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
837 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
838 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
839 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
840 # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
841 # define DP_TEST_BIT_DEPTH_SHIFT 5
842 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
843 # define DP_TEST_BIT_DEPTH_8 (1 << 5)
844 # define DP_TEST_BIT_DEPTH_10 (2 << 5)
845 # define DP_TEST_BIT_DEPTH_12 (3 << 5)
846 # define DP_TEST_BIT_DEPTH_16 (4 << 5)
848 #define DP_TEST_MISC1 0x233
849 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
850 # define DP_TEST_INTERLACED (1 << 1)
852 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
854 #define DP_TEST_MISC0 0x232
856 #define DP_TEST_CRC_R_CR 0x240
857 #define DP_TEST_CRC_G_Y 0x242
858 #define DP_TEST_CRC_B_CB 0x244
860 #define DP_TEST_SINK_MISC 0x246
861 # define DP_TEST_CRC_SUPPORTED (1 << 5)
862 # define DP_TEST_COUNT_MASK 0xf
864 #define DP_PHY_TEST_PATTERN 0x248
865 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
866 # define DP_PHY_TEST_PATTERN_NONE 0x0
867 # define DP_PHY_TEST_PATTERN_D10_2 0x1
868 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
869 # define DP_PHY_TEST_PATTERN_PRBS7 0x3
870 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
871 # define DP_PHY_TEST_PATTERN_CP2520 0x5
873 #define DP_PHY_SQUARE_PATTERN 0x249
875 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
876 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
877 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
878 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
879 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
880 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
881 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
882 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
883 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
884 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
885 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
887 #define DP_TEST_RESPONSE 0x260
888 # define DP_TEST_ACK (1 << 0)
889 # define DP_TEST_NAK (1 << 1)
890 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
892 #define DP_TEST_EDID_CHECKSUM 0x261
894 #define DP_TEST_SINK 0x270
895 # define DP_TEST_SINK_START (1 << 0)
896 #define DP_TEST_AUDIO_MODE 0x271
897 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
898 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
899 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
900 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
901 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
902 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
903 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
904 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
905 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
907 #define DP_FEC_STATUS 0x280 /* 1.4 */
908 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
909 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
911 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
913 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
914 # define DP_FEC_ERROR_COUNT_MASK 0x7F
915 # define DP_FEC_ERR_COUNT_VALID (1 << 7)
917 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
918 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
919 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
921 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
922 /* up to ID_SLOT_63 at 0x2ff */
924 /* Source Device-specific */
925 #define DP_SOURCE_OUI 0x300
927 /* Sink Device-specific */
928 #define DP_SINK_OUI 0x400
930 /* Branch Device-specific */
931 #define DP_BRANCH_OUI 0x500
932 #define DP_BRANCH_ID 0x503
933 #define DP_BRANCH_REVISION_START 0x509
934 #define DP_BRANCH_HW_REV 0x509
935 #define DP_BRANCH_SW_REV 0x50A
937 /* Link/Sink Device Power Control */
938 #define DP_SET_POWER 0x600
939 # define DP_SET_POWER_D0 0x1
940 # define DP_SET_POWER_D3 0x2
941 # define DP_SET_POWER_MASK 0x3
942 # define DP_SET_POWER_D3_AUX_ON 0x5
945 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
946 # define DP_EDP_11 0x00
947 # define DP_EDP_12 0x01
948 # define DP_EDP_13 0x02
949 # define DP_EDP_14 0x03
950 # define DP_EDP_14a 0x04 /* eDP 1.4a */
951 # define DP_EDP_14b 0x05 /* eDP 1.4b */
953 #define DP_EDP_GENERAL_CAP_1 0x701
954 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
955 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
956 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
957 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
958 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
959 # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
960 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
961 # define DP_EDP_SET_POWER_CAP (1 << 7)
963 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
964 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
965 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
966 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
967 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
968 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
969 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
970 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
971 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
973 #define DP_EDP_GENERAL_CAP_2 0x703
974 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
976 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
977 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
978 # define DP_EDP_X_REGION_CAP_SHIFT 0
979 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
980 # define DP_EDP_Y_REGION_CAP_SHIFT 4
982 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
983 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
984 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
985 # define DP_EDP_FRC_ENABLE (1 << 2)
986 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
987 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
989 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
990 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
991 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
992 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
993 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
994 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
995 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
996 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
997 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
998 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
999 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
1001 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1002 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1004 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
1005 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1006 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1007 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1009 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1011 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1012 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1014 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1015 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1016 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1018 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1019 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1020 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1022 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1023 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1025 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1026 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1028 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1029 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1030 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1031 # define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1033 /* Sideband MSG Buffers */
1034 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1035 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1036 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1037 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1039 /* DPRX Event Status Indicator */
1040 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1041 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1043 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1044 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1045 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1046 # define DP_CEC_IRQ (1 << 2)
1048 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1049 # define RX_CAP_CHANGED (1 << 0)
1050 # define LINK_STATUS_CHANGED (1 << 1)
1051 # define STREAM_STATUS_CHANGED (1 << 2)
1052 # define HDMI_LINK_STATUS_CHANGED (1 << 3)
1053 # define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1055 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1056 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
1057 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1058 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1060 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1061 # define DP_PSR_CAPS_CHANGE (1 << 0)
1063 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1064 # define DP_PSR_SINK_INACTIVE 0
1065 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1066 # define DP_PSR_SINK_ACTIVE_RFB 2
1067 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1068 # define DP_PSR_SINK_ACTIVE_RESYNC 4
1069 # define DP_PSR_SINK_INTERNAL_ERROR 7
1070 # define DP_PSR_SINK_STATE_MASK 0x07
1072 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1073 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1074 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1075 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1076 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1078 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1079 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1080 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
1081 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
1082 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
1083 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
1084 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
1085 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
1087 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1088 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1090 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1091 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1092 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1093 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1095 /* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1096 #define DP_DP13_DPCD_REV 0x2200
1098 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1099 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1100 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
1101 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
1102 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
1103 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
1104 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
1105 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
1106 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
1108 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1109 # define DP_UHBR10 (1 << 0)
1110 # define DP_UHBR20 (1 << 1)
1111 # define DP_UHBR13_5 (1 << 2)
1113 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1114 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
1115 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1116 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1117 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1118 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1119 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1120 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1121 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1122 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1124 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1125 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1127 /* DSC Extended Capability Branch Total DSC Resources */
1128 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1129 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1130 # define DP_DSC_DECODER_COUNT_SHIFT 5
1131 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1132 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1133 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1134 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
1136 /* Protocol Converter Extension */
1137 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1138 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
1139 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1140 # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1141 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1143 #define DP_CEC_TUNNELING_CONTROL 0x3001
1144 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
1145 # define DP_CEC_SNOOPING_ENABLE (1 << 1)
1147 #define DP_CEC_RX_MESSAGE_INFO 0x3002
1148 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1149 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1150 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1151 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1152 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1153 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1155 #define DP_CEC_TX_MESSAGE_INFO 0x3003
1156 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1157 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1158 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1159 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1160 # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1162 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1163 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1164 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1165 # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1166 # define DP_CEC_TX_LINE_ERROR (1 << 5)
1167 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1168 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1170 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1171 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1172 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1173 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1174 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1175 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1176 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1177 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1178 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1179 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1180 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1181 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1182 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1183 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1184 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1185 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1186 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1187 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1189 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1190 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1191 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1193 /* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1194 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1195 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1196 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1197 # define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1198 # define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1199 # define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1200 # define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1201 # define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1202 # define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1203 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1204 # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1205 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1206 # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1207 # define DP_PCON_ENABLE_HPD_READY (1 << 6)
1208 # define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1210 /* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1211 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1212 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1213 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1214 # define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1215 # define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1216 # define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1217 # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1218 # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1219 # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1220 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1222 /* PCON HDMI LINK STATUS */
1223 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1224 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1225 # define DP_PCON_FRL_READY (1 << 1)
1227 /* PCON HDMI POST FRL STATUS */
1228 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1229 # define DP_PCON_HDMI_LINK_MODE (1 << 0)
1230 # define DP_PCON_HDMI_MODE_TMDS 0
1231 # define DP_PCON_HDMI_MODE_FRL 1
1232 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1233 # define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1234 # define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1235 # define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1236 # define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1237 # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1238 # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1240 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1241 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1242 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1243 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1244 # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
1245 # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
1246 # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
1247 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1248 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1249 # define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1250 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1251 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1252 # define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1253 # define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1254 # define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1255 # define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1256 # define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1257 # define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1259 /* PCON Downstream HDMI ERROR Status per Lane */
1260 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1261 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1262 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1263 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1264 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1265 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1266 # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1267 # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1269 /* PCON HDMI CONFIG PPS Override Buffer
1270 * Valid Offsets to be added to Base : 0-127
1272 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1274 /* PCON HDMI CONFIG PPS Override Parameter: Slice height
1275 * Offset-0 8LSBs of the Slice height.
1276 * Offset-1 8MSBs of the Slice height.
1278 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1280 /* PCON HDMI CONFIG PPS Override Parameter: Slice width
1281 * Offset-0 8LSBs of the Slice width.
1282 * Offset-1 8MSBs of the Slice width.
1284 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1286 /* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1287 * Offset-0 8LSBs of the bits_per_pixel.
1288 * Offset-1 2MSBs of the bits_per_pixel.
1290 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1292 /* HDCP 1.3 and HDCP 2.2 */
1293 #define DP_AUX_HDCP_BKSV 0x68000
1294 #define DP_AUX_HDCP_RI_PRIME 0x68005
1295 #define DP_AUX_HDCP_AKSV 0x68007
1296 #define DP_AUX_HDCP_AN 0x6800C
1297 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1298 #define DP_AUX_HDCP_BCAPS 0x68028
1299 # define DP_BCAPS_REPEATER_PRESENT BIT(1)
1300 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
1301 #define DP_AUX_HDCP_BSTATUS 0x68029
1302 # define DP_BSTATUS_REAUTH_REQ BIT(3)
1303 # define DP_BSTATUS_LINK_FAILURE BIT(2)
1304 # define DP_BSTATUS_R0_PRIME_READY BIT(1)
1305 # define DP_BSTATUS_READY BIT(0)
1306 #define DP_AUX_HDCP_BINFO 0x6802A
1307 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
1308 #define DP_AUX_HDCP_AINFO 0x6803B
1310 /* DP HDCP2.2 parameter offsets in DPCD address space */
1311 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1312 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1313 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1314 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1315 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1316 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1317 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1318 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1319 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1320 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1321 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1322 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1323 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1324 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1325 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1326 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1327 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1328 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1329 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1330 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1331 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1332 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1333 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1334 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1335 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1336 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1338 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1339 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1340 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1341 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1342 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1343 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1344 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1345 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1346 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1347 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1348 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
1349 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1350 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1364 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1367 #define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1369 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1370 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1371 #define DP_LTTPR_BASE(dp_phy) \
1372 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1373 ((dp_phy) - DP_PHY_LTTPR1))
1375 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1376 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1378 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1379 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1380 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1382 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1383 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1384 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1386 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1387 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1388 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1389 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1390 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1391 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1393 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1394 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1395 # define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1397 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1398 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1399 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1400 /* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */
1402 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1403 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1404 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1406 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1408 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1409 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1410 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1411 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1412 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1413 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1414 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1416 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1417 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1418 #define DP_FEC_BASE(dp_phy) \
1419 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1420 ((dp_phy) - DP_PHY_LTTPR1)))
1422 #define DP_FEC_REG(dp_phy, fec1_reg) \
1423 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1425 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1426 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1427 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1429 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1430 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1432 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1434 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1436 /* Repeater modes */
1437 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1438 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1440 /* DP HDCP message start offsets in DPCD address space */
1441 #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1442 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1443 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1444 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1445 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1446 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1447 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1448 #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1449 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1450 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1451 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1452 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1453 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1454 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1456 #define HDCP_2_2_DP_RXSTATUS_LEN 1
1457 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1458 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1459 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1460 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1461 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1463 /* DP 1.2 Sideband message defines */
1464 /* peer device type - DP 1.2a Table 2-92 */
1465 #define DP_PEER_DEVICE_NONE 0x0
1466 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1467 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1468 #define DP_PEER_DEVICE_SST_SINK 0x3
1469 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1471 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1472 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1473 #define DP_LINK_ADDRESS 0x01
1474 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1475 #define DP_ENUM_PATH_RESOURCES 0x10
1476 #define DP_ALLOCATE_PAYLOAD 0x11
1477 #define DP_QUERY_PAYLOAD 0x12
1478 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1479 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1480 #define DP_REMOTE_DPCD_READ 0x20
1481 #define DP_REMOTE_DPCD_WRITE 0x21
1482 #define DP_REMOTE_I2C_READ 0x22
1483 #define DP_REMOTE_I2C_WRITE 0x23
1484 #define DP_POWER_UP_PHY 0x24
1485 #define DP_POWER_DOWN_PHY 0x25
1486 #define DP_SINK_EVENT_NOTIFY 0x30
1487 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1488 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1489 #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1490 #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1492 /* DP 1.2 MST sideband reply types */
1493 #define DP_SIDEBAND_REPLY_ACK 0x00
1494 #define DP_SIDEBAND_REPLY_NAK 0x01
1496 /* DP 1.2 MST sideband nak reasons - table 2.84 */
1497 #define DP_NAK_WRITE_FAILURE 0x01
1498 #define DP_NAK_INVALID_READ 0x02
1499 #define DP_NAK_CRC_FAILURE 0x03
1500 #define DP_NAK_BAD_PARAM 0x04
1501 #define DP_NAK_DEFER 0x05
1502 #define DP_NAK_LINK_FAILURE 0x06
1503 #define DP_NAK_NO_RESOURCES 0x07
1504 #define DP_NAK_DPCD_FAIL 0x08
1505 #define DP_NAK_I2C_NAK 0x09
1506 #define DP_NAK_ALLOCATE_FAIL 0x0a
1508 #define MODE_I2C_START 1
1509 #define MODE_I2C_WRITE 2
1510 #define MODE_I2C_READ 4
1511 #define MODE_I2C_STOP 8
1513 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1514 #define DP_MST_PHYSICAL_PORT_0 0
1515 #define DP_MST_LOGICAL_PORT_0 8
1517 #define DP_LINK_CONSTANT_N_VALUE 0x8000
1518 #define DP_LINK_STATUS_SIZE 6
1520 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1521 #define DP_RECEIVER_CAP_SIZE 0xf
1522 #define DP_DSC_RECEIVER_CAP_SIZE 0xf
1523 #define EDP_PSR_RECEIVER_CAP_SIZE 2
1524 #define EDP_DISPLAY_CTL_CAP_SIZE 3
1525 #define DP_LTTPR_COMMON_CAP_SIZE 8
1526 #define DP_LTTPR_PHY_CAP_SIZE 3
1528 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1529 #define DP_SDP_AUDIO_STREAM 0x02
1530 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1531 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1532 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1533 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1534 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1535 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1536 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1537 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1538 /* 0x80+ CEA-861 infoframe types */
1540 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
1543 * struct dp_sdp_header - DP secondary data packet header
1544 * @HB0: Secondary Data Packet ID
1545 * @HB1: Secondary Data Packet Type
1546 * @HB2: Secondary Data Packet Specific header, Byte 0
1547 * @HB3: Secondary Data packet Specific header, Byte 1
1549 struct dp_sdp_header {
1556 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1557 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1558 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1561 * struct dp_sdp - DP secondary data packet
1562 * @sdp_header: DP secondary data packet header
1563 * @db: DP secondaray data packet data blocks
1564 * VSC SDP Payload for PSR
1565 * db[0]: Stereo Interface
1566 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1567 * db[2]: CRC value bits 7:0 of the R or Cr component
1568 * db[3]: CRC value bits 15:8 of the R or Cr component
1569 * db[4]: CRC value bits 7:0 of the G or Y component
1570 * db[5]: CRC value bits 15:8 of the G or Y component
1571 * db[6]: CRC value bits 7:0 of the B or Cb component
1572 * db[7]: CRC value bits 15:8 of the B or Cb component
1573 * db[8] - db[31]: Reserved
1574 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1575 * db[0] - db[15]: Reserved
1576 * db[16]: Pixel Encoding and Colorimetry Formats
1577 * db[17]: Dynamic Range and Component Bit Depth
1578 * db[18]: Content Type
1579 * db[19] - db[31]: Reserved
1582 struct dp_sdp_header sdp_header;
1586 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1587 #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1588 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1591 * enum dp_pixelformat - drm DP Pixel encoding formats
1593 * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1594 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1597 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1598 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1599 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1600 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1601 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1602 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1603 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1605 enum dp_pixelformat {
1606 DP_PIXELFORMAT_RGB = 0,
1607 DP_PIXELFORMAT_YUV444 = 0x1,
1608 DP_PIXELFORMAT_YUV422 = 0x2,
1609 DP_PIXELFORMAT_YUV420 = 0x3,
1610 DP_PIXELFORMAT_Y_ONLY = 0x4,
1611 DP_PIXELFORMAT_RAW = 0x5,
1612 DP_PIXELFORMAT_RESERVED = 0x6,
1616 * enum dp_colorimetry - drm DP Colorimetry formats
1618 * This enum is used to indicate DP VSC SDP Colorimetry formats.
1619 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1620 * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1622 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1623 * ITU-R BT.601 colorimetry format
1624 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1625 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1626 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1627 * (scRGB (IEC 61966-2-2)) colorimetry format
1628 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1629 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1630 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1631 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1632 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1633 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1634 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1635 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1636 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1637 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1639 enum dp_colorimetry {
1640 DP_COLORIMETRY_DEFAULT = 0,
1641 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1642 DP_COLORIMETRY_BT709_YCC = 0x1,
1643 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1644 DP_COLORIMETRY_XVYCC_601 = 0x2,
1645 DP_COLORIMETRY_OPRGB = 0x3,
1646 DP_COLORIMETRY_XVYCC_709 = 0x3,
1647 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1648 DP_COLORIMETRY_SYCC_601 = 0x4,
1649 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1650 DP_COLORIMETRY_OPYCC_601 = 0x5,
1651 DP_COLORIMETRY_BT2020_RGB = 0x6,
1652 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1653 DP_COLORIMETRY_BT2020_YCC = 0x7,
1657 * enum dp_dynamic_range - drm DP Dynamic Range
1659 * This enum is used to indicate DP VSC SDP Dynamic Range.
1660 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1663 * @DP_DYNAMIC_RANGE_VESA: VESA range
1664 * @DP_DYNAMIC_RANGE_CTA: CTA range
1666 enum dp_dynamic_range {
1667 DP_DYNAMIC_RANGE_VESA = 0,
1668 DP_DYNAMIC_RANGE_CTA = 1,
1672 * enum dp_content_type - drm DP Content Type
1674 * This enum is used to indicate DP VSC SDP Content Types.
1675 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1677 * CTA-861-G defines content types and expected processing by a sink device
1679 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1680 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1681 * @DP_CONTENT_TYPE_PHOTO: Photo type
1682 * @DP_CONTENT_TYPE_VIDEO: Video type
1683 * @DP_CONTENT_TYPE_GAME: Game type
1685 enum dp_content_type {
1686 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1687 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1688 DP_CONTENT_TYPE_PHOTO = 0x02,
1689 DP_CONTENT_TYPE_VIDEO = 0x03,
1690 DP_CONTENT_TYPE_GAME = 0x04,
1693 #endif /* _DRM_DP_H_ */
git.samba.org / sfrench / cifs-2.6.git / blob