drivers/xen/xen-pciback/conf_space_header.c

   1 /*
   2  * PCI Backend - Handles the virtual fields in the configuration space headers.
   3  *
   4  * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include "pciback.h"
  12 #include "conf_space.h"
  13
  14 struct pci_cmd_info {
  15         u16 val;
  16 };
  17
  18 struct pci_bar_info {
  19         u32 val;
  20         u32 len_val;
  21         int which;
  22 };
  23
  24 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
  25 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
  26
  27 /* Bits guests are allowed to control in permissive mode. */
  28 #define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
  29                            PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
  30                            PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)
  31
  32 static void *command_init(struct pci_dev *dev, int offset)
  33 {
  34         struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  35         int err;
  36
  37         if (!cmd)
  38                 return ERR_PTR(-ENOMEM);
  39
  40         err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
  41         if (err) {
  42                 kfree(cmd);
  43                 return ERR_PTR(err);
  44         }
  45
  46         return cmd;
  47 }
  48
  49 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
  50 {
  51         int ret = pci_read_config_word(dev, offset, value);
  52         const struct pci_cmd_info *cmd = data;
  53
  54         *value &= PCI_COMMAND_GUEST;
  55         *value |= cmd->val & ~PCI_COMMAND_GUEST;
  56
  57         return ret;
  58 }
  59
  60 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
  61 {
  62         struct xen_pcibk_dev_data *dev_data;
  63         int err;
  64         u16 val;
  65         struct pci_cmd_info *cmd = data;
  66
  67         dev_data = pci_get_drvdata(dev);
  68         if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
  69                 if (unlikely(verbose_request))
  70                         printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
  71                                pci_name(dev));
  72                 err = pci_enable_device(dev);
  73                 if (err)
  74                         return err;
  75                 if (dev_data)
  76                         dev_data->enable_intx = 1;
  77         } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
  78                 if (unlikely(verbose_request))
  79                         printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
  80                                pci_name(dev));
  81                 pci_disable_device(dev);
  82                 if (dev_data)
  83                         dev_data->enable_intx = 0;
  84         }
  85
  86         if (!dev->is_busmaster && is_master_cmd(value)) {
  87                 if (unlikely(verbose_request))
  88                         printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
  89                                pci_name(dev));
  90                 pci_set_master(dev);
  91         } else if (dev->is_busmaster && !is_master_cmd(value)) {
  92                 if (unlikely(verbose_request))
  93                         printk(KERN_DEBUG DRV_NAME ": %s: clear bus master\n",
  94                                pci_name(dev));
  95                 pci_clear_master(dev);
  96         }
  97
  98         if (!(cmd->val & PCI_COMMAND_INVALIDATE) &&
  99             (value & PCI_COMMAND_INVALIDATE)) {
 100                 if (unlikely(verbose_request))
 101                         printk(KERN_DEBUG
 102                                DRV_NAME ": %s: enable memory-write-invalidate\n",
 103                                pci_name(dev));
 104                 err = pci_set_mwi(dev);
 105                 if (err) {
 106                         pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
 107                                 pci_name(dev), err);
 108                         value &= ~PCI_COMMAND_INVALIDATE;
 109                 }
 110         } else if ((cmd->val & PCI_COMMAND_INVALIDATE) &&
 111                    !(value & PCI_COMMAND_INVALIDATE)) {
 112                 if (unlikely(verbose_request))
 113                         printk(KERN_DEBUG
 114                                DRV_NAME ": %s: disable memory-write-invalidate\n",
 115                                pci_name(dev));
 116                 pci_clear_mwi(dev);
 117         }
 118
 119         cmd->val = value;
 120
 121         if (!xen_pcibk_permissive && (!dev_data || !dev_data->permissive))
 122                 return 0;
 123
 124         /* Only allow the guest to control certain bits. */
 125         err = pci_read_config_word(dev, offset, &val);
 126         if (err || val == value)
 127                 return err;
 128
 129         value &= PCI_COMMAND_GUEST;
 130         value |= val & ~PCI_COMMAND_GUEST;
 131
 132         return pci_write_config_word(dev, offset, value);
 133 }
 134
 135 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
 136 {
 137         struct pci_bar_info *bar = data;
 138
 139         if (unlikely(!bar)) {
 140                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 141                        pci_name(dev));
 142                 return XEN_PCI_ERR_op_failed;
 143         }
 144
 145         /* A write to obtain the length must happen as a 32-bit write.
 146          * This does not (yet) support writing individual bytes
 147          */
 148         if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0U)
 149                 bar->which = 1;
 150         else {
 151                 u32 tmpval;
 152                 pci_read_config_dword(dev, offset, &tmpval);
 153                 if (tmpval != bar->val && value == bar->val) {
 154                         /* Allow restoration of bar value. */
 155                         pci_write_config_dword(dev, offset, bar->val);
 156                 }
 157                 bar->which = 0;
 158         }
 159
 160         /* Do we need to support enabling/disabling the rom address here? */
 161
 162         return 0;
 163 }
 164
 165 /* For the BARs, only allow writes which write ~0 or
 166  * the correct resource information
 167  * (Needed for when the driver probes the resource usage)
 168  */
 169 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
 170 {
 171         struct pci_bar_info *bar = data;
 172         unsigned int pos = (offset - PCI_BASE_ADDRESS_0) / 4;
 173         const struct resource *res = dev->resource;
 174         u32 mask;
 175
 176         if (unlikely(!bar)) {
 177                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 178                        pci_name(dev));
 179                 return XEN_PCI_ERR_op_failed;
 180         }
 181
 182         /* A write to obtain the length must happen as a 32-bit write.
 183          * This does not (yet) support writing individual bytes
 184          */
 185         if (res[pos].flags & IORESOURCE_IO)
 186                 mask = ~PCI_BASE_ADDRESS_IO_MASK;
 187         else if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64))
 188                 mask = 0;
 189         else
 190                 mask = ~PCI_BASE_ADDRESS_MEM_MASK;
 191         if ((value | mask) == ~0U)
 192                 bar->which = 1;
 193         else {
 194                 u32 tmpval;
 195                 pci_read_config_dword(dev, offset, &tmpval);
 196                 if (tmpval != bar->val && value == bar->val) {
 197                         /* Allow restoration of bar value. */
 198                         pci_write_config_dword(dev, offset, bar->val);
 199                 }
 200                 bar->which = 0;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
 207 {
 208         struct pci_bar_info *bar = data;
 209
 210         if (unlikely(!bar)) {
 211                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 212                        pci_name(dev));
 213                 return XEN_PCI_ERR_op_failed;
 214         }
 215
 216         *value = bar->which ? bar->len_val : bar->val;
 217
 218         return 0;
 219 }
 220
 221 static void *bar_init(struct pci_dev *dev, int offset)
 222 {
 223         unsigned int pos;
 224         const struct resource *res = dev->resource;
 225         struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
 226
 227         if (!bar)
 228                 return ERR_PTR(-ENOMEM);
 229
 230         if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
 231                 pos = PCI_ROM_RESOURCE;
 232         else {
 233                 pos = (offset - PCI_BASE_ADDRESS_0) / 4;
 234                 if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64)) {
 235                         bar->val = res[pos - 1].start >> 32;
 236                         bar->len_val = -resource_size(&res[pos - 1]) >> 32;
 237                         return bar;
 238                 }
 239         }
 240
 241         if (!res[pos].flags ||
 242             (res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
 243                                IORESOURCE_BUSY)))
 244                 return bar;
 245
 246         bar->val = res[pos].start |
 247                    (res[pos].flags & PCI_REGION_FLAG_MASK);
 248         bar->len_val = -resource_size(&res[pos]) |
 249                        (res[pos].flags & PCI_REGION_FLAG_MASK);
 250
 251         return bar;
 252 }
 253
 254 static void bar_reset(struct pci_dev *dev, int offset, void *data)
 255 {
 256         struct pci_bar_info *bar = data;
 257
 258         bar->which = 0;
 259 }
 260
 261 static void bar_release(struct pci_dev *dev, int offset, void *data)
 262 {
 263         kfree(data);
 264 }
 265
 266 static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
 267                                u16 *value, void *data)
 268 {
 269         *value = dev->vendor;
 270
 271         return 0;
 272 }
 273
 274 static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
 275                                u16 *value, void *data)
 276 {
 277         *value = dev->device;
 278
 279         return 0;
 280 }
 281
 282 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
 283                           void *data)
 284 {
 285         *value = (u8) dev->irq;
 286
 287         return 0;
 288 }
 289
 290 static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
 291 {
 292         u8 cur_value;
 293         int err;
 294
 295         err = pci_read_config_byte(dev, offset, &cur_value);
 296         if (err)
 297                 goto out;
 298
 299         if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
 300             || value == PCI_BIST_START)
 301                 err = pci_write_config_byte(dev, offset, value);
 302
 303 out:
 304         return err;
 305 }
 306
 307 static const struct config_field header_common[] = {
 308         {
 309          .offset    = PCI_VENDOR_ID,
 310          .size      = 2,
 311          .u.w.read  = xen_pcibk_read_vendor,
 312         },
 313         {
 314          .offset    = PCI_DEVICE_ID,
 315          .size      = 2,
 316          .u.w.read  = xen_pcibk_read_device,
 317         },
 318         {
 319          .offset    = PCI_COMMAND,
 320          .size      = 2,
 321          .init      = command_init,
 322          .release   = bar_release,
 323          .u.w.read  = command_read,
 324          .u.w.write = command_write,
 325         },
 326         {
 327          .offset    = PCI_INTERRUPT_LINE,
 328          .size      = 1,
 329          .u.b.read  = interrupt_read,
 330         },
 331         {
 332          .offset    = PCI_INTERRUPT_PIN,
 333          .size      = 1,
 334          .u.b.read  = xen_pcibk_read_config_byte,
 335         },
 336         {
 337          /* Any side effects of letting driver domain control cache line? */
 338          .offset    = PCI_CACHE_LINE_SIZE,
 339          .size      = 1,
 340          .u.b.read  = xen_pcibk_read_config_byte,
 341          .u.b.write = xen_pcibk_write_config_byte,
 342         },
 343         {
 344          .offset    = PCI_LATENCY_TIMER,
 345          .size      = 1,
 346          .u.b.read  = xen_pcibk_read_config_byte,
 347         },
 348         {
 349          .offset    = PCI_BIST,
 350          .size      = 1,
 351          .u.b.read  = xen_pcibk_read_config_byte,
 352          .u.b.write = bist_write,
 353         },
 354         {}
 355 };
 356
 357 #define CFG_FIELD_BAR(reg_offset)                       \
 358         {                                               \
 359         .offset     = reg_offset,                       \
 360         .size       = 4,                                \
 361         .init       = bar_init,                         \
 362         .reset      = bar_reset,                        \
 363         .release    = bar_release,                      \
 364         .u.dw.read  = bar_read,                         \
 365         .u.dw.write = bar_write,                        \
 366         }
 367
 368 #define CFG_FIELD_ROM(reg_offset)                       \
 369         {                                               \
 370         .offset     = reg_offset,                       \
 371         .size       = 4,                                \
 372         .init       = bar_init,                         \
 373         .reset      = bar_reset,                        \
 374         .release    = bar_release,                      \
 375         .u.dw.read  = bar_read,                         \
 376         .u.dw.write = rom_write,                        \
 377         }
 378
 379 static const struct config_field header_0[] = {
 380         CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
 381         CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
 382         CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
 383         CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
 384         CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
 385         CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
 386         CFG_FIELD_ROM(PCI_ROM_ADDRESS),
 387         {}
 388 };
 389
 390 static const struct config_field header_1[] = {
 391         CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
 392         CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
 393         CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
 394         {}
 395 };
 396
 397 int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
 398 {
 399         int err;
 400
 401         err = xen_pcibk_config_add_fields(dev, header_common);
 402         if (err)
 403                 goto out;
 404
 405         switch (dev->hdr_type) {
 406         case PCI_HEADER_TYPE_NORMAL:
 407                 err = xen_pcibk_config_add_fields(dev, header_0);
 408                 break;
 409
 410         case PCI_HEADER_TYPE_BRIDGE:
 411                 err = xen_pcibk_config_add_fields(dev, header_1);
 412                 break;
 413
 414         default:
 415                 err = -EINVAL;
 416                 pr_err("%s: Unsupported header type %d!\n",
 417                        pci_name(dev), dev->hdr_type);
 418                 break;
 419         }
 420
 421 out:
 422         return err;
 423 }