drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
   5 #define __DISABLE_TRACE_MMIO__
   6
   7 #include <linux/clk.h>
   8 #include <linux/console.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/irq.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/qcom-geni-se.h>
  20 #include <linux/serial.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/slab.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25
  26 /* UART specific GENI registers */
  27 #define SE_UART_LOOPBACK_CFG            0x22c
  28 #define SE_UART_IO_MACRO_CTRL           0x240
  29 #define SE_UART_TX_TRANS_CFG            0x25c
  30 #define SE_UART_TX_WORD_LEN             0x268
  31 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  32 #define SE_UART_TX_TRANS_LEN            0x270
  33 #define SE_UART_RX_TRANS_CFG            0x280
  34 #define SE_UART_RX_WORD_LEN             0x28c
  35 #define SE_UART_RX_STALE_CNT            0x294
  36 #define SE_UART_TX_PARITY_CFG           0x2a4
  37 #define SE_UART_RX_PARITY_CFG           0x2a8
  38 #define SE_UART_MANUAL_RFR              0x2ac
  39
  40 /* SE_UART_TRANS_CFG */
  41 #define UART_TX_PAR_EN          BIT(0)
  42 #define UART_CTS_MASK           BIT(1)
  43
  44 /* SE_UART_TX_WORD_LEN */
  45 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  46
  47 /* SE_UART_TX_STOP_BIT_LEN */
  48 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  49 #define TX_STOP_BIT_LEN_1       0
  50 #define TX_STOP_BIT_LEN_1_5     1
  51 #define TX_STOP_BIT_LEN_2       2
  52
  53 /* SE_UART_TX_TRANS_LEN */
  54 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  55
  56 /* SE_UART_RX_TRANS_CFG */
  57 #define UART_RX_INS_STATUS_BIT  BIT(2)
  58 #define UART_RX_PAR_EN          BIT(3)
  59
  60 /* SE_UART_RX_WORD_LEN */
  61 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  62
  63 /* SE_UART_RX_STALE_CNT */
  64 #define RX_STALE_CNT            GENMASK(23, 0)
  65
  66 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  67 #define PAR_CALC_EN             BIT(0)
  68 #define PAR_MODE_MSK            GENMASK(2, 1)
  69 #define PAR_MODE_SHFT           1
  70 #define PAR_EVEN                0x00
  71 #define PAR_ODD                 0x01
  72 #define PAR_SPACE               0x10
  73 #define PAR_MARK                0x11
  74
  75 /* SE_UART_MANUAL_RFR register fields */
  76 #define UART_MANUAL_RFR_EN      BIT(31)
  77 #define UART_RFR_NOT_READY      BIT(1)
  78 #define UART_RFR_READY          BIT(0)
  79
  80 /* UART M_CMD OP codes */
  81 #define UART_START_TX           0x1
  82 #define UART_START_BREAK        0x4
  83 #define UART_STOP_BREAK         0x5
  84 /* UART S_CMD OP codes */
  85 #define UART_START_READ         0x1
  86 #define UART_PARAM              0x1
  87
  88 #define UART_OVERSAMPLING       32
  89 #define STALE_TIMEOUT           16
  90 #define DEFAULT_BITS_PER_CHAR   10
  91 #define GENI_UART_CONS_PORTS    1
  92 #define GENI_UART_PORTS         3
  93 #define DEF_FIFO_DEPTH_WORDS    16
  94 #define DEF_TX_WM               2
  95 #define DEF_FIFO_WIDTH_BITS     32
  96 #define UART_RX_WM              2
  97
  98 /* SE_UART_LOOPBACK_CFG */
  99 #define RX_TX_SORTED    BIT(0)
 100 #define CTS_RTS_SORTED  BIT(1)
 101 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
 102
 103 /* UART pin swap value */
 104 #define DEFAULT_IO_MACRO_IO0_IO1_MASK           GENMASK(3, 0)
 105 #define IO_MACRO_IO0_SEL                0x3
 106 #define DEFAULT_IO_MACRO_IO2_IO3_MASK           GENMASK(15, 4)
 107 #define IO_MACRO_IO2_IO3_SWAP           0x4640
 108
 109 /* We always configure 4 bytes per FIFO word */
 110 #define BYTES_PER_FIFO_WORD             4
 111
 112 struct qcom_geni_private_data {
 113         /* NOTE: earlycon port will have NULL here */
 114         struct uart_driver *drv;
 115
 116         u32 poll_cached_bytes;
 117         unsigned int poll_cached_bytes_cnt;
 118
 119         u32 write_cached_bytes;
 120         unsigned int write_cached_bytes_cnt;
 121 };
 122
 123 struct qcom_geni_serial_port {
 124         struct uart_port uport;
 125         struct geni_se se;
 126         const char *name;
 127         u32 tx_fifo_depth;
 128         u32 tx_fifo_width;
 129         u32 rx_fifo_depth;
 130         bool setup;
 131         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 132         unsigned int baud;
 133         void *rx_fifo;
 134         u32 loopback;
 135         bool brk;
 136
 137         unsigned int tx_remaining;
 138         int wakeup_irq;
 139         bool rx_tx_swap;
 140         bool cts_rts_swap;
 141
 142         struct qcom_geni_private_data private_data;
 143 };
 144
 145 static const struct uart_ops qcom_geni_console_pops;
 146 static const struct uart_ops qcom_geni_uart_pops;
 147 static struct uart_driver qcom_geni_console_driver;
 148 static struct uart_driver qcom_geni_uart_driver;
 149 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 150 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 151 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 152 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 153 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 154
 155 #define to_dev_port(ptr, member) \
 156                 container_of(ptr, struct qcom_geni_serial_port, member)
 157
 158 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 159         [0] = {
 160                 .uport = {
 161                                 .iotype = UPIO_MEM,
 162                                 .ops = &qcom_geni_uart_pops,
 163                                 .flags = UPF_BOOT_AUTOCONF,
 164                                 .line = 0,
 165                 },
 166         },
 167         [1] = {
 168                 .uport = {
 169                                 .iotype = UPIO_MEM,
 170                                 .ops = &qcom_geni_uart_pops,
 171                                 .flags = UPF_BOOT_AUTOCONF,
 172                                 .line = 1,
 173                 },
 174         },
 175         [2] = {
 176                 .uport = {
 177                                 .iotype = UPIO_MEM,
 178                                 .ops = &qcom_geni_uart_pops,
 179                                 .flags = UPF_BOOT_AUTOCONF,
 180                                 .line = 2,
 181                 },
 182         },
 183 };
 184
 185 static struct qcom_geni_serial_port qcom_geni_console_port = {
 186         .uport = {
 187                 .iotype = UPIO_MEM,
 188                 .ops = &qcom_geni_console_pops,
 189                 .flags = UPF_BOOT_AUTOCONF,
 190                 .line = 0,
 191         },
 192 };
 193
 194 static int qcom_geni_serial_request_port(struct uart_port *uport)
 195 {
 196         struct platform_device *pdev = to_platform_device(uport->dev);
 197         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 198
 199         uport->membase = devm_platform_ioremap_resource(pdev, 0);
 200         if (IS_ERR(uport->membase))
 201                 return PTR_ERR(uport->membase);
 202         port->se.base = uport->membase;
 203         return 0;
 204 }
 205
 206 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 207 {
 208         if (cfg_flags & UART_CONFIG_TYPE) {
 209                 uport->type = PORT_MSM;
 210                 qcom_geni_serial_request_port(uport);
 211         }
 212 }
 213
 214 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 215 {
 216         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 217         u32 geni_ios;
 218
 219         if (uart_console(uport)) {
 220                 mctrl |= TIOCM_CTS;
 221         } else {
 222                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 223                 if (!(geni_ios & IO2_DATA_IN))
 224                         mctrl |= TIOCM_CTS;
 225         }
 226
 227         return mctrl;
 228 }
 229
 230 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 231                                                         unsigned int mctrl)
 232 {
 233         u32 uart_manual_rfr = 0;
 234         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 235
 236         if (uart_console(uport))
 237                 return;
 238
 239         if (mctrl & TIOCM_LOOP)
 240                 port->loopback = RX_TX_CTS_RTS_SORTED;
 241
 242         if (!(mctrl & TIOCM_RTS) && !uport->suspended)
 243                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 244         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 245 }
 246
 247 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 248 {
 249         return "MSM";
 250 }
 251
 252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 253 {
 254         struct qcom_geni_serial_port *port;
 255         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 256
 257         if (line < 0 || line >= nr_ports)
 258                 return ERR_PTR(-ENXIO);
 259
 260         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 261         return port;
 262 }
 263
 264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 265                                 int offset, int field, bool set)
 266 {
 267         u32 reg;
 268         struct qcom_geni_serial_port *port;
 269         unsigned int baud;
 270         unsigned int fifo_bits;
 271         unsigned long timeout_us = 20000;
 272         struct qcom_geni_private_data *private_data = uport->private_data;
 273
 274         if (private_data->drv) {
 275                 port = to_dev_port(uport, uport);
 276                 baud = port->baud;
 277                 if (!baud)
 278                         baud = 115200;
 279                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 280                 /*
 281                  * Total polling iterations based on FIFO worth of bytes to be
 282                  * sent at current baud. Add a little fluff to the wait.
 283                  */
 284                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 285         }
 286
 287         /*
 288          * Use custom implementation instead of readl_poll_atomic since ktimer
 289          * is not ready at the time of early console.
 290          */
 291         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 292         while (timeout_us) {
 293                 reg = readl(uport->membase + offset);
 294                 if ((bool)(reg & field) == set)
 295                         return true;
 296                 udelay(10);
 297                 timeout_us -= 10;
 298         }
 299         return false;
 300 }
 301
 302 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 303 {
 304         u32 m_cmd;
 305
 306         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 307         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 308         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 309 }
 310
 311 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 312 {
 313         int done;
 314         u32 irq_clear = M_CMD_DONE_EN;
 315
 316         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 317                                                 M_CMD_DONE_EN, true);
 318         if (!done) {
 319                 writel(M_GENI_CMD_ABORT, uport->membase +
 320                                                 SE_GENI_M_CMD_CTRL_REG);
 321                 irq_clear |= M_CMD_ABORT_EN;
 322                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 323                                                         M_CMD_ABORT_EN, true);
 324         }
 325         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 326 }
 327
 328 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 329 {
 330         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 331
 332         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 333         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 334                                         S_GENI_CMD_ABORT, false);
 335         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 336         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 337 }
 338
 339 #ifdef CONFIG_CONSOLE_POLL
 340
 341 static int qcom_geni_serial_get_char(struct uart_port *uport)
 342 {
 343         struct qcom_geni_private_data *private_data = uport->private_data;
 344         u32 status;
 345         u32 word_cnt;
 346         int ret;
 347
 348         if (!private_data->poll_cached_bytes_cnt) {
 349                 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 350                 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 351
 352                 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 353                 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 354
 355                 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 356                 word_cnt = status & RX_FIFO_WC_MSK;
 357                 if (!word_cnt)
 358                         return NO_POLL_CHAR;
 359
 360                 if (word_cnt == 1 && (status & RX_LAST))
 361                         /*
 362                          * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
 363                          * treated as if it was BYTES_PER_FIFO_WORD.
 364                          */
 365                         private_data->poll_cached_bytes_cnt =
 366                                 (status & RX_LAST_BYTE_VALID_MSK) >>
 367                                 RX_LAST_BYTE_VALID_SHFT;
 368
 369                 if (private_data->poll_cached_bytes_cnt == 0)
 370                         private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
 371
 372                 private_data->poll_cached_bytes =
 373                         readl(uport->membase + SE_GENI_RX_FIFOn);
 374         }
 375
 376         private_data->poll_cached_bytes_cnt--;
 377         ret = private_data->poll_cached_bytes & 0xff;
 378         private_data->poll_cached_bytes >>= 8;
 379
 380         return ret;
 381 }
 382
 383 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 384                                                         unsigned char c)
 385 {
 386         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 387         qcom_geni_serial_setup_tx(uport, 1);
 388         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 389                                                 M_TX_FIFO_WATERMARK_EN, true));
 390         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 391         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 392         qcom_geni_serial_poll_tx_done(uport);
 393 }
 394 #endif
 395
 396 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 397 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
 398 {
 399         struct qcom_geni_private_data *private_data = uport->private_data;
 400
 401         private_data->write_cached_bytes =
 402                 (private_data->write_cached_bytes >> 8) | (ch << 24);
 403         private_data->write_cached_bytes_cnt++;
 404
 405         if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
 406                 writel(private_data->write_cached_bytes,
 407                        uport->membase + SE_GENI_TX_FIFOn);
 408                 private_data->write_cached_bytes_cnt = 0;
 409         }
 410 }
 411
 412 static void
 413 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 414                                  unsigned int count)
 415 {
 416         struct qcom_geni_private_data *private_data = uport->private_data;
 417
 418         int i;
 419         u32 bytes_to_send = count;
 420
 421         for (i = 0; i < count; i++) {
 422                 /*
 423                  * uart_console_write() adds a carriage return for each newline.
 424                  * Account for additional bytes to be written.
 425                  */
 426                 if (s[i] == '\n')
 427                         bytes_to_send++;
 428         }
 429
 430         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 431         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 432         for (i = 0; i < count; ) {
 433                 size_t chars_to_write = 0;
 434                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 435
 436                 /*
 437                  * If the WM bit never set, then the Tx state machine is not
 438                  * in a valid state, so break, cancel/abort any existing
 439                  * command. Unfortunately the current data being written is
 440                  * lost.
 441                  */
 442                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 443                                                 M_TX_FIFO_WATERMARK_EN, true))
 444                         break;
 445                 chars_to_write = min_t(size_t, count - i, avail / 2);
 446                 uart_console_write(uport, s + i, chars_to_write,
 447                                                 qcom_geni_serial_wr_char);
 448                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 449                                                         SE_GENI_M_IRQ_CLEAR);
 450                 i += chars_to_write;
 451         }
 452
 453         if (private_data->write_cached_bytes_cnt) {
 454                 private_data->write_cached_bytes >>= BITS_PER_BYTE *
 455                         (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
 456                 writel(private_data->write_cached_bytes,
 457                        uport->membase + SE_GENI_TX_FIFOn);
 458                 private_data->write_cached_bytes_cnt = 0;
 459         }
 460
 461         qcom_geni_serial_poll_tx_done(uport);
 462 }
 463
 464 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 465                               unsigned int count)
 466 {
 467         struct uart_port *uport;
 468         struct qcom_geni_serial_port *port;
 469         bool locked = true;
 470         unsigned long flags;
 471         u32 geni_status;
 472         u32 irq_en;
 473
 474         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 475
 476         port = get_port_from_line(co->index, true);
 477         if (IS_ERR(port))
 478                 return;
 479
 480         uport = &port->uport;
 481         if (oops_in_progress)
 482                 locked = spin_trylock_irqsave(&uport->lock, flags);
 483         else
 484                 spin_lock_irqsave(&uport->lock, flags);
 485
 486         geni_status = readl(uport->membase + SE_GENI_STATUS);
 487
 488         /* Cancel the current write to log the fault */
 489         if (!locked) {
 490                 geni_se_cancel_m_cmd(&port->se);
 491                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 492                                                 M_CMD_CANCEL_EN, true)) {
 493                         geni_se_abort_m_cmd(&port->se);
 494                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 495                                                         M_CMD_ABORT_EN, true);
 496                         writel(M_CMD_ABORT_EN, uport->membase +
 497                                                         SE_GENI_M_IRQ_CLEAR);
 498                 }
 499                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 500         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 501                 /*
 502                  * It seems we can't interrupt existing transfers if all data
 503                  * has been sent, in which case we need to look for done first.
 504                  */
 505                 qcom_geni_serial_poll_tx_done(uport);
 506
 507                 if (!uart_circ_empty(&uport->state->xmit)) {
 508                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 509                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 510                                         uport->membase + SE_GENI_M_IRQ_EN);
 511                 }
 512         }
 513
 514         __qcom_geni_serial_console_write(uport, s, count);
 515
 516         if (port->tx_remaining)
 517                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 518
 519         if (locked)
 520                 spin_unlock_irqrestore(&uport->lock, flags);
 521 }
 522
 523 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 524 {
 525         u32 i;
 526         unsigned char buf[sizeof(u32)];
 527         struct tty_port *tport;
 528         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 529
 530         tport = &uport->state->port;
 531         for (i = 0; i < bytes; ) {
 532                 int c;
 533                 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
 534
 535                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 536                 i += chunk;
 537                 if (drop)
 538                         continue;
 539
 540                 for (c = 0; c < chunk; c++) {
 541                         int sysrq;
 542
 543                         uport->icount.rx++;
 544                         if (port->brk && buf[c] == 0) {
 545                                 port->brk = false;
 546                                 if (uart_handle_break(uport))
 547                                         continue;
 548                         }
 549
 550                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 551
 552                         if (!sysrq)
 553                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 554                 }
 555         }
 556         if (!drop)
 557                 tty_flip_buffer_push(tport);
 558         return 0;
 559 }
 560 #else
 561 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 562 {
 563         return -EPERM;
 564 }
 565
 566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 567
 568 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 569 {
 570         struct tty_port *tport;
 571         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 572         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 573         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 574         int ret;
 575
 576         tport = &uport->state->port;
 577         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 578         if (drop)
 579                 return 0;
 580
 581         ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
 582         if (ret != bytes) {
 583                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 584                                 __func__, ret, bytes);
 585                 WARN_ON_ONCE(1);
 586         }
 587         uport->icount.rx += ret;
 588         tty_flip_buffer_push(tport);
 589         return ret;
 590 }
 591
 592 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 593 {
 594         u32 irq_en;
 595         u32 status;
 596
 597         status = readl(uport->membase + SE_GENI_STATUS);
 598         if (status & M_GENI_CMD_ACTIVE)
 599                 return;
 600
 601         if (!qcom_geni_serial_tx_empty(uport))
 602                 return;
 603
 604         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 605         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 606
 607         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 608         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 609 }
 610
 611 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 612 {
 613         u32 irq_en;
 614         u32 status;
 615         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 616
 617         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 618         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 619         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 620         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 621         status = readl(uport->membase + SE_GENI_STATUS);
 622         /* Possible stop tx is called multiple times. */
 623         if (!(status & M_GENI_CMD_ACTIVE))
 624                 return;
 625
 626         geni_se_cancel_m_cmd(&port->se);
 627         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 628                                                 M_CMD_CANCEL_EN, true)) {
 629                 geni_se_abort_m_cmd(&port->se);
 630                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 631                                                 M_CMD_ABORT_EN, true);
 632                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 633         }
 634         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 635 }
 636
 637 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 638 {
 639         u32 irq_en;
 640         u32 status;
 641         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 642
 643         status = readl(uport->membase + SE_GENI_STATUS);
 644         if (status & S_GENI_CMD_ACTIVE)
 645                 qcom_geni_serial_stop_rx(uport);
 646
 647         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 648
 649         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 650         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 651         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 652
 653         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 654         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 655         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 656 }
 657
 658 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 659 {
 660         u32 irq_en;
 661         u32 status;
 662         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 663         u32 s_irq_status;
 664
 665         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 666         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 667         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 668
 669         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 670         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 671         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 672
 673         status = readl(uport->membase + SE_GENI_STATUS);
 674         /* Possible stop rx is called multiple times. */
 675         if (!(status & S_GENI_CMD_ACTIVE))
 676                 return;
 677
 678         geni_se_cancel_s_cmd(&port->se);
 679         qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 680                                         S_CMD_CANCEL_EN, true);
 681         /*
 682          * If timeout occurs secondary engine remains active
 683          * and Abort sequence is executed.
 684          */
 685         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 686         /* Flush the Rx buffer */
 687         if (s_irq_status & S_RX_FIFO_LAST_EN)
 688                 qcom_geni_serial_handle_rx(uport, true);
 689         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 690
 691         status = readl(uport->membase + SE_GENI_STATUS);
 692         if (status & S_GENI_CMD_ACTIVE)
 693                 qcom_geni_serial_abort_rx(uport);
 694 }
 695
 696 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 697 {
 698         u32 status;
 699         u32 word_cnt;
 700         u32 last_word_byte_cnt;
 701         u32 last_word_partial;
 702         u32 total_bytes;
 703         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 704
 705         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 706         word_cnt = status & RX_FIFO_WC_MSK;
 707         last_word_partial = status & RX_LAST;
 708         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 709                                                 RX_LAST_BYTE_VALID_SHFT;
 710
 711         if (!word_cnt)
 712                 return;
 713         total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
 714         if (last_word_partial && last_word_byte_cnt)
 715                 total_bytes += last_word_byte_cnt;
 716         else
 717                 total_bytes += BYTES_PER_FIFO_WORD;
 718         port->handle_rx(uport, total_bytes, drop);
 719 }
 720
 721 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 722                 bool active)
 723 {
 724         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 725         struct circ_buf *xmit = &uport->state->xmit;
 726         size_t avail;
 727         size_t remaining;
 728         size_t pending;
 729         int i;
 730         u32 status;
 731         u32 irq_en;
 732         unsigned int chunk;
 733         int tail;
 734
 735         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 736
 737         /* Complete the current tx command before taking newly added data */
 738         if (active)
 739                 pending = port->tx_remaining;
 740         else
 741                 pending = uart_circ_chars_pending(xmit);
 742
 743         /* All data has been transmitted and acknowledged as received */
 744         if (!pending && !status && done) {
 745                 qcom_geni_serial_stop_tx(uport);
 746                 goto out_write_wakeup;
 747         }
 748
 749         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 750         avail *= BYTES_PER_FIFO_WORD;
 751
 752         tail = xmit->tail;
 753         chunk = min(avail, pending);
 754         if (!chunk)
 755                 goto out_write_wakeup;
 756
 757         if (!port->tx_remaining) {
 758                 qcom_geni_serial_setup_tx(uport, pending);
 759                 port->tx_remaining = pending;
 760
 761                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 762                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 763                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 764                                         uport->membase + SE_GENI_M_IRQ_EN);
 765         }
 766
 767         remaining = chunk;
 768         for (i = 0; i < chunk; ) {
 769                 unsigned int tx_bytes;
 770                 u8 buf[sizeof(u32)];
 771                 int c;
 772
 773                 memset(buf, 0, sizeof(buf));
 774                 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
 775
 776                 for (c = 0; c < tx_bytes ; c++) {
 777                         buf[c] = xmit->buf[tail++];
 778                         tail &= UART_XMIT_SIZE - 1;
 779                 }
 780
 781                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 782
 783                 i += tx_bytes;
 784                 uport->icount.tx += tx_bytes;
 785                 remaining -= tx_bytes;
 786                 port->tx_remaining -= tx_bytes;
 787         }
 788
 789         xmit->tail = tail;
 790
 791         /*
 792          * The tx fifo watermark is level triggered and latched. Though we had
 793          * cleared it in qcom_geni_serial_isr it will have already reasserted
 794          * so we must clear it again here after our writes.
 795          */
 796         writel(M_TX_FIFO_WATERMARK_EN,
 797                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 798
 799 out_write_wakeup:
 800         if (!port->tx_remaining) {
 801                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 802                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 803                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 804                                         uport->membase + SE_GENI_M_IRQ_EN);
 805         }
 806
 807         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 808                 uart_write_wakeup(uport);
 809 }
 810
 811 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 812 {
 813         u32 m_irq_en;
 814         u32 m_irq_status;
 815         u32 s_irq_status;
 816         u32 geni_status;
 817         struct uart_port *uport = dev;
 818         bool drop_rx = false;
 819         struct tty_port *tport = &uport->state->port;
 820         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 821
 822         if (uport->suspended)
 823                 return IRQ_NONE;
 824
 825         spin_lock(&uport->lock);
 826
 827         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 828         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 829         geni_status = readl(uport->membase + SE_GENI_STATUS);
 830         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 831         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 832         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 833
 834         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 835                 goto out_unlock;
 836
 837         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 838                 uport->icount.overrun++;
 839                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 840         }
 841
 842         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 843                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 844                                         geni_status & M_GENI_CMD_ACTIVE);
 845
 846         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 847                 if (s_irq_status & S_GP_IRQ_0_EN)
 848                         uport->icount.parity++;
 849                 drop_rx = true;
 850         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 851                                         s_irq_status & S_GP_IRQ_3_EN) {
 852                 uport->icount.brk++;
 853                 port->brk = true;
 854         }
 855
 856         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 857                                         s_irq_status & S_RX_FIFO_LAST_EN)
 858                 qcom_geni_serial_handle_rx(uport, drop_rx);
 859
 860 out_unlock:
 861         uart_unlock_and_check_sysrq(uport);
 862
 863         return IRQ_HANDLED;
 864 }
 865
 866 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 867 {
 868         struct uart_port *uport;
 869
 870         uport = &port->uport;
 871         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 872         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 873         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 874         uport->fifosize =
 875                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 876 }
 877
 878
 879 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 880 {
 881         disable_irq(uport->irq);
 882 }
 883
 884 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 885 {
 886         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 887         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 888         u32 proto;
 889         u32 pin_swap;
 890
 891         proto = geni_se_read_proto(&port->se);
 892         if (proto != GENI_SE_UART) {
 893                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 894                 return -ENXIO;
 895         }
 896
 897         qcom_geni_serial_stop_rx(uport);
 898
 899         get_tx_fifo_size(port);
 900
 901         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 902
 903         pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
 904         if (port->rx_tx_swap) {
 905                 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
 906                 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
 907         }
 908         if (port->cts_rts_swap) {
 909                 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
 910                 pin_swap |= IO_MACRO_IO0_SEL;
 911         }
 912         /* Configure this register if RX-TX, CTS-RTS pins are swapped */
 913         if (port->rx_tx_swap || port->cts_rts_swap)
 914                 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
 915
 916         /*
 917          * Make an unconditional cancel on the main sequencer to reset
 918          * it else we could end up in data loss scenarios.
 919          */
 920         if (uart_console(uport))
 921                 qcom_geni_serial_poll_tx_done(uport);
 922         geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
 923                                false, true, true);
 924         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 925         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 926         port->setup = true;
 927
 928         return 0;
 929 }
 930
 931 static int qcom_geni_serial_startup(struct uart_port *uport)
 932 {
 933         int ret;
 934         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 935
 936         if (!port->setup) {
 937                 ret = qcom_geni_serial_port_setup(uport);
 938                 if (ret)
 939                         return ret;
 940         }
 941         enable_irq(uport->irq);
 942
 943         return 0;
 944 }
 945
 946 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
 947                         unsigned int sampling_rate, unsigned int *clk_div)
 948 {
 949         unsigned long ser_clk;
 950         unsigned long desired_clk;
 951         unsigned long freq, prev;
 952         unsigned long div, maxdiv;
 953         int64_t mult;
 954
 955         desired_clk = baud * sampling_rate;
 956         if (!desired_clk) {
 957                 pr_err("%s: Invalid frequency\n", __func__);
 958                 return 0;
 959         }
 960
 961         maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
 962         prev = 0;
 963
 964         for (div = 1; div <= maxdiv; div++) {
 965                 mult = div * desired_clk;
 966                 if (mult > ULONG_MAX)
 967                         break;
 968
 969                 freq = clk_round_rate(clk, (unsigned long)mult);
 970                 if (!(freq % desired_clk)) {
 971                         ser_clk = freq;
 972                         break;
 973                 }
 974
 975                 if (!prev)
 976                         ser_clk = freq;
 977                 else if (prev == freq)
 978                         break;
 979
 980                 prev = freq;
 981         }
 982
 983         if (!ser_clk) {
 984                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 985                                                                 __func__, baud);
 986                 return ser_clk;
 987         }
 988
 989         *clk_div = ser_clk / desired_clk;
 990         if (!(*clk_div))
 991                 *clk_div = 1;
 992
 993         return ser_clk;
 994 }
 995
 996 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 997                                 struct ktermios *termios, struct ktermios *old)
 998 {
 999         unsigned int baud;
1000         u32 bits_per_char;
1001         u32 tx_trans_cfg;
1002         u32 tx_parity_cfg;
1003         u32 rx_trans_cfg;
1004         u32 rx_parity_cfg;
1005         u32 stop_bit_len;
1006         unsigned int clk_div;
1007         u32 ser_clk_cfg;
1008         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1009         unsigned long clk_rate;
1010         u32 ver, sampling_rate;
1011         unsigned int avg_bw_core;
1012
1013         qcom_geni_serial_stop_rx(uport);
1014         /* baud rate */
1015         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1016         port->baud = baud;
1017
1018         sampling_rate = UART_OVERSAMPLING;
1019         /* Sampling rate is halved for IP versions >= 2.5 */
1020         ver = geni_se_get_qup_hw_version(&port->se);
1021         if (ver >= QUP_SE_VERSION_2_5)
1022                 sampling_rate /= 2;
1023
1024         clk_rate = get_clk_div_rate(port->se.clk, baud,
1025                 sampling_rate, &clk_div);
1026         if (!clk_rate)
1027                 goto out_restart_rx;
1028
1029         uport->uartclk = clk_rate;
1030         dev_pm_opp_set_rate(uport->dev, clk_rate);
1031         ser_clk_cfg = SER_CLK_EN;
1032         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1033
1034         /*
1035          * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1036          * only.
1037          */
1038         avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1039                                                 : GENI_DEFAULT_BW;
1040         port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1041         port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1042         geni_icc_set_bw(&port->se);
1043
1044         /* parity */
1045         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1046         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1047         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1048         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1049         if (termios->c_cflag & PARENB) {
1050                 tx_trans_cfg |= UART_TX_PAR_EN;
1051                 rx_trans_cfg |= UART_RX_PAR_EN;
1052                 tx_parity_cfg |= PAR_CALC_EN;
1053                 rx_parity_cfg |= PAR_CALC_EN;
1054                 if (termios->c_cflag & PARODD) {
1055                         tx_parity_cfg |= PAR_ODD;
1056                         rx_parity_cfg |= PAR_ODD;
1057                 } else if (termios->c_cflag & CMSPAR) {
1058                         tx_parity_cfg |= PAR_SPACE;
1059                         rx_parity_cfg |= PAR_SPACE;
1060                 } else {
1061                         tx_parity_cfg |= PAR_EVEN;
1062                         rx_parity_cfg |= PAR_EVEN;
1063                 }
1064         } else {
1065                 tx_trans_cfg &= ~UART_TX_PAR_EN;
1066                 rx_trans_cfg &= ~UART_RX_PAR_EN;
1067                 tx_parity_cfg &= ~PAR_CALC_EN;
1068                 rx_parity_cfg &= ~PAR_CALC_EN;
1069         }
1070
1071         /* bits per char */
1072         bits_per_char = tty_get_char_size(termios->c_cflag);
1073
1074         /* stop bits */
1075         if (termios->c_cflag & CSTOPB)
1076                 stop_bit_len = TX_STOP_BIT_LEN_2;
1077         else
1078                 stop_bit_len = TX_STOP_BIT_LEN_1;
1079
1080         /* flow control, clear the CTS_MASK bit if using flow control. */
1081         if (termios->c_cflag & CRTSCTS)
1082                 tx_trans_cfg &= ~UART_CTS_MASK;
1083         else
1084                 tx_trans_cfg |= UART_CTS_MASK;
1085
1086         if (baud)
1087                 uart_update_timeout(uport, termios->c_cflag, baud);
1088
1089         if (!uart_console(uport))
1090                 writel(port->loopback,
1091                                 uport->membase + SE_UART_LOOPBACK_CFG);
1092         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1093         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1094         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1095         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1096         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1097         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1098         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1099         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1100         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1101 out_restart_rx:
1102         qcom_geni_serial_start_rx(uport);
1103 }
1104
1105 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1106 {
1107         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1108 }
1109
1110 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1111 static int qcom_geni_console_setup(struct console *co, char *options)
1112 {
1113         struct uart_port *uport;
1114         struct qcom_geni_serial_port *port;
1115         int baud = 115200;
1116         int bits = 8;
1117         int parity = 'n';
1118         int flow = 'n';
1119         int ret;
1120
1121         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1122                 return -ENXIO;
1123
1124         port = get_port_from_line(co->index, true);
1125         if (IS_ERR(port)) {
1126                 pr_err("Invalid line %d\n", co->index);
1127                 return PTR_ERR(port);
1128         }
1129
1130         uport = &port->uport;
1131
1132         if (unlikely(!uport->membase))
1133                 return -ENXIO;
1134
1135         if (!port->setup) {
1136                 ret = qcom_geni_serial_port_setup(uport);
1137                 if (ret)
1138                         return ret;
1139         }
1140
1141         if (options)
1142                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1143
1144         return uart_set_options(uport, co, baud, parity, bits, flow);
1145 }
1146
1147 static void qcom_geni_serial_earlycon_write(struct console *con,
1148                                         const char *s, unsigned int n)
1149 {
1150         struct earlycon_device *dev = con->data;
1151
1152         __qcom_geni_serial_console_write(&dev->port, s, n);
1153 }
1154
1155 #ifdef CONFIG_CONSOLE_POLL
1156 static int qcom_geni_serial_earlycon_read(struct console *con,
1157                                           char *s, unsigned int n)
1158 {
1159         struct earlycon_device *dev = con->data;
1160         struct uart_port *uport = &dev->port;
1161         int num_read = 0;
1162         int ch;
1163
1164         while (num_read < n) {
1165                 ch = qcom_geni_serial_get_char(uport);
1166                 if (ch == NO_POLL_CHAR)
1167                         break;
1168                 s[num_read++] = ch;
1169         }
1170
1171         return num_read;
1172 }
1173
1174 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1175                                                       struct console *con)
1176 {
1177         geni_se_setup_s_cmd(se, UART_START_READ, 0);
1178         con->read = qcom_geni_serial_earlycon_read;
1179 }
1180 #else
1181 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1182                                                       struct console *con) { }
1183 #endif
1184
1185 static struct qcom_geni_private_data earlycon_private_data;
1186
1187 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1188                                                                 const char *opt)
1189 {
1190         struct uart_port *uport = &dev->port;
1191         u32 tx_trans_cfg;
1192         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1193         u32 rx_trans_cfg = 0;
1194         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1195         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1196         u32 bits_per_char;
1197         struct geni_se se;
1198
1199         if (!uport->membase)
1200                 return -EINVAL;
1201
1202         uport->private_data = &earlycon_private_data;
1203
1204         memset(&se, 0, sizeof(se));
1205         se.base = uport->membase;
1206         if (geni_se_read_proto(&se) != GENI_SE_UART)
1207                 return -ENXIO;
1208         /*
1209          * Ignore Flow control.
1210          * n = 8.
1211          */
1212         tx_trans_cfg = UART_CTS_MASK;
1213         bits_per_char = BITS_PER_BYTE;
1214
1215         /*
1216          * Make an unconditional cancel on the main sequencer to reset
1217          * it else we could end up in data loss scenarios.
1218          */
1219         qcom_geni_serial_poll_tx_done(uport);
1220         qcom_geni_serial_abort_rx(uport);
1221         geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1222                                false, true, true);
1223         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1224         geni_se_select_mode(&se, GENI_SE_FIFO);
1225
1226         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1227         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1228         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1229         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1230         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1231         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1232         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1233
1234         dev->con->write = qcom_geni_serial_earlycon_write;
1235         dev->con->setup = NULL;
1236         qcom_geni_serial_enable_early_read(&se, dev->con);
1237
1238         return 0;
1239 }
1240 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1241                                 qcom_geni_serial_earlycon_setup);
1242
1243 static int __init console_register(struct uart_driver *drv)
1244 {
1245         return uart_register_driver(drv);
1246 }
1247
1248 static void console_unregister(struct uart_driver *drv)
1249 {
1250         uart_unregister_driver(drv);
1251 }
1252
1253 static struct console cons_ops = {
1254         .name = "ttyMSM",
1255         .write = qcom_geni_serial_console_write,
1256         .device = uart_console_device,
1257         .setup = qcom_geni_console_setup,
1258         .flags = CON_PRINTBUFFER,
1259         .index = -1,
1260         .data = &qcom_geni_console_driver,
1261 };
1262
1263 static struct uart_driver qcom_geni_console_driver = {
1264         .owner = THIS_MODULE,
1265         .driver_name = "qcom_geni_console",
1266         .dev_name = "ttyMSM",
1267         .nr =  GENI_UART_CONS_PORTS,
1268         .cons = &cons_ops,
1269 };
1270 #else
1271 static int console_register(struct uart_driver *drv)
1272 {
1273         return 0;
1274 }
1275
1276 static void console_unregister(struct uart_driver *drv)
1277 {
1278 }
1279 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1280
1281 static struct uart_driver qcom_geni_uart_driver = {
1282         .owner = THIS_MODULE,
1283         .driver_name = "qcom_geni_uart",
1284         .dev_name = "ttyHS",
1285         .nr =  GENI_UART_PORTS,
1286 };
1287
1288 static void qcom_geni_serial_pm(struct uart_port *uport,
1289                 unsigned int new_state, unsigned int old_state)
1290 {
1291         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1292
1293         /* If we've never been called, treat it as off */
1294         if (old_state == UART_PM_STATE_UNDEFINED)
1295                 old_state = UART_PM_STATE_OFF;
1296
1297         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1298                 geni_icc_enable(&port->se);
1299                 geni_se_resources_on(&port->se);
1300         } else if (new_state == UART_PM_STATE_OFF &&
1301                         old_state == UART_PM_STATE_ON) {
1302                 geni_se_resources_off(&port->se);
1303                 geni_icc_disable(&port->se);
1304         }
1305 }
1306
1307 static const struct uart_ops qcom_geni_console_pops = {
1308         .tx_empty = qcom_geni_serial_tx_empty,
1309         .stop_tx = qcom_geni_serial_stop_tx,
1310         .start_tx = qcom_geni_serial_start_tx,
1311         .stop_rx = qcom_geni_serial_stop_rx,
1312         .start_rx = qcom_geni_serial_start_rx,
1313         .set_termios = qcom_geni_serial_set_termios,
1314         .startup = qcom_geni_serial_startup,
1315         .request_port = qcom_geni_serial_request_port,
1316         .config_port = qcom_geni_serial_config_port,
1317         .shutdown = qcom_geni_serial_shutdown,
1318         .type = qcom_geni_serial_get_type,
1319         .set_mctrl = qcom_geni_serial_set_mctrl,
1320         .get_mctrl = qcom_geni_serial_get_mctrl,
1321 #ifdef CONFIG_CONSOLE_POLL
1322         .poll_get_char  = qcom_geni_serial_get_char,
1323         .poll_put_char  = qcom_geni_serial_poll_put_char,
1324 #endif
1325         .pm = qcom_geni_serial_pm,
1326 };
1327
1328 static const struct uart_ops qcom_geni_uart_pops = {
1329         .tx_empty = qcom_geni_serial_tx_empty,
1330         .stop_tx = qcom_geni_serial_stop_tx,
1331         .start_tx = qcom_geni_serial_start_tx,
1332         .stop_rx = qcom_geni_serial_stop_rx,
1333         .set_termios = qcom_geni_serial_set_termios,
1334         .startup = qcom_geni_serial_startup,
1335         .request_port = qcom_geni_serial_request_port,
1336         .config_port = qcom_geni_serial_config_port,
1337         .shutdown = qcom_geni_serial_shutdown,
1338         .type = qcom_geni_serial_get_type,
1339         .set_mctrl = qcom_geni_serial_set_mctrl,
1340         .get_mctrl = qcom_geni_serial_get_mctrl,
1341         .pm = qcom_geni_serial_pm,
1342 };
1343
1344 static int qcom_geni_serial_probe(struct platform_device *pdev)
1345 {
1346         int ret = 0;
1347         int line;
1348         struct qcom_geni_serial_port *port;
1349         struct uart_port *uport;
1350         struct resource *res;
1351         int irq;
1352         bool console = false;
1353         struct uart_driver *drv;
1354
1355         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1356                 console = true;
1357
1358         if (console) {
1359                 drv = &qcom_geni_console_driver;
1360                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1361         } else {
1362                 drv = &qcom_geni_uart_driver;
1363                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1364                 if (line == -ENODEV) /* compat with non-standard aliases */
1365                         line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1366         }
1367
1368         port = get_port_from_line(line, console);
1369         if (IS_ERR(port)) {
1370                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1371                 return PTR_ERR(port);
1372         }
1373
1374         uport = &port->uport;
1375         /* Don't allow 2 drivers to access the same port */
1376         if (uport->private_data)
1377                 return -ENODEV;
1378
1379         uport->dev = &pdev->dev;
1380         port->se.dev = &pdev->dev;
1381         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1382         port->se.clk = devm_clk_get(&pdev->dev, "se");
1383         if (IS_ERR(port->se.clk)) {
1384                 ret = PTR_ERR(port->se.clk);
1385                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1386                 return ret;
1387         }
1388
1389         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390         if (!res)
1391                 return -EINVAL;
1392         uport->mapbase = res->start;
1393
1394         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1395         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1396         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1397
1398         if (!console) {
1399                 port->rx_fifo = devm_kcalloc(uport->dev,
1400                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1401                 if (!port->rx_fifo)
1402                         return -ENOMEM;
1403         }
1404
1405         ret = geni_icc_get(&port->se, NULL);
1406         if (ret)
1407                 return ret;
1408         port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1409         port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1410
1411         /* Set BW for register access */
1412         ret = geni_icc_set_bw(&port->se);
1413         if (ret)
1414                 return ret;
1415
1416         port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1417                         "qcom_geni_serial_%s%d",
1418                         uart_console(uport) ? "console" : "uart", uport->line);
1419         if (!port->name)
1420                 return -ENOMEM;
1421
1422         irq = platform_get_irq(pdev, 0);
1423         if (irq < 0)
1424                 return irq;
1425         uport->irq = irq;
1426         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1427
1428         if (!console)
1429                 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1430
1431         if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1432                 port->rx_tx_swap = true;
1433
1434         if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1435                 port->cts_rts_swap = true;
1436
1437         ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1438         if (ret)
1439                 return ret;
1440         /* OPP table is optional */
1441         ret = devm_pm_opp_of_add_table(&pdev->dev);
1442         if (ret && ret != -ENODEV) {
1443                 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1444                 return ret;
1445         }
1446
1447         port->private_data.drv = drv;
1448         uport->private_data = &port->private_data;
1449         platform_set_drvdata(pdev, port);
1450         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1451
1452         ret = uart_add_one_port(drv, uport);
1453         if (ret)
1454                 return ret;
1455
1456         irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1457         ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1458                         IRQF_TRIGGER_HIGH, port->name, uport);
1459         if (ret) {
1460                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1461                 uart_remove_one_port(drv, uport);
1462                 return ret;
1463         }
1464
1465         /*
1466          * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1467          * enabled/disabled from dev_pm_arm_wake_irq during system
1468          * suspend/resume respectively.
1469          */
1470         pm_runtime_set_active(&pdev->dev);
1471
1472         if (port->wakeup_irq > 0) {
1473                 device_init_wakeup(&pdev->dev, true);
1474                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1475                                                 port->wakeup_irq);
1476                 if (ret) {
1477                         device_init_wakeup(&pdev->dev, false);
1478                         uart_remove_one_port(drv, uport);
1479                         return ret;
1480                 }
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int qcom_geni_serial_remove(struct platform_device *pdev)
1487 {
1488         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1489         struct uart_driver *drv = port->private_data.drv;
1490
1491         dev_pm_clear_wake_irq(&pdev->dev);
1492         device_init_wakeup(&pdev->dev, false);
1493         uart_remove_one_port(drv, &port->uport);
1494
1495         return 0;
1496 }
1497
1498 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1499 {
1500         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1501         struct uart_port *uport = &port->uport;
1502         struct qcom_geni_private_data *private_data = uport->private_data;
1503
1504         /*
1505          * This is done so we can hit the lowest possible state in suspend
1506          * even with no_console_suspend
1507          */
1508         if (uart_console(uport)) {
1509                 geni_icc_set_tag(&port->se, 0x3);
1510                 geni_icc_set_bw(&port->se);
1511         }
1512         return uart_suspend_port(private_data->drv, uport);
1513 }
1514
1515 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1516 {
1517         int ret;
1518         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1519         struct uart_port *uport = &port->uport;
1520         struct qcom_geni_private_data *private_data = uport->private_data;
1521
1522         ret = uart_resume_port(private_data->drv, uport);
1523         if (uart_console(uport)) {
1524                 geni_icc_set_tag(&port->se, 0x7);
1525                 geni_icc_set_bw(&port->se);
1526         }
1527         return ret;
1528 }
1529
1530 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1531         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1532                                         qcom_geni_serial_sys_resume)
1533 };
1534
1535 static const struct of_device_id qcom_geni_serial_match_table[] = {
1536         { .compatible = "qcom,geni-debug-uart", },
1537         { .compatible = "qcom,geni-uart", },
1538         {}
1539 };
1540 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1541
1542 static struct platform_driver qcom_geni_serial_platform_driver = {
1543         .remove = qcom_geni_serial_remove,
1544         .probe = qcom_geni_serial_probe,
1545         .driver = {
1546                 .name = "qcom_geni_serial",
1547                 .of_match_table = qcom_geni_serial_match_table,
1548                 .pm = &qcom_geni_serial_pm_ops,
1549         },
1550 };
1551
1552 static int __init qcom_geni_serial_init(void)
1553 {
1554         int ret;
1555
1556         ret = console_register(&qcom_geni_console_driver);
1557         if (ret)
1558                 return ret;
1559
1560         ret = uart_register_driver(&qcom_geni_uart_driver);
1561         if (ret) {
1562                 console_unregister(&qcom_geni_console_driver);
1563                 return ret;
1564         }
1565
1566         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1567         if (ret) {
1568                 console_unregister(&qcom_geni_console_driver);
1569                 uart_unregister_driver(&qcom_geni_uart_driver);
1570         }
1571         return ret;
1572 }
1573 module_init(qcom_geni_serial_init);
1574
1575 static void __exit qcom_geni_serial_exit(void)
1576 {
1577         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1578         console_unregister(&qcom_geni_console_driver);
1579         uart_unregister_driver(&qcom_geni_uart_driver);
1580 }
1581 module_exit(qcom_geni_serial_exit);
1582
1583 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1584 MODULE_LICENSE("GPL v2");