drivers/staging/rtl8192u/r8192U_dm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*****************************************************************************
   3  *      Copyright(c) 2007,  RealTEK Technology Inc. All Right Reserved.
   4  *
   5  * Module:              Hal819xUsbDM.h  (RTL8192  Header H File)
   6  *
   7  *
   8  * Note:                For dynamic control definition constant structure.
   9  *
  10  *
  11  * Export:
  12  *
  13  * Abbrev:
  14  *
  15  * History:
  16  *      Data            Who             Remark
  17  *      10/04/2007  MHC         Create initial version.
  18  *
  19  *****************************************************************************/
  20  /* Check to see if the file has been included already.  */
  21 #ifndef __R8192UDM_H__
  22 #define __R8192UDM_H__
  23
  24
  25 /*--------------------------Define Parameters-------------------------------*/
  26 #define         DM_DIG_THRESH_HIGH                                      40
  27 #define         DM_DIG_THRESH_LOW                                       35
  28
  29 #define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
  30 #define         DM_DIG_HIGH_PWR_THRESH_LOW              70
  31
  32 #define         BW_AUTO_SWITCH_HIGH_LOW                 25
  33 #define         BW_AUTO_SWITCH_LOW_HIGH                 30
  34
  35 #define         DM_check_fsync_time_interval                            500
  36
  37
  38 #define         DM_DIG_BACKOFF                          12
  39 #define         DM_DIG_MAX                                      0x36
  40 #define         DM_DIG_MIN                                      0x1c
  41 #define         DM_DIG_MIN_Netcore                      0x12
  42
  43 #define         RxPathSelection_SS_TH_low               30
  44 #define         RxPathSelection_diff_TH                 18
  45
  46 #define         RateAdaptiveTH_High                     50
  47 #define         RateAdaptiveTH_Low_20M          30
  48 #define         RateAdaptiveTH_Low_40M          10
  49 #define         VeryLowRSSI                                     15
  50 #define         CTSToSelfTHVal                                  30
  51
  52 /* defined by vivi, for tx power track */
  53 #define         E_FOR_TX_POWER_TRACK               300
  54 /* Dynamic Tx Power Control Threshold */
  55 #define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
  56 #define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
  57 /* added by amy for atheros AP */
  58 #define         TX_POWER_ATHEROAP_THRESH_HIGH           78
  59 #define         TX_POWER_ATHEROAP_THRESH_LOW            72
  60
  61 /* defined by vivi, for showing on UI */
  62 #define                 Current_Tx_Rate_Reg         0x1b8
  63 #define                 Initial_Tx_Rate_Reg               0x1b9
  64 #define                 Tx_Retry_Count_Reg         0x1ac
  65 #define         RegC38_TH                                20
  66 /*--------------------------Define Parameters-------------------------------*/
  67
  68
  69 /*------------------------------Define structure----------------------------*/
  70 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
  71 struct dig {
  72         u8              dig_enable_flag;
  73         u8              dig_algorithm;
  74         u8              dbg_mode;
  75         u8              dig_algorithm_switch;
  76
  77         long            rssi_low_thresh;
  78         long            rssi_high_thresh;
  79
  80         long            rssi_high_power_lowthresh;
  81         long            rssi_high_power_highthresh;
  82
  83         u8              dig_state;
  84         u8              dig_highpwr_state;
  85         u8              cur_connect_state;
  86         u8              pre_connect_state;
  87
  88         u8              curpd_thstate;
  89         u8              prepd_thstate;
  90         u8              curcs_ratio_state;
  91         u8              precs_ratio_state;
  92
  93         u32             pre_ig_value;
  94         u32             cur_ig_value;
  95
  96         u8              backoff_val;
  97         u8              rx_gain_range_max;
  98         u8              rx_gain_range_min;
  99         bool            initialgain_lowerbound_state;
 100
 101         long            rssi_val;
 102 };
 103
 104 typedef enum tag_dynamic_init_gain_state_definition {
 105         DM_STA_DIG_OFF = 0,
 106         DM_STA_DIG_ON,
 107         DM_STA_DIG_MAX
 108 } dm_dig_sta_e;
 109
 110
 111 /* 2007/10/08 MH Define RATR state. */
 112 typedef enum tag_dynamic_ratr_state_definition {
 113         DM_RATR_STA_HIGH = 0,
 114         DM_RATR_STA_MIDDLE = 1,
 115         DM_RATR_STA_LOW = 2,
 116         DM_RATR_STA_MAX
 117 } dm_ratr_sta_e;
 118
 119 /* 2007/10/11 MH Define DIG operation type. */
 120 typedef enum tag_dynamic_init_gain_operation_type_definition {
 121         DIG_TYPE_THRESH_HIGH    = 0,
 122         DIG_TYPE_THRESH_LOW     = 1,
 123         DIG_TYPE_THRESH_HIGHPWR_HIGH    = 2,
 124         DIG_TYPE_THRESH_HIGHPWR_LOW     = 3,
 125         DIG_TYPE_DBG_MODE                               = 4,
 126         DIG_TYPE_RSSI                                           = 5,
 127         DIG_TYPE_ALGORITHM                              = 6,
 128         DIG_TYPE_BACKOFF                                        = 7,
 129         DIG_TYPE_PWDB_FACTOR                    = 8,
 130         DIG_TYPE_RX_GAIN_MIN                            = 9,
 131         DIG_TYPE_RX_GAIN_MAX                            = 10,
 132         DIG_TYPE_ENABLE                 = 20,
 133         DIG_TYPE_DISABLE                = 30,
 134         DIG_OP_TYPE_MAX
 135 } dm_dig_op_e;
 136
 137 typedef enum tag_dig_algorithm_definition {
 138         DIG_ALGO_BY_FALSE_ALARM = 0,
 139         DIG_ALGO_BY_RSSI        = 1,
 140         DIG_ALGO_MAX
 141 } dm_dig_alg_e;
 142
 143 typedef enum tag_dig_dbgmode_definition {
 144         DIG_DBG_OFF = 0,
 145         DIG_DBG_ON = 1,
 146         DIG_DBG_MAX
 147 } dm_dig_dbg_e;
 148
 149 typedef enum tag_dig_connect_definition {
 150         DIG_DISCONNECT = 0,
 151         DIG_CONNECT = 1,
 152         DIG_CONNECT_MAX
 153 } dm_dig_connect_e;
 154
 155 typedef enum tag_dig_packetdetection_threshold_definition {
 156         DIG_PD_AT_LOW_POWER = 0,
 157         DIG_PD_AT_NORMAL_POWER = 1,
 158         DIG_PD_AT_HIGH_POWER = 2,
 159         DIG_PD_MAX
 160 } dm_dig_pd_th_e;
 161
 162 typedef enum tag_dig_cck_cs_ratio_state_definition {
 163         DIG_CS_RATIO_LOWER = 0,
 164         DIG_CS_RATIO_HIGHER = 1,
 165         DIG_CS_MAX
 166 } dm_dig_cs_ratio_e;
 167 struct dynamic_rx_path_sel {
 168         u8              Enable;
 169         u8              DbgMode;
 170         u8              cck_method;
 171         u8              cck_Rx_path;
 172
 173         u8              SS_TH_low;
 174         u8              diff_TH;
 175         u8              disabledRF;
 176         u8              reserved;
 177
 178         u8              rf_rssi[4];
 179         u8              rf_enable_rssi_th[4];
 180         long            cck_pwdb_sta[4];
 181 };
 182
 183 typedef enum tag_CCK_Rx_Path_Method_Definition {
 184         CCK_Rx_Version_1 = 0,
 185         CCK_Rx_Version_2 = 1,
 186         CCK_Rx_Version_MAX
 187 } DM_CCK_Rx_Path_Method;
 188
 189 typedef enum tag_DM_DbgMode_Definition {
 190         DM_DBG_OFF = 0,
 191         DM_DBG_ON = 1,
 192         DM_DBG_MAX
 193 } DM_DBG_E;
 194
 195 typedef struct tag_Tx_Config_Cmd_Format {
 196         u32     Op;                     /* Command packet type. */
 197         u32     Length;                 /* Command packet length. */
 198         u32     Value;
 199 } DCMD_TXCMD_T, *PDCMD_TXCMD_T;
 200 /*------------------------------Define structure----------------------------*/
 201
 202
 203 /*------------------------Export global variable----------------------------*/
 204 extern struct dig dm_digtable;
 205 extern u8 dm_shadow[16][256];
 206 extern struct dynamic_rx_path_sel DM_RxPathSelTable;
 207 /*------------------------Export global variable----------------------------*/
 208
 209
 210 /*------------------------Export Marco Definition---------------------------*/
 211
 212 /*------------------------Export Marco Definition---------------------------*/
 213
 214
 215 /*--------------------------Exported Function prototype---------------------*/
 216 void init_hal_dm(struct net_device *dev);
 217 void deinit_hal_dm(struct net_device *dev);
 218 void hal_dm_watchdog(struct net_device *dev);
 219 void init_rate_adaptive(struct net_device *dev);
 220 void dm_txpower_trackingcallback(struct work_struct *work);
 221 void dm_restore_dynamic_mechanism_state(struct net_device *dev);
 222 void dm_backup_dynamic_mechanism_state(struct net_device *dev);
 223 void dm_change_dynamic_initgain_thresh(struct net_device *dev,
 224                                        u32 dm_type, u32 dm_value);
 225 void dm_force_tx_fw_info(struct net_device *dev,
 226                          u32 force_type, u32 force_value);
 227 void dm_init_edca_turbo(struct net_device *dev);
 228 void dm_rf_operation_test_callback(unsigned long data);
 229 void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
 230 void dm_fsync_timer_callback(unsigned long data);
 231 void dm_cck_txpower_adjust(struct net_device *dev, bool  binch14);
 232 void dm_shadow_init(struct net_device *dev);
 233 void dm_initialize_txpower_tracking(struct net_device *dev);
 234 /*--------------------------Exported Function prototype---------------------*/
 235
 236
 237 #endif  /*__R8192UDM_H__ */
 238
 239
 240 /* End of r8192U_dm.h */