drivers/spi/spi-bcm63xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Broadcom BCM63xx SPI controller support
   4  *
   5  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   6  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/completion.h>
  18 #include <linux/err.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/of.h>
  21
  22 /* BCM 6338/6348 SPI core */
  23 #define SPI_6348_RSET_SIZE              64
  24 #define SPI_6348_CMD                    0x00    /* 16-bits register */
  25 #define SPI_6348_INT_STATUS             0x02
  26 #define SPI_6348_INT_MASK_ST            0x03
  27 #define SPI_6348_INT_MASK               0x04
  28 #define SPI_6348_ST                     0x05
  29 #define SPI_6348_CLK_CFG                0x06
  30 #define SPI_6348_FILL_BYTE              0x07
  31 #define SPI_6348_MSG_TAIL               0x09
  32 #define SPI_6348_RX_TAIL                0x0b
  33 #define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
  34 #define SPI_6348_MSG_CTL_WIDTH          8
  35 #define SPI_6348_MSG_DATA               0x41
  36 #define SPI_6348_MSG_DATA_SIZE          0x3f
  37 #define SPI_6348_RX_DATA                0x80
  38 #define SPI_6348_RX_DATA_SIZE           0x3f
  39
  40 /* BCM 3368/6358/6262/6368 SPI core */
  41 #define SPI_6358_RSET_SIZE              1804
  42 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
  43 #define SPI_6358_MSG_CTL_WIDTH          16
  44 #define SPI_6358_MSG_DATA               0x02
  45 #define SPI_6358_MSG_DATA_SIZE          0x21e
  46 #define SPI_6358_RX_DATA                0x400
  47 #define SPI_6358_RX_DATA_SIZE           0x220
  48 #define SPI_6358_CMD                    0x700   /* 16-bits register */
  49 #define SPI_6358_INT_STATUS             0x702
  50 #define SPI_6358_INT_MASK_ST            0x703
  51 #define SPI_6358_INT_MASK               0x704
  52 #define SPI_6358_ST                     0x705
  53 #define SPI_6358_CLK_CFG                0x706
  54 #define SPI_6358_FILL_BYTE              0x707
  55 #define SPI_6358_MSG_TAIL               0x709
  56 #define SPI_6358_RX_TAIL                0x70B
  57
  58 /* Shared SPI definitions */
  59
  60 /* Message configuration */
  61 #define SPI_FD_RW                       0x00
  62 #define SPI_HD_W                        0x01
  63 #define SPI_HD_R                        0x02
  64 #define SPI_BYTE_CNT_SHIFT              0
  65 #define SPI_6348_MSG_TYPE_SHIFT         6
  66 #define SPI_6358_MSG_TYPE_SHIFT         14
  67
  68 /* Command */
  69 #define SPI_CMD_NOOP                    0x00
  70 #define SPI_CMD_SOFT_RESET              0x01
  71 #define SPI_CMD_HARD_RESET              0x02
  72 #define SPI_CMD_START_IMMEDIATE         0x03
  73 #define SPI_CMD_COMMAND_SHIFT           0
  74 #define SPI_CMD_COMMAND_MASK            0x000f
  75 #define SPI_CMD_DEVICE_ID_SHIFT         4
  76 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
  77 #define SPI_CMD_ONE_BYTE_SHIFT          11
  78 #define SPI_CMD_ONE_WIRE_SHIFT          12
  79 #define SPI_DEV_ID_0                    0
  80 #define SPI_DEV_ID_1                    1
  81 #define SPI_DEV_ID_2                    2
  82 #define SPI_DEV_ID_3                    3
  83
  84 /* Interrupt mask */
  85 #define SPI_INTR_CMD_DONE               0x01
  86 #define SPI_INTR_RX_OVERFLOW            0x02
  87 #define SPI_INTR_TX_UNDERFLOW           0x04
  88 #define SPI_INTR_TX_OVERFLOW            0x08
  89 #define SPI_INTR_RX_UNDERFLOW           0x10
  90 #define SPI_INTR_CLEAR_ALL              0x1f
  91
  92 /* Status */
  93 #define SPI_RX_EMPTY                    0x02
  94 #define SPI_CMD_BUSY                    0x04
  95 #define SPI_SERIAL_BUSY                 0x08
  96
  97 /* Clock configuration */
  98 #define SPI_CLK_20MHZ                   0x00
  99 #define SPI_CLK_0_391MHZ                0x01
 100 #define SPI_CLK_0_781MHZ                0x02    /* default */
 101 #define SPI_CLK_1_563MHZ                0x03
 102 #define SPI_CLK_3_125MHZ                0x04
 103 #define SPI_CLK_6_250MHZ                0x05
 104 #define SPI_CLK_12_50MHZ                0x06
 105 #define SPI_CLK_MASK                    0x07
 106 #define SPI_SSOFFTIME_MASK              0x38
 107 #define SPI_SSOFFTIME_SHIFT             3
 108 #define SPI_BYTE_SWAP                   0x80
 109
 110 enum bcm63xx_regs_spi {
 111         SPI_CMD,
 112         SPI_INT_STATUS,
 113         SPI_INT_MASK_ST,
 114         SPI_INT_MASK,
 115         SPI_ST,
 116         SPI_CLK_CFG,
 117         SPI_FILL_BYTE,
 118         SPI_MSG_TAIL,
 119         SPI_RX_TAIL,
 120         SPI_MSG_CTL,
 121         SPI_MSG_DATA,
 122         SPI_RX_DATA,
 123         SPI_MSG_TYPE_SHIFT,
 124         SPI_MSG_CTL_WIDTH,
 125         SPI_MSG_DATA_SIZE,
 126 };
 127
 128 #define BCM63XX_SPI_MAX_PREPEND         15
 129
 130 #define BCM63XX_SPI_MAX_CS              8
 131 #define BCM63XX_SPI_BUS_NUM             0
 132
 133 struct bcm63xx_spi {
 134         struct completion       done;
 135
 136         void __iomem            *regs;
 137         int                     irq;
 138
 139         /* Platform data */
 140         const unsigned long     *reg_offsets;
 141         unsigned int            fifo_size;
 142         unsigned int            msg_type_shift;
 143         unsigned int            msg_ctl_width;
 144
 145         /* data iomem */
 146         u8 __iomem              *tx_io;
 147         const u8 __iomem        *rx_io;
 148
 149         struct clk              *clk;
 150         struct platform_device  *pdev;
 151 };
 152
 153 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 154                                unsigned int offset)
 155 {
 156         return readb(bs->regs + bs->reg_offsets[offset]);
 157 }
 158
 159 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 160                                 unsigned int offset)
 161 {
 162 #ifdef CONFIG_CPU_BIG_ENDIAN
 163         return ioread16be(bs->regs + bs->reg_offsets[offset]);
 164 #else
 165         return readw(bs->regs + bs->reg_offsets[offset]);
 166 #endif
 167 }
 168
 169 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 170                                   u8 value, unsigned int offset)
 171 {
 172         writeb(value, bs->regs + bs->reg_offsets[offset]);
 173 }
 174
 175 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 176                                   u16 value, unsigned int offset)
 177 {
 178 #ifdef CONFIG_CPU_BIG_ENDIAN
 179         iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
 180 #else
 181         writew(value, bs->regs + bs->reg_offsets[offset]);
 182 #endif
 183 }
 184
 185 static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
 186         { 20000000, SPI_CLK_20MHZ },
 187         { 12500000, SPI_CLK_12_50MHZ },
 188         {  6250000, SPI_CLK_6_250MHZ },
 189         {  3125000, SPI_CLK_3_125MHZ },
 190         {  1563000, SPI_CLK_1_563MHZ },
 191         {   781000, SPI_CLK_0_781MHZ },
 192         {   391000, SPI_CLK_0_391MHZ }
 193 };
 194
 195 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 196                                       struct spi_transfer *t)
 197 {
 198         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 199         u8 clk_cfg, reg;
 200         int i;
 201
 202         /* Default to lowest clock configuration */
 203         clk_cfg = SPI_CLK_0_391MHZ;
 204
 205         /* Find the closest clock configuration */
 206         for (i = 0; i < SPI_CLK_MASK; i++) {
 207                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 208                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 209                         break;
 210                 }
 211         }
 212
 213         /* clear existing clock configuration bits of the register */
 214         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 215         reg &= ~SPI_CLK_MASK;
 216         reg |= clk_cfg;
 217
 218         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 219         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 220                 clk_cfg, t->speed_hz);
 221 }
 222
 223 /* the spi->mode bits understood by this driver: */
 224 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 225
 226 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 227                                 unsigned int num_transfers)
 228 {
 229         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 230         u16 msg_ctl;
 231         u16 cmd;
 232         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 233         struct spi_transfer *t = first;
 234         bool do_rx = false;
 235         bool do_tx = false;
 236
 237         /* Disable the CMD_DONE interrupt */
 238         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 239
 240         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 241                 t->tx_buf, t->rx_buf, t->len);
 242
 243         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 244                 prepend_len = t->len;
 245
 246         /* prepare the buffer */
 247         for (i = 0; i < num_transfers; i++) {
 248                 if (t->tx_buf) {
 249                         do_tx = true;
 250                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 251
 252                         /* don't prepend more than one tx */
 253                         if (t != first)
 254                                 prepend_len = 0;
 255                 }
 256
 257                 if (t->rx_buf) {
 258                         do_rx = true;
 259                         /* prepend is half-duplex write only */
 260                         if (t == first)
 261                                 prepend_len = 0;
 262                 }
 263
 264                 len += t->len;
 265
 266                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 267                                transfer_list);
 268         }
 269
 270         reinit_completion(&bs->done);
 271
 272         /* Fill in the Message control register */
 273         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 274
 275         if (do_rx && do_tx && prepend_len == 0)
 276                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 277         else if (do_rx)
 278                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 279         else if (do_tx)
 280                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 281
 282         switch (bs->msg_ctl_width) {
 283         case 8:
 284                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 285                 break;
 286         case 16:
 287                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 288                 break;
 289         }
 290
 291         /* Issue the transfer */
 292         cmd = SPI_CMD_START_IMMEDIATE;
 293         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 294         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 295         bcm_spi_writew(bs, cmd, SPI_CMD);
 296
 297         /* Enable the CMD_DONE interrupt */
 298         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 299
 300         timeout = wait_for_completion_timeout(&bs->done, HZ);
 301         if (!timeout)
 302                 return -ETIMEDOUT;
 303
 304         if (!do_rx)
 305                 return 0;
 306
 307         len = 0;
 308         t = first;
 309         /* Read out all the data */
 310         for (i = 0; i < num_transfers; i++) {
 311                 if (t->rx_buf)
 312                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 313
 314                 if (t != first || prepend_len == 0)
 315                         len += t->len;
 316
 317                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 318                                transfer_list);
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 325                                         struct spi_message *m)
 326 {
 327         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 328         struct spi_transfer *t, *first = NULL;
 329         struct spi_device *spi = m->spi;
 330         int status = 0;
 331         unsigned int n_transfers = 0, total_len = 0;
 332         bool can_use_prepend = false;
 333
 334         /*
 335          * This SPI controller does not support keeping CS active after a
 336          * transfer.
 337          * Work around this by merging as many transfers we can into one big
 338          * full-duplex transfers.
 339          */
 340         list_for_each_entry(t, &m->transfers, transfer_list) {
 341                 if (!first)
 342                         first = t;
 343
 344                 n_transfers++;
 345                 total_len += t->len;
 346
 347                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 348                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 349                         can_use_prepend = true;
 350                 else if (can_use_prepend && t->tx_buf)
 351                         can_use_prepend = false;
 352
 353                 /* we can only transfer one fifo worth of data */
 354                 if ((can_use_prepend &&
 355                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 356                     (!can_use_prepend && total_len > bs->fifo_size)) {
 357                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 358                                 total_len, bs->fifo_size);
 359                         status = -EINVAL;
 360                         goto exit;
 361                 }
 362
 363                 /* all combined transfers have to have the same speed */
 364                 if (t->speed_hz != first->speed_hz) {
 365                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 366                         status = -EINVAL;
 367                         goto exit;
 368                 }
 369
 370                 /* CS will be deasserted directly after transfer */
 371                 if (t->delay_usecs) {
 372                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 373                         status = -EINVAL;
 374                         goto exit;
 375                 }
 376
 377                 if (t->cs_change ||
 378                     list_is_last(&t->transfer_list, &m->transfers)) {
 379                         /* configure adapter for a new transfer */
 380                         bcm63xx_spi_setup_transfer(spi, first);
 381
 382                         /* send the data */
 383                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 384                         if (status)
 385                                 goto exit;
 386
 387                         m->actual_length += total_len;
 388
 389                         first = NULL;
 390                         n_transfers = 0;
 391                         total_len = 0;
 392                         can_use_prepend = false;
 393                 }
 394         }
 395 exit:
 396         m->status = status;
 397         spi_finalize_current_message(master);
 398
 399         return 0;
 400 }
 401
 402 /* This driver supports single master mode only. Hence
 403  * CMD_DONE is the only interrupt we care about
 404  */
 405 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 406 {
 407         struct spi_master *master = (struct spi_master *)dev_id;
 408         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 409         u8 intr;
 410
 411         /* Read interupts and clear them immediately */
 412         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 413         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 414         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 415
 416         /* A transfer completed */
 417         if (intr & SPI_INTR_CMD_DONE)
 418                 complete(&bs->done);
 419
 420         return IRQ_HANDLED;
 421 }
 422
 423 static size_t bcm63xx_spi_max_length(struct spi_device *spi)
 424 {
 425         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 426
 427         return bs->fifo_size;
 428 }
 429
 430 static const unsigned long bcm6348_spi_reg_offsets[] = {
 431         [SPI_CMD]               = SPI_6348_CMD,
 432         [SPI_INT_STATUS]        = SPI_6348_INT_STATUS,
 433         [SPI_INT_MASK_ST]       = SPI_6348_INT_MASK_ST,
 434         [SPI_INT_MASK]          = SPI_6348_INT_MASK,
 435         [SPI_ST]                = SPI_6348_ST,
 436         [SPI_CLK_CFG]           = SPI_6348_CLK_CFG,
 437         [SPI_FILL_BYTE]         = SPI_6348_FILL_BYTE,
 438         [SPI_MSG_TAIL]          = SPI_6348_MSG_TAIL,
 439         [SPI_RX_TAIL]           = SPI_6348_RX_TAIL,
 440         [SPI_MSG_CTL]           = SPI_6348_MSG_CTL,
 441         [SPI_MSG_DATA]          = SPI_6348_MSG_DATA,
 442         [SPI_RX_DATA]           = SPI_6348_RX_DATA,
 443         [SPI_MSG_TYPE_SHIFT]    = SPI_6348_MSG_TYPE_SHIFT,
 444         [SPI_MSG_CTL_WIDTH]     = SPI_6348_MSG_CTL_WIDTH,
 445         [SPI_MSG_DATA_SIZE]     = SPI_6348_MSG_DATA_SIZE,
 446 };
 447
 448 static const unsigned long bcm6358_spi_reg_offsets[] = {
 449         [SPI_CMD]               = SPI_6358_CMD,
 450         [SPI_INT_STATUS]        = SPI_6358_INT_STATUS,
 451         [SPI_INT_MASK_ST]       = SPI_6358_INT_MASK_ST,
 452         [SPI_INT_MASK]          = SPI_6358_INT_MASK,
 453         [SPI_ST]                = SPI_6358_ST,
 454         [SPI_CLK_CFG]           = SPI_6358_CLK_CFG,
 455         [SPI_FILL_BYTE]         = SPI_6358_FILL_BYTE,
 456         [SPI_MSG_TAIL]          = SPI_6358_MSG_TAIL,
 457         [SPI_RX_TAIL]           = SPI_6358_RX_TAIL,
 458         [SPI_MSG_CTL]           = SPI_6358_MSG_CTL,
 459         [SPI_MSG_DATA]          = SPI_6358_MSG_DATA,
 460         [SPI_RX_DATA]           = SPI_6358_RX_DATA,
 461         [SPI_MSG_TYPE_SHIFT]    = SPI_6358_MSG_TYPE_SHIFT,
 462         [SPI_MSG_CTL_WIDTH]     = SPI_6358_MSG_CTL_WIDTH,
 463         [SPI_MSG_DATA_SIZE]     = SPI_6358_MSG_DATA_SIZE,
 464 };
 465
 466 static const struct platform_device_id bcm63xx_spi_dev_match[] = {
 467         {
 468                 .name = "bcm6348-spi",
 469                 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
 470         },
 471         {
 472                 .name = "bcm6358-spi",
 473                 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
 474         },
 475         {
 476         },
 477 };
 478
 479 static const struct of_device_id bcm63xx_spi_of_match[] = {
 480         { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
 481         { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
 482         { },
 483 };
 484
 485 static int bcm63xx_spi_probe(struct platform_device *pdev)
 486 {
 487         struct resource *r;
 488         const unsigned long *bcm63xx_spireg;
 489         struct device *dev = &pdev->dev;
 490         int irq, bus_num;
 491         struct spi_master *master;
 492         struct clk *clk;
 493         struct bcm63xx_spi *bs;
 494         int ret;
 495         u32 num_cs = BCM63XX_SPI_MAX_CS;
 496
 497         if (dev->of_node) {
 498                 const struct of_device_id *match;
 499
 500                 match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
 501                 if (!match)
 502                         return -EINVAL;
 503                 bcm63xx_spireg = match->data;
 504
 505                 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
 506                 if (num_cs > BCM63XX_SPI_MAX_CS) {
 507                         dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
 508                                  num_cs);
 509                         num_cs = BCM63XX_SPI_MAX_CS;
 510                 }
 511
 512                 bus_num = -1;
 513         } else if (pdev->id_entry->driver_data) {
 514                 const struct platform_device_id *match = pdev->id_entry;
 515
 516                 bcm63xx_spireg = (const unsigned long *)match->driver_data;
 517                 bus_num = BCM63XX_SPI_BUS_NUM;
 518         } else {
 519                 return -EINVAL;
 520         }
 521
 522         irq = platform_get_irq(pdev, 0);
 523         if (irq < 0) {
 524                 dev_err(dev, "no irq: %d\n", irq);
 525                 return irq;
 526         }
 527
 528         clk = devm_clk_get(dev, "spi");
 529         if (IS_ERR(clk)) {
 530                 dev_err(dev, "no clock for device\n");
 531                 return PTR_ERR(clk);
 532         }
 533
 534         master = spi_alloc_master(dev, sizeof(*bs));
 535         if (!master) {
 536                 dev_err(dev, "out of memory\n");
 537                 return -ENOMEM;
 538         }
 539
 540         bs = spi_master_get_devdata(master);
 541         init_completion(&bs->done);
 542
 543         platform_set_drvdata(pdev, master);
 544         bs->pdev = pdev;
 545
 546         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 547         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 548         if (IS_ERR(bs->regs)) {
 549                 ret = PTR_ERR(bs->regs);
 550                 goto out_err;
 551         }
 552
 553         bs->irq = irq;
 554         bs->clk = clk;
 555         bs->reg_offsets = bcm63xx_spireg;
 556         bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
 557
 558         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 559                                                         pdev->name, master);
 560         if (ret) {
 561                 dev_err(dev, "unable to request irq\n");
 562                 goto out_err;
 563         }
 564
 565         master->dev.of_node = dev->of_node;
 566         master->bus_num = bus_num;
 567         master->num_chipselect = num_cs;
 568         master->transfer_one_message = bcm63xx_spi_transfer_one;
 569         master->mode_bits = MODEBITS;
 570         master->bits_per_word_mask = SPI_BPW_MASK(8);
 571         master->max_transfer_size = bcm63xx_spi_max_length;
 572         master->max_message_size = bcm63xx_spi_max_length;
 573         master->auto_runtime_pm = true;
 574         bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
 575         bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
 576         bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
 577         bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
 578
 579         /* Initialize hardware */
 580         ret = clk_prepare_enable(bs->clk);
 581         if (ret)
 582                 goto out_err;
 583
 584         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 585
 586         /* register and we are done */
 587         ret = devm_spi_register_master(dev, master);
 588         if (ret) {
 589                 dev_err(dev, "spi register failed\n");
 590                 goto out_clk_disable;
 591         }
 592
 593         dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
 594                  r, irq, bs->fifo_size);
 595
 596         return 0;
 597
 598 out_clk_disable:
 599         clk_disable_unprepare(clk);
 600 out_err:
 601         spi_master_put(master);
 602         return ret;
 603 }
 604
 605 static int bcm63xx_spi_remove(struct platform_device *pdev)
 606 {
 607         struct spi_master *master = platform_get_drvdata(pdev);
 608         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 609
 610         /* reset spi block */
 611         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 612
 613         /* HW shutdown */
 614         clk_disable_unprepare(bs->clk);
 615
 616         return 0;
 617 }
 618
 619 #ifdef CONFIG_PM_SLEEP
 620 static int bcm63xx_spi_suspend(struct device *dev)
 621 {
 622         struct spi_master *master = dev_get_drvdata(dev);
 623         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 624
 625         spi_master_suspend(master);
 626
 627         clk_disable_unprepare(bs->clk);
 628
 629         return 0;
 630 }
 631
 632 static int bcm63xx_spi_resume(struct device *dev)
 633 {
 634         struct spi_master *master = dev_get_drvdata(dev);
 635         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 636         int ret;
 637
 638         ret = clk_prepare_enable(bs->clk);
 639         if (ret)
 640                 return ret;
 641
 642         spi_master_resume(master);
 643
 644         return 0;
 645 }
 646 #endif
 647
 648 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 649         SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
 650 };
 651
 652 static struct platform_driver bcm63xx_spi_driver = {
 653         .driver = {
 654                 .name   = "bcm63xx-spi",
 655                 .pm     = &bcm63xx_spi_pm_ops,
 656                 .of_match_table = bcm63xx_spi_of_match,
 657         },
 658         .id_table       = bcm63xx_spi_dev_match,
 659         .probe          = bcm63xx_spi_probe,
 660         .remove         = bcm63xx_spi_remove,
 661 };
 662
 663 module_platform_driver(bcm63xx_spi_driver);
 664
 665 MODULE_ALIAS("platform:bcm63xx_spi");
 666 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 667 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 668 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 669 MODULE_LICENSE("GPL");