drivers/pinctrl/intel/pinctrl-jasperlake.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Jasper Lake PCH pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2020, Intel Corporation
   6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  */
   8
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12
  13 #include <linux/pinctrl/pinctrl.h>
  14
  15 #include "pinctrl-intel.h"
  16
  17 #define JSL_PAD_OWN     0x020
  18 #define JSL_PADCFGLOCK  0x080
  19 #define JSL_HOSTSW_OWN  0x0c0
  20 #define JSL_GPI_IS      0x100
  21 #define JSL_GPI_IE      0x120
  22
  23 #define JSL_GPP(r, s, e, g)                             \
  24         {                                               \
  25                 .reg_num = (r),                         \
  26                 .base = (s),                            \
  27                 .size = ((e) - (s) + 1),                \
  28                 .gpio_base = (g),                       \
  29         }
  30
  31 #define JSL_COMMUNITY(b, s, e, g)                       \
  32         {                                               \
  33                 .barno = (b),                           \
  34                 .padown_offset = JSL_PAD_OWN,           \
  35                 .padcfglock_offset = JSL_PADCFGLOCK,    \
  36                 .hostown_offset = JSL_HOSTSW_OWN,       \
  37                 .is_offset = JSL_GPI_IS,                \
  38                 .ie_offset = JSL_GPI_IE,                \
  39                 .pin_base = (s),                        \
  40                 .npins = ((e) - (s) + 1),               \
  41                 .gpps = (g),                            \
  42                 .ngpps = ARRAY_SIZE(g),                 \
  43         }
  44
  45 /* Jasper Lake */
  46 static const struct pinctrl_pin_desc jsl_pins[] = {
  47         /* GPP_F */
  48         PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
  49         PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
  50         PINCTRL_PIN(2, "EMMC_HIP_MON"),
  51         PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
  52         PINCTRL_PIN(4, "CNV_RF_RESET_B"),
  53         PINCTRL_PIN(5, "MODEM_CLKREQ"),
  54         PINCTRL_PIN(6, "CNV_PA_BLANKING"),
  55         PINCTRL_PIN(7, "EMMC_CMD"),
  56         PINCTRL_PIN(8, "EMMC_DATA0"),
  57         PINCTRL_PIN(9, "EMMC_DATA1"),
  58         PINCTRL_PIN(10, "EMMC_DATA2"),
  59         PINCTRL_PIN(11, "EMMC_DATA3"),
  60         PINCTRL_PIN(12, "EMMC_DATA4"),
  61         PINCTRL_PIN(13, "EMMC_DATA5"),
  62         PINCTRL_PIN(14, "EMMC_DATA6"),
  63         PINCTRL_PIN(15, "EMMC_DATA7"),
  64         PINCTRL_PIN(16, "EMMC_RCLK"),
  65         PINCTRL_PIN(17, "EMMC_CLK"),
  66         PINCTRL_PIN(18, "EMMC_RESETB"),
  67         PINCTRL_PIN(19, "A4WP_PRESENT"),
  68         /* SPI */
  69         PINCTRL_PIN(20, "SPI0_IO_2"),
  70         PINCTRL_PIN(21, "SPI0_IO_3"),
  71         PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
  72         PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
  73         PINCTRL_PIN(24, "SPI0_TPM_CSB"),
  74         PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
  75         PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
  76         PINCTRL_PIN(27, "SPI0_CLK"),
  77         PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
  78         /* GPP_B */
  79         PINCTRL_PIN(29, "CORE_VID_0"),
  80         PINCTRL_PIN(30, "CORE_VID_1"),
  81         PINCTRL_PIN(31, "VRALERTB"),
  82         PINCTRL_PIN(32, "CPU_GP_2"),
  83         PINCTRL_PIN(33, "CPU_GP_3"),
  84         PINCTRL_PIN(34, "SRCCLKREQB_0"),
  85         PINCTRL_PIN(35, "SRCCLKREQB_1"),
  86         PINCTRL_PIN(36, "SRCCLKREQB_2"),
  87         PINCTRL_PIN(37, "SRCCLKREQB_3"),
  88         PINCTRL_PIN(38, "SRCCLKREQB_4"),
  89         PINCTRL_PIN(39, "SRCCLKREQB_5"),
  90         PINCTRL_PIN(40, "PMCALERTB"),
  91         PINCTRL_PIN(41, "SLP_S0B"),
  92         PINCTRL_PIN(42, "PLTRSTB"),
  93         PINCTRL_PIN(43, "SPKR"),
  94         PINCTRL_PIN(44, "GSPI0_CS0B"),
  95         PINCTRL_PIN(45, "GSPI0_CLK"),
  96         PINCTRL_PIN(46, "GSPI0_MISO"),
  97         PINCTRL_PIN(47, "GSPI0_MOSI"),
  98         PINCTRL_PIN(48, "GSPI1_CS0B"),
  99         PINCTRL_PIN(49, "GSPI1_CLK"),
 100         PINCTRL_PIN(50, "GSPI1_MISO"),
 101         PINCTRL_PIN(51, "GSPI1_MOSI"),
 102         PINCTRL_PIN(52, "DDSP_HPD_A"),
 103         PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
 104         PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
 105         /* GPP_A */
 106         PINCTRL_PIN(55, "ESPI_IO_0"),
 107         PINCTRL_PIN(56, "ESPI_IO_1"),
 108         PINCTRL_PIN(57, "ESPI_IO_2"),
 109         PINCTRL_PIN(58, "ESPI_IO_3"),
 110         PINCTRL_PIN(59, "ESPI_CSB"),
 111         PINCTRL_PIN(60, "ESPI_CLK"),
 112         PINCTRL_PIN(61, "ESPI_RESETB"),
 113         PINCTRL_PIN(62, "SMBCLK"),
 114         PINCTRL_PIN(63, "SMBDATA"),
 115         PINCTRL_PIN(64, "SMBALERTB"),
 116         PINCTRL_PIN(65, "CPU_GP_0"),
 117         PINCTRL_PIN(66, "CPU_GP_1"),
 118         PINCTRL_PIN(67, "USB2_OCB_1"),
 119         PINCTRL_PIN(68, "USB2_OCB_2"),
 120         PINCTRL_PIN(69, "USB2_OCB_3"),
 121         PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"),
 122         PINCTRL_PIN(71, "DDSP_HPD_B"),
 123         PINCTRL_PIN(72, "DDSP_HPD_C"),
 124         PINCTRL_PIN(73, "USB2_OCB_0"),
 125         PINCTRL_PIN(74, "PCHHOTB"),
 126         PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"),
 127         /* GPP_S */
 128         PINCTRL_PIN(76, "SNDW1_CLK"),
 129         PINCTRL_PIN(77, "SNDW1_DATA"),
 130         PINCTRL_PIN(78, "SNDW2_CLK"),
 131         PINCTRL_PIN(79, "SNDW2_DATA"),
 132         PINCTRL_PIN(80, "SNDW1_CLK"),
 133         PINCTRL_PIN(81, "SNDW1_DATA"),
 134         PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"),
 135         PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"),
 136         /* GPP_R */
 137         PINCTRL_PIN(84, "HDA_BCLK"),
 138         PINCTRL_PIN(85, "HDA_SYNC"),
 139         PINCTRL_PIN(86, "HDA_SDO"),
 140         PINCTRL_PIN(87, "HDA_SDI_0"),
 141         PINCTRL_PIN(88, "HDA_RSTB"),
 142         PINCTRL_PIN(89, "HDA_SDI_1"),
 143         PINCTRL_PIN(90, "I2S1_SFRM"),
 144         PINCTRL_PIN(91, "I2S1_TXD"),
 145         /* GPP_H */
 146         PINCTRL_PIN(92, "GPPC_H_0"),
 147         PINCTRL_PIN(93, "SD_PWR_EN_B"),
 148         PINCTRL_PIN(94, "MODEM_CLKREQ"),
 149         PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"),
 150         PINCTRL_PIN(96, "I2C2_SDA"),
 151         PINCTRL_PIN(97, "I2C2_SCL"),
 152         PINCTRL_PIN(98, "I2C3_SDA"),
 153         PINCTRL_PIN(99, "I2C3_SCL"),
 154         PINCTRL_PIN(100, "I2C4_SDA"),
 155         PINCTRL_PIN(101, "I2C4_SCL"),
 156         PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"),
 157         PINCTRL_PIN(103, "I2S2_SCLK"),
 158         PINCTRL_PIN(104, "I2S2_SFRM"),
 159         PINCTRL_PIN(105, "I2S2_TXD"),
 160         PINCTRL_PIN(106, "I2S2_RXD"),
 161         PINCTRL_PIN(107, "I2S1_SCLK"),
 162         PINCTRL_PIN(108, "GPPC_H_16"),
 163         PINCTRL_PIN(109, "GPPC_H_17"),
 164         PINCTRL_PIN(110, "GPPC_H_18"),
 165         PINCTRL_PIN(111, "GPPC_H_19"),
 166         PINCTRL_PIN(112, "GPPC_H_20"),
 167         PINCTRL_PIN(113, "GPPC_H_21"),
 168         PINCTRL_PIN(114, "GPPC_H_22"),
 169         PINCTRL_PIN(115, "GPPC_H_23"),
 170         /* GPP_D */
 171         PINCTRL_PIN(116, "SPI1_CSB"),
 172         PINCTRL_PIN(117, "SPI1_CLK"),
 173         PINCTRL_PIN(118, "SPI1_MISO_IO_1"),
 174         PINCTRL_PIN(119, "SPI1_MOSI_IO_0"),
 175         PINCTRL_PIN(120, "ISH_I2C0_SDA"),
 176         PINCTRL_PIN(121, "ISH_I2C0_SCL"),
 177         PINCTRL_PIN(122, "ISH_I2C1_SDA"),
 178         PINCTRL_PIN(123, "ISH_I2C1_SCL"),
 179         PINCTRL_PIN(124, "ISH_SPI_CSB"),
 180         PINCTRL_PIN(125, "ISH_SPI_CLK"),
 181         PINCTRL_PIN(126, "ISH_SPI_MISO"),
 182         PINCTRL_PIN(127, "ISH_SPI_MOSI"),
 183         PINCTRL_PIN(128, "ISH_UART0_RXD"),
 184         PINCTRL_PIN(129, "ISH_UART0_TXD"),
 185         PINCTRL_PIN(130, "ISH_UART0_RTSB"),
 186         PINCTRL_PIN(131, "ISH_UART0_CTSB"),
 187         PINCTRL_PIN(132, "SPI1_IO_2"),
 188         PINCTRL_PIN(133, "SPI1_IO_3"),
 189         PINCTRL_PIN(134, "I2S_MCLK"),
 190         PINCTRL_PIN(135, "CNV_MFUART2_RXD"),
 191         PINCTRL_PIN(136, "CNV_MFUART2_TXD"),
 192         PINCTRL_PIN(137, "CNV_PA_BLANKING"),
 193         PINCTRL_PIN(138, "I2C5_SDA"),
 194         PINCTRL_PIN(139, "I2C5_SCL"),
 195         PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"),
 196         PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"),
 197         /* vGPIO */
 198         PINCTRL_PIN(142, "CNV_BTEN"),
 199         PINCTRL_PIN(143, "CNV_WCEN"),
 200         PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"),
 201         PINCTRL_PIN(145, "CNV_BT_IF_SELECT"),
 202         PINCTRL_PIN(146, "vCNV_BT_UART_TXD"),
 203         PINCTRL_PIN(147, "vCNV_BT_UART_RXD"),
 204         PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"),
 205         PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"),
 206         PINCTRL_PIN(150, "vCNV_MFUART1_TXD"),
 207         PINCTRL_PIN(151, "vCNV_MFUART1_RXD"),
 208         PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"),
 209         PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"),
 210         PINCTRL_PIN(154, "vUART0_TXD"),
 211         PINCTRL_PIN(155, "vUART0_RXD"),
 212         PINCTRL_PIN(156, "vUART0_CTS_B"),
 213         PINCTRL_PIN(157, "vUART0_RTS_B"),
 214         PINCTRL_PIN(158, "vISH_UART0_TXD"),
 215         PINCTRL_PIN(159, "vISH_UART0_RXD"),
 216         PINCTRL_PIN(160, "vISH_UART0_CTS_B"),
 217         PINCTRL_PIN(161, "vISH_UART0_RTS_B"),
 218         PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"),
 219         PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"),
 220         PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"),
 221         PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"),
 222         PINCTRL_PIN(166, "vI2S2_SCLK"),
 223         PINCTRL_PIN(167, "vI2S2_SFRM"),
 224         PINCTRL_PIN(168, "vI2S2_TXD"),
 225         PINCTRL_PIN(169, "vI2S2_RXD"),
 226         PINCTRL_PIN(170, "vSD3_CD_B"),
 227         /* GPP_C */
 228         PINCTRL_PIN(171, "GPPC_C_0"),
 229         PINCTRL_PIN(172, "GPPC_C_1"),
 230         PINCTRL_PIN(173, "GPPC_C_2"),
 231         PINCTRL_PIN(174, "GPPC_C_3"),
 232         PINCTRL_PIN(175, "GPPC_C_4"),
 233         PINCTRL_PIN(176, "GPPC_C_5"),
 234         PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"),
 235         PINCTRL_PIN(178, "SUSACKB"),
 236         PINCTRL_PIN(179, "UART0_RXD"),
 237         PINCTRL_PIN(180, "UART0_TXD"),
 238         PINCTRL_PIN(181, "UART0_RTSB"),
 239         PINCTRL_PIN(182, "UART0_CTSB"),
 240         PINCTRL_PIN(183, "UART1_RXD"),
 241         PINCTRL_PIN(184, "UART1_TXD"),
 242         PINCTRL_PIN(185, "UART1_RTSB"),
 243         PINCTRL_PIN(186, "UART1_CTSB"),
 244         PINCTRL_PIN(187, "I2C0_SDA"),
 245         PINCTRL_PIN(188, "I2C0_SCL"),
 246         PINCTRL_PIN(189, "I2C1_SDA"),
 247         PINCTRL_PIN(190, "I2C1_SCL"),
 248         PINCTRL_PIN(191, "UART2_RXD"),
 249         PINCTRL_PIN(192, "UART2_TXD"),
 250         PINCTRL_PIN(193, "UART2_RTSB"),
 251         PINCTRL_PIN(194, "UART2_CTSB"),
 252         /* HVCMOS */
 253         PINCTRL_PIN(195, "L_BKLTEN"),
 254         PINCTRL_PIN(196, "L_BKLTCTL"),
 255         PINCTRL_PIN(197, "L_VDDEN"),
 256         PINCTRL_PIN(198, "SYS_PWROK"),
 257         PINCTRL_PIN(199, "SYS_RESETB"),
 258         PINCTRL_PIN(200, "MLK_RSTB"),
 259         /* GPP_E */
 260         PINCTRL_PIN(201, "ISH_GP_0"),
 261         PINCTRL_PIN(202, "ISH_GP_1"),
 262         PINCTRL_PIN(203, "IMGCLKOUT_1"),
 263         PINCTRL_PIN(204, "ISH_GP_2"),
 264         PINCTRL_PIN(205, "IMGCLKOUT_2"),
 265         PINCTRL_PIN(206, "SATA_LEDB"),
 266         PINCTRL_PIN(207, "IMGCLKOUT_3"),
 267         PINCTRL_PIN(208, "ISH_GP_3"),
 268         PINCTRL_PIN(209, "ISH_GP_4"),
 269         PINCTRL_PIN(210, "ISH_GP_5"),
 270         PINCTRL_PIN(211, "ISH_GP_6"),
 271         PINCTRL_PIN(212, "ISH_GP_7"),
 272         PINCTRL_PIN(213, "IMGCLKOUT_4"),
 273         PINCTRL_PIN(214, "DDPA_CTRLCLK"),
 274         PINCTRL_PIN(215, "DDPA_CTRLDATA"),
 275         PINCTRL_PIN(216, "DDPB_CTRLCLK"),
 276         PINCTRL_PIN(217, "DDPB_CTRLDATA"),
 277         PINCTRL_PIN(218, "DDPC_CTRLCLK"),
 278         PINCTRL_PIN(219, "DDPC_CTRLDATA"),
 279         PINCTRL_PIN(220, "IMGCLKOUT_5"),
 280         PINCTRL_PIN(221, "CNV_BRI_DT"),
 281         PINCTRL_PIN(222, "CNV_BRI_RSP"),
 282         PINCTRL_PIN(223, "CNV_RGI_DT"),
 283         PINCTRL_PIN(224, "CNV_RGI_RSP"),
 284         /* GPP_G */
 285         PINCTRL_PIN(225, "SD3_CMD"),
 286         PINCTRL_PIN(226, "SD3_D0"),
 287         PINCTRL_PIN(227, "SD3_D1"),
 288         PINCTRL_PIN(228, "SD3_D2"),
 289         PINCTRL_PIN(229, "SD3_D3"),
 290         PINCTRL_PIN(230, "SD3_CDB"),
 291         PINCTRL_PIN(231, "SD3_CLK"),
 292         PINCTRL_PIN(232, "SD3_WP"),
 293 };
 294
 295 static const struct intel_padgroup jsl_community0_gpps[] = {
 296         JSL_GPP(0, 0, 19, 320),                         /* GPP_F */
 297         JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP),      /* SPI */
 298         JSL_GPP(2, 29, 54, 32),                         /* GPP_B */
 299         JSL_GPP(3, 55, 75, 64),                         /* GPP_A */
 300         JSL_GPP(4, 76, 83, 96),                         /* GPP_S */
 301         JSL_GPP(5, 84, 91, 128),                        /* GPP_R */
 302 };
 303
 304 static const struct intel_padgroup jsl_community1_gpps[] = {
 305         JSL_GPP(0, 92, 115, 160),                       /* GPP_H */
 306         JSL_GPP(1, 116, 141, 192),                      /* GPP_D */
 307         JSL_GPP(2, 142, 170, 224),                      /* vGPIO */
 308         JSL_GPP(3, 171, 194, 256),                      /* GPP_C */
 309 };
 310
 311 static const struct intel_padgroup jsl_community4_gpps[] = {
 312         JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP),    /* HVCMOS */
 313         JSL_GPP(1, 201, 224, 288),                      /* GPP_E */
 314 };
 315
 316 static const struct intel_padgroup jsl_community5_gpps[] = {
 317         JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO),     /* GPP_G */
 318 };
 319
 320 static const struct intel_community jsl_communities[] = {
 321         JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps),
 322         JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps),
 323         JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps),
 324         JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps),
 325 };
 326
 327 static const struct intel_pinctrl_soc_data jsl_soc_data = {
 328         .pins = jsl_pins,
 329         .npins = ARRAY_SIZE(jsl_pins),
 330         .communities = jsl_communities,
 331         .ncommunities = ARRAY_SIZE(jsl_communities),
 332 };
 333
 334 static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
 335         { "INT34C8", (kernel_ulong_t)&jsl_soc_data },
 336         { }
 337 };
 338 MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
 339
 340 static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
 341
 342 static struct platform_driver jsl_pinctrl_driver = {
 343         .probe = intel_pinctrl_probe_by_hid,
 344         .driver = {
 345                 .name = "jasperlake-pinctrl",
 346                 .acpi_match_table = jsl_pinctrl_acpi_match,
 347                 .pm = &jsl_pinctrl_pm_ops,
 348         },
 349 };
 350 module_platform_driver(jsl_pinctrl_driver);
 351
 352 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 353 MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver");
 354 MODULE_LICENSE("GPL v2");