1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
41 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
46 u32 l0s; /* L0s latency (nsec) */
47 u32 l1; /* L1 latency (nsec) */
50 struct pcie_link_state {
51 struct pci_dev *pdev; /* Upstream component of the Link */
52 struct pci_dev *downstream; /* Downstream component, function 0 */
53 struct pcie_link_state *root; /* pointer to the root port link */
54 struct pcie_link_state *parent; /* pointer to the parent Link state */
55 struct list_head sibling; /* node in link_list */
58 u32 aspm_support:7; /* Supported ASPM state */
59 u32 aspm_enabled:7; /* Enabled ASPM state */
60 u32 aspm_capable:7; /* Capable ASPM state with latency */
61 u32 aspm_default:7; /* Default ASPM state by BIOS */
62 u32 aspm_disable:7; /* Disabled ASPM state */
65 u32 clkpm_capable:1; /* Clock PM capable? */
66 u32 clkpm_enabled:1; /* Current Clock PM state */
67 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
70 struct aspm_latency latency_up; /* Upstream direction exit latency */
71 struct aspm_latency latency_dw; /* Downstream direction exit latency */
73 * Endpoint acceptable latencies. A pcie downstream port only
74 * has one slot under it, so at most there are 8 functions.
76 struct aspm_latency acceptable[8];
78 /* L1 PM Substate info */
80 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
81 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
82 u32 ctl1; /* value to be programmed in ctl1 */
83 u32 ctl2; /* value to be programmed in ctl2 */
87 static int aspm_disabled, aspm_force;
88 static bool aspm_support_enabled = true;
89 static DEFINE_MUTEX(aspm_lock);
90 static LIST_HEAD(link_list);
92 #define POLICY_DEFAULT 0 /* BIOS default setting */
93 #define POLICY_PERFORMANCE 1 /* high performance */
94 #define POLICY_POWERSAVE 2 /* high power saving */
95 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
97 #ifdef CONFIG_PCIEASPM_PERFORMANCE
98 static int aspm_policy = POLICY_PERFORMANCE;
99 #elif defined CONFIG_PCIEASPM_POWERSAVE
100 static int aspm_policy = POLICY_POWERSAVE;
101 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
102 static int aspm_policy = POLICY_POWER_SUPERSAVE;
104 static int aspm_policy;
107 static const char *policy_str[] = {
108 [POLICY_DEFAULT] = "default",
109 [POLICY_PERFORMANCE] = "performance",
110 [POLICY_POWERSAVE] = "powersave",
111 [POLICY_POWER_SUPERSAVE] = "powersupersave"
114 #define LINK_RETRAIN_TIMEOUT HZ
116 static int policy_to_aspm_state(struct pcie_link_state *link)
118 switch (aspm_policy) {
119 case POLICY_PERFORMANCE:
120 /* Disable ASPM and Clock PM */
122 case POLICY_POWERSAVE:
123 /* Enable ASPM L0s/L1 */
124 return (ASPM_STATE_L0S | ASPM_STATE_L1);
125 case POLICY_POWER_SUPERSAVE:
126 /* Enable Everything */
127 return ASPM_STATE_ALL;
129 return link->aspm_default;
134 static int policy_to_clkpm_state(struct pcie_link_state *link)
136 switch (aspm_policy) {
137 case POLICY_PERFORMANCE:
138 /* Disable ASPM and Clock PM */
140 case POLICY_POWERSAVE:
141 case POLICY_POWER_SUPERSAVE:
142 /* Enable Clock PM */
145 return link->clkpm_default;
150 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
152 struct pci_dev *child;
153 struct pci_bus *linkbus = link->pdev->subordinate;
154 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
156 list_for_each_entry(child, &linkbus->devices, bus_list)
157 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
158 PCI_EXP_LNKCTL_CLKREQ_EN,
160 link->clkpm_enabled = !!enable;
163 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
165 /* Don't enable Clock PM if the link is not Clock PM capable */
166 if (!link->clkpm_capable)
168 /* Need nothing if the specified equals to current state */
169 if (link->clkpm_enabled == enable)
171 pcie_set_clkpm_nocheck(link, enable);
174 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
176 int capable = 1, enabled = 1;
179 struct pci_dev *child;
180 struct pci_bus *linkbus = link->pdev->subordinate;
182 /* All functions should have the same cap and state, take the worst */
183 list_for_each_entry(child, &linkbus->devices, bus_list) {
184 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
185 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
190 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
191 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
194 link->clkpm_enabled = enabled;
195 link->clkpm_default = enabled;
196 link->clkpm_capable = (blacklist) ? 0 : capable;
200 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
201 * could use common clock. If they are, configure them to use the
202 * common clock. That will reduce the ASPM state exit latency.
204 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
207 u16 reg16, parent_reg, child_reg[8];
208 unsigned long start_jiffies;
209 struct pci_dev *child, *parent = link->pdev;
210 struct pci_bus *linkbus = parent->subordinate;
212 * All functions of a slot should have the same Slot Clock
213 * Configuration, so just check one function
215 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
216 BUG_ON(!pci_is_pcie(child));
218 /* Check downstream component if bit Slot Clock Configuration is 1 */
219 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
220 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
223 /* Check upstream component if bit Slot Clock Configuration is 1 */
224 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
225 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
228 /* Port might be already in common clock mode */
229 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
230 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
231 bool consistent = true;
233 list_for_each_entry(child, &linkbus->devices, bus_list) {
234 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
236 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
243 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
246 /* Configure downstream component, all functions */
247 list_for_each_entry(child, &linkbus->devices, bus_list) {
248 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
249 child_reg[PCI_FUNC(child->devfn)] = reg16;
251 reg16 |= PCI_EXP_LNKCTL_CCC;
253 reg16 &= ~PCI_EXP_LNKCTL_CCC;
254 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
257 /* Configure upstream component */
258 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
261 reg16 |= PCI_EXP_LNKCTL_CCC;
263 reg16 &= ~PCI_EXP_LNKCTL_CCC;
264 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
267 reg16 |= PCI_EXP_LNKCTL_RL;
268 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
270 /* Wait for link training end. Break out after waiting for timeout */
271 start_jiffies = jiffies;
273 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
274 if (!(reg16 & PCI_EXP_LNKSTA_LT))
276 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
280 if (!(reg16 & PCI_EXP_LNKSTA_LT))
283 /* Training failed. Restore common clock configurations */
284 pci_err(parent, "ASPM: Could not configure common clock\n");
285 list_for_each_entry(child, &linkbus->devices, bus_list)
286 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
287 child_reg[PCI_FUNC(child->devfn)]);
288 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
291 /* Convert L0s latency encoding to ns */
292 static u32 calc_l0s_latency(u32 encoding)
295 return (5 * 1000); /* > 4us */
296 return (64 << encoding);
299 /* Convert L0s acceptable latency encoding to ns */
300 static u32 calc_l0s_acceptable(u32 encoding)
304 return (64 << encoding);
307 /* Convert L1 latency encoding to ns */
308 static u32 calc_l1_latency(u32 encoding)
311 return (65 * 1000); /* > 64us */
312 return (1000 << encoding);
315 /* Convert L1 acceptable latency encoding to ns */
316 static u32 calc_l1_acceptable(u32 encoding)
320 return (1000 << encoding);
323 /* Convert L1SS T_pwr encoding to usec */
324 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
334 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
338 static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
340 u32 threshold_ns = threshold_us * 1000;
342 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
343 if (threshold_ns < 32) {
345 *value = threshold_ns;
346 } else if (threshold_ns < 1024) {
348 *value = threshold_ns >> 5;
349 } else if (threshold_ns < 32768) {
351 *value = threshold_ns >> 10;
352 } else if (threshold_ns < 1048576) {
354 *value = threshold_ns >> 15;
355 } else if (threshold_ns < 33554432) {
357 *value = threshold_ns >> 20;
360 *value = threshold_ns >> 25;
364 struct aspm_register_info {
367 u32 latency_encoding_l0s;
368 u32 latency_encoding_l1;
377 static void pcie_get_aspm_reg(struct pci_dev *pdev,
378 struct aspm_register_info *info)
383 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
384 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
385 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
386 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
387 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
388 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
390 /* Read L1 PM substate capabilities */
391 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
392 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
393 if (!info->l1ss_cap_ptr)
395 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
397 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
403 * If we don't have LTR for the entire path from the Root Complex
404 * to this device, we can't use ASPM L1.2 because it relies on the
405 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
408 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
410 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
412 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
416 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
418 u32 latency, l1_switch_latency = 0;
419 struct aspm_latency *acceptable;
420 struct pcie_link_state *link;
422 /* Device not in D0 doesn't need latency check */
423 if ((endpoint->current_state != PCI_D0) &&
424 (endpoint->current_state != PCI_UNKNOWN))
427 link = endpoint->bus->self->link_state;
428 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
431 /* Check upstream direction L0s latency */
432 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
433 (link->latency_up.l0s > acceptable->l0s))
434 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
436 /* Check downstream direction L0s latency */
437 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
438 (link->latency_dw.l0s > acceptable->l0s))
439 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
442 * Every switch on the path to root complex need 1
443 * more microsecond for L1. Spec doesn't mention L0s.
445 * The exit latencies for L1 substates are not advertised
446 * by a device. Since the spec also doesn't mention a way
447 * to determine max latencies introduced by enabling L1
448 * substates on the components, it is not clear how to do
449 * a L1 substate exit latency check. We assume that the
450 * L1 exit latencies advertised by a device include L1
451 * substate latencies (and hence do not do any check).
453 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
454 if ((link->aspm_capable & ASPM_STATE_L1) &&
455 (latency + l1_switch_latency > acceptable->l1))
456 link->aspm_capable &= ~ASPM_STATE_L1;
457 l1_switch_latency += 1000;
464 * The L1 PM substate capability is only implemented in function 0 in a
465 * multi function device.
467 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
469 struct pci_dev *child;
471 list_for_each_entry(child, &linkbus->devices, bus_list)
472 if (PCI_FUNC(child->devfn) == 0)
477 /* Calculate L1.2 PM substate timing parameters */
478 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
479 struct aspm_register_info *upreg,
480 struct aspm_register_info *dwreg)
482 u32 val1, val2, scale1, scale2;
483 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
485 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
486 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
487 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
489 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
492 /* Choose the greater of the two Port Common_Mode_Restore_Times */
493 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
494 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
495 t_common_mode = max(val1, val2);
497 /* Choose the greater of the two Port T_POWER_ON times */
498 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
499 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
500 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
501 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
503 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
504 calc_l1ss_pwron(link->downstream, scale2, val2)) {
505 link->l1ss.ctl2 |= scale1 | (val1 << 3);
506 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
508 link->l1ss.ctl2 |= scale2 | (val2 << 3);
509 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
513 * Set LTR_L1.2_THRESHOLD to the time required to transition the
514 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
515 * downstream devices report (via LTR) that they can tolerate at
516 * least that much latency.
518 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
519 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
522 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
523 encode_l12_threshold(l1_2_threshold, &scale, &value);
524 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
527 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
529 struct pci_dev *child = link->downstream, *parent = link->pdev;
530 struct pci_bus *linkbus = parent->subordinate;
531 struct aspm_register_info upreg, dwreg;
534 /* Set enabled/disable so that we will disable ASPM later */
535 link->aspm_enabled = ASPM_STATE_ALL;
536 link->aspm_disable = ASPM_STATE_ALL;
540 /* Get upstream/downstream components' register state */
541 pcie_get_aspm_reg(parent, &upreg);
542 pcie_get_aspm_reg(child, &dwreg);
545 * If ASPM not supported, don't mess with the clocks and link,
548 if (!(upreg.support & dwreg.support))
551 /* Configure common clock before checking latencies */
552 pcie_aspm_configure_common_clock(link);
555 * Re-read upstream/downstream components' register state
556 * after clock configuration
558 pcie_get_aspm_reg(parent, &upreg);
559 pcie_get_aspm_reg(child, &dwreg);
564 * Note that we must not enable L0s in either direction on a
565 * given link unless components on both sides of the link each
568 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
569 link->aspm_support |= ASPM_STATE_L0S;
570 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
571 link->aspm_enabled |= ASPM_STATE_L0S_UP;
572 if (upreg.enabled & PCIE_LINK_STATE_L0S)
573 link->aspm_enabled |= ASPM_STATE_L0S_DW;
574 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
575 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
578 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
579 link->aspm_support |= ASPM_STATE_L1;
580 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
581 link->aspm_enabled |= ASPM_STATE_L1;
582 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
583 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
585 /* Setup L1 substate */
586 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
587 link->aspm_support |= ASPM_STATE_L1_1;
588 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
589 link->aspm_support |= ASPM_STATE_L1_2;
590 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
591 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
592 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
593 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
595 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
596 link->aspm_enabled |= ASPM_STATE_L1_1;
597 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
598 link->aspm_enabled |= ASPM_STATE_L1_2;
599 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
600 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
601 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
602 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
604 if (link->aspm_support & ASPM_STATE_L1SS)
605 aspm_calc_l1ss_info(link, &upreg, &dwreg);
607 /* Save default state */
608 link->aspm_default = link->aspm_enabled;
610 /* Setup initial capable state. Will be updated later */
611 link->aspm_capable = link->aspm_support;
613 * If the downstream component has pci bridge function, don't
616 list_for_each_entry(child, &linkbus->devices, bus_list) {
617 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
618 link->aspm_disable = ASPM_STATE_ALL;
623 /* Get and check endpoint acceptable latencies */
624 list_for_each_entry(child, &linkbus->devices, bus_list) {
626 struct aspm_latency *acceptable =
627 &link->acceptable[PCI_FUNC(child->devfn)];
629 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
630 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
633 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
634 /* Calculate endpoint L0s acceptable latency */
635 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
636 acceptable->l0s = calc_l0s_acceptable(encoding);
637 /* Calculate endpoint L1 acceptable latency */
638 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
639 acceptable->l1 = calc_l1_acceptable(encoding);
641 pcie_aspm_check_latency(child);
645 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
650 pci_read_config_dword(pdev, pos, &val);
653 pci_write_config_dword(pdev, pos, val);
656 /* Configure the ASPM L1 substates */
657 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
660 struct pci_dev *child = link->downstream, *parent = link->pdev;
661 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
662 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
664 enable_req = (link->aspm_enabled ^ state) & state;
667 * Here are the rules specified in the PCIe spec for enabling L1SS:
668 * - When enabling L1.x, enable bit at parent first, then at child
669 * - When disabling L1.x, disable bit at child first, then at parent
670 * - When enabling ASPM L1.x, need to disable L1
671 * (at child followed by parent).
672 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
675 * To keep it simple, disable all L1SS bits first, and later enable
679 /* Disable all L1 substates */
680 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
681 PCI_L1SS_CTL1_L1SS_MASK, 0);
682 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
683 PCI_L1SS_CTL1_L1SS_MASK, 0);
685 * If needed, disable L1, and it gets enabled later
686 * in pcie_config_aspm_link().
688 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
689 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
690 PCI_EXP_LNKCTL_ASPM_L1, 0);
691 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
692 PCI_EXP_LNKCTL_ASPM_L1, 0);
695 if (enable_req & ASPM_STATE_L1_2_MASK) {
697 /* Program T_POWER_ON times in both ports */
698 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
700 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
703 /* Program Common_Mode_Restore_Time in upstream device */
704 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
705 PCI_L1SS_CTL1_CM_RESTORE_TIME,
708 /* Program LTR_L1.2_THRESHOLD time in both ports */
709 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
710 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
711 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
713 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
714 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
715 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
720 if (state & ASPM_STATE_L1_1)
721 val |= PCI_L1SS_CTL1_ASPM_L1_1;
722 if (state & ASPM_STATE_L1_2)
723 val |= PCI_L1SS_CTL1_ASPM_L1_2;
724 if (state & ASPM_STATE_L1_1_PCIPM)
725 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
726 if (state & ASPM_STATE_L1_2_PCIPM)
727 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
729 /* Enable what we need to enable */
730 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
731 PCI_L1SS_CAP_L1_PM_SS, val);
732 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
733 PCI_L1SS_CAP_L1_PM_SS, val);
736 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
738 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
739 PCI_EXP_LNKCTL_ASPMC, val);
742 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
744 u32 upstream = 0, dwstream = 0;
745 struct pci_dev *child = link->downstream, *parent = link->pdev;
746 struct pci_bus *linkbus = parent->subordinate;
748 /* Enable only the states that were not explicitly disabled */
749 state &= (link->aspm_capable & ~link->aspm_disable);
751 /* Can't enable any substates if L1 is not enabled */
752 if (!(state & ASPM_STATE_L1))
753 state &= ~ASPM_STATE_L1SS;
755 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
756 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
757 state &= ~ASPM_STATE_L1_SS_PCIPM;
758 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
761 /* Nothing to do if the link is already in the requested state */
762 if (link->aspm_enabled == state)
764 /* Convert ASPM state to upstream/downstream ASPM register state */
765 if (state & ASPM_STATE_L0S_UP)
766 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
767 if (state & ASPM_STATE_L0S_DW)
768 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
769 if (state & ASPM_STATE_L1) {
770 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
771 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
774 if (link->aspm_capable & ASPM_STATE_L1SS)
775 pcie_config_aspm_l1ss(link, state);
778 * Spec 2.0 suggests all functions should be configured the
779 * same setting for ASPM. Enabling ASPM L1 should be done in
780 * upstream component first and then downstream, and vice
781 * versa for disabling ASPM L1. Spec doesn't mention L0S.
783 if (state & ASPM_STATE_L1)
784 pcie_config_aspm_dev(parent, upstream);
785 list_for_each_entry(child, &linkbus->devices, bus_list)
786 pcie_config_aspm_dev(child, dwstream);
787 if (!(state & ASPM_STATE_L1))
788 pcie_config_aspm_dev(parent, upstream);
790 link->aspm_enabled = state;
793 static void pcie_config_aspm_path(struct pcie_link_state *link)
796 pcie_config_aspm_link(link, policy_to_aspm_state(link));
801 static void free_link_state(struct pcie_link_state *link)
803 link->pdev->link_state = NULL;
807 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
809 struct pci_dev *child;
813 * Some functions in a slot might not all be PCIe functions,
814 * very strange. Disable ASPM for the whole slot
816 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
817 if (!pci_is_pcie(child))
821 * If ASPM is disabled then we're not going to change
822 * the BIOS state. It's safe to continue even if it's a
830 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
831 * RBER bit to determine if a function is 1.1 version device
833 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
834 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
835 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
842 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
844 struct pcie_link_state *link;
846 link = kzalloc(sizeof(*link), GFP_KERNEL);
850 INIT_LIST_HEAD(&link->sibling);
852 link->downstream = pci_function_0(pdev->subordinate);
855 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
856 * hierarchies. Note that some PCIe host implementations omit
857 * the root ports entirely, in which case a downstream port on
858 * a switch may become the root of the link state chain for all
859 * its subordinate endpoints.
861 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
862 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
863 !pdev->bus->parent->self) {
866 struct pcie_link_state *parent;
868 parent = pdev->bus->parent->self->link_state;
874 link->parent = parent;
875 link->root = link->parent->root;
878 list_add(&link->sibling, &link_list);
879 pdev->link_state = link;
884 * pcie_aspm_init_link_state: Initiate PCI express link state.
885 * It is called after the pcie and its children devices are scanned.
886 * @pdev: the root port or switch downstream port
888 void pcie_aspm_init_link_state(struct pci_dev *pdev)
890 struct pcie_link_state *link;
891 int blacklist = !!pcie_aspm_sanity_check(pdev);
893 if (!aspm_support_enabled)
896 if (pdev->link_state)
900 * We allocate pcie_link_state for the component on the upstream
901 * end of a Link, so there's nothing to do unless this device has a
902 * Link on its secondary side.
904 if (!pdev->has_secondary_link)
907 /* VIA has a strange chipset, root port is under a bridge */
908 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
912 down_read(&pci_bus_sem);
913 if (list_empty(&pdev->subordinate->devices))
916 mutex_lock(&aspm_lock);
917 link = alloc_pcie_link_state(pdev);
921 * Setup initial ASPM state. Note that we need to configure
922 * upstream links also because capable state of them can be
923 * update through pcie_aspm_cap_init().
925 pcie_aspm_cap_init(link, blacklist);
927 /* Setup initial Clock PM state */
928 pcie_clkpm_cap_init(link, blacklist);
931 * At this stage drivers haven't had an opportunity to change the
932 * link policy setting. Enabling ASPM on broken hardware can cripple
933 * it even before the driver has had a chance to disable ASPM, so
934 * default to a safe level right now. If we're enabling ASPM beyond
935 * the BIOS's expectation, we'll do so once pci_enable_device() is
938 if (aspm_policy != POLICY_POWERSAVE &&
939 aspm_policy != POLICY_POWER_SUPERSAVE) {
940 pcie_config_aspm_path(link);
941 pcie_set_clkpm(link, policy_to_clkpm_state(link));
945 mutex_unlock(&aspm_lock);
947 up_read(&pci_bus_sem);
950 /* Recheck latencies and update aspm_capable for links under the root */
951 static void pcie_update_aspm_capable(struct pcie_link_state *root)
953 struct pcie_link_state *link;
954 BUG_ON(root->parent);
955 list_for_each_entry(link, &link_list, sibling) {
956 if (link->root != root)
958 link->aspm_capable = link->aspm_support;
960 list_for_each_entry(link, &link_list, sibling) {
961 struct pci_dev *child;
962 struct pci_bus *linkbus = link->pdev->subordinate;
963 if (link->root != root)
965 list_for_each_entry(child, &linkbus->devices, bus_list) {
966 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
967 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
969 pcie_aspm_check_latency(child);
974 /* @pdev: the endpoint device */
975 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
977 struct pci_dev *parent = pdev->bus->self;
978 struct pcie_link_state *link, *root, *parent_link;
980 if (!parent || !parent->link_state)
983 down_read(&pci_bus_sem);
984 mutex_lock(&aspm_lock);
986 * All PCIe functions are in one slot, remove one function will remove
987 * the whole slot, so just wait until we are the last function left.
989 if (!list_empty(&parent->subordinate->devices))
992 link = parent->link_state;
994 parent_link = link->parent;
996 /* All functions are removed, so just disable ASPM for the link */
997 pcie_config_aspm_link(link, 0);
998 list_del(&link->sibling);
999 /* Clock PM is for endpoint device */
1000 free_link_state(link);
1002 /* Recheck latencies and configure upstream links */
1004 pcie_update_aspm_capable(root);
1005 pcie_config_aspm_path(parent_link);
1008 mutex_unlock(&aspm_lock);
1009 up_read(&pci_bus_sem);
1012 /* @pdev: the root port or switch downstream port */
1013 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1015 struct pcie_link_state *link = pdev->link_state;
1017 if (aspm_disabled || !link)
1020 * Devices changed PM state, we should recheck if latency
1021 * meets all functions' requirement
1023 down_read(&pci_bus_sem);
1024 mutex_lock(&aspm_lock);
1025 pcie_update_aspm_capable(link->root);
1026 pcie_config_aspm_path(link);
1027 mutex_unlock(&aspm_lock);
1028 up_read(&pci_bus_sem);
1031 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1033 struct pcie_link_state *link = pdev->link_state;
1035 if (aspm_disabled || !link)
1038 if (aspm_policy != POLICY_POWERSAVE &&
1039 aspm_policy != POLICY_POWER_SUPERSAVE)
1042 down_read(&pci_bus_sem);
1043 mutex_lock(&aspm_lock);
1044 pcie_config_aspm_path(link);
1045 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1046 mutex_unlock(&aspm_lock);
1047 up_read(&pci_bus_sem);
1050 static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1052 struct pci_dev *parent = pdev->bus->self;
1053 struct pcie_link_state *link;
1055 if (!pci_is_pcie(pdev))
1058 if (pdev->has_secondary_link)
1060 if (!parent || !parent->link_state)
1064 * A driver requested that ASPM be disabled on this device, but
1065 * if we don't have permission to manage ASPM (e.g., on ACPI
1066 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1067 * the _OSC method), we can't honor that request. Windows has
1068 * a similar mechanism using "PciASPMOptOut", which is also
1069 * ignored in this situation.
1071 if (aspm_disabled) {
1072 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1077 down_read(&pci_bus_sem);
1078 mutex_lock(&aspm_lock);
1079 link = parent->link_state;
1080 if (state & PCIE_LINK_STATE_L0S)
1081 link->aspm_disable |= ASPM_STATE_L0S;
1082 if (state & PCIE_LINK_STATE_L1)
1083 link->aspm_disable |= ASPM_STATE_L1;
1084 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1086 if (state & PCIE_LINK_STATE_CLKPM) {
1087 link->clkpm_capable = 0;
1088 pcie_set_clkpm(link, 0);
1090 mutex_unlock(&aspm_lock);
1092 up_read(&pci_bus_sem);
1095 void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1097 __pci_disable_link_state(pdev, state, false);
1099 EXPORT_SYMBOL(pci_disable_link_state_locked);
1102 * pci_disable_link_state - Disable device's link state, so the link will
1103 * never enter specific states. Note that if the BIOS didn't grant ASPM
1104 * control to the OS, this does nothing because we can't touch the LNKCTL
1108 * @state: ASPM link state to disable
1110 void pci_disable_link_state(struct pci_dev *pdev, int state)
1112 __pci_disable_link_state(pdev, state, true);
1114 EXPORT_SYMBOL(pci_disable_link_state);
1116 static int pcie_aspm_set_policy(const char *val,
1117 const struct kernel_param *kp)
1120 struct pcie_link_state *link;
1124 i = sysfs_match_string(policy_str, val);
1127 if (i == aspm_policy)
1130 down_read(&pci_bus_sem);
1131 mutex_lock(&aspm_lock);
1133 list_for_each_entry(link, &link_list, sibling) {
1134 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1135 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1137 mutex_unlock(&aspm_lock);
1138 up_read(&pci_bus_sem);
1142 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1145 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1146 if (i == aspm_policy)
1147 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1149 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1153 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1156 #ifdef CONFIG_PCIEASPM_DEBUG
1157 static ssize_t link_state_show(struct device *dev,
1158 struct device_attribute *attr,
1161 struct pci_dev *pci_device = to_pci_dev(dev);
1162 struct pcie_link_state *link_state = pci_device->link_state;
1164 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1167 static ssize_t link_state_store(struct device *dev,
1168 struct device_attribute *attr,
1172 struct pci_dev *pdev = to_pci_dev(dev);
1173 struct pcie_link_state *link, *root = pdev->link_state->root;
1179 if (kstrtouint(buf, 10, &state))
1181 if ((state & ~ASPM_STATE_ALL) != 0)
1184 down_read(&pci_bus_sem);
1185 mutex_lock(&aspm_lock);
1186 list_for_each_entry(link, &link_list, sibling) {
1187 if (link->root != root)
1189 pcie_config_aspm_link(link, state);
1191 mutex_unlock(&aspm_lock);
1192 up_read(&pci_bus_sem);
1196 static ssize_t clk_ctl_show(struct device *dev,
1197 struct device_attribute *attr,
1200 struct pci_dev *pci_device = to_pci_dev(dev);
1201 struct pcie_link_state *link_state = pci_device->link_state;
1203 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1206 static ssize_t clk_ctl_store(struct device *dev,
1207 struct device_attribute *attr,
1211 struct pci_dev *pdev = to_pci_dev(dev);
1214 if (strtobool(buf, &state))
1217 down_read(&pci_bus_sem);
1218 mutex_lock(&aspm_lock);
1219 pcie_set_clkpm_nocheck(pdev->link_state, state);
1220 mutex_unlock(&aspm_lock);
1221 up_read(&pci_bus_sem);
1226 static DEVICE_ATTR_RW(link_state);
1227 static DEVICE_ATTR_RW(clk_ctl);
1229 static char power_group[] = "power";
1230 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1232 struct pcie_link_state *link_state = pdev->link_state;
1237 if (link_state->aspm_support)
1238 sysfs_add_file_to_group(&pdev->dev.kobj,
1239 &dev_attr_link_state.attr, power_group);
1240 if (link_state->clkpm_capable)
1241 sysfs_add_file_to_group(&pdev->dev.kobj,
1242 &dev_attr_clk_ctl.attr, power_group);
1245 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1247 struct pcie_link_state *link_state = pdev->link_state;
1252 if (link_state->aspm_support)
1253 sysfs_remove_file_from_group(&pdev->dev.kobj,
1254 &dev_attr_link_state.attr, power_group);
1255 if (link_state->clkpm_capable)
1256 sysfs_remove_file_from_group(&pdev->dev.kobj,
1257 &dev_attr_clk_ctl.attr, power_group);
1261 static int __init pcie_aspm_disable(char *str)
1263 if (!strcmp(str, "off")) {
1264 aspm_policy = POLICY_DEFAULT;
1266 aspm_support_enabled = false;
1267 printk(KERN_INFO "PCIe ASPM is disabled\n");
1268 } else if (!strcmp(str, "force")) {
1270 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1275 __setup("pcie_aspm=", pcie_aspm_disable);
1277 void pcie_no_aspm(void)
1280 * Disabling ASPM is intended to prevent the kernel from modifying
1281 * existing hardware state, not to clear existing state. To that end:
1282 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1283 * (b) prevent userspace from changing policy
1286 aspm_policy = POLICY_DEFAULT;
1291 bool pcie_aspm_support_enabled(void)
1293 return aspm_support_enabled;
1295 EXPORT_SYMBOL(pcie_aspm_support_enabled);