1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
50 EXPORT_SYMBOL(pci_pci_problems);
52 unsigned int pci_pm_d3hot_delay;
54 static void pci_pme_list_scan(struct work_struct *work);
56 static LIST_HEAD(pci_pme_list);
57 static DEFINE_MUTEX(pci_pme_list_mutex);
58 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
60 struct pci_pme_device {
61 struct list_head list;
65 #define PME_TIMEOUT 1000 /* How long between PME checks */
68 * Following exit from Conventional Reset, devices must be ready within 1 sec
69 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 * Reset (PCIe r6.0 sec 5.8).
72 #define PCI_RESET_WAIT 1000 /* msec */
75 * Devices may extend the 1 sec period through Request Retry Status
76 * completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
77 * limit, but 60 sec ought to be enough for any device to become
80 #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
82 static void pci_dev_d3_sleep(struct pci_dev *dev)
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
88 /* Use a 20% upper bound, 1ms minimum */
89 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
90 usleep_range(delay_ms * USEC_PER_MSEC,
91 (delay_ms + upper) * USEC_PER_MSEC);
95 bool pci_reset_supported(struct pci_dev *dev)
97 return dev->reset_methods[0] != 0;
100 #ifdef CONFIG_PCI_DOMAINS
101 int pci_domains_supported = 1;
104 #define DEFAULT_CARDBUS_IO_SIZE (256)
105 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
106 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
107 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
108 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
110 #define DEFAULT_HOTPLUG_IO_SIZE (256)
111 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
112 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
113 /* hpiosize=nn can override this */
114 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
117 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
118 * pci=hpmemsize=nnM overrides both
120 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
121 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
123 #define DEFAULT_HOTPLUG_BUS_SIZE 1
124 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
128 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
129 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
130 #elif defined CONFIG_PCIE_BUS_SAFE
131 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
132 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
133 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
134 #elif defined CONFIG_PCIE_BUS_PEER2PEER
135 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
137 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
141 * The default CLS is used if arch didn't set CLS explicitly and not
142 * all pci devices agree on the same value. Arch can override either
143 * the dfl or actual value as it sees fit. Don't forget this is
144 * measured in 32-bit words, not bytes.
146 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
147 u8 pci_cache_line_size;
150 * If we set up a device for bus mastering, we need to check the latency
151 * timer as certain BIOSes forget to set it properly.
153 unsigned int pcibios_max_latency = 255;
155 /* If set, the PCIe ARI capability will not be used. */
156 static bool pcie_ari_disabled;
158 /* If set, the PCIe ATS capability will not be used. */
159 static bool pcie_ats_disabled;
161 /* If set, the PCI config space of each device is printed during boot. */
164 bool pci_ats_disabled(void)
166 return pcie_ats_disabled;
168 EXPORT_SYMBOL_GPL(pci_ats_disabled);
170 /* Disable bridge_d3 for all PCIe ports */
171 static bool pci_bridge_d3_disable;
172 /* Force bridge_d3 for all PCIe ports */
173 static bool pci_bridge_d3_force;
175 static int __init pcie_port_pm_setup(char *str)
177 if (!strcmp(str, "off"))
178 pci_bridge_d3_disable = true;
179 else if (!strcmp(str, "force"))
180 pci_bridge_d3_force = true;
183 __setup("pcie_port_pm=", pcie_port_pm_setup);
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
187 * @bus: pointer to PCI bus structure to search
189 * Given a PCI bus, returns the highest PCI bus number present in the set
190 * including the given PCI bus and its list of child PCI buses.
192 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
195 unsigned char max, n;
197 max = bus->busn_res.end;
198 list_for_each_entry(tmp, &bus->children, node) {
199 n = pci_bus_max_busnr(tmp);
205 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
209 * @pdev: the PCI device
211 * Returns error bits set in PCI_STATUS and clears them.
213 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
218 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
219 if (ret != PCIBIOS_SUCCESSFUL)
222 status &= PCI_STATUS_ERROR_BITS;
224 pci_write_config_word(pdev, PCI_STATUS, status);
228 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
230 #ifdef CONFIG_HAS_IOMEM
231 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
234 struct resource *res = &pdev->resource[bar];
235 resource_size_t start = res->start;
236 resource_size_t size = resource_size(res);
239 * Make sure the BAR is actually a memory resource, not an IO resource
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
242 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
247 return ioremap_wc(start, size);
249 return ioremap(start, size);
252 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
254 return __pci_ioremap_resource(pdev, bar, false);
256 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
258 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
260 return __pci_ioremap_resource(pdev, bar, true);
262 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
266 * pci_dev_str_match_path - test if a path string matches a device
267 * @dev: the PCI device to test
268 * @path: string to match the device against
269 * @endptr: pointer to the string after the match
271 * Test if a string (typically from a kernel parameter) formatted as a
272 * path of device/function addresses matches a PCI device. The string must
275 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
277 * A path for a device can be obtained using 'lspci -t'. Using a path
278 * is more robust against bus renumbering than using only a single bus,
279 * device and function address.
281 * Returns 1 if the string matches the device, 0 if it does not and
282 * a negative error code if it fails to parse the string.
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
288 unsigned int seg, bus, slot, func;
292 *endptr = strchrnul(path, ';');
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
299 p = strrchr(wpath, '/');
302 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
308 if (dev->devfn != PCI_DEVFN(slot, func)) {
314 * Note: we don't need to get a reference to the upstream
315 * bridge because we hold a reference to the top level
316 * device which should hold a reference to the bridge,
319 dev = pci_upstream_bridge(dev);
328 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
332 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
339 ret = (seg == pci_domain_nr(dev->bus) &&
340 bus == dev->bus->number &&
341 dev->devfn == PCI_DEVFN(slot, func));
349 * pci_dev_str_match - test if a string matches a device
350 * @dev: the PCI device to test
351 * @p: string to match the device against
352 * @endptr: pointer to the string after the match
354 * Test if a string (typically from a kernel parameter) matches a specified
355 * PCI device. The string may be of one of the following formats:
357 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
358 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
360 * The first format specifies a PCI bus/device/function address which
361 * may change if new hardware is inserted, if motherboard firmware changes,
362 * or due to changes caused in kernel parameters. If the domain is
363 * left unspecified, it is taken to be 0. In order to be robust against
364 * bus renumbering issues, a path of PCI device/function numbers may be used
365 * to address the specific device. The path for a device can be determined
366 * through the use of 'lspci -t'.
368 * The second format matches devices using IDs in the configuration
369 * space which may match multiple devices in the system. A value of 0
370 * for any field will match all devices. (Note: this differs from
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
372 * legacy reasons and convenience so users don't have to specify
373 * FFFFFFFFs on the command line.)
375 * Returns 1 if the string matches the device, 0 if it does not and
376 * a negative error code if the string cannot be parsed.
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
383 unsigned short vendor, device, subsystem_vendor, subsystem_device;
385 if (strncmp(p, "pci:", 4) == 0) {
386 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
388 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
389 &subsystem_vendor, &subsystem_device, &count);
391 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
395 subsystem_vendor = 0;
396 subsystem_device = 0;
401 if ((!vendor || vendor == dev->vendor) &&
402 (!device || device == dev->device) &&
403 (!subsystem_vendor ||
404 subsystem_vendor == dev->subsystem_vendor) &&
405 (!subsystem_device ||
406 subsystem_device == dev->subsystem_device))
410 * PCI Bus, Device, Function IDs are specified
411 * (optionally, may include a path of devfns following it)
413 ret = pci_dev_str_match_path(dev, p, &p);
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
429 u8 pos, int cap, int *ttl)
434 pci_bus_read_config_byte(bus, devfn, pos, &pos);
440 pci_bus_read_config_word(bus, devfn, pos, &ent);
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
455 int ttl = PCI_FIND_CAP_TTL;
457 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
462 return __pci_find_next_cap(dev->bus, dev->devfn,
463 pos + PCI_CAP_LIST_NEXT, cap);
465 EXPORT_SYMBOL_GPL(pci_find_next_capability);
467 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
468 unsigned int devfn, u8 hdr_type)
472 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
473 if (!(status & PCI_STATUS_CAP_LIST))
477 case PCI_HEADER_TYPE_NORMAL:
478 case PCI_HEADER_TYPE_BRIDGE:
479 return PCI_CAPABILITY_LIST;
480 case PCI_HEADER_TYPE_CARDBUS:
481 return PCI_CB_CAPABILITY_LIST;
488 * pci_find_capability - query for devices' capabilities
489 * @dev: PCI device to query
490 * @cap: capability code
492 * Tell if a device supports a given PCI capability.
493 * Returns the address of the requested capability structure within the
494 * device's PCI configuration space or 0 in case the device does not
495 * support it. Possible values for @cap include:
497 * %PCI_CAP_ID_PM Power Management
498 * %PCI_CAP_ID_AGP Accelerated Graphics Port
499 * %PCI_CAP_ID_VPD Vital Product Data
500 * %PCI_CAP_ID_SLOTID Slot Identification
501 * %PCI_CAP_ID_MSI Message Signalled Interrupts
502 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
503 * %PCI_CAP_ID_PCIX PCI-X
504 * %PCI_CAP_ID_EXP PCI Express
506 u8 pci_find_capability(struct pci_dev *dev, int cap)
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
516 EXPORT_SYMBOL(pci_find_capability);
519 * pci_bus_find_capability - query for devices' capabilities
520 * @bus: the PCI bus to query
521 * @devfn: PCI device to query
522 * @cap: capability code
524 * Like pci_find_capability() but works for PCI devices that do not have a
525 * pci_dev structure set up yet.
527 * Returns the address of the requested capability structure within the
528 * device's PCI configuration space or 0 in case the device does not
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
535 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
537 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & PCI_HEADER_TYPE_MASK);
539 pos = __pci_find_next_cap(bus, devfn, pos, cap);
543 EXPORT_SYMBOL(pci_bus_find_capability);
546 * pci_find_next_ext_capability - Find an extended capability
547 * @dev: PCI device to query
548 * @start: address at which to start looking (0 to start at beginning of list)
549 * @cap: capability code
551 * Returns the address of the next matching extended capability structure
552 * within the device's PCI configuration space or 0 if the device does
553 * not support it. Some capabilities can occur several times, e.g., the
554 * vendor-specific capability, and this provides a way to find them all.
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
560 u16 pos = PCI_CFG_SPACE_SIZE;
562 /* minimum 8 bytes per capability */
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
571 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
575 * If we have no capabilities, this is indicated by cap ID,
576 * cap version and next pointer all being 0.
582 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
585 pos = PCI_EXT_CAP_NEXT(header);
586 if (pos < PCI_CFG_SPACE_SIZE)
589 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
595 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
598 * pci_find_ext_capability - Find an extended capability
599 * @dev: PCI device to query
600 * @cap: capability code
602 * Returns the address of the requested extended capability structure
603 * within the device's PCI configuration space or 0 if the device does
604 * not support it. Possible values for @cap include:
606 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
607 * %PCI_EXT_CAP_ID_VC Virtual Channel
608 * %PCI_EXT_CAP_ID_DSN Device Serial Number
609 * %PCI_EXT_CAP_ID_PWR Power Budgeting
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
613 return pci_find_next_ext_capability(dev, 0, cap);
615 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
619 * @dev: PCI device to query
621 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
624 * Returns the DSN, or zero if the capability does not exist.
626 u64 pci_get_dsn(struct pci_dev *dev)
632 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
637 * The Device Serial Number is two dwords offset 4 bytes from the
638 * capability position. The specification says that the first dword is
639 * the lower half, and the second dword is the upper half.
642 pci_read_config_dword(dev, pos, &dword);
644 pci_read_config_dword(dev, pos + 4, &dword);
645 dsn |= ((u64)dword) << 32;
649 EXPORT_SYMBOL_GPL(pci_get_dsn);
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
653 int rc, ttl = PCI_FIND_CAP_TTL;
656 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
657 mask = HT_3BIT_CAP_MASK;
659 mask = HT_5BIT_CAP_MASK;
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
662 PCI_CAP_ID_HT, &ttl);
664 rc = pci_read_config_byte(dev, pos + 3, &cap);
665 if (rc != PCIBIOS_SUCCESSFUL)
668 if ((cap & mask) == ht_cap)
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
672 pos + PCI_CAP_LIST_NEXT,
673 PCI_CAP_ID_HT, &ttl);
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
681 * @dev: PCI device to query
682 * @pos: Position from which to continue searching
683 * @ht_cap: HyperTransport capability code
685 * To be used in conjunction with pci_find_ht_capability() to search for
686 * all capabilities matching @ht_cap. @pos should always be a value returned
687 * from pci_find_ht_capability().
689 * NB. To be 100% safe against broken PCI devices, the caller should take
690 * steps to avoid an infinite loop.
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
694 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
696 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
700 * @dev: PCI device to query
701 * @ht_cap: HyperTransport capability code
703 * Tell if a device supports a given HyperTransport capability.
704 * Returns an address within the device's PCI configuration space
705 * or 0 in case the device does not support the request capability.
706 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
707 * which has a HyperTransport capability matching @ht_cap.
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
715 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
719 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
723 * @dev: PCI device to query
724 * @vendor: Vendor ID for which capability is defined
725 * @cap: Vendor-specific capability ID
727 * If @dev has Vendor ID @vendor, search for a VSEC capability with
728 * VSEC ID @cap. If found, return the capability offset in
729 * config space; otherwise return 0.
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
737 if (vendor != dev->vendor)
740 while ((vsec = pci_find_next_ext_capability(dev, vsec,
741 PCI_EXT_CAP_ID_VNDR))) {
742 ret = pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
743 if (ret != PCIBIOS_SUCCESSFUL)
746 if (PCI_VNDR_HEADER_ID(header) == cap)
752 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
755 * pci_find_dvsec_capability - Find DVSEC for vendor
756 * @dev: PCI device to query
757 * @vendor: Vendor ID to match for the DVSEC
758 * @dvsec: Designated Vendor-specific capability ID
760 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
761 * offset in config space; otherwise return 0.
763 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
767 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
774 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
775 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
776 if (vendor == v && dvsec == id)
779 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
784 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
787 * pci_find_parent_resource - return resource region of parent bus of given
789 * @dev: PCI device structure contains resources to be searched
790 * @res: child resource record for which parent is sought
792 * For given resource region of given device, return the resource region of
793 * parent bus the given region is contained in.
795 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
796 struct resource *res)
798 const struct pci_bus *bus = dev->bus;
801 pci_bus_for_each_resource(bus, r) {
804 if (resource_contains(r, res)) {
807 * If the window is prefetchable but the BAR is
808 * not, the allocator made a mistake.
810 if (r->flags & IORESOURCE_PREFETCH &&
811 !(res->flags & IORESOURCE_PREFETCH))
815 * If we're below a transparent bridge, there may
816 * be both a positively-decoded aperture and a
817 * subtractively-decoded region that contain the BAR.
818 * We want the positively-decoded one, so this depends
819 * on pci_bus_for_each_resource() giving us those
827 EXPORT_SYMBOL(pci_find_parent_resource);
830 * pci_find_resource - Return matching PCI device resource
831 * @dev: PCI device to query
832 * @res: Resource to look for
834 * Goes over standard PCI resources (BARs) and checks if the given resource
835 * is partially or fully contained in any of them. In that case the
836 * matching resource is returned, %NULL otherwise.
838 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
842 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
843 struct resource *r = &dev->resource[i];
845 if (r->start && resource_contains(r, res))
851 EXPORT_SYMBOL(pci_find_resource);
854 * pci_resource_name - Return the name of the PCI resource
855 * @dev: PCI device to query
856 * @i: index of the resource
858 * Return the standard PCI resource (BAR) name according to their index.
860 const char *pci_resource_name(struct pci_dev *dev, unsigned int i)
862 static const char * const bar_name[] = {
870 #ifdef CONFIG_PCI_IOV
878 "bridge window", /* "io" included in %pR */
879 "bridge window", /* "mem" included in %pR */
880 "bridge window", /* "mem pref" included in %pR */
882 static const char * const cardbus_name[] = {
889 #ifdef CONFIG_PCI_IOV
897 "CardBus bridge window 0", /* I/O */
898 "CardBus bridge window 1", /* I/O */
899 "CardBus bridge window 0", /* mem */
900 "CardBus bridge window 1", /* mem */
903 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS &&
904 i < ARRAY_SIZE(cardbus_name))
905 return cardbus_name[i];
907 if (i < ARRAY_SIZE(bar_name))
914 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
915 * @dev: the PCI device to operate on
916 * @pos: config space offset of status word
917 * @mask: mask of bit(s) to care about in status word
919 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
921 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
925 /* Wait for Transaction Pending bit clean */
926 for (i = 0; i < 4; i++) {
929 msleep((1 << (i - 1)) * 100);
931 pci_read_config_word(dev, pos, &status);
932 if (!(status & mask))
939 static int pci_acs_enable;
942 * pci_request_acs - ask for ACS to be enabled if supported
944 void pci_request_acs(void)
949 static const char *disable_acs_redir_param;
952 * pci_disable_acs_redir - disable ACS redirect capabilities
953 * @dev: the PCI device
955 * For only devices specified in the disable_acs_redir parameter.
957 static void pci_disable_acs_redir(struct pci_dev *dev)
964 if (!disable_acs_redir_param)
967 p = disable_acs_redir_param;
969 ret = pci_dev_str_match(dev, p, &p);
971 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
972 disable_acs_redir_param);
975 } else if (ret == 1) {
980 if (*p != ';' && *p != ',') {
981 /* End of param or invalid format */
990 if (!pci_dev_specific_disable_acs_redir(dev))
995 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
999 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1001 /* P2P Request & Completion Redirect */
1002 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
1004 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1006 pci_info(dev, "disabled ACS redirect\n");
1010 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1011 * @dev: the PCI device
1013 static void pci_std_enable_acs(struct pci_dev *dev)
1023 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1024 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1026 /* Source Validation */
1027 ctrl |= (cap & PCI_ACS_SV);
1029 /* P2P Request Redirect */
1030 ctrl |= (cap & PCI_ACS_RR);
1032 /* P2P Completion Redirect */
1033 ctrl |= (cap & PCI_ACS_CR);
1035 /* Upstream Forwarding */
1036 ctrl |= (cap & PCI_ACS_UF);
1038 /* Enable Translation Blocking for external devices and noats */
1039 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
1040 ctrl |= (cap & PCI_ACS_TB);
1042 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1046 * pci_enable_acs - enable ACS if hardware support it
1047 * @dev: the PCI device
1049 static void pci_enable_acs(struct pci_dev *dev)
1051 if (!pci_acs_enable)
1052 goto disable_acs_redir;
1054 if (!pci_dev_specific_enable_acs(dev))
1055 goto disable_acs_redir;
1057 pci_std_enable_acs(dev);
1061 * Note: pci_disable_acs_redir() must be called even if ACS was not
1062 * enabled by the kernel because it may have been enabled by
1063 * platform firmware. So if we are told to disable it, we should
1064 * always disable it after setting the kernel's default
1067 pci_disable_acs_redir(dev);
1071 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1072 * @dev: PCI device to have its BARs restored
1074 * Restore the BAR values for a given device, so as to make it
1075 * accessible by its driver.
1077 static void pci_restore_bars(struct pci_dev *dev)
1081 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1082 pci_update_resource(dev, i);
1085 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1087 if (pci_use_mid_pm())
1090 return acpi_pci_power_manageable(dev);
1093 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1096 if (pci_use_mid_pm())
1097 return mid_pci_set_power_state(dev, t);
1099 return acpi_pci_set_power_state(dev, t);
1102 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1104 if (pci_use_mid_pm())
1105 return mid_pci_get_power_state(dev);
1107 return acpi_pci_get_power_state(dev);
1110 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1112 if (!pci_use_mid_pm())
1113 acpi_pci_refresh_power_state(dev);
1116 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1118 if (pci_use_mid_pm())
1119 return PCI_POWER_ERROR;
1121 return acpi_pci_choose_state(dev);
1124 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1126 if (pci_use_mid_pm())
1127 return PCI_POWER_ERROR;
1129 return acpi_pci_wakeup(dev, enable);
1132 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1134 if (pci_use_mid_pm())
1137 return acpi_pci_need_resume(dev);
1140 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1142 if (pci_use_mid_pm())
1145 return acpi_pci_bridge_d3(dev);
1149 * pci_update_current_state - Read power state of given device and cache it
1150 * @dev: PCI device to handle.
1151 * @state: State to cache in case the device doesn't have the PM capability
1153 * The power state is read from the PMCSR register, which however is
1154 * inaccessible in D3cold. The platform firmware is therefore queried first
1155 * to detect accessibility of the register. In case the platform firmware
1156 * reports an incorrect state or the device isn't power manageable by the
1157 * platform at all, we try to detect D3cold by testing accessibility of the
1158 * vendor ID in config space.
1160 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1162 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1163 dev->current_state = PCI_D3cold;
1164 } else if (dev->pm_cap) {
1167 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1168 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1169 dev->current_state = PCI_D3cold;
1172 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1174 dev->current_state = state;
1179 * pci_refresh_power_state - Refresh the given device's power state data
1180 * @dev: Target PCI device.
1182 * Ask the platform to refresh the devices power state information and invoke
1183 * pci_update_current_state() to update its current PCI power state.
1185 void pci_refresh_power_state(struct pci_dev *dev)
1187 platform_pci_refresh_power_state(dev);
1188 pci_update_current_state(dev, dev->current_state);
1192 * pci_platform_power_transition - Use platform to change device power state
1193 * @dev: PCI device to handle.
1194 * @state: State to put the device into.
1196 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1200 error = platform_pci_set_power_state(dev, state);
1202 pci_update_current_state(dev, state);
1203 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1204 dev->current_state = PCI_D0;
1208 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1210 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1212 pm_request_resume(&pci_dev->dev);
1217 * pci_resume_bus - Walk given bus and runtime resume devices on it
1218 * @bus: Top bus of the subtree to walk.
1220 void pci_resume_bus(struct pci_bus *bus)
1223 pci_walk_bus(bus, pci_resume_one, NULL);
1226 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1229 bool retrain = false;
1230 struct pci_dev *bridge;
1232 if (pci_is_pcie(dev)) {
1233 bridge = pci_upstream_bridge(dev);
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1243 * the read (except when CRS SV is enabled and the read was for the
1244 * Vendor ID; in that case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1253 pci_read_config_dword(dev, PCI_COMMAND, &id);
1254 if (!PCI_POSSIBLE_ERROR(id))
1257 if (delay > timeout) {
1258 pci_warn(dev, "not ready %dms after %s; giving up\n",
1259 delay - 1, reset_type);
1263 if (delay > PCI_RESET_WAIT) {
1266 if (pcie_failed_link_retrain(bridge)) {
1271 pci_info(dev, "not ready %dms after %s; waiting\n",
1272 delay - 1, reset_type);
1279 if (delay > PCI_RESET_WAIT)
1280 pci_info(dev, "ready %dms after %s\n", delay - 1,
1283 pci_dbg(dev, "ready %dms after %s\n", delay - 1,
1290 * pci_power_up - Put the given device into D0
1291 * @dev: PCI device to power up
1293 * On success, return 0 or 1, depending on whether or not it is necessary to
1294 * restore the device's BARs subsequently (1 is returned in that case).
1296 * On failure, return a negative error code. Always return failure if @dev
1297 * lacks a Power Management Capability, even if the platform was able to
1298 * put the device in D0 via non-PCI means.
1300 int pci_power_up(struct pci_dev *dev)
1306 platform_pci_set_power_state(dev, PCI_D0);
1309 state = platform_pci_get_power_state(dev);
1310 if (state == PCI_UNKNOWN)
1311 dev->current_state = PCI_D0;
1313 dev->current_state = state;
1318 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1319 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1320 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1321 pci_power_name(dev->current_state));
1322 dev->current_state = PCI_D3cold;
1326 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1328 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1329 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1331 if (state == PCI_D0)
1335 * Force the entire word to 0. This doesn't affect PME_Status, disables
1336 * PME_En, and sets PowerState to 0.
1338 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1340 /* Mandatory transition delays; see PCI PM 1.2. */
1341 if (state == PCI_D3hot)
1342 pci_dev_d3_sleep(dev);
1343 else if (state == PCI_D2)
1344 udelay(PCI_PM_D2_DELAY);
1347 dev->current_state = PCI_D0;
1355 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1356 * @dev: PCI device to power up
1358 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1359 * to confirm the state change, restore its BARs if they might be lost and
1360 * reconfigure ASPM in accordance with the new power state.
1362 * If pci_restore_state() is going to be called right after a power state change
1363 * to D0, it is more efficient to use pci_power_up() directly instead of this
1366 static int pci_set_full_power_state(struct pci_dev *dev)
1371 ret = pci_power_up(dev);
1373 if (dev->current_state == PCI_D0)
1379 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1380 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1381 if (dev->current_state != PCI_D0) {
1382 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1383 pci_power_name(dev->current_state));
1384 } else if (ret > 0) {
1386 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1387 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1388 * from D3hot to D0 _may_ perform an internal reset, thereby
1389 * going to "D0 Uninitialized" rather than "D0 Initialized".
1390 * For example, at least some versions of the 3c905B and the
1391 * 3c556B exhibit this behaviour.
1393 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1394 * devices in a D3hot state at boot. Consequently, we need to
1395 * restore at least the BARs so that the device will be
1396 * accessible to its driver.
1398 pci_restore_bars(dev);
1402 pcie_aspm_pm_state_change(dev->bus->self);
1408 * __pci_dev_set_current_state - Set current state of a PCI device
1409 * @dev: Device to handle
1410 * @data: pointer to state to be set
1412 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1414 pci_power_t state = *(pci_power_t *)data;
1416 dev->current_state = state;
1421 * pci_bus_set_current_state - Walk given bus and set current state of devices
1422 * @bus: Top bus of the subtree to walk.
1423 * @state: state to be set
1425 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1428 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1432 * pci_set_low_power_state - Put a PCI device into a low-power state.
1433 * @dev: PCI device to handle.
1434 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1436 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1439 * -EINVAL if the requested state is invalid.
1440 * -EIO if device does not support PCI PM or its PM capabilities register has a
1441 * wrong version, or device doesn't support the requested state.
1442 * 0 if device already is in the requested state.
1443 * 0 if device's power state has been successfully changed.
1445 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1453 * Validate transition: We can enter D0 from any state, but if
1454 * we're already in a low-power state, we can only go deeper. E.g.,
1455 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1456 * we'd have to go from D3 to D0, then to D1.
1458 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1459 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1460 pci_power_name(dev->current_state),
1461 pci_power_name(state));
1465 /* Check if this device supports the desired state */
1466 if ((state == PCI_D1 && !dev->d1_support)
1467 || (state == PCI_D2 && !dev->d2_support))
1470 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1471 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1472 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1473 pci_power_name(dev->current_state),
1474 pci_power_name(state));
1475 dev->current_state = PCI_D3cold;
1479 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1482 /* Enter specified state */
1483 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1485 /* Mandatory power management transition delays; see PCI PM 1.2. */
1486 if (state == PCI_D3hot)
1487 pci_dev_d3_sleep(dev);
1488 else if (state == PCI_D2)
1489 udelay(PCI_PM_D2_DELAY);
1491 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1492 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1493 if (dev->current_state != state)
1494 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1495 pci_power_name(dev->current_state),
1496 pci_power_name(state));
1499 pcie_aspm_pm_state_change(dev->bus->self);
1505 * pci_set_power_state - Set the power state of a PCI device
1506 * @dev: PCI device to handle.
1507 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1509 * Transition a device to a new power state, using the platform firmware and/or
1510 * the device's PCI PM registers.
1513 * -EINVAL if the requested state is invalid.
1514 * -EIO if device does not support PCI PM or its PM capabilities register has a
1515 * wrong version, or device doesn't support the requested state.
1516 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1517 * 0 if device already is in the requested state.
1518 * 0 if the transition is to D3 but D3 is not supported.
1519 * 0 if device's power state has been successfully changed.
1521 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1525 /* Bound the state we're entering */
1526 if (state > PCI_D3cold)
1528 else if (state < PCI_D0)
1530 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1533 * If the device or the parent bridge do not support PCI
1534 * PM, ignore the request if we're doing anything other
1535 * than putting it into D0 (which would only happen on
1540 /* Check if we're already there */
1541 if (dev->current_state == state)
1544 if (state == PCI_D0)
1545 return pci_set_full_power_state(dev);
1548 * This device is quirked not to be put into D3, so don't put it in
1551 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1554 if (state == PCI_D3cold) {
1556 * To put the device in D3cold, put it into D3hot in the native
1557 * way, then put it into D3cold using platform ops.
1559 error = pci_set_low_power_state(dev, PCI_D3hot);
1561 if (pci_platform_power_transition(dev, PCI_D3cold))
1564 /* Powering off a bridge may power off the whole hierarchy */
1565 if (dev->current_state == PCI_D3cold)
1566 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1568 error = pci_set_low_power_state(dev, state);
1570 if (pci_platform_power_transition(dev, state))
1576 EXPORT_SYMBOL(pci_set_power_state);
1578 #define PCI_EXP_SAVE_REGS 7
1580 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1581 u16 cap, bool extended)
1583 struct pci_cap_saved_state *tmp;
1585 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1586 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1592 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1594 return _pci_find_saved_cap(dev, cap, false);
1597 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1599 return _pci_find_saved_cap(dev, cap, true);
1602 static int pci_save_pcie_state(struct pci_dev *dev)
1605 struct pci_cap_saved_state *save_state;
1608 if (!pci_is_pcie(dev))
1611 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1613 pci_err(dev, "buffer not found in %s\n", __func__);
1617 cap = (u16 *)&save_state->cap.data[0];
1618 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1619 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1620 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1621 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1622 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1623 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1624 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1629 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1631 #ifdef CONFIG_PCIEASPM
1632 struct pci_dev *bridge;
1635 bridge = pci_upstream_bridge(dev);
1636 if (bridge && bridge->ltr_path) {
1637 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1638 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1639 pci_dbg(bridge, "re-enabling LTR\n");
1640 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1641 PCI_EXP_DEVCTL2_LTR_EN);
1647 static void pci_restore_pcie_state(struct pci_dev *dev)
1650 struct pci_cap_saved_state *save_state;
1653 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1658 * Downstream ports reset the LTR enable bit when link goes down.
1659 * Check and re-configure the bit here before restoring device.
1660 * PCIe r5.0, sec 7.5.3.16.
1662 pci_bridge_reconfigure_ltr(dev);
1664 cap = (u16 *)&save_state->cap.data[0];
1665 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1666 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1667 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1668 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1669 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1670 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1671 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1674 static int pci_save_pcix_state(struct pci_dev *dev)
1677 struct pci_cap_saved_state *save_state;
1679 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1683 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1685 pci_err(dev, "buffer not found in %s\n", __func__);
1689 pci_read_config_word(dev, pos + PCI_X_CMD,
1690 (u16 *)save_state->cap.data);
1695 static void pci_restore_pcix_state(struct pci_dev *dev)
1698 struct pci_cap_saved_state *save_state;
1701 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1702 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1703 if (!save_state || !pos)
1705 cap = (u16 *)&save_state->cap.data[0];
1707 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1710 static void pci_save_ltr_state(struct pci_dev *dev)
1713 struct pci_cap_saved_state *save_state;
1716 if (!pci_is_pcie(dev))
1719 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1723 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1725 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1729 /* Some broken devices only support dword access to LTR */
1730 cap = &save_state->cap.data[0];
1731 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1734 static void pci_restore_ltr_state(struct pci_dev *dev)
1736 struct pci_cap_saved_state *save_state;
1740 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1741 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1742 if (!save_state || !ltr)
1745 /* Some broken devices only support dword access to LTR */
1746 cap = &save_state->cap.data[0];
1747 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1751 * pci_save_state - save the PCI configuration space of a device before
1753 * @dev: PCI device that we're dealing with
1755 int pci_save_state(struct pci_dev *dev)
1758 /* XXX: 100% dword access ok here? */
1759 for (i = 0; i < 16; i++) {
1760 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1761 pci_dbg(dev, "save config %#04x: %#010x\n",
1762 i * 4, dev->saved_config_space[i]);
1764 dev->state_saved = true;
1766 i = pci_save_pcie_state(dev);
1770 i = pci_save_pcix_state(dev);
1774 pci_save_ltr_state(dev);
1775 pci_save_dpc_state(dev);
1776 pci_save_aer_state(dev);
1777 pci_save_ptm_state(dev);
1778 return pci_save_vc_state(dev);
1780 EXPORT_SYMBOL(pci_save_state);
1782 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1783 u32 saved_val, int retry, bool force)
1787 pci_read_config_dword(pdev, offset, &val);
1788 if (!force && val == saved_val)
1792 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n",
1793 offset, val, saved_val);
1794 pci_write_config_dword(pdev, offset, saved_val);
1798 pci_read_config_dword(pdev, offset, &val);
1799 if (val == saved_val)
1806 static void pci_restore_config_space_range(struct pci_dev *pdev,
1807 int start, int end, int retry,
1812 for (index = end; index >= start; index--)
1813 pci_restore_config_dword(pdev, 4 * index,
1814 pdev->saved_config_space[index],
1818 static void pci_restore_config_space(struct pci_dev *pdev)
1820 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1821 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1822 /* Restore BARs before the command register. */
1823 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1824 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1825 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1826 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1829 * Force rewriting of prefetch registers to avoid S3 resume
1830 * issues on Intel PCI bridges that occur when these
1831 * registers are not explicitly written.
1833 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1834 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1836 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1840 static void pci_restore_rebar_state(struct pci_dev *pdev)
1842 unsigned int pos, nbars, i;
1845 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1849 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1850 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
1852 for (i = 0; i < nbars; i++, pos += 8) {
1853 struct resource *res;
1856 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1857 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1858 res = pdev->resource + bar_idx;
1859 size = pci_rebar_bytes_to_size(resource_size(res));
1860 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1861 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
1862 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1867 * pci_restore_state - Restore the saved state of a PCI device
1868 * @dev: PCI device that we're dealing with
1870 void pci_restore_state(struct pci_dev *dev)
1872 if (!dev->state_saved)
1876 * Restore max latencies (in the LTR capability) before enabling
1877 * LTR itself (in the PCIe capability).
1879 pci_restore_ltr_state(dev);
1881 pci_restore_pcie_state(dev);
1882 pci_restore_pasid_state(dev);
1883 pci_restore_pri_state(dev);
1884 pci_restore_ats_state(dev);
1885 pci_restore_vc_state(dev);
1886 pci_restore_rebar_state(dev);
1887 pci_restore_dpc_state(dev);
1888 pci_restore_ptm_state(dev);
1890 pci_aer_clear_status(dev);
1891 pci_restore_aer_state(dev);
1893 pci_restore_config_space(dev);
1895 pci_restore_pcix_state(dev);
1896 pci_restore_msi_state(dev);
1898 /* Restore ACS and IOV configuration state */
1899 pci_enable_acs(dev);
1900 pci_restore_iov_state(dev);
1902 dev->state_saved = false;
1904 EXPORT_SYMBOL(pci_restore_state);
1906 struct pci_saved_state {
1907 u32 config_space[16];
1908 struct pci_cap_saved_data cap[];
1912 * pci_store_saved_state - Allocate and return an opaque struct containing
1913 * the device saved state.
1914 * @dev: PCI device that we're dealing with
1916 * Return NULL if no state or error.
1918 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1920 struct pci_saved_state *state;
1921 struct pci_cap_saved_state *tmp;
1922 struct pci_cap_saved_data *cap;
1925 if (!dev->state_saved)
1928 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1930 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1931 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1933 state = kzalloc(size, GFP_KERNEL);
1937 memcpy(state->config_space, dev->saved_config_space,
1938 sizeof(state->config_space));
1941 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1942 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1943 memcpy(cap, &tmp->cap, len);
1944 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1946 /* Empty cap_save terminates list */
1950 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1953 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1954 * @dev: PCI device that we're dealing with
1955 * @state: Saved state returned from pci_store_saved_state()
1957 int pci_load_saved_state(struct pci_dev *dev,
1958 struct pci_saved_state *state)
1960 struct pci_cap_saved_data *cap;
1962 dev->state_saved = false;
1967 memcpy(dev->saved_config_space, state->config_space,
1968 sizeof(state->config_space));
1972 struct pci_cap_saved_state *tmp;
1974 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1975 if (!tmp || tmp->cap.size != cap->size)
1978 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1979 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1980 sizeof(struct pci_cap_saved_data) + cap->size);
1983 dev->state_saved = true;
1986 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1989 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1990 * and free the memory allocated for it.
1991 * @dev: PCI device that we're dealing with
1992 * @state: Pointer to saved state returned from pci_store_saved_state()
1994 int pci_load_and_free_saved_state(struct pci_dev *dev,
1995 struct pci_saved_state **state)
1997 int ret = pci_load_saved_state(dev, *state);
2002 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
2004 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
2006 return pci_enable_resources(dev, bars);
2009 static int do_pci_enable_device(struct pci_dev *dev, int bars)
2012 struct pci_dev *bridge;
2016 err = pci_set_power_state(dev, PCI_D0);
2017 if (err < 0 && err != -EIO)
2020 bridge = pci_upstream_bridge(dev);
2022 pcie_aspm_powersave_config_link(bridge);
2024 err = pcibios_enable_device(dev, bars);
2027 pci_fixup_device(pci_fixup_enable, dev);
2029 if (dev->msi_enabled || dev->msix_enabled)
2032 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
2034 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2035 if (cmd & PCI_COMMAND_INTX_DISABLE)
2036 pci_write_config_word(dev, PCI_COMMAND,
2037 cmd & ~PCI_COMMAND_INTX_DISABLE);
2044 * pci_reenable_device - Resume abandoned device
2045 * @dev: PCI device to be resumed
2047 * NOTE: This function is a backend of pci_default_resume() and is not supposed
2048 * to be called by normal code, write proper resume handler and use it instead.
2050 int pci_reenable_device(struct pci_dev *dev)
2052 if (pci_is_enabled(dev))
2053 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
2056 EXPORT_SYMBOL(pci_reenable_device);
2058 static void pci_enable_bridge(struct pci_dev *dev)
2060 struct pci_dev *bridge;
2063 bridge = pci_upstream_bridge(dev);
2065 pci_enable_bridge(bridge);
2067 if (pci_is_enabled(dev)) {
2068 if (!dev->is_busmaster)
2069 pci_set_master(dev);
2073 retval = pci_enable_device(dev);
2075 pci_err(dev, "Error enabling bridge (%d), continuing\n",
2077 pci_set_master(dev);
2080 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
2082 struct pci_dev *bridge;
2087 * Power state could be unknown at this point, either due to a fresh
2088 * boot or a device removal call. So get the current power state
2089 * so that things like MSI message writing will behave as expected
2090 * (e.g. if the device really is in D0 at enable time).
2092 pci_update_current_state(dev, dev->current_state);
2094 if (atomic_inc_return(&dev->enable_cnt) > 1)
2095 return 0; /* already enabled */
2097 bridge = pci_upstream_bridge(dev);
2099 pci_enable_bridge(bridge);
2101 /* only skip sriov related */
2102 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2103 if (dev->resource[i].flags & flags)
2105 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2106 if (dev->resource[i].flags & flags)
2109 err = do_pci_enable_device(dev, bars);
2111 atomic_dec(&dev->enable_cnt);
2116 * pci_enable_device_io - Initialize a device for use with IO space
2117 * @dev: PCI device to be initialized
2119 * Initialize device before it's used by a driver. Ask low-level code
2120 * to enable I/O resources. Wake up the device if it was suspended.
2121 * Beware, this function can fail.
2123 int pci_enable_device_io(struct pci_dev *dev)
2125 return pci_enable_device_flags(dev, IORESOURCE_IO);
2127 EXPORT_SYMBOL(pci_enable_device_io);
2130 * pci_enable_device_mem - Initialize a device for use with Memory space
2131 * @dev: PCI device to be initialized
2133 * Initialize device before it's used by a driver. Ask low-level code
2134 * to enable Memory resources. Wake up the device if it was suspended.
2135 * Beware, this function can fail.
2137 int pci_enable_device_mem(struct pci_dev *dev)
2139 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2141 EXPORT_SYMBOL(pci_enable_device_mem);
2144 * pci_enable_device - Initialize device before it's used by a driver.
2145 * @dev: PCI device to be initialized
2147 * Initialize device before it's used by a driver. Ask low-level code
2148 * to enable I/O and memory. Wake up the device if it was suspended.
2149 * Beware, this function can fail.
2151 * Note we don't actually enable the device many times if we call
2152 * this function repeatedly (we just increment the count).
2154 int pci_enable_device(struct pci_dev *dev)
2156 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2158 EXPORT_SYMBOL(pci_enable_device);
2161 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2162 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2163 * there's no need to track it separately. pci_devres is initialized
2164 * when a device is enabled using managed PCI device enable interface.
2167 unsigned int enabled:1;
2168 unsigned int pinned:1;
2169 unsigned int orig_intx:1;
2170 unsigned int restore_intx:1;
2175 static void pcim_release(struct device *gendev, void *res)
2177 struct pci_dev *dev = to_pci_dev(gendev);
2178 struct pci_devres *this = res;
2181 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2182 if (this->region_mask & (1 << i))
2183 pci_release_region(dev, i);
2188 if (this->restore_intx)
2189 pci_intx(dev, this->orig_intx);
2191 if (this->enabled && !this->pinned)
2192 pci_disable_device(dev);
2195 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2197 struct pci_devres *dr, *new_dr;
2199 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2203 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2206 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2209 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2211 if (pci_is_managed(pdev))
2212 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2217 * pcim_enable_device - Managed pci_enable_device()
2218 * @pdev: PCI device to be initialized
2220 * Managed pci_enable_device().
2222 int pcim_enable_device(struct pci_dev *pdev)
2224 struct pci_devres *dr;
2227 dr = get_pci_dr(pdev);
2233 rc = pci_enable_device(pdev);
2235 pdev->is_managed = 1;
2240 EXPORT_SYMBOL(pcim_enable_device);
2243 * pcim_pin_device - Pin managed PCI device
2244 * @pdev: PCI device to pin
2246 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2247 * driver detach. @pdev must have been enabled with
2248 * pcim_enable_device().
2250 void pcim_pin_device(struct pci_dev *pdev)
2252 struct pci_devres *dr;
2254 dr = find_pci_dr(pdev);
2255 WARN_ON(!dr || !dr->enabled);
2259 EXPORT_SYMBOL(pcim_pin_device);
2262 * pcibios_device_add - provide arch specific hooks when adding device dev
2263 * @dev: the PCI device being added
2265 * Permits the platform to provide architecture specific functionality when
2266 * devices are added. This is the default implementation. Architecture
2267 * implementations can override this.
2269 int __weak pcibios_device_add(struct pci_dev *dev)
2275 * pcibios_release_device - provide arch specific hooks when releasing
2277 * @dev: the PCI device being released
2279 * Permits the platform to provide architecture specific functionality when
2280 * devices are released. This is the default implementation. Architecture
2281 * implementations can override this.
2283 void __weak pcibios_release_device(struct pci_dev *dev) {}
2286 * pcibios_disable_device - disable arch specific PCI resources for device dev
2287 * @dev: the PCI device to disable
2289 * Disables architecture specific PCI resources for the device. This
2290 * is the default implementation. Architecture implementations can
2293 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2296 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2297 * @irq: ISA IRQ to penalize
2298 * @active: IRQ active or not
2300 * Permits the platform to provide architecture-specific functionality when
2301 * penalizing ISA IRQs. This is the default implementation. Architecture
2302 * implementations can override this.
2304 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2306 static void do_pci_disable_device(struct pci_dev *dev)
2310 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2311 if (pci_command & PCI_COMMAND_MASTER) {
2312 pci_command &= ~PCI_COMMAND_MASTER;
2313 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2316 pcibios_disable_device(dev);
2320 * pci_disable_enabled_device - Disable device without updating enable_cnt
2321 * @dev: PCI device to disable
2323 * NOTE: This function is a backend of PCI power management routines and is
2324 * not supposed to be called drivers.
2326 void pci_disable_enabled_device(struct pci_dev *dev)
2328 if (pci_is_enabled(dev))
2329 do_pci_disable_device(dev);
2333 * pci_disable_device - Disable PCI device after use
2334 * @dev: PCI device to be disabled
2336 * Signal to the system that the PCI device is not in use by the system
2337 * anymore. This only involves disabling PCI bus-mastering, if active.
2339 * Note we don't actually disable the device until all callers of
2340 * pci_enable_device() have called pci_disable_device().
2342 void pci_disable_device(struct pci_dev *dev)
2344 struct pci_devres *dr;
2346 dr = find_pci_dr(dev);
2350 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2351 "disabling already-disabled device");
2353 if (atomic_dec_return(&dev->enable_cnt) != 0)
2356 do_pci_disable_device(dev);
2358 dev->is_busmaster = 0;
2360 EXPORT_SYMBOL(pci_disable_device);
2363 * pcibios_set_pcie_reset_state - set reset state for device dev
2364 * @dev: the PCIe device reset
2365 * @state: Reset state to enter into
2367 * Set the PCIe reset state for the device. This is the default
2368 * implementation. Architecture implementations can override this.
2370 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2371 enum pcie_reset_state state)
2377 * pci_set_pcie_reset_state - set reset state for device dev
2378 * @dev: the PCIe device reset
2379 * @state: Reset state to enter into
2381 * Sets the PCI reset state for the device.
2383 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2385 return pcibios_set_pcie_reset_state(dev, state);
2387 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2389 #ifdef CONFIG_PCIEAER
2390 void pcie_clear_device_status(struct pci_dev *dev)
2394 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2395 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2400 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2401 * @dev: PCIe root port or event collector.
2403 void pcie_clear_root_pme_status(struct pci_dev *dev)
2405 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2409 * pci_check_pme_status - Check if given device has generated PME.
2410 * @dev: Device to check.
2412 * Check the PME status of the device and if set, clear it and clear PME enable
2413 * (if set). Return 'true' if PME status and PME enable were both set or
2414 * 'false' otherwise.
2416 bool pci_check_pme_status(struct pci_dev *dev)
2425 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2426 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2427 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2430 /* Clear PME status. */
2431 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2432 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2433 /* Disable PME to avoid interrupt flood. */
2434 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2438 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2444 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2445 * @dev: Device to handle.
2446 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2448 * Check if @dev has generated PME and queue a resume request for it in that
2451 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2453 if (pme_poll_reset && dev->pme_poll)
2454 dev->pme_poll = false;
2456 if (pci_check_pme_status(dev)) {
2457 pci_wakeup_event(dev);
2458 pm_request_resume(&dev->dev);
2464 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2465 * @bus: Top bus of the subtree to walk.
2467 void pci_pme_wakeup_bus(struct pci_bus *bus)
2470 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2475 * pci_pme_capable - check the capability of PCI device to generate PME#
2476 * @dev: PCI device to handle.
2477 * @state: PCI state from which device will issue PME#.
2479 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2484 return !!(dev->pme_support & (1 << state));
2486 EXPORT_SYMBOL(pci_pme_capable);
2488 static void pci_pme_list_scan(struct work_struct *work)
2490 struct pci_pme_device *pme_dev, *n;
2492 mutex_lock(&pci_pme_list_mutex);
2493 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2494 struct pci_dev *pdev = pme_dev->dev;
2496 if (pdev->pme_poll) {
2497 struct pci_dev *bridge = pdev->bus->self;
2498 struct device *dev = &pdev->dev;
2502 * If bridge is in low power state, the
2503 * configuration space of subordinate devices
2504 * may be not accessible
2506 if (bridge && bridge->current_state != PCI_D0)
2510 * If the device is in a low power state it
2511 * should not be polled either.
2513 pm_status = pm_runtime_get_if_active(dev, true);
2517 if (pdev->current_state != PCI_D3cold)
2518 pci_pme_wakeup(pdev, NULL);
2521 pm_runtime_put(dev);
2523 list_del(&pme_dev->list);
2527 if (!list_empty(&pci_pme_list))
2528 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2529 msecs_to_jiffies(PME_TIMEOUT));
2530 mutex_unlock(&pci_pme_list_mutex);
2533 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2537 if (!dev->pme_support)
2540 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2541 /* Clear PME_Status by writing 1 to it and enable PME# */
2542 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2544 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2546 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2550 * pci_pme_restore - Restore PME configuration after config space restore.
2551 * @dev: PCI device to update.
2553 void pci_pme_restore(struct pci_dev *dev)
2557 if (!dev->pme_support)
2560 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2561 if (dev->wakeup_prepared) {
2562 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2563 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2565 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2566 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2568 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2572 * pci_pme_active - enable or disable PCI device's PME# function
2573 * @dev: PCI device to handle.
2574 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2576 * The caller must verify that the device is capable of generating PME# before
2577 * calling this function with @enable equal to 'true'.
2579 void pci_pme_active(struct pci_dev *dev, bool enable)
2581 __pci_pme_active(dev, enable);
2584 * PCI (as opposed to PCIe) PME requires that the device have
2585 * its PME# line hooked up correctly. Not all hardware vendors
2586 * do this, so the PME never gets delivered and the device
2587 * remains asleep. The easiest way around this is to
2588 * periodically walk the list of suspended devices and check
2589 * whether any have their PME flag set. The assumption is that
2590 * we'll wake up often enough anyway that this won't be a huge
2591 * hit, and the power savings from the devices will still be a
2594 * Although PCIe uses in-band PME message instead of PME# line
2595 * to report PME, PME does not work for some PCIe devices in
2596 * reality. For example, there are devices that set their PME
2597 * status bits, but don't really bother to send a PME message;
2598 * there are PCI Express Root Ports that don't bother to
2599 * trigger interrupts when they receive PME messages from the
2600 * devices below. So PME poll is used for PCIe devices too.
2603 if (dev->pme_poll) {
2604 struct pci_pme_device *pme_dev;
2606 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2609 pci_warn(dev, "can't enable PME#\n");
2613 mutex_lock(&pci_pme_list_mutex);
2614 list_add(&pme_dev->list, &pci_pme_list);
2615 if (list_is_singular(&pci_pme_list))
2616 queue_delayed_work(system_freezable_wq,
2618 msecs_to_jiffies(PME_TIMEOUT));
2619 mutex_unlock(&pci_pme_list_mutex);
2621 mutex_lock(&pci_pme_list_mutex);
2622 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2623 if (pme_dev->dev == dev) {
2624 list_del(&pme_dev->list);
2629 mutex_unlock(&pci_pme_list_mutex);
2633 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2635 EXPORT_SYMBOL(pci_pme_active);
2638 * __pci_enable_wake - enable PCI device as wakeup event source
2639 * @dev: PCI device affected
2640 * @state: PCI state from which device will issue wakeup events
2641 * @enable: True to enable event generation; false to disable
2643 * This enables the device as a wakeup event source, or disables it.
2644 * When such events involves platform-specific hooks, those hooks are
2645 * called automatically by this routine.
2647 * Devices with legacy power management (no standard PCI PM capabilities)
2648 * always require such platform hooks.
2651 * 0 is returned on success
2652 * -EINVAL is returned if device is not supposed to wake up the system
2653 * Error code depending on the platform is returned if both the platform and
2654 * the native mechanism fail to enable the generation of wake-up events
2656 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2661 * Bridges that are not power-manageable directly only signal
2662 * wakeup on behalf of subordinate devices which is set up
2663 * elsewhere, so skip them. However, bridges that are
2664 * power-manageable may signal wakeup for themselves (for example,
2665 * on a hotplug event) and they need to be covered here.
2667 if (!pci_power_manageable(dev))
2670 /* Don't do the same thing twice in a row for one device. */
2671 if (!!enable == !!dev->wakeup_prepared)
2675 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2676 * Anderson we should be doing PME# wake enable followed by ACPI wake
2677 * enable. To disable wake-up we call the platform first, for symmetry.
2684 * Enable PME signaling if the device can signal PME from
2685 * D3cold regardless of whether or not it can signal PME from
2686 * the current target state, because that will allow it to
2687 * signal PME when the hierarchy above it goes into D3cold and
2688 * the device itself ends up in D3cold as a result of that.
2690 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2691 pci_pme_active(dev, true);
2694 error = platform_pci_set_wakeup(dev, true);
2698 dev->wakeup_prepared = true;
2700 platform_pci_set_wakeup(dev, false);
2701 pci_pme_active(dev, false);
2702 dev->wakeup_prepared = false;
2709 * pci_enable_wake - change wakeup settings for a PCI device
2710 * @pci_dev: Target device
2711 * @state: PCI state from which device will issue wakeup events
2712 * @enable: Whether or not to enable event generation
2714 * If @enable is set, check device_may_wakeup() for the device before calling
2715 * __pci_enable_wake() for it.
2717 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2719 if (enable && !device_may_wakeup(&pci_dev->dev))
2722 return __pci_enable_wake(pci_dev, state, enable);
2724 EXPORT_SYMBOL(pci_enable_wake);
2727 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2728 * @dev: PCI device to prepare
2729 * @enable: True to enable wake-up event generation; false to disable
2731 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2732 * and this function allows them to set that up cleanly - pci_enable_wake()
2733 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2734 * ordering constraints.
2736 * This function only returns error code if the device is not allowed to wake
2737 * up the system from sleep or it is not capable of generating PME# from both
2738 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2740 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2742 return pci_pme_capable(dev, PCI_D3cold) ?
2743 pci_enable_wake(dev, PCI_D3cold, enable) :
2744 pci_enable_wake(dev, PCI_D3hot, enable);
2746 EXPORT_SYMBOL(pci_wake_from_d3);
2749 * pci_target_state - find an appropriate low power state for a given PCI dev
2751 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2753 * Use underlying platform code to find a supported low power state for @dev.
2754 * If the platform can't manage @dev, return the deepest state from which it
2755 * can generate wake events, based on any available PME info.
2757 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2759 if (platform_pci_power_manageable(dev)) {
2761 * Call the platform to find the target state for the device.
2763 pci_power_t state = platform_pci_choose_state(dev);
2766 case PCI_POWER_ERROR:
2772 if (pci_no_d1d2(dev))
2780 * If the device is in D3cold even though it's not power-manageable by
2781 * the platform, it may have been powered down by non-standard means.
2782 * Best to let it slumber.
2784 if (dev->current_state == PCI_D3cold)
2786 else if (!dev->pm_cap)
2789 if (wakeup && dev->pme_support) {
2790 pci_power_t state = PCI_D3hot;
2793 * Find the deepest state from which the device can generate
2796 while (state && !(dev->pme_support & (1 << state)))
2801 else if (dev->pme_support & 1)
2809 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2810 * into a sleep state
2811 * @dev: Device to handle.
2813 * Choose the power state appropriate for the device depending on whether
2814 * it can wake up the system and/or is power manageable by the platform
2815 * (PCI_D3hot is the default) and put the device into that state.
2817 int pci_prepare_to_sleep(struct pci_dev *dev)
2819 bool wakeup = device_may_wakeup(&dev->dev);
2820 pci_power_t target_state = pci_target_state(dev, wakeup);
2823 if (target_state == PCI_POWER_ERROR)
2826 pci_enable_wake(dev, target_state, wakeup);
2828 error = pci_set_power_state(dev, target_state);
2831 pci_enable_wake(dev, target_state, false);
2835 EXPORT_SYMBOL(pci_prepare_to_sleep);
2838 * pci_back_from_sleep - turn PCI device on during system-wide transition
2839 * into working state
2840 * @dev: Device to handle.
2842 * Disable device's system wake-up capability and put it into D0.
2844 int pci_back_from_sleep(struct pci_dev *dev)
2846 int ret = pci_set_power_state(dev, PCI_D0);
2851 pci_enable_wake(dev, PCI_D0, false);
2854 EXPORT_SYMBOL(pci_back_from_sleep);
2857 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2858 * @dev: PCI device being suspended.
2860 * Prepare @dev to generate wake-up events at run time and put it into a low
2863 int pci_finish_runtime_suspend(struct pci_dev *dev)
2865 pci_power_t target_state;
2868 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2869 if (target_state == PCI_POWER_ERROR)
2872 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2874 error = pci_set_power_state(dev, target_state);
2877 pci_enable_wake(dev, target_state, false);
2883 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2884 * @dev: Device to check.
2886 * Return true if the device itself is capable of generating wake-up events
2887 * (through the platform or using the native PCIe PME) or if the device supports
2888 * PME and one of its upstream bridges can generate wake-up events.
2890 bool pci_dev_run_wake(struct pci_dev *dev)
2892 struct pci_bus *bus = dev->bus;
2894 if (!dev->pme_support)
2897 /* PME-capable in principle, but not from the target power state */
2898 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2901 if (device_can_wakeup(&dev->dev))
2904 while (bus->parent) {
2905 struct pci_dev *bridge = bus->self;
2907 if (device_can_wakeup(&bridge->dev))
2913 /* We have reached the root bus. */
2915 return device_can_wakeup(bus->bridge);
2919 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2922 * pci_dev_need_resume - Check if it is necessary to resume the device.
2923 * @pci_dev: Device to check.
2925 * Return 'true' if the device is not runtime-suspended or it has to be
2926 * reconfigured due to wakeup settings difference between system and runtime
2927 * suspend, or the current power state of it is not suitable for the upcoming
2928 * (system-wide) transition.
2930 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2932 struct device *dev = &pci_dev->dev;
2933 pci_power_t target_state;
2935 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2938 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2941 * If the earlier platform check has not triggered, D3cold is just power
2942 * removal on top of D3hot, so no need to resume the device in that
2945 return target_state != pci_dev->current_state &&
2946 target_state != PCI_D3cold &&
2947 pci_dev->current_state != PCI_D3hot;
2951 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2952 * @pci_dev: Device to check.
2954 * If the device is suspended and it is not configured for system wakeup,
2955 * disable PME for it to prevent it from waking up the system unnecessarily.
2957 * Note that if the device's power state is D3cold and the platform check in
2958 * pci_dev_need_resume() has not triggered, the device's configuration need not
2961 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2963 struct device *dev = &pci_dev->dev;
2965 spin_lock_irq(&dev->power.lock);
2967 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2968 pci_dev->current_state < PCI_D3cold)
2969 __pci_pme_active(pci_dev, false);
2971 spin_unlock_irq(&dev->power.lock);
2975 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2976 * @pci_dev: Device to handle.
2978 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2979 * it might have been disabled during the prepare phase of system suspend if
2980 * the device was not configured for system wakeup.
2982 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2984 struct device *dev = &pci_dev->dev;
2986 if (!pci_dev_run_wake(pci_dev))
2989 spin_lock_irq(&dev->power.lock);
2991 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2992 __pci_pme_active(pci_dev, true);
2994 spin_unlock_irq(&dev->power.lock);
2998 * pci_choose_state - Choose the power state of a PCI device.
2999 * @dev: Target PCI device.
3000 * @state: Target state for the whole system.
3002 * Returns PCI power state suitable for @dev and @state.
3004 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
3006 if (state.event == PM_EVENT_ON)
3009 return pci_target_state(dev, false);
3011 EXPORT_SYMBOL(pci_choose_state);
3013 void pci_config_pm_runtime_get(struct pci_dev *pdev)
3015 struct device *dev = &pdev->dev;
3016 struct device *parent = dev->parent;
3019 pm_runtime_get_sync(parent);
3020 pm_runtime_get_noresume(dev);
3022 * pdev->current_state is set to PCI_D3cold during suspending,
3023 * so wait until suspending completes
3025 pm_runtime_barrier(dev);
3027 * Only need to resume devices in D3cold, because config
3028 * registers are still accessible for devices suspended but
3031 if (pdev->current_state == PCI_D3cold)
3032 pm_runtime_resume(dev);
3035 void pci_config_pm_runtime_put(struct pci_dev *pdev)
3037 struct device *dev = &pdev->dev;
3038 struct device *parent = dev->parent;
3040 pm_runtime_put(dev);
3042 pm_runtime_put_sync(parent);
3045 static const struct dmi_system_id bridge_d3_blacklist[] = {
3049 * Gigabyte X299 root port is not marked as hotplug capable
3050 * which allows Linux to power manage it. However, this
3051 * confuses the BIOS SMI handler so don't power manage root
3052 * ports on that system.
3054 .ident = "X299 DESIGNARE EX-CF",
3056 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
3057 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3062 * Downstream device is not accessible after putting a root port
3063 * into D3cold and back into D0 on Elo Continental Z2 board
3065 .ident = "Elo Continental Z2",
3067 DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"),
3068 DMI_MATCH(DMI_BOARD_NAME, "Geminilake"),
3069 DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"),
3077 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3078 * @bridge: Bridge to check
3080 * This function checks if it is possible to move the bridge to D3.
3081 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3083 bool pci_bridge_d3_possible(struct pci_dev *bridge)
3085 if (!pci_is_pcie(bridge))
3088 switch (pci_pcie_type(bridge)) {
3089 case PCI_EXP_TYPE_ROOT_PORT:
3090 case PCI_EXP_TYPE_UPSTREAM:
3091 case PCI_EXP_TYPE_DOWNSTREAM:
3092 if (pci_bridge_d3_disable)
3096 * Hotplug ports handled by firmware in System Management Mode
3097 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
3099 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
3102 if (pci_bridge_d3_force)
3105 /* Even the oldest 2010 Thunderbolt controller supports D3. */
3106 if (bridge->is_thunderbolt)
3109 /* Platform might know better if the bridge supports D3 */
3110 if (platform_pci_bridge_d3(bridge))
3114 * Hotplug ports handled natively by the OS were not validated
3115 * by vendors for runtime D3 at least until 2018 because there
3116 * was no OS support.
3118 if (bridge->is_hotplug_bridge)
3121 if (dmi_check_system(bridge_d3_blacklist))
3125 * It should be safe to put PCIe ports from 2015 or newer
3128 if (dmi_get_bios_year() >= 2015)
3136 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3138 bool *d3cold_ok = data;
3140 if (/* The device needs to be allowed to go D3cold ... */
3141 dev->no_d3cold || !dev->d3cold_allowed ||
3143 /* ... and if it is wakeup capable to do so from D3cold. */
3144 (device_may_wakeup(&dev->dev) &&
3145 !pci_pme_capable(dev, PCI_D3cold)) ||
3147 /* If it is a bridge it must be allowed to go to D3. */
3148 !pci_power_manageable(dev))
3156 * pci_bridge_d3_update - Update bridge D3 capabilities
3157 * @dev: PCI device which is changed
3159 * Update upstream bridge PM capabilities accordingly depending on if the
3160 * device PM configuration was changed or the device is being removed. The
3161 * change is also propagated upstream.
3163 void pci_bridge_d3_update(struct pci_dev *dev)
3165 bool remove = !device_is_registered(&dev->dev);
3166 struct pci_dev *bridge;
3167 bool d3cold_ok = true;
3169 bridge = pci_upstream_bridge(dev);
3170 if (!bridge || !pci_bridge_d3_possible(bridge))
3174 * If D3 is currently allowed for the bridge, removing one of its
3175 * children won't change that.
3177 if (remove && bridge->bridge_d3)
3181 * If D3 is currently allowed for the bridge and a child is added or
3182 * changed, disallowance of D3 can only be caused by that child, so
3183 * we only need to check that single device, not any of its siblings.
3185 * If D3 is currently not allowed for the bridge, checking the device
3186 * first may allow us to skip checking its siblings.
3189 pci_dev_check_d3cold(dev, &d3cold_ok);
3192 * If D3 is currently not allowed for the bridge, this may be caused
3193 * either by the device being changed/removed or any of its siblings,
3194 * so we need to go through all children to find out if one of them
3195 * continues to block D3.
3197 if (d3cold_ok && !bridge->bridge_d3)
3198 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3201 if (bridge->bridge_d3 != d3cold_ok) {
3202 bridge->bridge_d3 = d3cold_ok;
3203 /* Propagate change to upstream bridges */
3204 pci_bridge_d3_update(bridge);
3209 * pci_d3cold_enable - Enable D3cold for device
3210 * @dev: PCI device to handle
3212 * This function can be used in drivers to enable D3cold from the device
3213 * they handle. It also updates upstream PCI bridge PM capabilities
3216 void pci_d3cold_enable(struct pci_dev *dev)
3218 if (dev->no_d3cold) {
3219 dev->no_d3cold = false;
3220 pci_bridge_d3_update(dev);
3223 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3226 * pci_d3cold_disable - Disable D3cold for device
3227 * @dev: PCI device to handle
3229 * This function can be used in drivers to disable D3cold from the device
3230 * they handle. It also updates upstream PCI bridge PM capabilities
3233 void pci_d3cold_disable(struct pci_dev *dev)
3235 if (!dev->no_d3cold) {
3236 dev->no_d3cold = true;
3237 pci_bridge_d3_update(dev);
3240 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3243 * pci_pm_init - Initialize PM functions of given PCI device
3244 * @dev: PCI device to handle.
3246 void pci_pm_init(struct pci_dev *dev)
3252 pm_runtime_forbid(&dev->dev);
3253 pm_runtime_set_active(&dev->dev);
3254 pm_runtime_enable(&dev->dev);
3255 device_enable_async_suspend(&dev->dev);
3256 dev->wakeup_prepared = false;
3259 dev->pme_support = 0;
3261 /* find PCI PM capability in list */
3262 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3265 /* Check device's ability to generate PME# */
3266 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3268 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3269 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3270 pmc & PCI_PM_CAP_VER_MASK);
3275 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3276 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3277 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3278 dev->d3cold_allowed = true;
3280 dev->d1_support = false;
3281 dev->d2_support = false;
3282 if (!pci_no_d1d2(dev)) {
3283 if (pmc & PCI_PM_CAP_D1)
3284 dev->d1_support = true;
3285 if (pmc & PCI_PM_CAP_D2)
3286 dev->d2_support = true;
3288 if (dev->d1_support || dev->d2_support)
3289 pci_info(dev, "supports%s%s\n",
3290 dev->d1_support ? " D1" : "",
3291 dev->d2_support ? " D2" : "");
3294 pmc &= PCI_PM_CAP_PME_MASK;
3296 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3297 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3298 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3299 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3300 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3301 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3302 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc);
3303 dev->pme_poll = true;
3305 * Make device's PM flags reflect the wake-up capability, but
3306 * let the user space enable it to wake up the system as needed.
3308 device_set_wakeup_capable(&dev->dev, true);
3309 /* Disable the PME# generation functionality */
3310 pci_pme_active(dev, false);
3313 pci_read_config_word(dev, PCI_STATUS, &status);
3314 if (status & PCI_STATUS_IMM_READY)
3318 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3320 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3324 case PCI_EA_P_VF_MEM:
3325 flags |= IORESOURCE_MEM;
3327 case PCI_EA_P_MEM_PREFETCH:
3328 case PCI_EA_P_VF_MEM_PREFETCH:
3329 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3332 flags |= IORESOURCE_IO;
3341 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3344 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3345 return &dev->resource[bei];
3346 #ifdef CONFIG_PCI_IOV
3347 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3348 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3349 return &dev->resource[PCI_IOV_RESOURCES +
3350 bei - PCI_EA_BEI_VF_BAR0];
3352 else if (bei == PCI_EA_BEI_ROM)
3353 return &dev->resource[PCI_ROM_RESOURCE];
3358 /* Read an Enhanced Allocation (EA) entry */
3359 static int pci_ea_read(struct pci_dev *dev, int offset)
3361 struct resource *res;
3362 const char *res_name;
3363 int ent_size, ent_offset = offset;
3364 resource_size_t start, end;
3365 unsigned long flags;
3366 u32 dw0, bei, base, max_offset;
3368 bool support_64 = (sizeof(resource_size_t) >= 8);
3370 pci_read_config_dword(dev, ent_offset, &dw0);
3373 /* Entry size field indicates DWORDs after 1st */
3374 ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2;
3376 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3379 bei = FIELD_GET(PCI_EA_BEI, dw0);
3380 prop = FIELD_GET(PCI_EA_PP, dw0);
3383 * If the Property is in the reserved range, try the Secondary
3386 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3387 prop = FIELD_GET(PCI_EA_SP, dw0);
3388 if (prop > PCI_EA_P_BRIDGE_IO)
3391 res = pci_ea_get_resource(dev, bei, prop);
3392 res_name = pci_resource_name(dev, bei);
3394 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3398 flags = pci_ea_flags(dev, prop);
3400 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3405 pci_read_config_dword(dev, ent_offset, &base);
3406 start = (base & PCI_EA_FIELD_MASK);
3409 /* Read MaxOffset */
3410 pci_read_config_dword(dev, ent_offset, &max_offset);
3413 /* Read Base MSBs (if 64-bit entry) */
3414 if (base & PCI_EA_IS_64) {
3417 pci_read_config_dword(dev, ent_offset, &base_upper);
3420 flags |= IORESOURCE_MEM_64;
3422 /* entry starts above 32-bit boundary, can't use */
3423 if (!support_64 && base_upper)
3427 start |= ((u64)base_upper << 32);
3430 end = start + (max_offset | 0x03);
3432 /* Read MaxOffset MSBs (if 64-bit entry) */
3433 if (max_offset & PCI_EA_IS_64) {
3434 u32 max_offset_upper;
3436 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3439 flags |= IORESOURCE_MEM_64;
3441 /* entry too big, can't use */
3442 if (!support_64 && max_offset_upper)
3446 end += ((u64)max_offset_upper << 32);
3450 pci_err(dev, "EA Entry crosses address boundary\n");
3454 if (ent_size != ent_offset - offset) {
3455 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3456 ent_size, ent_offset - offset);
3460 res->name = pci_name(dev);
3465 if (bei <= PCI_EA_BEI_BAR5)
3466 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3467 res_name, res, prop);
3468 else if (bei == PCI_EA_BEI_ROM)
3469 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3470 res_name, res, prop);
3471 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3472 pci_info(dev, "%s %pR: from Enhanced Allocation, properties %#02x\n",
3473 res_name, res, prop);
3475 pci_info(dev, "BEI %d %pR: from Enhanced Allocation, properties %#02x\n",
3479 return offset + ent_size;
3482 /* Enhanced Allocation Initialization */
3483 void pci_ea_init(struct pci_dev *dev)
3490 /* find PCI EA capability in list */
3491 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3495 /* determine the number of entries */
3496 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3498 num_ent &= PCI_EA_NUM_ENT_MASK;
3500 offset = ea + PCI_EA_FIRST_ENT;
3502 /* Skip DWORD 2 for type 1 functions */
3503 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3506 /* parse each EA entry */
3507 for (i = 0; i < num_ent; ++i)
3508 offset = pci_ea_read(dev, offset);
3511 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3512 struct pci_cap_saved_state *new_cap)
3514 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3518 * _pci_add_cap_save_buffer - allocate buffer for saving given
3519 * capability registers
3520 * @dev: the PCI device
3521 * @cap: the capability to allocate the buffer for
3522 * @extended: Standard or Extended capability ID
3523 * @size: requested size of the buffer
3525 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3526 bool extended, unsigned int size)
3529 struct pci_cap_saved_state *save_state;
3532 pos = pci_find_ext_capability(dev, cap);
3534 pos = pci_find_capability(dev, cap);
3539 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3543 save_state->cap.cap_nr = cap;
3544 save_state->cap.cap_extended = extended;
3545 save_state->cap.size = size;
3546 pci_add_saved_cap(dev, save_state);
3551 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3553 return _pci_add_cap_save_buffer(dev, cap, false, size);
3556 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3558 return _pci_add_cap_save_buffer(dev, cap, true, size);
3562 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3563 * @dev: the PCI device
3565 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3569 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3570 PCI_EXP_SAVE_REGS * sizeof(u16));
3572 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3574 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3576 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3578 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3581 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3583 pci_allocate_vc_save_buffers(dev);
3586 void pci_free_cap_save_buffers(struct pci_dev *dev)
3588 struct pci_cap_saved_state *tmp;
3589 struct hlist_node *n;
3591 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3596 * pci_configure_ari - enable or disable ARI forwarding
3597 * @dev: the PCI device
3599 * If @dev and its upstream bridge both support ARI, enable ARI in the
3600 * bridge. Otherwise, disable ARI in the bridge.
3602 void pci_configure_ari(struct pci_dev *dev)
3605 struct pci_dev *bridge;
3607 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3610 bridge = dev->bus->self;
3614 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3615 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3618 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3619 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3620 PCI_EXP_DEVCTL2_ARI);
3621 bridge->ari_enabled = 1;
3623 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3624 PCI_EXP_DEVCTL2_ARI);
3625 bridge->ari_enabled = 0;
3629 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3634 pos = pdev->acs_cap;
3639 * Except for egress control, capabilities are either required
3640 * or only required if controllable. Features missing from the
3641 * capability field can therefore be assumed as hard-wired enabled.
3643 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3644 acs_flags &= (cap | PCI_ACS_EC);
3646 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3647 return (ctrl & acs_flags) == acs_flags;
3651 * pci_acs_enabled - test ACS against required flags for a given device
3652 * @pdev: device to test
3653 * @acs_flags: required PCI ACS flags
3655 * Return true if the device supports the provided flags. Automatically
3656 * filters out flags that are not implemented on multifunction devices.
3658 * Note that this interface checks the effective ACS capabilities of the
3659 * device rather than the actual capabilities. For instance, most single
3660 * function endpoints are not required to support ACS because they have no
3661 * opportunity for peer-to-peer access. We therefore return 'true'
3662 * regardless of whether the device exposes an ACS capability. This makes
3663 * it much easier for callers of this function to ignore the actual type
3664 * or topology of the device when testing ACS support.
3666 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3670 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3675 * Conventional PCI and PCI-X devices never support ACS, either
3676 * effectively or actually. The shared bus topology implies that
3677 * any device on the bus can receive or snoop DMA.
3679 if (!pci_is_pcie(pdev))
3682 switch (pci_pcie_type(pdev)) {
3684 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3685 * but since their primary interface is PCI/X, we conservatively
3686 * handle them as we would a non-PCIe device.
3688 case PCI_EXP_TYPE_PCIE_BRIDGE:
3690 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3691 * applicable... must never implement an ACS Extended Capability...".
3692 * This seems arbitrary, but we take a conservative interpretation
3693 * of this statement.
3695 case PCI_EXP_TYPE_PCI_BRIDGE:
3696 case PCI_EXP_TYPE_RC_EC:
3699 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3700 * implement ACS in order to indicate their peer-to-peer capabilities,
3701 * regardless of whether they are single- or multi-function devices.
3703 case PCI_EXP_TYPE_DOWNSTREAM:
3704 case PCI_EXP_TYPE_ROOT_PORT:
3705 return pci_acs_flags_enabled(pdev, acs_flags);
3707 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3708 * implemented by the remaining PCIe types to indicate peer-to-peer
3709 * capabilities, but only when they are part of a multifunction
3710 * device. The footnote for section 6.12 indicates the specific
3711 * PCIe types included here.
3713 case PCI_EXP_TYPE_ENDPOINT:
3714 case PCI_EXP_TYPE_UPSTREAM:
3715 case PCI_EXP_TYPE_LEG_END:
3716 case PCI_EXP_TYPE_RC_END:
3717 if (!pdev->multifunction)
3720 return pci_acs_flags_enabled(pdev, acs_flags);
3724 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3725 * to single function devices with the exception of downstream ports.
3731 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3732 * @start: starting downstream device
3733 * @end: ending upstream device or NULL to search to the root bus
3734 * @acs_flags: required flags
3736 * Walk up a device tree from start to end testing PCI ACS support. If
3737 * any step along the way does not support the required flags, return false.
3739 bool pci_acs_path_enabled(struct pci_dev *start,
3740 struct pci_dev *end, u16 acs_flags)
3742 struct pci_dev *pdev, *parent = start;
3747 if (!pci_acs_enabled(pdev, acs_flags))
3750 if (pci_is_root_bus(pdev->bus))
3751 return (end == NULL);
3753 parent = pdev->bus->self;
3754 } while (pdev != end);
3760 * pci_acs_init - Initialize ACS if hardware supports it
3761 * @dev: the PCI device
3763 void pci_acs_init(struct pci_dev *dev)
3765 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3768 * Attempt to enable ACS regardless of capability because some Root
3769 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3770 * the standard ACS capability but still support ACS via those
3773 pci_enable_acs(dev);
3777 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3781 * Helper to find the position of the ctrl register for a BAR.
3782 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3783 * Returns -ENOENT if no ctrl register for the BAR could be found.
3785 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3787 unsigned int pos, nbars, i;
3790 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3794 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3795 nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
3797 for (i = 0; i < nbars; i++, pos += 8) {
3800 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3801 bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
3810 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3812 * @bar: BAR to query
3814 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3815 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3817 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3822 pos = pci_rebar_find_pos(pdev, bar);
3826 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3827 cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap);
3829 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3830 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3831 bar == 0 && cap == 0x700)
3836 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3839 * pci_rebar_get_current_size - get the current size of a BAR
3841 * @bar: BAR to set size to
3843 * Read the size of a BAR from the resizable BAR config.
3844 * Returns size if found or negative error code.
3846 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3851 pos = pci_rebar_find_pos(pdev, bar);
3855 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3856 return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl);
3860 * pci_rebar_set_size - set a new size for a BAR
3862 * @bar: BAR to set size to
3863 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3865 * Set the new size of a BAR as defined in the spec.
3866 * Returns zero if resizing was successful, error code otherwise.
3868 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3873 pos = pci_rebar_find_pos(pdev, bar);
3877 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3878 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3879 ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
3880 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3885 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3886 * @dev: the PCI device
3887 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3888 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3889 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3890 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3892 * Return 0 if all upstream bridges support AtomicOp routing, egress
3893 * blocking is disabled on all upstream ports, and the root port supports
3894 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3895 * AtomicOp completion), or negative otherwise.
3897 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3899 struct pci_bus *bus = dev->bus;
3900 struct pci_dev *bridge;
3904 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3905 * in Device Control 2 is reserved in VFs and the PF value applies
3906 * to all associated VFs.
3911 if (!pci_is_pcie(dev))
3915 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3916 * AtomicOp requesters. For now, we only support endpoints as
3917 * requesters and root ports as completers. No endpoints as
3918 * completers, and no peer-to-peer.
3921 switch (pci_pcie_type(dev)) {
3922 case PCI_EXP_TYPE_ENDPOINT:
3923 case PCI_EXP_TYPE_LEG_END:
3924 case PCI_EXP_TYPE_RC_END:
3930 while (bus->parent) {
3933 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3935 switch (pci_pcie_type(bridge)) {
3936 /* Ensure switch ports support AtomicOp routing */
3937 case PCI_EXP_TYPE_UPSTREAM:
3938 case PCI_EXP_TYPE_DOWNSTREAM:
3939 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3943 /* Ensure root port supports all the sizes we care about */
3944 case PCI_EXP_TYPE_ROOT_PORT:
3945 if ((cap & cap_mask) != cap_mask)
3950 /* Ensure upstream ports don't block AtomicOps on egress */
3951 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3952 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3954 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3961 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3962 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3965 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3968 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3969 * @dev: the PCI device
3970 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3972 * Perform INTx swizzling for a device behind one level of bridge. This is
3973 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3974 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3975 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3976 * the PCI Express Base Specification, Revision 2.1)
3978 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3982 if (pci_ari_enabled(dev->bus))
3985 slot = PCI_SLOT(dev->devfn);
3987 return (((pin - 1) + slot) % 4) + 1;
3990 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3998 while (!pci_is_root_bus(dev->bus)) {
3999 pin = pci_swizzle_interrupt_pin(dev, pin);
4000 dev = dev->bus->self;
4007 * pci_common_swizzle - swizzle INTx all the way to root bridge
4008 * @dev: the PCI device
4009 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
4011 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4012 * bridges all the way up to a PCI root bus.
4014 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
4018 while (!pci_is_root_bus(dev->bus)) {
4019 pin = pci_swizzle_interrupt_pin(dev, pin);
4020 dev = dev->bus->self;
4023 return PCI_SLOT(dev->devfn);
4025 EXPORT_SYMBOL_GPL(pci_common_swizzle);
4028 * pci_release_region - Release a PCI bar
4029 * @pdev: PCI device whose resources were previously reserved by
4030 * pci_request_region()
4031 * @bar: BAR to release
4033 * Releases the PCI I/O and memory resources previously reserved by a
4034 * successful call to pci_request_region(). Call this function only
4035 * after all use of the PCI regions has ceased.
4037 void pci_release_region(struct pci_dev *pdev, int bar)
4039 struct pci_devres *dr;
4041 if (pci_resource_len(pdev, bar) == 0)
4043 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
4044 release_region(pci_resource_start(pdev, bar),
4045 pci_resource_len(pdev, bar));
4046 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
4047 release_mem_region(pci_resource_start(pdev, bar),
4048 pci_resource_len(pdev, bar));
4050 dr = find_pci_dr(pdev);
4052 dr->region_mask &= ~(1 << bar);
4054 EXPORT_SYMBOL(pci_release_region);
4057 * __pci_request_region - Reserved PCI I/O and memory resource
4058 * @pdev: PCI device whose resources are to be reserved
4059 * @bar: BAR to be reserved
4060 * @res_name: Name to be associated with resource.
4061 * @exclusive: whether the region access is exclusive or not
4063 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4064 * being reserved by owner @res_name. Do not access any
4065 * address inside the PCI regions unless this call returns
4068 * If @exclusive is set, then the region is marked so that userspace
4069 * is explicitly not allowed to map the resource via /dev/mem or
4070 * sysfs MMIO access.
4072 * Returns 0 on success, or %EBUSY on error. A warning
4073 * message is also printed on failure.
4075 static int __pci_request_region(struct pci_dev *pdev, int bar,
4076 const char *res_name, int exclusive)
4078 struct pci_devres *dr;
4080 if (pci_resource_len(pdev, bar) == 0)
4083 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
4084 if (!request_region(pci_resource_start(pdev, bar),
4085 pci_resource_len(pdev, bar), res_name))
4087 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
4088 if (!__request_mem_region(pci_resource_start(pdev, bar),
4089 pci_resource_len(pdev, bar), res_name,
4094 dr = find_pci_dr(pdev);
4096 dr->region_mask |= 1 << bar;
4101 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
4102 &pdev->resource[bar]);
4107 * pci_request_region - Reserve PCI I/O and memory resource
4108 * @pdev: PCI device whose resources are to be reserved
4109 * @bar: BAR to be reserved
4110 * @res_name: Name to be associated with resource
4112 * Mark the PCI region associated with PCI device @pdev BAR @bar as
4113 * being reserved by owner @res_name. Do not access any
4114 * address inside the PCI regions unless this call returns
4117 * Returns 0 on success, or %EBUSY on error. A warning
4118 * message is also printed on failure.
4120 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4122 return __pci_request_region(pdev, bar, res_name, 0);
4124 EXPORT_SYMBOL(pci_request_region);
4127 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4128 * @pdev: PCI device whose resources were previously reserved
4129 * @bars: Bitmask of BARs to be released
4131 * Release selected PCI I/O and memory resources previously reserved.
4132 * Call this function only after all use of the PCI regions has ceased.
4134 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4138 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4139 if (bars & (1 << i))
4140 pci_release_region(pdev, i);
4142 EXPORT_SYMBOL(pci_release_selected_regions);
4144 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4145 const char *res_name, int excl)
4149 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4150 if (bars & (1 << i))
4151 if (__pci_request_region(pdev, i, res_name, excl))
4157 if (bars & (1 << i))
4158 pci_release_region(pdev, i);
4165 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4166 * @pdev: PCI device whose resources are to be reserved
4167 * @bars: Bitmask of BARs to be requested
4168 * @res_name: Name to be associated with resource
4170 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4171 const char *res_name)
4173 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4175 EXPORT_SYMBOL(pci_request_selected_regions);
4177 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4178 const char *res_name)
4180 return __pci_request_selected_regions(pdev, bars, res_name,
4181 IORESOURCE_EXCLUSIVE);
4183 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4186 * pci_release_regions - Release reserved PCI I/O and memory resources
4187 * @pdev: PCI device whose resources were previously reserved by
4188 * pci_request_regions()
4190 * Releases all PCI I/O and memory resources previously reserved by a
4191 * successful call to pci_request_regions(). Call this function only
4192 * after all use of the PCI regions has ceased.
4195 void pci_release_regions(struct pci_dev *pdev)
4197 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4199 EXPORT_SYMBOL(pci_release_regions);
4202 * pci_request_regions - Reserve PCI I/O and memory resources
4203 * @pdev: PCI device whose resources are to be reserved
4204 * @res_name: Name to be associated with resource.
4206 * Mark all PCI regions associated with PCI device @pdev as
4207 * being reserved by owner @res_name. Do not access any
4208 * address inside the PCI regions unless this call returns
4211 * Returns 0 on success, or %EBUSY on error. A warning
4212 * message is also printed on failure.
4214 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4216 return pci_request_selected_regions(pdev,
4217 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4219 EXPORT_SYMBOL(pci_request_regions);
4222 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4223 * @pdev: PCI device whose resources are to be reserved
4224 * @res_name: Name to be associated with resource.
4226 * Mark all PCI regions associated with PCI device @pdev as being reserved
4227 * by owner @res_name. Do not access any address inside the PCI regions
4228 * unless this call returns successfully.
4230 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4231 * and the sysfs MMIO access will not be allowed.
4233 * Returns 0 on success, or %EBUSY on error. A warning message is also
4234 * printed on failure.
4236 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4238 return pci_request_selected_regions_exclusive(pdev,
4239 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4241 EXPORT_SYMBOL(pci_request_regions_exclusive);
4244 * Record the PCI IO range (expressed as CPU physical address + size).
4245 * Return a negative value if an error has occurred, zero otherwise
4247 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4248 resource_size_t size)
4252 struct logic_pio_hwaddr *range;
4254 if (!size || addr + size < addr)
4257 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4261 range->fwnode = fwnode;
4263 range->hw_start = addr;
4264 range->flags = LOGIC_PIO_CPU_MMIO;
4266 ret = logic_pio_register_range(range);
4270 /* Ignore duplicates due to deferred probing */
4278 phys_addr_t pci_pio_to_address(unsigned long pio)
4281 if (pio < MMIO_UPPER_LIMIT)
4282 return logic_pio_to_hwaddr(pio);
4285 return (phys_addr_t) OF_BAD_ADDR;
4287 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4289 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4292 return logic_pio_trans_cpuaddr(address);
4294 if (address > IO_SPACE_LIMIT)
4295 return (unsigned long)-1;
4297 return (unsigned long) address;
4302 * pci_remap_iospace - Remap the memory mapped I/O space
4303 * @res: Resource describing the I/O space
4304 * @phys_addr: physical address of range to be mapped
4306 * Remap the memory mapped I/O space described by the @res and the CPU
4307 * physical address @phys_addr into virtual address space. Only
4308 * architectures that have memory mapped IO functions defined (and the
4309 * PCI_IOBASE value defined) should call this function.
4311 #ifndef pci_remap_iospace
4312 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4314 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4315 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4317 if (!(res->flags & IORESOURCE_IO))
4320 if (res->end > IO_SPACE_LIMIT)
4323 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4324 pgprot_device(PAGE_KERNEL));
4327 * This architecture does not have memory mapped I/O space,
4328 * so this function should never be called
4330 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4334 EXPORT_SYMBOL(pci_remap_iospace);
4338 * pci_unmap_iospace - Unmap the memory mapped I/O space
4339 * @res: resource to be unmapped
4341 * Unmap the CPU virtual address @res from virtual address space. Only
4342 * architectures that have memory mapped IO functions defined (and the
4343 * PCI_IOBASE value defined) should call this function.
4345 void pci_unmap_iospace(struct resource *res)
4347 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4348 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4350 vunmap_range(vaddr, vaddr + resource_size(res));
4353 EXPORT_SYMBOL(pci_unmap_iospace);
4355 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4357 struct resource **res = ptr;
4359 pci_unmap_iospace(*res);
4363 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4364 * @dev: Generic device to remap IO address for
4365 * @res: Resource describing the I/O space
4366 * @phys_addr: physical address of range to be mapped
4368 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4371 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4372 phys_addr_t phys_addr)
4374 const struct resource **ptr;
4377 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4381 error = pci_remap_iospace(res, phys_addr);
4386 devres_add(dev, ptr);
4391 EXPORT_SYMBOL(devm_pci_remap_iospace);
4394 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4395 * @dev: Generic device to remap IO address for
4396 * @offset: Resource address to map
4397 * @size: Size of map
4399 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4402 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4403 resource_size_t offset,
4404 resource_size_t size)
4406 void __iomem **ptr, *addr;
4408 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4412 addr = pci_remap_cfgspace(offset, size);
4415 devres_add(dev, ptr);
4421 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4424 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4425 * @dev: generic device to handle the resource for
4426 * @res: configuration space resource to be handled
4428 * Checks that a resource is a valid memory region, requests the memory
4429 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4430 * proper PCI configuration space memory attributes are guaranteed.
4432 * All operations are managed and will be undone on driver detach.
4434 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4435 * on failure. Usage example::
4437 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4438 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4440 * return PTR_ERR(base);
4442 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4443 struct resource *res)
4445 resource_size_t size;
4447 void __iomem *dest_ptr;
4451 if (!res || resource_type(res) != IORESOURCE_MEM) {
4452 dev_err(dev, "invalid resource\n");
4453 return IOMEM_ERR_PTR(-EINVAL);
4456 size = resource_size(res);
4459 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4462 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4464 return IOMEM_ERR_PTR(-ENOMEM);
4466 if (!devm_request_mem_region(dev, res->start, size, name)) {
4467 dev_err(dev, "can't request region for resource %pR\n", res);
4468 return IOMEM_ERR_PTR(-EBUSY);
4471 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4473 dev_err(dev, "ioremap failed for resource %pR\n", res);
4474 devm_release_mem_region(dev, res->start, size);
4475 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4480 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4482 static void __pci_set_master(struct pci_dev *dev, bool enable)
4486 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4488 cmd = old_cmd | PCI_COMMAND_MASTER;
4490 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4491 if (cmd != old_cmd) {
4492 pci_dbg(dev, "%s bus mastering\n",
4493 enable ? "enabling" : "disabling");
4494 pci_write_config_word(dev, PCI_COMMAND, cmd);
4496 dev->is_busmaster = enable;
4500 * pcibios_setup - process "pci=" kernel boot arguments
4501 * @str: string used to pass in "pci=" kernel boot arguments
4503 * Process kernel boot arguments. This is the default implementation.
4504 * Architecture specific implementations can override this as necessary.
4506 char * __weak __init pcibios_setup(char *str)
4512 * pcibios_set_master - enable PCI bus-mastering for device dev
4513 * @dev: the PCI device to enable
4515 * Enables PCI bus-mastering for the device. This is the default
4516 * implementation. Architecture specific implementations can override
4517 * this if necessary.
4519 void __weak pcibios_set_master(struct pci_dev *dev)
4523 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4524 if (pci_is_pcie(dev))
4527 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4529 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4530 else if (lat > pcibios_max_latency)
4531 lat = pcibios_max_latency;
4535 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4539 * pci_set_master - enables bus-mastering for device dev
4540 * @dev: the PCI device to enable
4542 * Enables bus-mastering on the device and calls pcibios_set_master()
4543 * to do the needed arch specific settings.
4545 void pci_set_master(struct pci_dev *dev)
4547 __pci_set_master(dev, true);
4548 pcibios_set_master(dev);
4550 EXPORT_SYMBOL(pci_set_master);
4553 * pci_clear_master - disables bus-mastering for device dev
4554 * @dev: the PCI device to disable
4556 void pci_clear_master(struct pci_dev *dev)
4558 __pci_set_master(dev, false);
4560 EXPORT_SYMBOL(pci_clear_master);
4563 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4564 * @dev: the PCI device for which MWI is to be enabled
4566 * Helper function for pci_set_mwi.
4567 * Originally copied from drivers/net/acenic.c.
4568 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4570 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4572 int pci_set_cacheline_size(struct pci_dev *dev)
4576 if (!pci_cache_line_size)
4579 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4580 equal to or multiple of the right value. */
4581 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4582 if (cacheline_size >= pci_cache_line_size &&
4583 (cacheline_size % pci_cache_line_size) == 0)
4586 /* Write the correct value. */
4587 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4589 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4590 if (cacheline_size == pci_cache_line_size)
4593 pci_dbg(dev, "cache line size of %d is not supported\n",
4594 pci_cache_line_size << 2);
4598 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4601 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4602 * @dev: the PCI device for which MWI is enabled
4604 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4606 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4608 int pci_set_mwi(struct pci_dev *dev)
4610 #ifdef PCI_DISABLE_MWI
4616 rc = pci_set_cacheline_size(dev);
4620 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4621 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4622 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4623 cmd |= PCI_COMMAND_INVALIDATE;
4624 pci_write_config_word(dev, PCI_COMMAND, cmd);
4629 EXPORT_SYMBOL(pci_set_mwi);
4632 * pcim_set_mwi - a device-managed pci_set_mwi()
4633 * @dev: the PCI device for which MWI is enabled
4635 * Managed pci_set_mwi().
4637 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4639 int pcim_set_mwi(struct pci_dev *dev)
4641 struct pci_devres *dr;
4643 dr = find_pci_dr(dev);
4648 return pci_set_mwi(dev);
4650 EXPORT_SYMBOL(pcim_set_mwi);
4653 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4654 * @dev: the PCI device for which MWI is enabled
4656 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4657 * Callers are not required to check the return value.
4659 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4661 int pci_try_set_mwi(struct pci_dev *dev)
4663 #ifdef PCI_DISABLE_MWI
4666 return pci_set_mwi(dev);
4669 EXPORT_SYMBOL(pci_try_set_mwi);
4672 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4673 * @dev: the PCI device to disable
4675 * Disables PCI Memory-Write-Invalidate transaction on the device
4677 void pci_clear_mwi(struct pci_dev *dev)
4679 #ifndef PCI_DISABLE_MWI
4682 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4683 if (cmd & PCI_COMMAND_INVALIDATE) {
4684 cmd &= ~PCI_COMMAND_INVALIDATE;
4685 pci_write_config_word(dev, PCI_COMMAND, cmd);
4689 EXPORT_SYMBOL(pci_clear_mwi);
4692 * pci_disable_parity - disable parity checking for device
4693 * @dev: the PCI device to operate on
4695 * Disable parity checking for device @dev
4697 void pci_disable_parity(struct pci_dev *dev)
4701 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4702 if (cmd & PCI_COMMAND_PARITY) {
4703 cmd &= ~PCI_COMMAND_PARITY;
4704 pci_write_config_word(dev, PCI_COMMAND, cmd);
4709 * pci_intx - enables/disables PCI INTx for device dev
4710 * @pdev: the PCI device to operate on
4711 * @enable: boolean: whether to enable or disable PCI INTx
4713 * Enables/disables PCI INTx for device @pdev
4715 void pci_intx(struct pci_dev *pdev, int enable)
4717 u16 pci_command, new;
4719 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4722 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4724 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4726 if (new != pci_command) {
4727 struct pci_devres *dr;
4729 pci_write_config_word(pdev, PCI_COMMAND, new);
4731 dr = find_pci_dr(pdev);
4732 if (dr && !dr->restore_intx) {
4733 dr->restore_intx = 1;
4734 dr->orig_intx = !enable;
4738 EXPORT_SYMBOL_GPL(pci_intx);
4740 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4742 struct pci_bus *bus = dev->bus;
4743 bool mask_updated = true;
4744 u32 cmd_status_dword;
4745 u16 origcmd, newcmd;
4746 unsigned long flags;
4750 * We do a single dword read to retrieve both command and status.
4751 * Document assumptions that make this possible.
4753 BUILD_BUG_ON(PCI_COMMAND % 4);
4754 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4756 raw_spin_lock_irqsave(&pci_lock, flags);
4758 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4760 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4763 * Check interrupt status register to see whether our device
4764 * triggered the interrupt (when masking) or the next IRQ is
4765 * already pending (when unmasking).
4767 if (mask != irq_pending) {
4768 mask_updated = false;
4772 origcmd = cmd_status_dword;
4773 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4775 newcmd |= PCI_COMMAND_INTX_DISABLE;
4776 if (newcmd != origcmd)
4777 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4780 raw_spin_unlock_irqrestore(&pci_lock, flags);
4782 return mask_updated;
4786 * pci_check_and_mask_intx - mask INTx on pending interrupt
4787 * @dev: the PCI device to operate on
4789 * Check if the device dev has its INTx line asserted, mask it and return
4790 * true in that case. False is returned if no interrupt was pending.
4792 bool pci_check_and_mask_intx(struct pci_dev *dev)
4794 return pci_check_and_set_intx_mask(dev, true);
4796 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4799 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4800 * @dev: the PCI device to operate on
4802 * Check if the device dev has its INTx line asserted, unmask it if not and
4803 * return true. False is returned and the mask remains active if there was
4804 * still an interrupt pending.
4806 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4808 return pci_check_and_set_intx_mask(dev, false);
4810 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4813 * pci_wait_for_pending_transaction - wait for pending transaction
4814 * @dev: the PCI device to operate on
4816 * Return 0 if transaction is pending 1 otherwise.
4818 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4820 if (!pci_is_pcie(dev))
4823 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4824 PCI_EXP_DEVSTA_TRPND);
4826 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4829 * pcie_flr - initiate a PCIe function level reset
4830 * @dev: device to reset
4832 * Initiate a function level reset unconditionally on @dev without
4833 * checking any flags and DEVCAP
4835 int pcie_flr(struct pci_dev *dev)
4837 if (!pci_wait_for_pending_transaction(dev))
4838 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4840 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4846 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4847 * 100ms, but may silently discard requests while the FLR is in
4848 * progress. Wait 100ms before trying to access the device.
4852 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4854 EXPORT_SYMBOL_GPL(pcie_flr);
4857 * pcie_reset_flr - initiate a PCIe function level reset
4858 * @dev: device to reset
4859 * @probe: if true, return 0 if device can be reset this way
4861 * Initiate a function level reset on @dev.
4863 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4865 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4868 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4874 return pcie_flr(dev);
4876 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4878 static int pci_af_flr(struct pci_dev *dev, bool probe)
4883 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4887 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4890 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4891 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4898 * Wait for Transaction Pending bit to clear. A word-aligned test
4899 * is used, so we use the control offset rather than status and shift
4900 * the test bit to match.
4902 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4903 PCI_AF_STATUS_TP << 8))
4904 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4906 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4912 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4913 * updated 27 July 2006; a device must complete an FLR within
4914 * 100ms, but may silently discard requests while the FLR is in
4915 * progress. Wait 100ms before trying to access the device.
4919 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4923 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4924 * @dev: Device to reset.
4925 * @probe: if true, return 0 if the device can be reset this way.
4927 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4928 * unset, it will be reinitialized internally when going from PCI_D3hot to
4929 * PCI_D0. If that's the case and the device is not in a low-power state
4930 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4932 * NOTE: This causes the caller to sleep for twice the device power transition
4933 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4934 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4935 * Moreover, only devices in D0 can be reset by this function.
4937 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4941 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4944 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4945 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4951 if (dev->current_state != PCI_D0)
4954 csr &= ~PCI_PM_CTRL_STATE_MASK;
4956 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4957 pci_dev_d3_sleep(dev);
4959 csr &= ~PCI_PM_CTRL_STATE_MASK;
4961 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4962 pci_dev_d3_sleep(dev);
4964 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4968 * pcie_wait_for_link_status - Wait for link status change
4969 * @pdev: Device whose link to wait for.
4970 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE.
4971 * @active: Waiting for active or inactive?
4973 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4974 * PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
4976 static int pcie_wait_for_link_status(struct pci_dev *pdev,
4977 bool use_lt, bool active)
4979 u16 lnksta_mask, lnksta_match;
4980 unsigned long end_jiffies;
4983 lnksta_mask = use_lt ? PCI_EXP_LNKSTA_LT : PCI_EXP_LNKSTA_DLLLA;
4984 lnksta_match = active ? lnksta_mask : 0;
4986 end_jiffies = jiffies + msecs_to_jiffies(PCIE_LINK_RETRAIN_TIMEOUT_MS);
4988 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
4989 if ((lnksta & lnksta_mask) == lnksta_match)
4992 } while (time_before(jiffies, end_jiffies));
4998 * pcie_retrain_link - Request a link retrain and wait for it to complete
4999 * @pdev: Device whose link to retrain.
5000 * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE, for status.
5002 * Retrain completion status is retrieved from the Link Status Register
5003 * according to @use_lt. It is not verified whether the use of the DLLLA
5006 * Return 0 if successful, or -ETIMEDOUT if training has not completed
5007 * within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
5009 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt)
5014 * Ensure the updated LNKCTL parameters are used during link
5015 * training by checking that there is no ongoing link training to
5016 * avoid LTSSM race as recommended in Implementation Note at the
5017 * end of PCIe r6.0.1 sec 7.5.3.7.
5019 rc = pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5023 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5024 if (pdev->clear_retrain_link) {
5026 * Due to an erratum in some devices the Retrain Link bit
5027 * needs to be cleared again manually to allow the link
5028 * training to succeed.
5030 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RL);
5033 return pcie_wait_for_link_status(pdev, use_lt, !use_lt);
5037 * pcie_wait_for_link_delay - Wait until link is active or inactive
5038 * @pdev: Bridge device
5039 * @active: waiting for active or inactive?
5040 * @delay: Delay to wait after link has become active (in ms)
5042 * Use this to wait till link becomes active or inactive.
5044 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
5050 * Some controllers might not implement link active reporting. In this
5051 * case, we wait for 1000 ms + any delay requested by the caller.
5053 if (!pdev->link_active_reporting) {
5054 msleep(PCIE_LINK_RETRAIN_TIMEOUT_MS + delay);
5059 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
5060 * after which we should expect an link active if the reset was
5061 * successful. If so, software must wait a minimum 100ms before sending
5062 * configuration requests to devices downstream this port.
5064 * If the link fails to activate, either the device was physically
5065 * removed or the link is permanently failed.
5069 rc = pcie_wait_for_link_status(pdev, false, active);
5072 rc = pcie_failed_link_retrain(pdev);
5087 * pcie_wait_for_link - Wait until link is active or inactive
5088 * @pdev: Bridge device
5089 * @active: waiting for active or inactive?
5091 * Use this to wait till link becomes active or inactive.
5093 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
5095 return pcie_wait_for_link_delay(pdev, active, 100);
5099 * Find maximum D3cold delay required by all the devices on the bus. The
5100 * spec says 100 ms, but firmware can lower it and we allow drivers to
5101 * increase it as well.
5103 * Called with @pci_bus_sem locked for reading.
5105 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
5107 const struct pci_dev *pdev;
5108 int min_delay = 100;
5111 list_for_each_entry(pdev, &bus->devices, bus_list) {
5112 if (pdev->d3cold_delay < min_delay)
5113 min_delay = pdev->d3cold_delay;
5114 if (pdev->d3cold_delay > max_delay)
5115 max_delay = pdev->d3cold_delay;
5118 return max(min_delay, max_delay);
5122 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5124 * @reset_type: reset type in human-readable form
5126 * Handle necessary delays before access to the devices on the secondary
5127 * side of the bridge are permitted after D3cold to D0 transition
5128 * or Conventional Reset.
5130 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
5131 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
5134 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5135 * failed to become accessible.
5137 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
5139 struct pci_dev *child;
5142 if (pci_dev_is_disconnected(dev))
5145 if (!pci_is_bridge(dev))
5148 down_read(&pci_bus_sem);
5151 * We only deal with devices that are present currently on the bus.
5152 * For any hot-added devices the access delay is handled in pciehp
5153 * board_added(). In case of ACPI hotplug the firmware is expected
5154 * to configure the devices before OS is notified.
5156 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
5157 up_read(&pci_bus_sem);
5161 /* Take d3cold_delay requirements into account */
5162 delay = pci_bus_max_d3cold_delay(dev->subordinate);
5164 up_read(&pci_bus_sem);
5168 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
5170 up_read(&pci_bus_sem);
5173 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
5174 * accessing the device after reset (that is 1000 ms + 100 ms).
5176 if (!pci_is_pcie(dev)) {
5177 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5178 msleep(1000 + delay);
5183 * For PCIe downstream and root ports that do not support speeds
5184 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5185 * speeds (gen3) we need to wait first for the data link layer to
5188 * However, 100 ms is the minimum and the PCIe spec says the
5189 * software must allow at least 1s before it can determine that the
5190 * device that did not respond is a broken device. Also device can
5191 * take longer than that to respond if it indicates so through Request
5192 * Retry Status completions.
5194 * Therefore we wait for 100 ms and check for the device presence
5195 * until the timeout expires.
5197 if (!pcie_downstream_port(dev))
5200 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5203 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5206 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay))
5210 * If the port supports active link reporting we now check
5211 * whether the link is active and if not bail out early with
5212 * the assumption that the device is not present anymore.
5214 if (!dev->link_active_reporting)
5217 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
5218 if (!(status & PCI_EXP_LNKSTA_DLLLA))
5221 return pci_dev_wait(child, reset_type,
5222 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT);
5225 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5227 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5228 /* Did not train, no need to wait any further */
5229 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5233 return pci_dev_wait(child, reset_type,
5234 PCIE_RESET_READY_POLL_MS - delay);
5237 void pci_reset_secondary_bus(struct pci_dev *dev)
5241 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5242 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5243 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5246 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5247 * this to 2ms to ensure that we meet the minimum requirement.
5251 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5252 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5255 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5257 pci_reset_secondary_bus(dev);
5261 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5262 * @dev: Bridge device
5264 * Use the bridge control register to assert reset on the secondary bus.
5265 * Devices on the secondary bus are left in power-on state.
5267 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5269 pcibios_reset_secondary_bus(dev);
5271 return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5273 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5275 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5277 struct pci_dev *pdev;
5279 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5280 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5283 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5290 return pci_bridge_secondary_bus_reset(dev->bus->self);
5293 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5297 if (!hotplug || !try_module_get(hotplug->owner))
5300 if (hotplug->ops->reset_slot)
5301 rc = hotplug->ops->reset_slot(hotplug, probe);
5303 module_put(hotplug->owner);
5308 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5310 if (dev->multifunction || dev->subordinate || !dev->slot ||
5311 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5314 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5317 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5321 rc = pci_dev_reset_slot_function(dev, probe);
5324 return pci_parent_bus_reset(dev, probe);
5327 void pci_dev_lock(struct pci_dev *dev)
5329 /* block PM suspend, driver probe, etc. */
5330 device_lock(&dev->dev);
5331 pci_cfg_access_lock(dev);
5333 EXPORT_SYMBOL_GPL(pci_dev_lock);
5335 /* Return 1 on successful lock, 0 on contention */
5336 int pci_dev_trylock(struct pci_dev *dev)
5338 if (device_trylock(&dev->dev)) {
5339 if (pci_cfg_access_trylock(dev))
5341 device_unlock(&dev->dev);
5346 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5348 void pci_dev_unlock(struct pci_dev *dev)
5350 pci_cfg_access_unlock(dev);
5351 device_unlock(&dev->dev);
5353 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5355 static void pci_dev_save_and_disable(struct pci_dev *dev)
5357 const struct pci_error_handlers *err_handler =
5358 dev->driver ? dev->driver->err_handler : NULL;
5361 * dev->driver->err_handler->reset_prepare() is protected against
5362 * races with ->remove() by the device lock, which must be held by
5365 if (err_handler && err_handler->reset_prepare)
5366 err_handler->reset_prepare(dev);
5369 * Wake-up device prior to save. PM registers default to D0 after
5370 * reset and a simple register restore doesn't reliably return
5371 * to a non-D0 state anyway.
5373 pci_set_power_state(dev, PCI_D0);
5375 pci_save_state(dev);
5377 * Disable the device by clearing the Command register, except for
5378 * INTx-disable which is set. This not only disables MMIO and I/O port
5379 * BARs, but also prevents the device from being Bus Master, preventing
5380 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5381 * compliant devices, INTx-disable prevents legacy interrupts.
5383 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5386 static void pci_dev_restore(struct pci_dev *dev)
5388 const struct pci_error_handlers *err_handler =
5389 dev->driver ? dev->driver->err_handler : NULL;
5391 pci_restore_state(dev);
5394 * dev->driver->err_handler->reset_done() is protected against
5395 * races with ->remove() by the device lock, which must be held by
5398 if (err_handler && err_handler->reset_done)
5399 err_handler->reset_done(dev);
5402 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5403 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5405 { pci_dev_specific_reset, .name = "device_specific" },
5406 { pci_dev_acpi_reset, .name = "acpi" },
5407 { pcie_reset_flr, .name = "flr" },
5408 { pci_af_flr, .name = "af_flr" },
5409 { pci_pm_reset, .name = "pm" },
5410 { pci_reset_bus_function, .name = "bus" },
5413 static ssize_t reset_method_show(struct device *dev,
5414 struct device_attribute *attr, char *buf)
5416 struct pci_dev *pdev = to_pci_dev(dev);
5420 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5421 m = pdev->reset_methods[i];
5425 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5426 pci_reset_fn_methods[m].name);
5430 len += sysfs_emit_at(buf, len, "\n");
5435 static int reset_method_lookup(const char *name)
5439 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5440 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5444 return 0; /* not found */
5447 static ssize_t reset_method_store(struct device *dev,
5448 struct device_attribute *attr,
5449 const char *buf, size_t count)
5451 struct pci_dev *pdev = to_pci_dev(dev);
5452 char *options, *name;
5454 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5456 if (sysfs_streq(buf, "")) {
5457 pdev->reset_methods[0] = 0;
5458 pci_warn(pdev, "All device reset methods disabled by user");
5462 if (sysfs_streq(buf, "default")) {
5463 pci_init_reset_methods(pdev);
5467 options = kstrndup(buf, count, GFP_KERNEL);
5472 while ((name = strsep(&options, " ")) != NULL) {
5473 if (sysfs_streq(name, ""))
5478 m = reset_method_lookup(name);
5480 pci_err(pdev, "Invalid reset method '%s'", name);
5484 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5485 pci_err(pdev, "Unsupported reset method '%s'", name);
5489 if (n == PCI_NUM_RESET_METHODS - 1) {
5490 pci_err(pdev, "Too many reset methods\n");
5494 reset_methods[n++] = m;
5497 reset_methods[n] = 0;
5499 /* Warn if dev-specific supported but not highest priority */
5500 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5501 reset_methods[0] != 1)
5502 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5503 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5508 /* Leave previous methods unchanged */
5512 static DEVICE_ATTR_RW(reset_method);
5514 static struct attribute *pci_dev_reset_method_attrs[] = {
5515 &dev_attr_reset_method.attr,
5519 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5520 struct attribute *a, int n)
5522 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5524 if (!pci_reset_supported(pdev))
5530 const struct attribute_group pci_dev_reset_method_attr_group = {
5531 .attrs = pci_dev_reset_method_attrs,
5532 .is_visible = pci_dev_reset_method_attr_is_visible,
5536 * __pci_reset_function_locked - reset a PCI device function while holding
5537 * the @dev mutex lock.
5538 * @dev: PCI device to reset
5540 * Some devices allow an individual function to be reset without affecting
5541 * other functions in the same device. The PCI device must be responsive
5542 * to PCI config space in order to use this function.
5544 * The device function is presumed to be unused and the caller is holding
5545 * the device mutex lock when this function is called.
5547 * Resetting the device will make the contents of PCI configuration space
5548 * random, so any caller of this must be prepared to reinitialise the
5549 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5552 * Returns 0 if the device function was successfully reset or negative if the
5553 * device doesn't support resetting a single function.
5555 int __pci_reset_function_locked(struct pci_dev *dev)
5562 * A reset method returns -ENOTTY if it doesn't support this device and
5563 * we should try the next method.
5565 * If it returns 0 (success), we're finished. If it returns any other
5566 * error, we're also finished: this indicates that further reset
5567 * mechanisms might be broken on the device.
5569 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5570 m = dev->reset_methods[i];
5574 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5583 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5586 * pci_init_reset_methods - check whether device can be safely reset
5587 * and store supported reset mechanisms.
5588 * @dev: PCI device to check for reset mechanisms
5590 * Some devices allow an individual function to be reset without affecting
5591 * other functions in the same device. The PCI device must be in D0-D3hot
5594 * Stores reset mechanisms supported by device in reset_methods byte array
5595 * which is a member of struct pci_dev.
5597 void pci_init_reset_methods(struct pci_dev *dev)
5601 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5606 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5607 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5609 dev->reset_methods[i++] = m;
5610 else if (rc != -ENOTTY)
5614 dev->reset_methods[i] = 0;
5618 * pci_reset_function - quiesce and reset a PCI device function
5619 * @dev: PCI device to reset
5621 * Some devices allow an individual function to be reset without affecting
5622 * other functions in the same device. The PCI device must be responsive
5623 * to PCI config space in order to use this function.
5625 * This function does not just reset the PCI portion of a device, but
5626 * clears all the state associated with the device. This function differs
5627 * from __pci_reset_function_locked() in that it saves and restores device state
5628 * over the reset and takes the PCI device lock.
5630 * Returns 0 if the device function was successfully reset or negative if the
5631 * device doesn't support resetting a single function.
5633 int pci_reset_function(struct pci_dev *dev)
5637 if (!pci_reset_supported(dev))
5641 pci_dev_save_and_disable(dev);
5643 rc = __pci_reset_function_locked(dev);
5645 pci_dev_restore(dev);
5646 pci_dev_unlock(dev);
5650 EXPORT_SYMBOL_GPL(pci_reset_function);
5653 * pci_reset_function_locked - quiesce and reset a PCI device function
5654 * @dev: PCI device to reset
5656 * Some devices allow an individual function to be reset without affecting
5657 * other functions in the same device. The PCI device must be responsive
5658 * to PCI config space in order to use this function.
5660 * This function does not just reset the PCI portion of a device, but
5661 * clears all the state associated with the device. This function differs
5662 * from __pci_reset_function_locked() in that it saves and restores device state
5663 * over the reset. It also differs from pci_reset_function() in that it
5664 * requires the PCI device lock to be held.
5666 * Returns 0 if the device function was successfully reset or negative if the
5667 * device doesn't support resetting a single function.
5669 int pci_reset_function_locked(struct pci_dev *dev)
5673 if (!pci_reset_supported(dev))
5676 pci_dev_save_and_disable(dev);
5678 rc = __pci_reset_function_locked(dev);
5680 pci_dev_restore(dev);
5684 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5687 * pci_try_reset_function - quiesce and reset a PCI device function
5688 * @dev: PCI device to reset
5690 * Same as above, except return -EAGAIN if unable to lock device.
5692 int pci_try_reset_function(struct pci_dev *dev)
5696 if (!pci_reset_supported(dev))
5699 if (!pci_dev_trylock(dev))
5702 pci_dev_save_and_disable(dev);
5703 rc = __pci_reset_function_locked(dev);
5704 pci_dev_restore(dev);
5705 pci_dev_unlock(dev);
5709 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5711 /* Do any devices on or below this bus prevent a bus reset? */
5712 static bool pci_bus_resettable(struct pci_bus *bus)
5714 struct pci_dev *dev;
5717 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5720 list_for_each_entry(dev, &bus->devices, bus_list) {
5721 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5722 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5729 /* Lock devices from the top of the tree down */
5730 static void pci_bus_lock(struct pci_bus *bus)
5732 struct pci_dev *dev;
5734 list_for_each_entry(dev, &bus->devices, bus_list) {
5736 if (dev->subordinate)
5737 pci_bus_lock(dev->subordinate);
5741 /* Unlock devices from the bottom of the tree up */
5742 static void pci_bus_unlock(struct pci_bus *bus)
5744 struct pci_dev *dev;
5746 list_for_each_entry(dev, &bus->devices, bus_list) {
5747 if (dev->subordinate)
5748 pci_bus_unlock(dev->subordinate);
5749 pci_dev_unlock(dev);
5753 /* Return 1 on successful lock, 0 on contention */
5754 static int pci_bus_trylock(struct pci_bus *bus)
5756 struct pci_dev *dev;
5758 list_for_each_entry(dev, &bus->devices, bus_list) {
5759 if (!pci_dev_trylock(dev))
5761 if (dev->subordinate) {
5762 if (!pci_bus_trylock(dev->subordinate)) {
5763 pci_dev_unlock(dev);
5771 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5772 if (dev->subordinate)
5773 pci_bus_unlock(dev->subordinate);
5774 pci_dev_unlock(dev);
5779 /* Do any devices on or below this slot prevent a bus reset? */
5780 static bool pci_slot_resettable(struct pci_slot *slot)
5782 struct pci_dev *dev;
5784 if (slot->bus->self &&
5785 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5788 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5789 if (!dev->slot || dev->slot != slot)
5791 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5792 (dev->subordinate && !pci_bus_resettable(dev->subordinate)))
5799 /* Lock devices from the top of the tree down */
5800 static void pci_slot_lock(struct pci_slot *slot)
5802 struct pci_dev *dev;
5804 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5805 if (!dev->slot || dev->slot != slot)
5808 if (dev->subordinate)
5809 pci_bus_lock(dev->subordinate);
5813 /* Unlock devices from the bottom of the tree up */
5814 static void pci_slot_unlock(struct pci_slot *slot)
5816 struct pci_dev *dev;
5818 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5819 if (!dev->slot || dev->slot != slot)
5821 if (dev->subordinate)
5822 pci_bus_unlock(dev->subordinate);
5823 pci_dev_unlock(dev);
5827 /* Return 1 on successful lock, 0 on contention */
5828 static int pci_slot_trylock(struct pci_slot *slot)
5830 struct pci_dev *dev;
5832 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5833 if (!dev->slot || dev->slot != slot)
5835 if (!pci_dev_trylock(dev))
5837 if (dev->subordinate) {
5838 if (!pci_bus_trylock(dev->subordinate)) {
5839 pci_dev_unlock(dev);
5847 list_for_each_entry_continue_reverse(dev,
5848 &slot->bus->devices, bus_list) {
5849 if (!dev->slot || dev->slot != slot)
5851 if (dev->subordinate)
5852 pci_bus_unlock(dev->subordinate);
5853 pci_dev_unlock(dev);
5859 * Save and disable devices from the top of the tree down while holding
5860 * the @dev mutex lock for the entire tree.
5862 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5864 struct pci_dev *dev;
5866 list_for_each_entry(dev, &bus->devices, bus_list) {
5867 pci_dev_save_and_disable(dev);
5868 if (dev->subordinate)
5869 pci_bus_save_and_disable_locked(dev->subordinate);
5874 * Restore devices from top of the tree down while holding @dev mutex lock
5875 * for the entire tree. Parent bridges need to be restored before we can
5876 * get to subordinate devices.
5878 static void pci_bus_restore_locked(struct pci_bus *bus)
5880 struct pci_dev *dev;
5882 list_for_each_entry(dev, &bus->devices, bus_list) {
5883 pci_dev_restore(dev);
5884 if (dev->subordinate)
5885 pci_bus_restore_locked(dev->subordinate);
5890 * Save and disable devices from the top of the tree down while holding
5891 * the @dev mutex lock for the entire tree.
5893 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5895 struct pci_dev *dev;
5897 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5898 if (!dev->slot || dev->slot != slot)
5900 pci_dev_save_and_disable(dev);
5901 if (dev->subordinate)
5902 pci_bus_save_and_disable_locked(dev->subordinate);
5907 * Restore devices from top of the tree down while holding @dev mutex lock
5908 * for the entire tree. Parent bridges need to be restored before we can
5909 * get to subordinate devices.
5911 static void pci_slot_restore_locked(struct pci_slot *slot)
5913 struct pci_dev *dev;
5915 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5916 if (!dev->slot || dev->slot != slot)
5918 pci_dev_restore(dev);
5919 if (dev->subordinate)
5920 pci_bus_restore_locked(dev->subordinate);
5924 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5928 if (!slot || !pci_slot_resettable(slot))
5932 pci_slot_lock(slot);
5936 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5939 pci_slot_unlock(slot);
5945 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5946 * @slot: PCI slot to probe
5948 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5950 int pci_probe_reset_slot(struct pci_slot *slot)
5952 return pci_slot_reset(slot, PCI_RESET_PROBE);
5954 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5957 * __pci_reset_slot - Try to reset a PCI slot
5958 * @slot: PCI slot to reset
5960 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5961 * independent of other slots. For instance, some slots may support slot power
5962 * control. In the case of a 1:1 bus to slot architecture, this function may
5963 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5964 * Generally a slot reset should be attempted before a bus reset. All of the
5965 * function of the slot and any subordinate buses behind the slot are reset
5966 * through this function. PCI config space of all devices in the slot and
5967 * behind the slot is saved before and restored after reset.
5969 * Same as above except return -EAGAIN if the slot cannot be locked
5971 static int __pci_reset_slot(struct pci_slot *slot)
5975 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5979 if (pci_slot_trylock(slot)) {
5980 pci_slot_save_and_disable_locked(slot);
5982 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5983 pci_slot_restore_locked(slot);
5984 pci_slot_unlock(slot);
5991 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5995 if (!bus->self || !pci_bus_resettable(bus))
6005 ret = pci_bridge_secondary_bus_reset(bus->self);
6007 pci_bus_unlock(bus);
6013 * pci_bus_error_reset - reset the bridge's subordinate bus
6014 * @bridge: The parent device that connects to the bus to reset
6016 * This function will first try to reset the slots on this bus if the method is
6017 * available. If slot reset fails or is not available, this will fall back to a
6018 * secondary bus reset.
6020 int pci_bus_error_reset(struct pci_dev *bridge)
6022 struct pci_bus *bus = bridge->subordinate;
6023 struct pci_slot *slot;
6028 mutex_lock(&pci_slot_mutex);
6029 if (list_empty(&bus->slots))
6032 list_for_each_entry(slot, &bus->slots, list)
6033 if (pci_probe_reset_slot(slot))
6036 list_for_each_entry(slot, &bus->slots, list)
6037 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
6040 mutex_unlock(&pci_slot_mutex);
6043 mutex_unlock(&pci_slot_mutex);
6044 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
6048 * pci_probe_reset_bus - probe whether a PCI bus can be reset
6049 * @bus: PCI bus to probe
6051 * Return 0 if bus can be reset, negative if a bus reset is not supported.
6053 int pci_probe_reset_bus(struct pci_bus *bus)
6055 return pci_bus_reset(bus, PCI_RESET_PROBE);
6057 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
6060 * __pci_reset_bus - Try to reset a PCI bus
6061 * @bus: top level PCI bus to reset
6063 * Same as above except return -EAGAIN if the bus cannot be locked
6065 static int __pci_reset_bus(struct pci_bus *bus)
6069 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
6073 if (pci_bus_trylock(bus)) {
6074 pci_bus_save_and_disable_locked(bus);
6076 rc = pci_bridge_secondary_bus_reset(bus->self);
6077 pci_bus_restore_locked(bus);
6078 pci_bus_unlock(bus);
6086 * pci_reset_bus - Try to reset a PCI bus
6087 * @pdev: top level PCI device to reset via slot/bus
6089 * Same as above except return -EAGAIN if the bus cannot be locked
6091 int pci_reset_bus(struct pci_dev *pdev)
6093 return (!pci_probe_reset_slot(pdev->slot)) ?
6094 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
6096 EXPORT_SYMBOL_GPL(pci_reset_bus);
6099 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6100 * @dev: PCI device to query
6102 * Returns mmrbc: maximum designed memory read count in bytes or
6103 * appropriate error value.
6105 int pcix_get_max_mmrbc(struct pci_dev *dev)
6110 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6114 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6117 return 512 << FIELD_GET(PCI_X_STATUS_MAX_READ, stat);
6119 EXPORT_SYMBOL(pcix_get_max_mmrbc);
6122 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6123 * @dev: PCI device to query
6125 * Returns mmrbc: maximum memory read count in bytes or appropriate error
6128 int pcix_get_mmrbc(struct pci_dev *dev)
6133 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6137 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6140 return 512 << FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6142 EXPORT_SYMBOL(pcix_get_mmrbc);
6145 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6146 * @dev: PCI device to query
6147 * @mmrbc: maximum memory read count in bytes
6148 * valid values are 512, 1024, 2048, 4096
6150 * If possible sets maximum memory read byte count, some bridges have errata
6151 * that prevent this.
6153 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
6159 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
6162 v = ffs(mmrbc) - 10;
6164 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
6168 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
6171 if (v > FIELD_GET(PCI_X_STATUS_MAX_READ, stat))
6174 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
6177 o = FIELD_GET(PCI_X_CMD_MAX_READ, cmd);
6179 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
6182 cmd &= ~PCI_X_CMD_MAX_READ;
6183 cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v);
6184 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
6189 EXPORT_SYMBOL(pcix_set_mmrbc);
6192 * pcie_get_readrq - get PCI Express read request size
6193 * @dev: PCI device to query
6195 * Returns maximum memory read request in bytes or appropriate error value.
6197 int pcie_get_readrq(struct pci_dev *dev)
6201 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6203 return 128 << FIELD_GET(PCI_EXP_DEVCTL_READRQ, ctl);
6205 EXPORT_SYMBOL(pcie_get_readrq);
6208 * pcie_set_readrq - set PCI Express maximum memory read request
6209 * @dev: PCI device to query
6210 * @rq: maximum memory read count in bytes
6211 * valid values are 128, 256, 512, 1024, 2048, 4096
6213 * If possible sets maximum memory read request in bytes
6215 int pcie_set_readrq(struct pci_dev *dev, int rq)
6219 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6221 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6225 * If using the "performance" PCIe config, we clamp the read rq
6226 * size to the max packet size to keep the host bridge from
6227 * generating requests larger than we can cope with.
6229 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6230 int mps = pcie_get_mps(dev);
6236 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8);
6238 if (bridge->no_inc_mrrs) {
6239 int max_mrrs = pcie_get_readrq(dev);
6241 if (rq > max_mrrs) {
6242 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6247 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6248 PCI_EXP_DEVCTL_READRQ, v);
6250 return pcibios_err_to_errno(ret);
6252 EXPORT_SYMBOL(pcie_set_readrq);
6255 * pcie_get_mps - get PCI Express maximum payload size
6256 * @dev: PCI device to query
6258 * Returns maximum payload size in bytes
6260 int pcie_get_mps(struct pci_dev *dev)
6264 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6266 return 128 << FIELD_GET(PCI_EXP_DEVCTL_PAYLOAD, ctl);
6268 EXPORT_SYMBOL(pcie_get_mps);
6271 * pcie_set_mps - set PCI Express maximum payload size
6272 * @dev: PCI device to query
6273 * @mps: maximum payload size in bytes
6274 * valid values are 128, 256, 512, 1024, 2048, 4096
6276 * If possible sets maximum payload size
6278 int pcie_set_mps(struct pci_dev *dev, int mps)
6283 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6287 if (v > dev->pcie_mpss)
6289 v = FIELD_PREP(PCI_EXP_DEVCTL_PAYLOAD, v);
6291 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6292 PCI_EXP_DEVCTL_PAYLOAD, v);
6294 return pcibios_err_to_errno(ret);
6296 EXPORT_SYMBOL(pcie_set_mps);
6298 static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
6300 return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
6303 int pcie_link_speed_mbps(struct pci_dev *pdev)
6308 err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
6312 switch (to_pcie_link_speed(lnksta)) {
6313 case PCIE_SPEED_2_5GT:
6315 case PCIE_SPEED_5_0GT:
6317 case PCIE_SPEED_8_0GT:
6319 case PCIE_SPEED_16_0GT:
6321 case PCIE_SPEED_32_0GT:
6323 case PCIE_SPEED_64_0GT:
6331 EXPORT_SYMBOL(pcie_link_speed_mbps);
6334 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6335 * device and its bandwidth limitation
6336 * @dev: PCI device to query
6337 * @limiting_dev: storage for device causing the bandwidth limitation
6338 * @speed: storage for speed of limiting device
6339 * @width: storage for width of limiting device
6341 * Walk up the PCI device chain and find the point where the minimum
6342 * bandwidth is available. Return the bandwidth available there and (if
6343 * limiting_dev, speed, and width pointers are supplied) information about
6344 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6347 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6348 enum pci_bus_speed *speed,
6349 enum pcie_link_width *width)
6352 enum pci_bus_speed next_speed;
6353 enum pcie_link_width next_width;
6357 *speed = PCI_SPEED_UNKNOWN;
6359 *width = PCIE_LNK_WIDTH_UNKNOWN;
6364 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6366 next_speed = to_pcie_link_speed(lnksta);
6367 next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
6369 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6371 /* Check if current device limits the total bandwidth */
6372 if (!bw || next_bw <= bw) {
6376 *limiting_dev = dev;
6378 *speed = next_speed;
6380 *width = next_width;
6383 dev = pci_upstream_bridge(dev);
6388 EXPORT_SYMBOL(pcie_bandwidth_available);
6391 * pcie_get_speed_cap - query for the PCI device's link speed capability
6392 * @dev: PCI device to query
6394 * Query the PCI device speed capability. Return the maximum link speed
6395 * supported by the device.
6397 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6399 u32 lnkcap2, lnkcap;
6402 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6403 * implementation note there recommends using the Supported Link
6404 * Speeds Vector in Link Capabilities 2 when supported.
6406 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6407 * should use the Supported Link Speeds field in Link Capabilities,
6408 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6410 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6412 /* PCIe r3.0-compliant */
6414 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6416 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6417 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6418 return PCIE_SPEED_5_0GT;
6419 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6420 return PCIE_SPEED_2_5GT;
6422 return PCI_SPEED_UNKNOWN;
6424 EXPORT_SYMBOL(pcie_get_speed_cap);
6427 * pcie_get_width_cap - query for the PCI device's link width capability
6428 * @dev: PCI device to query
6430 * Query the PCI device width capability. Return the maximum link width
6431 * supported by the device.
6433 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6437 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6439 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
6441 return PCIE_LNK_WIDTH_UNKNOWN;
6443 EXPORT_SYMBOL(pcie_get_width_cap);
6446 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6448 * @speed: storage for link speed
6449 * @width: storage for link width
6451 * Calculate a PCI device's link bandwidth by querying for its link speed
6452 * and width, multiplying them, and applying encoding overhead. The result
6453 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6455 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6456 enum pcie_link_width *width)
6458 *speed = pcie_get_speed_cap(dev);
6459 *width = pcie_get_width_cap(dev);
6461 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6464 return *width * PCIE_SPEED2MBS_ENC(*speed);
6468 * __pcie_print_link_status - Report the PCI device's link speed and width
6469 * @dev: PCI device to query
6470 * @verbose: Print info even when enough bandwidth is available
6472 * If the available bandwidth at the device is less than the device is
6473 * capable of, report the device's maximum possible bandwidth and the
6474 * upstream link that limits its performance. If @verbose, always print
6475 * the available bandwidth, even if the device isn't constrained.
6477 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6479 enum pcie_link_width width, width_cap;
6480 enum pci_bus_speed speed, speed_cap;
6481 struct pci_dev *limiting_dev = NULL;
6482 u32 bw_avail, bw_cap;
6484 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6485 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6487 if (bw_avail >= bw_cap && verbose)
6488 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6489 bw_cap / 1000, bw_cap % 1000,
6490 pci_speed_string(speed_cap), width_cap);
6491 else if (bw_avail < bw_cap)
6492 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6493 bw_avail / 1000, bw_avail % 1000,
6494 pci_speed_string(speed), width,
6495 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6496 bw_cap / 1000, bw_cap % 1000,
6497 pci_speed_string(speed_cap), width_cap);
6501 * pcie_print_link_status - Report the PCI device's link speed and width
6502 * @dev: PCI device to query
6504 * Report the available bandwidth at the device.
6506 void pcie_print_link_status(struct pci_dev *dev)
6508 __pcie_print_link_status(dev, true);
6510 EXPORT_SYMBOL(pcie_print_link_status);
6513 * pci_select_bars - Make BAR mask from the type of resource
6514 * @dev: the PCI device for which BAR mask is made
6515 * @flags: resource type mask to be selected
6517 * This helper routine makes bar mask from the type of resource.
6519 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6522 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6523 if (pci_resource_flags(dev, i) & flags)
6527 EXPORT_SYMBOL(pci_select_bars);
6529 /* Some architectures require additional programming to enable VGA */
6530 static arch_set_vga_state_t arch_set_vga_state;
6532 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6534 arch_set_vga_state = func; /* NULL disables */
6537 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6538 unsigned int command_bits, u32 flags)
6540 if (arch_set_vga_state)
6541 return arch_set_vga_state(dev, decode, command_bits,
6547 * pci_set_vga_state - set VGA decode state on device and parents if requested
6548 * @dev: the PCI device
6549 * @decode: true = enable decoding, false = disable decoding
6550 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6551 * @flags: traverse ancestors and change bridges
6552 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6554 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6555 unsigned int command_bits, u32 flags)
6557 struct pci_bus *bus;
6558 struct pci_dev *bridge;
6562 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6564 /* ARCH specific VGA enables */
6565 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6569 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6570 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6572 cmd |= command_bits;
6574 cmd &= ~command_bits;
6575 pci_write_config_word(dev, PCI_COMMAND, cmd);
6578 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6585 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6588 cmd |= PCI_BRIDGE_CTL_VGA;
6590 cmd &= ~PCI_BRIDGE_CTL_VGA;
6591 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6600 bool pci_pr3_present(struct pci_dev *pdev)
6602 struct acpi_device *adev;
6607 adev = ACPI_COMPANION(&pdev->dev);
6611 return adev->power.flags.power_resources &&
6612 acpi_has_method(adev->handle, "_PR3");
6614 EXPORT_SYMBOL_GPL(pci_pr3_present);
6618 * pci_add_dma_alias - Add a DMA devfn alias for a device
6619 * @dev: the PCI device for which alias is added
6620 * @devfn_from: alias slot and function
6621 * @nr_devfns: number of subsequent devfns to alias
6623 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6624 * which is used to program permissible bus-devfn source addresses for DMA
6625 * requests in an IOMMU. These aliases factor into IOMMU group creation
6626 * and are useful for devices generating DMA requests beyond or different
6627 * from their logical bus-devfn. Examples include device quirks where the
6628 * device simply uses the wrong devfn, as well as non-transparent bridges
6629 * where the alias may be a proxy for devices in another domain.
6631 * IOMMU group creation is performed during device discovery or addition,
6632 * prior to any potential DMA mapping and therefore prior to driver probing
6633 * (especially for userspace assigned devices where IOMMU group definition
6634 * cannot be left as a userspace activity). DMA aliases should therefore
6635 * be configured via quirks, such as the PCI fixup header quirk.
6637 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6638 unsigned int nr_devfns)
6642 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6643 devfn_to = devfn_from + nr_devfns - 1;
6645 if (!dev->dma_alias_mask)
6646 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6647 if (!dev->dma_alias_mask) {
6648 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6652 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6655 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6656 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6657 else if (nr_devfns > 1)
6658 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6659 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6660 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6663 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6665 return (dev1->dma_alias_mask &&
6666 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6667 (dev2->dma_alias_mask &&
6668 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6669 pci_real_dma_dev(dev1) == dev2 ||
6670 pci_real_dma_dev(dev2) == dev1;
6673 bool pci_device_is_present(struct pci_dev *pdev)
6677 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6678 pdev = pci_physfn(pdev);
6679 if (pci_dev_is_disconnected(pdev))
6681 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6683 EXPORT_SYMBOL_GPL(pci_device_is_present);
6685 void pci_ignore_hotplug(struct pci_dev *dev)
6687 struct pci_dev *bridge = dev->bus->self;
6689 dev->ignore_hotplug = 1;
6690 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6692 bridge->ignore_hotplug = 1;
6694 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6697 * pci_real_dma_dev - Get PCI DMA device for PCI device
6698 * @dev: the PCI device that may have a PCI DMA alias
6700 * Permits the platform to provide architecture-specific functionality to
6701 * devices needing to alias DMA to another PCI device on another PCI bus. If
6702 * the PCI device is on the same bus, it is recommended to use
6703 * pci_add_dma_alias(). This is the default implementation. Architecture
6704 * implementations can override this.
6706 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6711 resource_size_t __weak pcibios_default_alignment(void)
6717 * Arches that don't want to expose struct resource to userland as-is in
6718 * sysfs and /proc can implement their own pci_resource_to_user().
6720 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6721 const struct resource *rsrc,
6722 resource_size_t *start, resource_size_t *end)
6724 *start = rsrc->start;
6728 static char *resource_alignment_param;
6729 static DEFINE_SPINLOCK(resource_alignment_lock);
6732 * pci_specified_resource_alignment - get resource alignment specified by user.
6733 * @dev: the PCI device to get
6734 * @resize: whether or not to change resources' size when reassigning alignment
6736 * RETURNS: Resource alignment if it is specified.
6737 * Zero if it is not specified.
6739 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6742 int align_order, count;
6743 resource_size_t align = pcibios_default_alignment();
6747 spin_lock(&resource_alignment_lock);
6748 p = resource_alignment_param;
6751 if (pci_has_flag(PCI_PROBE_ONLY)) {
6753 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6759 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6762 if (align_order > 63) {
6763 pr_err("PCI: Invalid requested alignment (order %d)\n",
6765 align_order = PAGE_SHIFT;
6768 align_order = PAGE_SHIFT;
6771 ret = pci_dev_str_match(dev, p, &p);
6774 align = 1ULL << align_order;
6776 } else if (ret < 0) {
6777 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6782 if (*p != ';' && *p != ',') {
6783 /* End of param or invalid format */
6789 spin_unlock(&resource_alignment_lock);
6793 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6794 resource_size_t align, bool resize)
6796 struct resource *r = &dev->resource[bar];
6797 const char *r_name = pci_resource_name(dev, bar);
6798 resource_size_t size;
6800 if (!(r->flags & IORESOURCE_MEM))
6803 if (r->flags & IORESOURCE_PCI_FIXED) {
6804 pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n",
6805 r_name, r, (unsigned long long)align);
6809 size = resource_size(r);
6814 * Increase the alignment of the resource. There are two ways we
6817 * 1) Increase the size of the resource. BARs are aligned on their
6818 * size, so when we reallocate space for this resource, we'll
6819 * allocate it with the larger alignment. This also prevents
6820 * assignment of any other BARs inside the alignment region, so
6821 * if we're requesting page alignment, this means no other BARs
6822 * will share the page.
6824 * The disadvantage is that this makes the resource larger than
6825 * the hardware BAR, which may break drivers that compute things
6826 * based on the resource size, e.g., to find registers at a
6827 * fixed offset before the end of the BAR.
6829 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6830 * set r->start to the desired alignment. By itself this
6831 * doesn't prevent other BARs being put inside the alignment
6832 * region, but if we realign *every* resource of every device in
6833 * the system, none of them will share an alignment region.
6835 * When the user has requested alignment for only some devices via
6836 * the "pci=resource_alignment" argument, "resize" is true and we
6837 * use the first method. Otherwise we assume we're aligning all
6838 * devices and we use the second.
6841 pci_info(dev, "%s %pR: requesting alignment to %#llx\n",
6842 r_name, r, (unsigned long long)align);
6848 r->flags &= ~IORESOURCE_SIZEALIGN;
6849 r->flags |= IORESOURCE_STARTALIGN;
6851 r->end = r->start + size - 1;
6853 r->flags |= IORESOURCE_UNSET;
6857 * This function disables memory decoding and releases memory resources
6858 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6859 * It also rounds up size to specified alignment.
6860 * Later on, the kernel will assign page-aligned memory resource back
6863 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6867 resource_size_t align;
6869 bool resize = false;
6872 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6873 * 3.4.1.11. Their resources are allocated from the space
6874 * described by the VF BARx register in the PF's SR-IOV capability.
6875 * We can't influence their alignment here.
6880 /* check if specified PCI is target device to reassign */
6881 align = pci_specified_resource_alignment(dev, &resize);
6885 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6886 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6887 pci_warn(dev, "Can't reassign resources to host bridge\n");
6891 pci_read_config_word(dev, PCI_COMMAND, &command);
6892 command &= ~PCI_COMMAND_MEMORY;
6893 pci_write_config_word(dev, PCI_COMMAND, command);
6895 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6896 pci_request_resource_alignment(dev, i, align, resize);
6899 * Need to disable bridge's resource window,
6900 * to enable the kernel to reassign new resource
6903 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6904 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6905 r = &dev->resource[i];
6906 if (!(r->flags & IORESOURCE_MEM))
6908 r->flags |= IORESOURCE_UNSET;
6909 r->end = resource_size(r) - 1;
6912 pci_disable_bridge_window(dev);
6916 static ssize_t resource_alignment_show(const struct bus_type *bus, char *buf)
6920 spin_lock(&resource_alignment_lock);
6921 if (resource_alignment_param)
6922 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6923 spin_unlock(&resource_alignment_lock);
6928 static ssize_t resource_alignment_store(const struct bus_type *bus,
6929 const char *buf, size_t count)
6931 char *param, *old, *end;
6933 if (count >= (PAGE_SIZE - 1))
6936 param = kstrndup(buf, count, GFP_KERNEL);
6940 end = strchr(param, '\n');
6944 spin_lock(&resource_alignment_lock);
6945 old = resource_alignment_param;
6946 if (strlen(param)) {
6947 resource_alignment_param = param;
6950 resource_alignment_param = NULL;
6952 spin_unlock(&resource_alignment_lock);
6959 static BUS_ATTR_RW(resource_alignment);
6961 static int __init pci_resource_alignment_sysfs_init(void)
6963 return bus_create_file(&pci_bus_type,
6964 &bus_attr_resource_alignment);
6966 late_initcall(pci_resource_alignment_sysfs_init);
6968 static void pci_no_domains(void)
6970 #ifdef CONFIG_PCI_DOMAINS
6971 pci_domains_supported = 0;
6975 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6976 static DEFINE_IDA(pci_domain_nr_static_ida);
6977 static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6979 static void of_pci_reserve_static_domain_nr(void)
6981 struct device_node *np;
6984 for_each_node_by_type(np, "pci") {
6985 domain_nr = of_get_pci_domain_nr(np);
6989 * Permanently allocate domain_nr in dynamic_ida
6990 * to prevent it from dynamic allocation.
6992 ida_alloc_range(&pci_domain_nr_dynamic_ida,
6993 domain_nr, domain_nr, GFP_KERNEL);
6997 static int of_pci_bus_find_domain_nr(struct device *parent)
6999 static bool static_domains_reserved = false;
7002 /* On the first call scan device tree for static allocations. */
7003 if (!static_domains_reserved) {
7004 of_pci_reserve_static_domain_nr();
7005 static_domains_reserved = true;
7010 * If domain is in DT, allocate it in static IDA. This
7011 * prevents duplicate static allocations in case of errors
7014 domain_nr = of_get_pci_domain_nr(parent->of_node);
7016 return ida_alloc_range(&pci_domain_nr_static_ida,
7017 domain_nr, domain_nr,
7022 * If domain was not specified in DT, choose a free ID from dynamic
7023 * allocations. All domain numbers from DT are permanently in
7024 * dynamic allocations to prevent assigning them to other DT nodes
7025 * without static domain.
7027 return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
7030 static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7032 if (bus->domain_nr < 0)
7035 /* Release domain from IDA where it was allocated. */
7036 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
7037 ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
7039 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
7042 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
7044 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
7045 acpi_pci_bus_find_domain_nr(bus);
7048 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
7052 of_pci_bus_release_domain_nr(bus, parent);
7057 * pci_ext_cfg_avail - can we access extended PCI config space?
7059 * Returns 1 if we can access PCI extended config space (offsets
7060 * greater than 0xff). This is the default implementation. Architecture
7061 * implementations can override this.
7063 int __weak pci_ext_cfg_avail(void)
7068 void __weak pci_fixup_cardbus(struct pci_bus *bus)
7071 EXPORT_SYMBOL(pci_fixup_cardbus);
7073 static int __init pci_setup(char *str)
7076 char *k = strchr(str, ',');
7079 if (*str && (str = pcibios_setup(str)) && *str) {
7080 if (!strcmp(str, "nomsi")) {
7082 } else if (!strncmp(str, "noats", 5)) {
7083 pr_info("PCIe: ATS is disabled\n");
7084 pcie_ats_disabled = true;
7085 } else if (!strcmp(str, "noaer")) {
7087 } else if (!strcmp(str, "earlydump")) {
7088 pci_early_dump = true;
7089 } else if (!strncmp(str, "realloc=", 8)) {
7090 pci_realloc_get_opt(str + 8);
7091 } else if (!strncmp(str, "realloc", 7)) {
7092 pci_realloc_get_opt("on");
7093 } else if (!strcmp(str, "nodomains")) {
7095 } else if (!strncmp(str, "noari", 5)) {
7096 pcie_ari_disabled = true;
7097 } else if (!strncmp(str, "cbiosize=", 9)) {
7098 pci_cardbus_io_size = memparse(str + 9, &str);
7099 } else if (!strncmp(str, "cbmemsize=", 10)) {
7100 pci_cardbus_mem_size = memparse(str + 10, &str);
7101 } else if (!strncmp(str, "resource_alignment=", 19)) {
7102 resource_alignment_param = str + 19;
7103 } else if (!strncmp(str, "ecrc=", 5)) {
7104 pcie_ecrc_get_policy(str + 5);
7105 } else if (!strncmp(str, "hpiosize=", 9)) {
7106 pci_hotplug_io_size = memparse(str + 9, &str);
7107 } else if (!strncmp(str, "hpmmiosize=", 11)) {
7108 pci_hotplug_mmio_size = memparse(str + 11, &str);
7109 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
7110 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
7111 } else if (!strncmp(str, "hpmemsize=", 10)) {
7112 pci_hotplug_mmio_size = memparse(str + 10, &str);
7113 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
7114 } else if (!strncmp(str, "hpbussize=", 10)) {
7115 pci_hotplug_bus_size =
7116 simple_strtoul(str + 10, &str, 0);
7117 if (pci_hotplug_bus_size > 0xff)
7118 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
7119 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
7120 pcie_bus_config = PCIE_BUS_TUNE_OFF;
7121 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
7122 pcie_bus_config = PCIE_BUS_SAFE;
7123 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
7124 pcie_bus_config = PCIE_BUS_PERFORMANCE;
7125 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
7126 pcie_bus_config = PCIE_BUS_PEER2PEER;
7127 } else if (!strncmp(str, "pcie_scan_all", 13)) {
7128 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
7129 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
7130 disable_acs_redir_param = str + 18;
7132 pr_err("PCI: Unknown option `%s'\n", str);
7139 early_param("pci", pci_setup);
7142 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
7143 * in pci_setup(), above, to point to data in the __initdata section which
7144 * will be freed after the init sequence is complete. We can't allocate memory
7145 * in pci_setup() because some architectures do not have any memory allocation
7146 * service available during an early_param() call. So we allocate memory and
7147 * copy the variable here before the init section is freed.
7150 static int __init pci_realloc_setup_params(void)
7152 resource_alignment_param = kstrdup(resource_alignment_param,
7154 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
7158 pure_initcall(pci_realloc_setup_params);