drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/blk-integrity.h>
  14 #include <linux/dmi.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/memremap.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/once.h>
  23 #include <linux/pci.h>
  24 #include <linux/suspend.h>
  25 #include <linux/t10-pi.h>
  26 #include <linux/types.h>
  27 #include <linux/io-64-nonatomic-lo-hi.h>
  28 #include <linux/io-64-nonatomic-hi-lo.h>
  29 #include <linux/sed-opal.h>
  30 #include <linux/pci-p2pdma.h>
  31
  32 #include "trace.h"
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  36 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 /*
  41  * These can be higher, but we need to ensure that any command doesn't
  42  * require an sg allocation that needs more than a page of data.
  43  */
  44 #define NVME_MAX_KB_SZ  4096
  45 #define NVME_MAX_SEGS   127
  46
  47 static int use_threaded_interrupts;
  48 module_param(use_threaded_interrupts, int, 0444);
  49
  50 static bool use_cmb_sqes = true;
  51 module_param(use_cmb_sqes, bool, 0444);
  52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  53
  54 static unsigned int max_host_mem_size_mb = 128;
  55 module_param(max_host_mem_size_mb, uint, 0444);
  56 MODULE_PARM_DESC(max_host_mem_size_mb,
  57         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  58
  59 static unsigned int sgl_threshold = SZ_32K;
  60 module_param(sgl_threshold, uint, 0644);
  61 MODULE_PARM_DESC(sgl_threshold,
  62                 "Use SGLs when average request segment size is larger or equal to "
  63                 "this size. Use 0 to disable SGLs.");
  64
  65 #define NVME_PCI_MIN_QUEUE_SIZE 2
  66 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  68 static const struct kernel_param_ops io_queue_depth_ops = {
  69         .set = io_queue_depth_set,
  70         .get = param_get_uint,
  71 };
  72
  73 static unsigned int io_queue_depth = 1024;
  74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  76
  77 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  78 {
  79         unsigned int n;
  80         int ret;
  81
  82         ret = kstrtouint(val, 10, &n);
  83         if (ret != 0 || n > num_possible_cpus())
  84                 return -EINVAL;
  85         return param_set_uint(val, kp);
  86 }
  87
  88 static const struct kernel_param_ops io_queue_count_ops = {
  89         .set = io_queue_count_set,
  90         .get = param_get_uint,
  91 };
  92
  93 static unsigned int write_queues;
  94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  95 MODULE_PARM_DESC(write_queues,
  96         "Number of queues to use for writes. If not set, reads and writes "
  97         "will share a queue set.");
  98
  99 static unsigned int poll_queues;
 100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 102
 103 static bool noacpi;
 104 module_param(noacpi, bool, 0444);
 105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 106
 107 struct nvme_dev;
 108 struct nvme_queue;
 109
 110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 112
 113 /*
 114  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 115  */
 116 struct nvme_dev {
 117         struct nvme_queue *queues;
 118         struct blk_mq_tag_set tagset;
 119         struct blk_mq_tag_set admin_tagset;
 120         u32 __iomem *dbs;
 121         struct device *dev;
 122         struct dma_pool *prp_page_pool;
 123         struct dma_pool *prp_small_pool;
 124         unsigned online_queues;
 125         unsigned max_qid;
 126         unsigned io_queues[HCTX_MAX_TYPES];
 127         unsigned int num_vecs;
 128         u32 q_depth;
 129         int io_sqes;
 130         u32 db_stride;
 131         void __iomem *bar;
 132         unsigned long bar_mapped_size;
 133         struct work_struct remove_work;
 134         struct mutex shutdown_lock;
 135         bool subsystem;
 136         u64 cmb_size;
 137         bool cmb_use_sqes;
 138         u32 cmbsz;
 139         u32 cmbloc;
 140         struct nvme_ctrl ctrl;
 141         u32 last_ps;
 142         bool hmb;
 143
 144         mempool_t *iod_mempool;
 145
 146         /* shadow doorbell buffer support: */
 147         u32 *dbbuf_dbs;
 148         dma_addr_t dbbuf_dbs_dma_addr;
 149         u32 *dbbuf_eis;
 150         dma_addr_t dbbuf_eis_dma_addr;
 151
 152         /* host memory buffer support: */
 153         u64 host_mem_size;
 154         u32 nr_host_mem_descs;
 155         dma_addr_t host_mem_descs_dma;
 156         struct nvme_host_mem_buf_desc *host_mem_descs;
 157         void **host_mem_desc_bufs;
 158         unsigned int nr_allocated_queues;
 159         unsigned int nr_write_queues;
 160         unsigned int nr_poll_queues;
 161
 162         bool attrs_added;
 163 };
 164
 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 166 {
 167         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 168                         NVME_PCI_MAX_QUEUE_SIZE);
 169 }
 170
 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 172 {
 173         return qid * 2 * stride;
 174 }
 175
 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 177 {
 178         return (qid * 2 + 1) * stride;
 179 }
 180
 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 182 {
 183         return container_of(ctrl, struct nvme_dev, ctrl);
 184 }
 185
 186 /*
 187  * An NVM Express queue.  Each device has at least two (one for admin
 188  * commands and one for I/O commands).
 189  */
 190 struct nvme_queue {
 191         struct nvme_dev *dev;
 192         spinlock_t sq_lock;
 193         void *sq_cmds;
 194          /* only used for poll queues: */
 195         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 196         struct nvme_completion *cqes;
 197         dma_addr_t sq_dma_addr;
 198         dma_addr_t cq_dma_addr;
 199         u32 __iomem *q_db;
 200         u32 q_depth;
 201         u16 cq_vector;
 202         u16 sq_tail;
 203         u16 last_sq_tail;
 204         u16 cq_head;
 205         u16 qid;
 206         u8 cq_phase;
 207         u8 sqes;
 208         unsigned long flags;
 209 #define NVMEQ_ENABLED           0
 210 #define NVMEQ_SQ_CMB            1
 211 #define NVMEQ_DELETE_ERROR      2
 212 #define NVMEQ_POLLED            3
 213         u32 *dbbuf_sq_db;
 214         u32 *dbbuf_cq_db;
 215         u32 *dbbuf_sq_ei;
 216         u32 *dbbuf_cq_ei;
 217         struct completion delete_done;
 218 };
 219
 220 /*
 221  * The nvme_iod describes the data in an I/O.
 222  *
 223  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 224  * to the actual struct scatterlist.
 225  */
 226 struct nvme_iod {
 227         struct nvme_request req;
 228         struct nvme_command cmd;
 229         struct nvme_queue *nvmeq;
 230         bool use_sgl;
 231         int aborted;
 232         int npages;             /* In the PRP list. 0 means small pool in use */
 233         dma_addr_t first_dma;
 234         unsigned int dma_len;   /* length of single DMA segment mapping */
 235         dma_addr_t meta_dma;
 236         struct sg_table sgt;
 237 };
 238
 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240 {
 241         return dev->nr_allocated_queues * 8 * dev->db_stride;
 242 }
 243
 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245 {
 246         unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248         if (dev->dbbuf_dbs) {
 249                 /*
 250                  * Clear the dbbuf memory so the driver doesn't observe stale
 251                  * values from the previous instantiation.
 252                  */
 253                 memset(dev->dbbuf_dbs, 0, mem_size);
 254                 memset(dev->dbbuf_eis, 0, mem_size);
 255                 return 0;
 256         }
 257
 258         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 259                                             &dev->dbbuf_dbs_dma_addr,
 260                                             GFP_KERNEL);
 261         if (!dev->dbbuf_dbs)
 262                 return -ENOMEM;
 263         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 264                                             &dev->dbbuf_eis_dma_addr,
 265                                             GFP_KERNEL);
 266         if (!dev->dbbuf_eis) {
 267                 dma_free_coherent(dev->dev, mem_size,
 268                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 269                 dev->dbbuf_dbs = NULL;
 270                 return -ENOMEM;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 277 {
 278         unsigned int mem_size = nvme_dbbuf_size(dev);
 279
 280         if (dev->dbbuf_dbs) {
 281                 dma_free_coherent(dev->dev, mem_size,
 282                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 283                 dev->dbbuf_dbs = NULL;
 284         }
 285         if (dev->dbbuf_eis) {
 286                 dma_free_coherent(dev->dev, mem_size,
 287                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 288                 dev->dbbuf_eis = NULL;
 289         }
 290 }
 291
 292 static void nvme_dbbuf_init(struct nvme_dev *dev,
 293                             struct nvme_queue *nvmeq, int qid)
 294 {
 295         if (!dev->dbbuf_dbs || !qid)
 296                 return;
 297
 298         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 299         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 300         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 301         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 302 }
 303
 304 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 305 {
 306         if (!nvmeq->qid)
 307                 return;
 308
 309         nvmeq->dbbuf_sq_db = NULL;
 310         nvmeq->dbbuf_cq_db = NULL;
 311         nvmeq->dbbuf_sq_ei = NULL;
 312         nvmeq->dbbuf_cq_ei = NULL;
 313 }
 314
 315 static void nvme_dbbuf_set(struct nvme_dev *dev)
 316 {
 317         struct nvme_command c = { };
 318         unsigned int i;
 319
 320         if (!dev->dbbuf_dbs)
 321                 return;
 322
 323         c.dbbuf.opcode = nvme_admin_dbbuf;
 324         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 325         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 326
 327         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 328                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 329                 /* Free memory and continue on */
 330                 nvme_dbbuf_dma_free(dev);
 331
 332                 for (i = 1; i <= dev->online_queues; i++)
 333                         nvme_dbbuf_free(&dev->queues[i]);
 334         }
 335 }
 336
 337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 338 {
 339         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 340 }
 341
 342 /* Update dbbuf and return true if an MMIO is required */
 343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 344                                               volatile u32 *dbbuf_ei)
 345 {
 346         if (dbbuf_db) {
 347                 u16 old_value;
 348
 349                 /*
 350                  * Ensure that the queue is written before updating
 351                  * the doorbell in memory
 352                  */
 353                 wmb();
 354
 355                 old_value = *dbbuf_db;
 356                 *dbbuf_db = value;
 357
 358                 /*
 359                  * Ensure that the doorbell is updated before reading the event
 360                  * index from memory.  The controller needs to provide similar
 361                  * ordering to ensure the envent index is updated before reading
 362                  * the doorbell.
 363                  */
 364                 mb();
 365
 366                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 367                         return false;
 368         }
 369
 370         return true;
 371 }
 372
 373 /*
 374  * Will slightly overestimate the number of pages needed.  This is OK
 375  * as it only leads to a small amount of wasted memory for the lifetime of
 376  * the I/O.
 377  */
 378 static int nvme_pci_npages_prp(void)
 379 {
 380         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 381                                       NVME_CTRL_PAGE_SIZE);
 382         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 383 }
 384
 385 /*
 386  * Calculates the number of pages needed for the SGL segments. For example a 4k
 387  * page can accommodate 256 SGL descriptors.
 388  */
 389 static int nvme_pci_npages_sgl(void)
 390 {
 391         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 392                         PAGE_SIZE);
 393 }
 394
 395 static size_t nvme_pci_iod_alloc_size(void)
 396 {
 397         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 398
 399         return sizeof(__le64 *) * npages +
 400                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 401 }
 402
 403 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 404                                 unsigned int hctx_idx)
 405 {
 406         struct nvme_dev *dev = data;
 407         struct nvme_queue *nvmeq = &dev->queues[0];
 408
 409         WARN_ON(hctx_idx != 0);
 410         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 411
 412         hctx->driver_data = nvmeq;
 413         return 0;
 414 }
 415
 416 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 417                           unsigned int hctx_idx)
 418 {
 419         struct nvme_dev *dev = data;
 420         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 421
 422         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 423         hctx->driver_data = nvmeq;
 424         return 0;
 425 }
 426
 427 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 428                 struct request *req, unsigned int hctx_idx,
 429                 unsigned int numa_node)
 430 {
 431         struct nvme_dev *dev = set->driver_data;
 432         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 433         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 434         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 435
 436         BUG_ON(!nvmeq);
 437         iod->nvmeq = nvmeq;
 438
 439         nvme_req(req)->ctrl = &dev->ctrl;
 440         nvme_req(req)->cmd = &iod->cmd;
 441         return 0;
 442 }
 443
 444 static int queue_irq_offset(struct nvme_dev *dev)
 445 {
 446         /* if we have more than 1 vec, admin queue offsets us by 1 */
 447         if (dev->num_vecs > 1)
 448                 return 1;
 449
 450         return 0;
 451 }
 452
 453 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 454 {
 455         struct nvme_dev *dev = set->driver_data;
 456         int i, qoff, offset;
 457
 458         offset = queue_irq_offset(dev);
 459         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 460                 struct blk_mq_queue_map *map = &set->map[i];
 461
 462                 map->nr_queues = dev->io_queues[i];
 463                 if (!map->nr_queues) {
 464                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 465                         continue;
 466                 }
 467
 468                 /*
 469                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 470                  * affinity), so use the regular blk-mq cpu mapping
 471                  */
 472                 map->queue_offset = qoff;
 473                 if (i != HCTX_TYPE_POLL && offset)
 474                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 475                 else
 476                         blk_mq_map_queues(map);
 477                 qoff += map->nr_queues;
 478                 offset += map->nr_queues;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Write sq tail if we are asked to, or if the next command would wrap.
 486  */
 487 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 488 {
 489         if (!write_sq) {
 490                 u16 next_tail = nvmeq->sq_tail + 1;
 491
 492                 if (next_tail == nvmeq->q_depth)
 493                         next_tail = 0;
 494                 if (next_tail != nvmeq->last_sq_tail)
 495                         return;
 496         }
 497
 498         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 499                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 500                 writel(nvmeq->sq_tail, nvmeq->q_db);
 501         nvmeq->last_sq_tail = nvmeq->sq_tail;
 502 }
 503
 504 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 505                                     struct nvme_command *cmd)
 506 {
 507         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 508                 absolute_pointer(cmd), sizeof(*cmd));
 509         if (++nvmeq->sq_tail == nvmeq->q_depth)
 510                 nvmeq->sq_tail = 0;
 511 }
 512
 513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 514 {
 515         struct nvme_queue *nvmeq = hctx->driver_data;
 516
 517         spin_lock(&nvmeq->sq_lock);
 518         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 519                 nvme_write_sq_db(nvmeq, true);
 520         spin_unlock(&nvmeq->sq_lock);
 521 }
 522
 523 static void **nvme_pci_iod_list(struct request *req)
 524 {
 525         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 526         return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
 527 }
 528
 529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 530 {
 531         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 532         int nseg = blk_rq_nr_phys_segments(req);
 533         unsigned int avg_seg_size;
 534
 535         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 536
 537         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 538                 return false;
 539         if (!iod->nvmeq->qid)
 540                 return false;
 541         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 542                 return false;
 543         return true;
 544 }
 545
 546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 547 {
 548         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 549         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 550         dma_addr_t dma_addr = iod->first_dma;
 551         int i;
 552
 553         for (i = 0; i < iod->npages; i++) {
 554                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 555                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 556
 557                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 558                 dma_addr = next_dma_addr;
 559         }
 560 }
 561
 562 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 563 {
 564         const int last_sg = SGES_PER_PAGE - 1;
 565         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 566         dma_addr_t dma_addr = iod->first_dma;
 567         int i;
 568
 569         for (i = 0; i < iod->npages; i++) {
 570                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 571                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 572
 573                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 574                 dma_addr = next_dma_addr;
 575         }
 576 }
 577
 578 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 579 {
 580         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 581
 582         if (iod->dma_len) {
 583                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 584                                rq_dma_dir(req));
 585                 return;
 586         }
 587
 588         WARN_ON_ONCE(!iod->sgt.nents);
 589
 590         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 591
 592         if (iod->npages == 0)
 593                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 594                               iod->first_dma);
 595         else if (iod->use_sgl)
 596                 nvme_free_sgls(dev, req);
 597         else
 598                 nvme_free_prps(dev, req);
 599         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 600 }
 601
 602 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 603 {
 604         int i;
 605         struct scatterlist *sg;
 606
 607         for_each_sg(sgl, sg, nents, i) {
 608                 dma_addr_t phys = sg_phys(sg);
 609                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 610                         "dma_address:%pad dma_length:%d\n",
 611                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 612                         sg_dma_len(sg));
 613         }
 614 }
 615
 616 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 617                 struct request *req, struct nvme_rw_command *cmnd)
 618 {
 619         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 620         struct dma_pool *pool;
 621         int length = blk_rq_payload_bytes(req);
 622         struct scatterlist *sg = iod->sgt.sgl;
 623         int dma_len = sg_dma_len(sg);
 624         u64 dma_addr = sg_dma_address(sg);
 625         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 626         __le64 *prp_list;
 627         void **list = nvme_pci_iod_list(req);
 628         dma_addr_t prp_dma;
 629         int nprps, i;
 630
 631         length -= (NVME_CTRL_PAGE_SIZE - offset);
 632         if (length <= 0) {
 633                 iod->first_dma = 0;
 634                 goto done;
 635         }
 636
 637         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 638         if (dma_len) {
 639                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 640         } else {
 641                 sg = sg_next(sg);
 642                 dma_addr = sg_dma_address(sg);
 643                 dma_len = sg_dma_len(sg);
 644         }
 645
 646         if (length <= NVME_CTRL_PAGE_SIZE) {
 647                 iod->first_dma = dma_addr;
 648                 goto done;
 649         }
 650
 651         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 652         if (nprps <= (256 / 8)) {
 653                 pool = dev->prp_small_pool;
 654                 iod->npages = 0;
 655         } else {
 656                 pool = dev->prp_page_pool;
 657                 iod->npages = 1;
 658         }
 659
 660         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 661         if (!prp_list) {
 662                 iod->npages = -1;
 663                 return BLK_STS_RESOURCE;
 664         }
 665         list[0] = prp_list;
 666         iod->first_dma = prp_dma;
 667         i = 0;
 668         for (;;) {
 669                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 670                         __le64 *old_prp_list = prp_list;
 671                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 672                         if (!prp_list)
 673                                 goto free_prps;
 674                         list[iod->npages++] = prp_list;
 675                         prp_list[0] = old_prp_list[i - 1];
 676                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 677                         i = 1;
 678                 }
 679                 prp_list[i++] = cpu_to_le64(dma_addr);
 680                 dma_len -= NVME_CTRL_PAGE_SIZE;
 681                 dma_addr += NVME_CTRL_PAGE_SIZE;
 682                 length -= NVME_CTRL_PAGE_SIZE;
 683                 if (length <= 0)
 684                         break;
 685                 if (dma_len > 0)
 686                         continue;
 687                 if (unlikely(dma_len < 0))
 688                         goto bad_sgl;
 689                 sg = sg_next(sg);
 690                 dma_addr = sg_dma_address(sg);
 691                 dma_len = sg_dma_len(sg);
 692         }
 693 done:
 694         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
 695         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 696         return BLK_STS_OK;
 697 free_prps:
 698         nvme_free_prps(dev, req);
 699         return BLK_STS_RESOURCE;
 700 bad_sgl:
 701         WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
 702                         "Invalid SGL for payload:%d nents:%d\n",
 703                         blk_rq_payload_bytes(req), iod->sgt.nents);
 704         return BLK_STS_IOERR;
 705 }
 706
 707 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 708                 struct scatterlist *sg)
 709 {
 710         sge->addr = cpu_to_le64(sg_dma_address(sg));
 711         sge->length = cpu_to_le32(sg_dma_len(sg));
 712         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 713 }
 714
 715 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 716                 dma_addr_t dma_addr, int entries)
 717 {
 718         sge->addr = cpu_to_le64(dma_addr);
 719         if (entries < SGES_PER_PAGE) {
 720                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 721                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 722         } else {
 723                 sge->length = cpu_to_le32(PAGE_SIZE);
 724                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 725         }
 726 }
 727
 728 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 729                 struct request *req, struct nvme_rw_command *cmd)
 730 {
 731         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 732         struct dma_pool *pool;
 733         struct nvme_sgl_desc *sg_list;
 734         struct scatterlist *sg = iod->sgt.sgl;
 735         unsigned int entries = iod->sgt.nents;
 736         dma_addr_t sgl_dma;
 737         int i = 0;
 738
 739         /* setting the transfer type as SGL */
 740         cmd->flags = NVME_CMD_SGL_METABUF;
 741
 742         if (entries == 1) {
 743                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 744                 return BLK_STS_OK;
 745         }
 746
 747         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 748                 pool = dev->prp_small_pool;
 749                 iod->npages = 0;
 750         } else {
 751                 pool = dev->prp_page_pool;
 752                 iod->npages = 1;
 753         }
 754
 755         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 756         if (!sg_list) {
 757                 iod->npages = -1;
 758                 return BLK_STS_RESOURCE;
 759         }
 760
 761         nvme_pci_iod_list(req)[0] = sg_list;
 762         iod->first_dma = sgl_dma;
 763
 764         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 765
 766         do {
 767                 if (i == SGES_PER_PAGE) {
 768                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 769                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 770
 771                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 772                         if (!sg_list)
 773                                 goto free_sgls;
 774
 775                         i = 0;
 776                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 777                         sg_list[i++] = *link;
 778                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 779                 }
 780
 781                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 782                 sg = sg_next(sg);
 783         } while (--entries > 0);
 784
 785         return BLK_STS_OK;
 786 free_sgls:
 787         nvme_free_sgls(dev, req);
 788         return BLK_STS_RESOURCE;
 789 }
 790
 791 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 792                 struct request *req, struct nvme_rw_command *cmnd,
 793                 struct bio_vec *bv)
 794 {
 795         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 796         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 797         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 798
 799         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 800         if (dma_mapping_error(dev->dev, iod->first_dma))
 801                 return BLK_STS_RESOURCE;
 802         iod->dma_len = bv->bv_len;
 803
 804         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 805         if (bv->bv_len > first_prp_len)
 806                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 807         return BLK_STS_OK;
 808 }
 809
 810 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 811                 struct request *req, struct nvme_rw_command *cmnd,
 812                 struct bio_vec *bv)
 813 {
 814         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 815
 816         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 817         if (dma_mapping_error(dev->dev, iod->first_dma))
 818                 return BLK_STS_RESOURCE;
 819         iod->dma_len = bv->bv_len;
 820
 821         cmnd->flags = NVME_CMD_SGL_METABUF;
 822         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 823         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 824         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 825         return BLK_STS_OK;
 826 }
 827
 828 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 829                 struct nvme_command *cmnd)
 830 {
 831         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 832         blk_status_t ret = BLK_STS_RESOURCE;
 833         int rc;
 834
 835         if (blk_rq_nr_phys_segments(req) == 1) {
 836                 struct bio_vec bv = req_bvec(req);
 837
 838                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 839                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 840                                 return nvme_setup_prp_simple(dev, req,
 841                                                              &cmnd->rw, &bv);
 842
 843                         if (iod->nvmeq->qid && sgl_threshold &&
 844                             nvme_ctrl_sgl_supported(&dev->ctrl))
 845                                 return nvme_setup_sgl_simple(dev, req,
 846                                                              &cmnd->rw, &bv);
 847                 }
 848         }
 849
 850         iod->dma_len = 0;
 851         iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 852         if (!iod->sgt.sgl)
 853                 return BLK_STS_RESOURCE;
 854         sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
 855         iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
 856         if (!iod->sgt.orig_nents)
 857                 goto out_free_sg;
 858
 859         rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
 860                              DMA_ATTR_NO_WARN);
 861         if (rc) {
 862                 if (rc == -EREMOTEIO)
 863                         ret = BLK_STS_TARGET;
 864                 goto out_free_sg;
 865         }
 866
 867         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 868         if (iod->use_sgl)
 869                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
 870         else
 871                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 872         if (ret != BLK_STS_OK)
 873                 goto out_unmap_sg;
 874         return BLK_STS_OK;
 875
 876 out_unmap_sg:
 877         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 878 out_free_sg:
 879         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 880         return ret;
 881 }
 882
 883 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 884                 struct nvme_command *cmnd)
 885 {
 886         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 887
 888         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 889                         rq_dma_dir(req), 0);
 890         if (dma_mapping_error(dev->dev, iod->meta_dma))
 891                 return BLK_STS_IOERR;
 892         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 893         return BLK_STS_OK;
 894 }
 895
 896 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 897 {
 898         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 899         blk_status_t ret;
 900
 901         iod->aborted = 0;
 902         iod->npages = -1;
 903         iod->sgt.nents = 0;
 904
 905         ret = nvme_setup_cmd(req->q->queuedata, req);
 906         if (ret)
 907                 return ret;
 908
 909         if (blk_rq_nr_phys_segments(req)) {
 910                 ret = nvme_map_data(dev, req, &iod->cmd);
 911                 if (ret)
 912                         goto out_free_cmd;
 913         }
 914
 915         if (blk_integrity_rq(req)) {
 916                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 917                 if (ret)
 918                         goto out_unmap_data;
 919         }
 920
 921         blk_mq_start_request(req);
 922         return BLK_STS_OK;
 923 out_unmap_data:
 924         nvme_unmap_data(dev, req);
 925 out_free_cmd:
 926         nvme_cleanup_cmd(req);
 927         return ret;
 928 }
 929
 930 /*
 931  * NOTE: ns is NULL when called on the admin queue.
 932  */
 933 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 934                          const struct blk_mq_queue_data *bd)
 935 {
 936         struct nvme_queue *nvmeq = hctx->driver_data;
 937         struct nvme_dev *dev = nvmeq->dev;
 938         struct request *req = bd->rq;
 939         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 940         blk_status_t ret;
 941
 942         /*
 943          * We should not need to do this, but we're still using this to
 944          * ensure we can drain requests on a dying queue.
 945          */
 946         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 947                 return BLK_STS_IOERR;
 948
 949         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 950                 return nvme_fail_nonready_command(&dev->ctrl, req);
 951
 952         ret = nvme_prep_rq(dev, req);
 953         if (unlikely(ret))
 954                 return ret;
 955         spin_lock(&nvmeq->sq_lock);
 956         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 957         nvme_write_sq_db(nvmeq, bd->last);
 958         spin_unlock(&nvmeq->sq_lock);
 959         return BLK_STS_OK;
 960 }
 961
 962 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 963 {
 964         spin_lock(&nvmeq->sq_lock);
 965         while (!rq_list_empty(*rqlist)) {
 966                 struct request *req = rq_list_pop(rqlist);
 967                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 968
 969                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 970         }
 971         nvme_write_sq_db(nvmeq, true);
 972         spin_unlock(&nvmeq->sq_lock);
 973 }
 974
 975 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 976 {
 977         /*
 978          * We should not need to do this, but we're still using this to
 979          * ensure we can drain requests on a dying queue.
 980          */
 981         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 982                 return false;
 983         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 984                 return false;
 985
 986         req->mq_hctx->tags->rqs[req->tag] = req;
 987         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 988 }
 989
 990 static void nvme_queue_rqs(struct request **rqlist)
 991 {
 992         struct request *req, *next, *prev = NULL;
 993         struct request *requeue_list = NULL;
 994
 995         rq_list_for_each_safe(rqlist, req, next) {
 996                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 997
 998                 if (!nvme_prep_rq_batch(nvmeq, req)) {
 999                         /* detach 'req' and add to remainder list */
1000                         rq_list_move(rqlist, &requeue_list, req, prev);
1001
1002                         req = prev;
1003                         if (!req)
1004                                 continue;
1005                 }
1006
1007                 if (!next || req->mq_hctx != next->mq_hctx) {
1008                         /* detach rest of list, and submit */
1009                         req->rq_next = NULL;
1010                         nvme_submit_cmds(nvmeq, rqlist);
1011                         *rqlist = next;
1012                         prev = NULL;
1013                 } else
1014                         prev = req;
1015         }
1016
1017         *rqlist = requeue_list;
1018 }
1019
1020 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1021 {
1022         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1023         struct nvme_dev *dev = iod->nvmeq->dev;
1024
1025         if (blk_integrity_rq(req))
1026                 dma_unmap_page(dev->dev, iod->meta_dma,
1027                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1028         if (blk_rq_nr_phys_segments(req))
1029                 nvme_unmap_data(dev, req);
1030 }
1031
1032 static void nvme_pci_complete_rq(struct request *req)
1033 {
1034         nvme_pci_unmap_rq(req);
1035         nvme_complete_rq(req);
1036 }
1037
1038 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1039 {
1040         nvme_complete_batch(iob, nvme_pci_unmap_rq);
1041 }
1042
1043 /* We read the CQE phase first to check if the rest of the entry is valid */
1044 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1045 {
1046         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1047
1048         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1049 }
1050
1051 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1052 {
1053         u16 head = nvmeq->cq_head;
1054
1055         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1056                                               nvmeq->dbbuf_cq_ei))
1057                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1058 }
1059
1060 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1061 {
1062         if (!nvmeq->qid)
1063                 return nvmeq->dev->admin_tagset.tags[0];
1064         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1065 }
1066
1067 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1068                                    struct io_comp_batch *iob, u16 idx)
1069 {
1070         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1071         __u16 command_id = READ_ONCE(cqe->command_id);
1072         struct request *req;
1073
1074         /*
1075          * AEN requests are special as they don't time out and can
1076          * survive any kind of queue freeze and often don't respond to
1077          * aborts.  We don't even bother to allocate a struct request
1078          * for them but rather special case them here.
1079          */
1080         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1081                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1082                                 cqe->status, &cqe->result);
1083                 return;
1084         }
1085
1086         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1087         if (unlikely(!req)) {
1088                 dev_warn(nvmeq->dev->ctrl.device,
1089                         "invalid id %d completed on queue %d\n",
1090                         command_id, le16_to_cpu(cqe->sq_id));
1091                 return;
1092         }
1093
1094         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1095         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1096             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1097                                         nvme_pci_complete_batch))
1098                 nvme_pci_complete_rq(req);
1099 }
1100
1101 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1102 {
1103         u32 tmp = nvmeq->cq_head + 1;
1104
1105         if (tmp == nvmeq->q_depth) {
1106                 nvmeq->cq_head = 0;
1107                 nvmeq->cq_phase ^= 1;
1108         } else {
1109                 nvmeq->cq_head = tmp;
1110         }
1111 }
1112
1113 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1114                                struct io_comp_batch *iob)
1115 {
1116         int found = 0;
1117
1118         while (nvme_cqe_pending(nvmeq)) {
1119                 found++;
1120                 /*
1121                  * load-load control dependency between phase and the rest of
1122                  * the cqe requires a full read memory barrier
1123                  */
1124                 dma_rmb();
1125                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1126                 nvme_update_cq_head(nvmeq);
1127         }
1128
1129         if (found)
1130                 nvme_ring_cq_doorbell(nvmeq);
1131         return found;
1132 }
1133
1134 static irqreturn_t nvme_irq(int irq, void *data)
1135 {
1136         struct nvme_queue *nvmeq = data;
1137         DEFINE_IO_COMP_BATCH(iob);
1138
1139         if (nvme_poll_cq(nvmeq, &iob)) {
1140                 if (!rq_list_empty(iob.req_list))
1141                         nvme_pci_complete_batch(&iob);
1142                 return IRQ_HANDLED;
1143         }
1144         return IRQ_NONE;
1145 }
1146
1147 static irqreturn_t nvme_irq_check(int irq, void *data)
1148 {
1149         struct nvme_queue *nvmeq = data;
1150
1151         if (nvme_cqe_pending(nvmeq))
1152                 return IRQ_WAKE_THREAD;
1153         return IRQ_NONE;
1154 }
1155
1156 /*
1157  * Poll for completions for any interrupt driven queue
1158  * Can be called from any context.
1159  */
1160 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1161 {
1162         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1163
1164         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1165
1166         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1167         nvme_poll_cq(nvmeq, NULL);
1168         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1169 }
1170
1171 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1172 {
1173         struct nvme_queue *nvmeq = hctx->driver_data;
1174         bool found;
1175
1176         if (!nvme_cqe_pending(nvmeq))
1177                 return 0;
1178
1179         spin_lock(&nvmeq->cq_poll_lock);
1180         found = nvme_poll_cq(nvmeq, iob);
1181         spin_unlock(&nvmeq->cq_poll_lock);
1182
1183         return found;
1184 }
1185
1186 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1187 {
1188         struct nvme_dev *dev = to_nvme_dev(ctrl);
1189         struct nvme_queue *nvmeq = &dev->queues[0];
1190         struct nvme_command c = { };
1191
1192         c.common.opcode = nvme_admin_async_event;
1193         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1194
1195         spin_lock(&nvmeq->sq_lock);
1196         nvme_sq_copy_cmd(nvmeq, &c);
1197         nvme_write_sq_db(nvmeq, true);
1198         spin_unlock(&nvmeq->sq_lock);
1199 }
1200
1201 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1202 {
1203         struct nvme_command c = { };
1204
1205         c.delete_queue.opcode = opcode;
1206         c.delete_queue.qid = cpu_to_le16(id);
1207
1208         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1209 }
1210
1211 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1212                 struct nvme_queue *nvmeq, s16 vector)
1213 {
1214         struct nvme_command c = { };
1215         int flags = NVME_QUEUE_PHYS_CONTIG;
1216
1217         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1218                 flags |= NVME_CQ_IRQ_ENABLED;
1219
1220         /*
1221          * Note: we (ab)use the fact that the prp fields survive if no data
1222          * is attached to the request.
1223          */
1224         c.create_cq.opcode = nvme_admin_create_cq;
1225         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1226         c.create_cq.cqid = cpu_to_le16(qid);
1227         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1228         c.create_cq.cq_flags = cpu_to_le16(flags);
1229         c.create_cq.irq_vector = cpu_to_le16(vector);
1230
1231         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1232 }
1233
1234 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1235                                                 struct nvme_queue *nvmeq)
1236 {
1237         struct nvme_ctrl *ctrl = &dev->ctrl;
1238         struct nvme_command c = { };
1239         int flags = NVME_QUEUE_PHYS_CONTIG;
1240
1241         /*
1242          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1243          * set. Since URGENT priority is zeroes, it makes all queues
1244          * URGENT.
1245          */
1246         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1247                 flags |= NVME_SQ_PRIO_MEDIUM;
1248
1249         /*
1250          * Note: we (ab)use the fact that the prp fields survive if no data
1251          * is attached to the request.
1252          */
1253         c.create_sq.opcode = nvme_admin_create_sq;
1254         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1255         c.create_sq.sqid = cpu_to_le16(qid);
1256         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1257         c.create_sq.sq_flags = cpu_to_le16(flags);
1258         c.create_sq.cqid = cpu_to_le16(qid);
1259
1260         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1261 }
1262
1263 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1264 {
1265         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1266 }
1267
1268 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1269 {
1270         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1271 }
1272
1273 static void abort_endio(struct request *req, blk_status_t error)
1274 {
1275         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1276         struct nvme_queue *nvmeq = iod->nvmeq;
1277
1278         dev_warn(nvmeq->dev->ctrl.device,
1279                  "Abort status: 0x%x", nvme_req(req)->status);
1280         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1281         blk_mq_free_request(req);
1282 }
1283
1284 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1285 {
1286         /* If true, indicates loss of adapter communication, possibly by a
1287          * NVMe Subsystem reset.
1288          */
1289         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1290
1291         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1292         switch (dev->ctrl.state) {
1293         case NVME_CTRL_RESETTING:
1294         case NVME_CTRL_CONNECTING:
1295                 return false;
1296         default:
1297                 break;
1298         }
1299
1300         /* We shouldn't reset unless the controller is on fatal error state
1301          * _or_ if we lost the communication with it.
1302          */
1303         if (!(csts & NVME_CSTS_CFS) && !nssro)
1304                 return false;
1305
1306         return true;
1307 }
1308
1309 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1310 {
1311         /* Read a config register to help see what died. */
1312         u16 pci_status;
1313         int result;
1314
1315         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1316                                       &pci_status);
1317         if (result == PCIBIOS_SUCCESSFUL)
1318                 dev_warn(dev->ctrl.device,
1319                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1320                          csts, pci_status);
1321         else
1322                 dev_warn(dev->ctrl.device,
1323                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1324                          csts, result);
1325
1326         if (csts != ~0)
1327                 return;
1328
1329         dev_warn(dev->ctrl.device,
1330                  "Does your device have a faulty power saving mode enabled?\n");
1331         dev_warn(dev->ctrl.device,
1332                  "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1333 }
1334
1335 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1336 {
1337         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1338         struct nvme_queue *nvmeq = iod->nvmeq;
1339         struct nvme_dev *dev = nvmeq->dev;
1340         struct request *abort_req;
1341         struct nvme_command cmd = { };
1342         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1343
1344         /* If PCI error recovery process is happening, we cannot reset or
1345          * the recovery mechanism will surely fail.
1346          */
1347         mb();
1348         if (pci_channel_offline(to_pci_dev(dev->dev)))
1349                 return BLK_EH_RESET_TIMER;
1350
1351         /*
1352          * Reset immediately if the controller is failed
1353          */
1354         if (nvme_should_reset(dev, csts)) {
1355                 nvme_warn_reset(dev, csts);
1356                 nvme_dev_disable(dev, false);
1357                 nvme_reset_ctrl(&dev->ctrl);
1358                 return BLK_EH_DONE;
1359         }
1360
1361         /*
1362          * Did we miss an interrupt?
1363          */
1364         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1365                 nvme_poll(req->mq_hctx, NULL);
1366         else
1367                 nvme_poll_irqdisable(nvmeq);
1368
1369         if (blk_mq_request_completed(req)) {
1370                 dev_warn(dev->ctrl.device,
1371                          "I/O %d QID %d timeout, completion polled\n",
1372                          req->tag, nvmeq->qid);
1373                 return BLK_EH_DONE;
1374         }
1375
1376         /*
1377          * Shutdown immediately if controller times out while starting. The
1378          * reset work will see the pci device disabled when it gets the forced
1379          * cancellation error. All outstanding requests are completed on
1380          * shutdown, so we return BLK_EH_DONE.
1381          */
1382         switch (dev->ctrl.state) {
1383         case NVME_CTRL_CONNECTING:
1384                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1385                 fallthrough;
1386         case NVME_CTRL_DELETING:
1387                 dev_warn_ratelimited(dev->ctrl.device,
1388                          "I/O %d QID %d timeout, disable controller\n",
1389                          req->tag, nvmeq->qid);
1390                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1391                 nvme_dev_disable(dev, true);
1392                 return BLK_EH_DONE;
1393         case NVME_CTRL_RESETTING:
1394                 return BLK_EH_RESET_TIMER;
1395         default:
1396                 break;
1397         }
1398
1399         /*
1400          * Shutdown the controller immediately and schedule a reset if the
1401          * command was already aborted once before and still hasn't been
1402          * returned to the driver, or if this is the admin queue.
1403          */
1404         if (!nvmeq->qid || iod->aborted) {
1405                 dev_warn(dev->ctrl.device,
1406                          "I/O %d QID %d timeout, reset controller\n",
1407                          req->tag, nvmeq->qid);
1408                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1409                 nvme_dev_disable(dev, false);
1410                 nvme_reset_ctrl(&dev->ctrl);
1411
1412                 return BLK_EH_DONE;
1413         }
1414
1415         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1416                 atomic_inc(&dev->ctrl.abort_limit);
1417                 return BLK_EH_RESET_TIMER;
1418         }
1419         iod->aborted = 1;
1420
1421         cmd.abort.opcode = nvme_admin_abort_cmd;
1422         cmd.abort.cid = nvme_cid(req);
1423         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1424
1425         dev_warn(nvmeq->dev->ctrl.device,
1426                 "I/O %d (%s) QID %d timeout, aborting\n",
1427                  req->tag,
1428                  nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1429                  nvmeq->qid);
1430
1431         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1432                                          BLK_MQ_REQ_NOWAIT);
1433         if (IS_ERR(abort_req)) {
1434                 atomic_inc(&dev->ctrl.abort_limit);
1435                 return BLK_EH_RESET_TIMER;
1436         }
1437         nvme_init_request(abort_req, &cmd);
1438
1439         abort_req->end_io = abort_endio;
1440         abort_req->end_io_data = NULL;
1441         abort_req->rq_flags |= RQF_QUIET;
1442         blk_execute_rq_nowait(abort_req, false);
1443
1444         /*
1445          * The aborted req will be completed on receiving the abort req.
1446          * We enable the timer again. If hit twice, it'll cause a device reset,
1447          * as the device then is in a faulty state.
1448          */
1449         return BLK_EH_RESET_TIMER;
1450 }
1451
1452 static void nvme_free_queue(struct nvme_queue *nvmeq)
1453 {
1454         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1455                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1456         if (!nvmeq->sq_cmds)
1457                 return;
1458
1459         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1460                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1461                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1462         } else {
1463                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1464                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1465         }
1466 }
1467
1468 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1469 {
1470         int i;
1471
1472         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1473                 dev->ctrl.queue_count--;
1474                 nvme_free_queue(&dev->queues[i]);
1475         }
1476 }
1477
1478 /**
1479  * nvme_suspend_queue - put queue into suspended state
1480  * @nvmeq: queue to suspend
1481  */
1482 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1483 {
1484         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1485                 return 1;
1486
1487         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1488         mb();
1489
1490         nvmeq->dev->online_queues--;
1491         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1492                 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1493         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1494                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1495         return 0;
1496 }
1497
1498 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1499 {
1500         int i;
1501
1502         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1503                 nvme_suspend_queue(&dev->queues[i]);
1504 }
1505
1506 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1507 {
1508         struct nvme_queue *nvmeq = &dev->queues[0];
1509
1510         if (shutdown)
1511                 nvme_shutdown_ctrl(&dev->ctrl);
1512         else
1513                 nvme_disable_ctrl(&dev->ctrl);
1514
1515         nvme_poll_irqdisable(nvmeq);
1516 }
1517
1518 /*
1519  * Called only on a device that has been disabled and after all other threads
1520  * that can check this device's completion queues have synced, except
1521  * nvme_poll(). This is the last chance for the driver to see a natural
1522  * completion before nvme_cancel_request() terminates all incomplete requests.
1523  */
1524 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1525 {
1526         int i;
1527
1528         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1529                 spin_lock(&dev->queues[i].cq_poll_lock);
1530                 nvme_poll_cq(&dev->queues[i], NULL);
1531                 spin_unlock(&dev->queues[i].cq_poll_lock);
1532         }
1533 }
1534
1535 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1536                                 int entry_size)
1537 {
1538         int q_depth = dev->q_depth;
1539         unsigned q_size_aligned = roundup(q_depth * entry_size,
1540                                           NVME_CTRL_PAGE_SIZE);
1541
1542         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1543                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1544
1545                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1546                 q_depth = div_u64(mem_per_q, entry_size);
1547
1548                 /*
1549                  * Ensure the reduced q_depth is above some threshold where it
1550                  * would be better to map queues in system memory with the
1551                  * original depth
1552                  */
1553                 if (q_depth < 64)
1554                         return -ENOMEM;
1555         }
1556
1557         return q_depth;
1558 }
1559
1560 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1561                                 int qid)
1562 {
1563         struct pci_dev *pdev = to_pci_dev(dev->dev);
1564
1565         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1566                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1567                 if (nvmeq->sq_cmds) {
1568                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1569                                                         nvmeq->sq_cmds);
1570                         if (nvmeq->sq_dma_addr) {
1571                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1572                                 return 0;
1573                         }
1574
1575                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1576                 }
1577         }
1578
1579         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1580                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1581         if (!nvmeq->sq_cmds)
1582                 return -ENOMEM;
1583         return 0;
1584 }
1585
1586 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1587 {
1588         struct nvme_queue *nvmeq = &dev->queues[qid];
1589
1590         if (dev->ctrl.queue_count > qid)
1591                 return 0;
1592
1593         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1594         nvmeq->q_depth = depth;
1595         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1596                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1597         if (!nvmeq->cqes)
1598                 goto free_nvmeq;
1599
1600         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1601                 goto free_cqdma;
1602
1603         nvmeq->dev = dev;
1604         spin_lock_init(&nvmeq->sq_lock);
1605         spin_lock_init(&nvmeq->cq_poll_lock);
1606         nvmeq->cq_head = 0;
1607         nvmeq->cq_phase = 1;
1608         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1609         nvmeq->qid = qid;
1610         dev->ctrl.queue_count++;
1611
1612         return 0;
1613
1614  free_cqdma:
1615         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1616                           nvmeq->cq_dma_addr);
1617  free_nvmeq:
1618         return -ENOMEM;
1619 }
1620
1621 static int queue_request_irq(struct nvme_queue *nvmeq)
1622 {
1623         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1624         int nr = nvmeq->dev->ctrl.instance;
1625
1626         if (use_threaded_interrupts) {
1627                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1628                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1629         } else {
1630                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1631                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1632         }
1633 }
1634
1635 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1636 {
1637         struct nvme_dev *dev = nvmeq->dev;
1638
1639         nvmeq->sq_tail = 0;
1640         nvmeq->last_sq_tail = 0;
1641         nvmeq->cq_head = 0;
1642         nvmeq->cq_phase = 1;
1643         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1644         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1645         nvme_dbbuf_init(dev, nvmeq, qid);
1646         dev->online_queues++;
1647         wmb(); /* ensure the first interrupt sees the initialization */
1648 }
1649
1650 /*
1651  * Try getting shutdown_lock while setting up IO queues.
1652  */
1653 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1654 {
1655         /*
1656          * Give up if the lock is being held by nvme_dev_disable.
1657          */
1658         if (!mutex_trylock(&dev->shutdown_lock))
1659                 return -ENODEV;
1660
1661         /*
1662          * Controller is in wrong state, fail early.
1663          */
1664         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1665                 mutex_unlock(&dev->shutdown_lock);
1666                 return -ENODEV;
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1673 {
1674         struct nvme_dev *dev = nvmeq->dev;
1675         int result;
1676         u16 vector = 0;
1677
1678         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1679
1680         /*
1681          * A queue's vector matches the queue identifier unless the controller
1682          * has only one vector available.
1683          */
1684         if (!polled)
1685                 vector = dev->num_vecs == 1 ? 0 : qid;
1686         else
1687                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1688
1689         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1690         if (result)
1691                 return result;
1692
1693         result = adapter_alloc_sq(dev, qid, nvmeq);
1694         if (result < 0)
1695                 return result;
1696         if (result)
1697                 goto release_cq;
1698
1699         nvmeq->cq_vector = vector;
1700
1701         result = nvme_setup_io_queues_trylock(dev);
1702         if (result)
1703                 return result;
1704         nvme_init_queue(nvmeq, qid);
1705         if (!polled) {
1706                 result = queue_request_irq(nvmeq);
1707                 if (result < 0)
1708                         goto release_sq;
1709         }
1710
1711         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1712         mutex_unlock(&dev->shutdown_lock);
1713         return result;
1714
1715 release_sq:
1716         dev->online_queues--;
1717         mutex_unlock(&dev->shutdown_lock);
1718         adapter_delete_sq(dev, qid);
1719 release_cq:
1720         adapter_delete_cq(dev, qid);
1721         return result;
1722 }
1723
1724 static const struct blk_mq_ops nvme_mq_admin_ops = {
1725         .queue_rq       = nvme_queue_rq,
1726         .complete       = nvme_pci_complete_rq,
1727         .init_hctx      = nvme_admin_init_hctx,
1728         .init_request   = nvme_pci_init_request,
1729         .timeout        = nvme_timeout,
1730 };
1731
1732 static const struct blk_mq_ops nvme_mq_ops = {
1733         .queue_rq       = nvme_queue_rq,
1734         .queue_rqs      = nvme_queue_rqs,
1735         .complete       = nvme_pci_complete_rq,
1736         .commit_rqs     = nvme_commit_rqs,
1737         .init_hctx      = nvme_init_hctx,
1738         .init_request   = nvme_pci_init_request,
1739         .map_queues     = nvme_pci_map_queues,
1740         .timeout        = nvme_timeout,
1741         .poll           = nvme_poll,
1742 };
1743
1744 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1745 {
1746         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1747                 /*
1748                  * If the controller was reset during removal, it's possible
1749                  * user requests may be waiting on a stopped queue. Start the
1750                  * queue to flush these to completion.
1751                  */
1752                 nvme_start_admin_queue(&dev->ctrl);
1753                 blk_mq_destroy_queue(dev->ctrl.admin_q);
1754                 blk_mq_free_tag_set(&dev->admin_tagset);
1755         }
1756 }
1757
1758 static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
1759 {
1760         struct blk_mq_tag_set *set = &dev->admin_tagset;
1761
1762         set->ops = &nvme_mq_admin_ops;
1763         set->nr_hw_queues = 1;
1764
1765         set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1766         set->timeout = NVME_ADMIN_TIMEOUT;
1767         set->numa_node = dev->ctrl.numa_node;
1768         set->cmd_size = sizeof(struct nvme_iod);
1769         set->flags = BLK_MQ_F_NO_SCHED;
1770         set->driver_data = dev;
1771
1772         if (blk_mq_alloc_tag_set(set))
1773                 return -ENOMEM;
1774         dev->ctrl.admin_tagset = set;
1775
1776         dev->ctrl.admin_q = blk_mq_init_queue(set);
1777         if (IS_ERR(dev->ctrl.admin_q)) {
1778                 blk_mq_free_tag_set(set);
1779                 dev->ctrl.admin_q = NULL;
1780                 return -ENOMEM;
1781         }
1782         if (!blk_get_queue(dev->ctrl.admin_q)) {
1783                 nvme_dev_remove_admin(dev);
1784                 dev->ctrl.admin_q = NULL;
1785                 return -ENODEV;
1786         }
1787         return 0;
1788 }
1789
1790 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1791 {
1792         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1793 }
1794
1795 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1796 {
1797         struct pci_dev *pdev = to_pci_dev(dev->dev);
1798
1799         if (size <= dev->bar_mapped_size)
1800                 return 0;
1801         if (size > pci_resource_len(pdev, 0))
1802                 return -ENOMEM;
1803         if (dev->bar)
1804                 iounmap(dev->bar);
1805         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1806         if (!dev->bar) {
1807                 dev->bar_mapped_size = 0;
1808                 return -ENOMEM;
1809         }
1810         dev->bar_mapped_size = size;
1811         dev->dbs = dev->bar + NVME_REG_DBS;
1812
1813         return 0;
1814 }
1815
1816 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1817 {
1818         int result;
1819         u32 aqa;
1820         struct nvme_queue *nvmeq;
1821
1822         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1823         if (result < 0)
1824                 return result;
1825
1826         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1827                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1828
1829         if (dev->subsystem &&
1830             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1831                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1832
1833         result = nvme_disable_ctrl(&dev->ctrl);
1834         if (result < 0)
1835                 return result;
1836
1837         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1838         if (result)
1839                 return result;
1840
1841         dev->ctrl.numa_node = dev_to_node(dev->dev);
1842
1843         nvmeq = &dev->queues[0];
1844         aqa = nvmeq->q_depth - 1;
1845         aqa |= aqa << 16;
1846
1847         writel(aqa, dev->bar + NVME_REG_AQA);
1848         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1849         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1850
1851         result = nvme_enable_ctrl(&dev->ctrl);
1852         if (result)
1853                 return result;
1854
1855         nvmeq->cq_vector = 0;
1856         nvme_init_queue(nvmeq, 0);
1857         result = queue_request_irq(nvmeq);
1858         if (result) {
1859                 dev->online_queues--;
1860                 return result;
1861         }
1862
1863         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1864         return result;
1865 }
1866
1867 static int nvme_create_io_queues(struct nvme_dev *dev)
1868 {
1869         unsigned i, max, rw_queues;
1870         int ret = 0;
1871
1872         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1873                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1874                         ret = -ENOMEM;
1875                         break;
1876                 }
1877         }
1878
1879         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1880         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1881                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1882                                 dev->io_queues[HCTX_TYPE_READ];
1883         } else {
1884                 rw_queues = max;
1885         }
1886
1887         for (i = dev->online_queues; i <= max; i++) {
1888                 bool polled = i > rw_queues;
1889
1890                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1891                 if (ret)
1892                         break;
1893         }
1894
1895         /*
1896          * Ignore failing Create SQ/CQ commands, we can continue with less
1897          * than the desired amount of queues, and even a controller without
1898          * I/O queues can still be used to issue admin commands.  This might
1899          * be useful to upgrade a buggy firmware for example.
1900          */
1901         return ret >= 0 ? 0 : ret;
1902 }
1903
1904 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1905 {
1906         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1907
1908         return 1ULL << (12 + 4 * szu);
1909 }
1910
1911 static u32 nvme_cmb_size(struct nvme_dev *dev)
1912 {
1913         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1914 }
1915
1916 static void nvme_map_cmb(struct nvme_dev *dev)
1917 {
1918         u64 size, offset;
1919         resource_size_t bar_size;
1920         struct pci_dev *pdev = to_pci_dev(dev->dev);
1921         int bar;
1922
1923         if (dev->cmb_size)
1924                 return;
1925
1926         if (NVME_CAP_CMBS(dev->ctrl.cap))
1927                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1928
1929         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1930         if (!dev->cmbsz)
1931                 return;
1932         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1933
1934         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1935         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1936         bar = NVME_CMB_BIR(dev->cmbloc);
1937         bar_size = pci_resource_len(pdev, bar);
1938
1939         if (offset > bar_size)
1940                 return;
1941
1942         /*
1943          * Tell the controller about the host side address mapping the CMB,
1944          * and enable CMB decoding for the NVMe 1.4+ scheme:
1945          */
1946         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1947                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1948                              (pci_bus_address(pdev, bar) + offset),
1949                              dev->bar + NVME_REG_CMBMSC);
1950         }
1951
1952         /*
1953          * Controllers may support a CMB size larger than their BAR,
1954          * for example, due to being behind a bridge. Reduce the CMB to
1955          * the reported size of the BAR
1956          */
1957         if (size > bar_size - offset)
1958                 size = bar_size - offset;
1959
1960         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1961                 dev_warn(dev->ctrl.device,
1962                          "failed to register the CMB\n");
1963                 return;
1964         }
1965
1966         dev->cmb_size = size;
1967         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1968
1969         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1970                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1971                 pci_p2pmem_publish(pdev, true);
1972 }
1973
1974 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1975 {
1976         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1977         u64 dma_addr = dev->host_mem_descs_dma;
1978         struct nvme_command c = { };
1979         int ret;
1980
1981         c.features.opcode       = nvme_admin_set_features;
1982         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1983         c.features.dword11      = cpu_to_le32(bits);
1984         c.features.dword12      = cpu_to_le32(host_mem_size);
1985         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1986         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1987         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1988
1989         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1990         if (ret) {
1991                 dev_warn(dev->ctrl.device,
1992                          "failed to set host mem (err %d, flags %#x).\n",
1993                          ret, bits);
1994         } else
1995                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1996
1997         return ret;
1998 }
1999
2000 static void nvme_free_host_mem(struct nvme_dev *dev)
2001 {
2002         int i;
2003
2004         for (i = 0; i < dev->nr_host_mem_descs; i++) {
2005                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2006                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2007
2008                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2009                                le64_to_cpu(desc->addr),
2010                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2011         }
2012
2013         kfree(dev->host_mem_desc_bufs);
2014         dev->host_mem_desc_bufs = NULL;
2015         dma_free_coherent(dev->dev,
2016                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2017                         dev->host_mem_descs, dev->host_mem_descs_dma);
2018         dev->host_mem_descs = NULL;
2019         dev->nr_host_mem_descs = 0;
2020 }
2021
2022 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2023                 u32 chunk_size)
2024 {
2025         struct nvme_host_mem_buf_desc *descs;
2026         u32 max_entries, len;
2027         dma_addr_t descs_dma;
2028         int i = 0;
2029         void **bufs;
2030         u64 size, tmp;
2031
2032         tmp = (preferred + chunk_size - 1);
2033         do_div(tmp, chunk_size);
2034         max_entries = tmp;
2035
2036         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2037                 max_entries = dev->ctrl.hmmaxd;
2038
2039         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2040                                    &descs_dma, GFP_KERNEL);
2041         if (!descs)
2042                 goto out;
2043
2044         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2045         if (!bufs)
2046                 goto out_free_descs;
2047
2048         for (size = 0; size < preferred && i < max_entries; size += len) {
2049                 dma_addr_t dma_addr;
2050
2051                 len = min_t(u64, chunk_size, preferred - size);
2052                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2053                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2054                 if (!bufs[i])
2055                         break;
2056
2057                 descs[i].addr = cpu_to_le64(dma_addr);
2058                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2059                 i++;
2060         }
2061
2062         if (!size)
2063                 goto out_free_bufs;
2064
2065         dev->nr_host_mem_descs = i;
2066         dev->host_mem_size = size;
2067         dev->host_mem_descs = descs;
2068         dev->host_mem_descs_dma = descs_dma;
2069         dev->host_mem_desc_bufs = bufs;
2070         return 0;
2071
2072 out_free_bufs:
2073         while (--i >= 0) {
2074                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2075
2076                 dma_free_attrs(dev->dev, size, bufs[i],
2077                                le64_to_cpu(descs[i].addr),
2078                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2079         }
2080
2081         kfree(bufs);
2082 out_free_descs:
2083         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2084                         descs_dma);
2085 out:
2086         dev->host_mem_descs = NULL;
2087         return -ENOMEM;
2088 }
2089
2090 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2091 {
2092         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2093         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2094         u64 chunk_size;
2095
2096         /* start big and work our way down */
2097         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2098                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2099                         if (!min || dev->host_mem_size >= min)
2100                                 return 0;
2101                         nvme_free_host_mem(dev);
2102                 }
2103         }
2104
2105         return -ENOMEM;
2106 }
2107
2108 static int nvme_setup_host_mem(struct nvme_dev *dev)
2109 {
2110         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2111         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2112         u64 min = (u64)dev->ctrl.hmmin * 4096;
2113         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2114         int ret;
2115
2116         preferred = min(preferred, max);
2117         if (min > max) {
2118                 dev_warn(dev->ctrl.device,
2119                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2120                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2121                 nvme_free_host_mem(dev);
2122                 return 0;
2123         }
2124
2125         /*
2126          * If we already have a buffer allocated check if we can reuse it.
2127          */
2128         if (dev->host_mem_descs) {
2129                 if (dev->host_mem_size >= min)
2130                         enable_bits |= NVME_HOST_MEM_RETURN;
2131                 else
2132                         nvme_free_host_mem(dev);
2133         }
2134
2135         if (!dev->host_mem_descs) {
2136                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2137                         dev_warn(dev->ctrl.device,
2138                                 "failed to allocate host memory buffer.\n");
2139                         return 0; /* controller must work without HMB */
2140                 }
2141
2142                 dev_info(dev->ctrl.device,
2143                         "allocated %lld MiB host memory buffer.\n",
2144                         dev->host_mem_size >> ilog2(SZ_1M));
2145         }
2146
2147         ret = nvme_set_host_mem(dev, enable_bits);
2148         if (ret)
2149                 nvme_free_host_mem(dev);
2150         return ret;
2151 }
2152
2153 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2154                 char *buf)
2155 {
2156         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2157
2158         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2159                        ndev->cmbloc, ndev->cmbsz);
2160 }
2161 static DEVICE_ATTR_RO(cmb);
2162
2163 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2164                 char *buf)
2165 {
2166         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2167
2168         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2169 }
2170 static DEVICE_ATTR_RO(cmbloc);
2171
2172 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2173                 char *buf)
2174 {
2175         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2176
2177         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2178 }
2179 static DEVICE_ATTR_RO(cmbsz);
2180
2181 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2182                         char *buf)
2183 {
2184         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2185
2186         return sysfs_emit(buf, "%d\n", ndev->hmb);
2187 }
2188
2189 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2190                          const char *buf, size_t count)
2191 {
2192         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2193         bool new;
2194         int ret;
2195
2196         if (strtobool(buf, &new) < 0)
2197                 return -EINVAL;
2198
2199         if (new == ndev->hmb)
2200                 return count;
2201
2202         if (new) {
2203                 ret = nvme_setup_host_mem(ndev);
2204         } else {
2205                 ret = nvme_set_host_mem(ndev, 0);
2206                 if (!ret)
2207                         nvme_free_host_mem(ndev);
2208         }
2209
2210         if (ret < 0)
2211                 return ret;
2212
2213         return count;
2214 }
2215 static DEVICE_ATTR_RW(hmb);
2216
2217 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2218                 struct attribute *a, int n)
2219 {
2220         struct nvme_ctrl *ctrl =
2221                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2222         struct nvme_dev *dev = to_nvme_dev(ctrl);
2223
2224         if (a == &dev_attr_cmb.attr ||
2225             a == &dev_attr_cmbloc.attr ||
2226             a == &dev_attr_cmbsz.attr) {
2227                 if (!dev->cmbsz)
2228                         return 0;
2229         }
2230         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2231                 return 0;
2232
2233         return a->mode;
2234 }
2235
2236 static struct attribute *nvme_pci_attrs[] = {
2237         &dev_attr_cmb.attr,
2238         &dev_attr_cmbloc.attr,
2239         &dev_attr_cmbsz.attr,
2240         &dev_attr_hmb.attr,
2241         NULL,
2242 };
2243
2244 static const struct attribute_group nvme_pci_attr_group = {
2245         .attrs          = nvme_pci_attrs,
2246         .is_visible     = nvme_pci_attrs_are_visible,
2247 };
2248
2249 /*
2250  * nirqs is the number of interrupts available for write and read
2251  * queues. The core already reserved an interrupt for the admin queue.
2252  */
2253 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2254 {
2255         struct nvme_dev *dev = affd->priv;
2256         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2257
2258         /*
2259          * If there is no interrupt available for queues, ensure that
2260          * the default queue is set to 1. The affinity set size is
2261          * also set to one, but the irq core ignores it for this case.
2262          *
2263          * If only one interrupt is available or 'write_queue' == 0, combine
2264          * write and read queues.
2265          *
2266          * If 'write_queues' > 0, ensure it leaves room for at least one read
2267          * queue.
2268          */
2269         if (!nrirqs) {
2270                 nrirqs = 1;
2271                 nr_read_queues = 0;
2272         } else if (nrirqs == 1 || !nr_write_queues) {
2273                 nr_read_queues = 0;
2274         } else if (nr_write_queues >= nrirqs) {
2275                 nr_read_queues = 1;
2276         } else {
2277                 nr_read_queues = nrirqs - nr_write_queues;
2278         }
2279
2280         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2281         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2282         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2283         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2284         affd->nr_sets = nr_read_queues ? 2 : 1;
2285 }
2286
2287 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2288 {
2289         struct pci_dev *pdev = to_pci_dev(dev->dev);
2290         struct irq_affinity affd = {
2291                 .pre_vectors    = 1,
2292                 .calc_sets      = nvme_calc_irq_sets,
2293                 .priv           = dev,
2294         };
2295         unsigned int irq_queues, poll_queues;
2296
2297         /*
2298          * Poll queues don't need interrupts, but we need at least one I/O queue
2299          * left over for non-polled I/O.
2300          */
2301         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2302         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2303
2304         /*
2305          * Initialize for the single interrupt case, will be updated in
2306          * nvme_calc_irq_sets().
2307          */
2308         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2309         dev->io_queues[HCTX_TYPE_READ] = 0;
2310
2311         /*
2312          * We need interrupts for the admin queue and each non-polled I/O queue,
2313          * but some Apple controllers require all queues to use the first
2314          * vector.
2315          */
2316         irq_queues = 1;
2317         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2318                 irq_queues += (nr_io_queues - poll_queues);
2319         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2320                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2321 }
2322
2323 static void nvme_disable_io_queues(struct nvme_dev *dev)
2324 {
2325         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2326                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2327 }
2328
2329 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2330 {
2331         /*
2332          * If tags are shared with admin queue (Apple bug), then
2333          * make sure we only use one IO queue.
2334          */
2335         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2336                 return 1;
2337         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2338 }
2339
2340 static int nvme_setup_io_queues(struct nvme_dev *dev)
2341 {
2342         struct nvme_queue *adminq = &dev->queues[0];
2343         struct pci_dev *pdev = to_pci_dev(dev->dev);
2344         unsigned int nr_io_queues;
2345         unsigned long size;
2346         int result;
2347
2348         /*
2349          * Sample the module parameters once at reset time so that we have
2350          * stable values to work with.
2351          */
2352         dev->nr_write_queues = write_queues;
2353         dev->nr_poll_queues = poll_queues;
2354
2355         nr_io_queues = dev->nr_allocated_queues - 1;
2356         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2357         if (result < 0)
2358                 return result;
2359
2360         if (nr_io_queues == 0)
2361                 return 0;
2362
2363         /*
2364          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2365          * from set to unset. If there is a window to it is truely freed,
2366          * pci_free_irq_vectors() jumping into this window will crash.
2367          * And take lock to avoid racing with pci_free_irq_vectors() in
2368          * nvme_dev_disable() path.
2369          */
2370         result = nvme_setup_io_queues_trylock(dev);
2371         if (result)
2372                 return result;
2373         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2374                 pci_free_irq(pdev, 0, adminq);
2375
2376         if (dev->cmb_use_sqes) {
2377                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2378                                 sizeof(struct nvme_command));
2379                 if (result > 0)
2380                         dev->q_depth = result;
2381                 else
2382                         dev->cmb_use_sqes = false;
2383         }
2384
2385         do {
2386                 size = db_bar_size(dev, nr_io_queues);
2387                 result = nvme_remap_bar(dev, size);
2388                 if (!result)
2389                         break;
2390                 if (!--nr_io_queues) {
2391                         result = -ENOMEM;
2392                         goto out_unlock;
2393                 }
2394         } while (1);
2395         adminq->q_db = dev->dbs;
2396
2397  retry:
2398         /* Deregister the admin queue's interrupt */
2399         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2400                 pci_free_irq(pdev, 0, adminq);
2401
2402         /*
2403          * If we enable msix early due to not intx, disable it again before
2404          * setting up the full range we need.
2405          */
2406         pci_free_irq_vectors(pdev);
2407
2408         result = nvme_setup_irqs(dev, nr_io_queues);
2409         if (result <= 0) {
2410                 result = -EIO;
2411                 goto out_unlock;
2412         }
2413
2414         dev->num_vecs = result;
2415         result = max(result - 1, 1);
2416         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2417
2418         /*
2419          * Should investigate if there's a performance win from allocating
2420          * more queues than interrupt vectors; it might allow the submission
2421          * path to scale better, even if the receive path is limited by the
2422          * number of interrupts.
2423          */
2424         result = queue_request_irq(adminq);
2425         if (result)
2426                 goto out_unlock;
2427         set_bit(NVMEQ_ENABLED, &adminq->flags);
2428         mutex_unlock(&dev->shutdown_lock);
2429
2430         result = nvme_create_io_queues(dev);
2431         if (result || dev->online_queues < 2)
2432                 return result;
2433
2434         if (dev->online_queues - 1 < dev->max_qid) {
2435                 nr_io_queues = dev->online_queues - 1;
2436                 nvme_disable_io_queues(dev);
2437                 result = nvme_setup_io_queues_trylock(dev);
2438                 if (result)
2439                         return result;
2440                 nvme_suspend_io_queues(dev);
2441                 goto retry;
2442         }
2443         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2444                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2445                                         dev->io_queues[HCTX_TYPE_READ],
2446                                         dev->io_queues[HCTX_TYPE_POLL]);
2447         return 0;
2448 out_unlock:
2449         mutex_unlock(&dev->shutdown_lock);
2450         return result;
2451 }
2452
2453 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2454 {
2455         struct nvme_queue *nvmeq = req->end_io_data;
2456
2457         blk_mq_free_request(req);
2458         complete(&nvmeq->delete_done);
2459 }
2460
2461 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2462 {
2463         struct nvme_queue *nvmeq = req->end_io_data;
2464
2465         if (error)
2466                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2467
2468         nvme_del_queue_end(req, error);
2469 }
2470
2471 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2472 {
2473         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2474         struct request *req;
2475         struct nvme_command cmd = { };
2476
2477         cmd.delete_queue.opcode = opcode;
2478         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2479
2480         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2481         if (IS_ERR(req))
2482                 return PTR_ERR(req);
2483         nvme_init_request(req, &cmd);
2484
2485         if (opcode == nvme_admin_delete_cq)
2486                 req->end_io = nvme_del_cq_end;
2487         else
2488                 req->end_io = nvme_del_queue_end;
2489         req->end_io_data = nvmeq;
2490
2491         init_completion(&nvmeq->delete_done);
2492         req->rq_flags |= RQF_QUIET;
2493         blk_execute_rq_nowait(req, false);
2494         return 0;
2495 }
2496
2497 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2498 {
2499         int nr_queues = dev->online_queues - 1, sent = 0;
2500         unsigned long timeout;
2501
2502  retry:
2503         timeout = NVME_ADMIN_TIMEOUT;
2504         while (nr_queues > 0) {
2505                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2506                         break;
2507                 nr_queues--;
2508                 sent++;
2509         }
2510         while (sent) {
2511                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2512
2513                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2514                                 timeout);
2515                 if (timeout == 0)
2516                         return false;
2517
2518                 sent--;
2519                 if (nr_queues)
2520                         goto retry;
2521         }
2522         return true;
2523 }
2524
2525 static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
2526 {
2527         struct blk_mq_tag_set * set = &dev->tagset;
2528         int ret;
2529
2530         set->ops = &nvme_mq_ops;
2531         set->nr_hw_queues = dev->online_queues - 1;
2532         set->nr_maps = 2; /* default + read */
2533         if (dev->io_queues[HCTX_TYPE_POLL])
2534                 set->nr_maps++;
2535         set->timeout = NVME_IO_TIMEOUT;
2536         set->numa_node = dev->ctrl.numa_node;
2537         set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2538         set->cmd_size = sizeof(struct nvme_iod);
2539         set->flags = BLK_MQ_F_SHOULD_MERGE;
2540         set->driver_data = dev;
2541
2542         /*
2543          * Some Apple controllers requires tags to be unique
2544          * across admin and IO queue, so reserve the first 32
2545          * tags of the IO queue.
2546          */
2547         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2548                 set->reserved_tags = NVME_AQ_DEPTH;
2549
2550         ret = blk_mq_alloc_tag_set(set);
2551         if (ret) {
2552                 dev_warn(dev->ctrl.device,
2553                         "IO queues tagset allocation failed %d\n", ret);
2554                 return;
2555         }
2556         dev->ctrl.tagset = set;
2557 }
2558
2559 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2560 {
2561         blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2562         /* free previously allocated queues that are no longer usable */
2563         nvme_free_queues(dev, dev->online_queues);
2564 }
2565
2566 static int nvme_pci_enable(struct nvme_dev *dev)
2567 {
2568         int result = -ENOMEM;
2569         struct pci_dev *pdev = to_pci_dev(dev->dev);
2570         int dma_address_bits = 64;
2571
2572         if (pci_enable_device_mem(pdev))
2573                 return result;
2574
2575         pci_set_master(pdev);
2576
2577         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2578                 dma_address_bits = 48;
2579         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2580                 goto disable;
2581
2582         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2583                 result = -ENODEV;
2584                 goto disable;
2585         }
2586
2587         /*
2588          * Some devices and/or platforms don't advertise or work with INTx
2589          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2590          * adjust this later.
2591          */
2592         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2593         if (result < 0)
2594                 return result;
2595
2596         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2597
2598         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2599                                 io_queue_depth);
2600         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2601         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2602         dev->dbs = dev->bar + 4096;
2603
2604         /*
2605          * Some Apple controllers require a non-standard SQE size.
2606          * Interestingly they also seem to ignore the CC:IOSQES register
2607          * so we don't bother updating it here.
2608          */
2609         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2610                 dev->io_sqes = 7;
2611         else
2612                 dev->io_sqes = NVME_NVM_IOSQES;
2613
2614         /*
2615          * Temporary fix for the Apple controller found in the MacBook8,1 and
2616          * some MacBook7,1 to avoid controller resets and data loss.
2617          */
2618         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2619                 dev->q_depth = 2;
2620                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2621                         "set queue depth=%u to work around controller resets\n",
2622                         dev->q_depth);
2623         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2624                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2625                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2626                 dev->q_depth = 64;
2627                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2628                         "set queue depth=%u\n", dev->q_depth);
2629         }
2630
2631         /*
2632          * Controllers with the shared tags quirk need the IO queue to be
2633          * big enough so that we get 32 tags for the admin queue
2634          */
2635         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2636             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2637                 dev->q_depth = NVME_AQ_DEPTH + 2;
2638                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2639                          dev->q_depth);
2640         }
2641
2642
2643         nvme_map_cmb(dev);
2644
2645         pci_enable_pcie_error_reporting(pdev);
2646         pci_save_state(pdev);
2647         return 0;
2648
2649  disable:
2650         pci_disable_device(pdev);
2651         return result;
2652 }
2653
2654 static void nvme_dev_unmap(struct nvme_dev *dev)
2655 {
2656         if (dev->bar)
2657                 iounmap(dev->bar);
2658         pci_release_mem_regions(to_pci_dev(dev->dev));
2659 }
2660
2661 static void nvme_pci_disable(struct nvme_dev *dev)
2662 {
2663         struct pci_dev *pdev = to_pci_dev(dev->dev);
2664
2665         pci_free_irq_vectors(pdev);
2666
2667         if (pci_is_enabled(pdev)) {
2668                 pci_disable_pcie_error_reporting(pdev);
2669                 pci_disable_device(pdev);
2670         }
2671 }
2672
2673 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2674 {
2675         bool dead = true, freeze = false;
2676         struct pci_dev *pdev = to_pci_dev(dev->dev);
2677
2678         mutex_lock(&dev->shutdown_lock);
2679         if (pci_is_enabled(pdev)) {
2680                 u32 csts;
2681
2682                 if (pci_device_is_present(pdev))
2683                         csts = readl(dev->bar + NVME_REG_CSTS);
2684                 else
2685                         csts = ~0;
2686
2687                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2688                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2689                         freeze = true;
2690                         nvme_start_freeze(&dev->ctrl);
2691                 }
2692                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2693                         pdev->error_state  != pci_channel_io_normal);
2694         }
2695
2696         /*
2697          * Give the controller a chance to complete all entered requests if
2698          * doing a safe shutdown.
2699          */
2700         if (!dead && shutdown && freeze)
2701                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2702
2703         nvme_stop_queues(&dev->ctrl);
2704
2705         if (!dead && dev->ctrl.queue_count > 0) {
2706                 nvme_disable_io_queues(dev);
2707                 nvme_disable_admin_queue(dev, shutdown);
2708         }
2709         nvme_suspend_io_queues(dev);
2710         nvme_suspend_queue(&dev->queues[0]);
2711         nvme_pci_disable(dev);
2712         nvme_reap_pending_cqes(dev);
2713
2714         nvme_cancel_tagset(&dev->ctrl);
2715         nvme_cancel_admin_tagset(&dev->ctrl);
2716
2717         /*
2718          * The driver will not be starting up queues again if shutting down so
2719          * must flush all entered requests to their failed completion to avoid
2720          * deadlocking blk-mq hot-cpu notifier.
2721          */
2722         if (shutdown) {
2723                 nvme_start_queues(&dev->ctrl);
2724                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2725                         nvme_start_admin_queue(&dev->ctrl);
2726         }
2727         mutex_unlock(&dev->shutdown_lock);
2728 }
2729
2730 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2731 {
2732         if (!nvme_wait_reset(&dev->ctrl))
2733                 return -EBUSY;
2734         nvme_dev_disable(dev, shutdown);
2735         return 0;
2736 }
2737
2738 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2739 {
2740         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2741                                                 NVME_CTRL_PAGE_SIZE,
2742                                                 NVME_CTRL_PAGE_SIZE, 0);
2743         if (!dev->prp_page_pool)
2744                 return -ENOMEM;
2745
2746         /* Optimisation for I/Os between 4k and 128k */
2747         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2748                                                 256, 256, 0);
2749         if (!dev->prp_small_pool) {
2750                 dma_pool_destroy(dev->prp_page_pool);
2751                 return -ENOMEM;
2752         }
2753         return 0;
2754 }
2755
2756 static void nvme_release_prp_pools(struct nvme_dev *dev)
2757 {
2758         dma_pool_destroy(dev->prp_page_pool);
2759         dma_pool_destroy(dev->prp_small_pool);
2760 }
2761
2762 static void nvme_free_tagset(struct nvme_dev *dev)
2763 {
2764         if (dev->tagset.tags)
2765                 blk_mq_free_tag_set(&dev->tagset);
2766         dev->ctrl.tagset = NULL;
2767 }
2768
2769 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2770 {
2771         struct nvme_dev *dev = to_nvme_dev(ctrl);
2772
2773         nvme_dbbuf_dma_free(dev);
2774         nvme_free_tagset(dev);
2775         if (dev->ctrl.admin_q)
2776                 blk_put_queue(dev->ctrl.admin_q);
2777         free_opal_dev(dev->ctrl.opal_dev);
2778         mempool_destroy(dev->iod_mempool);
2779         put_device(dev->dev);
2780         kfree(dev->queues);
2781         kfree(dev);
2782 }
2783
2784 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2785 {
2786         /*
2787          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2788          * may be holding this pci_dev's device lock.
2789          */
2790         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2791         nvme_get_ctrl(&dev->ctrl);
2792         nvme_dev_disable(dev, false);
2793         nvme_kill_queues(&dev->ctrl);
2794         if (!queue_work(nvme_wq, &dev->remove_work))
2795                 nvme_put_ctrl(&dev->ctrl);
2796 }
2797
2798 static void nvme_reset_work(struct work_struct *work)
2799 {
2800         struct nvme_dev *dev =
2801                 container_of(work, struct nvme_dev, ctrl.reset_work);
2802         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2803         int result;
2804
2805         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2806                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2807                          dev->ctrl.state);
2808                 result = -ENODEV;
2809                 goto out;
2810         }
2811
2812         /*
2813          * If we're called to reset a live controller first shut it down before
2814          * moving on.
2815          */
2816         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2817                 nvme_dev_disable(dev, false);
2818         nvme_sync_queues(&dev->ctrl);
2819
2820         mutex_lock(&dev->shutdown_lock);
2821         result = nvme_pci_enable(dev);
2822         if (result)
2823                 goto out_unlock;
2824
2825         result = nvme_pci_configure_admin_queue(dev);
2826         if (result)
2827                 goto out_unlock;
2828
2829         if (!dev->ctrl.admin_q) {
2830                 result = nvme_pci_alloc_admin_tag_set(dev);
2831                 if (result)
2832                         goto out_unlock;
2833         } else {
2834                 nvme_start_admin_queue(&dev->ctrl);
2835         }
2836
2837         /*
2838          * Limit the max command size to prevent iod->sg allocations going
2839          * over a single page.
2840          */
2841         dev->ctrl.max_hw_sectors = min_t(u32,
2842                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2843         dev->ctrl.max_segments = NVME_MAX_SEGS;
2844
2845         /*
2846          * Don't limit the IOMMU merged segment size.
2847          */
2848         dma_set_max_seg_size(dev->dev, 0xffffffff);
2849         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2850
2851         mutex_unlock(&dev->shutdown_lock);
2852
2853         /*
2854          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2855          * initializing procedure here.
2856          */
2857         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2858                 dev_warn(dev->ctrl.device,
2859                         "failed to mark controller CONNECTING\n");
2860                 result = -EBUSY;
2861                 goto out;
2862         }
2863
2864         /*
2865          * We do not support an SGL for metadata (yet), so we are limited to a
2866          * single integrity segment for the separate metadata pointer.
2867          */
2868         dev->ctrl.max_integrity_segments = 1;
2869
2870         result = nvme_init_ctrl_finish(&dev->ctrl);
2871         if (result)
2872                 goto out;
2873
2874         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2875                 if (!dev->ctrl.opal_dev)
2876                         dev->ctrl.opal_dev =
2877                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2878                 else if (was_suspend)
2879                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2880         } else {
2881                 free_opal_dev(dev->ctrl.opal_dev);
2882                 dev->ctrl.opal_dev = NULL;
2883         }
2884
2885         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2886                 result = nvme_dbbuf_dma_alloc(dev);
2887                 if (result)
2888                         dev_warn(dev->dev,
2889                                  "unable to allocate dma for dbbuf\n");
2890         }
2891
2892         if (dev->ctrl.hmpre) {
2893                 result = nvme_setup_host_mem(dev);
2894                 if (result < 0)
2895                         goto out;
2896         }
2897
2898         result = nvme_setup_io_queues(dev);
2899         if (result)
2900                 goto out;
2901
2902         /*
2903          * Keep the controller around but remove all namespaces if we don't have
2904          * any working I/O queue.
2905          */
2906         if (dev->online_queues < 2) {
2907                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2908                 nvme_kill_queues(&dev->ctrl);
2909                 nvme_remove_namespaces(&dev->ctrl);
2910                 nvme_free_tagset(dev);
2911         } else {
2912                 nvme_start_queues(&dev->ctrl);
2913                 nvme_wait_freeze(&dev->ctrl);
2914                 if (!dev->ctrl.tagset)
2915                         nvme_pci_alloc_tag_set(dev);
2916                 else
2917                         nvme_pci_update_nr_queues(dev);
2918                 nvme_dbbuf_set(dev);
2919                 nvme_unfreeze(&dev->ctrl);
2920         }
2921
2922         /*
2923          * If only admin queue live, keep it to do further investigation or
2924          * recovery.
2925          */
2926         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2927                 dev_warn(dev->ctrl.device,
2928                         "failed to mark controller live state\n");
2929                 result = -ENODEV;
2930                 goto out;
2931         }
2932
2933         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2934                         &nvme_pci_attr_group))
2935                 dev->attrs_added = true;
2936
2937         nvme_start_ctrl(&dev->ctrl);
2938         return;
2939
2940  out_unlock:
2941         mutex_unlock(&dev->shutdown_lock);
2942  out:
2943         if (result)
2944                 dev_warn(dev->ctrl.device,
2945                          "Removing after probe failure status: %d\n", result);
2946         nvme_remove_dead_ctrl(dev);
2947 }
2948
2949 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2950 {
2951         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2952         struct pci_dev *pdev = to_pci_dev(dev->dev);
2953
2954         if (pci_get_drvdata(pdev))
2955                 device_release_driver(&pdev->dev);
2956         nvme_put_ctrl(&dev->ctrl);
2957 }
2958
2959 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2960 {
2961         *val = readl(to_nvme_dev(ctrl)->bar + off);
2962         return 0;
2963 }
2964
2965 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2966 {
2967         writel(val, to_nvme_dev(ctrl)->bar + off);
2968         return 0;
2969 }
2970
2971 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2972 {
2973         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2974         return 0;
2975 }
2976
2977 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2978 {
2979         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2980
2981         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2982 }
2983
2984 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2985 {
2986         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2987         struct nvme_subsystem *subsys = ctrl->subsys;
2988
2989         dev_err(ctrl->device,
2990                 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2991                 pdev->vendor, pdev->device,
2992                 nvme_strlen(subsys->model, sizeof(subsys->model)),
2993                 subsys->model, nvme_strlen(subsys->firmware_rev,
2994                                            sizeof(subsys->firmware_rev)),
2995                 subsys->firmware_rev);
2996 }
2997
2998 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2999 {
3000         struct nvme_dev *dev = to_nvme_dev(ctrl);
3001
3002         return dma_pci_p2pdma_supported(dev->dev);
3003 }
3004
3005 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
3006         .name                   = "pcie",
3007         .module                 = THIS_MODULE,
3008         .flags                  = NVME_F_METADATA_SUPPORTED,
3009         .reg_read32             = nvme_pci_reg_read32,
3010         .reg_write32            = nvme_pci_reg_write32,
3011         .reg_read64             = nvme_pci_reg_read64,
3012         .free_ctrl              = nvme_pci_free_ctrl,
3013         .submit_async_event     = nvme_pci_submit_async_event,
3014         .get_address            = nvme_pci_get_address,
3015         .print_device_info      = nvme_pci_print_device_info,
3016         .supports_pci_p2pdma    = nvme_pci_supports_pci_p2pdma,
3017 };
3018
3019 static int nvme_dev_map(struct nvme_dev *dev)
3020 {
3021         struct pci_dev *pdev = to_pci_dev(dev->dev);
3022
3023         if (pci_request_mem_regions(pdev, "nvme"))
3024                 return -ENODEV;
3025
3026         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
3027                 goto release;
3028
3029         return 0;
3030   release:
3031         pci_release_mem_regions(pdev);
3032         return -ENODEV;
3033 }
3034
3035 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3036 {
3037         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3038                 /*
3039                  * Several Samsung devices seem to drop off the PCIe bus
3040                  * randomly when APST is on and uses the deepest sleep state.
3041                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3042                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3043                  * 950 PRO 256GB", but it seems to be restricted to two Dell
3044                  * laptops.
3045                  */
3046                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3047                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3048                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3049                         return NVME_QUIRK_NO_DEEPEST_PS;
3050         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3051                 /*
3052                  * Samsung SSD 960 EVO drops off the PCIe bus after system
3053                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3054                  * within few minutes after bootup on a Coffee Lake board -
3055                  * ASUS PRIME Z370-A
3056                  */
3057                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3058                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3059                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3060                         return NVME_QUIRK_NO_APST;
3061         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3062                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3063                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3064                 /*
3065                  * Forcing to use host managed nvme power settings for
3066                  * lowest idle power with quick resume latency on
3067                  * Samsung and Toshiba SSDs based on suspend behavior
3068                  * on Coffee Lake board for LENOVO C640
3069                  */
3070                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3071                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3072                         return NVME_QUIRK_SIMPLE_SUSPEND;
3073         }
3074
3075         return 0;
3076 }
3077
3078 static void nvme_async_probe(void *data, async_cookie_t cookie)
3079 {
3080         struct nvme_dev *dev = data;
3081
3082         flush_work(&dev->ctrl.reset_work);
3083         flush_work(&dev->ctrl.scan_work);
3084         nvme_put_ctrl(&dev->ctrl);
3085 }
3086
3087 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3088 {
3089         int node, result = -ENOMEM;
3090         struct nvme_dev *dev;
3091         unsigned long quirks = id->driver_data;
3092         size_t alloc_size;
3093
3094         node = dev_to_node(&pdev->dev);
3095         if (node == NUMA_NO_NODE)
3096                 set_dev_node(&pdev->dev, first_memory_node);
3097
3098         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3099         if (!dev)
3100                 return -ENOMEM;
3101
3102         dev->nr_write_queues = write_queues;
3103         dev->nr_poll_queues = poll_queues;
3104         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3105         dev->queues = kcalloc_node(dev->nr_allocated_queues,
3106                         sizeof(struct nvme_queue), GFP_KERNEL, node);
3107         if (!dev->queues)
3108                 goto free;
3109
3110         dev->dev = get_device(&pdev->dev);
3111         pci_set_drvdata(pdev, dev);
3112
3113         result = nvme_dev_map(dev);
3114         if (result)
3115                 goto put_pci;
3116
3117         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3118         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3119         mutex_init(&dev->shutdown_lock);
3120
3121         result = nvme_setup_prp_pools(dev);
3122         if (result)
3123                 goto unmap;
3124
3125         quirks |= check_vendor_combination_bug(pdev);
3126
3127         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3128                 /*
3129                  * Some systems use a bios work around to ask for D3 on
3130                  * platforms that support kernel managed suspend.
3131                  */
3132                 dev_info(&pdev->dev,
3133                          "platform quirk: setting simple suspend\n");
3134                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3135         }
3136
3137         /*
3138          * Double check that our mempool alloc size will cover the biggest
3139          * command we support.
3140          */
3141         alloc_size = nvme_pci_iod_alloc_size();
3142         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3143
3144         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3145                                                 mempool_kfree,
3146                                                 (void *) alloc_size,
3147                                                 GFP_KERNEL, node);
3148         if (!dev->iod_mempool) {
3149                 result = -ENOMEM;
3150                 goto release_pools;
3151         }
3152
3153         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3154                         quirks);
3155         if (result)
3156                 goto release_mempool;
3157
3158         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3159
3160         nvme_reset_ctrl(&dev->ctrl);
3161         async_schedule(nvme_async_probe, dev);
3162
3163         return 0;
3164
3165  release_mempool:
3166         mempool_destroy(dev->iod_mempool);
3167  release_pools:
3168         nvme_release_prp_pools(dev);
3169  unmap:
3170         nvme_dev_unmap(dev);
3171  put_pci:
3172         put_device(dev->dev);
3173  free:
3174         kfree(dev->queues);
3175         kfree(dev);
3176         return result;
3177 }
3178
3179 static void nvme_reset_prepare(struct pci_dev *pdev)
3180 {
3181         struct nvme_dev *dev = pci_get_drvdata(pdev);
3182
3183         /*
3184          * We don't need to check the return value from waiting for the reset
3185          * state as pci_dev device lock is held, making it impossible to race
3186          * with ->remove().
3187          */
3188         nvme_disable_prepare_reset(dev, false);
3189         nvme_sync_queues(&dev->ctrl);
3190 }
3191
3192 static void nvme_reset_done(struct pci_dev *pdev)
3193 {
3194         struct nvme_dev *dev = pci_get_drvdata(pdev);
3195
3196         if (!nvme_try_sched_reset(&dev->ctrl))
3197                 flush_work(&dev->ctrl.reset_work);
3198 }
3199
3200 static void nvme_shutdown(struct pci_dev *pdev)
3201 {
3202         struct nvme_dev *dev = pci_get_drvdata(pdev);
3203
3204         nvme_disable_prepare_reset(dev, true);
3205 }
3206
3207 static void nvme_remove_attrs(struct nvme_dev *dev)
3208 {
3209         if (dev->attrs_added)
3210                 sysfs_remove_group(&dev->ctrl.device->kobj,
3211                                    &nvme_pci_attr_group);
3212 }
3213
3214 /*
3215  * The driver's remove may be called on a device in a partially initialized
3216  * state. This function must not have any dependencies on the device state in
3217  * order to proceed.
3218  */
3219 static void nvme_remove(struct pci_dev *pdev)
3220 {
3221         struct nvme_dev *dev = pci_get_drvdata(pdev);
3222
3223         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3224         pci_set_drvdata(pdev, NULL);
3225
3226         if (!pci_device_is_present(pdev)) {
3227                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3228                 nvme_dev_disable(dev, true);
3229         }
3230
3231         flush_work(&dev->ctrl.reset_work);
3232         nvme_stop_ctrl(&dev->ctrl);
3233         nvme_remove_namespaces(&dev->ctrl);
3234         nvme_dev_disable(dev, true);
3235         nvme_remove_attrs(dev);
3236         nvme_free_host_mem(dev);
3237         nvme_dev_remove_admin(dev);
3238         nvme_free_queues(dev, 0);
3239         nvme_release_prp_pools(dev);
3240         nvme_dev_unmap(dev);
3241         nvme_uninit_ctrl(&dev->ctrl);
3242 }
3243
3244 #ifdef CONFIG_PM_SLEEP
3245 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3246 {
3247         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3248 }
3249
3250 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3251 {
3252         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3253 }
3254
3255 static int nvme_resume(struct device *dev)
3256 {
3257         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3258         struct nvme_ctrl *ctrl = &ndev->ctrl;
3259
3260         if (ndev->last_ps == U32_MAX ||
3261             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3262                 goto reset;
3263         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3264                 goto reset;
3265
3266         return 0;
3267 reset:
3268         return nvme_try_sched_reset(ctrl);
3269 }
3270
3271 static int nvme_suspend(struct device *dev)
3272 {
3273         struct pci_dev *pdev = to_pci_dev(dev);
3274         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3275         struct nvme_ctrl *ctrl = &ndev->ctrl;
3276         int ret = -EBUSY;
3277
3278         ndev->last_ps = U32_MAX;
3279
3280         /*
3281          * The platform does not remove power for a kernel managed suspend so
3282          * use host managed nvme power settings for lowest idle power if
3283          * possible. This should have quicker resume latency than a full device
3284          * shutdown.  But if the firmware is involved after the suspend or the
3285          * device does not support any non-default power states, shut down the
3286          * device fully.
3287          *
3288          * If ASPM is not enabled for the device, shut down the device and allow
3289          * the PCI bus layer to put it into D3 in order to take the PCIe link
3290          * down, so as to allow the platform to achieve its minimum low-power
3291          * state (which may not be possible if the link is up).
3292          */
3293         if (pm_suspend_via_firmware() || !ctrl->npss ||
3294             !pcie_aspm_enabled(pdev) ||
3295             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3296                 return nvme_disable_prepare_reset(ndev, true);
3297
3298         nvme_start_freeze(ctrl);
3299         nvme_wait_freeze(ctrl);
3300         nvme_sync_queues(ctrl);
3301
3302         if (ctrl->state != NVME_CTRL_LIVE)
3303                 goto unfreeze;
3304
3305         /*
3306          * Host memory access may not be successful in a system suspend state,
3307          * but the specification allows the controller to access memory in a
3308          * non-operational power state.
3309          */
3310         if (ndev->hmb) {
3311                 ret = nvme_set_host_mem(ndev, 0);
3312                 if (ret < 0)
3313                         goto unfreeze;
3314         }
3315
3316         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3317         if (ret < 0)
3318                 goto unfreeze;
3319
3320         /*
3321          * A saved state prevents pci pm from generically controlling the
3322          * device's power. If we're using protocol specific settings, we don't
3323          * want pci interfering.
3324          */
3325         pci_save_state(pdev);
3326
3327         ret = nvme_set_power_state(ctrl, ctrl->npss);
3328         if (ret < 0)
3329                 goto unfreeze;
3330
3331         if (ret) {
3332                 /* discard the saved state */
3333                 pci_load_saved_state(pdev, NULL);
3334
3335                 /*
3336                  * Clearing npss forces a controller reset on resume. The
3337                  * correct value will be rediscovered then.
3338                  */
3339                 ret = nvme_disable_prepare_reset(ndev, true);
3340                 ctrl->npss = 0;
3341         }
3342 unfreeze:
3343         nvme_unfreeze(ctrl);
3344         return ret;
3345 }
3346
3347 static int nvme_simple_suspend(struct device *dev)
3348 {
3349         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3350
3351         return nvme_disable_prepare_reset(ndev, true);
3352 }
3353
3354 static int nvme_simple_resume(struct device *dev)
3355 {
3356         struct pci_dev *pdev = to_pci_dev(dev);
3357         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3358
3359         return nvme_try_sched_reset(&ndev->ctrl);
3360 }
3361
3362 static const struct dev_pm_ops nvme_dev_pm_ops = {
3363         .suspend        = nvme_suspend,
3364         .resume         = nvme_resume,
3365         .freeze         = nvme_simple_suspend,
3366         .thaw           = nvme_simple_resume,
3367         .poweroff       = nvme_simple_suspend,
3368         .restore        = nvme_simple_resume,
3369 };
3370 #endif /* CONFIG_PM_SLEEP */
3371
3372 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3373                                                 pci_channel_state_t state)
3374 {
3375         struct nvme_dev *dev = pci_get_drvdata(pdev);
3376
3377         /*
3378          * A frozen channel requires a reset. When detected, this method will
3379          * shutdown the controller to quiesce. The controller will be restarted
3380          * after the slot reset through driver's slot_reset callback.
3381          */
3382         switch (state) {
3383         case pci_channel_io_normal:
3384                 return PCI_ERS_RESULT_CAN_RECOVER;
3385         case pci_channel_io_frozen:
3386                 dev_warn(dev->ctrl.device,
3387                         "frozen state error detected, reset controller\n");
3388                 nvme_dev_disable(dev, false);
3389                 return PCI_ERS_RESULT_NEED_RESET;
3390         case pci_channel_io_perm_failure:
3391                 dev_warn(dev->ctrl.device,
3392                         "failure state error detected, request disconnect\n");
3393                 return PCI_ERS_RESULT_DISCONNECT;
3394         }
3395         return PCI_ERS_RESULT_NEED_RESET;
3396 }
3397
3398 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3399 {
3400         struct nvme_dev *dev = pci_get_drvdata(pdev);
3401
3402         dev_info(dev->ctrl.device, "restart after slot reset\n");
3403         pci_restore_state(pdev);
3404         nvme_reset_ctrl(&dev->ctrl);
3405         return PCI_ERS_RESULT_RECOVERED;
3406 }
3407
3408 static void nvme_error_resume(struct pci_dev *pdev)
3409 {
3410         struct nvme_dev *dev = pci_get_drvdata(pdev);
3411
3412         flush_work(&dev->ctrl.reset_work);
3413 }
3414
3415 static const struct pci_error_handlers nvme_err_handler = {
3416         .error_detected = nvme_error_detected,
3417         .slot_reset     = nvme_slot_reset,
3418         .resume         = nvme_error_resume,
3419         .reset_prepare  = nvme_reset_prepare,
3420         .reset_done     = nvme_reset_done,
3421 };
3422
3423 static const struct pci_device_id nvme_id_table[] = {
3424         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3425                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3426                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3427         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3428                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3429                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3430         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3431                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3432                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3433                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3434         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3435                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3436                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3437         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3438                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3439                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3440                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3441                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3442         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3443                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3444         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3445                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3446                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3447                                 NVME_QUIRK_BOGUS_NID, },
3448         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3449                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3450         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3451                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3452                                 NVME_QUIRK_BOGUS_NID, },
3453         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3454                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3455                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3456         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3457                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3458         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3459                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3460         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3461                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3462         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3463                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3464         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3465                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3466                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3467                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3468         { PCI_DEVICE(0x1987, 0x5012),   /* Phison E12 */
3469                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3470         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3471                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3472                                 NVME_QUIRK_BOGUS_NID, },
3473         { PCI_DEVICE(0x1987, 0x5019),  /* phison E19 */
3474                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3475         { PCI_DEVICE(0x1987, 0x5021),   /* Phison E21 */
3476                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3477         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3478                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3479                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3480         { PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3481                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3482         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3483                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3484                                 NVME_QUIRK_BOGUS_NID, },
3485         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3486                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3487                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3488          { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3489                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3490         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3491                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3492         { PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
3493                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3494         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3495                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3497                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3498         { PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
3499                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3500         { PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
3501                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3502         { PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
3503                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3504         { PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
3505                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3506         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3507                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3508         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3509                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3510         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3511                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3512         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3513                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3514         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3515                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3516         { PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
3517                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3518         { PCI_DEVICE(0x1dbe, 0x5236),   /* ADATA XPG GAMMIX S70 */
3519                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3520         { PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
3521                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3522         { PCI_DEVICE(0xc0a9, 0x540a),   /* Crucial P2 */
3523                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3524         { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3525                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3526         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3527                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3528         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3529                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3530         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3531                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3532         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3533                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3534         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3535                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3536         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3537                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3538         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3539                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3540         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3541         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3542                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3543                                 NVME_QUIRK_128_BYTES_SQES |
3544                                 NVME_QUIRK_SHARED_TAGS |
3545                                 NVME_QUIRK_SKIP_CID_GEN },
3546         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3547         { 0, }
3548 };
3549 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3550
3551 static struct pci_driver nvme_driver = {
3552         .name           = "nvme",
3553         .id_table       = nvme_id_table,
3554         .probe          = nvme_probe,
3555         .remove         = nvme_remove,
3556         .shutdown       = nvme_shutdown,
3557 #ifdef CONFIG_PM_SLEEP
3558         .driver         = {
3559                 .pm     = &nvme_dev_pm_ops,
3560         },
3561 #endif
3562         .sriov_configure = pci_sriov_configure_simple,
3563         .err_handler    = &nvme_err_handler,
3564 };
3565
3566 static int __init nvme_init(void)
3567 {
3568         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3569         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3570         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3571         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3572
3573         return pci_register_driver(&nvme_driver);
3574 }
3575
3576 static void __exit nvme_exit(void)
3577 {
3578         pci_unregister_driver(&nvme_driver);
3579         flush_workqueue(nvme_wq);
3580 }
3581
3582 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3583 MODULE_LICENSE("GPL");
3584 MODULE_VERSION("1.0");
3585 module_init(nvme_init);
3586 module_exit(nvme_exit);