drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/sched.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/etherdevice.h>
  39 #include <asm/unaligned.h>
  40 #include <net/mac80211.h>
  41
  42 #include "iwl-fh.h"
  43 #include "iwl-3945-fh.h"
  44 #include "iwl-commands.h"
  45 #include "iwl-sta.h"
  46 #include "iwl-3945.h"
  47 #include "iwl-eeprom.h"
  48 #include "iwl-core.h"
  49 #include "iwl-helpers.h"
  50 #include "iwl-led.h"
  51 #include "iwl-3945-led.h"
  52
  53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  54         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  55                                     IWL_RATE_##r##M_IEEE,   \
  56                                     IWL_RATE_##ip##M_INDEX, \
  57                                     IWL_RATE_##in##M_INDEX, \
  58                                     IWL_RATE_##rp##M_INDEX, \
  59                                     IWL_RATE_##rn##M_INDEX, \
  60                                     IWL_RATE_##pp##M_INDEX, \
  61                                     IWL_RATE_##np##M_INDEX, \
  62                                     IWL_RATE_##r##M_INDEX_TABLE, \
  63                                     IWL_RATE_##ip##M_INDEX_TABLE }
  64
  65 /*
  66  * Parameter order:
  67  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  68  *
  69  * If there isn't a valid next or previous rate then INV is used which
  70  * maps to IWL_RATE_INVALID
  71  *
  72  */
  73 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  74         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  75         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  76         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  77         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  78         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  79         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  80         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  81         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  82         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  83         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  84         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  85         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  86 };
  87
  88 /* 1 = enable the iwl3945_disable_events() function */
  89 #define IWL_EVT_DISABLE (0)
  90 #define IWL_EVT_DISABLE_SIZE (1532/32)
  91
  92 /**
  93  * iwl3945_disable_events - Disable selected events in uCode event log
  94  *
  95  * Disable an event by writing "1"s into "disable"
  96  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  97  *   Default values of 0 enable uCode events to be logged.
  98  * Use for only special debugging.  This function is just a placeholder as-is,
  99  *   you'll need to provide the special bits! ...
 100  *   ... and set IWL_EVT_DISABLE to 1. */
 101 void iwl3945_disable_events(struct iwl_priv *priv)
 102 {
 103         int i;
 104         u32 base;               /* SRAM address of event log header */
 105         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 106         u32 array_size;         /* # of u32 entries in array */
 107         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 108                 0x00000000,     /*   31 -    0  Event id numbers */
 109                 0x00000000,     /*   63 -   32 */
 110                 0x00000000,     /*   95 -   64 */
 111                 0x00000000,     /*  127 -   96 */
 112                 0x00000000,     /*  159 -  128 */
 113                 0x00000000,     /*  191 -  160 */
 114                 0x00000000,     /*  223 -  192 */
 115                 0x00000000,     /*  255 -  224 */
 116                 0x00000000,     /*  287 -  256 */
 117                 0x00000000,     /*  319 -  288 */
 118                 0x00000000,     /*  351 -  320 */
 119                 0x00000000,     /*  383 -  352 */
 120                 0x00000000,     /*  415 -  384 */
 121                 0x00000000,     /*  447 -  416 */
 122                 0x00000000,     /*  479 -  448 */
 123                 0x00000000,     /*  511 -  480 */
 124                 0x00000000,     /*  543 -  512 */
 125                 0x00000000,     /*  575 -  544 */
 126                 0x00000000,     /*  607 -  576 */
 127                 0x00000000,     /*  639 -  608 */
 128                 0x00000000,     /*  671 -  640 */
 129                 0x00000000,     /*  703 -  672 */
 130                 0x00000000,     /*  735 -  704 */
 131                 0x00000000,     /*  767 -  736 */
 132                 0x00000000,     /*  799 -  768 */
 133                 0x00000000,     /*  831 -  800 */
 134                 0x00000000,     /*  863 -  832 */
 135                 0x00000000,     /*  895 -  864 */
 136                 0x00000000,     /*  927 -  896 */
 137                 0x00000000,     /*  959 -  928 */
 138                 0x00000000,     /*  991 -  960 */
 139                 0x00000000,     /* 1023 -  992 */
 140                 0x00000000,     /* 1055 - 1024 */
 141                 0x00000000,     /* 1087 - 1056 */
 142                 0x00000000,     /* 1119 - 1088 */
 143                 0x00000000,     /* 1151 - 1120 */
 144                 0x00000000,     /* 1183 - 1152 */
 145                 0x00000000,     /* 1215 - 1184 */
 146                 0x00000000,     /* 1247 - 1216 */
 147                 0x00000000,     /* 1279 - 1248 */
 148                 0x00000000,     /* 1311 - 1280 */
 149                 0x00000000,     /* 1343 - 1312 */
 150                 0x00000000,     /* 1375 - 1344 */
 151                 0x00000000,     /* 1407 - 1376 */
 152                 0x00000000,     /* 1439 - 1408 */
 153                 0x00000000,     /* 1471 - 1440 */
 154                 0x00000000,     /* 1503 - 1472 */
 155         };
 156
 157         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 158         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 159                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 160                 return;
 161         }
 162
 163         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 164         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 165
 166         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 167                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 168                                disable_ptr);
 169                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 170                         iwl_write_targ_mem(priv,
 171                                            disable_ptr + (i * sizeof(u32)),
 172                                            evt_disable[i]);
 173
 174         } else {
 175                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 176                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 177                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 178                                disable_ptr, array_size);
 179         }
 180
 181 }
 182
 183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 184 {
 185         int idx;
 186
 187         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 188                 if (iwl3945_rates[idx].plcp == plcp)
 189                         return idx;
 190         return -1;
 191 }
 192
 193 #ifdef CONFIG_IWLWIFI_DEBUG
 194 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 195
 196 static const char *iwl3945_get_tx_fail_reason(u32 status)
 197 {
 198         switch (status & TX_STATUS_MSK) {
 199         case TX_STATUS_SUCCESS:
 200                 return "SUCCESS";
 201                 TX_STATUS_ENTRY(SHORT_LIMIT);
 202                 TX_STATUS_ENTRY(LONG_LIMIT);
 203                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 204                 TX_STATUS_ENTRY(MGMNT_ABORT);
 205                 TX_STATUS_ENTRY(NEXT_FRAG);
 206                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 207                 TX_STATUS_ENTRY(DEST_PS);
 208                 TX_STATUS_ENTRY(ABORTED);
 209                 TX_STATUS_ENTRY(BT_RETRY);
 210                 TX_STATUS_ENTRY(STA_INVALID);
 211                 TX_STATUS_ENTRY(FRAG_DROPPED);
 212                 TX_STATUS_ENTRY(TID_DISABLE);
 213                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 214                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 215                 TX_STATUS_ENTRY(TX_LOCKED);
 216                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 217         }
 218
 219         return "UNKNOWN";
 220 }
 221 #else
 222 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 223 {
 224         return "";
 225 }
 226 #endif
 227
 228 /*
 229  * get ieee prev rate from rate scale table.
 230  * for A and B mode we need to overright prev
 231  * value
 232  */
 233 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 234 {
 235         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 236
 237         switch (priv->band) {
 238         case IEEE80211_BAND_5GHZ:
 239                 if (rate == IWL_RATE_12M_INDEX)
 240                         next_rate = IWL_RATE_9M_INDEX;
 241                 else if (rate == IWL_RATE_6M_INDEX)
 242                         next_rate = IWL_RATE_6M_INDEX;
 243                 break;
 244         case IEEE80211_BAND_2GHZ:
 245                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 246                     iwl_is_associated(priv)) {
 247                         if (rate == IWL_RATE_11M_INDEX)
 248                                 next_rate = IWL_RATE_5M_INDEX;
 249                 }
 250                 break;
 251
 252         default:
 253                 break;
 254         }
 255
 256         return next_rate;
 257 }
 258
 259
 260 /**
 261  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 262  *
 263  * When FW advances 'R' index, all entries between old and new 'R' index
 264  * need to be reclaimed. As result, some free space forms. If there is
 265  * enough free space (> low mark), wake the stack that feeds us.
 266  */
 267 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 268                                      int txq_id, int index)
 269 {
 270         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 271         struct iwl_queue *q = &txq->q;
 272         struct iwl_tx_info *tx_info;
 273
 274         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 275
 276         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 277                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 278
 279                 tx_info = &txq->txb[txq->q.read_ptr];
 280                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 281                 tx_info->skb[0] = NULL;
 282                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 283         }
 284
 285         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 286                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 287                         priv->mac80211_registered)
 288                 iwl_wake_queue(priv, txq_id);
 289 }
 290
 291 /**
 292  * iwl3945_rx_reply_tx - Handle Tx response
 293  */
 294 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 295                             struct iwl_rx_mem_buffer *rxb)
 296 {
 297         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 298         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 299         int txq_id = SEQ_TO_QUEUE(sequence);
 300         int index = SEQ_TO_INDEX(sequence);
 301         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 302         struct ieee80211_tx_info *info;
 303         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 304         u32  status = le32_to_cpu(tx_resp->status);
 305         int rate_idx;
 306         int fail;
 307
 308         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 309                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 310                           "is out of range [0-%d] %d %d\n", txq_id,
 311                           index, txq->q.n_bd, txq->q.write_ptr,
 312                           txq->q.read_ptr);
 313                 return;
 314         }
 315
 316         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 317         ieee80211_tx_info_clear_status(info);
 318
 319         /* Fill the MRR chain with some info about on-chip retransmissions */
 320         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 321         if (info->band == IEEE80211_BAND_5GHZ)
 322                 rate_idx -= IWL_FIRST_OFDM_RATE;
 323
 324         fail = tx_resp->failure_frame;
 325
 326         info->status.rates[0].idx = rate_idx;
 327         info->status.rates[0].count = fail + 1; /* add final attempt */
 328
 329         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 330         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 331                                 IEEE80211_TX_STAT_ACK : 0;
 332
 333         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 334                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 335                         tx_resp->rate, tx_resp->failure_frame);
 336
 337         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 338         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 339
 340         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 341                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 342 }
 343
 344
 345
 346 /*****************************************************************************
 347  *
 348  * Intel PRO/Wireless 3945ABG/BG Network Connection
 349  *
 350  *  RX handler implementations
 351  *
 352  *****************************************************************************/
 353
 354 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 355                 struct iwl_rx_mem_buffer *rxb)
 356 {
 357         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 358         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 359                      (int)sizeof(struct iwl3945_notif_statistics),
 360                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 361
 362         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 363 }
 364
 365 /******************************************************************************
 366  *
 367  * Misc. internal state and helper functions
 368  *
 369  ******************************************************************************/
 370 #ifdef CONFIG_IWLWIFI_DEBUG
 371
 372 /**
 373  * iwl3945_report_frame - dump frame to syslog during debug sessions
 374  *
 375  * You may hack this function to show different aspects of received frames,
 376  * including selective frame dumps.
 377  * group100 parameter selects whether to show 1 out of 100 good frames.
 378  */
 379 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 380                       struct iwl_rx_packet *pkt,
 381                       struct ieee80211_hdr *header, int group100)
 382 {
 383         u32 to_us;
 384         u32 print_summary = 0;
 385         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 386         u32 hundred = 0;
 387         u32 dataframe = 0;
 388         __le16 fc;
 389         u16 seq_ctl;
 390         u16 channel;
 391         u16 phy_flags;
 392         u16 length;
 393         u16 status;
 394         u16 bcn_tmr;
 395         u32 tsf_low;
 396         u64 tsf;
 397         u8 rssi;
 398         u8 agc;
 399         u16 sig_avg;
 400         u16 noise_diff;
 401         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 402         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 403         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 404         u8 *data = IWL_RX_DATA(pkt);
 405
 406         /* MAC header */
 407         fc = header->frame_control;
 408         seq_ctl = le16_to_cpu(header->seq_ctrl);
 409
 410         /* metadata */
 411         channel = le16_to_cpu(rx_hdr->channel);
 412         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 413         length = le16_to_cpu(rx_hdr->len);
 414
 415         /* end-of-frame status and timestamp */
 416         status = le32_to_cpu(rx_end->status);
 417         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 418         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 419         tsf = le64_to_cpu(rx_end->timestamp);
 420
 421         /* signal statistics */
 422         rssi = rx_stats->rssi;
 423         agc = rx_stats->agc;
 424         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 425         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 426
 427         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 428
 429         /* if data frame is to us and all is good,
 430          *   (optionally) print summary for only 1 out of every 100 */
 431         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 432             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 433                 dataframe = 1;
 434                 if (!group100)
 435                         print_summary = 1;      /* print each frame */
 436                 else if (priv->framecnt_to_us < 100) {
 437                         priv->framecnt_to_us++;
 438                         print_summary = 0;
 439                 } else {
 440                         priv->framecnt_to_us = 0;
 441                         print_summary = 1;
 442                         hundred = 1;
 443                 }
 444         } else {
 445                 /* print summary for all other frames */
 446                 print_summary = 1;
 447         }
 448
 449         if (print_summary) {
 450                 char *title;
 451                 int rate;
 452
 453                 if (hundred)
 454                         title = "100Frames";
 455                 else if (ieee80211_has_retry(fc))
 456                         title = "Retry";
 457                 else if (ieee80211_is_assoc_resp(fc))
 458                         title = "AscRsp";
 459                 else if (ieee80211_is_reassoc_resp(fc))
 460                         title = "RasRsp";
 461                 else if (ieee80211_is_probe_resp(fc)) {
 462                         title = "PrbRsp";
 463                         print_dump = 1; /* dump frame contents */
 464                 } else if (ieee80211_is_beacon(fc)) {
 465                         title = "Beacon";
 466                         print_dump = 1; /* dump frame contents */
 467                 } else if (ieee80211_is_atim(fc))
 468                         title = "ATIM";
 469                 else if (ieee80211_is_auth(fc))
 470                         title = "Auth";
 471                 else if (ieee80211_is_deauth(fc))
 472                         title = "DeAuth";
 473                 else if (ieee80211_is_disassoc(fc))
 474                         title = "DisAssoc";
 475                 else
 476                         title = "Frame";
 477
 478                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 479                 if (rate == -1)
 480                         rate = 0;
 481                 else
 482                         rate = iwl3945_rates[rate].ieee / 2;
 483
 484                 /* print frame summary.
 485                  * MAC addresses show just the last byte (for brevity),
 486                  *    but you can hack it to show more, if you'd like to. */
 487                 if (dataframe)
 488                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 489                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 490                                      title, le16_to_cpu(fc), header->addr1[5],
 491                                      length, rssi, channel, rate);
 492                 else {
 493                         /* src/dst addresses assume managed mode */
 494                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 495                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 496                                      "phy=0x%02x, chnl=%d\n",
 497                                      title, le16_to_cpu(fc), header->addr1[5],
 498                                      header->addr3[5], rssi,
 499                                      tsf_low - priv->scan_start_tsf,
 500                                      phy_flags, channel);
 501                 }
 502         }
 503         if (print_dump)
 504                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 505 }
 506
 507 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 508                       struct iwl_rx_packet *pkt,
 509                       struct ieee80211_hdr *header, int group100)
 510 {
 511         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 512                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 513 }
 514
 515 #else
 516 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 517                       struct iwl_rx_packet *pkt,
 518                       struct ieee80211_hdr *header, int group100)
 519 {
 520 }
 521 #endif
 522
 523 /* This is necessary only for a number of statistics, see the caller. */
 524 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 525                 struct ieee80211_hdr *header)
 526 {
 527         /* Filter incoming packets to determine if they are targeted toward
 528          * this network, discarding packets coming from ourselves */
 529         switch (priv->iw_mode) {
 530         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 531                 /* packets to our IBSS update information */
 532                 return !compare_ether_addr(header->addr3, priv->bssid);
 533         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 534                 /* packets to our IBSS update information */
 535                 return !compare_ether_addr(header->addr2, priv->bssid);
 536         default:
 537                 return 1;
 538         }
 539 }
 540
 541 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 542                                    struct iwl_rx_mem_buffer *rxb,
 543                                    struct ieee80211_rx_status *stats)
 544 {
 545         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 546         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 547         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 548         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 549         u16 len = le16_to_cpu(rx_hdr->len);
 550         struct sk_buff *skb;
 551         int ret;
 552         __le16 fc = hdr->frame_control;
 553
 554         /* We received data from the HW, so stop the watchdog */
 555         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 556                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 557                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 558                 return;
 559         }
 560
 561         /* We only process data packets if the interface is open */
 562         if (unlikely(!priv->is_open)) {
 563                 IWL_DEBUG_DROP_LIMIT(priv,
 564                         "Dropping packet while interface is not open.\n");
 565                 return;
 566         }
 567
 568         skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
 569         if (!skb) {
 570                 IWL_ERR(priv, "alloc_skb failed\n");
 571                 return;
 572         }
 573
 574         if (!iwl3945_mod_params.sw_crypto)
 575                 iwl_set_decrypted_flag(priv,
 576                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 577                                        le32_to_cpu(rx_end->status), stats);
 578
 579         skb_reserve(skb, IWL_LINK_HDR_MAX);
 580         skb_add_rx_frag(skb, 0, rxb->page,
 581                         (void *)rx_hdr->payload - (void *)pkt, len);
 582
 583         /* mac80211 currently doesn't support paged SKB. Convert it to
 584          * linear SKB for management frame and data frame requires
 585          * software decryption or software defragementation. */
 586         if (ieee80211_is_mgmt(fc) ||
 587             ieee80211_has_protected(fc) ||
 588             ieee80211_has_morefrags(fc) ||
 589             le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
 590                 ret = skb_linearize(skb);
 591         else
 592                 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
 593                         0 : -ENOMEM;
 594
 595         if (ret) {
 596                 kfree_skb(skb);
 597                 goto out;
 598         }
 599
 600         /*
 601          * XXX: We cannot touch the page and its virtual memory (pkt) after
 602          * here. It might have already been freed by the above skb change.
 603          */
 604
 605         iwl_update_stats(priv, false, fc, len);
 606         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 607
 608         ieee80211_rx(priv->hw, skb);
 609  out:
 610         priv->alloc_rxb_page--;
 611         rxb->page = NULL;
 612 }
 613
 614 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 615
 616 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 617                                 struct iwl_rx_mem_buffer *rxb)
 618 {
 619         struct ieee80211_hdr *header;
 620         struct ieee80211_rx_status rx_status;
 621         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 622         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 623         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 624         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 625         int snr;
 626         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 627         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 628         u8 network_packet;
 629
 630         rx_status.flag = 0;
 631         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 632         rx_status.freq =
 633                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 634         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 635                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 636
 637         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 638         if (rx_status.band == IEEE80211_BAND_5GHZ)
 639                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 640
 641         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 642                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 643
 644         /* set the preamble flag if appropriate */
 645         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 646                 rx_status.flag |= RX_FLAG_SHORTPRE;
 647
 648         if ((unlikely(rx_stats->phy_count > 20))) {
 649                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 650                                 rx_stats->phy_count);
 651                 return;
 652         }
 653
 654         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 655             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 656                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 657                 return;
 658         }
 659
 660
 661
 662         /* Convert 3945's rssi indicator to dBm */
 663         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 664
 665         /* Set default noise value to -127 */
 666         if (priv->last_rx_noise == 0)
 667                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 668
 669         /* 3945 provides noise info for OFDM frames only.
 670          * sig_avg and noise_diff are measured by the 3945's digital signal
 671          *   processor (DSP), and indicate linear levels of signal level and
 672          *   distortion/noise within the packet preamble after
 673          *   automatic gain control (AGC).  sig_avg should stay fairly
 674          *   constant if the radio's AGC is working well.
 675          * Since these values are linear (not dB or dBm), linear
 676          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 677          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 678          *   to obtain noise level in dBm.
 679          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 680         if (rx_stats_noise_diff) {
 681                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 682                 rx_status.noise = rx_status.signal -
 683                                         iwl3945_calc_db_from_ratio(snr);
 684         } else {
 685                 rx_status.noise = priv->last_rx_noise;
 686         }
 687
 688
 689         IWL_DEBUG_STATS(priv, "Rssi %d noise %d sig_avg %d noise_diff %d\n",
 690                         rx_status.signal, rx_status.noise,
 691                         rx_stats_sig_avg, rx_stats_noise_diff);
 692
 693         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 694
 695         network_packet = iwl3945_is_network_packet(priv, header);
 696
 697         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 698                               network_packet ? '*' : ' ',
 699                               le16_to_cpu(rx_hdr->channel),
 700                               rx_status.signal, rx_status.signal,
 701                               rx_status.noise, rx_status.rate_idx);
 702
 703         /* Set "1" to report good data frames in groups of 100 */
 704         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 705         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 706
 707         if (network_packet) {
 708                 priv->_3945.last_beacon_time =
 709                         le32_to_cpu(rx_end->beacon_timestamp);
 710                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 711                 priv->_3945.last_rx_rssi = rx_status.signal;
 712                 priv->last_rx_noise = rx_status.noise;
 713         }
 714
 715         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 716 }
 717
 718 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 719                                      struct iwl_tx_queue *txq,
 720                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 721 {
 722         int count;
 723         struct iwl_queue *q;
 724         struct iwl3945_tfd *tfd, *tfd_tmp;
 725
 726         q = &txq->q;
 727         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 728         tfd = &tfd_tmp[q->write_ptr];
 729
 730         if (reset)
 731                 memset(tfd, 0, sizeof(*tfd));
 732
 733         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 734
 735         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 736                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 737                           NUM_TFD_CHUNKS);
 738                 return -EINVAL;
 739         }
 740
 741         tfd->tbs[count].addr = cpu_to_le32(addr);
 742         tfd->tbs[count].len = cpu_to_le32(len);
 743
 744         count++;
 745
 746         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 747                                          TFD_CTL_PAD_SET(pad));
 748
 749         return 0;
 750 }
 751
 752 /**
 753  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 754  *
 755  * Does NOT advance any indexes
 756  */
 757 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 758 {
 759         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 760         int index = txq->q.read_ptr;
 761         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 762         struct pci_dev *dev = priv->pci_dev;
 763         int i;
 764         int counter;
 765
 766         /* sanity check */
 767         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 768         if (counter > NUM_TFD_CHUNKS) {
 769                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 770                 /* @todo issue fatal error, it is quite serious situation */
 771                 return;
 772         }
 773
 774         /* Unmap tx_cmd */
 775         if (counter)
 776                 pci_unmap_single(dev,
 777                                 pci_unmap_addr(&txq->meta[index], mapping),
 778                                 pci_unmap_len(&txq->meta[index], len),
 779                                 PCI_DMA_TODEVICE);
 780
 781         /* unmap chunks if any */
 782
 783         for (i = 1; i < counter; i++) {
 784                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 785                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 786                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 787                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 788                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 789                                 /* Can be called from interrupt context */
 790                                 dev_kfree_skb_any(skb);
 791                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 792                         }
 793                 }
 794         }
 795         return ;
 796 }
 797
 798 /**
 799  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 800  *
 801 */
 802 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 803                                   struct iwl_device_cmd *cmd,
 804                                   struct ieee80211_tx_info *info,
 805                                   struct ieee80211_hdr *hdr,
 806                                   int sta_id, int tx_id)
 807 {
 808         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 809         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 810         u16 rate_mask;
 811         int rate;
 812         u8 rts_retry_limit;
 813         u8 data_retry_limit;
 814         __le32 tx_flags;
 815         __le16 fc = hdr->frame_control;
 816         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 817
 818         rate = iwl3945_rates[rate_index].plcp;
 819         tx_flags = tx_cmd->tx_flags;
 820
 821         /* We need to figure out how to get the sta->supp_rates while
 822          * in this running context */
 823         rate_mask = IWL_RATES_MASK;
 824
 825
 826         /* Set retry limit on DATA packets and Probe Responses*/
 827         if (ieee80211_is_probe_resp(fc))
 828                 data_retry_limit = 3;
 829         else
 830                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 831         tx_cmd->data_retry_limit = data_retry_limit;
 832
 833         if (tx_id >= IWL_CMD_QUEUE_NUM)
 834                 rts_retry_limit = 3;
 835         else
 836                 rts_retry_limit = 7;
 837
 838         if (data_retry_limit < rts_retry_limit)
 839                 rts_retry_limit = data_retry_limit;
 840         tx_cmd->rts_retry_limit = rts_retry_limit;
 841
 842         if (ieee80211_is_mgmt(fc)) {
 843                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 844                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 845                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 846                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 847                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 848                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 849                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 850                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 851                         }
 852                         break;
 853                 default:
 854                         break;
 855                 }
 856         }
 857
 858         tx_cmd->rate = rate;
 859         tx_cmd->tx_flags = tx_flags;
 860
 861         /* OFDM */
 862         tx_cmd->supp_rates[0] =
 863            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 864
 865         /* CCK */
 866         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 867
 868         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 869                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 870                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 871                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 872 }
 873
 874 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 875 {
 876         unsigned long flags_spin;
 877         struct iwl_station_entry *station;
 878
 879         if (sta_id == IWL_INVALID_STATION)
 880                 return IWL_INVALID_STATION;
 881
 882         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 883         station = &priv->stations[sta_id];
 884
 885         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 886         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 887         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 888
 889         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 890
 891         iwl_send_add_sta(priv, &station->sta, flags);
 892         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 893                         sta_id, tx_rate);
 894         return sta_id;
 895 }
 896
 897 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 898 {
 899         if (src == IWL_PWR_SRC_VAUX) {
 900                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 901                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 902                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 903                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 904
 905                         iwl_poll_bit(priv, CSR_GPIO_IN,
 906                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 907                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 908                 }
 909         } else {
 910                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 911                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 912                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 913
 914                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 915                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 922 {
 923         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 924         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 925         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 926         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 927                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 928                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 929                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 930                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 931                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 932                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 933                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 934                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 935
 936         /* fake read to flush all prev I/O */
 937         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 938
 939         return 0;
 940 }
 941
 942 static int iwl3945_tx_reset(struct iwl_priv *priv)
 943 {
 944
 945         /* bypass mode */
 946         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 947
 948         /* RA 0 is active */
 949         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 950
 951         /* all 6 fifo are active */
 952         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 953
 954         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 955         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 956         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 957         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 958
 959         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 960                              priv->_3945.shared_phys);
 961
 962         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 963                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 964                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 965                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 966                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 967                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 968                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 969                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 970
 971
 972         return 0;
 973 }
 974
 975 /**
 976  * iwl3945_txq_ctx_reset - Reset TX queue context
 977  *
 978  * Destroys all DMA structures and initialize them again
 979  */
 980 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 981 {
 982         int rc;
 983         int txq_id, slots_num;
 984
 985         iwl3945_hw_txq_ctx_free(priv);
 986
 987         /* allocate tx queue structure */
 988         rc = iwl_alloc_txq_mem(priv);
 989         if (rc)
 990                 return rc;
 991
 992         /* Tx CMD queue */
 993         rc = iwl3945_tx_reset(priv);
 994         if (rc)
 995                 goto error;
 996
 997         /* Tx queue(s) */
 998         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 999                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1000                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1001                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1002                                        txq_id);
1003                 if (rc) {
1004                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1005                         goto error;
1006                 }
1007         }
1008
1009         return rc;
1010
1011  error:
1012         iwl3945_hw_txq_ctx_free(priv);
1013         return rc;
1014 }
1015
1016
1017 /*
1018  * Start up 3945's basic functionality after it has been reset
1019  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1020  * NOTE:  This does not load uCode nor start the embedded processor
1021  */
1022 static int iwl3945_apm_init(struct iwl_priv *priv)
1023 {
1024         int ret = iwl_apm_init(priv);
1025
1026         /* Clear APMG (NIC's internal power management) interrupts */
1027         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1028         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1029
1030         /* Reset radio chip */
1031         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1032         udelay(5);
1033         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1034
1035         return ret;
1036 }
1037
1038 static void iwl3945_nic_config(struct iwl_priv *priv)
1039 {
1040         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1041         unsigned long flags;
1042         u8 rev_id = 0;
1043
1044         spin_lock_irqsave(&priv->lock, flags);
1045
1046         /* Determine HW type */
1047         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1048
1049         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1050
1051         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1052                 IWL_DEBUG_INFO(priv, "RTP type \n");
1053         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1054                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1055                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1056                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1057         } else {
1058                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1059                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1060                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1061         }
1062
1063         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1064                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1065                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1066                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1067         } else
1068                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1069
1070         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1071                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1072                                eeprom->board_revision);
1073                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1074                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1075         } else {
1076                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1077                                eeprom->board_revision);
1078                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1079                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1080         }
1081
1082         if (eeprom->almgor_m_version <= 1) {
1083                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1084                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1085                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1086                                eeprom->almgor_m_version);
1087         } else {
1088                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1089                                eeprom->almgor_m_version);
1090                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1091                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1092         }
1093         spin_unlock_irqrestore(&priv->lock, flags);
1094
1095         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1096                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1097
1098         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1099                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1100 }
1101
1102 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1103 {
1104         int rc;
1105         unsigned long flags;
1106         struct iwl_rx_queue *rxq = &priv->rxq;
1107
1108         spin_lock_irqsave(&priv->lock, flags);
1109         priv->cfg->ops->lib->apm_ops.init(priv);
1110         spin_unlock_irqrestore(&priv->lock, flags);
1111
1112         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1113         if (rc)
1114                 return rc;
1115
1116         priv->cfg->ops->lib->apm_ops.config(priv);
1117
1118         /* Allocate the RX queue, or reset if it is already allocated */
1119         if (!rxq->bd) {
1120                 rc = iwl_rx_queue_alloc(priv);
1121                 if (rc) {
1122                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1123                         return -ENOMEM;
1124                 }
1125         } else
1126                 iwl3945_rx_queue_reset(priv, rxq);
1127
1128         iwl3945_rx_replenish(priv);
1129
1130         iwl3945_rx_init(priv, rxq);
1131
1132
1133         /* Look at using this instead:
1134         rxq->need_update = 1;
1135         iwl_rx_queue_update_write_ptr(priv, rxq);
1136         */
1137
1138         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1139
1140         rc = iwl3945_txq_ctx_reset(priv);
1141         if (rc)
1142                 return rc;
1143
1144         set_bit(STATUS_INIT, &priv->status);
1145
1146         return 0;
1147 }
1148
1149 /**
1150  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1151  *
1152  * Destroy all TX DMA queues and structures
1153  */
1154 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1155 {
1156         int txq_id;
1157
1158         /* Tx queues */
1159         if (priv->txq)
1160                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1161                      txq_id++)
1162                         if (txq_id == IWL_CMD_QUEUE_NUM)
1163                                 iwl_cmd_queue_free(priv);
1164                         else
1165                                 iwl_tx_queue_free(priv, txq_id);
1166
1167         /* free tx queue structure */
1168         iwl_free_txq_mem(priv);
1169 }
1170
1171 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1172 {
1173         int txq_id;
1174
1175         /* stop SCD */
1176         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1177         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1178
1179         /* reset TFD queues */
1180         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1181                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1182                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1183                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1184                                 1000);
1185         }
1186
1187         iwl3945_hw_txq_ctx_free(priv);
1188 }
1189
1190 /**
1191  * iwl3945_hw_reg_adjust_power_by_temp
1192  * return index delta into power gain settings table
1193 */
1194 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1195 {
1196         return (new_reading - old_reading) * (-11) / 100;
1197 }
1198
1199 /**
1200  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1201  */
1202 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1203 {
1204         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1205 }
1206
1207 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1208 {
1209         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1210 }
1211
1212 /**
1213  * iwl3945_hw_reg_txpower_get_temperature
1214  * get the current temperature by reading from NIC
1215 */
1216 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1217 {
1218         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1219         int temperature;
1220
1221         temperature = iwl3945_hw_get_temperature(priv);
1222
1223         /* driver's okay range is -260 to +25.
1224          *   human readable okay range is 0 to +285 */
1225         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1226
1227         /* handle insane temp reading */
1228         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1229                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1230
1231                 /* if really really hot(?),
1232                  *   substitute the 3rd band/group's temp measured at factory */
1233                 if (priv->last_temperature > 100)
1234                         temperature = eeprom->groups[2].temperature;
1235                 else /* else use most recent "sane" value from driver */
1236                         temperature = priv->last_temperature;
1237         }
1238
1239         return temperature;     /* raw, not "human readable" */
1240 }
1241
1242 /* Adjust Txpower only if temperature variance is greater than threshold.
1243  *
1244  * Both are lower than older versions' 9 degrees */
1245 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1246
1247 /**
1248  * is_temp_calib_needed - determines if new calibration is needed
1249  *
1250  * records new temperature in tx_mgr->temperature.
1251  * replaces tx_mgr->last_temperature *only* if calib needed
1252  *    (assumes caller will actually do the calibration!). */
1253 static int is_temp_calib_needed(struct iwl_priv *priv)
1254 {
1255         int temp_diff;
1256
1257         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1258         temp_diff = priv->temperature - priv->last_temperature;
1259
1260         /* get absolute value */
1261         if (temp_diff < 0) {
1262                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1263                 temp_diff = -temp_diff;
1264         } else if (temp_diff == 0)
1265                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1266         else
1267                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1268
1269         /* if we don't need calibration, *don't* update last_temperature */
1270         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1271                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1272                 return 0;
1273         }
1274
1275         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1276
1277         /* assume that caller will actually do calib ...
1278          *   update the "last temperature" value */
1279         priv->last_temperature = priv->temperature;
1280         return 1;
1281 }
1282
1283 #define IWL_MAX_GAIN_ENTRIES 78
1284 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1285 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1286
1287 /* radio and DSP power table, each step is 1/2 dB.
1288  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1289 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1290         {
1291          {251, 127},            /* 2.4 GHz, highest power */
1292          {251, 127},
1293          {251, 127},
1294          {251, 127},
1295          {251, 125},
1296          {251, 110},
1297          {251, 105},
1298          {251, 98},
1299          {187, 125},
1300          {187, 115},
1301          {187, 108},
1302          {187, 99},
1303          {243, 119},
1304          {243, 111},
1305          {243, 105},
1306          {243, 97},
1307          {243, 92},
1308          {211, 106},
1309          {211, 100},
1310          {179, 120},
1311          {179, 113},
1312          {179, 107},
1313          {147, 125},
1314          {147, 119},
1315          {147, 112},
1316          {147, 106},
1317          {147, 101},
1318          {147, 97},
1319          {147, 91},
1320          {115, 107},
1321          {235, 121},
1322          {235, 115},
1323          {235, 109},
1324          {203, 127},
1325          {203, 121},
1326          {203, 115},
1327          {203, 108},
1328          {203, 102},
1329          {203, 96},
1330          {203, 92},
1331          {171, 110},
1332          {171, 104},
1333          {171, 98},
1334          {139, 116},
1335          {227, 125},
1336          {227, 119},
1337          {227, 113},
1338          {227, 107},
1339          {227, 101},
1340          {227, 96},
1341          {195, 113},
1342          {195, 106},
1343          {195, 102},
1344          {195, 95},
1345          {163, 113},
1346          {163, 106},
1347          {163, 102},
1348          {163, 95},
1349          {131, 113},
1350          {131, 106},
1351          {131, 102},
1352          {131, 95},
1353          {99, 113},
1354          {99, 106},
1355          {99, 102},
1356          {99, 95},
1357          {67, 113},
1358          {67, 106},
1359          {67, 102},
1360          {67, 95},
1361          {35, 113},
1362          {35, 106},
1363          {35, 102},
1364          {35, 95},
1365          {3, 113},
1366          {3, 106},
1367          {3, 102},
1368          {3, 95} },             /* 2.4 GHz, lowest power */
1369         {
1370          {251, 127},            /* 5.x GHz, highest power */
1371          {251, 120},
1372          {251, 114},
1373          {219, 119},
1374          {219, 101},
1375          {187, 113},
1376          {187, 102},
1377          {155, 114},
1378          {155, 103},
1379          {123, 117},
1380          {123, 107},
1381          {123, 99},
1382          {123, 92},
1383          {91, 108},
1384          {59, 125},
1385          {59, 118},
1386          {59, 109},
1387          {59, 102},
1388          {59, 96},
1389          {59, 90},
1390          {27, 104},
1391          {27, 98},
1392          {27, 92},
1393          {115, 118},
1394          {115, 111},
1395          {115, 104},
1396          {83, 126},
1397          {83, 121},
1398          {83, 113},
1399          {83, 105},
1400          {83, 99},
1401          {51, 118},
1402          {51, 111},
1403          {51, 104},
1404          {51, 98},
1405          {19, 116},
1406          {19, 109},
1407          {19, 102},
1408          {19, 98},
1409          {19, 93},
1410          {171, 113},
1411          {171, 107},
1412          {171, 99},
1413          {139, 120},
1414          {139, 113},
1415          {139, 107},
1416          {139, 99},
1417          {107, 120},
1418          {107, 113},
1419          {107, 107},
1420          {107, 99},
1421          {75, 120},
1422          {75, 113},
1423          {75, 107},
1424          {75, 99},
1425          {43, 120},
1426          {43, 113},
1427          {43, 107},
1428          {43, 99},
1429          {11, 120},
1430          {11, 113},
1431          {11, 107},
1432          {11, 99},
1433          {131, 107},
1434          {131, 99},
1435          {99, 120},
1436          {99, 113},
1437          {99, 107},
1438          {99, 99},
1439          {67, 120},
1440          {67, 113},
1441          {67, 107},
1442          {67, 99},
1443          {35, 120},
1444          {35, 113},
1445          {35, 107},
1446          {35, 99},
1447          {3, 120} }             /* 5.x GHz, lowest power */
1448 };
1449
1450 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1451 {
1452         if (index < 0)
1453                 return 0;
1454         if (index >= IWL_MAX_GAIN_ENTRIES)
1455                 return IWL_MAX_GAIN_ENTRIES - 1;
1456         return (u8) index;
1457 }
1458
1459 /* Kick off thermal recalibration check every 60 seconds */
1460 #define REG_RECALIB_PERIOD (60)
1461
1462 /**
1463  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1464  *
1465  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1466  * or 6 Mbit (OFDM) rates.
1467  */
1468 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1469                                s32 rate_index, const s8 *clip_pwrs,
1470                                struct iwl_channel_info *ch_info,
1471                                int band_index)
1472 {
1473         struct iwl3945_scan_power_info *scan_power_info;
1474         s8 power;
1475         u8 power_index;
1476
1477         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1478
1479         /* use this channel group's 6Mbit clipping/saturation pwr,
1480          *   but cap at regulatory scan power restriction (set during init
1481          *   based on eeprom channel data) for this channel.  */
1482         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1483
1484         /* further limit to user's max power preference.
1485          * FIXME:  Other spectrum management power limitations do not
1486          *   seem to apply?? */
1487         power = min(power, priv->tx_power_user_lmt);
1488         scan_power_info->requested_power = power;
1489
1490         /* find difference between new scan *power* and current "normal"
1491          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1492          *   current "normal" temperature-compensated Tx power *index* for
1493          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1494          *   *index*. */
1495         power_index = ch_info->power_info[rate_index].power_table_index
1496             - (power - ch_info->power_info
1497                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1498
1499         /* store reference index that we use when adjusting *all* scan
1500          *   powers.  So we can accommodate user (all channel) or spectrum
1501          *   management (single channel) power changes "between" temperature
1502          *   feedback compensation procedures.
1503          * don't force fit this reference index into gain table; it may be a
1504          *   negative number.  This will help avoid errors when we're at
1505          *   the lower bounds (highest gains, for warmest temperatures)
1506          *   of the table. */
1507
1508         /* don't exceed table bounds for "real" setting */
1509         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1510
1511         scan_power_info->power_table_index = power_index;
1512         scan_power_info->tpc.tx_gain =
1513             power_gain_table[band_index][power_index].tx_gain;
1514         scan_power_info->tpc.dsp_atten =
1515             power_gain_table[band_index][power_index].dsp_atten;
1516 }
1517
1518 /**
1519  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1520  *
1521  * Configures power settings for all rates for the current channel,
1522  * using values from channel info struct, and send to NIC
1523  */
1524 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1525 {
1526         int rate_idx, i;
1527         const struct iwl_channel_info *ch_info = NULL;
1528         struct iwl3945_txpowertable_cmd txpower = {
1529                 .channel = priv->active_rxon.channel,
1530         };
1531
1532         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1533         ch_info = iwl_get_channel_info(priv,
1534                                        priv->band,
1535                                        le16_to_cpu(priv->active_rxon.channel));
1536         if (!ch_info) {
1537                 IWL_ERR(priv,
1538                         "Failed to get channel info for channel %d [%d]\n",
1539                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1540                 return -EINVAL;
1541         }
1542
1543         if (!is_channel_valid(ch_info)) {
1544                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1545                                 "non-Tx channel.\n");
1546                 return 0;
1547         }
1548
1549         /* fill cmd with power settings for all rates for current channel */
1550         /* Fill OFDM rate */
1551         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1552              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1553
1554                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1555                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1556
1557                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1558                                 le16_to_cpu(txpower.channel),
1559                                 txpower.band,
1560                                 txpower.power[i].tpc.tx_gain,
1561                                 txpower.power[i].tpc.dsp_atten,
1562                                 txpower.power[i].rate);
1563         }
1564         /* Fill CCK rates */
1565         for (rate_idx = IWL_FIRST_CCK_RATE;
1566              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1567                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1568                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1569
1570                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1571                                 le16_to_cpu(txpower.channel),
1572                                 txpower.band,
1573                                 txpower.power[i].tpc.tx_gain,
1574                                 txpower.power[i].tpc.dsp_atten,
1575                                 txpower.power[i].rate);
1576         }
1577
1578         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1579                                 sizeof(struct iwl3945_txpowertable_cmd),
1580                                 &txpower);
1581
1582 }
1583
1584 /**
1585  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1586  * @ch_info: Channel to update.  Uses power_info.requested_power.
1587  *
1588  * Replace requested_power and base_power_index ch_info fields for
1589  * one channel.
1590  *
1591  * Called if user or spectrum management changes power preferences.
1592  * Takes into account h/w and modulation limitations (clip power).
1593  *
1594  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1595  *
1596  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1597  *       properly fill out the scan powers, and actual h/w gain settings,
1598  *       and send changes to NIC
1599  */
1600 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1601                              struct iwl_channel_info *ch_info)
1602 {
1603         struct iwl3945_channel_power_info *power_info;
1604         int power_changed = 0;
1605         int i;
1606         const s8 *clip_pwrs;
1607         int power;
1608
1609         /* Get this chnlgrp's rate-to-max/clip-powers table */
1610         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1611
1612         /* Get this channel's rate-to-current-power settings table */
1613         power_info = ch_info->power_info;
1614
1615         /* update OFDM Txpower settings */
1616         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1617              i++, ++power_info) {
1618                 int delta_idx;
1619
1620                 /* limit new power to be no more than h/w capability */
1621                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1622                 if (power == power_info->requested_power)
1623                         continue;
1624
1625                 /* find difference between old and new requested powers,
1626                  *    update base (non-temp-compensated) power index */
1627                 delta_idx = (power - power_info->requested_power) * 2;
1628                 power_info->base_power_index -= delta_idx;
1629
1630                 /* save new requested power value */
1631                 power_info->requested_power = power;
1632
1633                 power_changed = 1;
1634         }
1635
1636         /* update CCK Txpower settings, based on OFDM 12M setting ...
1637          *    ... all CCK power settings for a given channel are the *same*. */
1638         if (power_changed) {
1639                 power =
1640                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1641                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1642
1643                 /* do all CCK rates' iwl3945_channel_power_info structures */
1644                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1645                         power_info->requested_power = power;
1646                         power_info->base_power_index =
1647                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1648                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1649                         ++power_info;
1650                 }
1651         }
1652
1653         return 0;
1654 }
1655
1656 /**
1657  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1658  *
1659  * NOTE: Returned power limit may be less (but not more) than requested,
1660  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1661  *       (no consideration for h/w clipping limitations).
1662  */
1663 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1664 {
1665         s8 max_power;
1666
1667 #if 0
1668         /* if we're using TGd limits, use lower of TGd or EEPROM */
1669         if (ch_info->tgd_data.max_power != 0)
1670                 max_power = min(ch_info->tgd_data.max_power,
1671                                 ch_info->eeprom.max_power_avg);
1672
1673         /* else just use EEPROM limits */
1674         else
1675 #endif
1676                 max_power = ch_info->eeprom.max_power_avg;
1677
1678         return min(max_power, ch_info->max_power_avg);
1679 }
1680
1681 /**
1682  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1683  *
1684  * Compensate txpower settings of *all* channels for temperature.
1685  * This only accounts for the difference between current temperature
1686  *   and the factory calibration temperatures, and bases the new settings
1687  *   on the channel's base_power_index.
1688  *
1689  * If RxOn is "associated", this sends the new Txpower to NIC!
1690  */
1691 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1692 {
1693         struct iwl_channel_info *ch_info = NULL;
1694         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1695         int delta_index;
1696         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1697         u8 a_band;
1698         u8 rate_index;
1699         u8 scan_tbl_index;
1700         u8 i;
1701         int ref_temp;
1702         int temperature = priv->temperature;
1703
1704         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1705         for (i = 0; i < priv->channel_count; i++) {
1706                 ch_info = &priv->channel_info[i];
1707                 a_band = is_channel_a_band(ch_info);
1708
1709                 /* Get this chnlgrp's factory calibration temperature */
1710                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1711                     temperature;
1712
1713                 /* get power index adjustment based on current and factory
1714                  * temps */
1715                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1716                                                               ref_temp);
1717
1718                 /* set tx power value for all rates, OFDM and CCK */
1719                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1720                      rate_index++) {
1721                         int power_idx =
1722                             ch_info->power_info[rate_index].base_power_index;
1723
1724                         /* temperature compensate */
1725                         power_idx += delta_index;
1726
1727                         /* stay within table range */
1728                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1729                         ch_info->power_info[rate_index].
1730                             power_table_index = (u8) power_idx;
1731                         ch_info->power_info[rate_index].tpc =
1732                             power_gain_table[a_band][power_idx];
1733                 }
1734
1735                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1736                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1737
1738                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1739                 for (scan_tbl_index = 0;
1740                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1741                         s32 actual_index = (scan_tbl_index == 0) ?
1742                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1743                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1744                                            actual_index, clip_pwrs,
1745                                            ch_info, a_band);
1746                 }
1747         }
1748
1749         /* send Txpower command for current channel to ucode */
1750         return priv->cfg->ops->lib->send_tx_power(priv);
1751 }
1752
1753 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1754 {
1755         struct iwl_channel_info *ch_info;
1756         s8 max_power;
1757         u8 a_band;
1758         u8 i;
1759
1760         if (priv->tx_power_user_lmt == power) {
1761                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1762                                 "limit: %ddBm.\n", power);
1763                 return 0;
1764         }
1765
1766         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1767         priv->tx_power_user_lmt = power;
1768
1769         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1770
1771         for (i = 0; i < priv->channel_count; i++) {
1772                 ch_info = &priv->channel_info[i];
1773                 a_band = is_channel_a_band(ch_info);
1774
1775                 /* find minimum power of all user and regulatory constraints
1776                  *    (does not consider h/w clipping limitations) */
1777                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1778                 max_power = min(power, max_power);
1779                 if (max_power != ch_info->curr_txpow) {
1780                         ch_info->curr_txpow = max_power;
1781
1782                         /* this considers the h/w clipping limitations */
1783                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1784                 }
1785         }
1786
1787         /* update txpower settings for all channels,
1788          *   send to NIC if associated. */
1789         is_temp_calib_needed(priv);
1790         iwl3945_hw_reg_comp_txpower_temp(priv);
1791
1792         return 0;
1793 }
1794
1795 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1796 {
1797         int rc = 0;
1798         struct iwl_rx_packet *pkt;
1799         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1800         struct iwl_host_cmd cmd = {
1801                 .id = REPLY_RXON_ASSOC,
1802                 .len = sizeof(rxon_assoc),
1803                 .flags = CMD_WANT_SKB,
1804                 .data = &rxon_assoc,
1805         };
1806         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1807         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1808
1809         if ((rxon1->flags == rxon2->flags) &&
1810             (rxon1->filter_flags == rxon2->filter_flags) &&
1811             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1812             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1813                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1814                 return 0;
1815         }
1816
1817         rxon_assoc.flags = priv->staging_rxon.flags;
1818         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1819         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1820         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1821         rxon_assoc.reserved = 0;
1822
1823         rc = iwl_send_cmd_sync(priv, &cmd);
1824         if (rc)
1825                 return rc;
1826
1827         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1828         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1829                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1830                 rc = -EIO;
1831         }
1832
1833         iwl_free_pages(priv, cmd.reply_page);
1834
1835         return rc;
1836 }
1837
1838 /**
1839  * iwl3945_commit_rxon - commit staging_rxon to hardware
1840  *
1841  * The RXON command in staging_rxon is committed to the hardware and
1842  * the active_rxon structure is updated with the new data.  This
1843  * function correctly transitions out of the RXON_ASSOC_MSK state if
1844  * a HW tune is required based on the RXON structure changes.
1845  */
1846 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1847 {
1848         /* cast away the const for active_rxon in this function */
1849         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1850         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1851         int rc = 0;
1852         bool new_assoc =
1853                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1854
1855         if (!iwl_is_alive(priv))
1856                 return -1;
1857
1858         /* always get timestamp with Rx frame */
1859         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1860
1861         /* select antenna */
1862         staging_rxon->flags &=
1863             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1864         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1865
1866         rc = iwl_check_rxon_cmd(priv);
1867         if (rc) {
1868                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1869                 return -EINVAL;
1870         }
1871
1872         /* If we don't need to send a full RXON, we can use
1873          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1874          * and other flags for the current radio configuration. */
1875         if (!iwl_full_rxon_required(priv)) {
1876                 rc = iwl_send_rxon_assoc(priv);
1877                 if (rc) {
1878                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1879                                   "configuration (%d).\n", rc);
1880                         return rc;
1881                 }
1882
1883                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1884
1885                 return 0;
1886         }
1887
1888         /* If we are currently associated and the new config requires
1889          * an RXON_ASSOC and the new config wants the associated mask enabled,
1890          * we must clear the associated from the active configuration
1891          * before we apply the new config */
1892         if (iwl_is_associated(priv) && new_assoc) {
1893                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1894                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1895
1896                 /*
1897                  * reserved4 and 5 could have been filled by the iwlcore code.
1898                  * Let's clear them before pushing to the 3945.
1899                  */
1900                 active_rxon->reserved4 = 0;
1901                 active_rxon->reserved5 = 0;
1902                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1903                                       sizeof(struct iwl3945_rxon_cmd),
1904                                       &priv->active_rxon);
1905
1906                 /* If the mask clearing failed then we set
1907                  * active_rxon back to what it was previously */
1908                 if (rc) {
1909                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1910                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1911                                   "configuration (%d).\n", rc);
1912                         return rc;
1913                 }
1914                 iwl_clear_ucode_stations(priv, false);
1915                 iwl_restore_stations(priv);
1916         }
1917
1918         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1919                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1920                        "* channel = %d\n"
1921                        "* bssid = %pM\n",
1922                        (new_assoc ? "" : "out"),
1923                        le16_to_cpu(staging_rxon->channel),
1924                        staging_rxon->bssid_addr);
1925
1926         /*
1927          * reserved4 and 5 could have been filled by the iwlcore code.
1928          * Let's clear them before pushing to the 3945.
1929          */
1930         staging_rxon->reserved4 = 0;
1931         staging_rxon->reserved5 = 0;
1932
1933         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1934
1935         /* Apply the new configuration */
1936         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1937                               sizeof(struct iwl3945_rxon_cmd),
1938                               staging_rxon);
1939         if (rc) {
1940                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1941                 return rc;
1942         }
1943
1944         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1945
1946         if (!new_assoc) {
1947                 iwl_clear_ucode_stations(priv, false);
1948                 iwl_restore_stations(priv);
1949         }
1950
1951         /* If we issue a new RXON command which required a tune then we must
1952          * send a new TXPOWER command or we won't be able to Tx any frames */
1953         rc = priv->cfg->ops->lib->send_tx_power(priv);
1954         if (rc) {
1955                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1956                 return rc;
1957         }
1958
1959         /* Init the hardware's rate fallback order based on the band */
1960         rc = iwl3945_init_hw_rate_table(priv);
1961         if (rc) {
1962                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1963                 return -EIO;
1964         }
1965
1966         return 0;
1967 }
1968
1969 /**
1970  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1971  *
1972  * -- reset periodic timer
1973  * -- see if temp has changed enough to warrant re-calibration ... if so:
1974  *     -- correct coeffs for temp (can reset temp timer)
1975  *     -- save this temp as "last",
1976  *     -- send new set of gain settings to NIC
1977  * NOTE:  This should continue working, even when we're not associated,
1978  *   so we can keep our internal table of scan powers current. */
1979 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1980 {
1981         /* This will kick in the "brute force"
1982          * iwl3945_hw_reg_comp_txpower_temp() below */
1983         if (!is_temp_calib_needed(priv))
1984                 goto reschedule;
1985
1986         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1987          * This is based *only* on current temperature,
1988          * ignoring any previous power measurements */
1989         iwl3945_hw_reg_comp_txpower_temp(priv);
1990
1991  reschedule:
1992         queue_delayed_work(priv->workqueue,
1993                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1994 }
1995
1996 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1997 {
1998         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1999                                              _3945.thermal_periodic.work);
2000
2001         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2002                 return;
2003
2004         mutex_lock(&priv->mutex);
2005         iwl3945_reg_txpower_periodic(priv);
2006         mutex_unlock(&priv->mutex);
2007 }
2008
2009 /**
2010  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2011  *                                 for the channel.
2012  *
2013  * This function is used when initializing channel-info structs.
2014  *
2015  * NOTE: These channel groups do *NOT* match the bands above!
2016  *       These channel groups are based on factory-tested channels;
2017  *       on A-band, EEPROM's "group frequency" entries represent the top
2018  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2019  */
2020 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2021                                        const struct iwl_channel_info *ch_info)
2022 {
2023         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2024         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2025         u8 group;
2026         u16 group_index = 0;    /* based on factory calib frequencies */
2027         u8 grp_channel;
2028
2029         /* Find the group index for the channel ... don't use index 1(?) */
2030         if (is_channel_a_band(ch_info)) {
2031                 for (group = 1; group < 5; group++) {
2032                         grp_channel = ch_grp[group].group_channel;
2033                         if (ch_info->channel <= grp_channel) {
2034                                 group_index = group;
2035                                 break;
2036                         }
2037                 }
2038                 /* group 4 has a few channels *above* its factory cal freq */
2039                 if (group == 5)
2040                         group_index = 4;
2041         } else
2042                 group_index = 0;        /* 2.4 GHz, group 0 */
2043
2044         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2045                         group_index);
2046         return group_index;
2047 }
2048
2049 /**
2050  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2051  *
2052  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2053  *   into radio/DSP gain settings table for requested power.
2054  */
2055 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2056                                        s8 requested_power,
2057                                        s32 setting_index, s32 *new_index)
2058 {
2059         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2060         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2061         s32 index0, index1;
2062         s32 power = 2 * requested_power;
2063         s32 i;
2064         const struct iwl3945_eeprom_txpower_sample *samples;
2065         s32 gains0, gains1;
2066         s32 res;
2067         s32 denominator;
2068
2069         chnl_grp = &eeprom->groups[setting_index];
2070         samples = chnl_grp->samples;
2071         for (i = 0; i < 5; i++) {
2072                 if (power == samples[i].power) {
2073                         *new_index = samples[i].gain_index;
2074                         return 0;
2075                 }
2076         }
2077
2078         if (power > samples[1].power) {
2079                 index0 = 0;
2080                 index1 = 1;
2081         } else if (power > samples[2].power) {
2082                 index0 = 1;
2083                 index1 = 2;
2084         } else if (power > samples[3].power) {
2085                 index0 = 2;
2086                 index1 = 3;
2087         } else {
2088                 index0 = 3;
2089                 index1 = 4;
2090         }
2091
2092         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2093         if (denominator == 0)
2094                 return -EINVAL;
2095         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2096         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2097         res = gains0 + (gains1 - gains0) *
2098             ((s32) power - (s32) samples[index0].power) / denominator +
2099             (1 << 18);
2100         *new_index = res >> 19;
2101         return 0;
2102 }
2103
2104 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2105 {
2106         u32 i;
2107         s32 rate_index;
2108         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2109         const struct iwl3945_eeprom_txpower_group *group;
2110
2111         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2112
2113         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2114                 s8 *clip_pwrs;  /* table of power levels for each rate */
2115                 s8 satur_pwr;   /* saturation power for each chnl group */
2116                 group = &eeprom->groups[i];
2117
2118                 /* sanity check on factory saturation power value */
2119                 if (group->saturation_power < 40) {
2120                         IWL_WARN(priv, "Error: saturation power is %d, "
2121                                     "less than minimum expected 40\n",
2122                                     group->saturation_power);
2123                         return;
2124                 }
2125
2126                 /*
2127                  * Derive requested power levels for each rate, based on
2128                  *   hardware capabilities (saturation power for band).
2129                  * Basic value is 3dB down from saturation, with further
2130                  *   power reductions for highest 3 data rates.  These
2131                  *   backoffs provide headroom for high rate modulation
2132                  *   power peaks, without too much distortion (clipping).
2133                  */
2134                 /* we'll fill in this array with h/w max power levels */
2135                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2136
2137                 /* divide factory saturation power by 2 to find -3dB level */
2138                 satur_pwr = (s8) (group->saturation_power >> 1);
2139
2140                 /* fill in channel group's nominal powers for each rate */
2141                 for (rate_index = 0;
2142                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2143                         switch (rate_index) {
2144                         case IWL_RATE_36M_INDEX_TABLE:
2145                                 if (i == 0)     /* B/G */
2146                                         *clip_pwrs = satur_pwr;
2147                                 else    /* A */
2148                                         *clip_pwrs = satur_pwr - 5;
2149                                 break;
2150                         case IWL_RATE_48M_INDEX_TABLE:
2151                                 if (i == 0)
2152                                         *clip_pwrs = satur_pwr - 7;
2153                                 else
2154                                         *clip_pwrs = satur_pwr - 10;
2155                                 break;
2156                         case IWL_RATE_54M_INDEX_TABLE:
2157                                 if (i == 0)
2158                                         *clip_pwrs = satur_pwr - 9;
2159                                 else
2160                                         *clip_pwrs = satur_pwr - 12;
2161                                 break;
2162                         default:
2163                                 *clip_pwrs = satur_pwr;
2164                                 break;
2165                         }
2166                 }
2167         }
2168 }
2169
2170 /**
2171  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2172  *
2173  * Second pass (during init) to set up priv->channel_info
2174  *
2175  * Set up Tx-power settings in our channel info database for each VALID
2176  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2177  * and current temperature.
2178  *
2179  * Since this is based on current temperature (at init time), these values may
2180  * not be valid for very long, but it gives us a starting/default point,
2181  * and allows us to active (i.e. using Tx) scan.
2182  *
2183  * This does *not* write values to NIC, just sets up our internal table.
2184  */
2185 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2186 {
2187         struct iwl_channel_info *ch_info = NULL;
2188         struct iwl3945_channel_power_info *pwr_info;
2189         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2190         int delta_index;
2191         u8 rate_index;
2192         u8 scan_tbl_index;
2193         const s8 *clip_pwrs;    /* array of power levels for each rate */
2194         u8 gain, dsp_atten;
2195         s8 power;
2196         u8 pwr_index, base_pwr_index, a_band;
2197         u8 i;
2198         int temperature;
2199
2200         /* save temperature reference,
2201          *   so we can determine next time to calibrate */
2202         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2203         priv->last_temperature = temperature;
2204
2205         iwl3945_hw_reg_init_channel_groups(priv);
2206
2207         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2208         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2209              i++, ch_info++) {
2210                 a_band = is_channel_a_band(ch_info);
2211                 if (!is_channel_valid(ch_info))
2212                         continue;
2213
2214                 /* find this channel's channel group (*not* "band") index */
2215                 ch_info->group_index =
2216                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2217
2218                 /* Get this chnlgrp's rate->max/clip-powers table */
2219                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2220
2221                 /* calculate power index *adjustment* value according to
2222                  *  diff between current temperature and factory temperature */
2223                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2224                                 eeprom->groups[ch_info->group_index].
2225                                 temperature);
2226
2227                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2228                                 ch_info->channel, delta_index, temperature +
2229                                 IWL_TEMP_CONVERT);
2230
2231                 /* set tx power value for all OFDM rates */
2232                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2233                      rate_index++) {
2234                         s32 uninitialized_var(power_idx);
2235                         int rc;
2236
2237                         /* use channel group's clip-power table,
2238                          *   but don't exceed channel's max power */
2239                         s8 pwr = min(ch_info->max_power_avg,
2240                                      clip_pwrs[rate_index]);
2241
2242                         pwr_info = &ch_info->power_info[rate_index];
2243
2244                         /* get base (i.e. at factory-measured temperature)
2245                          *    power table index for this rate's power */
2246                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2247                                                          ch_info->group_index,
2248                                                          &power_idx);
2249                         if (rc) {
2250                                 IWL_ERR(priv, "Invalid power index\n");
2251                                 return rc;
2252                         }
2253                         pwr_info->base_power_index = (u8) power_idx;
2254
2255                         /* temperature compensate */
2256                         power_idx += delta_index;
2257
2258                         /* stay within range of gain table */
2259                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2260
2261                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2262                         pwr_info->requested_power = pwr;
2263                         pwr_info->power_table_index = (u8) power_idx;
2264                         pwr_info->tpc.tx_gain =
2265                             power_gain_table[a_band][power_idx].tx_gain;
2266                         pwr_info->tpc.dsp_atten =
2267                             power_gain_table[a_band][power_idx].dsp_atten;
2268                 }
2269
2270                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2271                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2272                 power = pwr_info->requested_power +
2273                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2274                 pwr_index = pwr_info->power_table_index +
2275                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2276                 base_pwr_index = pwr_info->base_power_index +
2277                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2278
2279                 /* stay within table range */
2280                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2281                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2282                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2283
2284                 /* fill each CCK rate's iwl3945_channel_power_info structure
2285                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2286                  * NOTE:  CCK rates start at end of OFDM rates! */
2287                 for (rate_index = 0;
2288                      rate_index < IWL_CCK_RATES; rate_index++) {
2289                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2290                         pwr_info->requested_power = power;
2291                         pwr_info->power_table_index = pwr_index;
2292                         pwr_info->base_power_index = base_pwr_index;
2293                         pwr_info->tpc.tx_gain = gain;
2294                         pwr_info->tpc.dsp_atten = dsp_atten;
2295                 }
2296
2297                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2298                 for (scan_tbl_index = 0;
2299                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2300                         s32 actual_index = (scan_tbl_index == 0) ?
2301                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2302                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2303                                 actual_index, clip_pwrs, ch_info, a_band);
2304                 }
2305         }
2306
2307         return 0;
2308 }
2309
2310 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2311 {
2312         int rc;
2313
2314         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2315         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2316                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2317         if (rc < 0)
2318                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2319
2320         return 0;
2321 }
2322
2323 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2324 {
2325         int txq_id = txq->q.id;
2326
2327         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2328
2329         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2330
2331         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2332         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2333
2334         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2335                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2336                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2337                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2338                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2339                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2340
2341         /* fake read to flush all prev. writes */
2342         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2343
2344         return 0;
2345 }
2346
2347 /*
2348  * HCMD utils
2349  */
2350 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2351 {
2352         switch (cmd_id) {
2353         case REPLY_RXON:
2354                 return sizeof(struct iwl3945_rxon_cmd);
2355         case POWER_TABLE_CMD:
2356                 return sizeof(struct iwl3945_powertable_cmd);
2357         default:
2358                 return len;
2359         }
2360 }
2361
2362
2363 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2364 {
2365         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2366         addsta->mode = cmd->mode;
2367         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2368         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2369         addsta->station_flags = cmd->station_flags;
2370         addsta->station_flags_msk = cmd->station_flags_msk;
2371         addsta->tid_disable_tx = cpu_to_le16(0);
2372         addsta->rate_n_flags = cmd->rate_n_flags;
2373         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2374         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2375         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2376
2377         return (u16)sizeof(struct iwl3945_addsta_cmd);
2378 }
2379
2380
2381 /**
2382  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2383  */
2384 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2385 {
2386         int rc, i, index, prev_index;
2387         struct iwl3945_rate_scaling_cmd rate_cmd = {
2388                 .reserved = {0, 0, 0},
2389         };
2390         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2391
2392         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2393                 index = iwl3945_rates[i].table_rs_index;
2394
2395                 table[index].rate_n_flags =
2396                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2397                 table[index].try_cnt = priv->retry_rate;
2398                 prev_index = iwl3945_get_prev_ieee_rate(i);
2399                 table[index].next_rate_index =
2400                                 iwl3945_rates[prev_index].table_rs_index;
2401         }
2402
2403         switch (priv->band) {
2404         case IEEE80211_BAND_5GHZ:
2405                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2406                 /* If one of the following CCK rates is used,
2407                  * have it fall back to the 6M OFDM rate */
2408                 for (i = IWL_RATE_1M_INDEX_TABLE;
2409                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2410                         table[i].next_rate_index =
2411                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2412
2413                 /* Don't fall back to CCK rates */
2414                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2415                                                 IWL_RATE_9M_INDEX_TABLE;
2416
2417                 /* Don't drop out of OFDM rates */
2418                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2419                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2420                 break;
2421
2422         case IEEE80211_BAND_2GHZ:
2423                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2424                 /* If an OFDM rate is used, have it fall back to the
2425                  * 1M CCK rates */
2426
2427                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2428                     iwl_is_associated(priv)) {
2429
2430                         index = IWL_FIRST_CCK_RATE;
2431                         for (i = IWL_RATE_6M_INDEX_TABLE;
2432                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2433                                 table[i].next_rate_index =
2434                                         iwl3945_rates[index].table_rs_index;
2435
2436                         index = IWL_RATE_11M_INDEX_TABLE;
2437                         /* CCK shouldn't fall back to OFDM... */
2438                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2439                 }
2440                 break;
2441
2442         default:
2443                 WARN_ON(1);
2444                 break;
2445         }
2446
2447         /* Update the rate scaling for control frame Tx */
2448         rate_cmd.table_id = 0;
2449         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2450                               &rate_cmd);
2451         if (rc)
2452                 return rc;
2453
2454         /* Update the rate scaling for data frame Tx */
2455         rate_cmd.table_id = 1;
2456         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2457                                 &rate_cmd);
2458 }
2459
2460 /* Called when initializing driver */
2461 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2462 {
2463         memset((void *)&priv->hw_params, 0,
2464                sizeof(struct iwl_hw_params));
2465
2466         priv->_3945.shared_virt =
2467                 dma_alloc_coherent(&priv->pci_dev->dev,
2468                                    sizeof(struct iwl3945_shared),
2469                                    &priv->_3945.shared_phys, GFP_KERNEL);
2470         if (!priv->_3945.shared_virt) {
2471                 IWL_ERR(priv, "failed to allocate pci memory\n");
2472                 mutex_unlock(&priv->mutex);
2473                 return -ENOMEM;
2474         }
2475
2476         /* Assign number of Usable TX queues */
2477         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2478
2479         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2480         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2481         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2482         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2483         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2484         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2485
2486         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2487         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2488
2489         return 0;
2490 }
2491
2492 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2493                           struct iwl3945_frame *frame, u8 rate)
2494 {
2495         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2496         unsigned int frame_size;
2497
2498         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2499         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2500
2501         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2502         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2503
2504         frame_size = iwl3945_fill_beacon_frame(priv,
2505                                 tx_beacon_cmd->frame,
2506                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2507
2508         BUG_ON(frame_size > MAX_MPDU_SIZE);
2509         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2510
2511         tx_beacon_cmd->tx.rate = rate;
2512         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2513                                       TX_CMD_FLG_TSF_MSK);
2514
2515         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2516         tx_beacon_cmd->tx.supp_rates[0] =
2517                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2518
2519         tx_beacon_cmd->tx.supp_rates[1] =
2520                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2521
2522         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2523 }
2524
2525 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2526 {
2527         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2528         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2529 }
2530
2531 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2532 {
2533         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2534                           iwl3945_bg_reg_txpower_periodic);
2535 }
2536
2537 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2538 {
2539         cancel_delayed_work(&priv->_3945.thermal_periodic);
2540 }
2541
2542 /* check contents of special bootstrap uCode SRAM */
2543 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2544  {
2545         __le32 *image = priv->ucode_boot.v_addr;
2546         u32 len = priv->ucode_boot.len;
2547         u32 reg;
2548         u32 val;
2549
2550         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2551
2552         /* verify BSM SRAM contents */
2553         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2554         for (reg = BSM_SRAM_LOWER_BOUND;
2555              reg < BSM_SRAM_LOWER_BOUND + len;
2556              reg += sizeof(u32), image++) {
2557                 val = iwl_read_prph(priv, reg);
2558                 if (val != le32_to_cpu(*image)) {
2559                         IWL_ERR(priv, "BSM uCode verification failed at "
2560                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2561                                   BSM_SRAM_LOWER_BOUND,
2562                                   reg - BSM_SRAM_LOWER_BOUND, len,
2563                                   val, le32_to_cpu(*image));
2564                         return -EIO;
2565                 }
2566         }
2567
2568         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2569
2570         return 0;
2571 }
2572
2573
2574 /******************************************************************************
2575  *
2576  * EEPROM related functions
2577  *
2578  ******************************************************************************/
2579
2580 /*
2581  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2582  * embedded controller) as EEPROM reader; each read is a series of pulses
2583  * to/from the EEPROM chip, not a single event, so even reads could conflict
2584  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2585  * simply claims ownership, which should be safe when this function is called
2586  * (i.e. before loading uCode!).
2587  */
2588 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2589 {
2590         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2591         return 0;
2592 }
2593
2594
2595 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2596 {
2597         return;
2598 }
2599
2600  /**
2601   * iwl3945_load_bsm - Load bootstrap instructions
2602   *
2603   * BSM operation:
2604   *
2605   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2606   * in special SRAM that does not power down during RFKILL.  When powering back
2607   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2608   * the bootstrap program into the on-board processor, and starts it.
2609   *
2610   * The bootstrap program loads (via DMA) instructions and data for a new
2611   * program from host DRAM locations indicated by the host driver in the
2612   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2613   * automatically.
2614   *
2615   * When initializing the NIC, the host driver points the BSM to the
2616   * "initialize" uCode image.  This uCode sets up some internal data, then
2617   * notifies host via "initialize alive" that it is complete.
2618   *
2619   * The host then replaces the BSM_DRAM_* pointer values to point to the
2620   * normal runtime uCode instructions and a backup uCode data cache buffer
2621   * (filled initially with starting data values for the on-board processor),
2622   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2623   * which begins normal operation.
2624   *
2625   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2626   * the backup data cache in DRAM before SRAM is powered down.
2627   *
2628   * When powering back up, the BSM loads the bootstrap program.  This reloads
2629   * the runtime uCode instructions and the backup data cache into SRAM,
2630   * and re-launches the runtime uCode from where it left off.
2631   */
2632 static int iwl3945_load_bsm(struct iwl_priv *priv)
2633 {
2634         __le32 *image = priv->ucode_boot.v_addr;
2635         u32 len = priv->ucode_boot.len;
2636         dma_addr_t pinst;
2637         dma_addr_t pdata;
2638         u32 inst_len;
2639         u32 data_len;
2640         int rc;
2641         int i;
2642         u32 done;
2643         u32 reg_offset;
2644
2645         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2646
2647         /* make sure bootstrap program is no larger than BSM's SRAM size */
2648         if (len > IWL39_MAX_BSM_SIZE)
2649                 return -EINVAL;
2650
2651         /* Tell bootstrap uCode where to find the "Initialize" uCode
2652         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2653         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2654         *        after the "initialize" uCode has run, to point to
2655         *        runtime/protocol instructions and backup data cache. */
2656         pinst = priv->ucode_init.p_addr;
2657         pdata = priv->ucode_init_data.p_addr;
2658         inst_len = priv->ucode_init.len;
2659         data_len = priv->ucode_init_data.len;
2660
2661         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2662         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2663         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2664         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2665
2666         /* Fill BSM memory with bootstrap instructions */
2667         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2668              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2669              reg_offset += sizeof(u32), image++)
2670                 _iwl_write_prph(priv, reg_offset,
2671                                           le32_to_cpu(*image));
2672
2673         rc = iwl3945_verify_bsm(priv);
2674         if (rc)
2675                 return rc;
2676
2677         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2678         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2679         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2680                                  IWL39_RTC_INST_LOWER_BOUND);
2681         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2682
2683         /* Load bootstrap code into instruction SRAM now,
2684          *   to prepare to load "initialize" uCode */
2685         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2686                 BSM_WR_CTRL_REG_BIT_START);
2687
2688         /* Wait for load of bootstrap uCode to finish */
2689         for (i = 0; i < 100; i++) {
2690                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2691                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2692                         break;
2693                 udelay(10);
2694         }
2695         if (i < 100)
2696                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2697         else {
2698                 IWL_ERR(priv, "BSM write did not complete!\n");
2699                 return -EIO;
2700         }
2701
2702         /* Enable future boot loads whenever power management unit triggers it
2703          *   (e.g. when powering back up after power-save shutdown) */
2704         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2705                 BSM_WR_CTRL_REG_BIT_START_EN);
2706
2707         return 0;
2708 }
2709
2710 #define IWL3945_UCODE_GET(item)                                         \
2711 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2712                                     u32 api_ver)                        \
2713 {                                                                       \
2714         return le32_to_cpu(ucode->u.v1.item);                           \
2715 }
2716
2717 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2718 {
2719         return UCODE_HEADER_SIZE(1);
2720 }
2721 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2722                                    u32 api_ver)
2723 {
2724         return 0;
2725 }
2726 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2727                                   u32 api_ver)
2728 {
2729         return (u8 *) ucode->u.v1.data;
2730 }
2731
2732 IWL3945_UCODE_GET(inst_size);
2733 IWL3945_UCODE_GET(data_size);
2734 IWL3945_UCODE_GET(init_size);
2735 IWL3945_UCODE_GET(init_data_size);
2736 IWL3945_UCODE_GET(boot_size);
2737
2738 static struct iwl_hcmd_ops iwl3945_hcmd = {
2739         .rxon_assoc = iwl3945_send_rxon_assoc,
2740         .commit_rxon = iwl3945_commit_rxon,
2741 };
2742
2743 static struct iwl_ucode_ops iwl3945_ucode = {
2744         .get_header_size = iwl3945_ucode_get_header_size,
2745         .get_build = iwl3945_ucode_get_build,
2746         .get_inst_size = iwl3945_ucode_get_inst_size,
2747         .get_data_size = iwl3945_ucode_get_data_size,
2748         .get_init_size = iwl3945_ucode_get_init_size,
2749         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2750         .get_boot_size = iwl3945_ucode_get_boot_size,
2751         .get_data = iwl3945_ucode_get_data,
2752 };
2753
2754 static struct iwl_lib_ops iwl3945_lib = {
2755         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2756         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2757         .txq_init = iwl3945_hw_tx_queue_init,
2758         .load_ucode = iwl3945_load_bsm,
2759         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2760         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2761         .apm_ops = {
2762                 .init = iwl3945_apm_init,
2763                 .stop = iwl_apm_stop,
2764                 .config = iwl3945_nic_config,
2765                 .set_pwr_src = iwl3945_set_pwr_src,
2766         },
2767         .eeprom_ops = {
2768                 .regulatory_bands = {
2769                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2770                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2771                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2772                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2773                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2774                         EEPROM_REGULATORY_BAND_NO_HT40,
2775                         EEPROM_REGULATORY_BAND_NO_HT40,
2776                 },
2777                 .verify_signature  = iwlcore_eeprom_verify_signature,
2778                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2779                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2780                 .query_addr = iwlcore_eeprom_query_addr,
2781         },
2782         .send_tx_power  = iwl3945_send_tx_power,
2783         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2784         .post_associate = iwl3945_post_associate,
2785         .isr = iwl_isr_legacy,
2786         .config_ap = iwl3945_config_ap,
2787         .add_bcast_station = iwl3945_add_bcast_station,
2788 };
2789
2790 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2791         .get_hcmd_size = iwl3945_get_hcmd_size,
2792         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2793         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2794 };
2795
2796 static const struct iwl_ops iwl3945_ops = {
2797         .ucode = &iwl3945_ucode,
2798         .lib = &iwl3945_lib,
2799         .hcmd = &iwl3945_hcmd,
2800         .utils = &iwl3945_hcmd_utils,
2801         .led = &iwl3945_led_ops,
2802 };
2803
2804 static struct iwl_cfg iwl3945_bg_cfg = {
2805         .name = "3945BG",
2806         .fw_name_pre = IWL3945_FW_PRE,
2807         .ucode_api_max = IWL3945_UCODE_API_MAX,
2808         .ucode_api_min = IWL3945_UCODE_API_MIN,
2809         .sku = IWL_SKU_G,
2810         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2811         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2812         .ops = &iwl3945_ops,
2813         .num_of_queues = IWL39_NUM_QUEUES,
2814         .mod_params = &iwl3945_mod_params,
2815         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2816         .set_l0s = false,
2817         .use_bsm = true,
2818         .use_isr_legacy = true,
2819         .ht_greenfield_support = false,
2820         .led_compensation = 64,
2821         .broken_powersave = true,
2822         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2823         .monitor_recover_period = IWL_MONITORING_PERIOD,
2824 };
2825
2826 static struct iwl_cfg iwl3945_abg_cfg = {
2827         .name = "3945ABG",
2828         .fw_name_pre = IWL3945_FW_PRE,
2829         .ucode_api_max = IWL3945_UCODE_API_MAX,
2830         .ucode_api_min = IWL3945_UCODE_API_MIN,
2831         .sku = IWL_SKU_A|IWL_SKU_G,
2832         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2833         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2834         .ops = &iwl3945_ops,
2835         .num_of_queues = IWL39_NUM_QUEUES,
2836         .mod_params = &iwl3945_mod_params,
2837         .use_isr_legacy = true,
2838         .ht_greenfield_support = false,
2839         .led_compensation = 64,
2840         .broken_powersave = true,
2841         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2842         .monitor_recover_period = IWL_MONITORING_PERIOD,
2843 };
2844
2845 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2846         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2847         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2848         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2849         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2850         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2851         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2852         {0}
2853 };
2854
2855 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);