1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
38 #include <linux/uaccess.h>
40 #define MII_MARVELL_PHY_PAGE 22
41 #define MII_MARVELL_COPPER_PAGE 0x00
42 #define MII_MARVELL_FIBER_PAGE 0x01
43 #define MII_MARVELL_MSCR_PAGE 0x02
44 #define MII_MARVELL_LED_PAGE 0x03
45 #define MII_MARVELL_VCT5_PAGE 0x05
46 #define MII_MARVELL_MISC_TEST_PAGE 0x06
47 #define MII_MARVELL_VCT7_PAGE 0x07
48 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_M1011_IEVENT 0x13
51 #define MII_M1011_IEVENT_CLEAR 0x0000
53 #define MII_M1011_IMASK 0x12
54 #define MII_M1011_IMASK_INIT 0x6400
55 #define MII_M1011_IMASK_CLEAR 0x0000
57 #define MII_M1011_PHY_SCR 0x10
58 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
59 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
61 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
62 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
63 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
65 #define MII_M1011_PHY_SSR 0x11
66 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
73 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
75 #define MII_M1111_RGMII_RX_DELAY BIT(7)
76 #define MII_M1111_RGMII_TX_DELAY BIT(1)
77 #define MII_M1111_PHY_EXT_SR 0x1b
79 #define MII_M1111_HWCFG_MODE_MASK 0xf
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_RTBI 0x7
83 #define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
84 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
85 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
86 #define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
87 #define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
88 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
89 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
91 #define MII_88E1121_PHY_MSCR_REG 21
92 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
93 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
94 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
96 #define MII_88E1121_MISC_TEST 0x1a
97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
98 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
99 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
100 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
101 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
102 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
104 #define MII_88E1510_TEMP_SENSOR 0x1b
105 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
107 #define MII_88E1540_COPPER_CTRL3 0x1a
108 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
109 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
110 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
111 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
112 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
113 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
115 #define MII_88E6390_MISC_TEST 0x1b
116 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
117 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
118 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
119 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
120 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
121 #define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
122 #define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
123 #define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
124 #define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
125 #define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
126 #define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
127 #define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
128 #define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
129 #define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
131 #define MII_88E6390_TEMP_SENSOR 0x1c
132 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
133 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
134 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
135 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
137 #define MII_88E1318S_PHY_MSCR1_REG 16
138 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
140 /* Copper Specific Interrupt Enable Register */
141 #define MII_88E1318S_PHY_CSIER 0x12
142 /* WOL Event Interrupt Enable */
143 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
145 /* LED Timer Control Register */
146 #define MII_88E1318S_PHY_LED_TCR 0x12
147 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
148 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
149 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
151 /* Magic Packet MAC address registers */
152 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
153 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
154 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
156 #define MII_88E1318S_PHY_WOL_CTRL 0x10
157 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
158 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
160 #define MII_PHY_LED_CTRL 16
161 #define MII_88E1121_PHY_LED_DEF 0x0030
162 #define MII_88E1510_PHY_LED_DEF 0x1177
163 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
165 #define MII_M1011_PHY_STATUS 0x11
166 #define MII_M1011_PHY_STATUS_1000 0x8000
167 #define MII_M1011_PHY_STATUS_100 0x4000
168 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
169 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
170 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
171 #define MII_M1011_PHY_STATUS_LINK 0x0400
173 #define MII_88E3016_PHY_SPEC_CTRL 0x10
174 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
175 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
177 #define MII_88E1510_GEN_CTRL_REG_1 0x14
178 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
179 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
180 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
182 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
183 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
184 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
185 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
186 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
187 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
188 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
190 #define MII_VCT5_CTRL 0x17
191 #define MII_VCT5_CTRL_ENABLE BIT(15)
192 #define MII_VCT5_CTRL_COMPLETE BIT(14)
193 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
194 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
195 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
196 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
197 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
198 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
199 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
200 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
201 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
202 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
203 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
204 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
205 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
206 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
207 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
208 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
209 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
210 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
211 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
212 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
214 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
215 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
216 #define MII_VCT5_TX_PULSE_CTRL 0x1c
217 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
218 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
219 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
220 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
221 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
222 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
223 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
224 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
225 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
226 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
227 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
228 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
229 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
231 /* For TDR measurements less than 11 meters, a short pulse should be
234 #define TDR_SHORT_CABLE_LENGTH 11
236 #define MII_VCT7_PAIR_0_DISTANCE 0x10
237 #define MII_VCT7_PAIR_1_DISTANCE 0x11
238 #define MII_VCT7_PAIR_2_DISTANCE 0x12
239 #define MII_VCT7_PAIR_3_DISTANCE 0x13
241 #define MII_VCT7_RESULTS 0x14
242 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
243 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
244 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
245 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
246 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
247 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
248 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
249 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
250 #define MII_VCT7_RESULTS_INVALID 0
251 #define MII_VCT7_RESULTS_OK 1
252 #define MII_VCT7_RESULTS_OPEN 2
253 #define MII_VCT7_RESULTS_SAME_SHORT 3
254 #define MII_VCT7_RESULTS_CROSS_SHORT 4
255 #define MII_VCT7_RESULTS_BUSY 9
257 #define MII_VCT7_CTRL 0x15
258 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
259 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
260 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
261 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
262 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
263 #define MII_VCT7_CTRL_METERS BIT(10)
264 #define MII_VCT7_CTRL_CENTIMETERS 0
266 #define LPA_PAUSE_FIBER 0x180
267 #define LPA_PAUSE_ASYM_FIBER 0x100
269 #define NB_FIBER_STATS 1
271 MODULE_DESCRIPTION("Marvell PHY driver");
272 MODULE_AUTHOR("Andy Fleming");
273 MODULE_LICENSE("GPL");
275 struct marvell_hw_stat {
282 static struct marvell_hw_stat marvell_hw_stats[] = {
283 { "phy_receive_errors_copper", 0, 21, 16},
284 { "phy_idle_errors", 0, 10, 8 },
285 { "phy_receive_errors_fiber", 1, 21, 16},
288 struct marvell_priv {
289 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
291 struct device *hwmon_dev;
299 static int marvell_read_page(struct phy_device *phydev)
301 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
304 static int marvell_write_page(struct phy_device *phydev, int page)
306 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
309 static int marvell_set_page(struct phy_device *phydev, int page)
311 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
314 static int marvell_ack_interrupt(struct phy_device *phydev)
318 /* Clear the interrupts by reading the reg */
319 err = phy_read(phydev, MII_M1011_IEVENT);
327 static int marvell_config_intr(struct phy_device *phydev)
331 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
332 err = marvell_ack_interrupt(phydev);
336 err = phy_write(phydev, MII_M1011_IMASK,
337 MII_M1011_IMASK_INIT);
339 err = phy_write(phydev, MII_M1011_IMASK,
340 MII_M1011_IMASK_CLEAR);
344 err = marvell_ack_interrupt(phydev);
350 static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
354 irq_status = phy_read(phydev, MII_M1011_IEVENT);
355 if (irq_status < 0) {
360 if (!(irq_status & MII_M1011_IMASK_INIT))
363 phy_trigger_machine(phydev);
368 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
374 /* get the current settings */
375 reg = phy_read(phydev, MII_M1011_PHY_SCR);
380 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
383 val |= MII_M1011_PHY_SCR_MDI;
386 val |= MII_M1011_PHY_SCR_MDI_X;
388 case ETH_TP_MDI_AUTO:
389 case ETH_TP_MDI_INVALID:
391 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
396 /* Set the new polarity value in the register */
397 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
405 static int marvell_config_aneg(struct phy_device *phydev)
410 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
416 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
417 MII_M1111_PHY_LED_DIRECT);
421 err = genphy_config_aneg(phydev);
425 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
426 /* A write to speed/duplex bits (that is performed by
427 * genphy_config_aneg() call above) must be followed by
428 * a software reset. Otherwise, the write has no effect.
430 err = genphy_soft_reset(phydev);
438 static int m88e1101_config_aneg(struct phy_device *phydev)
442 /* This Marvell PHY has an errata which requires
443 * that certain registers get written in order
444 * to restart autonegotiation
446 err = genphy_soft_reset(phydev);
450 err = phy_write(phydev, 0x1d, 0x1f);
454 err = phy_write(phydev, 0x1e, 0x200c);
458 err = phy_write(phydev, 0x1d, 0x5);
462 err = phy_write(phydev, 0x1e, 0);
466 err = phy_write(phydev, 0x1e, 0x100);
470 return marvell_config_aneg(phydev);
473 #if IS_ENABLED(CONFIG_OF_MDIO)
474 /* Set and/or override some configuration registers based on the
475 * marvell,reg-init property stored in the of_node for the phydev.
477 * marvell,reg-init = <reg-page reg mask value>,...;
479 * There may be one or more sets of <reg-page reg mask value>:
481 * reg-page: which register bank to use.
483 * mask: if non-zero, ANDed with existing register value.
484 * value: ORed with the masked value and written to the regiser.
487 static int marvell_of_reg_init(struct phy_device *phydev)
490 int len, i, saved_page, current_page, ret = 0;
492 if (!phydev->mdio.dev.of_node)
495 paddr = of_get_property(phydev->mdio.dev.of_node,
496 "marvell,reg-init", &len);
497 if (!paddr || len < (4 * sizeof(*paddr)))
500 saved_page = phy_save_page(phydev);
503 current_page = saved_page;
505 len /= sizeof(*paddr);
506 for (i = 0; i < len - 3; i += 4) {
507 u16 page = be32_to_cpup(paddr + i);
508 u16 reg = be32_to_cpup(paddr + i + 1);
509 u16 mask = be32_to_cpup(paddr + i + 2);
510 u16 val_bits = be32_to_cpup(paddr + i + 3);
513 if (page != current_page) {
515 ret = marvell_write_page(phydev, page);
522 val = __phy_read(phydev, reg);
531 ret = __phy_write(phydev, reg, val);
536 return phy_restore_page(phydev, saved_page, ret);
539 static int marvell_of_reg_init(struct phy_device *phydev)
543 #endif /* CONFIG_OF_MDIO */
545 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
549 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
551 MII_88E1121_PHY_MSCR_TX_DELAY;
552 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
553 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
554 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
555 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
559 return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
560 MII_88E1121_PHY_MSCR_REG,
561 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
564 static int m88e1121_config_aneg(struct phy_device *phydev)
569 if (phy_interface_is_rgmii(phydev)) {
570 err = m88e1121_config_aneg_rgmii_delays(phydev);
575 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
581 err = genphy_config_aneg(phydev);
585 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
586 /* A software reset is used to ensure a "commit" of the
589 err = genphy_soft_reset(phydev);
597 static int m88e1318_config_aneg(struct phy_device *phydev)
601 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
602 MII_88E1318S_PHY_MSCR1_REG,
603 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
607 return m88e1121_config_aneg(phydev);
611 * linkmode_adv_to_fiber_adv_t
612 * @advertise: the linkmode advertisement settings
614 * A small helper function that translates linkmode advertisement
615 * settings to phy autonegotiation advertisements for the MII_ADV
616 * register for fiber link.
618 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
622 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
623 result |= ADVERTISE_1000XHALF;
624 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
625 result |= ADVERTISE_1000XFULL;
627 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
628 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
629 result |= ADVERTISE_1000XPSE_ASYM;
630 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
631 result |= ADVERTISE_1000XPAUSE;
637 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
638 * @phydev: target phy_device struct
640 * Description: If auto-negotiation is enabled, we configure the
641 * advertising, and then restart auto-negotiation. If it is not
642 * enabled, then we write the BMCR. Adapted for fiber link in
643 * some Marvell's devices.
645 static int marvell_config_aneg_fiber(struct phy_device *phydev)
651 if (phydev->autoneg != AUTONEG_ENABLE)
652 return genphy_setup_forced(phydev);
654 /* Only allow advertising what this PHY supports */
655 linkmode_and(phydev->advertising, phydev->advertising,
658 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
660 /* Setup fiber advertisement */
661 err = phy_modify_changed(phydev, MII_ADVERTISE,
662 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
663 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
670 return genphy_check_and_restart_aneg(phydev, changed);
673 static int m88e1111_config_aneg(struct phy_device *phydev)
675 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
681 /* If not using SGMII or copper 1000BaseX modes, use normal process.
682 * Steps below are only required for these modes.
684 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
685 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
686 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
687 return marvell_config_aneg(phydev);
689 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
693 /* Configure the copper link first */
694 err = marvell_config_aneg(phydev);
698 /* Then the fiber link */
699 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
703 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
704 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
705 * Just ensure that SGMII-side autonegotiation is enabled.
706 * If we switched from some other mode to SGMII it may not be.
708 err = genphy_check_and_restart_aneg(phydev, false);
710 err = marvell_config_aneg_fiber(phydev);
714 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
717 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
721 static int m88e1510_config_aneg(struct phy_device *phydev)
725 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
729 /* Configure the copper link first */
730 err = m88e1318_config_aneg(phydev);
734 /* Do not touch the fiber page if we're in copper->sgmii mode */
735 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
738 /* Then the fiber link */
739 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
743 err = marvell_config_aneg_fiber(phydev);
747 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
750 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
754 static void marvell_config_led(struct phy_device *phydev)
759 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
760 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
761 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
762 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
763 def_config = MII_88E1121_PHY_LED_DEF;
765 /* Default PHY LED config:
766 * LED[0] .. 1000Mbps Link
767 * LED[1] .. 100Mbps Link
768 * LED[2] .. Blink, Activity
770 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
771 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
772 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
774 def_config = MII_88E1510_PHY_LED_DEF;
780 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
783 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
786 static int marvell_config_init(struct phy_device *phydev)
788 /* Set default LED */
789 marvell_config_led(phydev);
791 /* Set registers from marvell,reg-init DT property */
792 return marvell_of_reg_init(phydev);
795 static int m88e3016_config_init(struct phy_device *phydev)
799 /* Enable Scrambler and Auto-Crossover */
800 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
801 MII_88E3016_DISABLE_SCRAMBLER,
802 MII_88E3016_AUTO_MDIX_CROSSOVER);
806 return marvell_config_init(phydev);
809 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
811 int fibre_copper_auto)
813 if (fibre_copper_auto)
814 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
816 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
817 MII_M1111_HWCFG_MODE_MASK |
818 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
819 MII_M1111_HWCFG_FIBER_COPPER_RES,
823 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
827 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
828 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
829 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
830 delay = MII_M1111_RGMII_RX_DELAY;
831 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
832 delay = MII_M1111_RGMII_TX_DELAY;
837 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
838 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
842 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
847 err = m88e1111_config_init_rgmii_delays(phydev);
851 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
855 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
857 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
858 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
860 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
862 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
865 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
869 err = m88e1111_config_init_hwcfg_mode(
871 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
872 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
876 /* make sure copper is selected */
877 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
880 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
884 err = m88e1111_config_init_rgmii_delays(phydev);
888 err = m88e1111_config_init_hwcfg_mode(
890 MII_M1111_HWCFG_MODE_RTBI,
891 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
896 err = genphy_soft_reset(phydev);
900 return m88e1111_config_init_hwcfg_mode(
902 MII_M1111_HWCFG_MODE_RTBI,
903 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
906 static int m88e1111_config_init_1000basex(struct phy_device *phydev)
908 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
914 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
915 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
916 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
917 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
918 MII_M1111_HWCFG_MODE_MASK |
919 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
920 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
921 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
928 static int m88e1111_config_init(struct phy_device *phydev)
932 if (phy_interface_is_rgmii(phydev)) {
933 err = m88e1111_config_init_rgmii(phydev);
938 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
939 err = m88e1111_config_init_sgmii(phydev);
944 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
945 err = m88e1111_config_init_rtbi(phydev);
950 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
951 err = m88e1111_config_init_1000basex(phydev);
956 err = marvell_of_reg_init(phydev);
960 return genphy_soft_reset(phydev);
963 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
965 int val, cnt, enable;
967 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
971 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
972 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
974 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
979 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
983 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
987 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
988 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
990 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
991 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
993 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
994 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
995 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1002 return genphy_soft_reset(phydev);
1005 static int m88e1111_get_tunable(struct phy_device *phydev,
1006 struct ethtool_tunable *tuna, void *data)
1009 case ETHTOOL_PHY_DOWNSHIFT:
1010 return m88e1111_get_downshift(phydev, data);
1016 static int m88e1111_set_tunable(struct phy_device *phydev,
1017 struct ethtool_tunable *tuna, const void *data)
1020 case ETHTOOL_PHY_DOWNSHIFT:
1021 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1027 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1029 int val, cnt, enable;
1031 val = phy_read(phydev, MII_M1011_PHY_SCR);
1035 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1036 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1038 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1043 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1047 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1051 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1052 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1054 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1055 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1057 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1058 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1059 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1066 return genphy_soft_reset(phydev);
1069 static int m88e1011_get_tunable(struct phy_device *phydev,
1070 struct ethtool_tunable *tuna, void *data)
1073 case ETHTOOL_PHY_DOWNSHIFT:
1074 return m88e1011_get_downshift(phydev, data);
1080 static int m88e1011_set_tunable(struct phy_device *phydev,
1081 struct ethtool_tunable *tuna, const void *data)
1084 case ETHTOOL_PHY_DOWNSHIFT:
1085 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1091 static int m88e1112_config_init(struct phy_device *phydev)
1095 err = m88e1011_set_downshift(phydev, 3);
1099 return m88e1111_config_init(phydev);
1102 static int m88e1111gbe_config_init(struct phy_device *phydev)
1106 err = m88e1111_set_downshift(phydev, 3);
1110 return m88e1111_config_init(phydev);
1113 static int marvell_1011gbe_config_init(struct phy_device *phydev)
1117 err = m88e1011_set_downshift(phydev, 3);
1121 return marvell_config_init(phydev);
1123 static int m88e1116r_config_init(struct phy_device *phydev)
1127 err = genphy_soft_reset(phydev);
1133 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1137 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1141 err = m88e1011_set_downshift(phydev, 8);
1145 if (phy_interface_is_rgmii(phydev)) {
1146 err = m88e1121_config_aneg_rgmii_delays(phydev);
1151 err = genphy_soft_reset(phydev);
1155 return marvell_config_init(phydev);
1158 static int m88e1318_config_init(struct phy_device *phydev)
1160 if (phy_interrupt_is_valid(phydev)) {
1161 int err = phy_modify_paged(
1162 phydev, MII_MARVELL_LED_PAGE,
1163 MII_88E1318S_PHY_LED_TCR,
1164 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1165 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1166 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1171 return marvell_config_init(phydev);
1174 static int m88e1510_config_init(struct phy_device *phydev)
1178 /* SGMII-to-Copper mode initialization */
1179 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1180 /* Select page 18 */
1181 err = marvell_set_page(phydev, 18);
1185 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1186 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1187 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1188 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1192 /* PHY reset is necessary after changing MODE[2:0] */
1193 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1194 MII_88E1510_GEN_CTRL_REG_1_RESET);
1198 /* Reset page selection */
1199 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1203 err = m88e1011_set_downshift(phydev, 3);
1207 return m88e1318_config_init(phydev);
1210 static int m88e1118_config_aneg(struct phy_device *phydev)
1214 err = genphy_soft_reset(phydev);
1218 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1222 err = genphy_config_aneg(phydev);
1226 static int m88e1118_config_init(struct phy_device *phydev)
1230 /* Change address */
1231 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1235 /* Enable 1000 Mbit */
1236 err = phy_write(phydev, 0x15, 0x1070);
1240 /* Change address */
1241 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1245 /* Adjust LED Control */
1246 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1247 err = phy_write(phydev, 0x10, 0x1100);
1249 err = phy_write(phydev, 0x10, 0x021e);
1253 err = marvell_of_reg_init(phydev);
1258 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1262 return genphy_soft_reset(phydev);
1265 static int m88e1149_config_init(struct phy_device *phydev)
1269 /* Change address */
1270 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1274 /* Enable 1000 Mbit */
1275 err = phy_write(phydev, 0x15, 0x1048);
1279 err = marvell_of_reg_init(phydev);
1284 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1288 return genphy_soft_reset(phydev);
1291 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1295 err = m88e1111_config_init_rgmii_delays(phydev);
1299 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1300 err = phy_write(phydev, 0x1d, 0x0012);
1304 err = phy_modify(phydev, 0x1e, 0x0fc0,
1305 2 << 9 | /* 36 ohm */
1306 2 << 6); /* 39 ohm */
1310 err = phy_write(phydev, 0x1d, 0x3);
1314 err = phy_write(phydev, 0x1e, 0x8000);
1319 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1321 return m88e1111_config_init_hwcfg_mode(
1322 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1323 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1326 static int m88e1145_config_init(struct phy_device *phydev)
1330 /* Take care of errata E0 & E1 */
1331 err = phy_write(phydev, 0x1d, 0x001b);
1335 err = phy_write(phydev, 0x1e, 0x418f);
1339 err = phy_write(phydev, 0x1d, 0x0016);
1343 err = phy_write(phydev, 0x1e, 0xa2da);
1347 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1348 err = m88e1145_config_init_rgmii(phydev);
1353 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1354 err = m88e1145_config_init_sgmii(phydev);
1358 err = m88e1111_set_downshift(phydev, 3);
1362 err = marvell_of_reg_init(phydev);
1369 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1373 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1377 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1378 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1382 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1385 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1388 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1391 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1394 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1404 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1406 struct ethtool_eee eee;
1409 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1410 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1411 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1413 /* According to the Marvell data sheet EEE must be disabled for
1414 * Fast Link Down detection to work properly
1416 ret = phy_ethtool_get_eee(phydev, &eee);
1417 if (!ret && eee.eee_enabled) {
1418 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1423 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1424 else if (*msecs <= 15)
1425 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1426 else if (*msecs <= 30)
1427 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1429 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1431 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1433 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1434 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1438 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1439 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1442 static int m88e1540_get_tunable(struct phy_device *phydev,
1443 struct ethtool_tunable *tuna, void *data)
1446 case ETHTOOL_PHY_FAST_LINK_DOWN:
1447 return m88e1540_get_fld(phydev, data);
1448 case ETHTOOL_PHY_DOWNSHIFT:
1449 return m88e1011_get_downshift(phydev, data);
1455 static int m88e1540_set_tunable(struct phy_device *phydev,
1456 struct ethtool_tunable *tuna, const void *data)
1459 case ETHTOOL_PHY_FAST_LINK_DOWN:
1460 return m88e1540_set_fld(phydev, data);
1461 case ETHTOOL_PHY_DOWNSHIFT:
1462 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1468 /* The VOD can be out of specification on link up. Poke an
1469 * undocumented register, in an undocumented page, with a magic value
1472 static int m88e6390_errata(struct phy_device *phydev)
1476 err = phy_write(phydev, MII_BMCR,
1477 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1481 usleep_range(300, 400);
1483 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1487 return genphy_soft_reset(phydev);
1490 static int m88e6390_config_aneg(struct phy_device *phydev)
1494 err = m88e6390_errata(phydev);
1498 return m88e1510_config_aneg(phydev);
1502 * fiber_lpa_mod_linkmode_lpa_t
1503 * @advertising: the linkmode advertisement settings
1504 * @lpa: value of the MII_LPA register for fiber link
1506 * A small helper function that translates MII_LPA bits to linkmode LP
1507 * advertisement settings. Other bits in advertising are left
1510 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1512 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1513 advertising, lpa & LPA_1000XHALF);
1515 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1516 advertising, lpa & LPA_1000XFULL);
1519 static int marvell_read_status_page_an(struct phy_device *phydev,
1520 int fiber, int status)
1525 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1530 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1531 phydev->duplex = DUPLEX_FULL;
1533 phydev->duplex = DUPLEX_HALF;
1535 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1536 case MII_M1011_PHY_STATUS_1000:
1537 phydev->speed = SPEED_1000;
1540 case MII_M1011_PHY_STATUS_100:
1541 phydev->speed = SPEED_100;
1545 phydev->speed = SPEED_10;
1550 err = genphy_read_lpa(phydev);
1554 phy_resolve_aneg_pause(phydev);
1556 lpa = phy_read(phydev, MII_LPA);
1560 /* The fiber link is only 1000M capable */
1561 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1563 if (phydev->duplex == DUPLEX_FULL) {
1564 if (!(lpa & LPA_PAUSE_FIBER)) {
1566 phydev->asym_pause = 0;
1567 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1569 phydev->asym_pause = 1;
1572 phydev->asym_pause = 0;
1580 /* marvell_read_status_page
1583 * Check the link, then figure out the current state
1584 * by comparing what we advertise with what the link partner
1585 * advertises. Start by checking the gigabit possibilities,
1586 * then move on to 10/100.
1588 static int marvell_read_status_page(struct phy_device *phydev, int page)
1594 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1598 /* Use the generic register for copper link status,
1599 * and the PHY status register for fiber link status.
1601 if (page == MII_MARVELL_FIBER_PAGE) {
1602 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1604 err = genphy_update_link(phydev);
1609 if (page == MII_MARVELL_FIBER_PAGE)
1614 linkmode_zero(phydev->lp_advertising);
1616 phydev->asym_pause = 0;
1617 phydev->speed = SPEED_UNKNOWN;
1618 phydev->duplex = DUPLEX_UNKNOWN;
1619 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1621 if (phydev->autoneg == AUTONEG_ENABLE)
1622 err = marvell_read_status_page_an(phydev, fiber, status);
1624 err = genphy_read_status_fixed(phydev);
1629 /* marvell_read_status
1631 * Some Marvell's phys have two modes: fiber and copper.
1632 * Both need status checked.
1634 * First, check the fiber link and status.
1635 * If the fiber link is down, check the copper link and status which
1636 * will be the default value if both link are down.
1638 static int marvell_read_status(struct phy_device *phydev)
1642 /* Check the fiber mode first */
1643 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1644 phydev->supported) &&
1645 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1646 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1650 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1654 /* If the fiber link is up, it is the selected and
1655 * used link. In this case, we need to stay in the
1656 * fiber page. Please to be careful about that, avoid
1657 * to restore Copper page in other functions which
1658 * could break the behaviour for some fiber phy like
1664 /* If fiber link is down, check and save copper mode state */
1665 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1670 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1673 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1679 * Some Marvell's phys have two modes: fiber and copper.
1680 * Both need to be suspended
1682 static int marvell_suspend(struct phy_device *phydev)
1686 /* Suspend the fiber mode first */
1687 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1688 phydev->supported)) {
1689 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1693 /* With the page set, use the generic suspend */
1694 err = genphy_suspend(phydev);
1698 /* Then, the copper link */
1699 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1704 /* With the page set, use the generic suspend */
1705 return genphy_suspend(phydev);
1708 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1714 * Some Marvell's phys have two modes: fiber and copper.
1715 * Both need to be resumed
1717 static int marvell_resume(struct phy_device *phydev)
1721 /* Resume the fiber mode first */
1722 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1723 phydev->supported)) {
1724 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1728 /* With the page set, use the generic resume */
1729 err = genphy_resume(phydev);
1733 /* Then, the copper link */
1734 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1739 /* With the page set, use the generic resume */
1740 return genphy_resume(phydev);
1743 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1747 static int marvell_aneg_done(struct phy_device *phydev)
1749 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1751 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1754 static void m88e1318_get_wol(struct phy_device *phydev,
1755 struct ethtool_wolinfo *wol)
1759 wol->supported = WAKE_MAGIC;
1762 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1763 MII_88E1318S_PHY_WOL_CTRL);
1764 if (ret >= 0 && ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1765 wol->wolopts |= WAKE_MAGIC;
1768 static int m88e1318_set_wol(struct phy_device *phydev,
1769 struct ethtool_wolinfo *wol)
1771 int err = 0, oldpage;
1773 oldpage = phy_save_page(phydev);
1777 if (wol->wolopts & WAKE_MAGIC) {
1778 /* Explicitly switch to page 0x00, just to be sure */
1779 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1783 /* If WOL event happened once, the LED[2] interrupt pin
1784 * will not be cleared unless we reading the interrupt status
1785 * register. If interrupts are in use, the normal interrupt
1786 * handling will clear the WOL event. Clear the WOL event
1787 * before enabling it if !phy_interrupt_is_valid()
1789 if (!phy_interrupt_is_valid(phydev))
1790 __phy_read(phydev, MII_M1011_IEVENT);
1792 /* Enable the WOL interrupt */
1793 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1794 MII_88E1318S_PHY_CSIER_WOL_EIE);
1798 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1802 /* Setup LED[2] as interrupt pin (active low) */
1803 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1804 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1805 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1806 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1810 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1814 /* Store the device address for the magic packet */
1815 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1816 ((phydev->attached_dev->dev_addr[5] << 8) |
1817 phydev->attached_dev->dev_addr[4]));
1820 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1821 ((phydev->attached_dev->dev_addr[3] << 8) |
1822 phydev->attached_dev->dev_addr[2]));
1825 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1826 ((phydev->attached_dev->dev_addr[1] << 8) |
1827 phydev->attached_dev->dev_addr[0]));
1831 /* Clear WOL status and enable magic packet matching */
1832 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1833 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1834 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1838 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1842 /* Clear WOL status and disable magic packet matching */
1843 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1844 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1845 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1851 return phy_restore_page(phydev, oldpage, err);
1854 static int marvell_get_sset_count(struct phy_device *phydev)
1856 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1858 return ARRAY_SIZE(marvell_hw_stats);
1860 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1863 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1865 int count = marvell_get_sset_count(phydev);
1868 for (i = 0; i < count; i++) {
1869 strlcpy(data + i * ETH_GSTRING_LEN,
1870 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1874 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1876 struct marvell_hw_stat stat = marvell_hw_stats[i];
1877 struct marvell_priv *priv = phydev->priv;
1881 val = phy_read_paged(phydev, stat.page, stat.reg);
1885 val = val & ((1 << stat.bits) - 1);
1886 priv->stats[i] += val;
1887 ret = priv->stats[i];
1893 static void marvell_get_stats(struct phy_device *phydev,
1894 struct ethtool_stats *stats, u64 *data)
1896 int count = marvell_get_sset_count(phydev);
1899 for (i = 0; i < count; i++)
1900 data[i] = marvell_get_stat(phydev, i);
1903 static int marvell_vct5_wait_complete(struct phy_device *phydev)
1908 for (i = 0; i < 32; i++) {
1909 val = __phy_read(phydev, MII_VCT5_CTRL);
1913 if (val & MII_VCT5_CTRL_COMPLETE)
1917 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
1921 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
1927 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
1928 val = __phy_read(phydev, reg);
1933 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
1934 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
1936 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
1937 amplitude = -amplitude;
1939 return 1000 * amplitude / 128;
1942 static u32 marvell_vct5_distance2cm(int distance)
1944 return distance * 805 / 10;
1947 static u32 marvell_vct5_cm2distance(int cm)
1949 return cm * 10 / 805;
1952 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
1953 int distance, int pair)
1960 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
1965 reg = MII_VCT5_CTRL_ENABLE |
1966 MII_VCT5_CTRL_TX_SAME_CHANNEL |
1967 MII_VCT5_CTRL_SAMPLES_DEFAULT |
1968 MII_VCT5_CTRL_SAMPLE_POINT |
1969 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
1970 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
1974 err = marvell_vct5_wait_complete(phydev);
1978 for (i = 0; i < 4; i++) {
1979 if (pair != PHY_PAIR_ALL && i != pair)
1982 mV = marvell_vct5_amplitude(phydev, i);
1983 ethnl_cable_test_amplitude(phydev, i, mV);
1989 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
1991 struct marvell_priv *priv = phydev->priv;
1998 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
1999 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2001 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2003 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2004 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2005 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2007 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2008 MII_VCT5_TX_PULSE_CTRL, reg);
2012 /* Reading the TDR data is very MDIO heavy. We need to optimize
2013 * access to keep the time to a minimum. So lock the bus once,
2014 * and don't release it until complete. We can then avoid having
2015 * to change the page for every access, greatly speeding things
2018 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2022 for (distance = priv->first;
2023 distance <= priv->last;
2024 distance += priv->step) {
2025 err = marvell_vct5_amplitude_distance(phydev, distance,
2030 if (distance > TDR_SHORT_CABLE_LENGTH &&
2031 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2032 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2033 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2034 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2035 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2036 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2043 return phy_restore_page(phydev, page, err);
2046 static int marvell_cable_test_start_common(struct phy_device *phydev)
2048 int bmcr, bmsr, ret;
2050 /* If auto-negotiation is enabled, but not complete, the cable
2051 * test never completes. So disable auto-neg.
2053 bmcr = phy_read(phydev, MII_BMCR);
2057 bmsr = phy_read(phydev, MII_BMSR);
2062 if (bmcr & BMCR_ANENABLE) {
2063 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2066 ret = genphy_soft_reset(phydev);
2071 /* If the link is up, allow it some time to go down */
2072 if (bmsr & BMSR_LSTATUS)
2078 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2080 struct marvell_priv *priv = phydev->priv;
2083 ret = marvell_cable_test_start_common(phydev);
2087 priv->cable_test_tdr = false;
2089 /* Reset the VCT5 API control to defaults, otherwise
2090 * VCT7 does not work correctly.
2092 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2094 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2095 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2096 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2097 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2101 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2102 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2106 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2108 MII_VCT7_CTRL_RUN_NOW |
2109 MII_VCT7_CTRL_CENTIMETERS);
2112 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2113 const struct phy_tdr_config *cfg)
2115 struct marvell_priv *priv = phydev->priv;
2118 priv->cable_test_tdr = true;
2119 priv->first = marvell_vct5_cm2distance(cfg->first);
2120 priv->last = marvell_vct5_cm2distance(cfg->last);
2121 priv->step = marvell_vct5_cm2distance(cfg->step);
2122 priv->pair = cfg->pair;
2124 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2127 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2131 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2136 ret = marvell_cable_test_start_common(phydev);
2140 ret = ethnl_cable_test_pulse(phydev, 1000);
2144 return ethnl_cable_test_step(phydev,
2145 marvell_vct5_distance2cm(priv->first),
2146 marvell_vct5_distance2cm(priv->last),
2147 marvell_vct5_distance2cm(priv->step));
2150 static int marvell_vct7_distance_to_length(int distance, bool meter)
2158 static bool marvell_vct7_distance_valid(int result)
2161 case MII_VCT7_RESULTS_OPEN:
2162 case MII_VCT7_RESULTS_SAME_SHORT:
2163 case MII_VCT7_RESULTS_CROSS_SHORT:
2169 static int marvell_vct7_report_length(struct phy_device *phydev,
2170 int pair, bool meter)
2175 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2176 MII_VCT7_PAIR_0_DISTANCE + pair);
2180 length = marvell_vct7_distance_to_length(ret, meter);
2182 ethnl_cable_test_fault_length(phydev, pair, length);
2187 static int marvell_vct7_cable_test_report_trans(int result)
2190 case MII_VCT7_RESULTS_OK:
2191 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2192 case MII_VCT7_RESULTS_OPEN:
2193 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2194 case MII_VCT7_RESULTS_SAME_SHORT:
2195 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2196 case MII_VCT7_RESULTS_CROSS_SHORT:
2197 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2199 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2203 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2205 int pair0, pair1, pair2, pair3;
2209 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2214 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2215 MII_VCT7_RESULTS_PAIR3_SHIFT;
2216 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2217 MII_VCT7_RESULTS_PAIR2_SHIFT;
2218 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2219 MII_VCT7_RESULTS_PAIR1_SHIFT;
2220 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2221 MII_VCT7_RESULTS_PAIR0_SHIFT;
2223 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2224 marvell_vct7_cable_test_report_trans(pair0));
2225 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2226 marvell_vct7_cable_test_report_trans(pair1));
2227 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2228 marvell_vct7_cable_test_report_trans(pair2));
2229 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2230 marvell_vct7_cable_test_report_trans(pair3));
2232 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2236 meter = ret & MII_VCT7_CTRL_METERS;
2238 if (marvell_vct7_distance_valid(pair0))
2239 marvell_vct7_report_length(phydev, 0, meter);
2240 if (marvell_vct7_distance_valid(pair1))
2241 marvell_vct7_report_length(phydev, 1, meter);
2242 if (marvell_vct7_distance_valid(pair2))
2243 marvell_vct7_report_length(phydev, 2, meter);
2244 if (marvell_vct7_distance_valid(pair3))
2245 marvell_vct7_report_length(phydev, 3, meter);
2250 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2253 struct marvell_priv *priv = phydev->priv;
2256 if (priv->cable_test_tdr) {
2257 ret = marvell_vct5_amplitude_graph(phydev);
2264 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2270 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2273 return marvell_vct7_cable_test_report(phydev);
2280 struct marvell_hwmon_ops {
2281 int (*config)(struct phy_device *phydev);
2282 int (*get_temp)(struct phy_device *phydev, long *temp);
2283 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2284 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2285 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2288 static const struct marvell_hwmon_ops *
2289 to_marvell_hwmon_ops(const struct phy_device *phydev)
2291 return phydev->drv->driver_data;
2294 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2302 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2306 /* Enable temperature sensor */
2307 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2311 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2312 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2316 /* Wait for temperature to stabilize */
2317 usleep_range(10000, 12000);
2319 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2325 /* Disable temperature sensor */
2326 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2327 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2331 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2334 return phy_restore_page(phydev, oldpage, ret);
2337 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2343 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2344 MII_88E1510_TEMP_SENSOR);
2348 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2353 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2359 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2360 MII_88E1121_MISC_TEST);
2364 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2365 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2372 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2375 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2377 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2378 MII_88E1121_MISC_TEST,
2379 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2380 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2383 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2389 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2390 MII_88E1121_MISC_TEST);
2394 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2399 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2408 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2412 /* Enable temperature sensor */
2413 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2417 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2418 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2420 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2424 /* Wait for temperature to stabilize */
2425 usleep_range(10000, 12000);
2427 /* Reading the temperature sense has an errata. You need to read
2428 * a number of times and take an average.
2430 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2431 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2434 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2437 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2438 *temp = (sum - 75) * 1000;
2440 /* Disable temperature sensor */
2441 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2445 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2446 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2448 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2451 phy_restore_page(phydev, oldpage, ret);
2456 static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2460 err = m88e1510_get_temp(phydev, temp);
2462 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2463 * T + 75, so we have to subtract another 50
2470 static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2476 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2477 MII_88E6390_TEMP_SENSOR);
2481 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2482 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2487 static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2489 temp = (temp / 1000) + 75;
2491 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2492 MII_88E6390_TEMP_SENSOR,
2493 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2494 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2497 static int m88e6393_hwmon_config(struct phy_device *phydev)
2501 err = m88e6393_set_temp_critical(phydev, 100000);
2505 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2506 MII_88E6390_MISC_TEST,
2507 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2508 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2509 MII_88E6393_MISC_TEST_RATE_MASK,
2510 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2511 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2512 MII_88E6393_MISC_TEST_RATE_2_3MS);
2515 static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2516 u32 attr, int channel, long *temp)
2518 struct phy_device *phydev = dev_get_drvdata(dev);
2519 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2520 int err = -EOPNOTSUPP;
2523 case hwmon_temp_input:
2525 err = ops->get_temp(phydev, temp);
2527 case hwmon_temp_crit:
2528 if (ops->get_temp_critical)
2529 err = ops->get_temp_critical(phydev, temp);
2531 case hwmon_temp_max_alarm:
2532 if (ops->get_temp_alarm)
2533 err = ops->get_temp_alarm(phydev, temp);
2540 static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2541 u32 attr, int channel, long temp)
2543 struct phy_device *phydev = dev_get_drvdata(dev);
2544 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2545 int err = -EOPNOTSUPP;
2548 case hwmon_temp_crit:
2549 if (ops->set_temp_critical)
2550 err = ops->set_temp_critical(phydev, temp);
2557 static umode_t marvell_hwmon_is_visible(const void *data,
2558 enum hwmon_sensor_types type,
2559 u32 attr, int channel)
2561 const struct phy_device *phydev = data;
2562 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2564 if (type != hwmon_temp)
2568 case hwmon_temp_input:
2569 return ops->get_temp ? 0444 : 0;
2570 case hwmon_temp_max_alarm:
2571 return ops->get_temp_alarm ? 0444 : 0;
2572 case hwmon_temp_crit:
2573 return (ops->get_temp_critical ? 0444 : 0) |
2574 (ops->set_temp_critical ? 0200 : 0);
2580 static u32 marvell_hwmon_chip_config[] = {
2581 HWMON_C_REGISTER_TZ,
2585 static const struct hwmon_channel_info marvell_hwmon_chip = {
2587 .config = marvell_hwmon_chip_config,
2590 /* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2591 * defined for all PHYs, because the hwmon code checks whether the attributes
2592 * exists via the .is_visible method
2594 static u32 marvell_hwmon_temp_config[] = {
2595 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2599 static const struct hwmon_channel_info marvell_hwmon_temp = {
2601 .config = marvell_hwmon_temp_config,
2604 static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2605 &marvell_hwmon_chip,
2606 &marvell_hwmon_temp,
2610 static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2611 .is_visible = marvell_hwmon_is_visible,
2612 .read = marvell_hwmon_read,
2613 .write = marvell_hwmon_write,
2616 static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2617 .ops = &marvell_hwmon_hwmon_ops,
2618 .info = marvell_hwmon_info,
2621 static int marvell_hwmon_name(struct phy_device *phydev)
2623 struct marvell_priv *priv = phydev->priv;
2624 struct device *dev = &phydev->mdio.dev;
2625 const char *devname = dev_name(dev);
2626 size_t len = strlen(devname);
2629 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2630 if (!priv->hwmon_name)
2633 for (i = j = 0; i < len && devname[i]; i++) {
2634 if (isalnum(devname[i]))
2635 priv->hwmon_name[j++] = devname[i];
2641 static int marvell_hwmon_probe(struct phy_device *phydev)
2643 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2644 struct marvell_priv *priv = phydev->priv;
2645 struct device *dev = &phydev->mdio.dev;
2651 err = marvell_hwmon_name(phydev);
2655 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2656 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
2657 if (IS_ERR(priv->hwmon_dev))
2658 return PTR_ERR(priv->hwmon_dev);
2661 err = ops->config(phydev);
2666 static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2667 .get_temp = m88e1121_get_temp,
2670 static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2671 .get_temp = m88e1510_get_temp,
2672 .get_temp_critical = m88e1510_get_temp_critical,
2673 .set_temp_critical = m88e1510_set_temp_critical,
2674 .get_temp_alarm = m88e1510_get_temp_alarm,
2677 static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2678 .get_temp = m88e6390_get_temp,
2681 static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2682 .config = m88e6393_hwmon_config,
2683 .get_temp = m88e6393_get_temp,
2684 .get_temp_critical = m88e6393_get_temp_critical,
2685 .set_temp_critical = m88e6393_set_temp_critical,
2686 .get_temp_alarm = m88e1510_get_temp_alarm,
2689 #define DEF_MARVELL_HWMON_OPS(s) (&(s))
2693 #define DEF_MARVELL_HWMON_OPS(s) NULL
2695 static int marvell_hwmon_probe(struct phy_device *phydev)
2701 static int marvell_probe(struct phy_device *phydev)
2703 struct marvell_priv *priv;
2705 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2709 phydev->priv = priv;
2711 return marvell_hwmon_probe(phydev);
2714 static struct phy_driver marvell_drivers[] = {
2716 .phy_id = MARVELL_PHY_ID_88E1101,
2717 .phy_id_mask = MARVELL_PHY_ID_MASK,
2718 .name = "Marvell 88E1101",
2719 /* PHY_GBIT_FEATURES */
2720 .probe = marvell_probe,
2721 .config_init = marvell_config_init,
2722 .config_aneg = m88e1101_config_aneg,
2723 .config_intr = marvell_config_intr,
2724 .handle_interrupt = marvell_handle_interrupt,
2725 .resume = genphy_resume,
2726 .suspend = genphy_suspend,
2727 .read_page = marvell_read_page,
2728 .write_page = marvell_write_page,
2729 .get_sset_count = marvell_get_sset_count,
2730 .get_strings = marvell_get_strings,
2731 .get_stats = marvell_get_stats,
2734 .phy_id = MARVELL_PHY_ID_88E1112,
2735 .phy_id_mask = MARVELL_PHY_ID_MASK,
2736 .name = "Marvell 88E1112",
2737 /* PHY_GBIT_FEATURES */
2738 .probe = marvell_probe,
2739 .config_init = m88e1112_config_init,
2740 .config_aneg = marvell_config_aneg,
2741 .config_intr = marvell_config_intr,
2742 .handle_interrupt = marvell_handle_interrupt,
2743 .resume = genphy_resume,
2744 .suspend = genphy_suspend,
2745 .read_page = marvell_read_page,
2746 .write_page = marvell_write_page,
2747 .get_sset_count = marvell_get_sset_count,
2748 .get_strings = marvell_get_strings,
2749 .get_stats = marvell_get_stats,
2750 .get_tunable = m88e1011_get_tunable,
2751 .set_tunable = m88e1011_set_tunable,
2754 .phy_id = MARVELL_PHY_ID_88E1111,
2755 .phy_id_mask = MARVELL_PHY_ID_MASK,
2756 .name = "Marvell 88E1111",
2757 /* PHY_GBIT_FEATURES */
2758 .probe = marvell_probe,
2759 .config_init = m88e1111gbe_config_init,
2760 .config_aneg = m88e1111_config_aneg,
2761 .read_status = marvell_read_status,
2762 .config_intr = marvell_config_intr,
2763 .handle_interrupt = marvell_handle_interrupt,
2764 .resume = genphy_resume,
2765 .suspend = genphy_suspend,
2766 .read_page = marvell_read_page,
2767 .write_page = marvell_write_page,
2768 .get_sset_count = marvell_get_sset_count,
2769 .get_strings = marvell_get_strings,
2770 .get_stats = marvell_get_stats,
2771 .get_tunable = m88e1111_get_tunable,
2772 .set_tunable = m88e1111_set_tunable,
2775 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
2776 .phy_id_mask = MARVELL_PHY_ID_MASK,
2777 .name = "Marvell 88E1111 (Finisar)",
2778 /* PHY_GBIT_FEATURES */
2779 .probe = marvell_probe,
2780 .config_init = m88e1111gbe_config_init,
2781 .config_aneg = m88e1111_config_aneg,
2782 .read_status = marvell_read_status,
2783 .config_intr = marvell_config_intr,
2784 .handle_interrupt = marvell_handle_interrupt,
2785 .resume = genphy_resume,
2786 .suspend = genphy_suspend,
2787 .read_page = marvell_read_page,
2788 .write_page = marvell_write_page,
2789 .get_sset_count = marvell_get_sset_count,
2790 .get_strings = marvell_get_strings,
2791 .get_stats = marvell_get_stats,
2792 .get_tunable = m88e1111_get_tunable,
2793 .set_tunable = m88e1111_set_tunable,
2796 .phy_id = MARVELL_PHY_ID_88E1118,
2797 .phy_id_mask = MARVELL_PHY_ID_MASK,
2798 .name = "Marvell 88E1118",
2799 /* PHY_GBIT_FEATURES */
2800 .probe = marvell_probe,
2801 .config_init = m88e1118_config_init,
2802 .config_aneg = m88e1118_config_aneg,
2803 .config_intr = marvell_config_intr,
2804 .handle_interrupt = marvell_handle_interrupt,
2805 .resume = genphy_resume,
2806 .suspend = genphy_suspend,
2807 .read_page = marvell_read_page,
2808 .write_page = marvell_write_page,
2809 .get_sset_count = marvell_get_sset_count,
2810 .get_strings = marvell_get_strings,
2811 .get_stats = marvell_get_stats,
2814 .phy_id = MARVELL_PHY_ID_88E1121R,
2815 .phy_id_mask = MARVELL_PHY_ID_MASK,
2816 .name = "Marvell 88E1121R",
2817 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
2818 /* PHY_GBIT_FEATURES */
2819 .probe = marvell_probe,
2820 .config_init = marvell_1011gbe_config_init,
2821 .config_aneg = m88e1121_config_aneg,
2822 .read_status = marvell_read_status,
2823 .config_intr = marvell_config_intr,
2824 .handle_interrupt = marvell_handle_interrupt,
2825 .resume = genphy_resume,
2826 .suspend = genphy_suspend,
2827 .read_page = marvell_read_page,
2828 .write_page = marvell_write_page,
2829 .get_sset_count = marvell_get_sset_count,
2830 .get_strings = marvell_get_strings,
2831 .get_stats = marvell_get_stats,
2832 .get_tunable = m88e1011_get_tunable,
2833 .set_tunable = m88e1011_set_tunable,
2836 .phy_id = MARVELL_PHY_ID_88E1318S,
2837 .phy_id_mask = MARVELL_PHY_ID_MASK,
2838 .name = "Marvell 88E1318S",
2839 /* PHY_GBIT_FEATURES */
2840 .probe = marvell_probe,
2841 .config_init = m88e1318_config_init,
2842 .config_aneg = m88e1318_config_aneg,
2843 .read_status = marvell_read_status,
2844 .config_intr = marvell_config_intr,
2845 .handle_interrupt = marvell_handle_interrupt,
2846 .get_wol = m88e1318_get_wol,
2847 .set_wol = m88e1318_set_wol,
2848 .resume = genphy_resume,
2849 .suspend = genphy_suspend,
2850 .read_page = marvell_read_page,
2851 .write_page = marvell_write_page,
2852 .get_sset_count = marvell_get_sset_count,
2853 .get_strings = marvell_get_strings,
2854 .get_stats = marvell_get_stats,
2857 .phy_id = MARVELL_PHY_ID_88E1145,
2858 .phy_id_mask = MARVELL_PHY_ID_MASK,
2859 .name = "Marvell 88E1145",
2860 /* PHY_GBIT_FEATURES */
2861 .probe = marvell_probe,
2862 .config_init = m88e1145_config_init,
2863 .config_aneg = m88e1101_config_aneg,
2864 .config_intr = marvell_config_intr,
2865 .handle_interrupt = marvell_handle_interrupt,
2866 .resume = genphy_resume,
2867 .suspend = genphy_suspend,
2868 .read_page = marvell_read_page,
2869 .write_page = marvell_write_page,
2870 .get_sset_count = marvell_get_sset_count,
2871 .get_strings = marvell_get_strings,
2872 .get_stats = marvell_get_stats,
2873 .get_tunable = m88e1111_get_tunable,
2874 .set_tunable = m88e1111_set_tunable,
2877 .phy_id = MARVELL_PHY_ID_88E1149R,
2878 .phy_id_mask = MARVELL_PHY_ID_MASK,
2879 .name = "Marvell 88E1149R",
2880 /* PHY_GBIT_FEATURES */
2881 .probe = marvell_probe,
2882 .config_init = m88e1149_config_init,
2883 .config_aneg = m88e1118_config_aneg,
2884 .config_intr = marvell_config_intr,
2885 .handle_interrupt = marvell_handle_interrupt,
2886 .resume = genphy_resume,
2887 .suspend = genphy_suspend,
2888 .read_page = marvell_read_page,
2889 .write_page = marvell_write_page,
2890 .get_sset_count = marvell_get_sset_count,
2891 .get_strings = marvell_get_strings,
2892 .get_stats = marvell_get_stats,
2895 .phy_id = MARVELL_PHY_ID_88E1240,
2896 .phy_id_mask = MARVELL_PHY_ID_MASK,
2897 .name = "Marvell 88E1240",
2898 /* PHY_GBIT_FEATURES */
2899 .probe = marvell_probe,
2900 .config_init = m88e1112_config_init,
2901 .config_aneg = marvell_config_aneg,
2902 .config_intr = marvell_config_intr,
2903 .handle_interrupt = marvell_handle_interrupt,
2904 .resume = genphy_resume,
2905 .suspend = genphy_suspend,
2906 .read_page = marvell_read_page,
2907 .write_page = marvell_write_page,
2908 .get_sset_count = marvell_get_sset_count,
2909 .get_strings = marvell_get_strings,
2910 .get_stats = marvell_get_stats,
2911 .get_tunable = m88e1011_get_tunable,
2912 .set_tunable = m88e1011_set_tunable,
2915 .phy_id = MARVELL_PHY_ID_88E1116R,
2916 .phy_id_mask = MARVELL_PHY_ID_MASK,
2917 .name = "Marvell 88E1116R",
2918 /* PHY_GBIT_FEATURES */
2919 .probe = marvell_probe,
2920 .config_init = m88e1116r_config_init,
2921 .config_intr = marvell_config_intr,
2922 .handle_interrupt = marvell_handle_interrupt,
2923 .resume = genphy_resume,
2924 .suspend = genphy_suspend,
2925 .read_page = marvell_read_page,
2926 .write_page = marvell_write_page,
2927 .get_sset_count = marvell_get_sset_count,
2928 .get_strings = marvell_get_strings,
2929 .get_stats = marvell_get_stats,
2930 .get_tunable = m88e1011_get_tunable,
2931 .set_tunable = m88e1011_set_tunable,
2934 .phy_id = MARVELL_PHY_ID_88E1510,
2935 .phy_id_mask = MARVELL_PHY_ID_MASK,
2936 .name = "Marvell 88E1510",
2937 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2938 .features = PHY_GBIT_FIBRE_FEATURES,
2939 .flags = PHY_POLL_CABLE_TEST,
2940 .probe = marvell_probe,
2941 .config_init = m88e1510_config_init,
2942 .config_aneg = m88e1510_config_aneg,
2943 .read_status = marvell_read_status,
2944 .config_intr = marvell_config_intr,
2945 .handle_interrupt = marvell_handle_interrupt,
2946 .get_wol = m88e1318_get_wol,
2947 .set_wol = m88e1318_set_wol,
2948 .resume = marvell_resume,
2949 .suspend = marvell_suspend,
2950 .read_page = marvell_read_page,
2951 .write_page = marvell_write_page,
2952 .get_sset_count = marvell_get_sset_count,
2953 .get_strings = marvell_get_strings,
2954 .get_stats = marvell_get_stats,
2955 .set_loopback = genphy_loopback,
2956 .get_tunable = m88e1011_get_tunable,
2957 .set_tunable = m88e1011_set_tunable,
2958 .cable_test_start = marvell_vct7_cable_test_start,
2959 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2960 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2963 .phy_id = MARVELL_PHY_ID_88E1540,
2964 .phy_id_mask = MARVELL_PHY_ID_MASK,
2965 .name = "Marvell 88E1540",
2966 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2967 /* PHY_GBIT_FEATURES */
2968 .flags = PHY_POLL_CABLE_TEST,
2969 .probe = marvell_probe,
2970 .config_init = marvell_1011gbe_config_init,
2971 .config_aneg = m88e1510_config_aneg,
2972 .read_status = marvell_read_status,
2973 .config_intr = marvell_config_intr,
2974 .handle_interrupt = marvell_handle_interrupt,
2975 .resume = genphy_resume,
2976 .suspend = genphy_suspend,
2977 .read_page = marvell_read_page,
2978 .write_page = marvell_write_page,
2979 .get_sset_count = marvell_get_sset_count,
2980 .get_strings = marvell_get_strings,
2981 .get_stats = marvell_get_stats,
2982 .get_tunable = m88e1540_get_tunable,
2983 .set_tunable = m88e1540_set_tunable,
2984 .cable_test_start = marvell_vct7_cable_test_start,
2985 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2986 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2989 .phy_id = MARVELL_PHY_ID_88E1545,
2990 .phy_id_mask = MARVELL_PHY_ID_MASK,
2991 .name = "Marvell 88E1545",
2992 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2993 .probe = marvell_probe,
2994 /* PHY_GBIT_FEATURES */
2995 .flags = PHY_POLL_CABLE_TEST,
2996 .config_init = marvell_1011gbe_config_init,
2997 .config_aneg = m88e1510_config_aneg,
2998 .read_status = marvell_read_status,
2999 .config_intr = marvell_config_intr,
3000 .handle_interrupt = marvell_handle_interrupt,
3001 .resume = genphy_resume,
3002 .suspend = genphy_suspend,
3003 .read_page = marvell_read_page,
3004 .write_page = marvell_write_page,
3005 .get_sset_count = marvell_get_sset_count,
3006 .get_strings = marvell_get_strings,
3007 .get_stats = marvell_get_stats,
3008 .get_tunable = m88e1540_get_tunable,
3009 .set_tunable = m88e1540_set_tunable,
3010 .cable_test_start = marvell_vct7_cable_test_start,
3011 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3012 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3015 .phy_id = MARVELL_PHY_ID_88E3016,
3016 .phy_id_mask = MARVELL_PHY_ID_MASK,
3017 .name = "Marvell 88E3016",
3018 /* PHY_BASIC_FEATURES */
3019 .probe = marvell_probe,
3020 .config_init = m88e3016_config_init,
3021 .aneg_done = marvell_aneg_done,
3022 .read_status = marvell_read_status,
3023 .config_intr = marvell_config_intr,
3024 .handle_interrupt = marvell_handle_interrupt,
3025 .resume = genphy_resume,
3026 .suspend = genphy_suspend,
3027 .read_page = marvell_read_page,
3028 .write_page = marvell_write_page,
3029 .get_sset_count = marvell_get_sset_count,
3030 .get_strings = marvell_get_strings,
3031 .get_stats = marvell_get_stats,
3034 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
3035 .phy_id_mask = MARVELL_PHY_ID_MASK,
3036 .name = "Marvell 88E6341 Family",
3037 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3038 /* PHY_GBIT_FEATURES */
3039 .flags = PHY_POLL_CABLE_TEST,
3040 .probe = marvell_probe,
3041 .config_init = marvell_1011gbe_config_init,
3042 .config_aneg = m88e6390_config_aneg,
3043 .read_status = marvell_read_status,
3044 .config_intr = marvell_config_intr,
3045 .handle_interrupt = marvell_handle_interrupt,
3046 .resume = genphy_resume,
3047 .suspend = genphy_suspend,
3048 .read_page = marvell_read_page,
3049 .write_page = marvell_write_page,
3050 .get_sset_count = marvell_get_sset_count,
3051 .get_strings = marvell_get_strings,
3052 .get_stats = marvell_get_stats,
3053 .get_tunable = m88e1540_get_tunable,
3054 .set_tunable = m88e1540_set_tunable,
3055 .cable_test_start = marvell_vct7_cable_test_start,
3056 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3057 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3060 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3061 .phy_id_mask = MARVELL_PHY_ID_MASK,
3062 .name = "Marvell 88E6390 Family",
3063 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
3064 /* PHY_GBIT_FEATURES */
3065 .flags = PHY_POLL_CABLE_TEST,
3066 .probe = marvell_probe,
3067 .config_init = marvell_1011gbe_config_init,
3068 .config_aneg = m88e6390_config_aneg,
3069 .read_status = marvell_read_status,
3070 .config_intr = marvell_config_intr,
3071 .handle_interrupt = marvell_handle_interrupt,
3072 .resume = genphy_resume,
3073 .suspend = genphy_suspend,
3074 .read_page = marvell_read_page,
3075 .write_page = marvell_write_page,
3076 .get_sset_count = marvell_get_sset_count,
3077 .get_strings = marvell_get_strings,
3078 .get_stats = marvell_get_stats,
3079 .get_tunable = m88e1540_get_tunable,
3080 .set_tunable = m88e1540_set_tunable,
3081 .cable_test_start = marvell_vct7_cable_test_start,
3082 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3083 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3086 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3087 .phy_id_mask = MARVELL_PHY_ID_MASK,
3088 .name = "Marvell 88E6393 Family",
3089 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3090 /* PHY_GBIT_FEATURES */
3091 .flags = PHY_POLL_CABLE_TEST,
3092 .probe = marvell_probe,
3093 .config_init = marvell_1011gbe_config_init,
3094 .config_aneg = m88e1510_config_aneg,
3095 .read_status = marvell_read_status,
3096 .config_intr = marvell_config_intr,
3097 .handle_interrupt = marvell_handle_interrupt,
3098 .resume = genphy_resume,
3099 .suspend = genphy_suspend,
3100 .read_page = marvell_read_page,
3101 .write_page = marvell_write_page,
3102 .get_sset_count = marvell_get_sset_count,
3103 .get_strings = marvell_get_strings,
3104 .get_stats = marvell_get_stats,
3105 .get_tunable = m88e1540_get_tunable,
3106 .set_tunable = m88e1540_set_tunable,
3107 .cable_test_start = marvell_vct7_cable_test_start,
3108 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3109 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3112 .phy_id = MARVELL_PHY_ID_88E1340S,
3113 .phy_id_mask = MARVELL_PHY_ID_MASK,
3114 .name = "Marvell 88E1340S",
3115 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3116 .probe = marvell_probe,
3117 /* PHY_GBIT_FEATURES */
3118 .config_init = marvell_1011gbe_config_init,
3119 .config_aneg = m88e1510_config_aneg,
3120 .read_status = marvell_read_status,
3121 .config_intr = marvell_config_intr,
3122 .handle_interrupt = marvell_handle_interrupt,
3123 .resume = genphy_resume,
3124 .suspend = genphy_suspend,
3125 .read_page = marvell_read_page,
3126 .write_page = marvell_write_page,
3127 .get_sset_count = marvell_get_sset_count,
3128 .get_strings = marvell_get_strings,
3129 .get_stats = marvell_get_stats,
3130 .get_tunable = m88e1540_get_tunable,
3131 .set_tunable = m88e1540_set_tunable,
3134 .phy_id = MARVELL_PHY_ID_88E1548P,
3135 .phy_id_mask = MARVELL_PHY_ID_MASK,
3136 .name = "Marvell 88E1548P",
3137 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3138 .probe = marvell_probe,
3139 .features = PHY_GBIT_FIBRE_FEATURES,
3140 .config_init = marvell_1011gbe_config_init,
3141 .config_aneg = m88e1510_config_aneg,
3142 .read_status = marvell_read_status,
3143 .config_intr = marvell_config_intr,
3144 .handle_interrupt = marvell_handle_interrupt,
3145 .resume = genphy_resume,
3146 .suspend = genphy_suspend,
3147 .read_page = marvell_read_page,
3148 .write_page = marvell_write_page,
3149 .get_sset_count = marvell_get_sset_count,
3150 .get_strings = marvell_get_strings,
3151 .get_stats = marvell_get_stats,
3152 .get_tunable = m88e1540_get_tunable,
3153 .set_tunable = m88e1540_set_tunable,
3157 module_phy_driver(marvell_drivers);
3159 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3160 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3161 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3162 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3163 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3164 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3165 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3166 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3167 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3168 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3169 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3170 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3171 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3172 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3173 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3174 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3175 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3176 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3177 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
3178 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3179 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3183 MODULE_DEVICE_TABLE(mdio, marvell_tbl);