1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
38 #include <linux/uaccess.h>
40 #define MII_MARVELL_PHY_PAGE 22
41 #define MII_MARVELL_COPPER_PAGE 0x00
42 #define MII_MARVELL_FIBER_PAGE 0x01
43 #define MII_MARVELL_MSCR_PAGE 0x02
44 #define MII_MARVELL_LED_PAGE 0x03
45 #define MII_MARVELL_VCT5_PAGE 0x05
46 #define MII_MARVELL_MISC_TEST_PAGE 0x06
47 #define MII_MARVELL_VCT7_PAGE 0x07
48 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_M1011_IEVENT 0x13
51 #define MII_M1011_IEVENT_CLEAR 0x0000
53 #define MII_M1011_IMASK 0x12
54 #define MII_M1011_IMASK_INIT 0x6400
55 #define MII_M1011_IMASK_CLEAR 0x0000
57 #define MII_M1011_PHY_SCR 0x10
58 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
59 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
61 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
62 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
63 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
65 #define MII_M1011_PHY_SSR 0x11
66 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
73 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
75 #define MII_M1111_RGMII_RX_DELAY BIT(7)
76 #define MII_M1111_RGMII_TX_DELAY BIT(1)
77 #define MII_M1111_PHY_EXT_SR 0x1b
79 #define MII_M1111_HWCFG_MODE_MASK 0xf
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_RTBI 0x7
83 #define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
84 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
85 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
86 #define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
87 #define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
88 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
89 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
91 #define MII_88E1121_PHY_MSCR_REG 21
92 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
93 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
94 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
96 #define MII_88E1121_MISC_TEST 0x1a
97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
98 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
99 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
100 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
101 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
102 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
104 #define MII_88E1510_TEMP_SENSOR 0x1b
105 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
107 #define MII_88E1540_COPPER_CTRL3 0x1a
108 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
109 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
110 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
111 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
112 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
113 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
115 #define MII_88E6390_MISC_TEST 0x1b
116 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
117 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
118 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
119 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
120 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
121 #define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
122 #define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
123 #define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
124 #define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
125 #define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
126 #define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
127 #define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
128 #define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
129 #define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
131 #define MII_88E6390_TEMP_SENSOR 0x1c
132 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
133 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
134 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
135 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
137 #define MII_88E1318S_PHY_MSCR1_REG 16
138 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
140 /* Copper Specific Interrupt Enable Register */
141 #define MII_88E1318S_PHY_CSIER 0x12
142 /* WOL Event Interrupt Enable */
143 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
145 /* LED Timer Control Register */
146 #define MII_88E1318S_PHY_LED_TCR 0x12
147 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
148 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
149 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
151 /* Magic Packet MAC address registers */
152 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
153 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
154 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
156 #define MII_88E1318S_PHY_WOL_CTRL 0x10
157 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
158 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
160 #define MII_PHY_LED_CTRL 16
161 #define MII_88E1121_PHY_LED_DEF 0x0030
162 #define MII_88E1510_PHY_LED_DEF 0x1177
163 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
165 #define MII_M1011_PHY_STATUS 0x11
166 #define MII_M1011_PHY_STATUS_1000 0x8000
167 #define MII_M1011_PHY_STATUS_100 0x4000
168 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
169 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
170 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
171 #define MII_M1011_PHY_STATUS_LINK 0x0400
173 #define MII_88E3016_PHY_SPEC_CTRL 0x10
174 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
175 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
177 #define MII_88E1510_GEN_CTRL_REG_1 0x14
178 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
179 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
180 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
182 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
183 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
184 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
185 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
186 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
187 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
188 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
190 #define MII_VCT5_CTRL 0x17
191 #define MII_VCT5_CTRL_ENABLE BIT(15)
192 #define MII_VCT5_CTRL_COMPLETE BIT(14)
193 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
194 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
195 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
196 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
197 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
198 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
199 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
200 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
201 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
202 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
203 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
204 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
205 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
206 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
207 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
208 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
209 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
210 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
211 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
212 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
214 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
215 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
216 #define MII_VCT5_TX_PULSE_CTRL 0x1c
217 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
218 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
219 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
220 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
221 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
222 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
223 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
224 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
225 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
226 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
227 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
228 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
229 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
231 /* For TDR measurements less than 11 meters, a short pulse should be
234 #define TDR_SHORT_CABLE_LENGTH 11
236 #define MII_VCT7_PAIR_0_DISTANCE 0x10
237 #define MII_VCT7_PAIR_1_DISTANCE 0x11
238 #define MII_VCT7_PAIR_2_DISTANCE 0x12
239 #define MII_VCT7_PAIR_3_DISTANCE 0x13
241 #define MII_VCT7_RESULTS 0x14
242 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
243 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
244 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
245 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
246 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
247 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
248 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
249 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
250 #define MII_VCT7_RESULTS_INVALID 0
251 #define MII_VCT7_RESULTS_OK 1
252 #define MII_VCT7_RESULTS_OPEN 2
253 #define MII_VCT7_RESULTS_SAME_SHORT 3
254 #define MII_VCT7_RESULTS_CROSS_SHORT 4
255 #define MII_VCT7_RESULTS_BUSY 9
257 #define MII_VCT7_CTRL 0x15
258 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
259 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
260 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
261 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
262 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
263 #define MII_VCT7_CTRL_METERS BIT(10)
264 #define MII_VCT7_CTRL_CENTIMETERS 0
266 #define LPA_PAUSE_FIBER 0x180
267 #define LPA_PAUSE_ASYM_FIBER 0x100
269 #define NB_FIBER_STATS 1
271 MODULE_DESCRIPTION("Marvell PHY driver");
272 MODULE_AUTHOR("Andy Fleming");
273 MODULE_LICENSE("GPL");
275 struct marvell_hw_stat {
282 static struct marvell_hw_stat marvell_hw_stats[] = {
283 { "phy_receive_errors_copper", 0, 21, 16},
284 { "phy_idle_errors", 0, 10, 8 },
285 { "phy_receive_errors_fiber", 1, 21, 16},
288 struct marvell_priv {
289 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
291 struct device *hwmon_dev;
299 static int marvell_read_page(struct phy_device *phydev)
301 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
304 static int marvell_write_page(struct phy_device *phydev, int page)
306 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
309 static int marvell_set_page(struct phy_device *phydev, int page)
311 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
314 static int marvell_ack_interrupt(struct phy_device *phydev)
318 /* Clear the interrupts by reading the reg */
319 err = phy_read(phydev, MII_M1011_IEVENT);
327 static int marvell_config_intr(struct phy_device *phydev)
331 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
332 err = marvell_ack_interrupt(phydev);
336 err = phy_write(phydev, MII_M1011_IMASK,
337 MII_M1011_IMASK_INIT);
339 err = phy_write(phydev, MII_M1011_IMASK,
340 MII_M1011_IMASK_CLEAR);
344 err = marvell_ack_interrupt(phydev);
350 static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
354 irq_status = phy_read(phydev, MII_M1011_IEVENT);
355 if (irq_status < 0) {
360 if (!(irq_status & MII_M1011_IMASK_INIT))
363 phy_trigger_machine(phydev);
368 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
374 /* get the current settings */
375 reg = phy_read(phydev, MII_M1011_PHY_SCR);
380 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
383 val |= MII_M1011_PHY_SCR_MDI;
386 val |= MII_M1011_PHY_SCR_MDI_X;
388 case ETH_TP_MDI_AUTO:
389 case ETH_TP_MDI_INVALID:
391 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
396 /* Set the new polarity value in the register */
397 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
405 static int marvell_config_aneg(struct phy_device *phydev)
410 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
416 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
417 MII_M1111_PHY_LED_DIRECT);
421 err = genphy_config_aneg(phydev);
425 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
426 /* A write to speed/duplex bits (that is performed by
427 * genphy_config_aneg() call above) must be followed by
428 * a software reset. Otherwise, the write has no effect.
430 err = genphy_soft_reset(phydev);
438 static int m88e1101_config_aneg(struct phy_device *phydev)
442 /* This Marvell PHY has an errata which requires
443 * that certain registers get written in order
444 * to restart autonegotiation
446 err = genphy_soft_reset(phydev);
450 err = phy_write(phydev, 0x1d, 0x1f);
454 err = phy_write(phydev, 0x1e, 0x200c);
458 err = phy_write(phydev, 0x1d, 0x5);
462 err = phy_write(phydev, 0x1e, 0);
466 err = phy_write(phydev, 0x1e, 0x100);
470 return marvell_config_aneg(phydev);
473 #if IS_ENABLED(CONFIG_OF_MDIO)
474 /* Set and/or override some configuration registers based on the
475 * marvell,reg-init property stored in the of_node for the phydev.
477 * marvell,reg-init = <reg-page reg mask value>,...;
479 * There may be one or more sets of <reg-page reg mask value>:
481 * reg-page: which register bank to use.
483 * mask: if non-zero, ANDed with existing register value.
484 * value: ORed with the masked value and written to the regiser.
487 static int marvell_of_reg_init(struct phy_device *phydev)
490 int len, i, saved_page, current_page, ret = 0;
492 if (!phydev->mdio.dev.of_node)
495 paddr = of_get_property(phydev->mdio.dev.of_node,
496 "marvell,reg-init", &len);
497 if (!paddr || len < (4 * sizeof(*paddr)))
500 saved_page = phy_save_page(phydev);
503 current_page = saved_page;
505 len /= sizeof(*paddr);
506 for (i = 0; i < len - 3; i += 4) {
507 u16 page = be32_to_cpup(paddr + i);
508 u16 reg = be32_to_cpup(paddr + i + 1);
509 u16 mask = be32_to_cpup(paddr + i + 2);
510 u16 val_bits = be32_to_cpup(paddr + i + 3);
513 if (page != current_page) {
515 ret = marvell_write_page(phydev, page);
522 val = __phy_read(phydev, reg);
531 ret = __phy_write(phydev, reg, val);
536 return phy_restore_page(phydev, saved_page, ret);
539 static int marvell_of_reg_init(struct phy_device *phydev)
543 #endif /* CONFIG_OF_MDIO */
545 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
549 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
551 MII_88E1121_PHY_MSCR_TX_DELAY;
552 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
553 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
554 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
555 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
559 return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
560 MII_88E1121_PHY_MSCR_REG,
561 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
564 static int m88e1121_config_aneg(struct phy_device *phydev)
569 if (phy_interface_is_rgmii(phydev)) {
570 err = m88e1121_config_aneg_rgmii_delays(phydev);
575 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
581 err = genphy_config_aneg(phydev);
585 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
586 /* A software reset is used to ensure a "commit" of the
589 err = genphy_soft_reset(phydev);
597 static int m88e1318_config_aneg(struct phy_device *phydev)
601 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
602 MII_88E1318S_PHY_MSCR1_REG,
603 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
607 return m88e1121_config_aneg(phydev);
611 * linkmode_adv_to_fiber_adv_t
612 * @advertise: the linkmode advertisement settings
614 * A small helper function that translates linkmode advertisement
615 * settings to phy autonegotiation advertisements for the MII_ADV
616 * register for fiber link.
618 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
622 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
623 result |= ADVERTISE_1000XHALF;
624 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
625 result |= ADVERTISE_1000XFULL;
627 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
628 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
629 result |= ADVERTISE_1000XPSE_ASYM;
630 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
631 result |= ADVERTISE_1000XPAUSE;
637 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
638 * @phydev: target phy_device struct
640 * Description: If auto-negotiation is enabled, we configure the
641 * advertising, and then restart auto-negotiation. If it is not
642 * enabled, then we write the BMCR. Adapted for fiber link in
643 * some Marvell's devices.
645 static int marvell_config_aneg_fiber(struct phy_device *phydev)
651 if (phydev->autoneg != AUTONEG_ENABLE)
652 return genphy_setup_forced(phydev);
654 /* Only allow advertising what this PHY supports */
655 linkmode_and(phydev->advertising, phydev->advertising,
658 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
660 /* Setup fiber advertisement */
661 err = phy_modify_changed(phydev, MII_ADVERTISE,
662 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
663 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
670 return genphy_check_and_restart_aneg(phydev, changed);
673 static int m88e1111_config_aneg(struct phy_device *phydev)
675 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
681 /* If not using SGMII or copper 1000BaseX modes, use normal process.
682 * Steps below are only required for these modes.
684 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
685 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
686 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
687 return marvell_config_aneg(phydev);
689 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
693 /* Configure the copper link first */
694 err = marvell_config_aneg(phydev);
698 /* Then the fiber link */
699 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
703 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
704 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
705 * Just ensure that SGMII-side autonegotiation is enabled.
706 * If we switched from some other mode to SGMII it may not be.
708 err = genphy_check_and_restart_aneg(phydev, false);
710 err = marvell_config_aneg_fiber(phydev);
714 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
717 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
721 static int m88e1510_config_aneg(struct phy_device *phydev)
725 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
729 /* Configure the copper link first */
730 err = m88e1318_config_aneg(phydev);
734 /* Do not touch the fiber page if we're in copper->sgmii mode */
735 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
738 /* Then the fiber link */
739 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
743 err = marvell_config_aneg_fiber(phydev);
747 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
750 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
754 static void marvell_config_led(struct phy_device *phydev)
759 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
760 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
761 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
762 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
763 def_config = MII_88E1121_PHY_LED_DEF;
765 /* Default PHY LED config:
766 * LED[0] .. 1000Mbps Link
767 * LED[1] .. 100Mbps Link
768 * LED[2] .. Blink, Activity
770 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
771 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
772 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
774 def_config = MII_88E1510_PHY_LED_DEF;
780 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
783 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
786 static int marvell_config_init(struct phy_device *phydev)
788 /* Set default LED */
789 marvell_config_led(phydev);
791 /* Set registers from marvell,reg-init DT property */
792 return marvell_of_reg_init(phydev);
795 static int m88e3016_config_init(struct phy_device *phydev)
799 /* Enable Scrambler and Auto-Crossover */
800 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
801 MII_88E3016_DISABLE_SCRAMBLER,
802 MII_88E3016_AUTO_MDIX_CROSSOVER);
806 return marvell_config_init(phydev);
809 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
811 int fibre_copper_auto)
813 if (fibre_copper_auto)
814 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
816 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
817 MII_M1111_HWCFG_MODE_MASK |
818 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
819 MII_M1111_HWCFG_FIBER_COPPER_RES,
823 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
827 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
828 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
829 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
830 delay = MII_M1111_RGMII_RX_DELAY;
831 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
832 delay = MII_M1111_RGMII_TX_DELAY;
837 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
838 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
842 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
847 err = m88e1111_config_init_rgmii_delays(phydev);
851 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
855 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
857 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
858 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
860 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
862 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
865 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
869 err = m88e1111_config_init_hwcfg_mode(
871 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
872 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
876 /* make sure copper is selected */
877 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
880 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
884 err = m88e1111_config_init_rgmii_delays(phydev);
888 err = m88e1111_config_init_hwcfg_mode(
890 MII_M1111_HWCFG_MODE_RTBI,
891 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
896 err = genphy_soft_reset(phydev);
900 return m88e1111_config_init_hwcfg_mode(
902 MII_M1111_HWCFG_MODE_RTBI,
903 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
906 static int m88e1111_config_init_1000basex(struct phy_device *phydev)
908 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
914 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
915 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
916 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
917 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
918 MII_M1111_HWCFG_MODE_MASK |
919 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
920 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
921 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
928 static int m88e1111_config_init(struct phy_device *phydev)
932 if (phy_interface_is_rgmii(phydev)) {
933 err = m88e1111_config_init_rgmii(phydev);
938 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
939 err = m88e1111_config_init_sgmii(phydev);
944 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
945 err = m88e1111_config_init_rtbi(phydev);
950 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
951 err = m88e1111_config_init_1000basex(phydev);
956 err = marvell_of_reg_init(phydev);
960 return genphy_soft_reset(phydev);
963 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
965 int val, cnt, enable;
967 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
971 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
972 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
974 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
979 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
983 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
987 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
988 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
990 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
991 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
993 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
994 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
995 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1002 return genphy_soft_reset(phydev);
1005 static int m88e1111_get_tunable(struct phy_device *phydev,
1006 struct ethtool_tunable *tuna, void *data)
1009 case ETHTOOL_PHY_DOWNSHIFT:
1010 return m88e1111_get_downshift(phydev, data);
1016 static int m88e1111_set_tunable(struct phy_device *phydev,
1017 struct ethtool_tunable *tuna, const void *data)
1020 case ETHTOOL_PHY_DOWNSHIFT:
1021 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1027 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1029 int val, cnt, enable;
1031 val = phy_read(phydev, MII_M1011_PHY_SCR);
1035 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1036 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1038 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1043 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1047 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1051 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1052 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1054 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1055 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1057 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1058 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1059 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1066 return genphy_soft_reset(phydev);
1069 static int m88e1011_get_tunable(struct phy_device *phydev,
1070 struct ethtool_tunable *tuna, void *data)
1073 case ETHTOOL_PHY_DOWNSHIFT:
1074 return m88e1011_get_downshift(phydev, data);
1080 static int m88e1011_set_tunable(struct phy_device *phydev,
1081 struct ethtool_tunable *tuna, const void *data)
1084 case ETHTOOL_PHY_DOWNSHIFT:
1085 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1091 static int m88e1116r_config_init(struct phy_device *phydev)
1095 err = genphy_soft_reset(phydev);
1101 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1105 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1109 err = m88e1011_set_downshift(phydev, 8);
1113 if (phy_interface_is_rgmii(phydev)) {
1114 err = m88e1121_config_aneg_rgmii_delays(phydev);
1119 err = genphy_soft_reset(phydev);
1123 return marvell_config_init(phydev);
1126 static int m88e1318_config_init(struct phy_device *phydev)
1128 if (phy_interrupt_is_valid(phydev)) {
1129 int err = phy_modify_paged(
1130 phydev, MII_MARVELL_LED_PAGE,
1131 MII_88E1318S_PHY_LED_TCR,
1132 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1133 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1134 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1139 return marvell_config_init(phydev);
1142 static int m88e1510_config_init(struct phy_device *phydev)
1146 /* SGMII-to-Copper mode initialization */
1147 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1148 /* Select page 18 */
1149 err = marvell_set_page(phydev, 18);
1153 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1154 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1155 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1156 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1160 /* PHY reset is necessary after changing MODE[2:0] */
1161 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1162 MII_88E1510_GEN_CTRL_REG_1_RESET);
1166 /* Reset page selection */
1167 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1172 return m88e1318_config_init(phydev);
1175 static int m88e1118_config_aneg(struct phy_device *phydev)
1179 err = genphy_soft_reset(phydev);
1183 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1187 err = genphy_config_aneg(phydev);
1191 static int m88e1118_config_init(struct phy_device *phydev)
1195 /* Change address */
1196 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1200 /* Enable 1000 Mbit */
1201 err = phy_write(phydev, 0x15, 0x1070);
1205 /* Change address */
1206 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1210 /* Adjust LED Control */
1211 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1212 err = phy_write(phydev, 0x10, 0x1100);
1214 err = phy_write(phydev, 0x10, 0x021e);
1218 err = marvell_of_reg_init(phydev);
1223 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1227 return genphy_soft_reset(phydev);
1230 static int m88e1149_config_init(struct phy_device *phydev)
1234 /* Change address */
1235 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1239 /* Enable 1000 Mbit */
1240 err = phy_write(phydev, 0x15, 0x1048);
1244 err = marvell_of_reg_init(phydev);
1249 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1253 return genphy_soft_reset(phydev);
1256 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1260 err = m88e1111_config_init_rgmii_delays(phydev);
1264 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1265 err = phy_write(phydev, 0x1d, 0x0012);
1269 err = phy_modify(phydev, 0x1e, 0x0fc0,
1270 2 << 9 | /* 36 ohm */
1271 2 << 6); /* 39 ohm */
1275 err = phy_write(phydev, 0x1d, 0x3);
1279 err = phy_write(phydev, 0x1e, 0x8000);
1284 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1286 return m88e1111_config_init_hwcfg_mode(
1287 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1288 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1291 static int m88e1145_config_init(struct phy_device *phydev)
1295 /* Take care of errata E0 & E1 */
1296 err = phy_write(phydev, 0x1d, 0x001b);
1300 err = phy_write(phydev, 0x1e, 0x418f);
1304 err = phy_write(phydev, 0x1d, 0x0016);
1308 err = phy_write(phydev, 0x1e, 0xa2da);
1312 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1313 err = m88e1145_config_init_rgmii(phydev);
1318 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1319 err = m88e1145_config_init_sgmii(phydev);
1324 err = marvell_of_reg_init(phydev);
1331 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1335 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1339 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1340 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1344 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1347 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1350 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1353 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1356 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1366 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1368 struct ethtool_eee eee;
1371 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1372 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1373 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1375 /* According to the Marvell data sheet EEE must be disabled for
1376 * Fast Link Down detection to work properly
1378 ret = phy_ethtool_get_eee(phydev, &eee);
1379 if (!ret && eee.eee_enabled) {
1380 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1385 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1386 else if (*msecs <= 15)
1387 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1388 else if (*msecs <= 30)
1389 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1391 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1393 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1395 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1396 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1400 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1401 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1404 static int m88e1540_get_tunable(struct phy_device *phydev,
1405 struct ethtool_tunable *tuna, void *data)
1408 case ETHTOOL_PHY_FAST_LINK_DOWN:
1409 return m88e1540_get_fld(phydev, data);
1410 case ETHTOOL_PHY_DOWNSHIFT:
1411 return m88e1011_get_downshift(phydev, data);
1417 static int m88e1540_set_tunable(struct phy_device *phydev,
1418 struct ethtool_tunable *tuna, const void *data)
1421 case ETHTOOL_PHY_FAST_LINK_DOWN:
1422 return m88e1540_set_fld(phydev, data);
1423 case ETHTOOL_PHY_DOWNSHIFT:
1424 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1430 /* The VOD can be out of specification on link up. Poke an
1431 * undocumented register, in an undocumented page, with a magic value
1434 static int m88e6390_errata(struct phy_device *phydev)
1438 err = phy_write(phydev, MII_BMCR,
1439 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1443 usleep_range(300, 400);
1445 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1449 return genphy_soft_reset(phydev);
1452 static int m88e6390_config_aneg(struct phy_device *phydev)
1456 err = m88e6390_errata(phydev);
1460 return m88e1510_config_aneg(phydev);
1464 * fiber_lpa_mod_linkmode_lpa_t
1465 * @advertising: the linkmode advertisement settings
1466 * @lpa: value of the MII_LPA register for fiber link
1468 * A small helper function that translates MII_LPA bits to linkmode LP
1469 * advertisement settings. Other bits in advertising are left
1472 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1474 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1475 advertising, lpa & LPA_1000XHALF);
1477 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1478 advertising, lpa & LPA_1000XFULL);
1481 static int marvell_read_status_page_an(struct phy_device *phydev,
1482 int fiber, int status)
1487 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1492 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1493 phydev->duplex = DUPLEX_FULL;
1495 phydev->duplex = DUPLEX_HALF;
1497 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1498 case MII_M1011_PHY_STATUS_1000:
1499 phydev->speed = SPEED_1000;
1502 case MII_M1011_PHY_STATUS_100:
1503 phydev->speed = SPEED_100;
1507 phydev->speed = SPEED_10;
1512 err = genphy_read_lpa(phydev);
1516 phy_resolve_aneg_pause(phydev);
1518 lpa = phy_read(phydev, MII_LPA);
1522 /* The fiber link is only 1000M capable */
1523 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1525 if (phydev->duplex == DUPLEX_FULL) {
1526 if (!(lpa & LPA_PAUSE_FIBER)) {
1528 phydev->asym_pause = 0;
1529 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1531 phydev->asym_pause = 1;
1534 phydev->asym_pause = 0;
1542 /* marvell_read_status_page
1545 * Check the link, then figure out the current state
1546 * by comparing what we advertise with what the link partner
1547 * advertises. Start by checking the gigabit possibilities,
1548 * then move on to 10/100.
1550 static int marvell_read_status_page(struct phy_device *phydev, int page)
1556 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1560 /* Use the generic register for copper link status,
1561 * and the PHY status register for fiber link status.
1563 if (page == MII_MARVELL_FIBER_PAGE) {
1564 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1566 err = genphy_update_link(phydev);
1571 if (page == MII_MARVELL_FIBER_PAGE)
1576 linkmode_zero(phydev->lp_advertising);
1578 phydev->asym_pause = 0;
1579 phydev->speed = SPEED_UNKNOWN;
1580 phydev->duplex = DUPLEX_UNKNOWN;
1581 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1583 if (phydev->autoneg == AUTONEG_ENABLE)
1584 err = marvell_read_status_page_an(phydev, fiber, status);
1586 err = genphy_read_status_fixed(phydev);
1591 /* marvell_read_status
1593 * Some Marvell's phys have two modes: fiber and copper.
1594 * Both need status checked.
1596 * First, check the fiber link and status.
1597 * If the fiber link is down, check the copper link and status which
1598 * will be the default value if both link are down.
1600 static int marvell_read_status(struct phy_device *phydev)
1604 /* Check the fiber mode first */
1605 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1606 phydev->supported) &&
1607 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1608 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1612 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1616 /* If the fiber link is up, it is the selected and
1617 * used link. In this case, we need to stay in the
1618 * fiber page. Please to be careful about that, avoid
1619 * to restore Copper page in other functions which
1620 * could break the behaviour for some fiber phy like
1626 /* If fiber link is down, check and save copper mode state */
1627 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1632 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1635 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1641 * Some Marvell's phys have two modes: fiber and copper.
1642 * Both need to be suspended
1644 static int marvell_suspend(struct phy_device *phydev)
1648 /* Suspend the fiber mode first */
1649 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1650 phydev->supported)) {
1651 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1655 /* With the page set, use the generic suspend */
1656 err = genphy_suspend(phydev);
1660 /* Then, the copper link */
1661 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1666 /* With the page set, use the generic suspend */
1667 return genphy_suspend(phydev);
1670 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1676 * Some Marvell's phys have two modes: fiber and copper.
1677 * Both need to be resumed
1679 static int marvell_resume(struct phy_device *phydev)
1683 /* Resume the fiber mode first */
1684 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1685 phydev->supported)) {
1686 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1690 /* With the page set, use the generic resume */
1691 err = genphy_resume(phydev);
1695 /* Then, the copper link */
1696 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1701 /* With the page set, use the generic resume */
1702 return genphy_resume(phydev);
1705 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1709 static int marvell_aneg_done(struct phy_device *phydev)
1711 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1713 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1716 static void m88e1318_get_wol(struct phy_device *phydev,
1717 struct ethtool_wolinfo *wol)
1721 wol->supported = WAKE_MAGIC;
1724 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1725 MII_88E1318S_PHY_WOL_CTRL);
1726 if (ret >= 0 && ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1727 wol->wolopts |= WAKE_MAGIC;
1730 static int m88e1318_set_wol(struct phy_device *phydev,
1731 struct ethtool_wolinfo *wol)
1733 int err = 0, oldpage;
1735 oldpage = phy_save_page(phydev);
1739 if (wol->wolopts & WAKE_MAGIC) {
1740 /* Explicitly switch to page 0x00, just to be sure */
1741 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1745 /* If WOL event happened once, the LED[2] interrupt pin
1746 * will not be cleared unless we reading the interrupt status
1747 * register. If interrupts are in use, the normal interrupt
1748 * handling will clear the WOL event. Clear the WOL event
1749 * before enabling it if !phy_interrupt_is_valid()
1751 if (!phy_interrupt_is_valid(phydev))
1752 __phy_read(phydev, MII_M1011_IEVENT);
1754 /* Enable the WOL interrupt */
1755 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1756 MII_88E1318S_PHY_CSIER_WOL_EIE);
1760 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1764 /* Setup LED[2] as interrupt pin (active low) */
1765 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1766 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1767 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1768 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1772 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1776 /* Store the device address for the magic packet */
1777 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1778 ((phydev->attached_dev->dev_addr[5] << 8) |
1779 phydev->attached_dev->dev_addr[4]));
1782 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1783 ((phydev->attached_dev->dev_addr[3] << 8) |
1784 phydev->attached_dev->dev_addr[2]));
1787 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1788 ((phydev->attached_dev->dev_addr[1] << 8) |
1789 phydev->attached_dev->dev_addr[0]));
1793 /* Clear WOL status and enable magic packet matching */
1794 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1795 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1796 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1800 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1804 /* Clear WOL status and disable magic packet matching */
1805 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1806 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1807 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1813 return phy_restore_page(phydev, oldpage, err);
1816 static int marvell_get_sset_count(struct phy_device *phydev)
1818 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1820 return ARRAY_SIZE(marvell_hw_stats);
1822 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1825 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1827 int count = marvell_get_sset_count(phydev);
1830 for (i = 0; i < count; i++) {
1831 strlcpy(data + i * ETH_GSTRING_LEN,
1832 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1836 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1838 struct marvell_hw_stat stat = marvell_hw_stats[i];
1839 struct marvell_priv *priv = phydev->priv;
1843 val = phy_read_paged(phydev, stat.page, stat.reg);
1847 val = val & ((1 << stat.bits) - 1);
1848 priv->stats[i] += val;
1849 ret = priv->stats[i];
1855 static void marvell_get_stats(struct phy_device *phydev,
1856 struct ethtool_stats *stats, u64 *data)
1858 int count = marvell_get_sset_count(phydev);
1861 for (i = 0; i < count; i++)
1862 data[i] = marvell_get_stat(phydev, i);
1865 static int marvell_vct5_wait_complete(struct phy_device *phydev)
1870 for (i = 0; i < 32; i++) {
1871 val = __phy_read(phydev, MII_VCT5_CTRL);
1875 if (val & MII_VCT5_CTRL_COMPLETE)
1879 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
1883 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
1889 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
1890 val = __phy_read(phydev, reg);
1895 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
1896 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
1898 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
1899 amplitude = -amplitude;
1901 return 1000 * amplitude / 128;
1904 static u32 marvell_vct5_distance2cm(int distance)
1906 return distance * 805 / 10;
1909 static u32 marvell_vct5_cm2distance(int cm)
1911 return cm * 10 / 805;
1914 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
1915 int distance, int pair)
1922 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
1927 reg = MII_VCT5_CTRL_ENABLE |
1928 MII_VCT5_CTRL_TX_SAME_CHANNEL |
1929 MII_VCT5_CTRL_SAMPLES_DEFAULT |
1930 MII_VCT5_CTRL_SAMPLE_POINT |
1931 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
1932 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
1936 err = marvell_vct5_wait_complete(phydev);
1940 for (i = 0; i < 4; i++) {
1941 if (pair != PHY_PAIR_ALL && i != pair)
1944 mV = marvell_vct5_amplitude(phydev, i);
1945 ethnl_cable_test_amplitude(phydev, i, mV);
1951 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
1953 struct marvell_priv *priv = phydev->priv;
1960 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
1961 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
1963 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1965 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1966 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1967 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1969 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1970 MII_VCT5_TX_PULSE_CTRL, reg);
1974 /* Reading the TDR data is very MDIO heavy. We need to optimize
1975 * access to keep the time to a minimum. So lock the bus once,
1976 * and don't release it until complete. We can then avoid having
1977 * to change the page for every access, greatly speeding things
1980 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
1984 for (distance = priv->first;
1985 distance <= priv->last;
1986 distance += priv->step) {
1987 err = marvell_vct5_amplitude_distance(phydev, distance,
1992 if (distance > TDR_SHORT_CABLE_LENGTH &&
1993 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
1994 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1995 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1996 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1997 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1998 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2005 return phy_restore_page(phydev, page, err);
2008 static int marvell_cable_test_start_common(struct phy_device *phydev)
2010 int bmcr, bmsr, ret;
2012 /* If auto-negotiation is enabled, but not complete, the cable
2013 * test never completes. So disable auto-neg.
2015 bmcr = phy_read(phydev, MII_BMCR);
2019 bmsr = phy_read(phydev, MII_BMSR);
2024 if (bmcr & BMCR_ANENABLE) {
2025 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2028 ret = genphy_soft_reset(phydev);
2033 /* If the link is up, allow it some time to go down */
2034 if (bmsr & BMSR_LSTATUS)
2040 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2042 struct marvell_priv *priv = phydev->priv;
2045 ret = marvell_cable_test_start_common(phydev);
2049 priv->cable_test_tdr = false;
2051 /* Reset the VCT5 API control to defaults, otherwise
2052 * VCT7 does not work correctly.
2054 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2056 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2057 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2058 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2059 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2063 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2064 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2068 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2070 MII_VCT7_CTRL_RUN_NOW |
2071 MII_VCT7_CTRL_CENTIMETERS);
2074 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2075 const struct phy_tdr_config *cfg)
2077 struct marvell_priv *priv = phydev->priv;
2080 priv->cable_test_tdr = true;
2081 priv->first = marvell_vct5_cm2distance(cfg->first);
2082 priv->last = marvell_vct5_cm2distance(cfg->last);
2083 priv->step = marvell_vct5_cm2distance(cfg->step);
2084 priv->pair = cfg->pair;
2086 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2089 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2093 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2098 ret = marvell_cable_test_start_common(phydev);
2102 ret = ethnl_cable_test_pulse(phydev, 1000);
2106 return ethnl_cable_test_step(phydev,
2107 marvell_vct5_distance2cm(priv->first),
2108 marvell_vct5_distance2cm(priv->last),
2109 marvell_vct5_distance2cm(priv->step));
2112 static int marvell_vct7_distance_to_length(int distance, bool meter)
2120 static bool marvell_vct7_distance_valid(int result)
2123 case MII_VCT7_RESULTS_OPEN:
2124 case MII_VCT7_RESULTS_SAME_SHORT:
2125 case MII_VCT7_RESULTS_CROSS_SHORT:
2131 static int marvell_vct7_report_length(struct phy_device *phydev,
2132 int pair, bool meter)
2137 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2138 MII_VCT7_PAIR_0_DISTANCE + pair);
2142 length = marvell_vct7_distance_to_length(ret, meter);
2144 ethnl_cable_test_fault_length(phydev, pair, length);
2149 static int marvell_vct7_cable_test_report_trans(int result)
2152 case MII_VCT7_RESULTS_OK:
2153 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2154 case MII_VCT7_RESULTS_OPEN:
2155 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2156 case MII_VCT7_RESULTS_SAME_SHORT:
2157 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2158 case MII_VCT7_RESULTS_CROSS_SHORT:
2159 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2161 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2165 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2167 int pair0, pair1, pair2, pair3;
2171 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2176 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2177 MII_VCT7_RESULTS_PAIR3_SHIFT;
2178 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2179 MII_VCT7_RESULTS_PAIR2_SHIFT;
2180 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2181 MII_VCT7_RESULTS_PAIR1_SHIFT;
2182 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2183 MII_VCT7_RESULTS_PAIR0_SHIFT;
2185 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2186 marvell_vct7_cable_test_report_trans(pair0));
2187 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2188 marvell_vct7_cable_test_report_trans(pair1));
2189 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2190 marvell_vct7_cable_test_report_trans(pair2));
2191 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2192 marvell_vct7_cable_test_report_trans(pair3));
2194 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2198 meter = ret & MII_VCT7_CTRL_METERS;
2200 if (marvell_vct7_distance_valid(pair0))
2201 marvell_vct7_report_length(phydev, 0, meter);
2202 if (marvell_vct7_distance_valid(pair1))
2203 marvell_vct7_report_length(phydev, 1, meter);
2204 if (marvell_vct7_distance_valid(pair2))
2205 marvell_vct7_report_length(phydev, 2, meter);
2206 if (marvell_vct7_distance_valid(pair3))
2207 marvell_vct7_report_length(phydev, 3, meter);
2212 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2215 struct marvell_priv *priv = phydev->priv;
2218 if (priv->cable_test_tdr) {
2219 ret = marvell_vct5_amplitude_graph(phydev);
2226 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2232 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2235 return marvell_vct7_cable_test_report(phydev);
2242 struct marvell_hwmon_ops {
2243 int (*config)(struct phy_device *phydev);
2244 int (*get_temp)(struct phy_device *phydev, long *temp);
2245 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2246 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2247 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2250 static const struct marvell_hwmon_ops *
2251 to_marvell_hwmon_ops(const struct phy_device *phydev)
2253 return phydev->drv->driver_data;
2256 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2264 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2268 /* Enable temperature sensor */
2269 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2273 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2274 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2278 /* Wait for temperature to stabilize */
2279 usleep_range(10000, 12000);
2281 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2287 /* Disable temperature sensor */
2288 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2289 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2293 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2296 return phy_restore_page(phydev, oldpage, ret);
2299 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2305 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2306 MII_88E1510_TEMP_SENSOR);
2310 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2315 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2321 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2322 MII_88E1121_MISC_TEST);
2326 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2327 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2334 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2337 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2339 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2340 MII_88E1121_MISC_TEST,
2341 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2342 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2345 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2351 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2352 MII_88E1121_MISC_TEST);
2356 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2361 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2370 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2374 /* Enable temperature sensor */
2375 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2379 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2380 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2382 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2386 /* Wait for temperature to stabilize */
2387 usleep_range(10000, 12000);
2389 /* Reading the temperature sense has an errata. You need to read
2390 * a number of times and take an average.
2392 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2393 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2396 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2399 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2400 *temp = (sum - 75) * 1000;
2402 /* Disable temperature sensor */
2403 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2407 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2408 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2410 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2413 phy_restore_page(phydev, oldpage, ret);
2418 static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2422 err = m88e1510_get_temp(phydev, temp);
2424 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2425 * T + 75, so we have to subtract another 50
2432 static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2438 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2439 MII_88E6390_TEMP_SENSOR);
2443 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2444 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2449 static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2451 temp = (temp / 1000) + 75;
2453 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2454 MII_88E6390_TEMP_SENSOR,
2455 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2456 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2459 static int m88e6393_hwmon_config(struct phy_device *phydev)
2463 err = m88e6393_set_temp_critical(phydev, 100000);
2467 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2468 MII_88E6390_MISC_TEST,
2469 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2470 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2471 MII_88E6393_MISC_TEST_RATE_MASK,
2472 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2473 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2474 MII_88E6393_MISC_TEST_RATE_2_3MS);
2477 static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2478 u32 attr, int channel, long *temp)
2480 struct phy_device *phydev = dev_get_drvdata(dev);
2481 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2482 int err = -EOPNOTSUPP;
2485 case hwmon_temp_input:
2487 err = ops->get_temp(phydev, temp);
2489 case hwmon_temp_crit:
2490 if (ops->get_temp_critical)
2491 err = ops->get_temp_critical(phydev, temp);
2493 case hwmon_temp_max_alarm:
2494 if (ops->get_temp_alarm)
2495 err = ops->get_temp_alarm(phydev, temp);
2502 static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2503 u32 attr, int channel, long temp)
2505 struct phy_device *phydev = dev_get_drvdata(dev);
2506 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2507 int err = -EOPNOTSUPP;
2510 case hwmon_temp_crit:
2511 if (ops->set_temp_critical)
2512 err = ops->set_temp_critical(phydev, temp);
2519 static umode_t marvell_hwmon_is_visible(const void *data,
2520 enum hwmon_sensor_types type,
2521 u32 attr, int channel)
2523 const struct phy_device *phydev = data;
2524 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2526 if (type != hwmon_temp)
2530 case hwmon_temp_input:
2531 return ops->get_temp ? 0444 : 0;
2532 case hwmon_temp_max_alarm:
2533 return ops->get_temp_alarm ? 0444 : 0;
2534 case hwmon_temp_crit:
2535 return (ops->get_temp_critical ? 0444 : 0) |
2536 (ops->set_temp_critical ? 0200 : 0);
2542 static u32 marvell_hwmon_chip_config[] = {
2543 HWMON_C_REGISTER_TZ,
2547 static const struct hwmon_channel_info marvell_hwmon_chip = {
2549 .config = marvell_hwmon_chip_config,
2552 /* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2553 * defined for all PHYs, because the hwmon code checks whether the attributes
2554 * exists via the .is_visible method
2556 static u32 marvell_hwmon_temp_config[] = {
2557 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2561 static const struct hwmon_channel_info marvell_hwmon_temp = {
2563 .config = marvell_hwmon_temp_config,
2566 static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2567 &marvell_hwmon_chip,
2568 &marvell_hwmon_temp,
2572 static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2573 .is_visible = marvell_hwmon_is_visible,
2574 .read = marvell_hwmon_read,
2575 .write = marvell_hwmon_write,
2578 static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2579 .ops = &marvell_hwmon_hwmon_ops,
2580 .info = marvell_hwmon_info,
2583 static int marvell_hwmon_name(struct phy_device *phydev)
2585 struct marvell_priv *priv = phydev->priv;
2586 struct device *dev = &phydev->mdio.dev;
2587 const char *devname = dev_name(dev);
2588 size_t len = strlen(devname);
2591 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2592 if (!priv->hwmon_name)
2595 for (i = j = 0; i < len && devname[i]; i++) {
2596 if (isalnum(devname[i]))
2597 priv->hwmon_name[j++] = devname[i];
2603 static int marvell_hwmon_probe(struct phy_device *phydev)
2605 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2606 struct marvell_priv *priv = phydev->priv;
2607 struct device *dev = &phydev->mdio.dev;
2613 err = marvell_hwmon_name(phydev);
2617 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2618 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
2619 if (IS_ERR(priv->hwmon_dev))
2620 return PTR_ERR(priv->hwmon_dev);
2623 err = ops->config(phydev);
2628 static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2629 .get_temp = m88e1121_get_temp,
2632 static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2633 .get_temp = m88e1510_get_temp,
2634 .get_temp_critical = m88e1510_get_temp_critical,
2635 .set_temp_critical = m88e1510_set_temp_critical,
2636 .get_temp_alarm = m88e1510_get_temp_alarm,
2639 static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2640 .get_temp = m88e6390_get_temp,
2643 static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2644 .config = m88e6393_hwmon_config,
2645 .get_temp = m88e6393_get_temp,
2646 .get_temp_critical = m88e6393_get_temp_critical,
2647 .set_temp_critical = m88e6393_set_temp_critical,
2648 .get_temp_alarm = m88e1510_get_temp_alarm,
2651 #define DEF_MARVELL_HWMON_OPS(s) (&(s))
2655 #define DEF_MARVELL_HWMON_OPS(s) NULL
2657 static int marvell_hwmon_probe(struct phy_device *phydev)
2663 static int marvell_probe(struct phy_device *phydev)
2665 struct marvell_priv *priv;
2667 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2671 phydev->priv = priv;
2673 return marvell_hwmon_probe(phydev);
2676 static struct phy_driver marvell_drivers[] = {
2678 .phy_id = MARVELL_PHY_ID_88E1101,
2679 .phy_id_mask = MARVELL_PHY_ID_MASK,
2680 .name = "Marvell 88E1101",
2681 /* PHY_GBIT_FEATURES */
2682 .probe = marvell_probe,
2683 .config_init = marvell_config_init,
2684 .config_aneg = m88e1101_config_aneg,
2685 .config_intr = marvell_config_intr,
2686 .handle_interrupt = marvell_handle_interrupt,
2687 .resume = genphy_resume,
2688 .suspend = genphy_suspend,
2689 .read_page = marvell_read_page,
2690 .write_page = marvell_write_page,
2691 .get_sset_count = marvell_get_sset_count,
2692 .get_strings = marvell_get_strings,
2693 .get_stats = marvell_get_stats,
2696 .phy_id = MARVELL_PHY_ID_88E1112,
2697 .phy_id_mask = MARVELL_PHY_ID_MASK,
2698 .name = "Marvell 88E1112",
2699 /* PHY_GBIT_FEATURES */
2700 .probe = marvell_probe,
2701 .config_init = m88e1111_config_init,
2702 .config_aneg = marvell_config_aneg,
2703 .config_intr = marvell_config_intr,
2704 .handle_interrupt = marvell_handle_interrupt,
2705 .resume = genphy_resume,
2706 .suspend = genphy_suspend,
2707 .read_page = marvell_read_page,
2708 .write_page = marvell_write_page,
2709 .get_sset_count = marvell_get_sset_count,
2710 .get_strings = marvell_get_strings,
2711 .get_stats = marvell_get_stats,
2712 .get_tunable = m88e1011_get_tunable,
2713 .set_tunable = m88e1011_set_tunable,
2716 .phy_id = MARVELL_PHY_ID_88E1111,
2717 .phy_id_mask = MARVELL_PHY_ID_MASK,
2718 .name = "Marvell 88E1111",
2719 /* PHY_GBIT_FEATURES */
2720 .probe = marvell_probe,
2721 .config_init = m88e1111_config_init,
2722 .config_aneg = m88e1111_config_aneg,
2723 .read_status = marvell_read_status,
2724 .config_intr = marvell_config_intr,
2725 .handle_interrupt = marvell_handle_interrupt,
2726 .resume = genphy_resume,
2727 .suspend = genphy_suspend,
2728 .read_page = marvell_read_page,
2729 .write_page = marvell_write_page,
2730 .get_sset_count = marvell_get_sset_count,
2731 .get_strings = marvell_get_strings,
2732 .get_stats = marvell_get_stats,
2733 .get_tunable = m88e1111_get_tunable,
2734 .set_tunable = m88e1111_set_tunable,
2737 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
2738 .phy_id_mask = MARVELL_PHY_ID_MASK,
2739 .name = "Marvell 88E1111 (Finisar)",
2740 /* PHY_GBIT_FEATURES */
2741 .probe = marvell_probe,
2742 .config_init = m88e1111_config_init,
2743 .config_aneg = m88e1111_config_aneg,
2744 .read_status = marvell_read_status,
2745 .config_intr = marvell_config_intr,
2746 .handle_interrupt = marvell_handle_interrupt,
2747 .resume = genphy_resume,
2748 .suspend = genphy_suspend,
2749 .read_page = marvell_read_page,
2750 .write_page = marvell_write_page,
2751 .get_sset_count = marvell_get_sset_count,
2752 .get_strings = marvell_get_strings,
2753 .get_stats = marvell_get_stats,
2754 .get_tunable = m88e1111_get_tunable,
2755 .set_tunable = m88e1111_set_tunable,
2758 .phy_id = MARVELL_PHY_ID_88E1118,
2759 .phy_id_mask = MARVELL_PHY_ID_MASK,
2760 .name = "Marvell 88E1118",
2761 /* PHY_GBIT_FEATURES */
2762 .probe = marvell_probe,
2763 .config_init = m88e1118_config_init,
2764 .config_aneg = m88e1118_config_aneg,
2765 .config_intr = marvell_config_intr,
2766 .handle_interrupt = marvell_handle_interrupt,
2767 .resume = genphy_resume,
2768 .suspend = genphy_suspend,
2769 .read_page = marvell_read_page,
2770 .write_page = marvell_write_page,
2771 .get_sset_count = marvell_get_sset_count,
2772 .get_strings = marvell_get_strings,
2773 .get_stats = marvell_get_stats,
2776 .phy_id = MARVELL_PHY_ID_88E1121R,
2777 .phy_id_mask = MARVELL_PHY_ID_MASK,
2778 .name = "Marvell 88E1121R",
2779 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
2780 /* PHY_GBIT_FEATURES */
2781 .probe = marvell_probe,
2782 .config_init = marvell_config_init,
2783 .config_aneg = m88e1121_config_aneg,
2784 .read_status = marvell_read_status,
2785 .config_intr = marvell_config_intr,
2786 .handle_interrupt = marvell_handle_interrupt,
2787 .resume = genphy_resume,
2788 .suspend = genphy_suspend,
2789 .read_page = marvell_read_page,
2790 .write_page = marvell_write_page,
2791 .get_sset_count = marvell_get_sset_count,
2792 .get_strings = marvell_get_strings,
2793 .get_stats = marvell_get_stats,
2794 .get_tunable = m88e1011_get_tunable,
2795 .set_tunable = m88e1011_set_tunable,
2798 .phy_id = MARVELL_PHY_ID_88E1318S,
2799 .phy_id_mask = MARVELL_PHY_ID_MASK,
2800 .name = "Marvell 88E1318S",
2801 /* PHY_GBIT_FEATURES */
2802 .probe = marvell_probe,
2803 .config_init = m88e1318_config_init,
2804 .config_aneg = m88e1318_config_aneg,
2805 .read_status = marvell_read_status,
2806 .config_intr = marvell_config_intr,
2807 .handle_interrupt = marvell_handle_interrupt,
2808 .get_wol = m88e1318_get_wol,
2809 .set_wol = m88e1318_set_wol,
2810 .resume = genphy_resume,
2811 .suspend = genphy_suspend,
2812 .read_page = marvell_read_page,
2813 .write_page = marvell_write_page,
2814 .get_sset_count = marvell_get_sset_count,
2815 .get_strings = marvell_get_strings,
2816 .get_stats = marvell_get_stats,
2819 .phy_id = MARVELL_PHY_ID_88E1145,
2820 .phy_id_mask = MARVELL_PHY_ID_MASK,
2821 .name = "Marvell 88E1145",
2822 /* PHY_GBIT_FEATURES */
2823 .probe = marvell_probe,
2824 .config_init = m88e1145_config_init,
2825 .config_aneg = m88e1101_config_aneg,
2826 .config_intr = marvell_config_intr,
2827 .handle_interrupt = marvell_handle_interrupt,
2828 .resume = genphy_resume,
2829 .suspend = genphy_suspend,
2830 .read_page = marvell_read_page,
2831 .write_page = marvell_write_page,
2832 .get_sset_count = marvell_get_sset_count,
2833 .get_strings = marvell_get_strings,
2834 .get_stats = marvell_get_stats,
2835 .get_tunable = m88e1111_get_tunable,
2836 .set_tunable = m88e1111_set_tunable,
2839 .phy_id = MARVELL_PHY_ID_88E1149R,
2840 .phy_id_mask = MARVELL_PHY_ID_MASK,
2841 .name = "Marvell 88E1149R",
2842 /* PHY_GBIT_FEATURES */
2843 .probe = marvell_probe,
2844 .config_init = m88e1149_config_init,
2845 .config_aneg = m88e1118_config_aneg,
2846 .config_intr = marvell_config_intr,
2847 .handle_interrupt = marvell_handle_interrupt,
2848 .resume = genphy_resume,
2849 .suspend = genphy_suspend,
2850 .read_page = marvell_read_page,
2851 .write_page = marvell_write_page,
2852 .get_sset_count = marvell_get_sset_count,
2853 .get_strings = marvell_get_strings,
2854 .get_stats = marvell_get_stats,
2857 .phy_id = MARVELL_PHY_ID_88E1240,
2858 .phy_id_mask = MARVELL_PHY_ID_MASK,
2859 .name = "Marvell 88E1240",
2860 /* PHY_GBIT_FEATURES */
2861 .probe = marvell_probe,
2862 .config_init = m88e1111_config_init,
2863 .config_aneg = marvell_config_aneg,
2864 .config_intr = marvell_config_intr,
2865 .handle_interrupt = marvell_handle_interrupt,
2866 .resume = genphy_resume,
2867 .suspend = genphy_suspend,
2868 .read_page = marvell_read_page,
2869 .write_page = marvell_write_page,
2870 .get_sset_count = marvell_get_sset_count,
2871 .get_strings = marvell_get_strings,
2872 .get_stats = marvell_get_stats,
2873 .get_tunable = m88e1011_get_tunable,
2874 .set_tunable = m88e1011_set_tunable,
2877 .phy_id = MARVELL_PHY_ID_88E1116R,
2878 .phy_id_mask = MARVELL_PHY_ID_MASK,
2879 .name = "Marvell 88E1116R",
2880 /* PHY_GBIT_FEATURES */
2881 .probe = marvell_probe,
2882 .config_init = m88e1116r_config_init,
2883 .config_intr = marvell_config_intr,
2884 .handle_interrupt = marvell_handle_interrupt,
2885 .resume = genphy_resume,
2886 .suspend = genphy_suspend,
2887 .read_page = marvell_read_page,
2888 .write_page = marvell_write_page,
2889 .get_sset_count = marvell_get_sset_count,
2890 .get_strings = marvell_get_strings,
2891 .get_stats = marvell_get_stats,
2892 .get_tunable = m88e1011_get_tunable,
2893 .set_tunable = m88e1011_set_tunable,
2896 .phy_id = MARVELL_PHY_ID_88E1510,
2897 .phy_id_mask = MARVELL_PHY_ID_MASK,
2898 .name = "Marvell 88E1510",
2899 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2900 .features = PHY_GBIT_FIBRE_FEATURES,
2901 .flags = PHY_POLL_CABLE_TEST,
2902 .probe = marvell_probe,
2903 .config_init = m88e1510_config_init,
2904 .config_aneg = m88e1510_config_aneg,
2905 .read_status = marvell_read_status,
2906 .config_intr = marvell_config_intr,
2907 .handle_interrupt = marvell_handle_interrupt,
2908 .get_wol = m88e1318_get_wol,
2909 .set_wol = m88e1318_set_wol,
2910 .resume = marvell_resume,
2911 .suspend = marvell_suspend,
2912 .read_page = marvell_read_page,
2913 .write_page = marvell_write_page,
2914 .get_sset_count = marvell_get_sset_count,
2915 .get_strings = marvell_get_strings,
2916 .get_stats = marvell_get_stats,
2917 .set_loopback = genphy_loopback,
2918 .get_tunable = m88e1011_get_tunable,
2919 .set_tunable = m88e1011_set_tunable,
2920 .cable_test_start = marvell_vct7_cable_test_start,
2921 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2922 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2925 .phy_id = MARVELL_PHY_ID_88E1540,
2926 .phy_id_mask = MARVELL_PHY_ID_MASK,
2927 .name = "Marvell 88E1540",
2928 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2929 /* PHY_GBIT_FEATURES */
2930 .flags = PHY_POLL_CABLE_TEST,
2931 .probe = marvell_probe,
2932 .config_init = marvell_config_init,
2933 .config_aneg = m88e1510_config_aneg,
2934 .read_status = marvell_read_status,
2935 .config_intr = marvell_config_intr,
2936 .handle_interrupt = marvell_handle_interrupt,
2937 .resume = genphy_resume,
2938 .suspend = genphy_suspend,
2939 .read_page = marvell_read_page,
2940 .write_page = marvell_write_page,
2941 .get_sset_count = marvell_get_sset_count,
2942 .get_strings = marvell_get_strings,
2943 .get_stats = marvell_get_stats,
2944 .get_tunable = m88e1540_get_tunable,
2945 .set_tunable = m88e1540_set_tunable,
2946 .cable_test_start = marvell_vct7_cable_test_start,
2947 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2948 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2951 .phy_id = MARVELL_PHY_ID_88E1545,
2952 .phy_id_mask = MARVELL_PHY_ID_MASK,
2953 .name = "Marvell 88E1545",
2954 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
2955 .probe = marvell_probe,
2956 /* PHY_GBIT_FEATURES */
2957 .flags = PHY_POLL_CABLE_TEST,
2958 .config_init = marvell_config_init,
2959 .config_aneg = m88e1510_config_aneg,
2960 .read_status = marvell_read_status,
2961 .config_intr = marvell_config_intr,
2962 .handle_interrupt = marvell_handle_interrupt,
2963 .resume = genphy_resume,
2964 .suspend = genphy_suspend,
2965 .read_page = marvell_read_page,
2966 .write_page = marvell_write_page,
2967 .get_sset_count = marvell_get_sset_count,
2968 .get_strings = marvell_get_strings,
2969 .get_stats = marvell_get_stats,
2970 .get_tunable = m88e1540_get_tunable,
2971 .set_tunable = m88e1540_set_tunable,
2972 .cable_test_start = marvell_vct7_cable_test_start,
2973 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2974 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2977 .phy_id = MARVELL_PHY_ID_88E3016,
2978 .phy_id_mask = MARVELL_PHY_ID_MASK,
2979 .name = "Marvell 88E3016",
2980 /* PHY_BASIC_FEATURES */
2981 .probe = marvell_probe,
2982 .config_init = m88e3016_config_init,
2983 .aneg_done = marvell_aneg_done,
2984 .read_status = marvell_read_status,
2985 .config_intr = marvell_config_intr,
2986 .handle_interrupt = marvell_handle_interrupt,
2987 .resume = genphy_resume,
2988 .suspend = genphy_suspend,
2989 .read_page = marvell_read_page,
2990 .write_page = marvell_write_page,
2991 .get_sset_count = marvell_get_sset_count,
2992 .get_strings = marvell_get_strings,
2993 .get_stats = marvell_get_stats,
2996 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
2997 .phy_id_mask = MARVELL_PHY_ID_MASK,
2998 .name = "Marvell 88E6341 Family",
2999 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3000 /* PHY_GBIT_FEATURES */
3001 .flags = PHY_POLL_CABLE_TEST,
3002 .probe = marvell_probe,
3003 .config_init = marvell_config_init,
3004 .config_aneg = m88e6390_config_aneg,
3005 .read_status = marvell_read_status,
3006 .config_intr = marvell_config_intr,
3007 .handle_interrupt = marvell_handle_interrupt,
3008 .resume = genphy_resume,
3009 .suspend = genphy_suspend,
3010 .read_page = marvell_read_page,
3011 .write_page = marvell_write_page,
3012 .get_sset_count = marvell_get_sset_count,
3013 .get_strings = marvell_get_strings,
3014 .get_stats = marvell_get_stats,
3015 .get_tunable = m88e1540_get_tunable,
3016 .set_tunable = m88e1540_set_tunable,
3017 .cable_test_start = marvell_vct7_cable_test_start,
3018 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3019 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3022 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3023 .phy_id_mask = MARVELL_PHY_ID_MASK,
3024 .name = "Marvell 88E6390 Family",
3025 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
3026 /* PHY_GBIT_FEATURES */
3027 .flags = PHY_POLL_CABLE_TEST,
3028 .probe = marvell_probe,
3029 .config_init = marvell_config_init,
3030 .config_aneg = m88e6390_config_aneg,
3031 .read_status = marvell_read_status,
3032 .config_intr = marvell_config_intr,
3033 .handle_interrupt = marvell_handle_interrupt,
3034 .resume = genphy_resume,
3035 .suspend = genphy_suspend,
3036 .read_page = marvell_read_page,
3037 .write_page = marvell_write_page,
3038 .get_sset_count = marvell_get_sset_count,
3039 .get_strings = marvell_get_strings,
3040 .get_stats = marvell_get_stats,
3041 .get_tunable = m88e1540_get_tunable,
3042 .set_tunable = m88e1540_set_tunable,
3043 .cable_test_start = marvell_vct7_cable_test_start,
3044 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3045 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3048 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3049 .phy_id_mask = MARVELL_PHY_ID_MASK,
3050 .name = "Marvell 88E6393 Family",
3051 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3052 /* PHY_GBIT_FEATURES */
3053 .flags = PHY_POLL_CABLE_TEST,
3054 .probe = marvell_probe,
3055 .config_init = marvell_config_init,
3056 .config_aneg = m88e1510_config_aneg,
3057 .read_status = marvell_read_status,
3058 .config_intr = marvell_config_intr,
3059 .handle_interrupt = marvell_handle_interrupt,
3060 .resume = genphy_resume,
3061 .suspend = genphy_suspend,
3062 .read_page = marvell_read_page,
3063 .write_page = marvell_write_page,
3064 .get_sset_count = marvell_get_sset_count,
3065 .get_strings = marvell_get_strings,
3066 .get_stats = marvell_get_stats,
3067 .get_tunable = m88e1540_get_tunable,
3068 .set_tunable = m88e1540_set_tunable,
3069 .cable_test_start = marvell_vct7_cable_test_start,
3070 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3071 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3074 .phy_id = MARVELL_PHY_ID_88E1340S,
3075 .phy_id_mask = MARVELL_PHY_ID_MASK,
3076 .name = "Marvell 88E1340S",
3077 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3078 .probe = marvell_probe,
3079 /* PHY_GBIT_FEATURES */
3080 .config_init = marvell_config_init,
3081 .config_aneg = m88e1510_config_aneg,
3082 .read_status = marvell_read_status,
3083 .config_intr = marvell_config_intr,
3084 .handle_interrupt = marvell_handle_interrupt,
3085 .resume = genphy_resume,
3086 .suspend = genphy_suspend,
3087 .read_page = marvell_read_page,
3088 .write_page = marvell_write_page,
3089 .get_sset_count = marvell_get_sset_count,
3090 .get_strings = marvell_get_strings,
3091 .get_stats = marvell_get_stats,
3092 .get_tunable = m88e1540_get_tunable,
3093 .set_tunable = m88e1540_set_tunable,
3096 .phy_id = MARVELL_PHY_ID_88E1548P,
3097 .phy_id_mask = MARVELL_PHY_ID_MASK,
3098 .name = "Marvell 88E1548P",
3099 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3100 .probe = marvell_probe,
3101 .features = PHY_GBIT_FIBRE_FEATURES,
3102 .config_init = marvell_config_init,
3103 .config_aneg = m88e1510_config_aneg,
3104 .read_status = marvell_read_status,
3105 .config_intr = marvell_config_intr,
3106 .handle_interrupt = marvell_handle_interrupt,
3107 .resume = genphy_resume,
3108 .suspend = genphy_suspend,
3109 .read_page = marvell_read_page,
3110 .write_page = marvell_write_page,
3111 .get_sset_count = marvell_get_sset_count,
3112 .get_strings = marvell_get_strings,
3113 .get_stats = marvell_get_stats,
3114 .get_tunable = m88e1540_get_tunable,
3115 .set_tunable = m88e1540_set_tunable,
3119 module_phy_driver(marvell_drivers);
3121 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3122 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3123 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3124 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3125 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3126 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3127 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3128 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3129 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3130 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3131 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3132 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3133 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3134 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3135 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3136 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3137 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3138 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3139 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
3140 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3141 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3145 MODULE_DEVICE_TABLE(mdio, marvell_tbl);