drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "pch_gbe.h"
  21 #include "pch_gbe_api.h"
  22 #include <linux/module.h>
  23 #include <linux/net_tstamp.h>
  24 #include <linux/ptp_classify.h>
  25 #include <linux/gpio.h>
  26
  27 #define DRV_VERSION     "1.01"
  28 const char pch_driver_version[] = DRV_VERSION;
  29
  30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  31 #define PCH_GBE_MAR_ENTRIES             16
  32 #define PCH_GBE_SHORT_PKT               64
  33 #define DSC_INIT16                      0xC000
  34 #define PCH_GBE_DMA_ALIGN               0
  35 #define PCH_GBE_DMA_PADDING             2
  36 #define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  37 #define PCH_GBE_PCI_BAR                 1
  38 #define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  39
  40 /* Macros for ML7223 */
  41 #define PCI_VENDOR_ID_ROHM                      0x10db
  42 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  43
  44 /* Macros for ML7831 */
  45 #define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  46
  47 #define PCH_GBE_TX_WEIGHT         64
  48 #define PCH_GBE_RX_WEIGHT         64
  49 #define PCH_GBE_RX_BUFFER_WRITE   16
  50
  51 /* Initialize the wake-on-LAN settings */
  52 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  53
  54 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  55         PCH_GBE_CHIP_TYPE_INTERNAL | \
  56         PCH_GBE_RGMII_MODE_RGMII     \
  57         )
  58
  59 /* Ethertype field values */
  60 #define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  61 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  62 #define PCH_GBE_FRAME_SIZE_2048         2048
  63 #define PCH_GBE_FRAME_SIZE_4096         4096
  64 #define PCH_GBE_FRAME_SIZE_8192         8192
  65
  66 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  67 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  68 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  69 #define PCH_GBE_DESC_UNUSED(R) \
  70         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  71         (R)->next_to_clean - (R)->next_to_use - 1)
  72
  73 /* Pause packet value */
  74 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  75 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  76 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  77 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  78
  79
  80 /* This defines the bits that are set in the Interrupt Mask
  81  * Set/Read Register.  Each bit is documented below:
  82  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  83  *   o TXDW   = Transmit Descriptor Written Back
  84  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  85  *   o RXSEQ  = Receive Sequence Error
  86  *   o LSC    = Link Status Change
  87  */
  88 #define PCH_GBE_INT_ENABLE_MASK ( \
  89         PCH_GBE_INT_RX_DMA_CMPLT |    \
  90         PCH_GBE_INT_RX_DSC_EMP   |    \
  91         PCH_GBE_INT_RX_FIFO_ERR  |    \
  92         PCH_GBE_INT_WOL_DET      |    \
  93         PCH_GBE_INT_TX_CMPLT          \
  94         )
  95
  96 #define PCH_GBE_INT_DISABLE_ALL         0
  97
  98 /* Macros for ieee1588 */
  99 /* 0x40 Time Synchronization Channel Control Register Bits */
 100 #define MASTER_MODE   (1<<0)
 101 #define SLAVE_MODE    (0)
 102 #define V2_MODE       (1<<31)
 103 #define CAP_MODE0     (0)
 104 #define CAP_MODE2     (1<<17)
 105
 106 /* 0x44 Time Synchronization Channel Event Register Bits */
 107 #define TX_SNAPSHOT_LOCKED (1<<0)
 108 #define RX_SNAPSHOT_LOCKED (1<<1)
 109
 110 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 111 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 112
 113 #define MINNOW_PHY_RESET_GPIO           13
 114
 115 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 116 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 117                                int data);
 118 static void pch_gbe_set_multi(struct net_device *netdev);
 119
 120 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 121 {
 122         u8 *data = skb->data;
 123         unsigned int offset;
 124         u16 *hi, *id;
 125         u32 lo;
 126
 127         if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
 128                 return 0;
 129
 130         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 131
 132         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 133                 return 0;
 134
 135         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 136         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 137
 138         memcpy(&lo, &hi[1], sizeof(lo));
 139
 140         return (uid_hi == *hi &&
 141                 uid_lo == lo &&
 142                 seqid  == *id);
 143 }
 144
 145 static void
 146 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 147 {
 148         struct skb_shared_hwtstamps *shhwtstamps;
 149         struct pci_dev *pdev;
 150         u64 ns;
 151         u32 hi, lo, val;
 152         u16 uid, seq;
 153
 154         if (!adapter->hwts_rx_en)
 155                 return;
 156
 157         /* Get ieee1588's dev information */
 158         pdev = adapter->ptp_pdev;
 159
 160         val = pch_ch_event_read(pdev);
 161
 162         if (!(val & RX_SNAPSHOT_LOCKED))
 163                 return;
 164
 165         lo = pch_src_uuid_lo_read(pdev);
 166         hi = pch_src_uuid_hi_read(pdev);
 167
 168         uid = hi & 0xffff;
 169         seq = (hi >> 16) & 0xffff;
 170
 171         if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 172                 goto out;
 173
 174         ns = pch_rx_snap_read(pdev);
 175
 176         shhwtstamps = skb_hwtstamps(skb);
 177         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 178         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 179 out:
 180         pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 181 }
 182
 183 static void
 184 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 185 {
 186         struct skb_shared_hwtstamps shhwtstamps;
 187         struct pci_dev *pdev;
 188         struct skb_shared_info *shtx;
 189         u64 ns;
 190         u32 cnt, val;
 191
 192         shtx = skb_shinfo(skb);
 193         if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 194                 return;
 195
 196         shtx->tx_flags |= SKBTX_IN_PROGRESS;
 197
 198         /* Get ieee1588's dev information */
 199         pdev = adapter->ptp_pdev;
 200
 201         /*
 202          * This really stinks, but we have to poll for the Tx time stamp.
 203          */
 204         for (cnt = 0; cnt < 100; cnt++) {
 205                 val = pch_ch_event_read(pdev);
 206                 if (val & TX_SNAPSHOT_LOCKED)
 207                         break;
 208                 udelay(1);
 209         }
 210         if (!(val & TX_SNAPSHOT_LOCKED)) {
 211                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 212                 return;
 213         }
 214
 215         ns = pch_tx_snap_read(pdev);
 216
 217         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 218         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 219         skb_tstamp_tx(skb, &shhwtstamps);
 220
 221         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 222 }
 223
 224 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 225 {
 226         struct hwtstamp_config cfg;
 227         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 228         struct pci_dev *pdev;
 229         u8 station[20];
 230
 231         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 232                 return -EFAULT;
 233
 234         if (cfg.flags) /* reserved for future extensions */
 235                 return -EINVAL;
 236
 237         /* Get ieee1588's dev information */
 238         pdev = adapter->ptp_pdev;
 239
 240         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 241                 return -ERANGE;
 242
 243         switch (cfg.rx_filter) {
 244         case HWTSTAMP_FILTER_NONE:
 245                 adapter->hwts_rx_en = 0;
 246                 break;
 247         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 248                 adapter->hwts_rx_en = 0;
 249                 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 250                 break;
 251         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 252                 adapter->hwts_rx_en = 1;
 253                 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 254                 break;
 255         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 256                 adapter->hwts_rx_en = 1;
 257                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 258                 strcpy(station, PTP_L4_MULTICAST_SA);
 259                 pch_set_station_address(station, pdev);
 260                 break;
 261         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 262                 adapter->hwts_rx_en = 1;
 263                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 264                 strcpy(station, PTP_L2_MULTICAST_SA);
 265                 pch_set_station_address(station, pdev);
 266                 break;
 267         default:
 268                 return -ERANGE;
 269         }
 270
 271         adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 272
 273         /* Clear out any old time stamps. */
 274         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 275
 276         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 277 }
 278
 279 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 280 {
 281         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 282 }
 283
 284 /**
 285  * pch_gbe_mac_read_mac_addr - Read MAC address
 286  * @hw:             Pointer to the HW structure
 287  * Returns:
 288  *      0:                      Successful.
 289  */
 290 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 291 {
 292         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 293         u32  adr1a, adr1b;
 294
 295         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 296         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 297
 298         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 299         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 300         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 301         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 302         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 303         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 304
 305         netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 306         return 0;
 307 }
 308
 309 /**
 310  * pch_gbe_wait_clr_bit - Wait to clear a bit
 311  * @reg:        Pointer of register
 312  * @busy:       Busy bit
 313  */
 314 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 315 {
 316         u32 tmp;
 317
 318         /* wait busy */
 319         tmp = 1000;
 320         while ((ioread32(reg) & bit) && --tmp)
 321                 cpu_relax();
 322         if (!tmp)
 323                 pr_err("Error: busy bit is not cleared\n");
 324 }
 325
 326 /**
 327  * pch_gbe_mac_mar_set - Set MAC address register
 328  * @hw:     Pointer to the HW structure
 329  * @addr:   Pointer to the MAC address
 330  * @index:  MAC address array register
 331  */
 332 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 333 {
 334         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 335         u32 mar_low, mar_high, adrmask;
 336
 337         netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 338
 339         /*
 340          * HW expects these in little endian so we reverse the byte order
 341          * from network order (big endian) to little endian
 342          */
 343         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 344                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 345         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 346         /* Stop the MAC Address of index. */
 347         adrmask = ioread32(&hw->reg->ADDR_MASK);
 348         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 349         /* wait busy */
 350         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 351         /* Set the MAC address to the MAC address 1A/1B register */
 352         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 353         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 354         /* Start the MAC address of index */
 355         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 356         /* wait busy */
 357         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 358 }
 359
 360 /**
 361  * pch_gbe_mac_reset_hw - Reset hardware
 362  * @hw: Pointer to the HW structure
 363  */
 364 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 365 {
 366         /* Read the MAC address. and store to the private data */
 367         pch_gbe_mac_read_mac_addr(hw);
 368         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 369 #ifdef PCH_GBE_MAC_IFOP_RGMII
 370         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 371 #endif
 372         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 373         /* Setup the receive addresses */
 374         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 375         return;
 376 }
 377
 378 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 379 {
 380         u32 rctl;
 381         /* Disables Receive MAC */
 382         rctl = ioread32(&hw->reg->MAC_RX_EN);
 383         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 384 }
 385
 386 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 387 {
 388         u32 rctl;
 389         /* Enables Receive MAC */
 390         rctl = ioread32(&hw->reg->MAC_RX_EN);
 391         iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 392 }
 393
 394 /**
 395  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 396  * @hw: Pointer to the HW structure
 397  * @mar_count: Receive address registers
 398  */
 399 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 400 {
 401         u32 i;
 402
 403         /* Setup the receive address */
 404         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 405
 406         /* Zero out the other receive addresses */
 407         for (i = 1; i < mar_count; i++) {
 408                 iowrite32(0, &hw->reg->mac_adr[i].high);
 409                 iowrite32(0, &hw->reg->mac_adr[i].low);
 410         }
 411         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 412         /* wait busy */
 413         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 414 }
 415
 416
 417 /**
 418  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 419  * @hw:             Pointer to the HW structure
 420  * @mc_addr_list:   Array of multicast addresses to program
 421  * @mc_addr_count:  Number of multicast addresses to program
 422  * @mar_used_count: The first MAC Address register free to program
 423  * @mar_total_num:  Total number of supported MAC Address Registers
 424  */
 425 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 426                                             u8 *mc_addr_list, u32 mc_addr_count,
 427                                             u32 mar_used_count, u32 mar_total_num)
 428 {
 429         u32 i, adrmask;
 430
 431         /* Load the first set of multicast addresses into the exact
 432          * filters (RAR).  If there are not enough to fill the RAR
 433          * array, clear the filters.
 434          */
 435         for (i = mar_used_count; i < mar_total_num; i++) {
 436                 if (mc_addr_count) {
 437                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 438                         mc_addr_count--;
 439                         mc_addr_list += ETH_ALEN;
 440                 } else {
 441                         /* Clear MAC address mask */
 442                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 443                         iowrite32((adrmask | (0x0001 << i)),
 444                                         &hw->reg->ADDR_MASK);
 445                         /* wait busy */
 446                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 447                         /* Clear MAC address */
 448                         iowrite32(0, &hw->reg->mac_adr[i].high);
 449                         iowrite32(0, &hw->reg->mac_adr[i].low);
 450                 }
 451         }
 452 }
 453
 454 /**
 455  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 456  * @hw:             Pointer to the HW structure
 457  * Returns:
 458  *      0:                      Successful.
 459  *      Negative value:         Failed.
 460  */
 461 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 462 {
 463         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 464         struct pch_gbe_mac_info *mac = &hw->mac;
 465         u32 rx_fctrl;
 466
 467         netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 468
 469         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 470
 471         switch (mac->fc) {
 472         case PCH_GBE_FC_NONE:
 473                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 474                 mac->tx_fc_enable = false;
 475                 break;
 476         case PCH_GBE_FC_RX_PAUSE:
 477                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 478                 mac->tx_fc_enable = false;
 479                 break;
 480         case PCH_GBE_FC_TX_PAUSE:
 481                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 482                 mac->tx_fc_enable = true;
 483                 break;
 484         case PCH_GBE_FC_FULL:
 485                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 486                 mac->tx_fc_enable = true;
 487                 break;
 488         default:
 489                 netdev_err(adapter->netdev,
 490                            "Flow control param set incorrectly\n");
 491                 return -EINVAL;
 492         }
 493         if (mac->link_duplex == DUPLEX_HALF)
 494                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 495         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 496         netdev_dbg(adapter->netdev,
 497                    "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 498                    ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 499         return 0;
 500 }
 501
 502 /**
 503  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 504  * @hw:     Pointer to the HW structure
 505  * @wu_evt: Wake up event
 506  */
 507 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 508 {
 509         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 510         u32 addr_mask;
 511
 512         netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 513                    wu_evt, ioread32(&hw->reg->ADDR_MASK));
 514
 515         if (wu_evt) {
 516                 /* Set Wake-On-Lan address mask */
 517                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 518                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 519                 /* wait busy */
 520                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 521                 iowrite32(0, &hw->reg->WOL_ST);
 522                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 523                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 524                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 525         } else {
 526                 iowrite32(0, &hw->reg->WOL_CTRL);
 527                 iowrite32(0, &hw->reg->WOL_ST);
 528         }
 529         return;
 530 }
 531
 532 /**
 533  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 534  * @hw:   Pointer to the HW structure
 535  * @addr: Address of PHY
 536  * @dir:  Operetion. (Write or Read)
 537  * @reg:  Access register of PHY
 538  * @data: Write data.
 539  *
 540  * Returns: Read date.
 541  */
 542 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 543                         u16 data)
 544 {
 545         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 546         u32 data_out = 0;
 547         unsigned int i;
 548         unsigned long flags;
 549
 550         spin_lock_irqsave(&hw->miim_lock, flags);
 551
 552         for (i = 100; i; --i) {
 553                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 554                         break;
 555                 udelay(20);
 556         }
 557         if (i == 0) {
 558                 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 559                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 560                 return 0;       /* No way to indicate timeout error */
 561         }
 562         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 563                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 564                   dir | data), &hw->reg->MIIM);
 565         for (i = 0; i < 100; i++) {
 566                 udelay(20);
 567                 data_out = ioread32(&hw->reg->MIIM);
 568                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 569                         break;
 570         }
 571         spin_unlock_irqrestore(&hw->miim_lock, flags);
 572
 573         netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 574                    dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 575                    dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 576         return (u16) data_out;
 577 }
 578
 579 /**
 580  * pch_gbe_mac_set_pause_packet - Set pause packet
 581  * @hw:   Pointer to the HW structure
 582  */
 583 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 584 {
 585         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 586         unsigned long tmp2, tmp3;
 587
 588         /* Set Pause packet */
 589         tmp2 = hw->mac.addr[1];
 590         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 591         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 592
 593         tmp3 = hw->mac.addr[5];
 594         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 595         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 596         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 597
 598         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 599         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 600         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 601         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 602         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 603
 604         /* Transmit Pause Packet */
 605         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 606
 607         netdev_dbg(adapter->netdev,
 608                    "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 609                    ioread32(&hw->reg->PAUSE_PKT1),
 610                    ioread32(&hw->reg->PAUSE_PKT2),
 611                    ioread32(&hw->reg->PAUSE_PKT3),
 612                    ioread32(&hw->reg->PAUSE_PKT4),
 613                    ioread32(&hw->reg->PAUSE_PKT5));
 614
 615         return;
 616 }
 617
 618
 619 /**
 620  * pch_gbe_alloc_queues - Allocate memory for all rings
 621  * @adapter:  Board private structure to initialize
 622  * Returns:
 623  *      0:      Successfully
 624  *      Negative value: Failed
 625  */
 626 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 627 {
 628         adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 629                                         sizeof(*adapter->tx_ring), GFP_KERNEL);
 630         if (!adapter->tx_ring)
 631                 return -ENOMEM;
 632
 633         adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 634                                         sizeof(*adapter->rx_ring), GFP_KERNEL);
 635         if (!adapter->rx_ring)
 636                 return -ENOMEM;
 637         return 0;
 638 }
 639
 640 /**
 641  * pch_gbe_init_stats - Initialize status
 642  * @adapter:  Board private structure to initialize
 643  */
 644 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 645 {
 646         memset(&adapter->stats, 0, sizeof(adapter->stats));
 647         return;
 648 }
 649
 650 /**
 651  * pch_gbe_init_phy - Initialize PHY
 652  * @adapter:  Board private structure to initialize
 653  * Returns:
 654  *      0:      Successfully
 655  *      Negative value: Failed
 656  */
 657 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 658 {
 659         struct net_device *netdev = adapter->netdev;
 660         u32 addr;
 661         u16 bmcr, stat;
 662
 663         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 664         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 665                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 666                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 667                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 668                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 669                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 670                         break;
 671         }
 672         adapter->hw.phy.addr = adapter->mii.phy_id;
 673         netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 674         if (addr == PCH_GBE_PHY_REGS_LEN)
 675                 return -EAGAIN;
 676         /* Selected the phy and isolate the rest */
 677         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 678                 if (addr != adapter->mii.phy_id) {
 679                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 680                                            BMCR_ISOLATE);
 681                 } else {
 682                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 683                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 684                                            bmcr & ~BMCR_ISOLATE);
 685                 }
 686         }
 687
 688         /* MII setup */
 689         adapter->mii.phy_id_mask = 0x1F;
 690         adapter->mii.reg_num_mask = 0x1F;
 691         adapter->mii.dev = adapter->netdev;
 692         adapter->mii.mdio_read = pch_gbe_mdio_read;
 693         adapter->mii.mdio_write = pch_gbe_mdio_write;
 694         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 695         return 0;
 696 }
 697
 698 /**
 699  * pch_gbe_mdio_read - The read function for mii
 700  * @netdev: Network interface device structure
 701  * @addr:   Phy ID
 702  * @reg:    Access location
 703  * Returns:
 704  *      0:      Successfully
 705  *      Negative value: Failed
 706  */
 707 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 708 {
 709         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 710         struct pch_gbe_hw *hw = &adapter->hw;
 711
 712         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 713                                      (u16) 0);
 714 }
 715
 716 /**
 717  * pch_gbe_mdio_write - The write function for mii
 718  * @netdev: Network interface device structure
 719  * @addr:   Phy ID (not used)
 720  * @reg:    Access location
 721  * @data:   Write data
 722  */
 723 static void pch_gbe_mdio_write(struct net_device *netdev,
 724                                int addr, int reg, int data)
 725 {
 726         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 727         struct pch_gbe_hw *hw = &adapter->hw;
 728
 729         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 730 }
 731
 732 /**
 733  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 734  * @work:  Pointer of board private structure
 735  */
 736 static void pch_gbe_reset_task(struct work_struct *work)
 737 {
 738         struct pch_gbe_adapter *adapter;
 739         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 740
 741         rtnl_lock();
 742         pch_gbe_reinit_locked(adapter);
 743         rtnl_unlock();
 744 }
 745
 746 /**
 747  * pch_gbe_reinit_locked- Re-initialization
 748  * @adapter:  Board private structure
 749  */
 750 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 751 {
 752         pch_gbe_down(adapter);
 753         pch_gbe_up(adapter);
 754 }
 755
 756 /**
 757  * pch_gbe_reset - Reset GbE
 758  * @adapter:  Board private structure
 759  */
 760 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 761 {
 762         struct net_device *netdev = adapter->netdev;
 763
 764         pch_gbe_mac_reset_hw(&adapter->hw);
 765         /* reprogram multicast address register after reset */
 766         pch_gbe_set_multi(netdev);
 767         /* Setup the receive address. */
 768         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 769         if (pch_gbe_hal_init_hw(&adapter->hw))
 770                 netdev_err(netdev, "Hardware Error\n");
 771 }
 772
 773 /**
 774  * pch_gbe_free_irq - Free an interrupt
 775  * @adapter:  Board private structure
 776  */
 777 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 778 {
 779         struct net_device *netdev = adapter->netdev;
 780
 781         free_irq(adapter->irq, netdev);
 782         pci_free_irq_vectors(adapter->pdev);
 783 }
 784
 785 /**
 786  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 787  * @adapter:  Board private structure
 788  */
 789 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 790 {
 791         struct pch_gbe_hw *hw = &adapter->hw;
 792
 793         atomic_inc(&adapter->irq_sem);
 794         iowrite32(0, &hw->reg->INT_EN);
 795         ioread32(&hw->reg->INT_ST);
 796         synchronize_irq(adapter->irq);
 797
 798         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 799                    ioread32(&hw->reg->INT_EN));
 800 }
 801
 802 /**
 803  * pch_gbe_irq_enable - Enable default interrupt generation settings
 804  * @adapter:  Board private structure
 805  */
 806 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 807 {
 808         struct pch_gbe_hw *hw = &adapter->hw;
 809
 810         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 811                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 812         ioread32(&hw->reg->INT_ST);
 813         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 814                    ioread32(&hw->reg->INT_EN));
 815 }
 816
 817
 818
 819 /**
 820  * pch_gbe_setup_tctl - configure the Transmit control registers
 821  * @adapter:  Board private structure
 822  */
 823 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 824 {
 825         struct pch_gbe_hw *hw = &adapter->hw;
 826         u32 tx_mode, tcpip;
 827
 828         tx_mode = PCH_GBE_TM_LONG_PKT |
 829                 PCH_GBE_TM_ST_AND_FD |
 830                 PCH_GBE_TM_SHORT_PKT |
 831                 PCH_GBE_TM_TH_TX_STRT_8 |
 832                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 833
 834         iowrite32(tx_mode, &hw->reg->TX_MODE);
 835
 836         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 837         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 838         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 839         return;
 840 }
 841
 842 /**
 843  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 844  * @adapter:  Board private structure
 845  */
 846 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 847 {
 848         struct pch_gbe_hw *hw = &adapter->hw;
 849         u32 tdba, tdlen, dctrl;
 850
 851         netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 852                    (unsigned long long)adapter->tx_ring->dma,
 853                    adapter->tx_ring->size);
 854
 855         /* Setup the HW Tx Head and Tail descriptor pointers */
 856         tdba = adapter->tx_ring->dma;
 857         tdlen = adapter->tx_ring->size - 0x10;
 858         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 859         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 860         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 861
 862         /* Enables Transmission DMA */
 863         dctrl = ioread32(&hw->reg->DMA_CTRL);
 864         dctrl |= PCH_GBE_TX_DMA_EN;
 865         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 866 }
 867
 868 /**
 869  * pch_gbe_setup_rctl - Configure the receive control registers
 870  * @adapter:  Board private structure
 871  */
 872 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 873 {
 874         struct pch_gbe_hw *hw = &adapter->hw;
 875         u32 rx_mode, tcpip;
 876
 877         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 878         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 879
 880         iowrite32(rx_mode, &hw->reg->RX_MODE);
 881
 882         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 883
 884         tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 885         tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 886         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 887         return;
 888 }
 889
 890 /**
 891  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 892  * @adapter:  Board private structure
 893  */
 894 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 895 {
 896         struct pch_gbe_hw *hw = &adapter->hw;
 897         u32 rdba, rdlen, rxdma;
 898
 899         netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 900                    (unsigned long long)adapter->rx_ring->dma,
 901                    adapter->rx_ring->size);
 902
 903         pch_gbe_mac_force_mac_fc(hw);
 904
 905         pch_gbe_disable_mac_rx(hw);
 906
 907         /* Disables Receive DMA */
 908         rxdma = ioread32(&hw->reg->DMA_CTRL);
 909         rxdma &= ~PCH_GBE_RX_DMA_EN;
 910         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 911
 912         netdev_dbg(adapter->netdev,
 913                    "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 914                    ioread32(&hw->reg->MAC_RX_EN),
 915                    ioread32(&hw->reg->DMA_CTRL));
 916
 917         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 918          * the Base and Length of the Rx Descriptor Ring */
 919         rdba = adapter->rx_ring->dma;
 920         rdlen = adapter->rx_ring->size - 0x10;
 921         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 922         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 923         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 924 }
 925
 926 /**
 927  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 928  * @adapter:     Board private structure
 929  * @buffer_info: Buffer information structure
 930  */
 931 static void pch_gbe_unmap_and_free_tx_resource(
 932         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 933 {
 934         if (buffer_info->mapped) {
 935                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 936                                  buffer_info->length, DMA_TO_DEVICE);
 937                 buffer_info->mapped = false;
 938         }
 939         if (buffer_info->skb) {
 940                 dev_kfree_skb_any(buffer_info->skb);
 941                 buffer_info->skb = NULL;
 942         }
 943 }
 944
 945 /**
 946  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 947  * @adapter:      Board private structure
 948  * @buffer_info:  Buffer information structure
 949  */
 950 static void pch_gbe_unmap_and_free_rx_resource(
 951                                         struct pch_gbe_adapter *adapter,
 952                                         struct pch_gbe_buffer *buffer_info)
 953 {
 954         if (buffer_info->mapped) {
 955                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 956                                  buffer_info->length, DMA_FROM_DEVICE);
 957                 buffer_info->mapped = false;
 958         }
 959         if (buffer_info->skb) {
 960                 dev_kfree_skb_any(buffer_info->skb);
 961                 buffer_info->skb = NULL;
 962         }
 963 }
 964
 965 /**
 966  * pch_gbe_clean_tx_ring - Free Tx Buffers
 967  * @adapter:  Board private structure
 968  * @tx_ring:  Ring to be cleaned
 969  */
 970 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 971                                    struct pch_gbe_tx_ring *tx_ring)
 972 {
 973         struct pch_gbe_hw *hw = &adapter->hw;
 974         struct pch_gbe_buffer *buffer_info;
 975         unsigned long size;
 976         unsigned int i;
 977
 978         /* Free all the Tx ring sk_buffs */
 979         for (i = 0; i < tx_ring->count; i++) {
 980                 buffer_info = &tx_ring->buffer_info[i];
 981                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 982         }
 983         netdev_dbg(adapter->netdev,
 984                    "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 985
 986         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 987         memset(tx_ring->buffer_info, 0, size);
 988
 989         /* Zero out the descriptor ring */
 990         memset(tx_ring->desc, 0, tx_ring->size);
 991         tx_ring->next_to_use = 0;
 992         tx_ring->next_to_clean = 0;
 993         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
 994         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
 995 }
 996
 997 /**
 998  * pch_gbe_clean_rx_ring - Free Rx Buffers
 999  * @adapter:  Board private structure
1000  * @rx_ring:  Ring to free buffers from
1001  */
1002 static void
1003 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1004                       struct pch_gbe_rx_ring *rx_ring)
1005 {
1006         struct pch_gbe_hw *hw = &adapter->hw;
1007         struct pch_gbe_buffer *buffer_info;
1008         unsigned long size;
1009         unsigned int i;
1010
1011         /* Free all the Rx ring sk_buffs */
1012         for (i = 0; i < rx_ring->count; i++) {
1013                 buffer_info = &rx_ring->buffer_info[i];
1014                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1015         }
1016         netdev_dbg(adapter->netdev,
1017                    "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1018         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1019         memset(rx_ring->buffer_info, 0, size);
1020
1021         /* Zero out the descriptor ring */
1022         memset(rx_ring->desc, 0, rx_ring->size);
1023         rx_ring->next_to_clean = 0;
1024         rx_ring->next_to_use = 0;
1025         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1026         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1027 }
1028
1029 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1030                                     u16 duplex)
1031 {
1032         struct pch_gbe_hw *hw = &adapter->hw;
1033         unsigned long rgmii = 0;
1034
1035         /* Set the RGMII control. */
1036 #ifdef PCH_GBE_MAC_IFOP_RGMII
1037         switch (speed) {
1038         case SPEED_10:
1039                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1040                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1041                 break;
1042         case SPEED_100:
1043                 rgmii = (PCH_GBE_RGMII_RATE_25M |
1044                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1045                 break;
1046         case SPEED_1000:
1047                 rgmii = (PCH_GBE_RGMII_RATE_125M |
1048                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1049                 break;
1050         }
1051         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1052 #else   /* GMII */
1053         rgmii = 0;
1054         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1055 #endif
1056 }
1057 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1058                               u16 duplex)
1059 {
1060         struct net_device *netdev = adapter->netdev;
1061         struct pch_gbe_hw *hw = &adapter->hw;
1062         unsigned long mode = 0;
1063
1064         /* Set the communication mode */
1065         switch (speed) {
1066         case SPEED_10:
1067                 mode = PCH_GBE_MODE_MII_ETHER;
1068                 netdev->tx_queue_len = 10;
1069                 break;
1070         case SPEED_100:
1071                 mode = PCH_GBE_MODE_MII_ETHER;
1072                 netdev->tx_queue_len = 100;
1073                 break;
1074         case SPEED_1000:
1075                 mode = PCH_GBE_MODE_GMII_ETHER;
1076                 break;
1077         }
1078         if (duplex == DUPLEX_FULL)
1079                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1080         else
1081                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1082         iowrite32(mode, &hw->reg->MODE);
1083 }
1084
1085 /**
1086  * pch_gbe_watchdog - Watchdog process
1087  * @data:  Board private structure
1088  */
1089 static void pch_gbe_watchdog(struct timer_list *t)
1090 {
1091         struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1092                                                      watchdog_timer);
1093         struct net_device *netdev = adapter->netdev;
1094         struct pch_gbe_hw *hw = &adapter->hw;
1095
1096         netdev_dbg(netdev, "right now = %ld\n", jiffies);
1097
1098         pch_gbe_update_stats(adapter);
1099         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1100                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1101                 netdev->tx_queue_len = adapter->tx_queue_len;
1102                 /* mii library handles link maintenance tasks */
1103                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1104                         netdev_err(netdev, "ethtool get setting Error\n");
1105                         mod_timer(&adapter->watchdog_timer,
1106                                   round_jiffies(jiffies +
1107                                                 PCH_GBE_WATCHDOG_PERIOD));
1108                         return;
1109                 }
1110                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1111                 hw->mac.link_duplex = cmd.duplex;
1112                 /* Set the RGMII control. */
1113                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1114                                                 hw->mac.link_duplex);
1115                 /* Set the communication mode */
1116                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1117                                  hw->mac.link_duplex);
1118                 netdev_dbg(netdev,
1119                            "Link is Up %d Mbps %s-Duplex\n",
1120                            hw->mac.link_speed,
1121                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1122                 netif_carrier_on(netdev);
1123                 netif_wake_queue(netdev);
1124         } else if ((!mii_link_ok(&adapter->mii)) &&
1125                    (netif_carrier_ok(netdev))) {
1126                 netdev_dbg(netdev, "NIC Link is Down\n");
1127                 hw->mac.link_speed = SPEED_10;
1128                 hw->mac.link_duplex = DUPLEX_HALF;
1129                 netif_carrier_off(netdev);
1130                 netif_stop_queue(netdev);
1131         }
1132         mod_timer(&adapter->watchdog_timer,
1133                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1134 }
1135
1136 /**
1137  * pch_gbe_tx_queue - Carry out queuing of the transmission data
1138  * @adapter:  Board private structure
1139  * @tx_ring:  Tx descriptor ring structure
1140  * @skb:      Sockt buffer structure
1141  */
1142 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1143                               struct pch_gbe_tx_ring *tx_ring,
1144                               struct sk_buff *skb)
1145 {
1146         struct pch_gbe_hw *hw = &adapter->hw;
1147         struct pch_gbe_tx_desc *tx_desc;
1148         struct pch_gbe_buffer *buffer_info;
1149         struct sk_buff *tmp_skb;
1150         unsigned int frame_ctrl;
1151         unsigned int ring_num;
1152
1153         /*-- Set frame control --*/
1154         frame_ctrl = 0;
1155         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1156                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1157         if (skb->ip_summed == CHECKSUM_NONE)
1158                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1159
1160         /* Performs checksum processing */
1161         /*
1162          * It is because the hardware accelerator does not support a checksum,
1163          * when the received data size is less than 64 bytes.
1164          */
1165         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1166                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1167                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1168                 if (skb->protocol == htons(ETH_P_IP)) {
1169                         struct iphdr *iph = ip_hdr(skb);
1170                         unsigned int offset;
1171                         offset = skb_transport_offset(skb);
1172                         if (iph->protocol == IPPROTO_TCP) {
1173                                 skb->csum = 0;
1174                                 tcp_hdr(skb)->check = 0;
1175                                 skb->csum = skb_checksum(skb, offset,
1176                                                          skb->len - offset, 0);
1177                                 tcp_hdr(skb)->check =
1178                                         csum_tcpudp_magic(iph->saddr,
1179                                                           iph->daddr,
1180                                                           skb->len - offset,
1181                                                           IPPROTO_TCP,
1182                                                           skb->csum);
1183                         } else if (iph->protocol == IPPROTO_UDP) {
1184                                 skb->csum = 0;
1185                                 udp_hdr(skb)->check = 0;
1186                                 skb->csum =
1187                                         skb_checksum(skb, offset,
1188                                                      skb->len - offset, 0);
1189                                 udp_hdr(skb)->check =
1190                                         csum_tcpudp_magic(iph->saddr,
1191                                                           iph->daddr,
1192                                                           skb->len - offset,
1193                                                           IPPROTO_UDP,
1194                                                           skb->csum);
1195                         }
1196                 }
1197         }
1198
1199         ring_num = tx_ring->next_to_use;
1200         if (unlikely((ring_num + 1) == tx_ring->count))
1201                 tx_ring->next_to_use = 0;
1202         else
1203                 tx_ring->next_to_use = ring_num + 1;
1204
1205
1206         buffer_info = &tx_ring->buffer_info[ring_num];
1207         tmp_skb = buffer_info->skb;
1208
1209         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1210         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1211         tmp_skb->data[ETH_HLEN] = 0x00;
1212         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1213         tmp_skb->len = skb->len;
1214         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1215                (skb->len - ETH_HLEN));
1216         /*-- Set Buffer information --*/
1217         buffer_info->length = tmp_skb->len;
1218         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1219                                           buffer_info->length,
1220                                           DMA_TO_DEVICE);
1221         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1222                 netdev_err(adapter->netdev, "TX DMA map failed\n");
1223                 buffer_info->dma = 0;
1224                 buffer_info->time_stamp = 0;
1225                 tx_ring->next_to_use = ring_num;
1226                 return;
1227         }
1228         buffer_info->mapped = true;
1229         buffer_info->time_stamp = jiffies;
1230
1231         /*-- Set Tx descriptor --*/
1232         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1233         tx_desc->buffer_addr = (buffer_info->dma);
1234         tx_desc->length = (tmp_skb->len);
1235         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1236         tx_desc->tx_frame_ctrl = (frame_ctrl);
1237         tx_desc->gbec_status = (DSC_INIT16);
1238
1239         if (unlikely(++ring_num == tx_ring->count))
1240                 ring_num = 0;
1241
1242         /* Update software pointer of TX descriptor */
1243         iowrite32(tx_ring->dma +
1244                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1245                   &hw->reg->TX_DSC_SW_P);
1246
1247         pch_tx_timestamp(adapter, skb);
1248
1249         dev_kfree_skb_any(skb);
1250 }
1251
1252 /**
1253  * pch_gbe_update_stats - Update the board statistics counters
1254  * @adapter:  Board private structure
1255  */
1256 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1257 {
1258         struct net_device *netdev = adapter->netdev;
1259         struct pci_dev *pdev = adapter->pdev;
1260         struct pch_gbe_hw_stats *stats = &adapter->stats;
1261         unsigned long flags;
1262
1263         /*
1264          * Prevent stats update while adapter is being reset, or if the pci
1265          * connection is down.
1266          */
1267         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1268                 return;
1269
1270         spin_lock_irqsave(&adapter->stats_lock, flags);
1271
1272         /* Update device status "adapter->stats" */
1273         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1274         stats->tx_errors = stats->tx_length_errors +
1275             stats->tx_aborted_errors +
1276             stats->tx_carrier_errors + stats->tx_timeout_count;
1277
1278         /* Update network device status "adapter->net_stats" */
1279         netdev->stats.rx_packets = stats->rx_packets;
1280         netdev->stats.rx_bytes = stats->rx_bytes;
1281         netdev->stats.rx_dropped = stats->rx_dropped;
1282         netdev->stats.tx_packets = stats->tx_packets;
1283         netdev->stats.tx_bytes = stats->tx_bytes;
1284         netdev->stats.tx_dropped = stats->tx_dropped;
1285         /* Fill out the OS statistics structure */
1286         netdev->stats.multicast = stats->multicast;
1287         netdev->stats.collisions = stats->collisions;
1288         /* Rx Errors */
1289         netdev->stats.rx_errors = stats->rx_errors;
1290         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1291         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1292         /* Tx Errors */
1293         netdev->stats.tx_errors = stats->tx_errors;
1294         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1295         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1296
1297         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1298 }
1299
1300 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1301 {
1302         u32 rxdma;
1303
1304         /* Disable Receive DMA */
1305         rxdma = ioread32(&hw->reg->DMA_CTRL);
1306         rxdma &= ~PCH_GBE_RX_DMA_EN;
1307         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1308 }
1309
1310 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1311 {
1312         u32 rxdma;
1313
1314         /* Enables Receive DMA */
1315         rxdma = ioread32(&hw->reg->DMA_CTRL);
1316         rxdma |= PCH_GBE_RX_DMA_EN;
1317         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1318 }
1319
1320 /**
1321  * pch_gbe_intr - Interrupt Handler
1322  * @irq:   Interrupt number
1323  * @data:  Pointer to a network interface device structure
1324  * Returns:
1325  *      - IRQ_HANDLED:  Our interrupt
1326  *      - IRQ_NONE:     Not our interrupt
1327  */
1328 static irqreturn_t pch_gbe_intr(int irq, void *data)
1329 {
1330         struct net_device *netdev = data;
1331         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1332         struct pch_gbe_hw *hw = &adapter->hw;
1333         u32 int_st;
1334         u32 int_en;
1335
1336         /* Check request status */
1337         int_st = ioread32(&hw->reg->INT_ST);
1338         int_st = int_st & ioread32(&hw->reg->INT_EN);
1339         /* When request status is no interruption factor */
1340         if (unlikely(!int_st))
1341                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1342         netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1343         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1344                 adapter->stats.intr_rx_frame_err_count++;
1345         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1346                 if (!adapter->rx_stop_flag) {
1347                         adapter->stats.intr_rx_fifo_err_count++;
1348                         netdev_dbg(netdev, "Rx fifo over run\n");
1349                         adapter->rx_stop_flag = true;
1350                         int_en = ioread32(&hw->reg->INT_EN);
1351                         iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1352                                   &hw->reg->INT_EN);
1353                         pch_gbe_disable_dma_rx(&adapter->hw);
1354                         int_st |= ioread32(&hw->reg->INT_ST);
1355                         int_st = int_st & ioread32(&hw->reg->INT_EN);
1356                 }
1357         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1358                 adapter->stats.intr_rx_dma_err_count++;
1359         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1360                 adapter->stats.intr_tx_fifo_err_count++;
1361         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1362                 adapter->stats.intr_tx_dma_err_count++;
1363         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1364                 adapter->stats.intr_tcpip_err_count++;
1365         /* When Rx descriptor is empty  */
1366         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1367                 adapter->stats.intr_rx_dsc_empty_count++;
1368                 netdev_dbg(netdev, "Rx descriptor is empty\n");
1369                 int_en = ioread32(&hw->reg->INT_EN);
1370                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1371                 if (hw->mac.tx_fc_enable) {
1372                         /* Set Pause packet */
1373                         pch_gbe_mac_set_pause_packet(hw);
1374                 }
1375         }
1376
1377         /* When request status is Receive interruption */
1378         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1379             (adapter->rx_stop_flag)) {
1380                 if (likely(napi_schedule_prep(&adapter->napi))) {
1381                         /* Enable only Rx Descriptor empty */
1382                         atomic_inc(&adapter->irq_sem);
1383                         int_en = ioread32(&hw->reg->INT_EN);
1384                         int_en &=
1385                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1386                         iowrite32(int_en, &hw->reg->INT_EN);
1387                         /* Start polling for NAPI */
1388                         __napi_schedule(&adapter->napi);
1389                 }
1390         }
1391         netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1392                    IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1393         return IRQ_HANDLED;
1394 }
1395
1396 /**
1397  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1398  * @adapter:       Board private structure
1399  * @rx_ring:       Rx descriptor ring
1400  * @cleaned_count: Cleaned count
1401  */
1402 static void
1403 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1404                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1405 {
1406         struct net_device *netdev = adapter->netdev;
1407         struct pci_dev *pdev = adapter->pdev;
1408         struct pch_gbe_hw *hw = &adapter->hw;
1409         struct pch_gbe_rx_desc *rx_desc;
1410         struct pch_gbe_buffer *buffer_info;
1411         struct sk_buff *skb;
1412         unsigned int i;
1413         unsigned int bufsz;
1414
1415         bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1416         i = rx_ring->next_to_use;
1417
1418         while ((cleaned_count--)) {
1419                 buffer_info = &rx_ring->buffer_info[i];
1420                 skb = netdev_alloc_skb(netdev, bufsz);
1421                 if (unlikely(!skb)) {
1422                         /* Better luck next round */
1423                         adapter->stats.rx_alloc_buff_failed++;
1424                         break;
1425                 }
1426                 /* align */
1427                 skb_reserve(skb, NET_IP_ALIGN);
1428                 buffer_info->skb = skb;
1429
1430                 buffer_info->dma = dma_map_single(&pdev->dev,
1431                                                   buffer_info->rx_buffer,
1432                                                   buffer_info->length,
1433                                                   DMA_FROM_DEVICE);
1434                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1435                         dev_kfree_skb(skb);
1436                         buffer_info->skb = NULL;
1437                         buffer_info->dma = 0;
1438                         adapter->stats.rx_alloc_buff_failed++;
1439                         break; /* while !buffer_info->skb */
1440                 }
1441                 buffer_info->mapped = true;
1442                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1443                 rx_desc->buffer_addr = (buffer_info->dma);
1444                 rx_desc->gbec_status = DSC_INIT16;
1445
1446                 netdev_dbg(netdev,
1447                            "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1448                            i, (unsigned long long)buffer_info->dma,
1449                            buffer_info->length);
1450
1451                 if (unlikely(++i == rx_ring->count))
1452                         i = 0;
1453         }
1454         if (likely(rx_ring->next_to_use != i)) {
1455                 rx_ring->next_to_use = i;
1456                 if (unlikely(i-- == 0))
1457                         i = (rx_ring->count - 1);
1458                 iowrite32(rx_ring->dma +
1459                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1460                           &hw->reg->RX_DSC_SW_P);
1461         }
1462         return;
1463 }
1464
1465 static int
1466 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1467                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1468 {
1469         struct pci_dev *pdev = adapter->pdev;
1470         struct pch_gbe_buffer *buffer_info;
1471         unsigned int i;
1472         unsigned int bufsz;
1473         unsigned int size;
1474
1475         bufsz = adapter->rx_buffer_len;
1476
1477         size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1478         rx_ring->rx_buff_pool =
1479                 dma_zalloc_coherent(&pdev->dev, size,
1480                                     &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1481         if (!rx_ring->rx_buff_pool)
1482                 return -ENOMEM;
1483
1484         rx_ring->rx_buff_pool_size = size;
1485         for (i = 0; i < rx_ring->count; i++) {
1486                 buffer_info = &rx_ring->buffer_info[i];
1487                 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1488                 buffer_info->length = bufsz;
1489         }
1490         return 0;
1491 }
1492
1493 /**
1494  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1495  * @adapter:   Board private structure
1496  * @tx_ring:   Tx descriptor ring
1497  */
1498 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1499                                         struct pch_gbe_tx_ring *tx_ring)
1500 {
1501         struct pch_gbe_buffer *buffer_info;
1502         struct sk_buff *skb;
1503         unsigned int i;
1504         unsigned int bufsz;
1505         struct pch_gbe_tx_desc *tx_desc;
1506
1507         bufsz =
1508             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1509
1510         for (i = 0; i < tx_ring->count; i++) {
1511                 buffer_info = &tx_ring->buffer_info[i];
1512                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1513                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1514                 buffer_info->skb = skb;
1515                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1516                 tx_desc->gbec_status = (DSC_INIT16);
1517         }
1518         return;
1519 }
1520
1521 /**
1522  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1523  * @adapter:   Board private structure
1524  * @tx_ring:   Tx descriptor ring
1525  * Returns:
1526  *      true:  Cleaned the descriptor
1527  *      false: Not cleaned the descriptor
1528  */
1529 static bool
1530 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1531                  struct pch_gbe_tx_ring *tx_ring)
1532 {
1533         struct pch_gbe_tx_desc *tx_desc;
1534         struct pch_gbe_buffer *buffer_info;
1535         struct sk_buff *skb;
1536         unsigned int i;
1537         unsigned int cleaned_count = 0;
1538         bool cleaned = false;
1539         int unused, thresh;
1540
1541         netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1542                    tx_ring->next_to_clean);
1543
1544         i = tx_ring->next_to_clean;
1545         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1546         netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1547                    tx_desc->gbec_status, tx_desc->dma_status);
1548
1549         unused = PCH_GBE_DESC_UNUSED(tx_ring);
1550         thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1551         if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1552         {  /* current marked clean, tx queue filling up, do extra clean */
1553                 int j, k;
1554                 if (unused < 8) {  /* tx queue nearly full */
1555                         netdev_dbg(adapter->netdev,
1556                                    "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1557                                    tx_ring->next_to_clean, tx_ring->next_to_use,
1558                                    unused);
1559                 }
1560
1561                 /* current marked clean, scan for more that need cleaning. */
1562                 k = i;
1563                 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1564                 {
1565                         tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1566                         if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1567                         if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1568                 }
1569                 if (j < PCH_GBE_TX_WEIGHT) {
1570                         netdev_dbg(adapter->netdev,
1571                                    "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1572                                    unused, j, i, k, tx_ring->next_to_use,
1573                                    tx_desc->gbec_status);
1574                         i = k;  /*found one to clean, usu gbec_status==2000.*/
1575                 }
1576         }
1577
1578         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1579                 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1580                            tx_desc->gbec_status);
1581                 buffer_info = &tx_ring->buffer_info[i];
1582                 skb = buffer_info->skb;
1583                 cleaned = true;
1584
1585                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1586                         adapter->stats.tx_aborted_errors++;
1587                         netdev_err(adapter->netdev, "Transfer Abort Error\n");
1588                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1589                           ) {
1590                         adapter->stats.tx_carrier_errors++;
1591                         netdev_err(adapter->netdev,
1592                                    "Transfer Carrier Sense Error\n");
1593                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1594                           ) {
1595                         adapter->stats.tx_aborted_errors++;
1596                         netdev_err(adapter->netdev,
1597                                    "Transfer Collision Abort Error\n");
1598                 } else if ((tx_desc->gbec_status &
1599                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1600                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1601                         adapter->stats.collisions++;
1602                         adapter->stats.tx_packets++;
1603                         adapter->stats.tx_bytes += skb->len;
1604                         netdev_dbg(adapter->netdev, "Transfer Collision\n");
1605                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1606                           ) {
1607                         adapter->stats.tx_packets++;
1608                         adapter->stats.tx_bytes += skb->len;
1609                 }
1610                 if (buffer_info->mapped) {
1611                         netdev_dbg(adapter->netdev,
1612                                    "unmap buffer_info->dma : %d\n", i);
1613                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1614                                          buffer_info->length, DMA_TO_DEVICE);
1615                         buffer_info->mapped = false;
1616                 }
1617                 if (buffer_info->skb) {
1618                         netdev_dbg(adapter->netdev,
1619                                    "trim buffer_info->skb : %d\n", i);
1620                         skb_trim(buffer_info->skb, 0);
1621                 }
1622                 tx_desc->gbec_status = DSC_INIT16;
1623                 if (unlikely(++i == tx_ring->count))
1624                         i = 0;
1625                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1626
1627                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1628                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1629                         cleaned = false;
1630                         break;
1631                 }
1632         }
1633         netdev_dbg(adapter->netdev,
1634                    "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1635                    cleaned_count);
1636         if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1637                 /* Recover from running out of Tx resources in xmit_frame */
1638                 netif_tx_lock(adapter->netdev);
1639                 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1640                 {
1641                         netif_wake_queue(adapter->netdev);
1642                         adapter->stats.tx_restart_count++;
1643                         netdev_dbg(adapter->netdev, "Tx wake queue\n");
1644                 }
1645
1646                 tx_ring->next_to_clean = i;
1647
1648                 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1649                            tx_ring->next_to_clean);
1650                 netif_tx_unlock(adapter->netdev);
1651         }
1652         return cleaned;
1653 }
1654
1655 /**
1656  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1657  * @adapter:     Board private structure
1658  * @rx_ring:     Rx descriptor ring
1659  * @work_done:   Completed count
1660  * @work_to_do:  Request count
1661  * Returns:
1662  *      true:  Cleaned the descriptor
1663  *      false: Not cleaned the descriptor
1664  */
1665 static bool
1666 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1667                  struct pch_gbe_rx_ring *rx_ring,
1668                  int *work_done, int work_to_do)
1669 {
1670         struct net_device *netdev = adapter->netdev;
1671         struct pci_dev *pdev = adapter->pdev;
1672         struct pch_gbe_buffer *buffer_info;
1673         struct pch_gbe_rx_desc *rx_desc;
1674         u32 length;
1675         unsigned int i;
1676         unsigned int cleaned_count = 0;
1677         bool cleaned = false;
1678         struct sk_buff *skb;
1679         u8 dma_status;
1680         u16 gbec_status;
1681         u32 tcp_ip_status;
1682
1683         i = rx_ring->next_to_clean;
1684
1685         while (*work_done < work_to_do) {
1686                 /* Check Rx descriptor status */
1687                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1688                 if (rx_desc->gbec_status == DSC_INIT16)
1689                         break;
1690                 cleaned = true;
1691                 cleaned_count++;
1692
1693                 dma_status = rx_desc->dma_status;
1694                 gbec_status = rx_desc->gbec_status;
1695                 tcp_ip_status = rx_desc->tcp_ip_status;
1696                 rx_desc->gbec_status = DSC_INIT16;
1697                 buffer_info = &rx_ring->buffer_info[i];
1698                 skb = buffer_info->skb;
1699                 buffer_info->skb = NULL;
1700
1701                 /* unmap dma */
1702                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1703                                    buffer_info->length, DMA_FROM_DEVICE);
1704                 buffer_info->mapped = false;
1705
1706                 netdev_dbg(netdev,
1707                            "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1708                            i, dma_status, gbec_status, tcp_ip_status,
1709                            buffer_info);
1710                 /* Error check */
1711                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1712                         adapter->stats.rx_frame_errors++;
1713                         netdev_err(netdev, "Receive Not Octal Error\n");
1714                 } else if (unlikely(gbec_status &
1715                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1716                         adapter->stats.rx_frame_errors++;
1717                         netdev_err(netdev, "Receive Nibble Error\n");
1718                 } else if (unlikely(gbec_status &
1719                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1720                         adapter->stats.rx_crc_errors++;
1721                         netdev_err(netdev, "Receive CRC Error\n");
1722                 } else {
1723                         /* get receive length */
1724                         /* length convert[-3], length includes FCS length */
1725                         length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1726                         if (rx_desc->rx_words_eob & 0x02)
1727                                 length = length - 4;
1728                         /*
1729                          * buffer_info->rx_buffer: [Header:14][payload]
1730                          * skb->data: [Reserve:2][Header:14][payload]
1731                          */
1732                         memcpy(skb->data, buffer_info->rx_buffer, length);
1733
1734                         /* update status of driver */
1735                         adapter->stats.rx_bytes += length;
1736                         adapter->stats.rx_packets++;
1737                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1738                                 adapter->stats.multicast++;
1739                         /* Write meta date of skb */
1740                         skb_put(skb, length);
1741
1742                         pch_rx_timestamp(adapter, skb);
1743
1744                         skb->protocol = eth_type_trans(skb, netdev);
1745                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1746                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1747                         else
1748                                 skb->ip_summed = CHECKSUM_NONE;
1749
1750                         napi_gro_receive(&adapter->napi, skb);
1751                         (*work_done)++;
1752                         netdev_dbg(netdev,
1753                                    "Receive skb->ip_summed: %d length: %d\n",
1754                                    skb->ip_summed, length);
1755                 }
1756                 /* return some buffers to hardware, one at a time is too slow */
1757                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1758                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1759                                                  cleaned_count);
1760                         cleaned_count = 0;
1761                 }
1762                 if (++i == rx_ring->count)
1763                         i = 0;
1764         }
1765         rx_ring->next_to_clean = i;
1766         if (cleaned_count)
1767                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1768         return cleaned;
1769 }
1770
1771 /**
1772  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1773  * @adapter:  Board private structure
1774  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1775  * Returns:
1776  *      0:              Successfully
1777  *      Negative value: Failed
1778  */
1779 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1780                                 struct pch_gbe_tx_ring *tx_ring)
1781 {
1782         struct pci_dev *pdev = adapter->pdev;
1783         struct pch_gbe_tx_desc *tx_desc;
1784         int size;
1785         int desNo;
1786
1787         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1788         tx_ring->buffer_info = vzalloc(size);
1789         if (!tx_ring->buffer_info)
1790                 return -ENOMEM;
1791
1792         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1793
1794         tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1795                                             &tx_ring->dma, GFP_KERNEL);
1796         if (!tx_ring->desc) {
1797                 vfree(tx_ring->buffer_info);
1798                 return -ENOMEM;
1799         }
1800
1801         tx_ring->next_to_use = 0;
1802         tx_ring->next_to_clean = 0;
1803
1804         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1805                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1806                 tx_desc->gbec_status = DSC_INIT16;
1807         }
1808         netdev_dbg(adapter->netdev,
1809                    "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1810                    tx_ring->desc, (unsigned long long)tx_ring->dma,
1811                    tx_ring->next_to_clean, tx_ring->next_to_use);
1812         return 0;
1813 }
1814
1815 /**
1816  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1817  * @adapter:  Board private structure
1818  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1819  * Returns:
1820  *      0:              Successfully
1821  *      Negative value: Failed
1822  */
1823 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1824                                 struct pch_gbe_rx_ring *rx_ring)
1825 {
1826         struct pci_dev *pdev = adapter->pdev;
1827         struct pch_gbe_rx_desc *rx_desc;
1828         int size;
1829         int desNo;
1830
1831         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1832         rx_ring->buffer_info = vzalloc(size);
1833         if (!rx_ring->buffer_info)
1834                 return -ENOMEM;
1835
1836         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1837         rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1838                                             &rx_ring->dma, GFP_KERNEL);
1839         if (!rx_ring->desc) {
1840                 vfree(rx_ring->buffer_info);
1841                 return -ENOMEM;
1842         }
1843         rx_ring->next_to_clean = 0;
1844         rx_ring->next_to_use = 0;
1845         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1846                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1847                 rx_desc->gbec_status = DSC_INIT16;
1848         }
1849         netdev_dbg(adapter->netdev,
1850                    "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1851                    rx_ring->desc, (unsigned long long)rx_ring->dma,
1852                    rx_ring->next_to_clean, rx_ring->next_to_use);
1853         return 0;
1854 }
1855
1856 /**
1857  * pch_gbe_free_tx_resources - Free Tx Resources
1858  * @adapter:  Board private structure
1859  * @tx_ring:  Tx descriptor ring for a specific queue
1860  */
1861 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1862                                 struct pch_gbe_tx_ring *tx_ring)
1863 {
1864         struct pci_dev *pdev = adapter->pdev;
1865
1866         pch_gbe_clean_tx_ring(adapter, tx_ring);
1867         vfree(tx_ring->buffer_info);
1868         tx_ring->buffer_info = NULL;
1869         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1870         tx_ring->desc = NULL;
1871 }
1872
1873 /**
1874  * pch_gbe_free_rx_resources - Free Rx Resources
1875  * @adapter:  Board private structure
1876  * @rx_ring:  Ring to clean the resources from
1877  */
1878 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1879                                 struct pch_gbe_rx_ring *rx_ring)
1880 {
1881         struct pci_dev *pdev = adapter->pdev;
1882
1883         pch_gbe_clean_rx_ring(adapter, rx_ring);
1884         vfree(rx_ring->buffer_info);
1885         rx_ring->buffer_info = NULL;
1886         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1887         rx_ring->desc = NULL;
1888 }
1889
1890 /**
1891  * pch_gbe_request_irq - Allocate an interrupt line
1892  * @adapter:  Board private structure
1893  * Returns:
1894  *      0:              Successfully
1895  *      Negative value: Failed
1896  */
1897 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1898 {
1899         struct net_device *netdev = adapter->netdev;
1900         int err;
1901
1902         err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1903         if (err < 0)
1904                 return err;
1905
1906         adapter->irq = pci_irq_vector(adapter->pdev, 0);
1907
1908         err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1909                           netdev->name, netdev);
1910         if (err)
1911                 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1912                            err);
1913         netdev_dbg(netdev, "have_msi : %d  return : 0x%04x\n",
1914                    pci_dev_msi_enabled(adapter->pdev), err);
1915         return err;
1916 }
1917
1918 /**
1919  * pch_gbe_up - Up GbE network device
1920  * @adapter:  Board private structure
1921  * Returns:
1922  *      0:              Successfully
1923  *      Negative value: Failed
1924  */
1925 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1926 {
1927         struct net_device *netdev = adapter->netdev;
1928         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1929         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1930         int err = -EINVAL;
1931
1932         /* Ensure we have a valid MAC */
1933         if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1934                 netdev_err(netdev, "Error: Invalid MAC address\n");
1935                 goto out;
1936         }
1937
1938         /* hardware has been reset, we need to reload some things */
1939         pch_gbe_set_multi(netdev);
1940
1941         pch_gbe_setup_tctl(adapter);
1942         pch_gbe_configure_tx(adapter);
1943         pch_gbe_setup_rctl(adapter);
1944         pch_gbe_configure_rx(adapter);
1945
1946         err = pch_gbe_request_irq(adapter);
1947         if (err) {
1948                 netdev_err(netdev,
1949                            "Error: can't bring device up - irq request failed\n");
1950                 goto out;
1951         }
1952         err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1953         if (err) {
1954                 netdev_err(netdev,
1955                            "Error: can't bring device up - alloc rx buffers pool failed\n");
1956                 goto freeirq;
1957         }
1958         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1959         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1960         adapter->tx_queue_len = netdev->tx_queue_len;
1961         pch_gbe_enable_dma_rx(&adapter->hw);
1962         pch_gbe_enable_mac_rx(&adapter->hw);
1963
1964         mod_timer(&adapter->watchdog_timer, jiffies);
1965
1966         napi_enable(&adapter->napi);
1967         pch_gbe_irq_enable(adapter);
1968         netif_start_queue(adapter->netdev);
1969
1970         return 0;
1971
1972 freeirq:
1973         pch_gbe_free_irq(adapter);
1974 out:
1975         return err;
1976 }
1977
1978 /**
1979  * pch_gbe_down - Down GbE network device
1980  * @adapter:  Board private structure
1981  */
1982 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1983 {
1984         struct net_device *netdev = adapter->netdev;
1985         struct pci_dev *pdev = adapter->pdev;
1986         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1987
1988         /* signal that we're down so the interrupt handler does not
1989          * reschedule our watchdog timer */
1990         napi_disable(&adapter->napi);
1991         atomic_set(&adapter->irq_sem, 0);
1992
1993         pch_gbe_irq_disable(adapter);
1994         pch_gbe_free_irq(adapter);
1995
1996         del_timer_sync(&adapter->watchdog_timer);
1997
1998         netdev->tx_queue_len = adapter->tx_queue_len;
1999         netif_carrier_off(netdev);
2000         netif_stop_queue(netdev);
2001
2002         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2003                 pch_gbe_reset(adapter);
2004         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2005         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2006
2007         pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2008                             rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2009         rx_ring->rx_buff_pool_logic = 0;
2010         rx_ring->rx_buff_pool_size = 0;
2011         rx_ring->rx_buff_pool = NULL;
2012 }
2013
2014 /**
2015  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2016  * @adapter:  Board private structure to initialize
2017  * Returns:
2018  *      0:              Successfully
2019  *      Negative value: Failed
2020  */
2021 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2022 {
2023         struct pch_gbe_hw *hw = &adapter->hw;
2024         struct net_device *netdev = adapter->netdev;
2025
2026         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2027         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2028         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2029
2030         /* Initialize the hardware-specific values */
2031         if (pch_gbe_hal_setup_init_funcs(hw)) {
2032                 netdev_err(netdev, "Hardware Initialization Failure\n");
2033                 return -EIO;
2034         }
2035         if (pch_gbe_alloc_queues(adapter)) {
2036                 netdev_err(netdev, "Unable to allocate memory for queues\n");
2037                 return -ENOMEM;
2038         }
2039         spin_lock_init(&adapter->hw.miim_lock);
2040         spin_lock_init(&adapter->stats_lock);
2041         spin_lock_init(&adapter->ethtool_lock);
2042         atomic_set(&adapter->irq_sem, 0);
2043         pch_gbe_irq_disable(adapter);
2044
2045         pch_gbe_init_stats(adapter);
2046
2047         netdev_dbg(netdev,
2048                    "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
2049                    (u32) adapter->rx_buffer_len,
2050                    hw->mac.min_frame_size, hw->mac.max_frame_size);
2051         return 0;
2052 }
2053
2054 /**
2055  * pch_gbe_open - Called when a network interface is made active
2056  * @netdev:     Network interface device structure
2057  * Returns:
2058  *      0:              Successfully
2059  *      Negative value: Failed
2060  */
2061 static int pch_gbe_open(struct net_device *netdev)
2062 {
2063         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2064         struct pch_gbe_hw *hw = &adapter->hw;
2065         int err;
2066
2067         /* allocate transmit descriptors */
2068         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2069         if (err)
2070                 goto err_setup_tx;
2071         /* allocate receive descriptors */
2072         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2073         if (err)
2074                 goto err_setup_rx;
2075         pch_gbe_hal_power_up_phy(hw);
2076         err = pch_gbe_up(adapter);
2077         if (err)
2078                 goto err_up;
2079         netdev_dbg(netdev, "Success End\n");
2080         return 0;
2081
2082 err_up:
2083         if (!adapter->wake_up_evt)
2084                 pch_gbe_hal_power_down_phy(hw);
2085         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2086 err_setup_rx:
2087         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2088 err_setup_tx:
2089         pch_gbe_reset(adapter);
2090         netdev_err(netdev, "Error End\n");
2091         return err;
2092 }
2093
2094 /**
2095  * pch_gbe_stop - Disables a network interface
2096  * @netdev:  Network interface device structure
2097  * Returns:
2098  *      0: Successfully
2099  */
2100 static int pch_gbe_stop(struct net_device *netdev)
2101 {
2102         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2103         struct pch_gbe_hw *hw = &adapter->hw;
2104
2105         pch_gbe_down(adapter);
2106         if (!adapter->wake_up_evt)
2107                 pch_gbe_hal_power_down_phy(hw);
2108         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2109         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2110         return 0;
2111 }
2112
2113 /**
2114  * pch_gbe_xmit_frame - Packet transmitting start
2115  * @skb:     Socket buffer structure
2116  * @netdev:  Network interface device structure
2117  * Returns:
2118  *      - NETDEV_TX_OK:   Normal end
2119  *      - NETDEV_TX_BUSY: Error end
2120  */
2121 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2122 {
2123         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2124         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2125
2126         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2127                 netif_stop_queue(netdev);
2128                 netdev_dbg(netdev,
2129                            "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2130                            tx_ring->next_to_use, tx_ring->next_to_clean);
2131                 return NETDEV_TX_BUSY;
2132         }
2133
2134         /* CRC,ITAG no support */
2135         pch_gbe_tx_queue(adapter, tx_ring, skb);
2136         return NETDEV_TX_OK;
2137 }
2138
2139 /**
2140  * pch_gbe_set_multi - Multicast and Promiscuous mode set
2141  * @netdev:   Network interface device structure
2142  */
2143 static void pch_gbe_set_multi(struct net_device *netdev)
2144 {
2145         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2146         struct pch_gbe_hw *hw = &adapter->hw;
2147         struct netdev_hw_addr *ha;
2148         u8 *mta_list;
2149         u32 rctl;
2150         int i;
2151         int mc_count;
2152
2153         netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2154
2155         /* Check for Promiscuous and All Multicast modes */
2156         rctl = ioread32(&hw->reg->RX_MODE);
2157         mc_count = netdev_mc_count(netdev);
2158         if ((netdev->flags & IFF_PROMISC)) {
2159                 rctl &= ~PCH_GBE_ADD_FIL_EN;
2160                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2161         } else if ((netdev->flags & IFF_ALLMULTI)) {
2162                 /* all the multicasting receive permissions */
2163                 rctl |= PCH_GBE_ADD_FIL_EN;
2164                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2165         } else {
2166                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2167                         /* all the multicasting receive permissions */
2168                         rctl |= PCH_GBE_ADD_FIL_EN;
2169                         rctl &= ~PCH_GBE_MLT_FIL_EN;
2170                 } else {
2171                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2172                 }
2173         }
2174         iowrite32(rctl, &hw->reg->RX_MODE);
2175
2176         if (mc_count >= PCH_GBE_MAR_ENTRIES)
2177                 return;
2178         mta_list = kmalloc_array(ETH_ALEN, mc_count, GFP_ATOMIC);
2179         if (!mta_list)
2180                 return;
2181
2182         /* The shared function expects a packed array of only addresses. */
2183         i = 0;
2184         netdev_for_each_mc_addr(ha, netdev) {
2185                 if (i == mc_count)
2186                         break;
2187                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2188         }
2189         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2190                                         PCH_GBE_MAR_ENTRIES);
2191         kfree(mta_list);
2192
2193         netdev_dbg(netdev,
2194                  "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2195                  ioread32(&hw->reg->RX_MODE), mc_count);
2196 }
2197
2198 /**
2199  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2200  * @netdev: Network interface device structure
2201  * @addr:   Pointer to an address structure
2202  * Returns:
2203  *      0:              Successfully
2204  *      -EADDRNOTAVAIL: Failed
2205  */
2206 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2207 {
2208         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2209         struct sockaddr *skaddr = addr;
2210         int ret_val;
2211
2212         if (!is_valid_ether_addr(skaddr->sa_data)) {
2213                 ret_val = -EADDRNOTAVAIL;
2214         } else {
2215                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2216                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2217                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2218                 ret_val = 0;
2219         }
2220         netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2221         netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2222         netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2223         netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2224                    ioread32(&adapter->hw.reg->mac_adr[0].high),
2225                    ioread32(&adapter->hw.reg->mac_adr[0].low));
2226         return ret_val;
2227 }
2228
2229 /**
2230  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2231  * @netdev:   Network interface device structure
2232  * @new_mtu:  New value for maximum frame size
2233  * Returns:
2234  *      0:              Successfully
2235  *      -EINVAL:        Failed
2236  */
2237 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2238 {
2239         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2240         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2241         unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2242         int err;
2243
2244         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2245                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2246         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2247                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2248         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2249                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2250         else
2251                 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2252
2253         if (netif_running(netdev)) {
2254                 pch_gbe_down(adapter);
2255                 err = pch_gbe_up(adapter);
2256                 if (err) {
2257                         adapter->rx_buffer_len = old_rx_buffer_len;
2258                         pch_gbe_up(adapter);
2259                         return err;
2260                 } else {
2261                         netdev->mtu = new_mtu;
2262                         adapter->hw.mac.max_frame_size = max_frame;
2263                 }
2264         } else {
2265                 pch_gbe_reset(adapter);
2266                 netdev->mtu = new_mtu;
2267                 adapter->hw.mac.max_frame_size = max_frame;
2268         }
2269
2270         netdev_dbg(netdev,
2271                    "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2272                    max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2273                    adapter->hw.mac.max_frame_size);
2274         return 0;
2275 }
2276
2277 /**
2278  * pch_gbe_set_features - Reset device after features changed
2279  * @netdev:   Network interface device structure
2280  * @features:  New features
2281  * Returns:
2282  *      0:              HW state updated successfully
2283  */
2284 static int pch_gbe_set_features(struct net_device *netdev,
2285         netdev_features_t features)
2286 {
2287         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2288         netdev_features_t changed = features ^ netdev->features;
2289
2290         if (!(changed & NETIF_F_RXCSUM))
2291                 return 0;
2292
2293         if (netif_running(netdev))
2294                 pch_gbe_reinit_locked(adapter);
2295         else
2296                 pch_gbe_reset(adapter);
2297
2298         return 0;
2299 }
2300
2301 /**
2302  * pch_gbe_ioctl - Controls register through a MII interface
2303  * @netdev:   Network interface device structure
2304  * @ifr:      Pointer to ifr structure
2305  * @cmd:      Control command
2306  * Returns:
2307  *      0:      Successfully
2308  *      Negative value: Failed
2309  */
2310 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2311 {
2312         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2313
2314         netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2315
2316         if (cmd == SIOCSHWTSTAMP)
2317                 return hwtstamp_ioctl(netdev, ifr, cmd);
2318
2319         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2320 }
2321
2322 /**
2323  * pch_gbe_tx_timeout - Respond to a Tx Hang
2324  * @netdev:   Network interface device structure
2325  */
2326 static void pch_gbe_tx_timeout(struct net_device *netdev)
2327 {
2328         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2329
2330         /* Do the reset outside of interrupt context */
2331         adapter->stats.tx_timeout_count++;
2332         schedule_work(&adapter->reset_task);
2333 }
2334
2335 /**
2336  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2337  * @napi:    Pointer of polling device struct
2338  * @budget:  The maximum number of a packet
2339  * Returns:
2340  *      false:  Exit the polling mode
2341  *      true:   Continue the polling mode
2342  */
2343 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2344 {
2345         struct pch_gbe_adapter *adapter =
2346             container_of(napi, struct pch_gbe_adapter, napi);
2347         int work_done = 0;
2348         bool poll_end_flag = false;
2349         bool cleaned = false;
2350
2351         netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2352
2353         pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2354         cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2355
2356         if (cleaned)
2357                 work_done = budget;
2358         /* If no Tx and not enough Rx work done,
2359          * exit the polling mode
2360          */
2361         if (work_done < budget)
2362                 poll_end_flag = true;
2363
2364         if (poll_end_flag) {
2365                 napi_complete_done(napi, work_done);
2366                 pch_gbe_irq_enable(adapter);
2367         }
2368
2369         if (adapter->rx_stop_flag) {
2370                 adapter->rx_stop_flag = false;
2371                 pch_gbe_enable_dma_rx(&adapter->hw);
2372         }
2373
2374         netdev_dbg(adapter->netdev,
2375                    "poll_end_flag : %d  work_done : %d  budget : %d\n",
2376                    poll_end_flag, work_done, budget);
2377
2378         return work_done;
2379 }
2380
2381 #ifdef CONFIG_NET_POLL_CONTROLLER
2382 /**
2383  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2384  * @netdev:  Network interface device structure
2385  */
2386 static void pch_gbe_netpoll(struct net_device *netdev)
2387 {
2388         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2389
2390         disable_irq(adapter->irq);
2391         pch_gbe_intr(adapter->irq, netdev);
2392         enable_irq(adapter->irq);
2393 }
2394 #endif
2395
2396 static const struct net_device_ops pch_gbe_netdev_ops = {
2397         .ndo_open = pch_gbe_open,
2398         .ndo_stop = pch_gbe_stop,
2399         .ndo_start_xmit = pch_gbe_xmit_frame,
2400         .ndo_set_mac_address = pch_gbe_set_mac,
2401         .ndo_tx_timeout = pch_gbe_tx_timeout,
2402         .ndo_change_mtu = pch_gbe_change_mtu,
2403         .ndo_set_features = pch_gbe_set_features,
2404         .ndo_do_ioctl = pch_gbe_ioctl,
2405         .ndo_set_rx_mode = pch_gbe_set_multi,
2406 #ifdef CONFIG_NET_POLL_CONTROLLER
2407         .ndo_poll_controller = pch_gbe_netpoll,
2408 #endif
2409 };
2410
2411 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2412                                                 pci_channel_state_t state)
2413 {
2414         struct net_device *netdev = pci_get_drvdata(pdev);
2415         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2416
2417         netif_device_detach(netdev);
2418         if (netif_running(netdev))
2419                 pch_gbe_down(adapter);
2420         pci_disable_device(pdev);
2421         /* Request a slot slot reset. */
2422         return PCI_ERS_RESULT_NEED_RESET;
2423 }
2424
2425 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2426 {
2427         struct net_device *netdev = pci_get_drvdata(pdev);
2428         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2429         struct pch_gbe_hw *hw = &adapter->hw;
2430
2431         if (pci_enable_device(pdev)) {
2432                 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2433                 return PCI_ERS_RESULT_DISCONNECT;
2434         }
2435         pci_set_master(pdev);
2436         pci_enable_wake(pdev, PCI_D0, 0);
2437         pch_gbe_hal_power_up_phy(hw);
2438         pch_gbe_reset(adapter);
2439         /* Clear wake up status */
2440         pch_gbe_mac_set_wol_event(hw, 0);
2441
2442         return PCI_ERS_RESULT_RECOVERED;
2443 }
2444
2445 static void pch_gbe_io_resume(struct pci_dev *pdev)
2446 {
2447         struct net_device *netdev = pci_get_drvdata(pdev);
2448         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2449
2450         if (netif_running(netdev)) {
2451                 if (pch_gbe_up(adapter)) {
2452                         netdev_dbg(netdev,
2453                                    "can't bring device back up after reset\n");
2454                         return;
2455                 }
2456         }
2457         netif_device_attach(netdev);
2458 }
2459
2460 static int __pch_gbe_suspend(struct pci_dev *pdev)
2461 {
2462         struct net_device *netdev = pci_get_drvdata(pdev);
2463         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2464         struct pch_gbe_hw *hw = &adapter->hw;
2465         u32 wufc = adapter->wake_up_evt;
2466         int retval = 0;
2467
2468         netif_device_detach(netdev);
2469         if (netif_running(netdev))
2470                 pch_gbe_down(adapter);
2471         if (wufc) {
2472                 pch_gbe_set_multi(netdev);
2473                 pch_gbe_setup_rctl(adapter);
2474                 pch_gbe_configure_rx(adapter);
2475                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2476                                         hw->mac.link_duplex);
2477                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2478                                         hw->mac.link_duplex);
2479                 pch_gbe_mac_set_wol_event(hw, wufc);
2480                 pci_disable_device(pdev);
2481         } else {
2482                 pch_gbe_hal_power_down_phy(hw);
2483                 pch_gbe_mac_set_wol_event(hw, wufc);
2484                 pci_disable_device(pdev);
2485         }
2486         return retval;
2487 }
2488
2489 #ifdef CONFIG_PM
2490 static int pch_gbe_suspend(struct device *device)
2491 {
2492         struct pci_dev *pdev = to_pci_dev(device);
2493
2494         return __pch_gbe_suspend(pdev);
2495 }
2496
2497 static int pch_gbe_resume(struct device *device)
2498 {
2499         struct pci_dev *pdev = to_pci_dev(device);
2500         struct net_device *netdev = pci_get_drvdata(pdev);
2501         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2502         struct pch_gbe_hw *hw = &adapter->hw;
2503         u32 err;
2504
2505         err = pci_enable_device(pdev);
2506         if (err) {
2507                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2508                 return err;
2509         }
2510         pci_set_master(pdev);
2511         pch_gbe_hal_power_up_phy(hw);
2512         pch_gbe_reset(adapter);
2513         /* Clear wake on lan control and status */
2514         pch_gbe_mac_set_wol_event(hw, 0);
2515
2516         if (netif_running(netdev))
2517                 pch_gbe_up(adapter);
2518         netif_device_attach(netdev);
2519
2520         return 0;
2521 }
2522 #endif /* CONFIG_PM */
2523
2524 static void pch_gbe_shutdown(struct pci_dev *pdev)
2525 {
2526         __pch_gbe_suspend(pdev);
2527         if (system_state == SYSTEM_POWER_OFF) {
2528                 pci_wake_from_d3(pdev, true);
2529                 pci_set_power_state(pdev, PCI_D3hot);
2530         }
2531 }
2532
2533 static void pch_gbe_remove(struct pci_dev *pdev)
2534 {
2535         struct net_device *netdev = pci_get_drvdata(pdev);
2536         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2537
2538         cancel_work_sync(&adapter->reset_task);
2539         unregister_netdev(netdev);
2540
2541         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2542
2543         free_netdev(netdev);
2544 }
2545
2546 static int pch_gbe_probe(struct pci_dev *pdev,
2547                           const struct pci_device_id *pci_id)
2548 {
2549         struct net_device *netdev;
2550         struct pch_gbe_adapter *adapter;
2551         int ret;
2552
2553         ret = pcim_enable_device(pdev);
2554         if (ret)
2555                 return ret;
2556
2557         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2558                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2559                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2560                 if (ret) {
2561                         ret = pci_set_consistent_dma_mask(pdev,
2562                                                           DMA_BIT_MASK(32));
2563                         if (ret) {
2564                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2565                                         "configuration, aborting\n");
2566                                 return ret;
2567                         }
2568                 }
2569         }
2570
2571         ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2572         if (ret) {
2573                 dev_err(&pdev->dev,
2574                         "ERR: Can't reserve PCI I/O and memory resources\n");
2575                 return ret;
2576         }
2577         pci_set_master(pdev);
2578
2579         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2580         if (!netdev)
2581                 return -ENOMEM;
2582         SET_NETDEV_DEV(netdev, &pdev->dev);
2583
2584         pci_set_drvdata(pdev, netdev);
2585         adapter = netdev_priv(netdev);
2586         adapter->netdev = netdev;
2587         adapter->pdev = pdev;
2588         adapter->hw.back = adapter;
2589         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2590         adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2591         if (adapter->pdata && adapter->pdata->platform_init)
2592                 adapter->pdata->platform_init(pdev);
2593
2594         adapter->ptp_pdev =
2595                 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2596                                             adapter->pdev->bus->number,
2597                                             PCI_DEVFN(12, 4));
2598
2599         netdev->netdev_ops = &pch_gbe_netdev_ops;
2600         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2601         netif_napi_add(netdev, &adapter->napi,
2602                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2603         netdev->hw_features = NETIF_F_RXCSUM |
2604                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2605         netdev->features = netdev->hw_features;
2606         pch_gbe_set_ethtool_ops(netdev);
2607
2608         /* MTU range: 46 - 10300 */
2609         netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2610         netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2611                           (ETH_HLEN + ETH_FCS_LEN);
2612
2613         pch_gbe_mac_load_mac_addr(&adapter->hw);
2614         pch_gbe_mac_reset_hw(&adapter->hw);
2615
2616         /* setup the private structure */
2617         ret = pch_gbe_sw_init(adapter);
2618         if (ret)
2619                 goto err_free_netdev;
2620
2621         /* Initialize PHY */
2622         ret = pch_gbe_init_phy(adapter);
2623         if (ret) {
2624                 dev_err(&pdev->dev, "PHY initialize error\n");
2625                 goto err_free_adapter;
2626         }
2627         pch_gbe_hal_get_bus_info(&adapter->hw);
2628
2629         /* Read the MAC address. and store to the private data */
2630         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2631         if (ret) {
2632                 dev_err(&pdev->dev, "MAC address Read Error\n");
2633                 goto err_free_adapter;
2634         }
2635
2636         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2637         if (!is_valid_ether_addr(netdev->dev_addr)) {
2638                 /*
2639                  * If the MAC is invalid (or just missing), display a warning
2640                  * but do not abort setting up the device. pch_gbe_up will
2641                  * prevent the interface from being brought up until a valid MAC
2642                  * is set.
2643                  */
2644                 dev_err(&pdev->dev, "Invalid MAC address, "
2645                                     "interface disabled.\n");
2646         }
2647         timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
2648
2649         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2650
2651         pch_gbe_check_options(adapter);
2652
2653         /* initialize the wol settings based on the eeprom settings */
2654         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2655         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2656
2657         /* reset the hardware with the new settings */
2658         pch_gbe_reset(adapter);
2659
2660         ret = register_netdev(netdev);
2661         if (ret)
2662                 goto err_free_adapter;
2663         /* tell the stack to leave us alone until pch_gbe_open() is called */
2664         netif_carrier_off(netdev);
2665         netif_stop_queue(netdev);
2666
2667         dev_dbg(&pdev->dev, "PCH Network Connection\n");
2668
2669         /* Disable hibernation on certain platforms */
2670         if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2671                 pch_gbe_phy_disable_hibernate(&adapter->hw);
2672
2673         device_set_wakeup_enable(&pdev->dev, 1);
2674         return 0;
2675
2676 err_free_adapter:
2677         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2678 err_free_netdev:
2679         free_netdev(netdev);
2680         return ret;
2681 }
2682
2683 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2684  * ensure it is awake for probe and init. Request the line and reset the PHY.
2685  */
2686 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2687 {
2688         unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2689         unsigned gpio = MINNOW_PHY_RESET_GPIO;
2690         int ret;
2691
2692         ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2693                                     "minnow_phy_reset");
2694         if (ret) {
2695                 dev_err(&pdev->dev,
2696                         "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2697                 return ret;
2698         }
2699
2700         gpio_set_value(gpio, 0);
2701         usleep_range(1250, 1500);
2702         gpio_set_value(gpio, 1);
2703         usleep_range(1250, 1500);
2704
2705         return ret;
2706 }
2707
2708 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2709         .phy_tx_clk_delay = true,
2710         .phy_disable_hibernate = true,
2711         .platform_init = pch_gbe_minnow_platform_init,
2712 };
2713
2714 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2715         {.vendor = PCI_VENDOR_ID_INTEL,
2716          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2717          .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2718          .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2719          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2720          .class_mask = (0xFFFF00),
2721          .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2722          },
2723         {.vendor = PCI_VENDOR_ID_INTEL,
2724          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2725          .subvendor = PCI_ANY_ID,
2726          .subdevice = PCI_ANY_ID,
2727          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2728          .class_mask = (0xFFFF00)
2729          },
2730         {.vendor = PCI_VENDOR_ID_ROHM,
2731          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2732          .subvendor = PCI_ANY_ID,
2733          .subdevice = PCI_ANY_ID,
2734          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2735          .class_mask = (0xFFFF00)
2736          },
2737         {.vendor = PCI_VENDOR_ID_ROHM,
2738          .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2739          .subvendor = PCI_ANY_ID,
2740          .subdevice = PCI_ANY_ID,
2741          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2742          .class_mask = (0xFFFF00)
2743          },
2744         /* required last entry */
2745         {0}
2746 };
2747
2748 #ifdef CONFIG_PM
2749 static const struct dev_pm_ops pch_gbe_pm_ops = {
2750         .suspend = pch_gbe_suspend,
2751         .resume = pch_gbe_resume,
2752         .freeze = pch_gbe_suspend,
2753         .thaw = pch_gbe_resume,
2754         .poweroff = pch_gbe_suspend,
2755         .restore = pch_gbe_resume,
2756 };
2757 #endif
2758
2759 static const struct pci_error_handlers pch_gbe_err_handler = {
2760         .error_detected = pch_gbe_io_error_detected,
2761         .slot_reset = pch_gbe_io_slot_reset,
2762         .resume = pch_gbe_io_resume
2763 };
2764
2765 static struct pci_driver pch_gbe_driver = {
2766         .name = KBUILD_MODNAME,
2767         .id_table = pch_gbe_pcidev_id,
2768         .probe = pch_gbe_probe,
2769         .remove = pch_gbe_remove,
2770 #ifdef CONFIG_PM
2771         .driver.pm = &pch_gbe_pm_ops,
2772 #endif
2773         .shutdown = pch_gbe_shutdown,
2774         .err_handler = &pch_gbe_err_handler
2775 };
2776
2777
2778 static int __init pch_gbe_init_module(void)
2779 {
2780         int ret;
2781
2782         pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2783         ret = pci_register_driver(&pch_gbe_driver);
2784         return ret;
2785 }
2786
2787 static void __exit pch_gbe_exit_module(void)
2788 {
2789         pci_unregister_driver(&pch_gbe_driver);
2790 }
2791
2792 module_init(pch_gbe_init_module);
2793 module_exit(pch_gbe_exit_module);
2794
2795 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2796 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2797 MODULE_LICENSE("GPL");
2798 MODULE_VERSION(DRV_VERSION);
2799 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2800
2801 /* pch_gbe_main.c */