2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/mlx5/eswitch.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/fs.h>
45 #ifdef CONFIG_MLX5_ESWITCH
47 #define MLX5_MAX_UC_PER_VPORT(dev) \
48 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
50 #define MLX5_MAX_MC_PER_VPORT(dev) \
51 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
53 #define MLX5_MIN_BW_SHARE 1
55 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
56 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
58 #define mlx5_esw_has_fwd_fdb(dev) \
59 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
61 #define FDB_MAX_CHAIN 3
62 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
63 #define FDB_MAX_PRIO 16
65 struct vport_ingress {
66 struct mlx5_flow_table *acl;
67 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
68 struct mlx5_flow_group *allow_spoofchk_only_grp;
69 struct mlx5_flow_group *allow_untagged_only_grp;
70 struct mlx5_flow_group *drop_grp;
71 struct mlx5_flow_handle *allow_rule;
72 struct mlx5_flow_handle *drop_rule;
73 struct mlx5_fc *drop_counter;
77 struct mlx5_flow_table *acl;
78 struct mlx5_flow_group *allowed_vlans_grp;
79 struct mlx5_flow_group *drop_grp;
80 struct mlx5_flow_handle *allowed_vlan;
81 struct mlx5_flow_handle *drop_rule;
82 struct mlx5_fc *drop_counter;
85 struct mlx5_vport_drop_stats {
90 struct mlx5_vport_info {
103 struct mlx5_core_dev *dev;
105 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
106 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
107 struct mlx5_flow_handle *promisc_rule;
108 struct mlx5_flow_handle *allmulti_rule;
109 struct work_struct vport_change_handler;
111 struct vport_ingress ingress;
112 struct vport_egress egress;
114 struct mlx5_vport_info info;
126 enum offloads_fdb_flags {
127 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
130 extern const unsigned int ESW_POOLS[4];
132 #define PRIO_LEVELS 2
133 struct mlx5_eswitch_fdb {
136 struct mlx5_flow_table *fdb;
137 struct mlx5_flow_group *addr_grp;
138 struct mlx5_flow_group *allmulti_grp;
139 struct mlx5_flow_group *promisc_grp;
142 struct offloads_fdb {
143 struct mlx5_flow_table *slow_fdb;
144 struct mlx5_flow_group *send_to_vport_grp;
145 struct mlx5_flow_group *peer_miss_grp;
146 struct mlx5_flow_handle **peer_miss_rules;
147 struct mlx5_flow_group *miss_grp;
148 struct mlx5_flow_handle *miss_rule_uni;
149 struct mlx5_flow_handle *miss_rule_multi;
150 int vlan_push_pop_refcount;
153 struct mlx5_flow_table *fdb;
155 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
156 /* Protects fdb_prio table */
157 struct mutex fdb_prio_lock;
159 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
165 struct mlx5_esw_offload {
166 struct mlx5_flow_table *ft_offloads;
167 struct mlx5_flow_group *vport_rx_group;
168 struct mlx5_eswitch_rep *vport_reps;
169 struct list_head peer_flows;
170 struct mutex peer_mutex;
171 DECLARE_HASHTABLE(encap_tbl, 8);
172 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
178 /* E-Switch MC FDB table hash node */
179 struct esw_mc_addr { /* SRIOV only */
180 struct l2addr_node node;
181 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
185 struct mlx5_host_work {
186 struct work_struct work;
187 struct mlx5_eswitch *esw;
190 struct mlx5_host_info {
195 struct mlx5_eswitch {
196 struct mlx5_core_dev *dev;
198 struct mlx5_eswitch_fdb fdb_table;
199 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
200 struct workqueue_struct *work_queue;
201 struct mlx5_vport *vports;
204 /* Synchronize between vport change events
205 * and async SRIOV admin state changes
207 struct mutex state_lock;
208 struct esw_mc_addr mc_promisc;
215 struct mlx5_esw_offload offloads;
219 struct mlx5_host_info host_info;
222 void esw_offloads_cleanup(struct mlx5_eswitch *esw);
223 int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
225 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
226 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
229 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
230 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
231 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
232 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
233 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
234 int vport, u8 mac[ETH_ALEN]);
235 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
236 int vport, int link_state);
237 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
238 int vport, u16 vlan, u8 qos);
239 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
240 int vport, bool spoofchk);
241 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
242 int vport_num, bool setting);
243 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
244 u32 max_rate, u32 min_rate);
245 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
246 int vport, struct ifla_vf_info *ivi);
247 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
249 struct ifla_vf_stats *vf_stats);
250 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
252 struct mlx5_flow_spec;
253 struct mlx5_esw_flow_attr;
255 struct mlx5_flow_handle *
256 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
257 struct mlx5_flow_spec *spec,
258 struct mlx5_esw_flow_attr *attr);
259 struct mlx5_flow_handle *
260 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
261 struct mlx5_flow_spec *spec,
262 struct mlx5_esw_flow_attr *attr);
264 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
265 struct mlx5_flow_handle *rule,
266 struct mlx5_esw_flow_attr *attr);
268 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
269 struct mlx5_flow_handle *rule,
270 struct mlx5_esw_flow_attr *attr);
273 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
276 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
279 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
281 struct mlx5_flow_handle *
282 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
283 struct mlx5_flow_destination *dest);
286 SET_VLAN_STRIP = BIT(0),
287 SET_VLAN_INSERT = BIT(1)
290 enum mlx5_flow_match_level {
291 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
292 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
293 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
294 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
297 /* current maximum for flow based vport multicasting */
298 #define MLX5_MAX_FLOW_FWD_VPORTS 2
301 MLX5_ESW_DEST_ENCAP = BIT(0),
302 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
305 struct mlx5_esw_flow_attr {
306 struct mlx5_eswitch_rep *in_rep;
307 struct mlx5_core_dev *in_mdev;
308 struct mlx5_core_dev *counter_dev;
314 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
315 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
316 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
321 struct mlx5_eswitch_rep *rep;
322 struct mlx5_core_dev *mdev;
324 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
327 u8 tunnel_match_level;
328 struct mlx5_fc *counter;
332 struct mlx5e_tc_flow_parse_attr *parse_attr;
335 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
336 struct netlink_ext_ack *extack);
337 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
338 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
339 struct netlink_ext_ack *extack);
340 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
341 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
342 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
343 struct netlink_ext_ack *extack);
344 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
345 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
347 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
348 struct mlx5_esw_flow_attr *attr);
349 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
350 struct mlx5_esw_flow_attr *attr);
351 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
352 int vport, u16 vlan, u8 qos, u8 set_flags);
354 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
357 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
358 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
363 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
364 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
367 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
368 struct mlx5_core_dev *dev1);
370 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
372 #define esw_info(dev, format, ...) \
373 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
375 #define esw_warn(dev, format, ...) \
376 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
378 #define esw_debug(dev, format, ...) \
379 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
381 /* The returned number is valid only when the dev is eswitch manager. */
382 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
384 return mlx5_core_is_ecpf_esw_manager(dev) ?
385 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
388 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
390 /* Uplink always locate at the last element of the array.*/
391 return esw->total_vports - 1;
394 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
396 return esw->total_vports - 2;
399 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
402 if (vport_num == MLX5_VPORT_ECPF) {
403 if (!mlx5_ecpf_vport_exists(esw->dev))
404 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
405 return mlx5_eswitch_ecpf_idx(esw);
408 if (vport_num == MLX5_VPORT_UPLINK)
409 return mlx5_eswitch_uplink_idx(esw);
414 static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
417 if (index == mlx5_eswitch_ecpf_idx(esw) &&
418 mlx5_ecpf_vport_exists(esw->dev))
419 return MLX5_VPORT_ECPF;
421 if (index == mlx5_eswitch_uplink_idx(esw))
422 return MLX5_VPORT_UPLINK;
427 #else /* CONFIG_MLX5_ESWITCH */
428 /* eswitch API stubs */
429 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
430 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
431 static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
432 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
433 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
435 #define FDB_MAX_CHAIN 1
436 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
437 #define FDB_MAX_PRIO 1
439 #endif /* CONFIG_MLX5_ESWITCH */
441 #endif /* __MLX5_ESWITCH_H__ */