drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <net/tc_act/tc_mirred.h>
  42 #include <net/tc_act/tc_vlan.h>
  43 #include <net/tc_act/tc_tunnel_key.h>
  44 #include <net/tc_act/tc_pedit.h>
  45 #include <net/tc_act/tc_csum.h>
  46 #include <net/arp.h>
  47 #include "en.h"
  48 #include "en_rep.h"
  49 #include "en_tc.h"
  50 #include "eswitch.h"
  51 #include "fs_core.h"
  52 #include "en/port.h"
  53 #include "en/tc_tun.h"
  54 #include "lib/devcom.h"
  55
  56 struct mlx5_nic_flow_attr {
  57         u32 action;
  58         u32 flow_tag;
  59         u32 mod_hdr_id;
  60         u32 hairpin_tirn;
  61         u8 match_level;
  62         struct mlx5_flow_table  *hairpin_ft;
  63         struct mlx5_fc          *counter;
  64 };
  65
  66 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
  67
  68 enum {
  69         MLX5E_TC_FLOW_INGRESS   = MLX5E_TC_INGRESS,
  70         MLX5E_TC_FLOW_EGRESS    = MLX5E_TC_EGRESS,
  71         MLX5E_TC_FLOW_ESWITCH   = MLX5E_TC_ESW_OFFLOAD,
  72         MLX5E_TC_FLOW_NIC       = MLX5E_TC_NIC_OFFLOAD,
  73         MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
  74         MLX5E_TC_FLOW_HAIRPIN   = BIT(MLX5E_TC_FLOW_BASE + 1),
  75         MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
  76         MLX5E_TC_FLOW_SLOW        = BIT(MLX5E_TC_FLOW_BASE + 3),
  77         MLX5E_TC_FLOW_DUP         = BIT(MLX5E_TC_FLOW_BASE + 4),
  78 };
  79
  80 #define MLX5E_TC_MAX_SPLITS 1
  81
  82 /* Helper struct for accessing a struct containing list_head array.
  83  * Containing struct
  84  *   |- Helper array
  85  *      [0] Helper item 0
  86  *          |- list_head item 0
  87  *          |- index (0)
  88  *      [1] Helper item 1
  89  *          |- list_head item 1
  90  *          |- index (1)
  91  * To access the containing struct from one of the list_head items:
  92  * 1. Get the helper item from the list_head item using
  93  *    helper item =
  94  *        container_of(list_head item, helper struct type, list_head field)
  95  * 2. Get the contining struct from the helper item and its index in the array:
  96  *    containing struct =
  97  *        container_of(helper item, containing struct type, helper field[index])
  98  */
  99 struct encap_flow_item {
 100         struct list_head list;
 101         int index;
 102 };
 103
 104 struct mlx5e_tc_flow {
 105         struct rhash_head       node;
 106         struct mlx5e_priv       *priv;
 107         u64                     cookie;
 108         u16                     flags;
 109         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 110         /* Flow can be associated with multiple encap IDs.
 111          * The number of encaps is bounded by the number of supported
 112          * destinations.
 113          */
 114         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 115         struct mlx5e_tc_flow    *peer_flow;
 116         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 117         struct list_head        hairpin; /* flows sharing the same hairpin */
 118         struct list_head        peer;    /* flows with peer flow */
 119         union {
 120                 struct mlx5_esw_flow_attr esw_attr[0];
 121                 struct mlx5_nic_flow_attr nic_attr[0];
 122         };
 123 };
 124
 125 struct mlx5e_tc_flow_parse_attr {
 126         struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 127         struct net_device *filter_dev;
 128         struct mlx5_flow_spec spec;
 129         int num_mod_hdr_actions;
 130         int max_mod_hdr_actions;
 131         void *mod_hdr_actions;
 132         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 133 };
 134
 135 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 136 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 137
 138 struct mlx5e_hairpin {
 139         struct mlx5_hairpin *pair;
 140
 141         struct mlx5_core_dev *func_mdev;
 142         struct mlx5e_priv *func_priv;
 143         u32 tdn;
 144         u32 tirn;
 145
 146         int num_channels;
 147         struct mlx5e_rqt indir_rqt;
 148         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 149         struct mlx5e_ttc_table ttc;
 150 };
 151
 152 struct mlx5e_hairpin_entry {
 153         /* a node of a hash table which keeps all the  hairpin entries */
 154         struct hlist_node hairpin_hlist;
 155
 156         /* flows sharing the same hairpin */
 157         struct list_head flows;
 158
 159         u16 peer_vhca_id;
 160         u8 prio;
 161         struct mlx5e_hairpin *hp;
 162 };
 163
 164 struct mod_hdr_key {
 165         int num_actions;
 166         void *actions;
 167 };
 168
 169 struct mlx5e_mod_hdr_entry {
 170         /* a node of a hash table which keeps all the mod_hdr entries */
 171         struct hlist_node mod_hdr_hlist;
 172
 173         /* flows sharing the same mod_hdr entry */
 174         struct list_head flows;
 175
 176         struct mod_hdr_key key;
 177
 178         u32 mod_hdr_id;
 179 };
 180
 181 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
 182
 183 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 184 {
 185         return jhash(key->actions,
 186                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 187 }
 188
 189 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 190                                    struct mod_hdr_key *b)
 191 {
 192         if (a->num_actions != b->num_actions)
 193                 return 1;
 194
 195         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 196 }
 197
 198 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 199                                 struct mlx5e_tc_flow *flow,
 200                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 201 {
 202         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 203         int num_actions, actions_size, namespace, err;
 204         struct mlx5e_mod_hdr_entry *mh;
 205         struct mod_hdr_key key;
 206         bool found = false;
 207         u32 hash_key;
 208
 209         num_actions  = parse_attr->num_mod_hdr_actions;
 210         actions_size = MLX5_MH_ACT_SZ * num_actions;
 211
 212         key.actions = parse_attr->mod_hdr_actions;
 213         key.num_actions = num_actions;
 214
 215         hash_key = hash_mod_hdr_info(&key);
 216
 217         if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
 218                 namespace = MLX5_FLOW_NAMESPACE_FDB;
 219                 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
 220                                        mod_hdr_hlist, hash_key) {
 221                         if (!cmp_mod_hdr_info(&mh->key, &key)) {
 222                                 found = true;
 223                                 break;
 224                         }
 225                 }
 226         } else {
 227                 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
 228                 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
 229                                        mod_hdr_hlist, hash_key) {
 230                         if (!cmp_mod_hdr_info(&mh->key, &key)) {
 231                                 found = true;
 232                                 break;
 233                         }
 234                 }
 235         }
 236
 237         if (found)
 238                 goto attach_flow;
 239
 240         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 241         if (!mh)
 242                 return -ENOMEM;
 243
 244         mh->key.actions = (void *)mh + sizeof(*mh);
 245         memcpy(mh->key.actions, key.actions, actions_size);
 246         mh->key.num_actions = num_actions;
 247         INIT_LIST_HEAD(&mh->flows);
 248
 249         err = mlx5_modify_header_alloc(priv->mdev, namespace,
 250                                        mh->key.num_actions,
 251                                        mh->key.actions,
 252                                        &mh->mod_hdr_id);
 253         if (err)
 254                 goto out_err;
 255
 256         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
 257                 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
 258         else
 259                 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
 260
 261 attach_flow:
 262         list_add(&flow->mod_hdr, &mh->flows);
 263         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
 264                 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
 265         else
 266                 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
 267
 268         return 0;
 269
 270 out_err:
 271         kfree(mh);
 272         return err;
 273 }
 274
 275 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 276                                  struct mlx5e_tc_flow *flow)
 277 {
 278         struct list_head *next = flow->mod_hdr.next;
 279
 280         list_del(&flow->mod_hdr);
 281
 282         if (list_empty(next)) {
 283                 struct mlx5e_mod_hdr_entry *mh;
 284
 285                 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
 286
 287                 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
 288                 hash_del(&mh->mod_hdr_hlist);
 289                 kfree(mh);
 290         }
 291 }
 292
 293 static
 294 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 295 {
 296         struct net_device *netdev;
 297         struct mlx5e_priv *priv;
 298
 299         netdev = __dev_get_by_index(net, ifindex);
 300         priv = netdev_priv(netdev);
 301         return priv->mdev;
 302 }
 303
 304 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 305 {
 306         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 307         void *tirc;
 308         int err;
 309
 310         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 311         if (err)
 312                 goto alloc_tdn_err;
 313
 314         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 315
 316         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 317         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 318         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 319
 320         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 321         if (err)
 322                 goto create_tir_err;
 323
 324         return 0;
 325
 326 create_tir_err:
 327         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 328 alloc_tdn_err:
 329         return err;
 330 }
 331
 332 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 333 {
 334         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 335         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 336 }
 337
 338 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 339 {
 340         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 341         struct mlx5e_priv *priv = hp->func_priv;
 342         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 343
 344         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 345                                       hp->num_channels);
 346
 347         for (i = 0; i < sz; i++) {
 348                 ix = i;
 349                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 350                         ix = mlx5e_bits_invert(i, ilog2(sz));
 351                 ix = indirection_rqt[ix];
 352                 rqn = hp->pair->rqn[ix];
 353                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 354         }
 355 }
 356
 357 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 358 {
 359         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 360         struct mlx5e_priv *priv = hp->func_priv;
 361         struct mlx5_core_dev *mdev = priv->mdev;
 362         void *rqtc;
 363         u32 *in;
 364
 365         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 366         in = kvzalloc(inlen, GFP_KERNEL);
 367         if (!in)
 368                 return -ENOMEM;
 369
 370         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 371
 372         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 373         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 374
 375         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 376
 377         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 378         if (!err)
 379                 hp->indir_rqt.enabled = true;
 380
 381         kvfree(in);
 382         return err;
 383 }
 384
 385 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 386 {
 387         struct mlx5e_priv *priv = hp->func_priv;
 388         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 389         int tt, i, err;
 390         void *tirc;
 391
 392         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 393                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 394
 395                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 396                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 397
 398                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 399                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 400                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 401                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 402
 403                 err = mlx5_core_create_tir(hp->func_mdev, in,
 404                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 405                 if (err) {
 406                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 407                         goto err_destroy_tirs;
 408                 }
 409         }
 410         return 0;
 411
 412 err_destroy_tirs:
 413         for (i = 0; i < tt; i++)
 414                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 415         return err;
 416 }
 417
 418 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 419 {
 420         int tt;
 421
 422         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 423                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 424 }
 425
 426 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 427                                          struct ttc_params *ttc_params)
 428 {
 429         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 430         int tt;
 431
 432         memset(ttc_params, 0, sizeof(*ttc_params));
 433
 434         ttc_params->any_tt_tirn = hp->tirn;
 435
 436         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 437                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 438
 439         ft_attr->max_fte = MLX5E_NUM_TT;
 440         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 441         ft_attr->prio = MLX5E_TC_PRIO;
 442 }
 443
 444 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 445 {
 446         struct mlx5e_priv *priv = hp->func_priv;
 447         struct ttc_params ttc_params;
 448         int err;
 449
 450         err = mlx5e_hairpin_create_indirect_rqt(hp);
 451         if (err)
 452                 return err;
 453
 454         err = mlx5e_hairpin_create_indirect_tirs(hp);
 455         if (err)
 456                 goto err_create_indirect_tirs;
 457
 458         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 459         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 460         if (err)
 461                 goto err_create_ttc_table;
 462
 463         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 464                    hp->num_channels, hp->ttc.ft.t->id);
 465
 466         return 0;
 467
 468 err_create_ttc_table:
 469         mlx5e_hairpin_destroy_indirect_tirs(hp);
 470 err_create_indirect_tirs:
 471         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 472
 473         return err;
 474 }
 475
 476 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 477 {
 478         struct mlx5e_priv *priv = hp->func_priv;
 479
 480         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 481         mlx5e_hairpin_destroy_indirect_tirs(hp);
 482         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 483 }
 484
 485 static struct mlx5e_hairpin *
 486 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 487                      int peer_ifindex)
 488 {
 489         struct mlx5_core_dev *func_mdev, *peer_mdev;
 490         struct mlx5e_hairpin *hp;
 491         struct mlx5_hairpin *pair;
 492         int err;
 493
 494         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 495         if (!hp)
 496                 return ERR_PTR(-ENOMEM);
 497
 498         func_mdev = priv->mdev;
 499         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 500
 501         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 502         if (IS_ERR(pair)) {
 503                 err = PTR_ERR(pair);
 504                 goto create_pair_err;
 505         }
 506         hp->pair = pair;
 507         hp->func_mdev = func_mdev;
 508         hp->func_priv = priv;
 509         hp->num_channels = params->num_channels;
 510
 511         err = mlx5e_hairpin_create_transport(hp);
 512         if (err)
 513                 goto create_transport_err;
 514
 515         if (hp->num_channels > 1) {
 516                 err = mlx5e_hairpin_rss_init(hp);
 517                 if (err)
 518                         goto rss_init_err;
 519         }
 520
 521         return hp;
 522
 523 rss_init_err:
 524         mlx5e_hairpin_destroy_transport(hp);
 525 create_transport_err:
 526         mlx5_core_hairpin_destroy(hp->pair);
 527 create_pair_err:
 528         kfree(hp);
 529         return ERR_PTR(err);
 530 }
 531
 532 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 533 {
 534         if (hp->num_channels > 1)
 535                 mlx5e_hairpin_rss_cleanup(hp);
 536         mlx5e_hairpin_destroy_transport(hp);
 537         mlx5_core_hairpin_destroy(hp->pair);
 538         kvfree(hp);
 539 }
 540
 541 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 542 {
 543         return (peer_vhca_id << 16 | prio);
 544 }
 545
 546 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 547                                                      u16 peer_vhca_id, u8 prio)
 548 {
 549         struct mlx5e_hairpin_entry *hpe;
 550         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 551
 552         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 553                                hairpin_hlist, hash_key) {
 554                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
 555                         return hpe;
 556         }
 557
 558         return NULL;
 559 }
 560
 561 #define UNKNOWN_MATCH_PRIO 8
 562
 563 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 564                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 565                                   struct netlink_ext_ack *extack)
 566 {
 567         void *headers_c, *headers_v;
 568         u8 prio_val, prio_mask = 0;
 569         bool vlan_present;
 570
 571 #ifdef CONFIG_MLX5_CORE_EN_DCB
 572         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 573                 NL_SET_ERR_MSG_MOD(extack,
 574                                    "only PCP trust state supported for hairpin");
 575                 return -EOPNOTSUPP;
 576         }
 577 #endif
 578         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 579         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 580
 581         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 582         if (vlan_present) {
 583                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 584                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 585         }
 586
 587         if (!vlan_present || !prio_mask) {
 588                 prio_val = UNKNOWN_MATCH_PRIO;
 589         } else if (prio_mask != 0x7) {
 590                 NL_SET_ERR_MSG_MOD(extack,
 591                                    "masked priority match not supported for hairpin");
 592                 return -EOPNOTSUPP;
 593         }
 594
 595         *match_prio = prio_val;
 596         return 0;
 597 }
 598
 599 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 600                                   struct mlx5e_tc_flow *flow,
 601                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 602                                   struct netlink_ext_ack *extack)
 603 {
 604         int peer_ifindex = parse_attr->mirred_ifindex[0];
 605         struct mlx5_hairpin_params params;
 606         struct mlx5_core_dev *peer_mdev;
 607         struct mlx5e_hairpin_entry *hpe;
 608         struct mlx5e_hairpin *hp;
 609         u64 link_speed64;
 610         u32 link_speed;
 611         u8 match_prio;
 612         u16 peer_id;
 613         int err;
 614
 615         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 616         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 617                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 618                 return -EOPNOTSUPP;
 619         }
 620
 621         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 622         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 623                                      extack);
 624         if (err)
 625                 return err;
 626         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 627         if (hpe)
 628                 goto attach_flow;
 629
 630         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 631         if (!hpe)
 632                 return -ENOMEM;
 633
 634         INIT_LIST_HEAD(&hpe->flows);
 635         hpe->peer_vhca_id = peer_id;
 636         hpe->prio = match_prio;
 637
 638         params.log_data_size = 15;
 639         params.log_data_size = min_t(u8, params.log_data_size,
 640                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 641         params.log_data_size = max_t(u8, params.log_data_size,
 642                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 643
 644         params.log_num_packets = params.log_data_size -
 645                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 646         params.log_num_packets = min_t(u8, params.log_num_packets,
 647                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 648
 649         params.q_counter = priv->q_counter;
 650         /* set hairpin pair per each 50Gbs share of the link */
 651         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 652         link_speed = max_t(u32, link_speed, 50000);
 653         link_speed64 = link_speed;
 654         do_div(link_speed64, 50000);
 655         params.num_channels = link_speed64;
 656
 657         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 658         if (IS_ERR(hp)) {
 659                 err = PTR_ERR(hp);
 660                 goto create_hairpin_err;
 661         }
 662
 663         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 664                    hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
 665                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 666
 667         hpe->hp = hp;
 668         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 669                  hash_hairpin_info(peer_id, match_prio));
 670
 671 attach_flow:
 672         if (hpe->hp->num_channels > 1) {
 673                 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
 674                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 675         } else {
 676                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 677         }
 678         list_add(&flow->hairpin, &hpe->flows);
 679
 680         return 0;
 681
 682 create_hairpin_err:
 683         kfree(hpe);
 684         return err;
 685 }
 686
 687 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 688                                    struct mlx5e_tc_flow *flow)
 689 {
 690         struct list_head *next = flow->hairpin.next;
 691
 692         list_del(&flow->hairpin);
 693
 694         /* no more hairpin flows for us, release the hairpin pair */
 695         if (list_empty(next)) {
 696                 struct mlx5e_hairpin_entry *hpe;
 697
 698                 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
 699
 700                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 701                            hpe->hp->pair->peer_mdev->priv.name);
 702
 703                 mlx5e_hairpin_destroy(hpe->hp);
 704                 hash_del(&hpe->hairpin_hlist);
 705                 kfree(hpe);
 706         }
 707 }
 708
 709 static int
 710 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
 711                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 712                       struct mlx5e_tc_flow *flow,
 713                       struct netlink_ext_ack *extack)
 714 {
 715         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 716         struct mlx5_core_dev *dev = priv->mdev;
 717         struct mlx5_flow_destination dest[2] = {};
 718         struct mlx5_flow_act flow_act = {
 719                 .action = attr->action,
 720                 .flow_tag = attr->flow_tag,
 721                 .reformat_id = 0,
 722                 .flags    = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
 723         };
 724         struct mlx5_fc *counter = NULL;
 725         bool table_created = false;
 726         int err, dest_ix = 0;
 727
 728         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
 729                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
 730                 if (err) {
 731                         goto err_add_hairpin_flow;
 732                 }
 733                 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
 734                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 735                         dest[dest_ix].ft = attr->hairpin_ft;
 736                 } else {
 737                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 738                         dest[dest_ix].tir_num = attr->hairpin_tirn;
 739                 }
 740                 dest_ix++;
 741         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
 742                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 743                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
 744                 dest_ix++;
 745         }
 746
 747         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 748                 counter = mlx5_fc_create(dev, true);
 749                 if (IS_ERR(counter)) {
 750                         err = PTR_ERR(counter);
 751                         goto err_fc_create;
 752                 }
 753                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
 754                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
 755                 dest_ix++;
 756                 attr->counter = counter;
 757         }
 758
 759         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 760                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 761                 flow_act.modify_id = attr->mod_hdr_id;
 762                 kfree(parse_attr->mod_hdr_actions);
 763                 if (err)
 764                         goto err_create_mod_hdr_id;
 765         }
 766
 767         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
 768                 int tc_grp_size, tc_tbl_size;
 769                 u32 max_flow_counter;
 770
 771                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
 772                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
 773
 774                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
 775
 776                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
 777                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
 778
 779                 priv->fs.tc.t =
 780                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
 781                                                             MLX5E_TC_PRIO,
 782                                                             tc_tbl_size,
 783                                                             MLX5E_TC_TABLE_NUM_GROUPS,
 784                                                             MLX5E_TC_FT_LEVEL, 0);
 785                 if (IS_ERR(priv->fs.tc.t)) {
 786                         NL_SET_ERR_MSG_MOD(extack,
 787                                            "Failed to create tc offload table\n");
 788                         netdev_err(priv->netdev,
 789                                    "Failed to create tc offload table\n");
 790                         err = PTR_ERR(priv->fs.tc.t);
 791                         goto err_create_ft;
 792                 }
 793
 794                 table_created = true;
 795         }
 796
 797         if (attr->match_level != MLX5_MATCH_NONE)
 798                 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
 799
 800         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
 801                                             &flow_act, dest, dest_ix);
 802
 803         if (IS_ERR(flow->rule[0])) {
 804                 err = PTR_ERR(flow->rule[0]);
 805                 goto err_add_rule;
 806         }
 807
 808         return 0;
 809
 810 err_add_rule:
 811         if (table_created) {
 812                 mlx5_destroy_flow_table(priv->fs.tc.t);
 813                 priv->fs.tc.t = NULL;
 814         }
 815 err_create_ft:
 816         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
 817                 mlx5e_detach_mod_hdr(priv, flow);
 818 err_create_mod_hdr_id:
 819         mlx5_fc_destroy(dev, counter);
 820 err_fc_create:
 821         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
 822                 mlx5e_hairpin_flow_del(priv, flow);
 823 err_add_hairpin_flow:
 824         return err;
 825 }
 826
 827 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
 828                                   struct mlx5e_tc_flow *flow)
 829 {
 830         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 831         struct mlx5_fc *counter = NULL;
 832
 833         counter = attr->counter;
 834         mlx5_del_flow_rules(flow->rule[0]);
 835         mlx5_fc_destroy(priv->mdev, counter);
 836
 837         if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)  && priv->fs.tc.t) {
 838                 mlx5_destroy_flow_table(priv->fs.tc.t);
 839                 priv->fs.tc.t = NULL;
 840         }
 841
 842         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
 843                 mlx5e_detach_mod_hdr(priv, flow);
 844
 845         if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
 846                 mlx5e_hairpin_flow_del(priv, flow);
 847 }
 848
 849 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
 850                                struct mlx5e_tc_flow *flow, int out_index);
 851
 852 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
 853                               struct ip_tunnel_info *tun_info,
 854                               struct net_device *mirred_dev,
 855                               struct net_device **encap_dev,
 856                               struct mlx5e_tc_flow *flow,
 857                               struct netlink_ext_ack *extack,
 858                               int out_index);
 859
 860 static struct mlx5_flow_handle *
 861 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
 862                            struct mlx5e_tc_flow *flow,
 863                            struct mlx5_flow_spec *spec,
 864                            struct mlx5_esw_flow_attr *attr)
 865 {
 866         struct mlx5_flow_handle *rule;
 867
 868         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 869         if (IS_ERR(rule))
 870                 return rule;
 871
 872         if (attr->split_count) {
 873                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
 874                 if (IS_ERR(flow->rule[1])) {
 875                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 876                         return flow->rule[1];
 877                 }
 878         }
 879
 880         flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
 881         return rule;
 882 }
 883
 884 static void
 885 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
 886                              struct mlx5e_tc_flow *flow,
 887                            struct mlx5_esw_flow_attr *attr)
 888 {
 889         flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
 890
 891         if (attr->split_count)
 892                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
 893
 894         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
 895 }
 896
 897 static struct mlx5_flow_handle *
 898 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
 899                               struct mlx5e_tc_flow *flow,
 900                               struct mlx5_flow_spec *spec,
 901                               struct mlx5_esw_flow_attr *slow_attr)
 902 {
 903         struct mlx5_flow_handle *rule;
 904
 905         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
 906         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 907         slow_attr->split_count = 0;
 908         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
 909
 910         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
 911         if (!IS_ERR(rule))
 912                 flow->flags |= MLX5E_TC_FLOW_SLOW;
 913
 914         return rule;
 915 }
 916
 917 static void
 918 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
 919                                   struct mlx5e_tc_flow *flow,
 920                                   struct mlx5_esw_flow_attr *slow_attr)
 921 {
 922         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
 923         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 924         slow_attr->split_count = 0;
 925         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
 926         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
 927         flow->flags &= ~MLX5E_TC_FLOW_SLOW;
 928 }
 929
 930 static int
 931 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
 932                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 933                       struct mlx5e_tc_flow *flow,
 934                       struct netlink_ext_ack *extack)
 935 {
 936         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 937         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
 938         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
 939         u16 max_prio = mlx5_eswitch_get_prio_range(esw);
 940         struct net_device *out_dev, *encap_dev = NULL;
 941         struct mlx5_fc *counter = NULL;
 942         struct mlx5e_rep_priv *rpriv;
 943         struct mlx5e_priv *out_priv;
 944         int err = 0, encap_err = 0;
 945         int out_index;
 946
 947         if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
 948                 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
 949                 return -EOPNOTSUPP;
 950         }
 951
 952         if (attr->chain > max_chain) {
 953                 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
 954                 err = -EOPNOTSUPP;
 955                 goto err_max_prio_chain;
 956         }
 957
 958         if (attr->prio > max_prio) {
 959                 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
 960                 err = -EOPNOTSUPP;
 961                 goto err_max_prio_chain;
 962         }
 963
 964         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
 965                 int mirred_ifindex;
 966
 967                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
 968                         continue;
 969
 970                 mirred_ifindex = attr->parse_attr->mirred_ifindex[out_index];
 971                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
 972                                              mirred_ifindex);
 973                 err = mlx5e_attach_encap(priv,
 974                                          &parse_attr->tun_info[out_index],
 975                                          out_dev, &encap_dev, flow,
 976                                          extack, out_index);
 977                 if (err && err != -EAGAIN)
 978                         goto err_attach_encap;
 979                 if (err == -EAGAIN)
 980                         encap_err = err;
 981                 out_priv = netdev_priv(encap_dev);
 982                 rpriv = out_priv->ppriv;
 983                 attr->dests[out_index].rep = rpriv->rep;
 984                 attr->dests[out_index].mdev = out_priv->mdev;
 985         }
 986
 987         err = mlx5_eswitch_add_vlan_action(esw, attr);
 988         if (err)
 989                 goto err_add_vlan;
 990
 991         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 992                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 993                 kfree(parse_attr->mod_hdr_actions);
 994                 if (err)
 995                         goto err_mod_hdr;
 996         }
 997
 998         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 999                 counter = mlx5_fc_create(attr->counter_dev, true);
1000                 if (IS_ERR(counter)) {
1001                         err = PTR_ERR(counter);
1002                         goto err_create_counter;
1003                 }
1004
1005                 attr->counter = counter;
1006         }
1007
1008         /* we get here if (1) there's no error or when
1009          * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
1010          */
1011         if (encap_err == -EAGAIN) {
1012                 /* continue with goto slow path rule instead */
1013                 struct mlx5_esw_flow_attr slow_attr;
1014
1015                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1016         } else {
1017                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1018         }
1019
1020         if (IS_ERR(flow->rule[0])) {
1021                 err = PTR_ERR(flow->rule[0]);
1022                 goto err_add_rule;
1023         }
1024
1025         return 0;
1026
1027 err_add_rule:
1028         mlx5_fc_destroy(attr->counter_dev, counter);
1029 err_create_counter:
1030         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1031                 mlx5e_detach_mod_hdr(priv, flow);
1032 err_mod_hdr:
1033         mlx5_eswitch_del_vlan_action(esw, attr);
1034 err_add_vlan:
1035         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1036                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1037                         mlx5e_detach_encap(priv, flow, out_index);
1038 err_attach_encap:
1039 err_max_prio_chain:
1040         return err;
1041 }
1042
1043 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1044                                   struct mlx5e_tc_flow *flow)
1045 {
1046         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1047         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1048         struct mlx5_esw_flow_attr slow_attr;
1049         int out_index;
1050
1051         if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1052                 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1053                         mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1054                 else
1055                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1056         }
1057
1058         mlx5_eswitch_del_vlan_action(esw, attr);
1059
1060         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1061                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1062                         mlx5e_detach_encap(priv, flow, out_index);
1063         kvfree(attr->parse_attr);
1064
1065         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1066                 mlx5e_detach_mod_hdr(priv, flow);
1067
1068         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1069                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1070 }
1071
1072 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1073                               struct mlx5e_encap_entry *e)
1074 {
1075         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1076         struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1077         struct mlx5_flow_handle *rule;
1078         struct mlx5_flow_spec *spec;
1079         struct encap_flow_item *efi;
1080         struct mlx5e_tc_flow *flow;
1081         int err;
1082
1083         err = mlx5_packet_reformat_alloc(priv->mdev,
1084                                          e->reformat_type,
1085                                          e->encap_size, e->encap_header,
1086                                          MLX5_FLOW_NAMESPACE_FDB,
1087                                          &e->encap_id);
1088         if (err) {
1089                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1090                                err);
1091                 return;
1092         }
1093         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1094         mlx5e_rep_queue_neigh_stats_work(priv);
1095
1096         list_for_each_entry(efi, &e->flows, list) {
1097                 bool all_flow_encaps_valid = true;
1098                 int i;
1099
1100                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1101                 esw_attr = flow->esw_attr;
1102                 spec = &esw_attr->parse_attr->spec;
1103
1104                 esw_attr->dests[efi->index].encap_id = e->encap_id;
1105                 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1106                 /* Flow can be associated with multiple encap entries.
1107                  * Before offloading the flow verify that all of them have
1108                  * a valid neighbour.
1109                  */
1110                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1111                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1112                                 continue;
1113                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1114                                 all_flow_encaps_valid = false;
1115                                 break;
1116                         }
1117                 }
1118                 /* Do not offload flows with unresolved neighbors */
1119                 if (!all_flow_encaps_valid)
1120                         continue;
1121                 /* update from slow path rule to encap rule */
1122                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1123                 if (IS_ERR(rule)) {
1124                         err = PTR_ERR(rule);
1125                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1126                                        err);
1127                         continue;
1128                 }
1129
1130                 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1131                 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
1132                 flow->rule[0] = rule;
1133         }
1134 }
1135
1136 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1137                               struct mlx5e_encap_entry *e)
1138 {
1139         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1140         struct mlx5_esw_flow_attr slow_attr;
1141         struct mlx5_flow_handle *rule;
1142         struct mlx5_flow_spec *spec;
1143         struct encap_flow_item *efi;
1144         struct mlx5e_tc_flow *flow;
1145         int err;
1146
1147         list_for_each_entry(efi, &e->flows, list) {
1148                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1149                 spec = &flow->esw_attr->parse_attr->spec;
1150
1151                 /* update from encap rule to slow path rule */
1152                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1153                 /* mark the flow's encap dest as non-valid */
1154                 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1155
1156                 if (IS_ERR(rule)) {
1157                         err = PTR_ERR(rule);
1158                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1159                                        err);
1160                         continue;
1161                 }
1162
1163                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1164                 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1165                 flow->rule[0] = rule;
1166         }
1167
1168         /* we know that the encap is valid */
1169         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1170         mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1171 }
1172
1173 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1174 {
1175         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1176                 return flow->esw_attr->counter;
1177         else
1178                 return flow->nic_attr->counter;
1179 }
1180
1181 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1182 {
1183         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1184         u64 bytes, packets, lastuse = 0;
1185         struct mlx5e_tc_flow *flow;
1186         struct mlx5e_encap_entry *e;
1187         struct mlx5_fc *counter;
1188         struct neigh_table *tbl;
1189         bool neigh_used = false;
1190         struct neighbour *n;
1191
1192         if (m_neigh->family == AF_INET)
1193                 tbl = &arp_tbl;
1194 #if IS_ENABLED(CONFIG_IPV6)
1195         else if (m_neigh->family == AF_INET6)
1196                 tbl = &nd_tbl;
1197 #endif
1198         else
1199                 return;
1200
1201         list_for_each_entry(e, &nhe->encap_list, encap_list) {
1202                 struct encap_flow_item *efi;
1203                 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1204                         continue;
1205                 list_for_each_entry(efi, &e->flows, list) {
1206                         flow = container_of(efi, struct mlx5e_tc_flow,
1207                                             encaps[efi->index]);
1208                         if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1209                                 counter = mlx5e_tc_get_counter(flow);
1210                                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1211                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1212                                         neigh_used = true;
1213                                         break;
1214                                 }
1215                         }
1216                 }
1217                 if (neigh_used)
1218                         break;
1219         }
1220
1221         if (neigh_used) {
1222                 nhe->reported_lastuse = jiffies;
1223
1224                 /* find the relevant neigh according to the cached device and
1225                  * dst ip pair
1226                  */
1227                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1228                 if (!n)
1229                         return;
1230
1231                 neigh_event_send(n, NULL);
1232                 neigh_release(n);
1233         }
1234 }
1235
1236 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1237                                struct mlx5e_tc_flow *flow, int out_index)
1238 {
1239         struct list_head *next = flow->encaps[out_index].list.next;
1240
1241         list_del(&flow->encaps[out_index].list);
1242         if (list_empty(next)) {
1243                 struct mlx5e_encap_entry *e;
1244
1245                 e = list_entry(next, struct mlx5e_encap_entry, flows);
1246                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1247
1248                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1249                         mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1250
1251                 hash_del_rcu(&e->encap_hlist);
1252                 kfree(e->encap_header);
1253                 kfree(e);
1254         }
1255 }
1256
1257 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1258 {
1259         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1260
1261         if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1262             !(flow->flags & MLX5E_TC_FLOW_DUP))
1263                 return;
1264
1265         mutex_lock(&esw->offloads.peer_mutex);
1266         list_del(&flow->peer);
1267         mutex_unlock(&esw->offloads.peer_mutex);
1268
1269         flow->flags &= ~MLX5E_TC_FLOW_DUP;
1270
1271         mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1272         kvfree(flow->peer_flow);
1273         flow->peer_flow = NULL;
1274 }
1275
1276 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1277 {
1278         struct mlx5_core_dev *dev = flow->priv->mdev;
1279         struct mlx5_devcom *devcom = dev->priv.devcom;
1280         struct mlx5_eswitch *peer_esw;
1281
1282         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1283         if (!peer_esw)
1284                 return;
1285
1286         __mlx5e_tc_del_fdb_peer_flow(flow);
1287         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1288 }
1289
1290 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1291                               struct mlx5e_tc_flow *flow)
1292 {
1293         if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1294                 mlx5e_tc_del_fdb_peer_flow(flow);
1295                 mlx5e_tc_del_fdb_flow(priv, flow);
1296         } else {
1297                 mlx5e_tc_del_nic_flow(priv, flow);
1298         }
1299 }
1300
1301
1302 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1303                              struct mlx5_flow_spec *spec,
1304                              struct tc_cls_flower_offload *f,
1305                              struct net_device *filter_dev, u8 *match_level)
1306 {
1307         struct netlink_ext_ack *extack = f->common.extack;
1308         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1309                                        outer_headers);
1310         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1311                                        outer_headers);
1312         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1313         struct flow_match_control enc_control;
1314         int err;
1315
1316         err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1317                                  headers_c, headers_v, match_level);
1318         if (err) {
1319                 NL_SET_ERR_MSG_MOD(extack,
1320                                    "failed to parse tunnel attributes");
1321                 return err;
1322         }
1323
1324         flow_rule_match_enc_control(rule, &enc_control);
1325
1326         if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1327                 struct flow_match_ipv4_addrs match;
1328
1329                 flow_rule_match_enc_ipv4_addrs(rule, &match);
1330                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1331                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1332                          ntohl(match.mask->src));
1333                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1334                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1335                          ntohl(match.key->src));
1336
1337                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1338                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1339                          ntohl(match.mask->dst));
1340                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1341                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1342                          ntohl(match.key->dst));
1343
1344                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1345                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1346         } else if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1347                 struct flow_match_ipv6_addrs match;
1348
1349                 flow_rule_match_enc_ipv6_addrs(rule, &match);
1350                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1351                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1352                        &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1353                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1354                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1355                        &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1356
1357                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1358                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1359                        &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1360                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1361                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1362                        &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1363
1364                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1365                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1366         }
1367
1368         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1369                 struct flow_match_ip match;
1370
1371                 flow_rule_match_enc_ip(rule, &match);
1372                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1373                          match.mask->tos & 0x3);
1374                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1375                          match.key->tos & 0x3);
1376
1377                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1378                          match.mask->tos >> 2);
1379                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1380                          match.key->tos  >> 2);
1381
1382                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1383                          match.mask->ttl);
1384                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1385                          match.key->ttl);
1386
1387                 if (match.mask->ttl &&
1388                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1389                         (priv->mdev,
1390                          ft_field_support.outer_ipv4_ttl)) {
1391                         NL_SET_ERR_MSG_MOD(extack,
1392                                            "Matching on TTL is not supported");
1393                         return -EOPNOTSUPP;
1394                 }
1395
1396         }
1397
1398         /* Enforce DMAC when offloading incoming tunneled flows.
1399          * Flow counters require a match on the DMAC.
1400          */
1401         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1402         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1403         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1404                                      dmac_47_16), priv->netdev->dev_addr);
1405
1406         /* let software handle IP fragments */
1407         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1408         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1409
1410         return 0;
1411 }
1412
1413 static int __parse_cls_flower(struct mlx5e_priv *priv,
1414                               struct mlx5_flow_spec *spec,
1415                               struct tc_cls_flower_offload *f,
1416                               struct net_device *filter_dev,
1417                               u8 *match_level, u8 *tunnel_match_level)
1418 {
1419         struct netlink_ext_ack *extack = f->common.extack;
1420         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1421                                        outer_headers);
1422         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1423                                        outer_headers);
1424         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1425                                     misc_parameters);
1426         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1427                                     misc_parameters);
1428         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1429         struct flow_dissector *dissector = rule->match.dissector;
1430         u16 addr_type = 0;
1431         u8 ip_proto = 0;
1432
1433         *match_level = MLX5_MATCH_NONE;
1434
1435         if (dissector->used_keys &
1436             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1437               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1438               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1439               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1440               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1441               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1442               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1443               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1444               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1445               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1446               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1447               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1448               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1449               BIT(FLOW_DISSECTOR_KEY_TCP) |
1450               BIT(FLOW_DISSECTOR_KEY_IP)  |
1451               BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
1452                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1453                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1454                             dissector->used_keys);
1455                 return -EOPNOTSUPP;
1456         }
1457
1458         if ((flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1459              flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1460              flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1461             flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1462                 struct flow_match_control match;
1463
1464                 flow_rule_match_enc_control(rule, &match);
1465                 switch (match.key->addr_type) {
1466                 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
1467                 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
1468                         if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
1469                                 return -EOPNOTSUPP;
1470                         break;
1471                 default:
1472                         return -EOPNOTSUPP;
1473                 }
1474
1475                 /* In decap flow, header pointers should point to the inner
1476                  * headers, outer header were already set by parse_tunnel_attr
1477                  */
1478                 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1479                                          inner_headers);
1480                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1481                                          inner_headers);
1482         }
1483
1484         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1485                 struct flow_match_basic match;
1486
1487                 flow_rule_match_basic(rule, &match);
1488                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1489                          ntohs(match.mask->n_proto));
1490                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1491                          ntohs(match.key->n_proto));
1492
1493                 if (match.mask->n_proto)
1494                         *match_level = MLX5_MATCH_L2;
1495         }
1496
1497         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1498                 struct flow_match_vlan match;
1499
1500                 flow_rule_match_vlan(rule, &match);
1501                 if (match.mask->vlan_id ||
1502                     match.mask->vlan_priority ||
1503                     match.mask->vlan_tpid) {
1504                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1505                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1506                                          svlan_tag, 1);
1507                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1508                                          svlan_tag, 1);
1509                         } else {
1510                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1511                                          cvlan_tag, 1);
1512                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1513                                          cvlan_tag, 1);
1514                         }
1515
1516                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1517                                  match.mask->vlan_id);
1518                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1519                                  match.key->vlan_id);
1520
1521                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1522                                  match.mask->vlan_priority);
1523                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1524                                  match.key->vlan_priority);
1525
1526                         *match_level = MLX5_MATCH_L2;
1527                 }
1528         } else if (*match_level != MLX5_MATCH_NONE) {
1529                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1530                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1531                 *match_level = MLX5_MATCH_L2;
1532         }
1533
1534         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1535                 struct flow_match_vlan match;
1536
1537                 flow_rule_match_vlan(rule, &match);
1538                 if (match.mask->vlan_id ||
1539                     match.mask->vlan_priority ||
1540                     match.mask->vlan_tpid) {
1541                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1542                                 MLX5_SET(fte_match_set_misc, misc_c,
1543                                          outer_second_svlan_tag, 1);
1544                                 MLX5_SET(fte_match_set_misc, misc_v,
1545                                          outer_second_svlan_tag, 1);
1546                         } else {
1547                                 MLX5_SET(fte_match_set_misc, misc_c,
1548                                          outer_second_cvlan_tag, 1);
1549                                 MLX5_SET(fte_match_set_misc, misc_v,
1550                                          outer_second_cvlan_tag, 1);
1551                         }
1552
1553                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1554                                  match.mask->vlan_id);
1555                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1556                                  match.key->vlan_id);
1557                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1558                                  match.mask->vlan_priority);
1559                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1560                                  match.key->vlan_priority);
1561
1562                         *match_level = MLX5_MATCH_L2;
1563                 }
1564         }
1565
1566         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1567                 struct flow_match_eth_addrs match;
1568
1569                 flow_rule_match_eth_addrs(rule, &match);
1570                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1571                                              dmac_47_16),
1572                                 match.mask->dst);
1573                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1574                                              dmac_47_16),
1575                                 match.key->dst);
1576
1577                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1578                                              smac_47_16),
1579                                 match.mask->src);
1580                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1581                                              smac_47_16),
1582                                 match.key->src);
1583
1584                 if (!is_zero_ether_addr(match.mask->src) ||
1585                     !is_zero_ether_addr(match.mask->dst))
1586                         *match_level = MLX5_MATCH_L2;
1587         }
1588
1589         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1590                 struct flow_match_control match;
1591
1592                 flow_rule_match_control(rule, &match);
1593                 addr_type = match.key->addr_type;
1594
1595                 /* the HW doesn't support frag first/later */
1596                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
1597                         return -EOPNOTSUPP;
1598
1599                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
1600                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1601                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1602                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
1603
1604                         /* the HW doesn't need L3 inline to match on frag=no */
1605                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
1606                                 *match_level = MLX5_MATCH_L2;
1607         /* ***  L2 attributes parsing up to here *** */
1608                         else
1609                                 *match_level = MLX5_MATCH_L3;
1610                 }
1611         }
1612
1613         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1614                 struct flow_match_basic match;
1615
1616                 flow_rule_match_basic(rule, &match);
1617                 ip_proto = match.key->ip_proto;
1618
1619                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1620                          match.mask->ip_proto);
1621                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1622                          match.key->ip_proto);
1623
1624                 if (match.mask->ip_proto)
1625                         *match_level = MLX5_MATCH_L3;
1626         }
1627
1628         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1629                 struct flow_match_ipv4_addrs match;
1630
1631                 flow_rule_match_ipv4_addrs(rule, &match);
1632                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1633                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1634                        &match.mask->src, sizeof(match.mask->src));
1635                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1636                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1637                        &match.key->src, sizeof(match.key->src));
1638                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1639                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1640                        &match.mask->dst, sizeof(match.mask->dst));
1641                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1642                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1643                        &match.key->dst, sizeof(match.key->dst));
1644
1645                 if (match.mask->src || match.mask->dst)
1646                         *match_level = MLX5_MATCH_L3;
1647         }
1648
1649         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1650                 struct flow_match_ipv6_addrs match;
1651
1652                 flow_rule_match_ipv6_addrs(rule, &match);
1653                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1654                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1655                        &match.mask->src, sizeof(match.mask->src));
1656                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1657                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1658                        &match.key->src, sizeof(match.key->src));
1659
1660                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1661                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1662                        &match.mask->dst, sizeof(match.mask->dst));
1663                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1664                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1665                        &match.key->dst, sizeof(match.key->dst));
1666
1667                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1668                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
1669                         *match_level = MLX5_MATCH_L3;
1670         }
1671
1672         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1673                 struct flow_match_ip match;
1674
1675                 flow_rule_match_ip(rule, &match);
1676                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1677                          match.mask->tos & 0x3);
1678                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1679                          match.key->tos & 0x3);
1680
1681                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1682                          match.mask->tos >> 2);
1683                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1684                          match.key->tos  >> 2);
1685
1686                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1687                          match.mask->ttl);
1688                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1689                          match.key->ttl);
1690
1691                 if (match.mask->ttl &&
1692                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1693                                                 ft_field_support.outer_ipv4_ttl)) {
1694                         NL_SET_ERR_MSG_MOD(extack,
1695                                            "Matching on TTL is not supported");
1696                         return -EOPNOTSUPP;
1697                 }
1698
1699                 if (match.mask->tos || match.mask->ttl)
1700                         *match_level = MLX5_MATCH_L3;
1701         }
1702
1703         /* ***  L3 attributes parsing up to here *** */
1704
1705         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1706                 struct flow_match_ports match;
1707
1708                 flow_rule_match_ports(rule, &match);
1709                 switch (ip_proto) {
1710                 case IPPROTO_TCP:
1711                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1712                                  tcp_sport, ntohs(match.mask->src));
1713                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1714                                  tcp_sport, ntohs(match.key->src));
1715
1716                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1717                                  tcp_dport, ntohs(match.mask->dst));
1718                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1719                                  tcp_dport, ntohs(match.key->dst));
1720                         break;
1721
1722                 case IPPROTO_UDP:
1723                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1724                                  udp_sport, ntohs(match.mask->src));
1725                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1726                                  udp_sport, ntohs(match.key->src));
1727
1728                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1729                                  udp_dport, ntohs(match.mask->dst));
1730                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1731                                  udp_dport, ntohs(match.key->dst));
1732                         break;
1733                 default:
1734                         NL_SET_ERR_MSG_MOD(extack,
1735                                            "Only UDP and TCP transports are supported for L4 matching");
1736                         netdev_err(priv->netdev,
1737                                    "Only UDP and TCP transport are supported\n");
1738                         return -EINVAL;
1739                 }
1740
1741                 if (match.mask->src || match.mask->dst)
1742                         *match_level = MLX5_MATCH_L4;
1743         }
1744
1745         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1746                 struct flow_match_tcp match;
1747
1748                 flow_rule_match_tcp(rule, &match);
1749                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1750                          ntohs(match.mask->flags));
1751                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1752                          ntohs(match.key->flags));
1753
1754                 if (match.mask->flags)
1755                         *match_level = MLX5_MATCH_L4;
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int parse_cls_flower(struct mlx5e_priv *priv,
1762                             struct mlx5e_tc_flow *flow,
1763                             struct mlx5_flow_spec *spec,
1764                             struct tc_cls_flower_offload *f,
1765                             struct net_device *filter_dev)
1766 {
1767         struct netlink_ext_ack *extack = f->common.extack;
1768         struct mlx5_core_dev *dev = priv->mdev;
1769         struct mlx5_eswitch *esw = dev->priv.eswitch;
1770         struct mlx5e_rep_priv *rpriv = priv->ppriv;
1771         u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1772         struct mlx5_eswitch_rep *rep;
1773         int err;
1774
1775         err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
1776
1777         if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1778                 rep = rpriv->rep;
1779                 if (rep->vport != MLX5_VPORT_UPLINK &&
1780                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1781                     esw->offloads.inline_mode < match_level)) {
1782                         NL_SET_ERR_MSG_MOD(extack,
1783                                            "Flow is not offloaded due to min inline setting");
1784                         netdev_warn(priv->netdev,
1785                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1786                                     match_level, esw->offloads.inline_mode);
1787                         return -EOPNOTSUPP;
1788                 }
1789         }
1790
1791         if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1792                 flow->esw_attr->match_level = match_level;
1793                 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1794         } else {
1795                 flow->nic_attr->match_level = match_level;
1796         }
1797
1798         return err;
1799 }
1800
1801 struct pedit_headers {
1802         struct ethhdr  eth;
1803         struct iphdr   ip4;
1804         struct ipv6hdr ip6;
1805         struct tcphdr  tcp;
1806         struct udphdr  udp;
1807 };
1808
1809 struct pedit_headers_action {
1810         struct pedit_headers    vals;
1811         struct pedit_headers    masks;
1812         u32                     pedits;
1813 };
1814
1815 static int pedit_header_offsets[] = {
1816         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1817         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1818         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1819         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1820         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1821 };
1822
1823 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1824
1825 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1826                          struct pedit_headers_action *hdrs)
1827 {
1828         u32 *curr_pmask, *curr_pval;
1829
1830         if (hdr_type >= 2)
1831                 goto out_err;
1832
1833         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
1834         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
1835
1836         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
1837                 goto out_err;
1838
1839         *curr_pmask |= mask;
1840         *curr_pval  |= (val & mask);
1841
1842         return 0;
1843
1844 out_err:
1845         return -EOPNOTSUPP;
1846 }
1847
1848 struct mlx5_fields {
1849         u8  field;
1850         u8  size;
1851         u32 offset;
1852 };
1853
1854 #define OFFLOAD(fw_field, size, field, off) \
1855                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1856
1857 static struct mlx5_fields fields[] = {
1858         OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1859         OFFLOAD(DMAC_15_0,  2, eth.h_dest[4], 0),
1860         OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1861         OFFLOAD(SMAC_15_0,  2, eth.h_source[4], 0),
1862         OFFLOAD(ETHERTYPE,  2, eth.h_proto, 0),
1863
1864         OFFLOAD(IP_TTL, 1, ip4.ttl,   0),
1865         OFFLOAD(SIPV4,  4, ip4.saddr, 0),
1866         OFFLOAD(DIPV4,  4, ip4.daddr, 0),
1867
1868         OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1869         OFFLOAD(SIPV6_95_64,  4, ip6.saddr.s6_addr32[1], 0),
1870         OFFLOAD(SIPV6_63_32,  4, ip6.saddr.s6_addr32[2], 0),
1871         OFFLOAD(SIPV6_31_0,   4, ip6.saddr.s6_addr32[3], 0),
1872         OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1873         OFFLOAD(DIPV6_95_64,  4, ip6.daddr.s6_addr32[1], 0),
1874         OFFLOAD(DIPV6_63_32,  4, ip6.daddr.s6_addr32[2], 0),
1875         OFFLOAD(DIPV6_31_0,   4, ip6.daddr.s6_addr32[3], 0),
1876         OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
1877
1878         OFFLOAD(TCP_SPORT, 2, tcp.source,  0),
1879         OFFLOAD(TCP_DPORT, 2, tcp.dest,    0),
1880         OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1881
1882         OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1883         OFFLOAD(UDP_DPORT, 2, udp.dest,   0),
1884 };
1885
1886 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
1887  * max from the SW pedit action. On success, attr->num_mod_hdr_actions
1888  * says how many HW actions were actually parsed.
1889  */
1890 static int offload_pedit_fields(struct pedit_headers_action *hdrs,
1891                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
1892                                 struct netlink_ext_ack *extack)
1893 {
1894         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
1895         int i, action_size, nactions, max_actions, first, last, next_z;
1896         void *s_masks_p, *a_masks_p, *vals_p;
1897         struct mlx5_fields *f;
1898         u8 cmd, field_bsize;
1899         u32 s_mask, a_mask;
1900         unsigned long mask;
1901         __be32 mask_be32;
1902         __be16 mask_be16;
1903         void *action;
1904
1905         set_masks = &hdrs[0].masks;
1906         add_masks = &hdrs[1].masks;
1907         set_vals = &hdrs[0].vals;
1908         add_vals = &hdrs[1].vals;
1909
1910         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1911         action = parse_attr->mod_hdr_actions +
1912                  parse_attr->num_mod_hdr_actions * action_size;
1913
1914         max_actions = parse_attr->max_mod_hdr_actions;
1915         nactions = parse_attr->num_mod_hdr_actions;
1916
1917         for (i = 0; i < ARRAY_SIZE(fields); i++) {
1918                 f = &fields[i];
1919                 /* avoid seeing bits set from previous iterations */
1920                 s_mask = 0;
1921                 a_mask = 0;
1922
1923                 s_masks_p = (void *)set_masks + f->offset;
1924                 a_masks_p = (void *)add_masks + f->offset;
1925
1926                 memcpy(&s_mask, s_masks_p, f->size);
1927                 memcpy(&a_mask, a_masks_p, f->size);
1928
1929                 if (!s_mask && !a_mask) /* nothing to offload here */
1930                         continue;
1931
1932                 if (s_mask && a_mask) {
1933                         NL_SET_ERR_MSG_MOD(extack,
1934                                            "can't set and add to the same HW field");
1935                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1936                         return -EOPNOTSUPP;
1937                 }
1938
1939                 if (nactions == max_actions) {
1940                         NL_SET_ERR_MSG_MOD(extack,
1941                                            "too many pedit actions, can't offload");
1942                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1943                         return -EOPNOTSUPP;
1944                 }
1945
1946                 if (s_mask) {
1947                         cmd  = MLX5_ACTION_TYPE_SET;
1948                         mask = s_mask;
1949                         vals_p = (void *)set_vals + f->offset;
1950                         /* clear to denote we consumed this field */
1951                         memset(s_masks_p, 0, f->size);
1952                 } else {
1953                         cmd  = MLX5_ACTION_TYPE_ADD;
1954                         mask = a_mask;
1955                         vals_p = (void *)add_vals + f->offset;
1956                         /* clear to denote we consumed this field */
1957                         memset(a_masks_p, 0, f->size);
1958                 }
1959
1960                 field_bsize = f->size * BITS_PER_BYTE;
1961
1962                 if (field_bsize == 32) {
1963                         mask_be32 = *(__be32 *)&mask;
1964                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1965                 } else if (field_bsize == 16) {
1966                         mask_be16 = *(__be16 *)&mask;
1967                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1968                 }
1969
1970                 first = find_first_bit(&mask, field_bsize);
1971                 next_z = find_next_zero_bit(&mask, field_bsize, first);
1972                 last  = find_last_bit(&mask, field_bsize);
1973                 if (first < next_z && next_z < last) {
1974                         NL_SET_ERR_MSG_MOD(extack,
1975                                            "rewrite of few sub-fields isn't supported");
1976                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
1977                                mask);
1978                         return -EOPNOTSUPP;
1979                 }
1980
1981                 MLX5_SET(set_action_in, action, action_type, cmd);
1982                 MLX5_SET(set_action_in, action, field, f->field);
1983
1984                 if (cmd == MLX5_ACTION_TYPE_SET) {
1985                         MLX5_SET(set_action_in, action, offset, first);
1986                         /* length is num of bits to be written, zero means length of 32 */
1987                         MLX5_SET(set_action_in, action, length, (last - first + 1));
1988                 }
1989
1990                 if (field_bsize == 32)
1991                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
1992                 else if (field_bsize == 16)
1993                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
1994                 else if (field_bsize == 8)
1995                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
1996
1997                 action += action_size;
1998                 nactions++;
1999         }
2000
2001         parse_attr->num_mod_hdr_actions = nactions;
2002         return 0;
2003 }
2004
2005 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2006                                  struct pedit_headers_action *hdrs,
2007                                  int namespace,
2008                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2009 {
2010         int nkeys, action_size, max_actions;
2011
2012         nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2013                 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2014         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2015
2016         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2017                 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2018         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2019                 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2020
2021         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2022         max_actions = min(max_actions, nkeys * 16);
2023
2024         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2025         if (!parse_attr->mod_hdr_actions)
2026                 return -ENOMEM;
2027
2028         parse_attr->max_mod_hdr_actions = max_actions;
2029         return 0;
2030 }
2031
2032 static const struct pedit_headers zero_masks = {};
2033
2034 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2035                                  const struct flow_action_entry *act, int namespace,
2036                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2037                                  struct pedit_headers_action *hdrs,
2038                                  struct netlink_ext_ack *extack)
2039 {
2040         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2041         int err = -EOPNOTSUPP;
2042         u32 mask, val, offset;
2043         u8 htype;
2044
2045         htype = act->mangle.htype;
2046         err = -EOPNOTSUPP; /* can't be all optimistic */
2047
2048         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2049                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2050                 goto out_err;
2051         }
2052
2053         mask = act->mangle.mask;
2054         val = act->mangle.val;
2055         offset = act->mangle.offset;
2056
2057         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2058         if (err)
2059                 goto out_err;
2060
2061         hdrs[cmd].pedits++;
2062
2063         return 0;
2064 out_err:
2065         return err;
2066 }
2067
2068 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2069                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2070                                  struct pedit_headers_action *hdrs,
2071                                  struct netlink_ext_ack *extack)
2072 {
2073         struct pedit_headers *cmd_masks;
2074         int err;
2075         u8 cmd;
2076
2077         if (!parse_attr->mod_hdr_actions) {
2078                 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2079                 if (err)
2080                         goto out_err;
2081         }
2082
2083         err = offload_pedit_fields(hdrs, parse_attr, extack);
2084         if (err < 0)
2085                 goto out_dealloc_parsed_actions;
2086
2087         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2088                 cmd_masks = &hdrs[cmd].masks;
2089                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2090                         NL_SET_ERR_MSG_MOD(extack,
2091                                            "attempt to offload an unsupported field");
2092                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2093                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2094                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2095                         err = -EOPNOTSUPP;
2096                         goto out_dealloc_parsed_actions;
2097                 }
2098         }
2099
2100         return 0;
2101
2102 out_dealloc_parsed_actions:
2103         kfree(parse_attr->mod_hdr_actions);
2104 out_err:
2105         return err;
2106 }
2107
2108 static bool csum_offload_supported(struct mlx5e_priv *priv,
2109                                    u32 action,
2110                                    u32 update_flags,
2111                                    struct netlink_ext_ack *extack)
2112 {
2113         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2114                          TCA_CSUM_UPDATE_FLAG_UDP;
2115
2116         /*  The HW recalcs checksums only if re-writing headers */
2117         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2118                 NL_SET_ERR_MSG_MOD(extack,
2119                                    "TC csum action is only offloaded with pedit");
2120                 netdev_warn(priv->netdev,
2121                             "TC csum action is only offloaded with pedit\n");
2122                 return false;
2123         }
2124
2125         if (update_flags & ~prot_flags) {
2126                 NL_SET_ERR_MSG_MOD(extack,
2127                                    "can't offload TC csum action for some header/s");
2128                 netdev_warn(priv->netdev,
2129                             "can't offload TC csum action for some header/s - flags %#x\n",
2130                             update_flags);
2131                 return false;
2132         }
2133
2134         return true;
2135 }
2136
2137 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2138                                           struct flow_action *flow_action,
2139                                           u32 actions,
2140                                           struct netlink_ext_ack *extack)
2141 {
2142         const struct flow_action_entry *act;
2143         bool modify_ip_header;
2144         u8 htype, ip_proto;
2145         void *headers_v;
2146         u16 ethertype;
2147         int i;
2148
2149         if (actions & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2150                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2151         else
2152                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2153
2154         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2155
2156         /* for non-IP we only re-write MACs, so we're okay */
2157         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2158                 goto out_ok;
2159
2160         modify_ip_header = false;
2161         flow_action_for_each(i, act, flow_action) {
2162                 if (act->id != FLOW_ACTION_MANGLE &&
2163                     act->id != FLOW_ACTION_ADD)
2164                         continue;
2165
2166                 htype = act->mangle.htype;
2167                 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4 ||
2168                     htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2169                         modify_ip_header = true;
2170                         break;
2171                 }
2172         }
2173
2174         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2175         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2176             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2177                 NL_SET_ERR_MSG_MOD(extack,
2178                                    "can't offload re-write of non TCP/UDP");
2179                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2180                 return false;
2181         }
2182
2183 out_ok:
2184         return true;
2185 }
2186
2187 static bool actions_match_supported(struct mlx5e_priv *priv,
2188                                     struct flow_action *flow_action,
2189                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2190                                     struct mlx5e_tc_flow *flow,
2191                                     struct netlink_ext_ack *extack)
2192 {
2193         u32 actions;
2194
2195         if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2196                 actions = flow->esw_attr->action;
2197         else
2198                 actions = flow->nic_attr->action;
2199
2200         if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2201             !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2202                 return false;
2203
2204         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2205                 return modify_header_match_supported(&parse_attr->spec,
2206                                                      flow_action, actions,
2207                                                      extack);
2208
2209         return true;
2210 }
2211
2212 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2213 {
2214         struct mlx5_core_dev *fmdev, *pmdev;
2215         u64 fsystem_guid, psystem_guid;
2216
2217         fmdev = priv->mdev;
2218         pmdev = peer_priv->mdev;
2219
2220         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2221         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2222
2223         return (fsystem_guid == psystem_guid);
2224 }
2225
2226 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2227                                 struct flow_action *flow_action,
2228                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2229                                 struct mlx5e_tc_flow *flow,
2230                                 struct netlink_ext_ack *extack)
2231 {
2232         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2233         struct pedit_headers_action hdrs[2] = {};
2234         const struct flow_action_entry *act;
2235         u32 action = 0;
2236         int err, i;
2237
2238         if (!flow_action_has_entries(flow_action))
2239                 return -EINVAL;
2240
2241         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2242
2243         flow_action_for_each(i, act, flow_action) {
2244                 switch (act->id) {
2245                 case FLOW_ACTION_DROP:
2246                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2247                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2248                                                flow_table_properties_nic_receive.flow_counter))
2249                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2250                         break;
2251                 case FLOW_ACTION_MANGLE:
2252                 case FLOW_ACTION_ADD:
2253                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2254                                                     parse_attr, hdrs, extack);
2255                         if (err)
2256                                 return err;
2257
2258                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2259                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2260                         break;
2261                 case FLOW_ACTION_CSUM:
2262                         if (csum_offload_supported(priv, action,
2263                                                    act->csum_flags,
2264                                                    extack))
2265                                 break;
2266
2267                         return -EOPNOTSUPP;
2268                 case FLOW_ACTION_REDIRECT: {
2269                         struct net_device *peer_dev = act->dev;
2270
2271                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2272                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2273                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2274                                 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
2275                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2276                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2277                         } else {
2278                                 NL_SET_ERR_MSG_MOD(extack,
2279                                                    "device is not on same HW, can't offload");
2280                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2281                                             peer_dev->name);
2282                                 return -EINVAL;
2283                         }
2284                         }
2285                         break;
2286                 case FLOW_ACTION_MARK: {
2287                         u32 mark = act->mark;
2288
2289                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2290                                 NL_SET_ERR_MSG_MOD(extack,
2291                                                    "Bad flow mark - only 16 bit is supported");
2292                                 return -EINVAL;
2293                         }
2294
2295                         attr->flow_tag = mark;
2296                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2297                         }
2298                         break;
2299                 default:
2300                         return -EINVAL;
2301                 }
2302         }
2303
2304         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2305             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2306                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2307                                             parse_attr, hdrs, extack);
2308                 if (err)
2309                         return err;
2310         }
2311
2312         attr->action = action;
2313         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2314                 return -EOPNOTSUPP;
2315
2316         return 0;
2317 }
2318
2319 static inline int cmp_encap_info(struct ip_tunnel_key *a,
2320                                  struct ip_tunnel_key *b)
2321 {
2322         return memcmp(a, b, sizeof(*a));
2323 }
2324
2325 static inline int hash_encap_info(struct ip_tunnel_key *key)
2326 {
2327         return jhash(key, sizeof(*key), 0);
2328 }
2329
2330
2331 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2332                                   struct net_device *peer_netdev)
2333 {
2334         struct mlx5e_priv *peer_priv;
2335
2336         peer_priv = netdev_priv(peer_netdev);
2337
2338         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2339                 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2340                 same_hw_devs(priv, peer_priv) &&
2341                 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2342                 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2343 }
2344
2345
2346
2347 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2348                               struct ip_tunnel_info *tun_info,
2349                               struct net_device *mirred_dev,
2350                               struct net_device **encap_dev,
2351                               struct mlx5e_tc_flow *flow,
2352                               struct netlink_ext_ack *extack,
2353                               int out_index)
2354 {
2355         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2356         unsigned short family = ip_tunnel_info_af(tun_info);
2357         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2358         struct ip_tunnel_key *key = &tun_info->key;
2359         struct mlx5e_encap_entry *e;
2360         uintptr_t hash_key;
2361         bool found = false;
2362         int err = 0;
2363
2364         hash_key = hash_encap_info(key);
2365
2366         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2367                                    encap_hlist, hash_key) {
2368                 if (!cmp_encap_info(&e->tun_info.key, key)) {
2369                         found = true;
2370                         break;
2371                 }
2372         }
2373
2374         /* must verify if encap is valid or not */
2375         if (found)
2376                 goto attach_flow;
2377
2378         e = kzalloc(sizeof(*e), GFP_KERNEL);
2379         if (!e)
2380                 return -ENOMEM;
2381
2382         e->tun_info = *tun_info;
2383         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2384         if (err)
2385                 goto out_err;
2386
2387         INIT_LIST_HEAD(&e->flows);
2388
2389         if (family == AF_INET)
2390                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
2391         else if (family == AF_INET6)
2392                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
2393
2394         if (err && err != -EAGAIN)
2395                 goto out_err;
2396
2397         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2398
2399 attach_flow:
2400         list_add(&flow->encaps[out_index].list, &e->flows);
2401         flow->encaps[out_index].index = out_index;
2402         *encap_dev = e->out_dev;
2403         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2404                 attr->dests[out_index].encap_id = e->encap_id;
2405                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
2406         } else {
2407                 err = -EAGAIN;
2408         }
2409
2410         return err;
2411
2412 out_err:
2413         kfree(e);
2414         return err;
2415 }
2416
2417 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2418                                 const struct flow_action_entry *act,
2419                                 struct mlx5_esw_flow_attr *attr,
2420                                 u32 *action)
2421 {
2422         u8 vlan_idx = attr->total_vlan;
2423
2424         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2425                 return -EOPNOTSUPP;
2426
2427         switch (act->id) {
2428         case FLOW_ACTION_VLAN_POP:
2429                 if (vlan_idx) {
2430                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2431                                                                  MLX5_FS_VLAN_DEPTH))
2432                                 return -EOPNOTSUPP;
2433
2434                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2435                 } else {
2436                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2437                 }
2438                 break;
2439         case FLOW_ACTION_VLAN_PUSH:
2440                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2441                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2442                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
2443                 if (!attr->vlan_proto[vlan_idx])
2444                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2445
2446                 if (vlan_idx) {
2447                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2448                                                                  MLX5_FS_VLAN_DEPTH))
2449                                 return -EOPNOTSUPP;
2450
2451                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2452                 } else {
2453                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2454                             (act->vlan.proto != htons(ETH_P_8021Q) ||
2455                              act->vlan.prio))
2456                                 return -EOPNOTSUPP;
2457
2458                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2459                 }
2460                 break;
2461         default:
2462                 /* action is FLOW_ACT_VLAN_MANGLE */
2463                 return -EOPNOTSUPP;
2464         }
2465
2466         attr->total_vlan = vlan_idx + 1;
2467
2468         return 0;
2469 }
2470
2471 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2472                                 struct flow_action *flow_action,
2473                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2474                                 struct mlx5e_tc_flow *flow,
2475                                 struct netlink_ext_ack *extack)
2476 {
2477         struct pedit_headers_action hdrs[2] = {};
2478         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2479         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2480         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2481         const struct ip_tunnel_info *info = NULL;
2482         const struct flow_action_entry *act;
2483         bool encap = false;
2484         u32 action = 0;
2485         int err, i;
2486
2487         if (!flow_action_has_entries(flow_action))
2488                 return -EINVAL;
2489
2490         attr->in_rep = rpriv->rep;
2491         attr->in_mdev = priv->mdev;
2492
2493         flow_action_for_each(i, act, flow_action) {
2494                 switch (act->id) {
2495                 case FLOW_ACTION_DROP:
2496                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2497                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
2498                         break;
2499                 case FLOW_ACTION_MANGLE:
2500                 case FLOW_ACTION_ADD:
2501                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
2502                                                     parse_attr, hdrs, extack);
2503                         if (err)
2504                                 return err;
2505
2506                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2507                         attr->split_count = attr->out_count;
2508                         break;
2509                 case FLOW_ACTION_CSUM:
2510                         if (csum_offload_supported(priv, action,
2511                                                    act->csum_flags, extack))
2512                                 break;
2513
2514                         return -EOPNOTSUPP;
2515                 case FLOW_ACTION_REDIRECT:
2516                 case FLOW_ACTION_MIRRED: {
2517                         struct mlx5e_priv *out_priv;
2518                         struct net_device *out_dev;
2519
2520                         out_dev = act->dev;
2521                         if (!out_dev) {
2522                                 /* out_dev is NULL when filters with
2523                                  * non-existing mirred device are replayed to
2524                                  * the driver.
2525                                  */
2526                                 return -EINVAL;
2527                         }
2528
2529                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
2530                                 NL_SET_ERR_MSG_MOD(extack,
2531                                                    "can't support more output ports, can't offload forwarding");
2532                                 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2533                                        attr->out_count);
2534                                 return -EOPNOTSUPP;
2535                         }
2536
2537                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2538                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
2539                         if (netdev_port_same_parent_id(priv->netdev,
2540                                                        out_dev) ||
2541                             is_merged_eswitch_dev(priv, out_dev)) {
2542                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2543                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2544                                 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2545
2546                                 if (uplink_upper &&
2547                                     netif_is_lag_master(uplink_upper) &&
2548                                     uplink_upper == out_dev)
2549                                         out_dev = uplink_dev;
2550
2551                                 if (!mlx5e_eswitch_rep(out_dev))
2552                                         return -EOPNOTSUPP;
2553
2554                                 out_priv = netdev_priv(out_dev);
2555                                 rpriv = out_priv->ppriv;
2556                                 attr->dests[attr->out_count].rep = rpriv->rep;
2557                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
2558                                 attr->out_count++;
2559                         } else if (encap) {
2560                                 parse_attr->mirred_ifindex[attr->out_count] =
2561                                         out_dev->ifindex;
2562                                 parse_attr->tun_info[attr->out_count] = *info;
2563                                 encap = false;
2564                                 attr->parse_attr = parse_attr;
2565                                 attr->dests[attr->out_count].flags |=
2566                                         MLX5_ESW_DEST_ENCAP;
2567                                 attr->out_count++;
2568                                 /* attr->dests[].rep is resolved when we
2569                                  * handle encap
2570                                  */
2571                         } else if (parse_attr->filter_dev != priv->netdev) {
2572                                 /* All mlx5 devices are called to configure
2573                                  * high level device filters. Therefore, the
2574                                  * *attempt* to  install a filter on invalid
2575                                  * eswitch should not trigger an explicit error
2576                                  */
2577                                 return -EINVAL;
2578                         } else {
2579                                 NL_SET_ERR_MSG_MOD(extack,
2580                                                    "devices are not on same switch HW, can't offload forwarding");
2581                                 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2582                                        priv->netdev->name, out_dev->name);
2583                                 return -EINVAL;
2584                         }
2585                         }
2586                         break;
2587                 case FLOW_ACTION_TUNNEL_ENCAP:
2588                         info = act->tunnel;
2589                         if (info)
2590                                 encap = true;
2591                         else
2592                                 return -EOPNOTSUPP;
2593
2594                         break;
2595                 case FLOW_ACTION_VLAN_PUSH:
2596                 case FLOW_ACTION_VLAN_POP:
2597                         err = parse_tc_vlan_action(priv, act, attr, &action);
2598                         if (err)
2599                                 return err;
2600
2601                         attr->split_count = attr->out_count;
2602                         break;
2603                 case FLOW_ACTION_TUNNEL_DECAP:
2604                         action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2605                         break;
2606                 case FLOW_ACTION_GOTO: {
2607                         u32 dest_chain = act->chain_index;
2608                         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2609
2610                         if (dest_chain <= attr->chain) {
2611                                 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2612                                 return -EOPNOTSUPP;
2613                         }
2614                         if (dest_chain > max_chain) {
2615                                 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2616                                 return -EOPNOTSUPP;
2617                         }
2618                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2619                         attr->dest_chain = dest_chain;
2620                         break;
2621                         }
2622                 default:
2623                         return -EINVAL;
2624                 }
2625         }
2626
2627         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2628             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2629                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2630                                             parse_attr, hdrs, extack);
2631                 if (err)
2632                         return err;
2633         }
2634
2635         attr->action = action;
2636         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2637                 return -EOPNOTSUPP;
2638
2639         if (attr->dest_chain) {
2640                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2641                         NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2642                         return -EOPNOTSUPP;
2643                 }
2644                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2645         }
2646
2647         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
2648                 NL_SET_ERR_MSG_MOD(extack,
2649                                    "current firmware doesn't support split rule for port mirroring");
2650                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2651                 return -EOPNOTSUPP;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static void get_flags(int flags, u16 *flow_flags)
2658 {
2659         u16 __flow_flags = 0;
2660
2661         if (flags & MLX5E_TC_INGRESS)
2662                 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2663         if (flags & MLX5E_TC_EGRESS)
2664                 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2665
2666         if (flags & MLX5E_TC_ESW_OFFLOAD)
2667                 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2668         if (flags & MLX5E_TC_NIC_OFFLOAD)
2669                 __flow_flags |= MLX5E_TC_FLOW_NIC;
2670
2671         *flow_flags = __flow_flags;
2672 }
2673
2674 static const struct rhashtable_params tc_ht_params = {
2675         .head_offset = offsetof(struct mlx5e_tc_flow, node),
2676         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2677         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2678         .automatic_shrinking = true,
2679 };
2680
2681 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
2682 {
2683         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2684         struct mlx5e_rep_priv *uplink_rpriv;
2685
2686         if (flags & MLX5E_TC_ESW_OFFLOAD) {
2687                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2688                 return &uplink_rpriv->uplink_priv.tc_ht;
2689         } else /* NIC offload */
2690                 return &priv->fs.tc.ht;
2691 }
2692
2693 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
2694 {
2695         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2696         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
2697                               flow->flags & MLX5E_TC_FLOW_INGRESS;
2698         bool act_is_encap = !!(attr->action &
2699                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
2700         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
2701                                                 MLX5_DEVCOM_ESW_OFFLOADS);
2702
2703         return esw_paired && mlx5_lag_is_sriov(attr->in_mdev) &&
2704                (is_rep_ingress || act_is_encap);
2705 }
2706
2707 static int
2708 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
2709                  struct tc_cls_flower_offload *f, u16 flow_flags,
2710                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
2711                  struct mlx5e_tc_flow **__flow)
2712 {
2713         struct mlx5e_tc_flow_parse_attr *parse_attr;
2714         struct mlx5e_tc_flow *flow;
2715         int err;
2716
2717         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
2718         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
2719         if (!parse_attr || !flow) {
2720                 err = -ENOMEM;
2721                 goto err_free;
2722         }
2723
2724         flow->cookie = f->cookie;
2725         flow->flags = flow_flags;
2726         flow->priv = priv;
2727
2728         *__flow = flow;
2729         *__parse_attr = parse_attr;
2730
2731         return 0;
2732
2733 err_free:
2734         kfree(flow);
2735         kvfree(parse_attr);
2736         return err;
2737 }
2738
2739 static struct mlx5e_tc_flow *
2740 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2741                      struct tc_cls_flower_offload *f,
2742                      u16 flow_flags,
2743                      struct net_device *filter_dev,
2744                      struct mlx5_eswitch_rep *in_rep,
2745                      struct mlx5_core_dev *in_mdev)
2746 {
2747         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
2748         struct netlink_ext_ack *extack = f->common.extack;
2749         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2750         struct mlx5e_tc_flow_parse_attr *parse_attr;
2751         struct mlx5e_tc_flow *flow;
2752         int attr_size, err;
2753
2754         flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2755         attr_size  = sizeof(struct mlx5_esw_flow_attr);
2756         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2757                                &parse_attr, &flow);
2758         if (err)
2759                 goto out;
2760         parse_attr->filter_dev = filter_dev;
2761         flow->esw_attr->parse_attr = parse_attr;
2762         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2763                                f, filter_dev);
2764         if (err)
2765                 goto err_free;
2766
2767         flow->esw_attr->chain = f->common.chain_index;
2768         flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
2769         err = parse_tc_fdb_actions(priv, &rule->action, parse_attr, flow, extack);
2770         if (err)
2771                 goto err_free;
2772
2773         flow->esw_attr->in_rep = in_rep;
2774         flow->esw_attr->in_mdev = in_mdev;
2775
2776         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
2777             MLX5_COUNTER_SOURCE_ESWITCH)
2778                 flow->esw_attr->counter_dev = in_mdev;
2779         else
2780                 flow->esw_attr->counter_dev = priv->mdev;
2781
2782         err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
2783         if (err)
2784                 goto err_free;
2785
2786         return flow;
2787
2788 err_free:
2789         kfree(flow);
2790         kvfree(parse_attr);
2791 out:
2792         return ERR_PTR(err);
2793 }
2794
2795 static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
2796                                       struct mlx5e_tc_flow *flow)
2797 {
2798         struct mlx5e_priv *priv = flow->priv, *peer_priv;
2799         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
2800         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
2801         struct mlx5e_tc_flow_parse_attr *parse_attr;
2802         struct mlx5e_rep_priv *peer_urpriv;
2803         struct mlx5e_tc_flow *peer_flow;
2804         struct mlx5_core_dev *in_mdev;
2805         int err = 0;
2806
2807         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2808         if (!peer_esw)
2809                 return -ENODEV;
2810
2811         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
2812         peer_priv = netdev_priv(peer_urpriv->netdev);
2813
2814         /* in_mdev is assigned of which the packet originated from.
2815          * So packets redirected to uplink use the same mdev of the
2816          * original flow and packets redirected from uplink use the
2817          * peer mdev.
2818          */
2819         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
2820                 in_mdev = peer_priv->mdev;
2821         else
2822                 in_mdev = priv->mdev;
2823
2824         parse_attr = flow->esw_attr->parse_attr;
2825         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow->flags,
2826                                          parse_attr->filter_dev,
2827                                          flow->esw_attr->in_rep, in_mdev);
2828         if (IS_ERR(peer_flow)) {
2829                 err = PTR_ERR(peer_flow);
2830                 goto out;
2831         }
2832
2833         flow->peer_flow = peer_flow;
2834         flow->flags |= MLX5E_TC_FLOW_DUP;
2835         mutex_lock(&esw->offloads.peer_mutex);
2836         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
2837         mutex_unlock(&esw->offloads.peer_mutex);
2838
2839 out:
2840         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2841         return err;
2842 }
2843
2844 static int
2845 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2846                    struct tc_cls_flower_offload *f,
2847                    u16 flow_flags,
2848                    struct net_device *filter_dev,
2849                    struct mlx5e_tc_flow **__flow)
2850 {
2851         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2852         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
2853         struct mlx5_core_dev *in_mdev = priv->mdev;
2854         struct mlx5e_tc_flow *flow;
2855         int err;
2856
2857         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
2858                                     in_mdev);
2859         if (IS_ERR(flow))
2860                 return PTR_ERR(flow);
2861
2862         if (is_peer_flow_needed(flow)) {
2863                 err = mlx5e_tc_add_fdb_peer_flow(f, flow);
2864                 if (err) {
2865                         mlx5e_tc_del_fdb_flow(priv, flow);
2866                         goto out;
2867                 }
2868         }
2869
2870         *__flow = flow;
2871
2872         return 0;
2873
2874 out:
2875         return err;
2876 }
2877
2878 static int
2879 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2880                    struct tc_cls_flower_offload *f,
2881                    u16 flow_flags,
2882                    struct net_device *filter_dev,
2883                    struct mlx5e_tc_flow **__flow)
2884 {
2885         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
2886         struct netlink_ext_ack *extack = f->common.extack;
2887         struct mlx5e_tc_flow_parse_attr *parse_attr;
2888         struct mlx5e_tc_flow *flow;
2889         int attr_size, err;
2890
2891         /* multi-chain not supported for NIC rules */
2892         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
2893                 return -EOPNOTSUPP;
2894
2895         flow_flags |= MLX5E_TC_FLOW_NIC;
2896         attr_size  = sizeof(struct mlx5_nic_flow_attr);
2897         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2898                                &parse_attr, &flow);
2899         if (err)
2900                 goto out;
2901
2902         parse_attr->filter_dev = filter_dev;
2903         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2904                                f, filter_dev);
2905         if (err)
2906                 goto err_free;
2907
2908         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
2909         if (err)
2910                 goto err_free;
2911
2912         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
2913         if (err)
2914                 goto err_free;
2915
2916         flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2917         kvfree(parse_attr);
2918         *__flow = flow;
2919
2920         return 0;
2921
2922 err_free:
2923         kfree(flow);
2924         kvfree(parse_attr);
2925 out:
2926         return err;
2927 }
2928
2929 static int
2930 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
2931                   struct tc_cls_flower_offload *f,
2932                   int flags,
2933                   struct net_device *filter_dev,
2934                   struct mlx5e_tc_flow **flow)
2935 {
2936         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2937         u16 flow_flags;
2938         int err;
2939
2940         get_flags(flags, &flow_flags);
2941
2942         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
2943                 return -EOPNOTSUPP;
2944
2945         if (esw && esw->mode == SRIOV_OFFLOADS)
2946                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
2947                                          filter_dev, flow);
2948         else
2949                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
2950                                          filter_dev, flow);
2951
2952         return err;
2953 }
2954
2955 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
2956                            struct tc_cls_flower_offload *f, int flags)
2957 {
2958         struct netlink_ext_ack *extack = f->common.extack;
2959         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
2960         struct mlx5e_tc_flow *flow;
2961         int err = 0;
2962
2963         flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2964         if (flow) {
2965                 NL_SET_ERR_MSG_MOD(extack,
2966                                    "flow cookie already exists, ignoring");
2967                 netdev_warn_once(priv->netdev,
2968                                  "flow cookie %lx already exists, ignoring\n",
2969                                  f->cookie);
2970                 goto out;
2971         }
2972
2973         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
2974         if (err)
2975                 goto out;
2976
2977         err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2978         if (err)
2979                 goto err_free;
2980
2981         return 0;
2982
2983 err_free:
2984         mlx5e_tc_del_flow(priv, flow);
2985         kfree(flow);
2986 out:
2987         return err;
2988 }
2989
2990 #define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2991 #define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2992
2993 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2994 {
2995         if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2996                 return true;
2997
2998         return false;
2999 }
3000
3001 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
3002                         struct tc_cls_flower_offload *f, int flags)
3003 {
3004         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3005         struct mlx5e_tc_flow *flow;
3006
3007         flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3008         if (!flow || !same_flow_direction(flow, flags))
3009                 return -EINVAL;
3010
3011         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
3012
3013         mlx5e_tc_del_flow(priv, flow);
3014
3015         kfree(flow);
3016
3017         return 0;
3018 }
3019
3020 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
3021                        struct tc_cls_flower_offload *f, int flags)
3022 {
3023         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3024         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3025         struct mlx5_eswitch *peer_esw;
3026         struct mlx5e_tc_flow *flow;
3027         struct mlx5_fc *counter;
3028         u64 bytes;
3029         u64 packets;
3030         u64 lastuse;
3031
3032         flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3033         if (!flow || !same_flow_direction(flow, flags))
3034                 return -EINVAL;
3035
3036         if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3037                 return 0;
3038
3039         counter = mlx5e_tc_get_counter(flow);
3040         if (!counter)
3041                 return 0;
3042
3043         mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3044
3045         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3046         if (!peer_esw)
3047                 goto out;
3048
3049         if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3050             (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3051                 u64 bytes2;
3052                 u64 packets2;
3053                 u64 lastuse2;
3054
3055                 counter = mlx5e_tc_get_counter(flow->peer_flow);
3056                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3057
3058                 bytes += bytes2;
3059                 packets += packets2;
3060                 lastuse = max_t(u64, lastuse, lastuse2);
3061         }
3062
3063         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3064
3065 out:
3066         flow_stats_update(&f->stats, bytes, packets, lastuse);
3067
3068         return 0;
3069 }
3070
3071 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3072                                               struct mlx5e_priv *peer_priv)
3073 {
3074         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3075         struct mlx5e_hairpin_entry *hpe;
3076         u16 peer_vhca_id;
3077         int bkt;
3078
3079         if (!same_hw_devs(priv, peer_priv))
3080                 return;
3081
3082         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3083
3084         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3085                 if (hpe->peer_vhca_id == peer_vhca_id)
3086                         hpe->hp->pair->peer_gone = true;
3087         }
3088 }
3089
3090 static int mlx5e_tc_netdev_event(struct notifier_block *this,
3091                                  unsigned long event, void *ptr)
3092 {
3093         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3094         struct mlx5e_flow_steering *fs;
3095         struct mlx5e_priv *peer_priv;
3096         struct mlx5e_tc_table *tc;
3097         struct mlx5e_priv *priv;
3098
3099         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3100             event != NETDEV_UNREGISTER ||
3101             ndev->reg_state == NETREG_REGISTERED)
3102                 return NOTIFY_DONE;
3103
3104         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3105         fs = container_of(tc, struct mlx5e_flow_steering, tc);
3106         priv = container_of(fs, struct mlx5e_priv, fs);
3107         peer_priv = netdev_priv(ndev);
3108         if (priv == peer_priv ||
3109             !(priv->netdev->features & NETIF_F_HW_TC))
3110                 return NOTIFY_DONE;
3111
3112         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3113
3114         return NOTIFY_DONE;
3115 }
3116
3117 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
3118 {
3119         struct mlx5e_tc_table *tc = &priv->fs.tc;
3120         int err;
3121
3122         hash_init(tc->mod_hdr_tbl);
3123         hash_init(tc->hairpin_tbl);
3124
3125         err = rhashtable_init(&tc->ht, &tc_ht_params);
3126         if (err)
3127                 return err;
3128
3129         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3130         if (register_netdevice_notifier(&tc->netdevice_nb)) {
3131                 tc->netdevice_nb.notifier_call = NULL;
3132                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3133         }
3134
3135         return err;
3136 }
3137
3138 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3139 {
3140         struct mlx5e_tc_flow *flow = ptr;
3141         struct mlx5e_priv *priv = flow->priv;
3142
3143         mlx5e_tc_del_flow(priv, flow);
3144         kfree(flow);
3145 }
3146
3147 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
3148 {
3149         struct mlx5e_tc_table *tc = &priv->fs.tc;
3150
3151         if (tc->netdevice_nb.notifier_call)
3152                 unregister_netdevice_notifier(&tc->netdevice_nb);
3153
3154         rhashtable_destroy(&tc->ht);
3155
3156         if (!IS_ERR_OR_NULL(tc->t)) {
3157                 mlx5_destroy_flow_table(tc->t);
3158                 tc->t = NULL;
3159         }
3160 }
3161
3162 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3163 {
3164         return rhashtable_init(tc_ht, &tc_ht_params);
3165 }
3166
3167 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3168 {
3169         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3170 }
3171
3172 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
3173 {
3174         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3175
3176         return atomic_read(&tc_ht->nelems);
3177 }
3178
3179 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3180 {
3181         struct mlx5e_tc_flow *flow, *tmp;
3182
3183         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3184                 __mlx5e_tc_del_fdb_peer_flow(flow);
3185 }