drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 222 {
 223         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 224
 225         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 226                                                   sizeof(*rq->mpwqe.info)),
 227                                        GFP_KERNEL, node);
 228         if (!rq->mpwqe.info)
 229                 return -ENOMEM;
 230
 231         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 232
 233         return 0;
 234 }
 235
 236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 237                                  u64 npages, u8 page_shift,
 238                                  struct mlx5_core_mkey *umr_mkey,
 239                                  dma_addr_t filler_addr)
 240 {
 241         struct mlx5_mtt *mtt;
 242         int inlen;
 243         void *mkc;
 244         u32 *in;
 245         int err;
 246         int i;
 247
 248         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 249
 250         in = kvzalloc(inlen, GFP_KERNEL);
 251         if (!in)
 252                 return -ENOMEM;
 253
 254         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 255
 256         MLX5_SET(mkc, mkc, free, 1);
 257         MLX5_SET(mkc, mkc, umr_en, 1);
 258         MLX5_SET(mkc, mkc, lw, 1);
 259         MLX5_SET(mkc, mkc, lr, 1);
 260         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 261         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 262         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 263         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 264         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 265         MLX5_SET(mkc, mkc, translations_octword_size,
 266                  MLX5_MTT_OCTW(npages));
 267         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 268         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 269                  MLX5_MTT_OCTW(npages));
 270
 271         /* Initialize the mkey with all MTTs pointing to a default
 272          * page (filler_addr). When the channels are activated, UMR
 273          * WQEs will redirect the RX WQEs to the actual memory from
 274          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 275          * to the default page.
 276          */
 277         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 278         for (i = 0 ; i < npages ; i++)
 279                 mtt[i].ptag = cpu_to_be64(filler_addr);
 280
 281         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 282
 283         kvfree(in);
 284         return err;
 285 }
 286
 287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 288 {
 289         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 290
 291         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 292                                      rq->wqe_overflow.addr);
 293 }
 294
 295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 296 {
 297         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 298 }
 299
 300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_wqe_frag_info next_frag = {};
 303         struct mlx5e_wqe_frag_info *prev = NULL;
 304         int i;
 305
 306         next_frag.di = &rq->wqe.di[0];
 307
 308         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 309                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 310                 struct mlx5e_wqe_frag_info *frag =
 311                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 312                 int f;
 313
 314                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 315                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 316                                 next_frag.di++;
 317                                 next_frag.offset = 0;
 318                                 if (prev)
 319                                         prev->last_in_page = true;
 320                         }
 321                         *frag = next_frag;
 322
 323                         /* prepare next */
 324                         next_frag.offset += frag_info[f].frag_stride;
 325                         prev = frag;
 326                 }
 327         }
 328
 329         if (prev)
 330                 prev->last_in_page = true;
 331 }
 332
 333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 334 {
 335         int len = wq_sz << rq->wqe.info.log_num_frags;
 336
 337         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 338         if (!rq->wqe.di)
 339                 return -ENOMEM;
 340
 341         mlx5e_init_frags_partition(rq);
 342
 343         return 0;
 344 }
 345
 346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 347 {
 348         kvfree(rq->wqe.di);
 349 }
 350
 351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 352 {
 353         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 354
 355         mlx5e_reporter_rq_cqe_err(rq);
 356 }
 357
 358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 359 {
 360         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 361         if (!rq->wqe_overflow.page)
 362                 return -ENOMEM;
 363
 364         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 365                                              PAGE_SIZE, rq->buff.map_dir);
 366         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 367                 __free_page(rq->wqe_overflow.page);
 368                 return -ENOMEM;
 369         }
 370         return 0;
 371 }
 372
 373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 374 {
 375          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 376                         rq->buff.map_dir);
 377          __free_page(rq->wqe_overflow.page);
 378 }
 379
 380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 381                              struct mlx5e_rq *rq)
 382 {
 383         struct mlx5_core_dev *mdev = c->mdev;
 384         int err;
 385
 386         rq->wq_type      = params->rq_wq_type;
 387         rq->pdev         = c->pdev;
 388         rq->netdev       = c->netdev;
 389         rq->priv         = c->priv;
 390         rq->tstamp       = c->tstamp;
 391         rq->clock        = &mdev->clock;
 392         rq->icosq        = &c->icosq;
 393         rq->ix           = c->ix;
 394         rq->mdev         = mdev;
 395         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 396         rq->xdpsq        = &c->rq_xdpsq;
 397         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 398         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 399         err = mlx5e_rq_set_handlers(rq, params, NULL);
 400         if (err)
 401                 return err;
 402
 403         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 404 }
 405
 406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 407                           struct mlx5e_xsk_param *xsk,
 408                           struct mlx5e_rq_param *rqp,
 409                           int node, struct mlx5e_rq *rq)
 410 {
 411         struct page_pool_params pp_params = { 0 };
 412         struct mlx5_core_dev *mdev = rq->mdev;
 413         void *rqc = rqp->rqc;
 414         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 415         u32 pool_size;
 416         int wq_sz;
 417         int err;
 418         int i;
 419
 420         rqp->wq.db_numa_node = node;
 421         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 422
 423         if (params->xdp_prog)
 424                 bpf_prog_inc(params->xdp_prog);
 425         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 426
 427         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 428         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 429         pool_size = 1 << params->log_rq_mtu_frames;
 430
 431         switch (rq->wq_type) {
 432         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 433                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 434                                         &rq->wq_ctrl);
 435                 if (err)
 436                         goto err_rq_xdp_prog;
 437
 438                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 439                 if (err)
 440                         goto err_rq_wq_destroy;
 441
 442                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 443
 444                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 445
 446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 447                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 448
 449                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 450                 rq->mpwqe.num_strides =
 451                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 452
 453                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 454
 455                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 456                 if (err)
 457                         goto err_rq_drop_page;
 458                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 459
 460                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 461                 if (err)
 462                         goto err_rq_mkey;
 463                 break;
 464         default: /* MLX5_WQ_TYPE_CYCLIC */
 465                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 466                                          &rq->wq_ctrl);
 467                 if (err)
 468                         goto err_rq_xdp_prog;
 469
 470                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 471
 472                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 473
 474                 rq->wqe.info = rqp->frags_info;
 475                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 476
 477                 rq->wqe.frags =
 478                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 479                                         (wq_sz << rq->wqe.info.log_num_frags)),
 480                                       GFP_KERNEL, node);
 481                 if (!rq->wqe.frags) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485
 486                 err = mlx5e_init_di_list(rq, wq_sz, node);
 487                 if (err)
 488                         goto err_rq_frags;
 489
 490                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 491         }
 492
 493         if (xsk) {
 494                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 495                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 496                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 497         } else {
 498                 /* Create a page_pool and register it with rxq */
 499                 pp_params.order     = 0;
 500                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 501                 pp_params.pool_size = pool_size;
 502                 pp_params.nid       = node;
 503                 pp_params.dev       = rq->pdev;
 504                 pp_params.dma_dir   = rq->buff.map_dir;
 505
 506                 /* page_pool can be used even when there is no rq->xdp_prog,
 507                  * given page_pool does not handle DMA mapping there is no
 508                  * required state to clear. And page_pool gracefully handle
 509                  * elevated refcnt.
 510                  */
 511                 rq->page_pool = page_pool_create(&pp_params);
 512                 if (IS_ERR(rq->page_pool)) {
 513                         err = PTR_ERR(rq->page_pool);
 514                         rq->page_pool = NULL;
 515                         goto err_free_by_rq_type;
 516                 }
 517                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 518                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 519                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 520         }
 521         if (err)
 522                 goto err_free_by_rq_type;
 523
 524         for (i = 0; i < wq_sz; i++) {
 525                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 526                         struct mlx5e_rx_wqe_ll *wqe =
 527                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 528                         u32 byte_count =
 529                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 530                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 531
 532                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 533                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 534                         wqe->data[0].lkey = rq->mkey_be;
 535                 } else {
 536                         struct mlx5e_rx_wqe_cyc *wqe =
 537                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 538                         int f;
 539
 540                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 541                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 542                                         MLX5_HW_START_PADDING;
 543
 544                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 545                                 wqe->data[f].lkey = rq->mkey_be;
 546                         }
 547                         /* check if num_frags is not a pow of two */
 548                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 549                                 wqe->data[f].byte_count = 0;
 550                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 551                                 wqe->data[f].addr = 0;
 552                         }
 553                 }
 554         }
 555
 556         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 557
 558         switch (params->rx_cq_moderation.cq_period_mode) {
 559         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 561                 break;
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 563         default:
 564                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 565         }
 566
 567         rq->page_cache.head = 0;
 568         rq->page_cache.tail = 0;
 569
 570         return 0;
 571
 572 err_free_by_rq_type:
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kvfree(rq->mpwqe.info);
 576 err_rq_mkey:
 577                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 578 err_rq_drop_page:
 579                 mlx5e_free_mpwqe_rq_drop_page(rq);
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 mlx5e_free_di_list(rq);
 583 err_rq_frags:
 584                 kvfree(rq->wqe.frags);
 585         }
 586 err_rq_wq_destroy:
 587         mlx5_wq_destroy(&rq->wq_ctrl);
 588 err_rq_xdp_prog:
 589         if (params->xdp_prog)
 590                 bpf_prog_put(params->xdp_prog);
 591
 592         return err;
 593 }
 594
 595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 596 {
 597         struct bpf_prog *old_prog;
 598         int i;
 599
 600         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 601                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 602                                                      lockdep_is_held(&rq->priv->state_lock));
 603                 if (old_prog)
 604                         bpf_prog_put(old_prog);
 605         }
 606
 607         switch (rq->wq_type) {
 608         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 609                 kvfree(rq->mpwqe.info);
 610                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 611                 mlx5e_free_mpwqe_rq_drop_page(rq);
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 kvfree(rq->wqe.frags);
 615                 mlx5e_free_di_list(rq);
 616         }
 617
 618         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 619              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 620                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 621
 622                 /* With AF_XDP, page_cache is not used, so this loop is not
 623                  * entered, and it's safe to call mlx5e_page_release_dynamic
 624                  * directly.
 625                  */
 626                 mlx5e_page_release_dynamic(rq, dma_info, false);
 627         }
 628
 629         xdp_rxq_info_unreg(&rq->xdp_rxq);
 630         page_pool_destroy(rq->page_pool);
 631         mlx5_wq_destroy(&rq->wq_ctrl);
 632 }
 633
 634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 635 {
 636         struct mlx5_core_dev *mdev = rq->mdev;
 637         u8 ts_format;
 638         void *in;
 639         void *rqc;
 640         void *wq;
 641         int inlen;
 642         int err;
 643
 644         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 645                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 646         in = kvzalloc(inlen, GFP_KERNEL);
 647         if (!in)
 648                 return -ENOMEM;
 649
 650         ts_format = mlx5_is_real_time_rq(mdev) ?
 651                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 652                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 653         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 654         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 655
 656         memcpy(rqc, param->rqc, sizeof(param->rqc));
 657
 658         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 659         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 660         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 661         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 662                                                 MLX5_ADAPTER_PAGE_SHIFT);
 663         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 664
 665         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 666                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 667
 668         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 669
 670         kvfree(in);
 671
 672         return err;
 673 }
 674
 675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         int inlen;
 682         int err;
 683
 684         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 690                 mlx5e_rqwq_reset(rq);
 691
 692         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 693
 694         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 695         MLX5_SET(rqc, rqc, state, next_state);
 696
 697         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 705 {
 706         struct mlx5_core_dev *mdev = rq->mdev;
 707
 708         void *in;
 709         void *rqc;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 714         in = kvzalloc(inlen, GFP_KERNEL);
 715         if (!in)
 716                 return -ENOMEM;
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 721         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 722                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 723         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 724         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 725
 726         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 734 {
 735         struct mlx5_core_dev *mdev = rq->mdev;
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 751         MLX5_SET(rqc, rqc, vsd, vsd);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 762 {
 763         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 764 }
 765
 766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 767 {
 768         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 769
 770         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 771
 772         do {
 773                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 774                         return 0;
 775
 776                 msleep(20);
 777         } while (time_before(jiffies, exp_time));
 778
 779         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 780                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 781
 782         mlx5e_reporter_rx_timeout(rq);
 783         return -ETIMEDOUT;
 784 }
 785
 786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 787 {
 788         struct mlx5_wq_ll *wq;
 789         u16 head;
 790         int i;
 791
 792         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 793                 return;
 794
 795         wq = &rq->mpwqe.wq;
 796         head = wq->head;
 797
 798         /* Outstanding UMR WQEs (in progress) start at wq->head */
 799         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 800                 rq->dealloc_wqe(rq, head);
 801                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 802         }
 803
 804         rq->mpwqe.actual_wq_head = wq->head;
 805         rq->mpwqe.umr_in_progress = 0;
 806         rq->mpwqe.umr_completed = 0;
 807 }
 808
 809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 810 {
 811         __be16 wqe_ix_be;
 812         u16 wqe_ix;
 813
 814         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 815                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 816
 817                 mlx5e_free_rx_in_progress_descs(rq);
 818
 819                 while (!mlx5_wq_ll_is_empty(wq)) {
 820                         struct mlx5e_rx_wqe_ll *wqe;
 821
 822                         wqe_ix_be = *wq->tail_next;
 823                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 824                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 825                         rq->dealloc_wqe(rq, wqe_ix);
 826                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 827                                        &wqe->next.next_wqe_index);
 828                 }
 829         } else {
 830                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 831
 832                 while (!mlx5_wq_cyc_is_empty(wq)) {
 833                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 834                         rq->dealloc_wqe(rq, wqe_ix);
 835                         mlx5_wq_cyc_pop(wq);
 836                 }
 837         }
 838
 839 }
 840
 841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 842                   struct mlx5e_xsk_param *xsk, int node,
 843                   struct mlx5e_rq *rq)
 844 {
 845         struct mlx5_core_dev *mdev = rq->mdev;
 846         int err;
 847
 848         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_create_rq(rq, param);
 853         if (err)
 854                 goto err_free_rq;
 855
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
 861                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 862
 863         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 864                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 865
 866         if (params->rx_dim_enabled)
 867                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 868
 869         /* We disable csum_complete when XDP is enabled since
 870          * XDP programs might manipulate packets which will render
 871          * skb->checksum incorrect.
 872          */
 873         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 874                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 875
 876         /* For CQE compression on striding RQ, use stride index provided by
 877          * HW if capability is supported.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 880             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 881                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 882
 883         return 0;
 884
 885 err_destroy_rq:
 886         mlx5e_destroy_rq(rq);
 887 err_free_rq:
 888         mlx5e_free_rq(rq);
 889
 890         return err;
 891 }
 892
 893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 894 {
 895         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 896         if (rq->icosq) {
 897                 mlx5e_trigger_irq(rq->icosq);
 898         } else {
 899                 local_bh_disable();
 900                 napi_schedule(rq->cq.napi);
 901                 local_bh_enable();
 902         }
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         if (rq->icosq)
 915                 cancel_work_sync(&rq->icosq->recover_work);
 916         cancel_work_sync(&rq->recover_work);
 917         mlx5e_destroy_rq(rq);
 918         mlx5e_free_rx_descs(rq);
 919         mlx5e_free_rq(rq);
 920 }
 921
 922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 923 {
 924         kvfree(sq->db.xdpi_fifo.xi);
 925         kvfree(sq->db.wqe_info);
 926 }
 927
 928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 929 {
 930         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 931         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 932         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 933
 934         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 935                                       GFP_KERNEL, numa);
 936         if (!xdpi_fifo->xi)
 937                 return -ENOMEM;
 938
 939         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 940         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 941         xdpi_fifo->mask = dsegs_per_wq - 1;
 942
 943         return 0;
 944 }
 945
 946 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 947 {
 948         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 949         int err;
 950
 951         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 952                                         GFP_KERNEL, numa);
 953         if (!sq->db.wqe_info)
 954                 return -ENOMEM;
 955
 956         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 957         if (err) {
 958                 mlx5e_free_xdpsq_db(sq);
 959                 return err;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 966                              struct mlx5e_params *params,
 967                              struct xsk_buff_pool *xsk_pool,
 968                              struct mlx5e_sq_param *param,
 969                              struct mlx5e_xdpsq *sq,
 970                              bool is_redirect)
 971 {
 972         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 973         struct mlx5_core_dev *mdev = c->mdev;
 974         struct mlx5_wq_cyc *wq = &sq->wq;
 975         int err;
 976
 977         sq->pdev      = c->pdev;
 978         sq->mkey_be   = c->mkey_be;
 979         sq->channel   = c;
 980         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 981         sq->min_inline_mode = params->tx_min_inline_mode;
 982         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 983         sq->xsk_pool  = xsk_pool;
 984
 985         sq->stats = sq->xsk_pool ?
 986                 &c->priv->channel_stats[c->ix].xsksq :
 987                 is_redirect ?
 988                         &c->priv->channel_stats[c->ix].xdpsq :
 989                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 990
 991         param->wq.db_numa_node = cpu_to_node(c->cpu);
 992         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 993         if (err)
 994                 return err;
 995         wq->db = &wq->db[MLX5_SND_DBR];
 996
 997         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 998         if (err)
 999                 goto err_sq_wq_destroy;
1000
1001         return 0;
1002
1003 err_sq_wq_destroy:
1004         mlx5_wq_destroy(&sq->wq_ctrl);
1005
1006         return err;
1007 }
1008
1009 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1010 {
1011         mlx5e_free_xdpsq_db(sq);
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013 }
1014
1015 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1016 {
1017         kvfree(sq->db.wqe_info);
1018 }
1019
1020 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1021 {
1022         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1023         size_t size;
1024
1025         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1026         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1027         if (!sq->db.wqe_info)
1028                 return -ENOMEM;
1029
1030         return 0;
1031 }
1032
1033 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1034 {
1035         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1036                                               recover_work);
1037
1038         mlx5e_reporter_icosq_cqe_err(sq);
1039 }
1040
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042                              struct mlx5e_sq_param *param,
1043                              struct mlx5e_icosq *sq)
1044 {
1045         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046         struct mlx5_core_dev *mdev = c->mdev;
1047         struct mlx5_wq_cyc *wq = &sq->wq;
1048         int err;
1049
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1052         sq->reserved_room = param->stop_room;
1053
1054         param->wq.db_numa_node = cpu_to_node(c->cpu);
1055         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1056         if (err)
1057                 return err;
1058         wq->db = &wq->db[MLX5_SND_DBR];
1059
1060         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1061         if (err)
1062                 goto err_sq_wq_destroy;
1063
1064         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065
1066         return 0;
1067
1068 err_sq_wq_destroy:
1069         mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071         return err;
1072 }
1073
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1075 {
1076         mlx5e_free_icosq_db(sq);
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078 }
1079
1080 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1081 {
1082         kvfree(sq->db.wqe_info);
1083         kvfree(sq->db.skb_fifo.fifo);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1096                                                         sizeof(*sq->db.skb_fifo.fifo)),
1097                                         GFP_KERNEL, numa);
1098         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1099                                                    sizeof(*sq->db.wqe_info)),
1100                                         GFP_KERNEL, numa);
1101         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1102                 mlx5e_free_txqsq_db(sq);
1103                 return -ENOMEM;
1104         }
1105
1106         sq->dma_fifo_mask = df_sz - 1;
1107
1108         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1109         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1110         sq->db.skb_fifo.mask = df_sz - 1;
1111
1112         return 0;
1113 }
1114
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq,
1120                              int tc)
1121 {
1122         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123         struct mlx5_core_dev *mdev = c->mdev;
1124         struct mlx5_wq_cyc *wq = &sq->wq;
1125         int err;
1126
1127         sq->pdev      = c->pdev;
1128         sq->tstamp    = c->tstamp;
1129         sq->clock     = &mdev->clock;
1130         sq->mkey_be   = c->mkey_be;
1131         sq->netdev    = c->netdev;
1132         sq->mdev      = c->mdev;
1133         sq->priv      = c->priv;
1134         sq->ch_ix     = c->ix;
1135         sq->txq_ix    = txq_ix;
1136         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1137         sq->min_inline_mode = params->tx_min_inline_mode;
1138         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1139         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1140         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1141                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1142         if (MLX5_IPSEC_DEV(c->priv->mdev))
1143                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1144         if (param->is_mpw)
1145                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1146         sq->stop_room = param->stop_room;
1147         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1148
1149         param->wq.db_numa_node = cpu_to_node(c->cpu);
1150         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1151         if (err)
1152                 return err;
1153         wq->db    = &wq->db[MLX5_SND_DBR];
1154
1155         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1156         if (err)
1157                 goto err_sq_wq_destroy;
1158
1159         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1160         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1161
1162         return 0;
1163
1164 err_sq_wq_destroy:
1165         mlx5_wq_destroy(&sq->wq_ctrl);
1166
1167         return err;
1168 }
1169
1170 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1171 {
1172         mlx5e_free_txqsq_db(sq);
1173         mlx5_wq_destroy(&sq->wq_ctrl);
1174 }
1175
1176 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1177                            struct mlx5e_sq_param *param,
1178                            struct mlx5e_create_sq_param *csp,
1179                            u32 *sqn)
1180 {
1181         u8 ts_format;
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         ts_format = mlx5_is_real_time_sq(mdev) ?
1195                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1196                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1197         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1198         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1199
1200         memcpy(sqc, param->sqc, sizeof(param->sqc));
1201         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1202         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1203         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1204         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1205         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1206
1207
1208         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1210
1211         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1212         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1213
1214         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1215         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1216         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1217                                           MLX5_ADAPTER_PAGE_SHIFT);
1218         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1219
1220         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1222
1223         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224
1225         kvfree(in);
1226
1227         return err;
1228 }
1229
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231                     struct mlx5e_modify_sq_param *p)
1232 {
1233         u64 bitmask = 0;
1234         void *in;
1235         void *sqc;
1236         int inlen;
1237         int err;
1238
1239         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1245
1246         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247         MLX5_SET(sqc, sqc, state, p->next_state);
1248         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 bitmask |= 1;
1250                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1251         }
1252         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253                 bitmask |= 1 << 2;
1254                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1255         }
1256         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1257
1258         err = mlx5_core_modify_sq(mdev, sqn, in);
1259
1260         kvfree(in);
1261
1262         return err;
1263 }
1264
1265 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1266 {
1267         mlx5_core_destroy_sq(mdev, sqn);
1268 }
1269
1270 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1271                         struct mlx5e_sq_param *param,
1272                         struct mlx5e_create_sq_param *csp,
1273                         u16 qos_queue_group_id,
1274                         u32 *sqn)
1275 {
1276         struct mlx5e_modify_sq_param msp = {0};
1277         int err;
1278
1279         err = mlx5e_create_sq(mdev, param, csp, sqn);
1280         if (err)
1281                 return err;
1282
1283         msp.curr_state = MLX5_SQC_STATE_RST;
1284         msp.next_state = MLX5_SQC_STATE_RDY;
1285         if (qos_queue_group_id) {
1286                 msp.qos_update = true;
1287                 msp.qos_queue_group_id = qos_queue_group_id;
1288         }
1289         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1290         if (err)
1291                 mlx5e_destroy_sq(mdev, *sqn);
1292
1293         return err;
1294 }
1295
1296 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1297                                 struct mlx5e_txqsq *sq, u32 rate);
1298
1299 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1300                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1301                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1302 {
1303         struct mlx5e_create_sq_param csp = {};
1304         u32 tx_rate;
1305         int err;
1306
1307         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1308         if (err)
1309                 return err;
1310
1311         if (qos_queue_group_id)
1312                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1313         else
1314                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1315
1316         csp.tisn            = tisn;
1317         csp.tis_lst_sz      = 1;
1318         csp.cqn             = sq->cq.mcq.cqn;
1319         csp.wq_ctrl         = &sq->wq_ctrl;
1320         csp.min_inline_mode = sq->min_inline_mode;
1321         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1322         if (err)
1323                 goto err_free_txqsq;
1324
1325         tx_rate = c->priv->tx_rates[sq->txq_ix];
1326         if (tx_rate)
1327                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1328
1329         if (params->tx_dim_enabled)
1330                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331
1332         return 0;
1333
1334 err_free_txqsq:
1335         mlx5e_free_txqsq(sq);
1336
1337         return err;
1338 }
1339
1340 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1343         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344         netdev_tx_reset_queue(sq->txq);
1345         netif_tx_start_queue(sq->txq);
1346 }
1347
1348 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1349 {
1350         __netif_tx_lock_bh(txq);
1351         netif_tx_stop_queue(txq);
1352         __netif_tx_unlock_bh(txq);
1353 }
1354
1355 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1356 {
1357         struct mlx5_wq_cyc *wq = &sq->wq;
1358
1359         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1361
1362         mlx5e_tx_disable_queue(sq->txq);
1363
1364         /* last doorbell out, godspeed .. */
1365         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1366                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1367                 struct mlx5e_tx_wqe *nop;
1368
1369                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1370                         .num_wqebbs = 1,
1371                 };
1372
1373                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1375         }
1376 }
1377
1378 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5_core_dev *mdev = sq->mdev;
1381         struct mlx5_rate_limit rl = {0};
1382
1383         cancel_work_sync(&sq->dim.work);
1384         cancel_work_sync(&sq->recover_work);
1385         mlx5e_destroy_sq(mdev, sq->sqn);
1386         if (sq->rate_limit) {
1387                 rl.rate = sq->rate_limit;
1388                 mlx5_rl_remove_rate(mdev, &rl);
1389         }
1390         mlx5e_free_txqsq_descs(sq);
1391         mlx5e_free_txqsq(sq);
1392 }
1393
1394 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1395 {
1396         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1397                                               recover_work);
1398
1399         mlx5e_reporter_tx_err_cqe(sq);
1400 }
1401
1402 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1403                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1404 {
1405         struct mlx5e_create_sq_param csp = {};
1406         int err;
1407
1408         err = mlx5e_alloc_icosq(c, param, sq);
1409         if (err)
1410                 return err;
1411
1412         csp.cqn             = sq->cq.mcq.cqn;
1413         csp.wq_ctrl         = &sq->wq_ctrl;
1414         csp.min_inline_mode = params->tx_min_inline_mode;
1415         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1416         if (err)
1417                 goto err_free_icosq;
1418
1419         if (param->is_tls) {
1420                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1421                 if (IS_ERR(sq->ktls_resync)) {
1422                         err = PTR_ERR(sq->ktls_resync);
1423                         goto err_destroy_icosq;
1424                 }
1425         }
1426         return 0;
1427
1428 err_destroy_icosq:
1429         mlx5e_destroy_sq(c->mdev, sq->sqn);
1430 err_free_icosq:
1431         mlx5e_free_icosq(sq);
1432
1433         return err;
1434 }
1435
1436 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1437 {
1438         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1439 }
1440
1441 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1442 {
1443         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1444         synchronize_net(); /* Sync with NAPI. */
1445 }
1446
1447 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1448 {
1449         struct mlx5e_channel *c = sq->channel;
1450
1451         if (sq->ktls_resync)
1452                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1453         mlx5e_destroy_sq(c->mdev, sq->sqn);
1454         mlx5e_free_icosq_descs(sq);
1455         mlx5e_free_icosq(sq);
1456 }
1457
1458 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1459                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1460                      struct mlx5e_xdpsq *sq, bool is_redirect)
1461 {
1462         struct mlx5e_create_sq_param csp = {};
1463         int err;
1464
1465         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1466         if (err)
1467                 return err;
1468
1469         csp.tis_lst_sz      = 1;
1470         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1471         csp.cqn             = sq->cq.mcq.cqn;
1472         csp.wq_ctrl         = &sq->wq_ctrl;
1473         csp.min_inline_mode = sq->min_inline_mode;
1474         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1476         if (err)
1477                 goto err_free_xdpsq;
1478
1479         mlx5e_set_xmit_fp(sq, param->is_mpw);
1480
1481         if (!param->is_mpw) {
1482                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1483                 unsigned int inline_hdr_sz = 0;
1484                 int i;
1485
1486                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1487                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1488                         ds_cnt++;
1489                 }
1490
1491                 /* Pre initialize fixed WQE fields */
1492                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1493                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1494                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1495                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1496                         struct mlx5_wqe_data_seg *dseg;
1497
1498                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1499                                 .num_wqebbs = 1,
1500                                 .num_pkts   = 1,
1501                         };
1502
1503                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1504                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1505
1506                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1507                         dseg->lkey = sq->mkey_be;
1508                 }
1509         }
1510
1511         return 0;
1512
1513 err_free_xdpsq:
1514         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515         mlx5e_free_xdpsq(sq);
1516
1517         return err;
1518 }
1519
1520 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1521 {
1522         struct mlx5e_channel *c = sq->channel;
1523
1524         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525         synchronize_net(); /* Sync with NAPI. */
1526
1527         mlx5e_destroy_sq(c->mdev, sq->sqn);
1528         mlx5e_free_xdpsq_descs(sq);
1529         mlx5e_free_xdpsq(sq);
1530 }
1531
1532 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1533                                  struct mlx5e_cq_param *param,
1534                                  struct mlx5e_cq *cq)
1535 {
1536         struct mlx5_core_dev *mdev = priv->mdev;
1537         struct mlx5_core_cq *mcq = &cq->mcq;
1538         int eqn_not_used;
1539         unsigned int irqn;
1540         int err;
1541         u32 i;
1542
1543         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1544         if (err)
1545                 return err;
1546
1547         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1548                                &cq->wq_ctrl);
1549         if (err)
1550                 return err;
1551
1552         mcq->cqe_sz     = 64;
1553         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1554         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1555         *mcq->set_ci_db = 0;
1556         *mcq->arm_db    = 0;
1557         mcq->vector     = param->eq_ix;
1558         mcq->comp       = mlx5e_completion_event;
1559         mcq->event      = mlx5e_cq_error_event;
1560         mcq->irqn       = irqn;
1561
1562         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1563                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1564
1565                 cqe->op_own = 0xf1;
1566         }
1567
1568         cq->mdev = mdev;
1569         cq->netdev = priv->netdev;
1570         cq->priv = priv;
1571
1572         return 0;
1573 }
1574
1575 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1576                           struct mlx5e_cq_param *param,
1577                           struct mlx5e_create_cq_param *ccp,
1578                           struct mlx5e_cq *cq)
1579 {
1580         int err;
1581
1582         param->wq.buf_numa_node = ccp->node;
1583         param->wq.db_numa_node  = ccp->node;
1584         param->eq_ix            = ccp->ix;
1585
1586         err = mlx5e_alloc_cq_common(priv, param, cq);
1587
1588         cq->napi     = ccp->napi;
1589         cq->ch_stats = ccp->ch_stats;
1590
1591         return err;
1592 }
1593
1594 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1595 {
1596         mlx5_wq_destroy(&cq->wq_ctrl);
1597 }
1598
1599 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1600 {
1601         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1602         struct mlx5_core_dev *mdev = cq->mdev;
1603         struct mlx5_core_cq *mcq = &cq->mcq;
1604
1605         void *in;
1606         void *cqc;
1607         int inlen;
1608         unsigned int irqn_not_used;
1609         int eqn;
1610         int err;
1611
1612         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1613         if (err)
1614                 return err;
1615
1616         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1617                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1618         in = kvzalloc(inlen, GFP_KERNEL);
1619         if (!in)
1620                 return -ENOMEM;
1621
1622         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1623
1624         memcpy(cqc, param->cqc, sizeof(param->cqc));
1625
1626         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1627                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1628
1629         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1630         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1631         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1632         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1633                                             MLX5_ADAPTER_PAGE_SHIFT);
1634         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1635
1636         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1637
1638         kvfree(in);
1639
1640         if (err)
1641                 return err;
1642
1643         mlx5e_cq_arm(cq);
1644
1645         return 0;
1646 }
1647
1648 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1649 {
1650         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1651 }
1652
1653 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1654                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1655                   struct mlx5e_cq *cq)
1656 {
1657         struct mlx5_core_dev *mdev = priv->mdev;
1658         int err;
1659
1660         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1661         if (err)
1662                 return err;
1663
1664         err = mlx5e_create_cq(cq, param);
1665         if (err)
1666                 goto err_free_cq;
1667
1668         if (MLX5_CAP_GEN(mdev, cq_moderation))
1669                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1670         return 0;
1671
1672 err_free_cq:
1673         mlx5e_free_cq(cq);
1674
1675         return err;
1676 }
1677
1678 void mlx5e_close_cq(struct mlx5e_cq *cq)
1679 {
1680         mlx5e_destroy_cq(cq);
1681         mlx5e_free_cq(cq);
1682 }
1683
1684 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1685                              struct mlx5e_params *params,
1686                              struct mlx5e_create_cq_param *ccp,
1687                              struct mlx5e_channel_param *cparam)
1688 {
1689         int err;
1690         int tc;
1691
1692         for (tc = 0; tc < c->num_tc; tc++) {
1693                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1694                                     ccp, &c->sq[tc].cq);
1695                 if (err)
1696                         goto err_close_tx_cqs;
1697         }
1698
1699         return 0;
1700
1701 err_close_tx_cqs:
1702         for (tc--; tc >= 0; tc--)
1703                 mlx5e_close_cq(&c->sq[tc].cq);
1704
1705         return err;
1706 }
1707
1708 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1709 {
1710         int tc;
1711
1712         for (tc = 0; tc < c->num_tc; tc++)
1713                 mlx5e_close_cq(&c->sq[tc].cq);
1714 }
1715
1716 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1717                           struct mlx5e_params *params,
1718                           struct mlx5e_channel_param *cparam)
1719 {
1720         int err, tc;
1721
1722         for (tc = 0; tc < params->num_tc; tc++) {
1723                 int txq_ix = c->ix + tc * params->num_channels;
1724
1725                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1726                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1727                 if (err)
1728                         goto err_close_sqs;
1729         }
1730
1731         return 0;
1732
1733 err_close_sqs:
1734         for (tc--; tc >= 0; tc--)
1735                 mlx5e_close_txqsq(&c->sq[tc]);
1736
1737         return err;
1738 }
1739
1740 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1741 {
1742         int tc;
1743
1744         for (tc = 0; tc < c->num_tc; tc++)
1745                 mlx5e_close_txqsq(&c->sq[tc]);
1746 }
1747
1748 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1749                                 struct mlx5e_txqsq *sq, u32 rate)
1750 {
1751         struct mlx5e_priv *priv = netdev_priv(dev);
1752         struct mlx5_core_dev *mdev = priv->mdev;
1753         struct mlx5e_modify_sq_param msp = {0};
1754         struct mlx5_rate_limit rl = {0};
1755         u16 rl_index = 0;
1756         int err;
1757
1758         if (rate == sq->rate_limit)
1759                 /* nothing to do */
1760                 return 0;
1761
1762         if (sq->rate_limit) {
1763                 rl.rate = sq->rate_limit;
1764                 /* remove current rl index to free space to next ones */
1765                 mlx5_rl_remove_rate(mdev, &rl);
1766         }
1767
1768         sq->rate_limit = 0;
1769
1770         if (rate) {
1771                 rl.rate = rate;
1772                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1773                 if (err) {
1774                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1775                                    rate, err);
1776                         return err;
1777                 }
1778         }
1779
1780         msp.curr_state = MLX5_SQC_STATE_RDY;
1781         msp.next_state = MLX5_SQC_STATE_RDY;
1782         msp.rl_index   = rl_index;
1783         msp.rl_update  = true;
1784         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1785         if (err) {
1786                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1787                            rate, err);
1788                 /* remove the rate from the table */
1789                 if (rate)
1790                         mlx5_rl_remove_rate(mdev, &rl);
1791                 return err;
1792         }
1793
1794         sq->rate_limit = rate;
1795         return 0;
1796 }
1797
1798 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1799 {
1800         struct mlx5e_priv *priv = netdev_priv(dev);
1801         struct mlx5_core_dev *mdev = priv->mdev;
1802         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1803         int err = 0;
1804
1805         if (!mlx5_rl_is_supported(mdev)) {
1806                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1807                 return -EINVAL;
1808         }
1809
1810         /* rate is given in Mb/sec, HW config is in Kb/sec */
1811         rate = rate << 10;
1812
1813         /* Check whether rate in valid range, 0 is always valid */
1814         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1815                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1816                 return -ERANGE;
1817         }
1818
1819         mutex_lock(&priv->state_lock);
1820         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1821                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1822         if (!err)
1823                 priv->tx_rates[index] = rate;
1824         mutex_unlock(&priv->state_lock);
1825
1826         return err;
1827 }
1828
1829 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1830                              struct mlx5e_rq_param *rq_params)
1831 {
1832         int err;
1833
1834         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1835         if (err)
1836                 return err;
1837
1838         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1839 }
1840
1841 static int mlx5e_open_queues(struct mlx5e_channel *c,
1842                              struct mlx5e_params *params,
1843                              struct mlx5e_channel_param *cparam)
1844 {
1845         struct dim_cq_moder icocq_moder = {0, 0};
1846         struct mlx5e_create_cq_param ccp;
1847         int err;
1848
1849         mlx5e_build_create_cq_param(&ccp, c);
1850
1851         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1852                             &c->async_icosq.cq);
1853         if (err)
1854                 return err;
1855
1856         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1857                             &c->icosq.cq);
1858         if (err)
1859                 goto err_close_async_icosq_cq;
1860
1861         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1862         if (err)
1863                 goto err_close_icosq_cq;
1864
1865         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1866                             &c->xdpsq.cq);
1867         if (err)
1868                 goto err_close_tx_cqs;
1869
1870         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1871                             &c->rq.cq);
1872         if (err)
1873                 goto err_close_xdp_tx_cqs;
1874
1875         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1876                                      &ccp, &c->rq_xdpsq.cq) : 0;
1877         if (err)
1878                 goto err_close_rx_cq;
1879
1880         spin_lock_init(&c->async_icosq_lock);
1881
1882         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1883         if (err)
1884                 goto err_close_xdpsq_cq;
1885
1886         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1887         if (err)
1888                 goto err_close_async_icosq;
1889
1890         err = mlx5e_open_sqs(c, params, cparam);
1891         if (err)
1892                 goto err_close_icosq;
1893
1894         if (c->xdp) {
1895                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1896                                        &c->rq_xdpsq, false);
1897                 if (err)
1898                         goto err_close_sqs;
1899         }
1900
1901         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1902         if (err)
1903                 goto err_close_xdp_sq;
1904
1905         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1906         if (err)
1907                 goto err_close_rq;
1908
1909         return 0;
1910
1911 err_close_rq:
1912         mlx5e_close_rq(&c->rq);
1913
1914 err_close_xdp_sq:
1915         if (c->xdp)
1916                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1917
1918 err_close_sqs:
1919         mlx5e_close_sqs(c);
1920
1921 err_close_icosq:
1922         mlx5e_close_icosq(&c->icosq);
1923
1924 err_close_async_icosq:
1925         mlx5e_close_icosq(&c->async_icosq);
1926
1927 err_close_xdpsq_cq:
1928         if (c->xdp)
1929                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1930
1931 err_close_rx_cq:
1932         mlx5e_close_cq(&c->rq.cq);
1933
1934 err_close_xdp_tx_cqs:
1935         mlx5e_close_cq(&c->xdpsq.cq);
1936
1937 err_close_tx_cqs:
1938         mlx5e_close_tx_cqs(c);
1939
1940 err_close_icosq_cq:
1941         mlx5e_close_cq(&c->icosq.cq);
1942
1943 err_close_async_icosq_cq:
1944         mlx5e_close_cq(&c->async_icosq.cq);
1945
1946         return err;
1947 }
1948
1949 static void mlx5e_close_queues(struct mlx5e_channel *c)
1950 {
1951         mlx5e_close_xdpsq(&c->xdpsq);
1952         mlx5e_close_rq(&c->rq);
1953         if (c->xdp)
1954                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1955         mlx5e_close_sqs(c);
1956         mlx5e_close_icosq(&c->icosq);
1957         mlx5e_close_icosq(&c->async_icosq);
1958         if (c->xdp)
1959                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1960         mlx5e_close_cq(&c->rq.cq);
1961         mlx5e_close_cq(&c->xdpsq.cq);
1962         mlx5e_close_tx_cqs(c);
1963         mlx5e_close_cq(&c->icosq.cq);
1964         mlx5e_close_cq(&c->async_icosq.cq);
1965 }
1966
1967 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1968 {
1969         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1970
1971         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1972 }
1973
1974 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1975                               struct mlx5e_params *params,
1976                               struct mlx5e_channel_param *cparam,
1977                               struct xsk_buff_pool *xsk_pool,
1978                               struct mlx5e_channel **cp)
1979 {
1980         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1981         struct net_device *netdev = priv->netdev;
1982         struct mlx5e_xsk_param xsk;
1983         struct mlx5e_channel *c;
1984         unsigned int irq;
1985         int err;
1986         int eqn;
1987
1988         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1989         if (err)
1990                 return err;
1991
1992         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1993         if (!c)
1994                 return -ENOMEM;
1995
1996         c->priv     = priv;
1997         c->mdev     = priv->mdev;
1998         c->tstamp   = &priv->tstamp;
1999         c->ix       = ix;
2000         c->cpu      = cpu;
2001         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2002         c->netdev   = priv->netdev;
2003         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2004         c->num_tc   = params->num_tc;
2005         c->xdp      = !!params->xdp_prog;
2006         c->stats    = &priv->channel_stats[ix].ch;
2007         c->aff_mask = irq_get_effective_affinity_mask(irq);
2008         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2009
2010         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2011
2012         err = mlx5e_open_queues(c, params, cparam);
2013         if (unlikely(err))
2014                 goto err_napi_del;
2015
2016         if (xsk_pool) {
2017                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2018                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2019                 if (unlikely(err))
2020                         goto err_close_queues;
2021         }
2022
2023         *cp = c;
2024
2025         return 0;
2026
2027 err_close_queues:
2028         mlx5e_close_queues(c);
2029
2030 err_napi_del:
2031         netif_napi_del(&c->napi);
2032
2033         kvfree(c);
2034
2035         return err;
2036 }
2037
2038 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2039 {
2040         int tc;
2041
2042         napi_enable(&c->napi);
2043
2044         for (tc = 0; tc < c->num_tc; tc++)
2045                 mlx5e_activate_txqsq(&c->sq[tc]);
2046         mlx5e_activate_icosq(&c->icosq);
2047         mlx5e_activate_icosq(&c->async_icosq);
2048         mlx5e_activate_rq(&c->rq);
2049
2050         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051                 mlx5e_activate_xsk(c);
2052 }
2053
2054 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2055 {
2056         int tc;
2057
2058         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2059                 mlx5e_deactivate_xsk(c);
2060
2061         mlx5e_deactivate_rq(&c->rq);
2062         mlx5e_deactivate_icosq(&c->async_icosq);
2063         mlx5e_deactivate_icosq(&c->icosq);
2064         for (tc = 0; tc < c->num_tc; tc++)
2065                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2066         mlx5e_qos_deactivate_queues(c);
2067
2068         napi_disable(&c->napi);
2069 }
2070
2071 static void mlx5e_close_channel(struct mlx5e_channel *c)
2072 {
2073         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2074                 mlx5e_close_xsk(c);
2075         mlx5e_close_queues(c);
2076         mlx5e_qos_close_queues(c);
2077         netif_napi_del(&c->napi);
2078
2079         kvfree(c);
2080 }
2081
2082 int mlx5e_open_channels(struct mlx5e_priv *priv,
2083                         struct mlx5e_channels *chs)
2084 {
2085         struct mlx5e_channel_param *cparam;
2086         int err = -ENOMEM;
2087         int i;
2088
2089         chs->num = chs->params.num_channels;
2090
2091         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2092         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2093         if (!chs->c || !cparam)
2094                 goto err_free;
2095
2096         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2097         if (err)
2098                 goto err_free;
2099
2100         for (i = 0; i < chs->num; i++) {
2101                 struct xsk_buff_pool *xsk_pool = NULL;
2102
2103                 if (chs->params.xdp_prog)
2104                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2105
2106                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2107                 if (err)
2108                         goto err_close_channels;
2109         }
2110
2111         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2112                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2113                 if (err)
2114                         goto err_close_channels;
2115         }
2116
2117         err = mlx5e_qos_open_queues(priv, chs);
2118         if (err)
2119                 goto err_close_ptp;
2120
2121         mlx5e_health_channels_update(priv);
2122         kvfree(cparam);
2123         return 0;
2124
2125 err_close_ptp:
2126         if (chs->ptp)
2127                 mlx5e_ptp_close(chs->ptp);
2128
2129 err_close_channels:
2130         for (i--; i >= 0; i--)
2131                 mlx5e_close_channel(chs->c[i]);
2132
2133 err_free:
2134         kfree(chs->c);
2135         kvfree(cparam);
2136         chs->num = 0;
2137         return err;
2138 }
2139
2140 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2141 {
2142         int i;
2143
2144         for (i = 0; i < chs->num; i++)
2145                 mlx5e_activate_channel(chs->c[i]);
2146
2147         if (chs->ptp)
2148                 mlx5e_ptp_activate_channel(chs->ptp);
2149 }
2150
2151 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2152
2153 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2154 {
2155         int err = 0;
2156         int i;
2157
2158         for (i = 0; i < chs->num; i++) {
2159                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2160
2161                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2162
2163                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2164                  * doesn't provide any Fill Ring entries at the setup stage.
2165                  */
2166         }
2167
2168         return err ? -ETIMEDOUT : 0;
2169 }
2170
2171 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2172 {
2173         int i;
2174
2175         if (chs->ptp)
2176                 mlx5e_ptp_deactivate_channel(chs->ptp);
2177
2178         for (i = 0; i < chs->num; i++)
2179                 mlx5e_deactivate_channel(chs->c[i]);
2180 }
2181
2182 void mlx5e_close_channels(struct mlx5e_channels *chs)
2183 {
2184         int i;
2185
2186         if (chs->ptp) {
2187                 mlx5e_ptp_close(chs->ptp);
2188                 chs->ptp = NULL;
2189         }
2190         for (i = 0; i < chs->num; i++)
2191                 mlx5e_close_channel(chs->c[i]);
2192
2193         kfree(chs->c);
2194         chs->num = 0;
2195 }
2196
2197 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2198 {
2199         struct mlx5e_rx_res *res = priv->rx_res;
2200         struct mlx5e_lro_param lro_param;
2201
2202         lro_param = mlx5e_get_lro_param(&priv->channels.params);
2203
2204         return mlx5e_rx_res_lro_set_param(res, &lro_param);
2205 }
2206
2207 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2208
2209 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2210                          struct mlx5e_params *params, u16 mtu)
2211 {
2212         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2213         int err;
2214
2215         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2216         if (err)
2217                 return err;
2218
2219         /* Update vport context MTU */
2220         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2221         return 0;
2222 }
2223
2224 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2225                             struct mlx5e_params *params, u16 *mtu)
2226 {
2227         u16 hw_mtu = 0;
2228         int err;
2229
2230         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2231         if (err || !hw_mtu) /* fallback to port oper mtu */
2232                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2233
2234         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2235 }
2236
2237 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2238 {
2239         struct mlx5e_params *params = &priv->channels.params;
2240         struct net_device *netdev = priv->netdev;
2241         struct mlx5_core_dev *mdev = priv->mdev;
2242         u16 mtu;
2243         int err;
2244
2245         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2246         if (err)
2247                 return err;
2248
2249         mlx5e_query_mtu(mdev, params, &mtu);
2250         if (mtu != params->sw_mtu)
2251                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2252                             __func__, mtu, params->sw_mtu);
2253
2254         params->sw_mtu = mtu;
2255         return 0;
2256 }
2257
2258 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2259
2260 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2261 {
2262         struct mlx5e_params *params = &priv->channels.params;
2263         struct net_device *netdev   = priv->netdev;
2264         struct mlx5_core_dev *mdev  = priv->mdev;
2265         u16 max_mtu;
2266
2267         /* MTU range: 68 - hw-specific max */
2268         netdev->min_mtu = ETH_MIN_MTU;
2269
2270         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2271         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2272                                 ETH_MAX_MTU);
2273 }
2274
2275 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2276 {
2277         int tc;
2278
2279         netdev_reset_tc(netdev);
2280
2281         if (ntc == 1)
2282                 return;
2283
2284         netdev_set_num_tc(netdev, ntc);
2285
2286         /* Map netdev TCs to offset 0
2287          * We have our own UP to TXQ mapping for QoS
2288          */
2289         for (tc = 0; tc < ntc; tc++)
2290                 netdev_set_tc_queue(netdev, tc, nch, 0);
2291 }
2292
2293 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2294 {
2295         int qos_queues, nch, ntc, num_txqs, err;
2296
2297         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2298
2299         nch = priv->channels.params.num_channels;
2300         ntc = priv->channels.params.num_tc;
2301         num_txqs = nch * ntc + qos_queues;
2302         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2303                 num_txqs += ntc;
2304
2305         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2306         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2307         if (err)
2308                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2309
2310         return err;
2311 }
2312
2313 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2314 {
2315         struct net_device *netdev = priv->netdev;
2316         int old_num_txqs, old_ntc;
2317         int num_rxqs, nch, ntc;
2318         int err;
2319
2320         old_num_txqs = netdev->real_num_tx_queues;
2321         old_ntc = netdev->num_tc ? : 1;
2322
2323         nch = priv->channels.params.num_channels;
2324         ntc = priv->channels.params.num_tc;
2325         num_rxqs = nch * priv->profile->rq_groups;
2326
2327         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2328
2329         err = mlx5e_update_tx_netdev_queues(priv);
2330         if (err)
2331                 goto err_tcs;
2332         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2333         if (err) {
2334                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2335                 goto err_txqs;
2336         }
2337
2338         return 0;
2339
2340 err_txqs:
2341         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2342          * one of nch and ntc is changed in this function. That means, the call
2343          * to netif_set_real_num_tx_queues below should not fail, because it
2344          * decreases the number of TX queues.
2345          */
2346         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2347
2348 err_tcs:
2349         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2350         return err;
2351 }
2352
2353 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2354                                            struct mlx5e_params *params)
2355 {
2356         struct mlx5_core_dev *mdev = priv->mdev;
2357         int num_comp_vectors, ix, irq;
2358
2359         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2360
2361         for (ix = 0; ix < params->num_channels; ix++) {
2362                 cpumask_clear(priv->scratchpad.cpumask);
2363
2364                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2365                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2366
2367                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2368                 }
2369
2370                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2371         }
2372 }
2373
2374 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2375 {
2376         u16 count = priv->channels.params.num_channels;
2377         int err;
2378
2379         err = mlx5e_update_netdev_queues(priv);
2380         if (err)
2381                 return err;
2382
2383         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2384
2385         /* This function may be called on attach, before priv->rx_res is created. */
2386         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2387                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2388
2389         return 0;
2390 }
2391
2392 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2393
2394 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2395 {
2396         int i, ch, tc, num_tc;
2397
2398         ch = priv->channels.num;
2399         num_tc = priv->channels.params.num_tc;
2400
2401         for (i = 0; i < ch; i++) {
2402                 for (tc = 0; tc < num_tc; tc++) {
2403                         struct mlx5e_channel *c = priv->channels.c[i];
2404                         struct mlx5e_txqsq *sq = &c->sq[tc];
2405
2406                         priv->txq2sq[sq->txq_ix] = sq;
2407                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2408                 }
2409         }
2410
2411         if (!priv->channels.ptp)
2412                 return;
2413
2414         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2415                 return;
2416
2417         for (tc = 0; tc < num_tc; tc++) {
2418                 struct mlx5e_ptp *c = priv->channels.ptp;
2419                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2420
2421                 priv->txq2sq[sq->txq_ix] = sq;
2422                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2423         }
2424 }
2425
2426 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2427 {
2428         /* Sync with mlx5e_select_queue. */
2429         WRITE_ONCE(priv->num_tc_x_num_ch,
2430                    priv->channels.params.num_tc * priv->channels.num);
2431 }
2432
2433 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2434 {
2435         mlx5e_update_num_tc_x_num_ch(priv);
2436         mlx5e_build_txq_maps(priv);
2437         mlx5e_activate_channels(&priv->channels);
2438         mlx5e_qos_activate_queues(priv);
2439         mlx5e_xdp_tx_enable(priv);
2440         netif_tx_start_all_queues(priv->netdev);
2441
2442         if (mlx5e_is_vport_rep(priv))
2443                 mlx5e_add_sqs_fwd_rules(priv);
2444
2445         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2446
2447         if (priv->rx_res)
2448                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2449 }
2450
2451 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2452 {
2453         if (priv->rx_res)
2454                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2455
2456         if (mlx5e_is_vport_rep(priv))
2457                 mlx5e_remove_sqs_fwd_rules(priv);
2458
2459         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2460          * polling for inactive tx queues.
2461          */
2462         netif_tx_stop_all_queues(priv->netdev);
2463         netif_tx_disable(priv->netdev);
2464         mlx5e_xdp_tx_disable(priv);
2465         mlx5e_deactivate_channels(&priv->channels);
2466 }
2467
2468 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2469                                     struct mlx5e_params *new_params,
2470                                     mlx5e_fp_preactivate preactivate,
2471                                     void *context)
2472 {
2473         struct mlx5e_params old_params;
2474
2475         old_params = priv->channels.params;
2476         priv->channels.params = *new_params;
2477
2478         if (preactivate) {
2479                 int err;
2480
2481                 err = preactivate(priv, context);
2482                 if (err) {
2483                         priv->channels.params = old_params;
2484                         return err;
2485                 }
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2492                                       struct mlx5e_channels *new_chs,
2493                                       mlx5e_fp_preactivate preactivate,
2494                                       void *context)
2495 {
2496         struct net_device *netdev = priv->netdev;
2497         struct mlx5e_channels old_chs;
2498         int carrier_ok;
2499         int err = 0;
2500
2501         carrier_ok = netif_carrier_ok(netdev);
2502         netif_carrier_off(netdev);
2503
2504         mlx5e_deactivate_priv_channels(priv);
2505
2506         old_chs = priv->channels;
2507         priv->channels = *new_chs;
2508
2509         /* New channels are ready to roll, call the preactivate hook if needed
2510          * to modify HW settings or update kernel parameters.
2511          */
2512         if (preactivate) {
2513                 err = preactivate(priv, context);
2514                 if (err) {
2515                         priv->channels = old_chs;
2516                         goto out;
2517                 }
2518         }
2519
2520         mlx5e_close_channels(&old_chs);
2521         priv->profile->update_rx(priv);
2522
2523 out:
2524         mlx5e_activate_priv_channels(priv);
2525
2526         /* return carrier back if needed */
2527         if (carrier_ok)
2528                 netif_carrier_on(netdev);
2529
2530         return err;
2531 }
2532
2533 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2534                              struct mlx5e_params *params,
2535                              mlx5e_fp_preactivate preactivate,
2536                              void *context, bool reset)
2537 {
2538         struct mlx5e_channels new_chs = {};
2539         int err;
2540
2541         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2542         if (!reset)
2543                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2544
2545         new_chs.params = *params;
2546         err = mlx5e_open_channels(priv, &new_chs);
2547         if (err)
2548                 return err;
2549         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2550         if (err)
2551                 mlx5e_close_channels(&new_chs);
2552
2553         return err;
2554 }
2555
2556 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2557 {
2558         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2559 }
2560
2561 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2562 {
2563         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2564         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2565 }
2566
2567 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2568                                      enum mlx5_port_status state)
2569 {
2570         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2571         int vport_admin_state;
2572
2573         mlx5_set_port_admin_status(mdev, state);
2574
2575         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2576             !MLX5_CAP_GEN(mdev, uplink_follow))
2577                 return;
2578
2579         if (state == MLX5_PORT_UP)
2580                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2581         else
2582                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2583
2584         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2585 }
2586
2587 int mlx5e_open_locked(struct net_device *netdev)
2588 {
2589         struct mlx5e_priv *priv = netdev_priv(netdev);
2590         int err;
2591
2592         set_bit(MLX5E_STATE_OPENED, &priv->state);
2593
2594         err = mlx5e_open_channels(priv, &priv->channels);
2595         if (err)
2596                 goto err_clear_state_opened_flag;
2597
2598         priv->profile->update_rx(priv);
2599         mlx5e_activate_priv_channels(priv);
2600         mlx5e_apply_traps(priv, true);
2601         if (priv->profile->update_carrier)
2602                 priv->profile->update_carrier(priv);
2603
2604         mlx5e_queue_update_stats(priv);
2605         return 0;
2606
2607 err_clear_state_opened_flag:
2608         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2609         return err;
2610 }
2611
2612 int mlx5e_open(struct net_device *netdev)
2613 {
2614         struct mlx5e_priv *priv = netdev_priv(netdev);
2615         int err;
2616
2617         mutex_lock(&priv->state_lock);
2618         err = mlx5e_open_locked(netdev);
2619         if (!err)
2620                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2621         mutex_unlock(&priv->state_lock);
2622
2623         return err;
2624 }
2625
2626 int mlx5e_close_locked(struct net_device *netdev)
2627 {
2628         struct mlx5e_priv *priv = netdev_priv(netdev);
2629
2630         /* May already be CLOSED in case a previous configuration operation
2631          * (e.g RX/TX queue size change) that involves close&open failed.
2632          */
2633         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2634                 return 0;
2635
2636         mlx5e_apply_traps(priv, false);
2637         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2638
2639         netif_carrier_off(priv->netdev);
2640         mlx5e_deactivate_priv_channels(priv);
2641         mlx5e_close_channels(&priv->channels);
2642
2643         return 0;
2644 }
2645
2646 int mlx5e_close(struct net_device *netdev)
2647 {
2648         struct mlx5e_priv *priv = netdev_priv(netdev);
2649         int err;
2650
2651         if (!netif_device_present(netdev))
2652                 return -ENODEV;
2653
2654         mutex_lock(&priv->state_lock);
2655         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2656         err = mlx5e_close_locked(netdev);
2657         mutex_unlock(&priv->state_lock);
2658
2659         return err;
2660 }
2661
2662 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2663 {
2664         mlx5_wq_destroy(&rq->wq_ctrl);
2665 }
2666
2667 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2668                                struct mlx5e_rq *rq,
2669                                struct mlx5e_rq_param *param)
2670 {
2671         void *rqc = param->rqc;
2672         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2673         int err;
2674
2675         param->wq.db_numa_node = param->wq.buf_numa_node;
2676
2677         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2678                                  &rq->wq_ctrl);
2679         if (err)
2680                 return err;
2681
2682         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2683         xdp_rxq_info_unused(&rq->xdp_rxq);
2684
2685         rq->mdev = mdev;
2686
2687         return 0;
2688 }
2689
2690 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2691                                struct mlx5e_cq *cq,
2692                                struct mlx5e_cq_param *param)
2693 {
2694         struct mlx5_core_dev *mdev = priv->mdev;
2695
2696         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2697         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
2698
2699         return mlx5e_alloc_cq_common(priv, param, cq);
2700 }
2701
2702 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2703                        struct mlx5e_rq *drop_rq)
2704 {
2705         struct mlx5_core_dev *mdev = priv->mdev;
2706         struct mlx5e_cq_param cq_param = {};
2707         struct mlx5e_rq_param rq_param = {};
2708         struct mlx5e_cq *cq = &drop_rq->cq;
2709         int err;
2710
2711         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2712
2713         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2714         if (err)
2715                 return err;
2716
2717         err = mlx5e_create_cq(cq, &cq_param);
2718         if (err)
2719                 goto err_free_cq;
2720
2721         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2722         if (err)
2723                 goto err_destroy_cq;
2724
2725         err = mlx5e_create_rq(drop_rq, &rq_param);
2726         if (err)
2727                 goto err_free_rq;
2728
2729         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2730         if (err)
2731                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2732
2733         return 0;
2734
2735 err_free_rq:
2736         mlx5e_free_drop_rq(drop_rq);
2737
2738 err_destroy_cq:
2739         mlx5e_destroy_cq(cq);
2740
2741 err_free_cq:
2742         mlx5e_free_cq(cq);
2743
2744         return err;
2745 }
2746
2747 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2748 {
2749         mlx5e_destroy_rq(drop_rq);
2750         mlx5e_free_drop_rq(drop_rq);
2751         mlx5e_destroy_cq(&drop_rq->cq);
2752         mlx5e_free_cq(&drop_rq->cq);
2753 }
2754
2755 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
2756 {
2757         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2758
2759         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
2760
2761         if (MLX5_GET(tisc, tisc, tls_en))
2762                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
2763
2764         if (mlx5_lag_is_lacp_owner(mdev))
2765                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2766
2767         return mlx5_core_create_tis(mdev, in, tisn);
2768 }
2769
2770 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2771 {
2772         mlx5_core_destroy_tis(mdev, tisn);
2773 }
2774
2775 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
2776 {
2777         int tc, i;
2778
2779         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
2780                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2781                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2782 }
2783
2784 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
2785 {
2786         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
2787 }
2788
2789 int mlx5e_create_tises(struct mlx5e_priv *priv)
2790 {
2791         int tc, i;
2792         int err;
2793
2794         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
2795                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2796                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
2797                         void *tisc;
2798
2799                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2800
2801                         MLX5_SET(tisc, tisc, prio, tc << 1);
2802
2803                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
2804                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
2805
2806                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
2807                         if (err)
2808                                 goto err_close_tises;
2809                 }
2810         }
2811
2812         return 0;
2813
2814 err_close_tises:
2815         for (; i >= 0; i--) {
2816                 for (tc--; tc >= 0; tc--)
2817                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2818                 tc = priv->profile->max_tc;
2819         }
2820
2821         return err;
2822 }
2823
2824 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2825 {
2826         mlx5e_destroy_tises(priv);
2827 }
2828
2829 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2830 {
2831         int err = 0;
2832         int i;
2833
2834         for (i = 0; i < chs->num; i++) {
2835                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2836                 if (err)
2837                         return err;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2844 {
2845         int err;
2846         int i;
2847
2848         for (i = 0; i < chs->num; i++) {
2849                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2850                 if (err)
2851                         return err;
2852         }
2853         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
2854                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
2855
2856         return 0;
2857 }
2858
2859 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
2860                                  struct tc_mqprio_qopt *mqprio)
2861 {
2862         struct mlx5e_params new_params;
2863         u8 tc = mqprio->num_tc;
2864         int err = 0;
2865
2866         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2867
2868         if (tc && tc != MLX5E_MAX_NUM_TC)
2869                 return -EINVAL;
2870
2871         mutex_lock(&priv->state_lock);
2872
2873         /* MQPRIO is another toplevel qdisc that can't be attached
2874          * simultaneously with the offloaded HTB.
2875          */
2876         if (WARN_ON(priv->htb.maj_id)) {
2877                 err = -EINVAL;
2878                 goto out;
2879         }
2880
2881         new_params = priv->channels.params;
2882         new_params.num_tc = tc ? tc : 1;
2883
2884         err = mlx5e_safe_switch_params(priv, &new_params,
2885                                        mlx5e_num_channels_changed_ctx, NULL, true);
2886
2887 out:
2888         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
2889                                     priv->channels.params.num_tc);
2890         mutex_unlock(&priv->state_lock);
2891         return err;
2892 }
2893
2894 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
2895 {
2896         int res;
2897
2898         switch (htb->command) {
2899         case TC_HTB_CREATE:
2900                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
2901                                           htb->extack);
2902         case TC_HTB_DESTROY:
2903                 return mlx5e_htb_root_del(priv);
2904         case TC_HTB_LEAF_ALLOC_QUEUE:
2905                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
2906                                                  htb->rate, htb->ceil, htb->extack);
2907                 if (res < 0)
2908                         return res;
2909                 htb->qid = res;
2910                 return 0;
2911         case TC_HTB_LEAF_TO_INNER:
2912                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
2913                                                htb->rate, htb->ceil, htb->extack);
2914         case TC_HTB_LEAF_DEL:
2915                 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
2916                                           htb->extack);
2917         case TC_HTB_LEAF_DEL_LAST:
2918         case TC_HTB_LEAF_DEL_LAST_FORCE:
2919                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
2920                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
2921                                                htb->extack);
2922         case TC_HTB_NODE_MODIFY:
2923                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
2924                                              htb->extack);
2925         case TC_HTB_LEAF_QUERY_QUEUE:
2926                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
2927                 if (res < 0)
2928                         return res;
2929                 htb->qid = res;
2930                 return 0;
2931         default:
2932                 return -EOPNOTSUPP;
2933         }
2934 }
2935
2936 static LIST_HEAD(mlx5e_block_cb_list);
2937
2938 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
2939                           void *type_data)
2940 {
2941         struct mlx5e_priv *priv = netdev_priv(dev);
2942         bool tc_unbind = false;
2943         int err;
2944
2945         if (type == TC_SETUP_BLOCK &&
2946             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
2947                 tc_unbind = true;
2948
2949         if (!netif_device_present(dev) && !tc_unbind)
2950                 return -ENODEV;
2951
2952         switch (type) {
2953         case TC_SETUP_BLOCK: {
2954                 struct flow_block_offload *f = type_data;
2955
2956                 f->unlocked_driver_cb = true;
2957                 return flow_block_cb_setup_simple(type_data,
2958                                                   &mlx5e_block_cb_list,
2959                                                   mlx5e_setup_tc_block_cb,
2960                                                   priv, priv, true);
2961         }
2962         case TC_SETUP_QDISC_MQPRIO:
2963                 return mlx5e_setup_tc_mqprio(priv, type_data);
2964         case TC_SETUP_QDISC_HTB:
2965                 mutex_lock(&priv->state_lock);
2966                 err = mlx5e_setup_tc_htb(priv, type_data);
2967                 mutex_unlock(&priv->state_lock);
2968                 return err;
2969         default:
2970                 return -EOPNOTSUPP;
2971         }
2972 }
2973
2974 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
2975 {
2976         int i;
2977
2978         for (i = 0; i < priv->max_nch; i++) {
2979                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
2980                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
2981                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
2982                 int j;
2983
2984                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
2985                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
2986                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
2987
2988                 for (j = 0; j < priv->max_opened_tc; j++) {
2989                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
2990
2991                         s->tx_packets    += sq_stats->packets;
2992                         s->tx_bytes      += sq_stats->bytes;
2993                         s->tx_dropped    += sq_stats->dropped;
2994                 }
2995         }
2996         if (priv->tx_ptp_opened) {
2997                 for (i = 0; i < priv->max_opened_tc; i++) {
2998                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
2999
3000                         s->tx_packets    += sq_stats->packets;
3001                         s->tx_bytes      += sq_stats->bytes;
3002                         s->tx_dropped    += sq_stats->dropped;
3003                 }
3004         }
3005         if (priv->rx_ptp_opened) {
3006                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3007
3008                 s->rx_packets   += rq_stats->packets;
3009                 s->rx_bytes     += rq_stats->bytes;
3010                 s->multicast    += rq_stats->mcast_packets;
3011         }
3012 }
3013
3014 void
3015 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3016 {
3017         struct mlx5e_priv *priv = netdev_priv(dev);
3018         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3019
3020         if (!netif_device_present(dev))
3021                 return;
3022
3023         /* In switchdev mode, monitor counters doesn't monitor
3024          * rx/tx stats of 802_3. The update stats mechanism
3025          * should keep the 802_3 layout counters updated
3026          */
3027         if (!mlx5e_monitor_counter_supported(priv) ||
3028             mlx5e_is_uplink_rep(priv)) {
3029                 /* update HW stats in background for next time */
3030                 mlx5e_queue_update_stats(priv);
3031         }
3032
3033         if (mlx5e_is_uplink_rep(priv)) {
3034                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3035
3036                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3037                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3038                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3039                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3040
3041                 /* vport multicast also counts packets that are dropped due to steering
3042                  * or rx out of buffer
3043                  */
3044                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3045         } else {
3046                 mlx5e_fold_sw_stats64(priv, stats);
3047         }
3048
3049         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3050
3051         stats->rx_length_errors =
3052                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3053                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3054                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3055         stats->rx_crc_errors =
3056                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3057         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3058         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3059         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3060                            stats->rx_frame_errors;
3061         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3062 }
3063
3064 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3065 {
3066         if (mlx5e_is_uplink_rep(priv))
3067                 return; /* no rx mode for uplink rep */
3068
3069         queue_work(priv->wq, &priv->set_rx_mode_work);
3070 }
3071
3072 static void mlx5e_set_rx_mode(struct net_device *dev)
3073 {
3074         struct mlx5e_priv *priv = netdev_priv(dev);
3075
3076         mlx5e_nic_set_rx_mode(priv);
3077 }
3078
3079 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3080 {
3081         struct mlx5e_priv *priv = netdev_priv(netdev);
3082         struct sockaddr *saddr = addr;
3083
3084         if (!is_valid_ether_addr(saddr->sa_data))
3085                 return -EADDRNOTAVAIL;
3086
3087         netif_addr_lock_bh(netdev);
3088         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3089         netif_addr_unlock_bh(netdev);
3090
3091         mlx5e_nic_set_rx_mode(priv);
3092
3093         return 0;
3094 }
3095
3096 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3097         do {                                            \
3098                 if (enable)                             \
3099                         *features |= feature;           \
3100                 else                                    \
3101                         *features &= ~feature;          \
3102         } while (0)
3103
3104 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3105
3106 static int set_feature_lro(struct net_device *netdev, bool enable)
3107 {
3108         struct mlx5e_priv *priv = netdev_priv(netdev);
3109         struct mlx5_core_dev *mdev = priv->mdev;
3110         struct mlx5e_params *cur_params;
3111         struct mlx5e_params new_params;
3112         bool reset = true;
3113         int err = 0;
3114
3115         mutex_lock(&priv->state_lock);
3116
3117         if (enable && priv->xsk.refcnt) {
3118                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3119                             priv->xsk.refcnt);
3120                 err = -EINVAL;
3121                 goto out;
3122         }
3123
3124         cur_params = &priv->channels.params;
3125         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3126                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3127                 err = -EINVAL;
3128                 goto out;
3129         }
3130
3131         new_params = *cur_params;
3132         new_params.lro_en = enable;
3133
3134         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3135                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3136                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3137                         reset = false;
3138         }
3139
3140         err = mlx5e_safe_switch_params(priv, &new_params,
3141                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3142 out:
3143         mutex_unlock(&priv->state_lock);
3144         return err;
3145 }
3146
3147 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3148 {
3149         struct mlx5e_priv *priv = netdev_priv(netdev);
3150
3151         if (enable)
3152                 mlx5e_enable_cvlan_filter(priv);
3153         else
3154                 mlx5e_disable_cvlan_filter(priv);
3155
3156         return 0;
3157 }
3158
3159 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3160 {
3161         struct mlx5e_priv *priv = netdev_priv(netdev);
3162
3163 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3164         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3165                 netdev_err(netdev,
3166                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3167                 return -EINVAL;
3168         }
3169 #endif
3170
3171         if (!enable && priv->htb.maj_id) {
3172                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3173                 return -EINVAL;
3174         }
3175
3176         return 0;
3177 }
3178
3179 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3180 {
3181         struct mlx5e_priv *priv = netdev_priv(netdev);
3182         struct mlx5_core_dev *mdev = priv->mdev;
3183
3184         return mlx5_set_port_fcs(mdev, !enable);
3185 }
3186
3187 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3188 {
3189         struct mlx5e_priv *priv = netdev_priv(netdev);
3190         int err;
3191
3192         mutex_lock(&priv->state_lock);
3193
3194         priv->channels.params.scatter_fcs_en = enable;
3195         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3196         if (err)
3197                 priv->channels.params.scatter_fcs_en = !enable;
3198
3199         mutex_unlock(&priv->state_lock);
3200
3201         return err;
3202 }
3203
3204 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3205 {
3206         struct mlx5e_priv *priv = netdev_priv(netdev);
3207         int err = 0;
3208
3209         mutex_lock(&priv->state_lock);
3210
3211         priv->channels.params.vlan_strip_disable = !enable;
3212         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3213                 goto unlock;
3214
3215         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3216         if (err)
3217                 priv->channels.params.vlan_strip_disable = enable;
3218
3219 unlock:
3220         mutex_unlock(&priv->state_lock);
3221
3222         return err;
3223 }
3224
3225 #ifdef CONFIG_MLX5_EN_ARFS
3226 static int set_feature_arfs(struct net_device *netdev, bool enable)
3227 {
3228         struct mlx5e_priv *priv = netdev_priv(netdev);
3229         int err;
3230
3231         if (enable)
3232                 err = mlx5e_arfs_enable(priv);
3233         else
3234                 err = mlx5e_arfs_disable(priv);
3235
3236         return err;
3237 }
3238 #endif
3239
3240 static int mlx5e_handle_feature(struct net_device *netdev,
3241                                 netdev_features_t *features,
3242                                 netdev_features_t wanted_features,
3243                                 netdev_features_t feature,
3244                                 mlx5e_feature_handler feature_handler)
3245 {
3246         netdev_features_t changes = wanted_features ^ netdev->features;
3247         bool enable = !!(wanted_features & feature);
3248         int err;
3249
3250         if (!(changes & feature))
3251                 return 0;
3252
3253         err = feature_handler(netdev, enable);
3254         if (err) {
3255                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3256                            enable ? "Enable" : "Disable", &feature, err);
3257                 return err;
3258         }
3259
3260         MLX5E_SET_FEATURE(features, feature, enable);
3261         return 0;
3262 }
3263
3264 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3265 {
3266         netdev_features_t oper_features = netdev->features;
3267         int err = 0;
3268
3269 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3270         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3271
3272         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3273         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3274                                     set_feature_cvlan_filter);
3275         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3276         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3277         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3278         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3279 #ifdef CONFIG_MLX5_EN_ARFS
3280         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3281 #endif
3282         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3283
3284         if (err) {
3285                 netdev->features = oper_features;
3286                 return -EINVAL;
3287         }
3288
3289         return 0;
3290 }
3291
3292 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3293                                                        netdev_features_t features)
3294 {
3295         features &= ~NETIF_F_HW_TLS_RX;
3296         if (netdev->features & NETIF_F_HW_TLS_RX)
3297                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3298
3299         features &= ~NETIF_F_HW_TLS_TX;
3300         if (netdev->features & NETIF_F_HW_TLS_TX)
3301                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3302
3303         features &= ~NETIF_F_NTUPLE;
3304         if (netdev->features & NETIF_F_NTUPLE)
3305                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3306
3307         return features;
3308 }
3309
3310 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3311                                             netdev_features_t features)
3312 {
3313         struct mlx5e_priv *priv = netdev_priv(netdev);
3314         struct mlx5e_params *params;
3315
3316         mutex_lock(&priv->state_lock);
3317         params = &priv->channels.params;
3318         if (!priv->fs.vlan ||
3319             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3320                 /* HW strips the outer C-tag header, this is a problem
3321                  * for S-tag traffic.
3322                  */
3323                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3324                 if (!params->vlan_strip_disable)
3325                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3326         }
3327
3328         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3329                 if (features & NETIF_F_LRO) {
3330                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3331                         features &= ~NETIF_F_LRO;
3332                 }
3333         }
3334
3335         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3336                 features &= ~NETIF_F_RXHASH;
3337                 if (netdev->features & NETIF_F_RXHASH)
3338                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3339         }
3340
3341         if (mlx5e_is_uplink_rep(priv))
3342                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3343
3344         mutex_unlock(&priv->state_lock);
3345
3346         return features;
3347 }
3348
3349 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3350                                    struct mlx5e_channels *chs,
3351                                    struct mlx5e_params *new_params,
3352                                    struct mlx5_core_dev *mdev)
3353 {
3354         u16 ix;
3355
3356         for (ix = 0; ix < chs->params.num_channels; ix++) {
3357                 struct xsk_buff_pool *xsk_pool =
3358                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3359                 struct mlx5e_xsk_param xsk;
3360
3361                 if (!xsk_pool)
3362                         continue;
3363
3364                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3365
3366                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3367                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3368                         int max_mtu_frame, max_mtu_page, max_mtu;
3369
3370                         /* Two criteria must be met:
3371                          * 1. HW MTU + all headrooms <= XSK frame size.
3372                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3373                          */
3374                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3375                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3376                         max_mtu = min(max_mtu_frame, max_mtu_page);
3377
3378                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3379                                    new_params->sw_mtu, ix, max_mtu);
3380                         return false;
3381                 }
3382         }
3383
3384         return true;
3385 }
3386
3387 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3388                      mlx5e_fp_preactivate preactivate)
3389 {
3390         struct mlx5e_priv *priv = netdev_priv(netdev);
3391         struct mlx5e_params new_params;
3392         struct mlx5e_params *params;
3393         bool reset = true;
3394         int err = 0;
3395
3396         mutex_lock(&priv->state_lock);
3397
3398         params = &priv->channels.params;
3399
3400         new_params = *params;
3401         new_params.sw_mtu = new_mtu;
3402         err = mlx5e_validate_params(priv->mdev, &new_params);
3403         if (err)
3404                 goto out;
3405
3406         if (params->xdp_prog &&
3407             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3408                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3409                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3410                 err = -EINVAL;
3411                 goto out;
3412         }
3413
3414         if (priv->xsk.refcnt &&
3415             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3416                                     &new_params, priv->mdev)) {
3417                 err = -EINVAL;
3418                 goto out;
3419         }
3420
3421         if (params->lro_en)
3422                 reset = false;
3423
3424         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3425                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3426                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3427                                                                   &new_params, NULL);
3428                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3429                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3430
3431                 /* Always reset in linear mode - hw_mtu is used in data path.
3432                  * Check that the mode was non-linear and didn't change.
3433                  * If XSK is active, XSK RQs are linear.
3434                  */
3435                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3436                     ppw_old == ppw_new)
3437                         reset = false;
3438         }
3439
3440         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3441
3442 out:
3443         netdev->mtu = params->sw_mtu;
3444         mutex_unlock(&priv->state_lock);
3445         return err;
3446 }
3447
3448 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3449 {
3450         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3451 }
3452
3453 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3454 {
3455         bool set  = *(bool *)ctx;
3456
3457         return mlx5e_ptp_rx_manage_fs(priv, set);
3458 }
3459
3460 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3461 {
3462         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3463         int err;
3464
3465         if (!rx_filter)
3466                 /* Reset CQE compression to Admin default */
3467                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3468
3469         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3470                 return 0;
3471
3472         /* Disable CQE compression */
3473         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3474         err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3475         if (err)
3476                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3477
3478         return err;
3479 }
3480
3481 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3482 {
3483         struct mlx5e_params new_params;
3484
3485         if (ptp_rx == priv->channels.params.ptp_rx)
3486                 return 0;
3487
3488         new_params = priv->channels.params;
3489         new_params.ptp_rx = ptp_rx;
3490         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3491                                         &new_params.ptp_rx, true);
3492 }
3493
3494 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3495 {
3496         struct hwtstamp_config config;
3497         bool rx_cqe_compress_def;
3498         bool ptp_rx;
3499         int err;
3500
3501         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3502             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3503                 return -EOPNOTSUPP;
3504
3505         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3506                 return -EFAULT;
3507
3508         /* TX HW timestamp */
3509         switch (config.tx_type) {
3510         case HWTSTAMP_TX_OFF:
3511         case HWTSTAMP_TX_ON:
3512                 break;
3513         default:
3514                 return -ERANGE;
3515         }
3516
3517         mutex_lock(&priv->state_lock);
3518         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3519
3520         /* RX HW timestamp */
3521         switch (config.rx_filter) {
3522         case HWTSTAMP_FILTER_NONE:
3523                 ptp_rx = false;
3524                 break;
3525         case HWTSTAMP_FILTER_ALL:
3526         case HWTSTAMP_FILTER_SOME:
3527         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3528         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3529         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3530         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3531         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3532         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3533         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3534         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3535         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3536         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3537         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3538         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3539         case HWTSTAMP_FILTER_NTP_ALL:
3540                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3541                 /* ptp_rx is set if both HW TS is set and CQE
3542                  * compression is set
3543                  */
3544                 ptp_rx = rx_cqe_compress_def;
3545                 break;
3546         default:
3547                 err = -ERANGE;
3548                 goto err_unlock;
3549         }
3550
3551         if (!priv->profile->rx_ptp_support)
3552                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
3553                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
3554         else
3555                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
3556         if (err)
3557                 goto err_unlock;
3558
3559         memcpy(&priv->tstamp, &config, sizeof(config));
3560         mutex_unlock(&priv->state_lock);
3561
3562         /* might need to fix some features */
3563         netdev_update_features(priv->netdev);
3564
3565         return copy_to_user(ifr->ifr_data, &config,
3566                             sizeof(config)) ? -EFAULT : 0;
3567 err_unlock:
3568         mutex_unlock(&priv->state_lock);
3569         return err;
3570 }
3571
3572 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3573 {
3574         struct hwtstamp_config *cfg = &priv->tstamp;
3575
3576         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3577                 return -EOPNOTSUPP;
3578
3579         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3580 }
3581
3582 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3583 {
3584         struct mlx5e_priv *priv = netdev_priv(dev);
3585
3586         switch (cmd) {
3587         case SIOCSHWTSTAMP:
3588                 return mlx5e_hwstamp_set(priv, ifr);
3589         case SIOCGHWTSTAMP:
3590                 return mlx5e_hwstamp_get(priv, ifr);
3591         default:
3592                 return -EOPNOTSUPP;
3593         }
3594 }
3595
3596 #ifdef CONFIG_MLX5_ESWITCH
3597 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3598 {
3599         struct mlx5e_priv *priv = netdev_priv(dev);
3600         struct mlx5_core_dev *mdev = priv->mdev;
3601
3602         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3603 }
3604
3605 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3606                              __be16 vlan_proto)
3607 {
3608         struct mlx5e_priv *priv = netdev_priv(dev);
3609         struct mlx5_core_dev *mdev = priv->mdev;
3610
3611         if (vlan_proto != htons(ETH_P_8021Q))
3612                 return -EPROTONOSUPPORT;
3613
3614         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3615                                            vlan, qos);
3616 }
3617
3618 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3619 {
3620         struct mlx5e_priv *priv = netdev_priv(dev);
3621         struct mlx5_core_dev *mdev = priv->mdev;
3622
3623         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3624 }
3625
3626 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3627 {
3628         struct mlx5e_priv *priv = netdev_priv(dev);
3629         struct mlx5_core_dev *mdev = priv->mdev;
3630
3631         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3632 }
3633
3634 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3635                       int max_tx_rate)
3636 {
3637         struct mlx5e_priv *priv = netdev_priv(dev);
3638         struct mlx5_core_dev *mdev = priv->mdev;
3639
3640         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3641                                            max_tx_rate, min_tx_rate);
3642 }
3643
3644 static int mlx5_vport_link2ifla(u8 esw_link)
3645 {
3646         switch (esw_link) {
3647         case MLX5_VPORT_ADMIN_STATE_DOWN:
3648                 return IFLA_VF_LINK_STATE_DISABLE;
3649         case MLX5_VPORT_ADMIN_STATE_UP:
3650                 return IFLA_VF_LINK_STATE_ENABLE;
3651         }
3652         return IFLA_VF_LINK_STATE_AUTO;
3653 }
3654
3655 static int mlx5_ifla_link2vport(u8 ifla_link)
3656 {
3657         switch (ifla_link) {
3658         case IFLA_VF_LINK_STATE_DISABLE:
3659                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3660         case IFLA_VF_LINK_STATE_ENABLE:
3661                 return MLX5_VPORT_ADMIN_STATE_UP;
3662         }
3663         return MLX5_VPORT_ADMIN_STATE_AUTO;
3664 }
3665
3666 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3667                                    int link_state)
3668 {
3669         struct mlx5e_priv *priv = netdev_priv(dev);
3670         struct mlx5_core_dev *mdev = priv->mdev;
3671
3672         if (mlx5e_is_uplink_rep(priv))
3673                 return -EOPNOTSUPP;
3674
3675         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3676                                             mlx5_ifla_link2vport(link_state));
3677 }
3678
3679 int mlx5e_get_vf_config(struct net_device *dev,
3680                         int vf, struct ifla_vf_info *ivi)
3681 {
3682         struct mlx5e_priv *priv = netdev_priv(dev);
3683         struct mlx5_core_dev *mdev = priv->mdev;
3684         int err;
3685
3686         if (!netif_device_present(dev))
3687                 return -EOPNOTSUPP;
3688
3689         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3690         if (err)
3691                 return err;
3692         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3693         return 0;
3694 }
3695
3696 int mlx5e_get_vf_stats(struct net_device *dev,
3697                        int vf, struct ifla_vf_stats *vf_stats)
3698 {
3699         struct mlx5e_priv *priv = netdev_priv(dev);
3700         struct mlx5_core_dev *mdev = priv->mdev;
3701
3702         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3703                                             vf_stats);
3704 }
3705
3706 static bool
3707 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
3708 {
3709         struct mlx5e_priv *priv = netdev_priv(dev);
3710
3711         if (!netif_device_present(dev))
3712                 return false;
3713
3714         if (!mlx5e_is_uplink_rep(priv))
3715                 return false;
3716
3717         return mlx5e_rep_has_offload_stats(dev, attr_id);
3718 }
3719
3720 static int
3721 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
3722                         void *sp)
3723 {
3724         struct mlx5e_priv *priv = netdev_priv(dev);
3725
3726         if (!mlx5e_is_uplink_rep(priv))
3727                 return -EOPNOTSUPP;
3728
3729         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
3730 }
3731 #endif
3732
3733 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
3734 {
3735         switch (proto_type) {
3736         case IPPROTO_GRE:
3737                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
3738         case IPPROTO_IPIP:
3739         case IPPROTO_IPV6:
3740                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
3741                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
3742         default:
3743                 return false;
3744         }
3745 }
3746
3747 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
3748                                                            struct sk_buff *skb)
3749 {
3750         switch (skb->inner_protocol) {
3751         case htons(ETH_P_IP):
3752         case htons(ETH_P_IPV6):
3753         case htons(ETH_P_TEB):
3754                 return true;
3755         case htons(ETH_P_MPLS_UC):
3756         case htons(ETH_P_MPLS_MC):
3757                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
3758         }
3759         return false;
3760 }
3761
3762 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3763                                                      struct sk_buff *skb,
3764                                                      netdev_features_t features)
3765 {
3766         unsigned int offset = 0;
3767         struct udphdr *udph;
3768         u8 proto;
3769         u16 port;
3770
3771         switch (vlan_get_protocol(skb)) {
3772         case htons(ETH_P_IP):
3773                 proto = ip_hdr(skb)->protocol;
3774                 break;
3775         case htons(ETH_P_IPV6):
3776                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3777                 break;
3778         default:
3779                 goto out;
3780         }
3781
3782         switch (proto) {
3783         case IPPROTO_GRE:
3784                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
3785                         return features;
3786                 break;
3787         case IPPROTO_IPIP:
3788         case IPPROTO_IPV6:
3789                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
3790                         return features;
3791                 break;
3792         case IPPROTO_UDP:
3793                 udph = udp_hdr(skb);
3794                 port = be16_to_cpu(udph->dest);
3795
3796                 /* Verify if UDP port is being offloaded by HW */
3797                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
3798                         return features;
3799
3800 #if IS_ENABLED(CONFIG_GENEVE)
3801                 /* Support Geneve offload for default UDP port */
3802                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
3803                         return features;
3804 #endif
3805                 break;
3806 #ifdef CONFIG_MLX5_EN_IPSEC
3807         case IPPROTO_ESP:
3808                 return mlx5e_ipsec_feature_check(skb, features);
3809 #endif
3810         }
3811
3812 out:
3813         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3814         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3815 }
3816
3817 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3818                                        struct net_device *netdev,
3819                                        netdev_features_t features)
3820 {
3821         struct mlx5e_priv *priv = netdev_priv(netdev);
3822
3823         features = vlan_features_check(skb, features);
3824         features = vxlan_features_check(skb, features);
3825
3826         /* Validate if the tunneled packet is being offloaded by HW */
3827         if (skb->encapsulation &&
3828             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3829                 return mlx5e_tunnel_features_check(priv, skb, features);
3830
3831         return features;
3832 }
3833
3834 static void mlx5e_tx_timeout_work(struct work_struct *work)
3835 {
3836         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3837                                                tx_timeout_work);
3838         struct net_device *netdev = priv->netdev;
3839         int i;
3840
3841         rtnl_lock();
3842         mutex_lock(&priv->state_lock);
3843
3844         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3845                 goto unlock;
3846
3847         for (i = 0; i < netdev->real_num_tx_queues; i++) {
3848                 struct netdev_queue *dev_queue =
3849                         netdev_get_tx_queue(netdev, i);
3850                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3851
3852                 if (!netif_xmit_stopped(dev_queue))
3853                         continue;
3854
3855                 if (mlx5e_reporter_tx_timeout(sq))
3856                 /* break if tried to reopened channels */
3857                         break;
3858         }
3859
3860 unlock:
3861         mutex_unlock(&priv->state_lock);
3862         rtnl_unlock();
3863 }
3864
3865 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
3866 {
3867         struct mlx5e_priv *priv = netdev_priv(dev);
3868
3869         netdev_err(dev, "TX timeout detected\n");
3870         queue_work(priv->wq, &priv->tx_timeout_work);
3871 }
3872
3873 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
3874 {
3875         struct net_device *netdev = priv->netdev;
3876         struct mlx5e_params new_params;
3877
3878         if (priv->channels.params.lro_en) {
3879                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3880                 return -EINVAL;
3881         }
3882
3883         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
3884                 netdev_warn(netdev,
3885                             "XDP is not available on Innova cards with IPsec support\n");
3886                 return -EINVAL;
3887         }
3888
3889         new_params = priv->channels.params;
3890         new_params.xdp_prog = prog;
3891
3892         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3893          * the XDP program.
3894          */
3895         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3896                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
3897                             new_params.sw_mtu,
3898                             mlx5e_xdp_max_mtu(&new_params, NULL));
3899                 return -EINVAL;
3900         }
3901
3902         return 0;
3903 }
3904
3905 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
3906 {
3907         struct bpf_prog *old_prog;
3908
3909         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
3910                                        lockdep_is_held(&rq->priv->state_lock));
3911         if (old_prog)
3912                 bpf_prog_put(old_prog);
3913 }
3914
3915 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3916 {
3917         struct mlx5e_priv *priv = netdev_priv(netdev);
3918         struct mlx5e_params new_params;
3919         struct bpf_prog *old_prog;
3920         int err = 0;
3921         bool reset;
3922         int i;
3923
3924         mutex_lock(&priv->state_lock);
3925
3926         if (prog) {
3927                 err = mlx5e_xdp_allowed(priv, prog);
3928                 if (err)
3929                         goto unlock;
3930         }
3931
3932         /* no need for full reset when exchanging programs */
3933         reset = (!priv->channels.params.xdp_prog || !prog);
3934
3935         new_params = priv->channels.params;
3936         new_params.xdp_prog = prog;
3937         if (reset)
3938                 mlx5e_set_rq_type(priv->mdev, &new_params);
3939         old_prog = priv->channels.params.xdp_prog;
3940
3941         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3942         if (err)
3943                 goto unlock;
3944
3945         if (old_prog)
3946                 bpf_prog_put(old_prog);
3947
3948         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3949                 goto unlock;
3950
3951         /* exchanging programs w/o reset, we update ref counts on behalf
3952          * of the channels RQs here.
3953          */
3954         bpf_prog_add(prog, priv->channels.num);
3955         for (i = 0; i < priv->channels.num; i++) {
3956                 struct mlx5e_channel *c = priv->channels.c[i];
3957
3958                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
3959                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
3960                         bpf_prog_inc(prog);
3961                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
3962                 }
3963         }
3964
3965 unlock:
3966         mutex_unlock(&priv->state_lock);
3967         return err;
3968 }
3969
3970 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3971 {
3972         switch (xdp->command) {
3973         case XDP_SETUP_PROG:
3974                 return mlx5e_xdp_set(dev, xdp->prog);
3975         case XDP_SETUP_XSK_POOL:
3976                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
3977                                             xdp->xsk.queue_id);
3978         default:
3979                 return -EINVAL;
3980         }
3981 }
3982
3983 #ifdef CONFIG_MLX5_ESWITCH
3984 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
3985                                 struct net_device *dev, u32 filter_mask,
3986                                 int nlflags)
3987 {
3988         struct mlx5e_priv *priv = netdev_priv(dev);
3989         struct mlx5_core_dev *mdev = priv->mdev;
3990         u8 mode, setting;
3991         int err;
3992
3993         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
3994         if (err)
3995                 return err;
3996         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
3997         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
3998                                        mode,
3999                                        0, 0, nlflags, filter_mask, NULL);
4000 }
4001
4002 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4003                                 u16 flags, struct netlink_ext_ack *extack)
4004 {
4005         struct mlx5e_priv *priv = netdev_priv(dev);
4006         struct mlx5_core_dev *mdev = priv->mdev;
4007         struct nlattr *attr, *br_spec;
4008         u16 mode = BRIDGE_MODE_UNDEF;
4009         u8 setting;
4010         int rem;
4011
4012         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4013         if (!br_spec)
4014                 return -EINVAL;
4015
4016         nla_for_each_nested(attr, br_spec, rem) {
4017                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4018                         continue;
4019
4020                 if (nla_len(attr) < sizeof(mode))
4021                         return -EINVAL;
4022
4023                 mode = nla_get_u16(attr);
4024                 if (mode > BRIDGE_MODE_VEPA)
4025                         return -EINVAL;
4026
4027                 break;
4028         }
4029
4030         if (mode == BRIDGE_MODE_UNDEF)
4031                 return -EINVAL;
4032
4033         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4034         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4035 }
4036 #endif
4037
4038 const struct net_device_ops mlx5e_netdev_ops = {
4039         .ndo_open                = mlx5e_open,
4040         .ndo_stop                = mlx5e_close,
4041         .ndo_start_xmit          = mlx5e_xmit,
4042         .ndo_setup_tc            = mlx5e_setup_tc,
4043         .ndo_select_queue        = mlx5e_select_queue,
4044         .ndo_get_stats64         = mlx5e_get_stats,
4045         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4046         .ndo_set_mac_address     = mlx5e_set_mac,
4047         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4048         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4049         .ndo_set_features        = mlx5e_set_features,
4050         .ndo_fix_features        = mlx5e_fix_features,
4051         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4052         .ndo_eth_ioctl            = mlx5e_ioctl,
4053         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4054         .ndo_features_check      = mlx5e_features_check,
4055         .ndo_tx_timeout          = mlx5e_tx_timeout,
4056         .ndo_bpf                 = mlx5e_xdp,
4057         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4058         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4059 #ifdef CONFIG_MLX5_EN_ARFS
4060         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4061 #endif
4062 #ifdef CONFIG_MLX5_ESWITCH
4063         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4064         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4065
4066         /* SRIOV E-Switch NDOs */
4067         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4068         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4069         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4070         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4071         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4072         .ndo_get_vf_config       = mlx5e_get_vf_config,
4073         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4074         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4075         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4076         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4077 #endif
4078         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4079 };
4080
4081 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4082 {
4083         int i;
4084
4085         /* The supported periods are organized in ascending order */
4086         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4087                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4088                         break;
4089
4090         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4091 }
4092
4093 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4094 {
4095         struct mlx5e_params *params = &priv->channels.params;
4096         struct mlx5_core_dev *mdev = priv->mdev;
4097         u8 rx_cq_period_mode;
4098
4099         priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4100
4101         params->sw_mtu = mtu;
4102         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4103         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4104                                      priv->max_nch);
4105         params->num_tc       = 1;
4106
4107         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4108          * divide by zero if called before first activating channels.
4109          */
4110         priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4111
4112         /* SQ */
4113         params->log_sq_size = is_kdump_kernel() ?
4114                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4115                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4116         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4117
4118         /* XDP SQ */
4119         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4120
4121         /* set CQE compression */
4122         params->rx_cqe_compress_def = false;
4123         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4124             MLX5_CAP_GEN(mdev, vport_group_manager))
4125                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4126
4127         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4128         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4129
4130         /* RQ */
4131         mlx5e_build_rq_params(mdev, params);
4132
4133         /* HW LRO */
4134         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4135             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4136                 /* No XSK params: checking the availability of striding RQ in general. */
4137                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4138                         params->lro_en = !slow_pci_heuristic(mdev);
4139         }
4140         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4141
4142         /* CQ moderation params */
4143         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4144                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4145                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4146         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4147         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4148         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4149         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4150
4151         /* TX inline */
4152         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4153
4154         params->tunneled_offload_en = mlx5e_tunnel_inner_ft_supported(mdev);
4155
4156         /* AF_XDP */
4157         params->xsk = xsk;
4158
4159         /* Do not update netdev->features directly in here
4160          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4161          * To update netdev->features please modify mlx5e_fix_features()
4162          */
4163 }
4164
4165 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4166 {
4167         struct mlx5e_priv *priv = netdev_priv(netdev);
4168
4169         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4170         if (is_zero_ether_addr(netdev->dev_addr) &&
4171             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4172                 eth_hw_addr_random(netdev);
4173                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4174         }
4175 }
4176
4177 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4178                                 unsigned int entry, struct udp_tunnel_info *ti)
4179 {
4180         struct mlx5e_priv *priv = netdev_priv(netdev);
4181
4182         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4183 }
4184
4185 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4186                                   unsigned int entry, struct udp_tunnel_info *ti)
4187 {
4188         struct mlx5e_priv *priv = netdev_priv(netdev);
4189
4190         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4191 }
4192
4193 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4194 {
4195         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4196                 return;
4197
4198         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4199         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4200         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4201                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4202         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4203         /* Don't count the space hard-coded to the IANA port */
4204         priv->nic_info.tables[0].n_entries =
4205                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4206
4207         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4208 }
4209
4210 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4211 {
4212         int tt;
4213
4214         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4215                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4216                         return true;
4217         }
4218         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4219 }
4220
4221 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4222 {
4223         struct mlx5e_priv *priv = netdev_priv(netdev);
4224         struct mlx5_core_dev *mdev = priv->mdev;
4225         bool fcs_supported;
4226         bool fcs_enabled;
4227
4228         SET_NETDEV_DEV(netdev, mdev->device);
4229
4230         netdev->netdev_ops = &mlx5e_netdev_ops;
4231
4232         mlx5e_dcbnl_build_netdev(netdev);
4233
4234         netdev->watchdog_timeo    = 15 * HZ;
4235
4236         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4237
4238         netdev->vlan_features    |= NETIF_F_SG;
4239         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4240         netdev->vlan_features    |= NETIF_F_GRO;
4241         netdev->vlan_features    |= NETIF_F_TSO;
4242         netdev->vlan_features    |= NETIF_F_TSO6;
4243         netdev->vlan_features    |= NETIF_F_RXCSUM;
4244         netdev->vlan_features    |= NETIF_F_RXHASH;
4245
4246         netdev->mpls_features    |= NETIF_F_SG;
4247         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4248         netdev->mpls_features    |= NETIF_F_TSO;
4249         netdev->mpls_features    |= NETIF_F_TSO6;
4250
4251         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4252         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4253
4254         /* Tunneled LRO is not supported in the driver, and the same RQs are
4255          * shared between inner and outer TIRs, so the driver can't disable LRO
4256          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4257          * block LRO altogether if the firmware declares tunneled LRO support.
4258          */
4259         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4260             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4261             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4262             mlx5e_check_fragmented_striding_rq_cap(mdev))
4263                 netdev->vlan_features    |= NETIF_F_LRO;
4264
4265         netdev->hw_features       = netdev->vlan_features;
4266         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4267         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4268         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4269         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4270
4271         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4272                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4273                 netdev->hw_enc_features |= NETIF_F_TSO;
4274                 netdev->hw_enc_features |= NETIF_F_TSO6;
4275                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4276         }
4277
4278         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4279                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4280                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4281                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4282         }
4283
4284         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4285                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4286                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4287                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4288         }
4289
4290         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4291                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4292                                        NETIF_F_GSO_IPXIP6;
4293                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4294                                            NETIF_F_GSO_IPXIP6;
4295                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4296                                                 NETIF_F_GSO_IPXIP6;
4297         }
4298
4299         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4300         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4301         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4302         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4303
4304         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4305
4306         if (fcs_supported)
4307                 netdev->hw_features |= NETIF_F_RXALL;
4308
4309         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4310                 netdev->hw_features |= NETIF_F_RXFCS;
4311
4312         if (mlx5_qos_is_supported(mdev))
4313                 netdev->hw_features |= NETIF_F_HW_TC;
4314
4315         netdev->features          = netdev->hw_features;
4316
4317         /* Defaults */
4318         if (fcs_enabled)
4319                 netdev->features  &= ~NETIF_F_RXALL;
4320         netdev->features  &= ~NETIF_F_LRO;
4321         netdev->features  &= ~NETIF_F_RXFCS;
4322
4323 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4324         if (FT_CAP(flow_modify_en) &&
4325             FT_CAP(modify_root) &&
4326             FT_CAP(identified_miss_table_mode) &&
4327             FT_CAP(flow_table_modify)) {
4328 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4329                 netdev->hw_features      |= NETIF_F_HW_TC;
4330 #endif
4331 #ifdef CONFIG_MLX5_EN_ARFS
4332                 netdev->hw_features      |= NETIF_F_NTUPLE;
4333 #endif
4334         }
4335
4336         netdev->features         |= NETIF_F_HIGHDMA;
4337         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4338
4339         netdev->priv_flags       |= IFF_UNICAST_FLT;
4340
4341         mlx5e_set_netdev_dev_addr(netdev);
4342         mlx5e_ipsec_build_netdev(priv);
4343         mlx5e_tls_build_netdev(priv);
4344 }
4345
4346 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4347 {
4348         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4349         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4350         struct mlx5_core_dev *mdev = priv->mdev;
4351         int err;
4352
4353         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4354         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4355         if (!err)
4356                 priv->q_counter =
4357                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4358
4359         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4360         if (!err)
4361                 priv->drop_rq_q_counter =
4362                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4363 }
4364
4365 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4366 {
4367         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4368
4369         MLX5_SET(dealloc_q_counter_in, in, opcode,
4370                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4371         if (priv->q_counter) {
4372                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4373                          priv->q_counter);
4374                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4375         }
4376
4377         if (priv->drop_rq_q_counter) {
4378                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4379                          priv->drop_rq_q_counter);
4380                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4381         }
4382 }
4383
4384 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4385                           struct net_device *netdev)
4386 {
4387         struct mlx5e_priv *priv = netdev_priv(netdev);
4388         int err;
4389
4390         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4391         mlx5e_vxlan_set_netdev_info(priv);
4392
4393         mlx5e_timestamp_init(priv);
4394
4395         err = mlx5e_ipsec_init(priv);
4396         if (err)
4397                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4398
4399         err = mlx5e_tls_init(priv);
4400         if (err)
4401                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4402
4403         mlx5e_health_create_reporters(priv);
4404         return 0;
4405 }
4406
4407 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4408 {
4409         mlx5e_health_destroy_reporters(priv);
4410         mlx5e_tls_cleanup(priv);
4411         mlx5e_ipsec_cleanup(priv);
4412 }
4413
4414 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4415 {
4416         struct mlx5_core_dev *mdev = priv->mdev;
4417         enum mlx5e_rx_res_features features;
4418         struct mlx5e_lro_param lro_param;
4419         int err;
4420
4421         priv->rx_res = mlx5e_rx_res_alloc();
4422         if (!priv->rx_res)
4423                 return -ENOMEM;
4424
4425         mlx5e_create_q_counters(priv);
4426
4427         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4428         if (err) {
4429                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4430                 goto err_destroy_q_counters;
4431         }
4432
4433         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4434         if (priv->channels.params.tunneled_offload_en)
4435                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4436         lro_param = mlx5e_get_lro_param(&priv->channels.params);
4437         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4438                                 priv->max_nch, priv->drop_rq.rqn, &lro_param,
4439                                 priv->channels.params.num_channels);
4440         if (err)
4441                 goto err_close_drop_rq;
4442
4443         err = mlx5e_create_flow_steering(priv);
4444         if (err) {
4445                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4446                 goto err_destroy_rx_res;
4447         }
4448
4449         err = mlx5e_tc_nic_init(priv);
4450         if (err)
4451                 goto err_destroy_flow_steering;
4452
4453         err = mlx5e_accel_init_rx(priv);
4454         if (err)
4455                 goto err_tc_nic_cleanup;
4456
4457 #ifdef CONFIG_MLX5_EN_ARFS
4458         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4459 #endif
4460
4461         return 0;
4462
4463 err_tc_nic_cleanup:
4464         mlx5e_tc_nic_cleanup(priv);
4465 err_destroy_flow_steering:
4466         mlx5e_destroy_flow_steering(priv);
4467 err_destroy_rx_res:
4468         mlx5e_rx_res_destroy(priv->rx_res);
4469 err_close_drop_rq:
4470         mlx5e_close_drop_rq(&priv->drop_rq);
4471 err_destroy_q_counters:
4472         mlx5e_destroy_q_counters(priv);
4473         mlx5e_rx_res_free(priv->rx_res);
4474         priv->rx_res = NULL;
4475         return err;
4476 }
4477
4478 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4479 {
4480         mlx5e_accel_cleanup_rx(priv);
4481         mlx5e_tc_nic_cleanup(priv);
4482         mlx5e_destroy_flow_steering(priv);
4483         mlx5e_rx_res_destroy(priv->rx_res);
4484         mlx5e_close_drop_rq(&priv->drop_rq);
4485         mlx5e_destroy_q_counters(priv);
4486         mlx5e_rx_res_free(priv->rx_res);
4487         priv->rx_res = NULL;
4488 }
4489
4490 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4491 {
4492         int err;
4493
4494         err = mlx5e_create_tises(priv);
4495         if (err) {
4496                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4497                 return err;
4498         }
4499
4500         mlx5e_dcbnl_initialize(priv);
4501         return 0;
4502 }
4503
4504 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4505 {
4506         struct net_device *netdev = priv->netdev;
4507         struct mlx5_core_dev *mdev = priv->mdev;
4508
4509         mlx5e_init_l2_addr(priv);
4510
4511         /* Marking the link as currently not needed by the Driver */
4512         if (!netif_running(netdev))
4513                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
4514
4515         mlx5e_set_netdev_mtu_boundaries(priv);
4516         mlx5e_set_dev_port_mtu(priv);
4517
4518         mlx5_lag_add_netdev(mdev, netdev);
4519
4520         mlx5e_enable_async_events(priv);
4521         mlx5e_enable_blocking_events(priv);
4522         if (mlx5e_monitor_counter_supported(priv))
4523                 mlx5e_monitor_counter_init(priv);
4524
4525         mlx5e_hv_vhca_stats_create(priv);
4526         if (netdev->reg_state != NETREG_REGISTERED)
4527                 return;
4528         mlx5e_dcbnl_init_app(priv);
4529
4530         mlx5e_nic_set_rx_mode(priv);
4531
4532         rtnl_lock();
4533         if (netif_running(netdev))
4534                 mlx5e_open(netdev);
4535         udp_tunnel_nic_reset_ntf(priv->netdev);
4536         netif_device_attach(netdev);
4537         rtnl_unlock();
4538 }
4539
4540 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4541 {
4542         struct mlx5_core_dev *mdev = priv->mdev;
4543
4544         if (priv->netdev->reg_state == NETREG_REGISTERED)
4545                 mlx5e_dcbnl_delete_app(priv);
4546
4547         rtnl_lock();
4548         if (netif_running(priv->netdev))
4549                 mlx5e_close(priv->netdev);
4550         netif_device_detach(priv->netdev);
4551         rtnl_unlock();
4552
4553         mlx5e_nic_set_rx_mode(priv);
4554
4555         mlx5e_hv_vhca_stats_destroy(priv);
4556         if (mlx5e_monitor_counter_supported(priv))
4557                 mlx5e_monitor_counter_cleanup(priv);
4558
4559         mlx5e_disable_blocking_events(priv);
4560         if (priv->en_trap) {
4561                 mlx5e_deactivate_trap(priv);
4562                 mlx5e_close_trap(priv->en_trap);
4563                 priv->en_trap = NULL;
4564         }
4565         mlx5e_disable_async_events(priv);
4566         mlx5_lag_remove_netdev(mdev, priv->netdev);
4567         mlx5_vxlan_reset_to_default(mdev->vxlan);
4568 }
4569
4570 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
4571 {
4572         return mlx5e_refresh_tirs(priv, false, false);
4573 }
4574
4575 static const struct mlx5e_profile mlx5e_nic_profile = {
4576         .init              = mlx5e_nic_init,
4577         .cleanup           = mlx5e_nic_cleanup,
4578         .init_rx           = mlx5e_init_nic_rx,
4579         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4580         .init_tx           = mlx5e_init_nic_tx,
4581         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4582         .enable            = mlx5e_nic_enable,
4583         .disable           = mlx5e_nic_disable,
4584         .update_rx         = mlx5e_update_nic_rx,
4585         .update_stats      = mlx5e_stats_update_ndo_stats,
4586         .update_carrier    = mlx5e_update_carrier,
4587         .rx_handlers       = &mlx5e_rx_handlers_nic,
4588         .max_tc            = MLX5E_MAX_NUM_TC,
4589         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
4590         .stats_grps        = mlx5e_nic_stats_grps,
4591         .stats_grps_num    = mlx5e_nic_stats_grps_num,
4592         .rx_ptp_support    = true,
4593 };
4594
4595 /* mlx5e generic netdev management API (move to en_common.c) */
4596 int mlx5e_priv_init(struct mlx5e_priv *priv,
4597                     struct net_device *netdev,
4598                     struct mlx5_core_dev *mdev)
4599 {
4600         /* priv init */
4601         priv->mdev        = mdev;
4602         priv->netdev      = netdev;
4603         priv->msglevel    = MLX5E_MSG_LEVEL;
4604         priv->max_opened_tc = 1;
4605
4606         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
4607                 return -ENOMEM;
4608
4609         mutex_init(&priv->state_lock);
4610         hash_init(priv->htb.qos_tc2node);
4611         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4612         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4613         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4614         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4615
4616         priv->wq = create_singlethread_workqueue("mlx5e");
4617         if (!priv->wq)
4618                 goto err_free_cpumask;
4619
4620         return 0;
4621
4622 err_free_cpumask:
4623         free_cpumask_var(priv->scratchpad.cpumask);
4624
4625         return -ENOMEM;
4626 }
4627
4628 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
4629 {
4630         int i;
4631
4632         /* bail if change profile failed and also rollback failed */
4633         if (!priv->mdev)
4634                 return;
4635
4636         destroy_workqueue(priv->wq);
4637         free_cpumask_var(priv->scratchpad.cpumask);
4638
4639         for (i = 0; i < priv->htb.max_qos_sqs; i++)
4640                 kfree(priv->htb.qos_sq_stats[i]);
4641         kvfree(priv->htb.qos_sq_stats);
4642
4643         memset(priv, 0, sizeof(*priv));
4644 }
4645
4646 struct net_device *
4647 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
4648 {
4649         struct net_device *netdev;
4650         int err;
4651
4652         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
4653         if (!netdev) {
4654                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4655                 return NULL;
4656         }
4657
4658         err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
4659         if (err) {
4660                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4661                 goto err_free_netdev;
4662         }
4663
4664         netif_carrier_off(netdev);
4665         dev_net_set(netdev, mlx5_core_net(mdev));
4666
4667         return netdev;
4668
4669 err_free_netdev:
4670         free_netdev(netdev);
4671
4672         return NULL;
4673 }
4674
4675 static void mlx5e_update_features(struct net_device *netdev)
4676 {
4677         if (netdev->reg_state != NETREG_REGISTERED)
4678                 return; /* features will be updated on netdev registration */
4679
4680         rtnl_lock();
4681         netdev_update_features(netdev);
4682         rtnl_unlock();
4683 }
4684
4685 static void mlx5e_reset_channels(struct net_device *netdev)
4686 {
4687         netdev_reset_tc(netdev);
4688 }
4689
4690 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4691 {
4692         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
4693         const struct mlx5e_profile *profile = priv->profile;
4694         int max_nch;
4695         int err;
4696
4697         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4698
4699         /* max number of channels may have changed */
4700         max_nch = mlx5e_get_max_num_channels(priv->mdev);
4701         if (priv->channels.params.num_channels > max_nch) {
4702                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
4703                 /* Reducing the number of channels - RXFH has to be reset, and
4704                  * mlx5e_num_channels_changed below will build the RQT.
4705                  */
4706                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
4707                 priv->channels.params.num_channels = max_nch;
4708         }
4709         /* 1. Set the real number of queues in the kernel the first time.
4710          * 2. Set our default XPS cpumask.
4711          * 3. Build the RQT.
4712          *
4713          * rtnl_lock is required by netif_set_real_num_*_queues in case the
4714          * netdev has been registered by this point (if this function was called
4715          * in the reload or resume flow).
4716          */
4717         if (take_rtnl)
4718                 rtnl_lock();
4719         err = mlx5e_num_channels_changed(priv);
4720         if (take_rtnl)
4721                 rtnl_unlock();
4722         if (err)
4723                 goto out;
4724
4725         err = profile->init_tx(priv);
4726         if (err)
4727                 goto out;
4728
4729         err = profile->init_rx(priv);
4730         if (err)
4731                 goto err_cleanup_tx;
4732
4733         if (profile->enable)
4734                 profile->enable(priv);
4735
4736         mlx5e_update_features(priv->netdev);
4737
4738         return 0;
4739
4740 err_cleanup_tx:
4741         profile->cleanup_tx(priv);
4742
4743 out:
4744         mlx5e_reset_channels(priv->netdev);
4745         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4746         cancel_work_sync(&priv->update_stats_work);
4747         return err;
4748 }
4749
4750 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4751 {
4752         const struct mlx5e_profile *profile = priv->profile;
4753
4754         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4755
4756         if (profile->disable)
4757                 profile->disable(priv);
4758         flush_workqueue(priv->wq);
4759
4760         profile->cleanup_rx(priv);
4761         profile->cleanup_tx(priv);
4762         mlx5e_reset_channels(priv->netdev);
4763         cancel_work_sync(&priv->update_stats_work);
4764 }
4765
4766 static int
4767 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
4768                             const struct mlx5e_profile *new_profile, void *new_ppriv)
4769 {
4770         struct mlx5e_priv *priv = netdev_priv(netdev);
4771         int err;
4772
4773         err = mlx5e_priv_init(priv, netdev, mdev);
4774         if (err) {
4775                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4776                 return err;
4777         }
4778         netif_carrier_off(netdev);
4779         priv->profile = new_profile;
4780         priv->ppriv = new_ppriv;
4781         err = new_profile->init(priv->mdev, priv->netdev);
4782         if (err)
4783                 goto priv_cleanup;
4784         err = mlx5e_attach_netdev(priv);
4785         if (err)
4786                 goto profile_cleanup;
4787         return err;
4788
4789 profile_cleanup:
4790         new_profile->cleanup(priv);
4791 priv_cleanup:
4792         mlx5e_priv_cleanup(priv);
4793         return err;
4794 }
4795
4796 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
4797                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
4798 {
4799         unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
4800         const struct mlx5e_profile *orig_profile = priv->profile;
4801         struct net_device *netdev = priv->netdev;
4802         struct mlx5_core_dev *mdev = priv->mdev;
4803         void *orig_ppriv = priv->ppriv;
4804         int err, rollback_err;
4805
4806         /* sanity */
4807         if (new_max_nch != priv->max_nch) {
4808                 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
4809                             __func__);
4810                 return -EINVAL;
4811         }
4812
4813         /* cleanup old profile */
4814         mlx5e_detach_netdev(priv);
4815         priv->profile->cleanup(priv);
4816         mlx5e_priv_cleanup(priv);
4817
4818         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
4819         if (err) { /* roll back to original profile */
4820                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
4821                 goto rollback;
4822         }
4823
4824         return 0;
4825
4826 rollback:
4827         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
4828         if (rollback_err)
4829                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
4830                            __func__, rollback_err);
4831         return err;
4832 }
4833
4834 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
4835 {
4836         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
4837 }
4838
4839 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4840 {
4841         struct net_device *netdev = priv->netdev;
4842
4843         mlx5e_priv_cleanup(priv);
4844         free_netdev(netdev);
4845 }
4846
4847 static int mlx5e_resume(struct auxiliary_device *adev)
4848 {
4849         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
4850         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
4851         struct net_device *netdev = priv->netdev;
4852         struct mlx5_core_dev *mdev = edev->mdev;
4853         int err;
4854
4855         if (netif_device_present(netdev))
4856                 return 0;
4857
4858         err = mlx5e_create_mdev_resources(mdev);
4859         if (err)
4860                 return err;
4861
4862         err = mlx5e_attach_netdev(priv);
4863         if (err) {
4864                 mlx5e_destroy_mdev_resources(mdev);
4865                 return err;
4866         }
4867
4868         return 0;
4869 }
4870
4871 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
4872 {
4873         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
4874         struct net_device *netdev = priv->netdev;
4875         struct mlx5_core_dev *mdev = priv->mdev;
4876
4877         if (!netif_device_present(netdev))
4878                 return -ENODEV;
4879
4880         mlx5e_detach_netdev(priv);
4881         mlx5e_destroy_mdev_resources(mdev);
4882         return 0;
4883 }
4884
4885 static int mlx5e_probe(struct auxiliary_device *adev,
4886                        const struct auxiliary_device_id *id)
4887 {
4888         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
4889         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
4890         struct mlx5_core_dev *mdev = edev->mdev;
4891         struct net_device *netdev;
4892         pm_message_t state = {};
4893         unsigned int txqs, rxqs, ptp_txqs = 0;
4894         struct mlx5e_priv *priv;
4895         int qos_sqs = 0;
4896         int err;
4897         int nch;
4898
4899         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
4900                 ptp_txqs = profile->max_tc;
4901
4902         if (mlx5_qos_is_supported(mdev))
4903                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
4904
4905         nch = mlx5e_get_max_num_channels(mdev);
4906         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
4907         rxqs = nch * profile->rq_groups;
4908         netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
4909         if (!netdev) {
4910                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4911                 return -ENOMEM;
4912         }
4913
4914         mlx5e_build_nic_netdev(netdev);
4915
4916         priv = netdev_priv(netdev);
4917         dev_set_drvdata(&adev->dev, priv);
4918
4919         priv->profile = profile;
4920         priv->ppriv = NULL;
4921
4922         err = mlx5e_devlink_port_register(priv);
4923         if (err) {
4924                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
4925                 goto err_destroy_netdev;
4926         }
4927
4928         err = profile->init(mdev, netdev);
4929         if (err) {
4930                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
4931                 goto err_devlink_cleanup;
4932         }
4933
4934         err = mlx5e_resume(adev);
4935         if (err) {
4936                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
4937                 goto err_profile_cleanup;
4938         }
4939
4940         err = register_netdev(netdev);
4941         if (err) {
4942                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4943                 goto err_resume;
4944         }
4945
4946         mlx5e_devlink_port_type_eth_set(priv);
4947
4948         mlx5e_dcbnl_init_app(priv);
4949         mlx5_uplink_netdev_set(mdev, netdev);
4950         return 0;
4951
4952 err_resume:
4953         mlx5e_suspend(adev, state);
4954 err_profile_cleanup:
4955         profile->cleanup(priv);
4956 err_devlink_cleanup:
4957         mlx5e_devlink_port_unregister(priv);
4958 err_destroy_netdev:
4959         mlx5e_destroy_netdev(priv);
4960         return err;
4961 }
4962
4963 static void mlx5e_remove(struct auxiliary_device *adev)
4964 {
4965         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
4966         pm_message_t state = {};
4967
4968         mlx5e_dcbnl_delete_app(priv);
4969         unregister_netdev(priv->netdev);
4970         mlx5e_suspend(adev, state);
4971         priv->profile->cleanup(priv);
4972         mlx5e_devlink_port_unregister(priv);
4973         mlx5e_destroy_netdev(priv);
4974 }
4975
4976 static const struct auxiliary_device_id mlx5e_id_table[] = {
4977         { .name = MLX5_ADEV_NAME ".eth", },
4978         {},
4979 };
4980
4981 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
4982
4983 static struct auxiliary_driver mlx5e_driver = {
4984         .name = "eth",
4985         .probe = mlx5e_probe,
4986         .remove = mlx5e_remove,
4987         .suspend = mlx5e_suspend,
4988         .resume = mlx5e_resume,
4989         .id_table = mlx5e_id_table,
4990 };
4991
4992 int mlx5e_init(void)
4993 {
4994         int ret;
4995
4996         mlx5e_ipsec_build_inverse_table();
4997         mlx5e_build_ptys2ethtool_map();
4998         ret = auxiliary_driver_register(&mlx5e_driver);
4999         if (ret)
5000                 return ret;
5001
5002         ret = mlx5e_rep_init();
5003         if (ret)
5004                 auxiliary_driver_unregister(&mlx5e_driver);
5005         return ret;
5006 }
5007
5008 void mlx5e_cleanup(void)
5009 {
5010         mlx5e_rep_cleanup();
5011         auxiliary_driver_unregister(&mlx5e_driver);
5012 }