2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
63 extern const struct net_device_ops mlx5e_netdev_ops;
66 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
67 #define MLX5E_METADATA_ETHER_LEN 8
69 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
71 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
73 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
74 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
76 #define MLX5E_MAX_NUM_TC 8
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
82 #define MLX5E_RX_MAX_HEAD (256)
84 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
85 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
86 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
87 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
88 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
89 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
91 #define MLX5_MPWRQ_LOG_WQE_SZ 18
92 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
93 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
94 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
96 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
97 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
98 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
99 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
100 * WQEs, This page will absorb write overflow by the hardware, when
101 * receiving packets larger than MTU. These oversize packets are
102 * dropped by the driver at a later stage.
104 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
105 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
106 #define MLX5E_MAX_RQ_NUM_MTTS \
107 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
108 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
109 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
110 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
111 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
112 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
113 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
115 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
116 #define MLX5E_LOG_MAX_RX_WQE_BULK \
117 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
119 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
120 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
121 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
123 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
124 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
125 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
126 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
130 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
131 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
142 #define MLX5E_MIN_NUM_CHANNELS 0x1
143 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
144 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
145 #define MLX5E_TX_CQ_POLL_BUDGET 128
146 #define MLX5E_TX_XSK_POLL_BUDGET 64
147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
149 #define MLX5E_UMR_WQE_INLINE_SZ \
150 (sizeof(struct mlx5e_umr_wqe) + \
151 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
152 MLX5_UMR_MTT_ALIGNMENT))
153 #define MLX5E_UMR_WQEBBS \
154 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
156 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
158 #define mlx5e_dbg(mlevel, priv, format, ...) \
160 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
161 netdev_warn(priv->netdev, format, \
165 #define mlx5e_state_dereference(priv, p) \
166 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
168 enum mlx5e_rq_group {
169 MLX5E_RQ_GROUP_REGULAR,
171 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
174 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
176 if (mlx5_lag_is_lacp_owner(mdev))
179 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
182 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
185 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
186 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
189 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
194 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
195 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
197 return is_kdump_kernel() ?
198 MLX5E_MIN_NUM_CHANNELS :
199 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
202 struct mlx5e_tx_wqe {
203 struct mlx5_wqe_ctrl_seg ctrl;
204 struct mlx5_wqe_eth_seg eth;
205 struct mlx5_wqe_data_seg data[0];
208 struct mlx5e_rx_wqe_ll {
209 struct mlx5_wqe_srq_next_seg next;
210 struct mlx5_wqe_data_seg data[];
213 struct mlx5e_rx_wqe_cyc {
214 struct mlx5_wqe_data_seg data[0];
217 struct mlx5e_umr_wqe {
218 struct mlx5_wqe_ctrl_seg ctrl;
219 struct mlx5_wqe_umr_ctrl_seg uctrl;
220 struct mlx5_mkey_seg mkc;
221 struct mlx5_mtt inline_mtts[0];
224 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
226 enum mlx5e_priv_flag {
227 MLX5E_PFLAG_RX_CQE_BASED_MODER,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER,
229 MLX5E_PFLAG_RX_CQE_COMPRESS,
230 MLX5E_PFLAG_RX_STRIDING_RQ,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
232 MLX5E_PFLAG_XDP_TX_MPWQE,
233 MLX5E_PFLAG_SKB_TX_MPWQE,
234 MLX5E_PFLAG_TX_PORT_TS,
235 MLX5E_NUM_PFLAGS, /* Keep last */
238 #define MLX5E_SET_PFLAG(params, pflag, enable) \
241 (params)->pflags |= BIT(pflag); \
243 (params)->pflags &= ~(BIT(pflag)); \
246 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
248 struct mlx5e_params {
251 u8 log_rq_mtu_frames;
254 bool rx_cqe_compress_def;
255 bool tunneled_offload_en;
256 struct dim_cq_moder rx_cq_moderation;
257 struct dim_cq_moder tx_cq_moderation;
259 u8 tx_min_inline_mode;
260 bool vlan_strip_disable;
266 struct bpf_prog *xdp_prog;
267 struct mlx5e_xsk *xsk;
274 MLX5E_RQ_STATE_ENABLED,
275 MLX5E_RQ_STATE_RECOVERING,
277 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
278 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
279 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
280 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
284 /* data path - accessed per cqe */
287 /* data path - accessed per napi poll */
289 struct napi_struct *napi;
290 struct mlx5_core_cq mcq;
291 struct mlx5e_ch_stats *ch_stats;
294 struct net_device *netdev;
295 struct mlx5_core_dev *mdev;
296 struct mlx5e_priv *priv;
297 struct mlx5_wq_ctrl wq_ctrl;
298 } ____cacheline_aligned_in_smp;
300 struct mlx5e_cq_decomp {
301 /* cqe decompression */
302 struct mlx5_cqe64 title;
303 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
307 } ____cacheline_aligned_in_smp;
309 enum mlx5e_dma_map_type {
310 MLX5E_DMA_MAP_SINGLE,
314 struct mlx5e_sq_dma {
317 enum mlx5e_dma_map_type type;
321 MLX5E_SQ_STATE_ENABLED,
322 MLX5E_SQ_STATE_MPWQE,
323 MLX5E_SQ_STATE_RECOVERING,
324 MLX5E_SQ_STATE_IPSEC,
326 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
327 MLX5E_SQ_STATE_PENDING_XSK_TX,
328 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
331 struct mlx5e_tx_mpwqe {
332 /* Current MPWQE session */
333 struct mlx5e_tx_wqe *wqe;
340 struct mlx5e_skb_fifo {
341 struct sk_buff **fifo;
352 /* dirtied @completion */
356 struct dim dim; /* Adaptive Moderation */
359 u16 pc ____cacheline_aligned_in_smp;
362 struct mlx5e_tx_mpwqe mpwqe;
367 struct mlx5_wq_cyc wq;
369 struct mlx5e_sq_stats *stats;
371 struct mlx5e_sq_dma *dma_fifo;
372 struct mlx5e_skb_fifo skb_fifo;
373 struct mlx5e_tx_wqe_info *wqe_info;
375 void __iomem *uar_map;
376 struct netdev_queue *txq;
384 struct hwtstamp_config *tstamp;
385 struct mlx5_clock *clock;
386 struct net_device *netdev;
387 struct mlx5_core_dev *mdev;
388 struct mlx5e_priv *priv;
391 struct mlx5_wq_ctrl wq_ctrl;
395 struct work_struct recover_work;
396 struct mlx5e_ptpsq *ptpsq;
397 cqe_ts_to_ns ptp_cyc2time;
398 } ____cacheline_aligned_in_smp;
400 struct mlx5e_dma_info {
404 struct xdp_buff *xsk;
408 /* XDP packets can be transmitted in different ways. On completion, we need to
409 * distinguish between them to clean up things in a proper way.
411 enum mlx5e_xdp_xmit_mode {
412 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
413 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
416 MLX5E_XDP_XMIT_MODE_FRAME,
418 /* The xdp_frame was created in place as a result of XDP_TX from a
419 * regular RQ. No DMA remapping happened, and the page belongs to us.
421 MLX5E_XDP_XMIT_MODE_PAGE,
423 /* No xdp_frame was created at all, the transmit happened from a UMEM
424 * page. The UMEM Completion Ring producer pointer has to be increased.
426 MLX5E_XDP_XMIT_MODE_XSK,
429 struct mlx5e_xdp_info {
430 enum mlx5e_xdp_xmit_mode mode;
433 struct xdp_frame *xdpf;
438 struct mlx5e_dma_info di;
443 struct mlx5e_xmit_data {
449 struct mlx5e_xdp_info_fifo {
450 struct mlx5e_xdp_info *xi;
457 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
458 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
459 struct mlx5e_xmit_data *,
460 struct mlx5e_xdp_info *,
466 /* dirtied @completion */
471 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
473 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
474 struct mlx5e_tx_mpwqe mpwqe;
479 struct xsk_buff_pool *xsk_pool;
480 struct mlx5_wq_cyc wq;
481 struct mlx5e_xdpsq_stats *stats;
482 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
483 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
485 struct mlx5e_xdp_wqe_info *wqe_info;
486 struct mlx5e_xdp_info_fifo xdpi_fifo;
488 void __iomem *uar_map;
497 struct mlx5_wq_ctrl wq_ctrl;
498 struct mlx5e_channel *channel;
499 } ____cacheline_aligned_in_smp;
501 struct mlx5e_ktls_resync_resp;
508 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
511 /* write@xmit, read@completion */
513 struct mlx5e_icosq_wqe_info *wqe_info;
517 struct mlx5_wq_cyc wq;
518 void __iomem *uar_map;
522 struct mlx5e_ktls_resync_resp *ktls_resync;
525 struct mlx5_wq_ctrl wq_ctrl;
526 struct mlx5e_channel *channel;
528 struct work_struct recover_work;
529 } ____cacheline_aligned_in_smp;
531 struct mlx5e_wqe_frag_info {
532 struct mlx5e_dma_info *di;
537 struct mlx5e_umr_dma_info {
538 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
541 struct mlx5e_mpw_info {
542 struct mlx5e_umr_dma_info umr;
543 u16 consumed_strides;
544 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
547 #define MLX5E_MAX_RX_FRAGS 4
549 /* a single cache unit is capable to serve one napi call (for non-striding rq)
550 * or a MPWQE (for striding rq).
552 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
553 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
554 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
555 struct mlx5e_page_cache {
558 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
562 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
563 typedef struct sk_buff *
564 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
565 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
566 typedef struct sk_buff *
567 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
568 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
569 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
570 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
572 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
573 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
576 MLX5E_RQ_FLAG_XDP_XMIT,
577 MLX5E_RQ_FLAG_XDP_REDIRECT,
580 struct mlx5e_rq_frag_info {
585 struct mlx5e_rq_frags_info {
586 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
596 struct mlx5_wq_cyc wq;
597 struct mlx5e_wqe_frag_info *frags;
598 struct mlx5e_dma_info *di;
599 struct mlx5e_rq_frags_info info;
600 mlx5e_fp_skb_from_cqe skb_from_cqe;
603 struct mlx5_wq_ll wq;
604 struct mlx5e_umr_wqe umr_wqe;
605 struct mlx5e_mpw_info *info;
606 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
618 u8 map_dir; /* dma map direction */
622 struct net_device *netdev;
623 struct mlx5e_rq_stats *stats;
625 struct mlx5e_cq_decomp cqd;
626 struct mlx5e_page_cache page_cache;
627 struct hwtstamp_config *tstamp;
628 struct mlx5_clock *clock;
629 struct mlx5e_icosq *icosq;
630 struct mlx5e_priv *priv;
632 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
633 mlx5e_fp_post_rx_wqes post_wqes;
634 mlx5e_fp_dealloc_wqe dealloc_wqe;
640 struct dim dim; /* Dynamic Interrupt Moderation */
643 struct bpf_prog __rcu *xdp_prog;
644 struct mlx5e_xdpsq *xdpsq;
645 DECLARE_BITMAP(flags, 8);
646 struct page_pool *page_pool;
648 /* AF_XDP zero-copy */
649 struct xsk_buff_pool *xsk_pool;
651 struct work_struct recover_work;
654 struct mlx5_wq_ctrl wq_ctrl;
658 struct mlx5_core_dev *mdev;
659 struct mlx5_core_mkey umr_mkey;
660 struct mlx5e_dma_info wqe_overflow;
662 /* XDP read-mostly */
663 struct xdp_rxq_info xdp_rxq;
664 cqe_ts_to_ns ptp_cyc2time;
665 } ____cacheline_aligned_in_smp;
667 enum mlx5e_channel_state {
668 MLX5E_CHANNEL_STATE_XSK,
669 MLX5E_CHANNEL_NUM_STATES
672 struct mlx5e_channel {
675 struct mlx5e_xdpsq rq_xdpsq;
676 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
677 struct mlx5e_icosq icosq; /* internal control operations */
678 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
680 struct napi_struct napi;
682 struct net_device *netdev;
689 struct mlx5e_xdpsq xdpsq;
691 /* AF_XDP zero-copy */
692 struct mlx5e_rq xskrq;
693 struct mlx5e_xdpsq xsksq;
696 struct mlx5e_icosq async_icosq;
697 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
698 spinlock_t async_icosq_lock;
700 /* data path - accessed per napi poll */
701 const struct cpumask *aff_mask;
702 struct mlx5e_ch_stats *stats;
705 struct mlx5e_priv *priv;
706 struct mlx5_core_dev *mdev;
707 struct hwtstamp_config *tstamp;
708 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
715 struct mlx5e_channels {
716 struct mlx5e_channel **c;
717 struct mlx5e_ptp *ptp;
719 struct mlx5e_params params;
722 struct mlx5e_channel_stats {
723 struct mlx5e_ch_stats ch;
724 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
725 struct mlx5e_rq_stats rq;
726 struct mlx5e_rq_stats xskrq;
727 struct mlx5e_xdpsq_stats rq_xdpsq;
728 struct mlx5e_xdpsq_stats xdpsq;
729 struct mlx5e_xdpsq_stats xsksq;
730 } ____cacheline_aligned_in_smp;
732 struct mlx5e_ptp_stats {
733 struct mlx5e_ch_stats ch;
734 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
735 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
736 struct mlx5e_rq_stats rq;
737 } ____cacheline_aligned_in_smp;
741 MLX5E_STATE_DESTROYING,
742 MLX5E_STATE_XDP_TX_ENABLED,
743 MLX5E_STATE_XDP_ACTIVE,
751 struct mlx5e_modify_sq_param {
757 u16 qos_queue_group_id;
760 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
761 struct mlx5e_hv_vhca_stats_agent {
762 struct mlx5_hv_vhca_agent *agent;
763 struct delayed_work work;
770 /* XSK buffer pools are stored separately from channels,
771 * because we don't want to lose them when channels are
772 * recreated. The kernel also stores buffer pool, but it doesn't
773 * distinguish between zero-copy and non-zero-copy UMEMs, so
774 * rely on our mechanism.
776 struct xsk_buff_pool **pools;
781 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
782 * initialized, and used where we can't allocate them because that functions
783 * must not fail. Use with care and make sure the same variable is not used
784 * simultaneously by multiple users.
786 struct mlx5e_scratchpad {
787 cpumask_var_t cpumask;
791 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES));
792 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES);
793 struct mlx5e_sq_stats **qos_sq_stats;
802 /* priv data path fields - start */
803 /* +1 for port ptp ts */
804 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC +
805 MLX5E_QOS_MAX_LEAF_NODES];
806 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
807 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
808 #ifdef CONFIG_MLX5_CORE_EN_DCB
809 struct mlx5e_dcbx_dp dcbx_dp;
811 /* priv data path fields - end */
815 struct mutex state_lock; /* Protects Interface state */
816 struct mlx5e_rq drop_rq;
818 struct mlx5e_channels channels;
819 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
820 struct mlx5e_rx_res *rx_res;
821 u32 tx_rates[MLX5E_MAX_NUM_SQS];
823 struct mlx5e_flow_steering fs;
825 struct workqueue_struct *wq;
826 struct work_struct update_carrier_work;
827 struct work_struct set_rx_mode_work;
828 struct work_struct tx_timeout_work;
829 struct work_struct update_stats_work;
830 struct work_struct monitor_counters_work;
831 struct mlx5_nb monitor_counters_nb;
833 struct mlx5_core_dev *mdev;
834 struct net_device *netdev;
835 struct mlx5e_trap *en_trap;
836 struct mlx5e_stats stats;
837 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
838 struct mlx5e_channel_stats trap_stats;
839 struct mlx5e_ptp_stats ptp_stats;
844 struct hwtstamp_config tstamp;
846 u16 drop_rq_q_counter;
847 struct notifier_block events_nb;
848 struct notifier_block blocking_events_nb;
851 struct udp_tunnel_nic_info nic_info;
852 #ifdef CONFIG_MLX5_CORE_EN_DCB
853 struct mlx5e_dcbx dcbx;
856 const struct mlx5e_profile *profile;
858 #ifdef CONFIG_MLX5_EN_IPSEC
859 struct mlx5e_ipsec *ipsec;
861 #ifdef CONFIG_MLX5_EN_TLS
862 struct mlx5e_tls *tls;
864 struct devlink_health_reporter *tx_reporter;
865 struct devlink_health_reporter *rx_reporter;
866 struct mlx5e_xsk xsk;
867 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
868 struct mlx5e_hv_vhca_stats_agent stats_agent;
870 struct mlx5e_scratchpad scratchpad;
871 struct mlx5e_htb htb;
874 struct mlx5e_rx_handlers {
875 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
876 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
879 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
881 struct mlx5e_profile {
882 int (*init)(struct mlx5_core_dev *mdev,
883 struct net_device *netdev);
884 void (*cleanup)(struct mlx5e_priv *priv);
885 int (*init_rx)(struct mlx5e_priv *priv);
886 void (*cleanup_rx)(struct mlx5e_priv *priv);
887 int (*init_tx)(struct mlx5e_priv *priv);
888 void (*cleanup_tx)(struct mlx5e_priv *priv);
889 void (*enable)(struct mlx5e_priv *priv);
890 void (*disable)(struct mlx5e_priv *priv);
891 int (*update_rx)(struct mlx5e_priv *priv);
892 void (*update_stats)(struct mlx5e_priv *priv);
893 void (*update_carrier)(struct mlx5e_priv *priv);
894 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
895 mlx5e_stats_grp_t *stats_grps;
896 const struct mlx5e_rx_handlers *rx_handlers;
902 void mlx5e_build_ptys2ethtool_map(void);
904 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
906 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
907 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
909 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
910 int mlx5e_self_test_num(struct mlx5e_priv *priv);
911 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
913 void mlx5e_set_rx_mode_work(struct work_struct *work);
915 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
916 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
917 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
919 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
921 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
923 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
925 struct mlx5e_xsk_param;
927 struct mlx5e_rq_param;
928 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
929 struct mlx5e_xsk_param *xsk, int node,
930 struct mlx5e_rq *rq);
931 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
932 void mlx5e_close_rq(struct mlx5e_rq *rq);
933 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
934 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
936 struct mlx5e_sq_param;
937 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
938 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
939 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
940 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
941 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
942 struct mlx5e_xdpsq *sq, bool is_redirect);
943 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
945 struct mlx5e_create_cq_param {
946 struct napi_struct *napi;
947 struct mlx5e_ch_stats *ch_stats;
952 struct mlx5e_cq_param;
953 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
954 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
955 struct mlx5e_cq *cq);
956 void mlx5e_close_cq(struct mlx5e_cq *cq);
958 int mlx5e_open_locked(struct net_device *netdev);
959 int mlx5e_close_locked(struct net_device *netdev);
961 int mlx5e_open_channels(struct mlx5e_priv *priv,
962 struct mlx5e_channels *chs);
963 void mlx5e_close_channels(struct mlx5e_channels *chs);
965 /* Function pointer to be used to modify HW or kernel settings while
968 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
969 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
970 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
974 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
975 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
976 struct mlx5e_params *new_params,
977 mlx5e_fp_preactivate preactivate,
978 void *context, bool reset);
979 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
980 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
981 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
982 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
983 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
984 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
986 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
987 void mlx5e_activate_rq(struct mlx5e_rq *rq);
988 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
989 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
990 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
992 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
993 struct mlx5e_modify_sq_param *p);
994 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
995 struct mlx5e_params *params, struct mlx5e_sq_param *param,
996 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid);
997 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
998 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
999 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1000 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1001 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1002 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1003 struct mlx5e_create_sq_param;
1004 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1005 struct mlx5e_sq_param *param,
1006 struct mlx5e_create_sq_param *csp,
1007 u16 qos_queue_group_id,
1009 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1010 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1012 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1014 return MLX5_CAP_ETH(mdev, swp) &&
1015 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1018 extern const struct ethtool_ops mlx5e_ethtool_ops;
1020 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1021 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1022 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1024 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1026 /* common netdev helpers */
1027 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1028 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1029 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1030 struct mlx5e_rq *drop_rq);
1031 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1032 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1033 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1035 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1036 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1038 int mlx5e_create_tises(struct mlx5e_priv *priv);
1039 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1040 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1041 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1042 int mlx5e_close(struct net_device *netdev);
1043 int mlx5e_open(struct net_device *netdev);
1045 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1047 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1048 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1049 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1050 mlx5e_fp_preactivate preactivate);
1051 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1053 /* ethtool helpers */
1054 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1055 struct ethtool_drvinfo *drvinfo);
1056 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1057 uint32_t stringset, uint8_t *data);
1058 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1059 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1060 struct ethtool_stats *stats, u64 *data);
1061 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1062 struct ethtool_ringparam *param);
1063 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1064 struct ethtool_ringparam *param);
1065 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1066 struct ethtool_channels *ch);
1067 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1068 struct ethtool_channels *ch);
1069 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1070 struct ethtool_coalesce *coal);
1071 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1072 struct ethtool_coalesce *coal);
1073 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1074 struct ethtool_link_ksettings *link_ksettings);
1075 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1076 const struct ethtool_link_ksettings *link_ksettings);
1077 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1078 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1080 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1082 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1083 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1084 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1085 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1086 struct ethtool_ts_info *info);
1087 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1088 struct ethtool_flash *flash);
1089 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1090 struct ethtool_pauseparam *pauseparam);
1091 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1092 struct ethtool_pauseparam *pauseparam);
1094 /* mlx5e generic netdev management API */
1095 static inline unsigned int
1096 mlx5e_calc_max_nch(struct mlx5e_priv *priv, const struct mlx5e_profile *profile)
1098 return priv->netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
1102 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1104 return !is_kdump_kernel() &&
1105 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1108 int mlx5e_priv_init(struct mlx5e_priv *priv,
1109 struct net_device *netdev,
1110 struct mlx5_core_dev *mdev);
1111 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1113 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs);
1114 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1115 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1116 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1117 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1118 const struct mlx5e_profile *new_profile, void *new_ppriv);
1119 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1120 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1121 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1122 void mlx5e_rx_dim_work(struct work_struct *work);
1123 void mlx5e_tx_dim_work(struct work_struct *work);
1125 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1126 struct net_device *netdev,
1127 netdev_features_t features);
1128 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1129 #ifdef CONFIG_MLX5_ESWITCH
1130 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1131 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1132 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1133 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1135 #endif /* __MLX5_EN_H__ */