drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
   3  * Copyright 2016-2020 NXP
   4  */
   5 #include <linux/init.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/of_net.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/msi.h>
  12 #include <linux/kthread.h>
  13 #include <linux/iommu.h>
  14 #include <linux/fsl/mc.h>
  15 #include <linux/bpf.h>
  16 #include <linux/bpf_trace.h>
  17 #include <linux/fsl/ptp_qoriq.h>
  18 #include <linux/ptp_classify.h>
  19 #include <net/pkt_cls.h>
  20 #include <net/sock.h>
  21
  22 #include "dpaa2-eth.h"
  23
  24 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
  25  * using trace events only need to #include <trace/events/sched.h>
  26  */
  27 #define CREATE_TRACE_POINTS
  28 #include "dpaa2-eth-trace.h"
  29
  30 MODULE_LICENSE("Dual BSD/GPL");
  31 MODULE_AUTHOR("Freescale Semiconductor, Inc");
  32 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
  33
  34 struct ptp_qoriq *dpaa2_ptp;
  35 EXPORT_SYMBOL(dpaa2_ptp);
  36
  37 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
  38                                 dma_addr_t iova_addr)
  39 {
  40         phys_addr_t phys_addr;
  41
  42         phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  43
  44         return phys_to_virt(phys_addr);
  45 }
  46
  47 static void dpaa2_eth_validate_rx_csum(struct dpaa2_eth_priv *priv,
  48                                        u32 fd_status,
  49                                        struct sk_buff *skb)
  50 {
  51         skb_checksum_none_assert(skb);
  52
  53         /* HW checksum validation is disabled, nothing to do here */
  54         if (!(priv->net_dev->features & NETIF_F_RXCSUM))
  55                 return;
  56
  57         /* Read checksum validation bits */
  58         if (!((fd_status & DPAA2_FAS_L3CV) &&
  59               (fd_status & DPAA2_FAS_L4CV)))
  60                 return;
  61
  62         /* Inform the stack there's no need to compute L3/L4 csum anymore */
  63         skb->ip_summed = CHECKSUM_UNNECESSARY;
  64 }
  65
  66 /* Free a received FD.
  67  * Not to be used for Tx conf FDs or on any other paths.
  68  */
  69 static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv,
  70                                  const struct dpaa2_fd *fd,
  71                                  void *vaddr)
  72 {
  73         struct device *dev = priv->net_dev->dev.parent;
  74         dma_addr_t addr = dpaa2_fd_get_addr(fd);
  75         u8 fd_format = dpaa2_fd_get_format(fd);
  76         struct dpaa2_sg_entry *sgt;
  77         void *sg_vaddr;
  78         int i;
  79
  80         /* If single buffer frame, just free the data buffer */
  81         if (fd_format == dpaa2_fd_single)
  82                 goto free_buf;
  83         else if (fd_format != dpaa2_fd_sg)
  84                 /* We don't support any other format */
  85                 return;
  86
  87         /* For S/G frames, we first need to free all SG entries
  88          * except the first one, which was taken care of already
  89          */
  90         sgt = vaddr + dpaa2_fd_get_offset(fd);
  91         for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
  92                 addr = dpaa2_sg_get_addr(&sgt[i]);
  93                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
  94                 dma_unmap_page(dev, addr, priv->rx_buf_size,
  95                                DMA_BIDIRECTIONAL);
  96
  97                 free_pages((unsigned long)sg_vaddr, 0);
  98                 if (dpaa2_sg_is_final(&sgt[i]))
  99                         break;
 100         }
 101
 102 free_buf:
 103         free_pages((unsigned long)vaddr, 0);
 104 }
 105
 106 /* Build a linear skb based on a single-buffer frame descriptor */
 107 static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_channel *ch,
 108                                                   const struct dpaa2_fd *fd,
 109                                                   void *fd_vaddr)
 110 {
 111         struct sk_buff *skb = NULL;
 112         u16 fd_offset = dpaa2_fd_get_offset(fd);
 113         u32 fd_length = dpaa2_fd_get_len(fd);
 114
 115         ch->buf_count--;
 116
 117         skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 118         if (unlikely(!skb))
 119                 return NULL;
 120
 121         skb_reserve(skb, fd_offset);
 122         skb_put(skb, fd_length);
 123
 124         return skb;
 125 }
 126
 127 /* Build a non linear (fragmented) skb based on a S/G table */
 128 static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv,
 129                                                 struct dpaa2_eth_channel *ch,
 130                                                 struct dpaa2_sg_entry *sgt)
 131 {
 132         struct sk_buff *skb = NULL;
 133         struct device *dev = priv->net_dev->dev.parent;
 134         void *sg_vaddr;
 135         dma_addr_t sg_addr;
 136         u16 sg_offset;
 137         u32 sg_length;
 138         struct page *page, *head_page;
 139         int page_offset;
 140         int i;
 141
 142         for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
 143                 struct dpaa2_sg_entry *sge = &sgt[i];
 144
 145                 /* NOTE: We only support SG entries in dpaa2_sg_single format,
 146                  * but this is the only format we may receive from HW anyway
 147                  */
 148
 149                 /* Get the address and length from the S/G entry */
 150                 sg_addr = dpaa2_sg_get_addr(sge);
 151                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
 152                 dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
 153                                DMA_BIDIRECTIONAL);
 154
 155                 sg_length = dpaa2_sg_get_len(sge);
 156
 157                 if (i == 0) {
 158                         /* We build the skb around the first data buffer */
 159                         skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 160                         if (unlikely(!skb)) {
 161                                 /* Free the first SG entry now, since we already
 162                                  * unmapped it and obtained the virtual address
 163                                  */
 164                                 free_pages((unsigned long)sg_vaddr, 0);
 165
 166                                 /* We still need to subtract the buffers used
 167                                  * by this FD from our software counter
 168                                  */
 169                                 while (!dpaa2_sg_is_final(&sgt[i]) &&
 170                                        i < DPAA2_ETH_MAX_SG_ENTRIES)
 171                                         i++;
 172                                 break;
 173                         }
 174
 175                         sg_offset = dpaa2_sg_get_offset(sge);
 176                         skb_reserve(skb, sg_offset);
 177                         skb_put(skb, sg_length);
 178                 } else {
 179                         /* Rest of the data buffers are stored as skb frags */
 180                         page = virt_to_page(sg_vaddr);
 181                         head_page = virt_to_head_page(sg_vaddr);
 182
 183                         /* Offset in page (which may be compound).
 184                          * Data in subsequent SG entries is stored from the
 185                          * beginning of the buffer, so we don't need to add the
 186                          * sg_offset.
 187                          */
 188                         page_offset = ((unsigned long)sg_vaddr &
 189                                 (PAGE_SIZE - 1)) +
 190                                 (page_address(page) - page_address(head_page));
 191
 192                         skb_add_rx_frag(skb, i - 1, head_page, page_offset,
 193                                         sg_length, priv->rx_buf_size);
 194                 }
 195
 196                 if (dpaa2_sg_is_final(sge))
 197                         break;
 198         }
 199
 200         WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
 201
 202         /* Count all data buffers + SG table buffer */
 203         ch->buf_count -= i + 2;
 204
 205         return skb;
 206 }
 207
 208 /* Free buffers acquired from the buffer pool or which were meant to
 209  * be released in the pool
 210  */
 211 static void dpaa2_eth_free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array,
 212                                 int count)
 213 {
 214         struct device *dev = priv->net_dev->dev.parent;
 215         void *vaddr;
 216         int i;
 217
 218         for (i = 0; i < count; i++) {
 219                 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
 220                 dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
 221                                DMA_BIDIRECTIONAL);
 222                 free_pages((unsigned long)vaddr, 0);
 223         }
 224 }
 225
 226 static void dpaa2_eth_xdp_release_buf(struct dpaa2_eth_priv *priv,
 227                                       struct dpaa2_eth_channel *ch,
 228                                       dma_addr_t addr)
 229 {
 230         int retries = 0;
 231         int err;
 232
 233         ch->xdp.drop_bufs[ch->xdp.drop_cnt++] = addr;
 234         if (ch->xdp.drop_cnt < DPAA2_ETH_BUFS_PER_CMD)
 235                 return;
 236
 237         while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
 238                                                ch->xdp.drop_bufs,
 239                                                ch->xdp.drop_cnt)) == -EBUSY) {
 240                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
 241                         break;
 242                 cpu_relax();
 243         }
 244
 245         if (err) {
 246                 dpaa2_eth_free_bufs(priv, ch->xdp.drop_bufs, ch->xdp.drop_cnt);
 247                 ch->buf_count -= ch->xdp.drop_cnt;
 248         }
 249
 250         ch->xdp.drop_cnt = 0;
 251 }
 252
 253 static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
 254                                struct dpaa2_eth_fq *fq,
 255                                struct dpaa2_eth_xdp_fds *xdp_fds)
 256 {
 257         int total_enqueued = 0, retries = 0, enqueued;
 258         struct dpaa2_eth_drv_stats *percpu_extras;
 259         int num_fds, err, max_retries;
 260         struct dpaa2_fd *fds;
 261
 262         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 263
 264         /* try to enqueue all the FDs until the max number of retries is hit */
 265         fds = xdp_fds->fds;
 266         num_fds = xdp_fds->num;
 267         max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
 268         while (total_enqueued < num_fds && retries < max_retries) {
 269                 err = priv->enqueue(priv, fq, &fds[total_enqueued],
 270                                     0, num_fds - total_enqueued, &enqueued);
 271                 if (err == -EBUSY) {
 272                         percpu_extras->tx_portal_busy += ++retries;
 273                         continue;
 274                 }
 275                 total_enqueued += enqueued;
 276         }
 277         xdp_fds->num = 0;
 278
 279         return total_enqueued;
 280 }
 281
 282 static void dpaa2_eth_xdp_tx_flush(struct dpaa2_eth_priv *priv,
 283                                    struct dpaa2_eth_channel *ch,
 284                                    struct dpaa2_eth_fq *fq)
 285 {
 286         struct rtnl_link_stats64 *percpu_stats;
 287         struct dpaa2_fd *fds;
 288         int enqueued, i;
 289
 290         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 291
 292         // enqueue the array of XDP_TX frames
 293         enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
 294
 295         /* update statistics */
 296         percpu_stats->tx_packets += enqueued;
 297         fds = fq->xdp_tx_fds.fds;
 298         for (i = 0; i < enqueued; i++) {
 299                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
 300                 ch->stats.xdp_tx++;
 301         }
 302         for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
 303                 dpaa2_eth_xdp_release_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
 304                 percpu_stats->tx_errors++;
 305                 ch->stats.xdp_tx_err++;
 306         }
 307         fq->xdp_tx_fds.num = 0;
 308 }
 309
 310 static void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
 311                                   struct dpaa2_eth_channel *ch,
 312                                   struct dpaa2_fd *fd,
 313                                   void *buf_start, u16 queue_id)
 314 {
 315         struct dpaa2_faead *faead;
 316         struct dpaa2_fd *dest_fd;
 317         struct dpaa2_eth_fq *fq;
 318         u32 ctrl, frc;
 319
 320         /* Mark the egress frame hardware annotation area as valid */
 321         frc = dpaa2_fd_get_frc(fd);
 322         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 323         dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
 324
 325         /* Instruct hardware to release the FD buffer directly into
 326          * the buffer pool once transmission is completed, instead of
 327          * sending a Tx confirmation frame to us
 328          */
 329         ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
 330         faead = dpaa2_get_faead(buf_start, false);
 331         faead->ctrl = cpu_to_le32(ctrl);
 332         faead->conf_fqid = 0;
 333
 334         fq = &priv->fq[queue_id];
 335         dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
 336         memcpy(dest_fd, fd, sizeof(*dest_fd));
 337
 338         if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
 339                 return;
 340
 341         dpaa2_eth_xdp_tx_flush(priv, ch, fq);
 342 }
 343
 344 static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv,
 345                              struct dpaa2_eth_channel *ch,
 346                              struct dpaa2_eth_fq *rx_fq,
 347                              struct dpaa2_fd *fd, void *vaddr)
 348 {
 349         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 350         struct bpf_prog *xdp_prog;
 351         struct xdp_buff xdp;
 352         u32 xdp_act = XDP_PASS;
 353         int err;
 354
 355         rcu_read_lock();
 356
 357         xdp_prog = READ_ONCE(ch->xdp.prog);
 358         if (!xdp_prog)
 359                 goto out;
 360
 361         xdp.data = vaddr + dpaa2_fd_get_offset(fd);
 362         xdp.data_end = xdp.data + dpaa2_fd_get_len(fd);
 363         xdp.data_hard_start = xdp.data - XDP_PACKET_HEADROOM;
 364         xdp_set_data_meta_invalid(&xdp);
 365         xdp.rxq = &ch->xdp_rxq;
 366
 367         xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE -
 368                 (dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM);
 369
 370         xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
 371
 372         /* xdp.data pointer may have changed */
 373         dpaa2_fd_set_offset(fd, xdp.data - vaddr);
 374         dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
 375
 376         switch (xdp_act) {
 377         case XDP_PASS:
 378                 break;
 379         case XDP_TX:
 380                 dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
 381                 break;
 382         default:
 383                 bpf_warn_invalid_xdp_action(xdp_act);
 384                 fallthrough;
 385         case XDP_ABORTED:
 386                 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
 387                 fallthrough;
 388         case XDP_DROP:
 389                 dpaa2_eth_xdp_release_buf(priv, ch, addr);
 390                 ch->stats.xdp_drop++;
 391                 break;
 392         case XDP_REDIRECT:
 393                 dma_unmap_page(priv->net_dev->dev.parent, addr,
 394                                priv->rx_buf_size, DMA_BIDIRECTIONAL);
 395                 ch->buf_count--;
 396
 397                 /* Allow redirect use of full headroom */
 398                 xdp.data_hard_start = vaddr;
 399                 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
 400
 401                 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
 402                 if (unlikely(err))
 403                         ch->stats.xdp_drop++;
 404                 else
 405                         ch->stats.xdp_redirect++;
 406                 break;
 407         }
 408
 409         ch->xdp.res |= xdp_act;
 410 out:
 411         rcu_read_unlock();
 412         return xdp_act;
 413 }
 414
 415 /* Main Rx frame processing routine */
 416 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
 417                          struct dpaa2_eth_channel *ch,
 418                          const struct dpaa2_fd *fd,
 419                          struct dpaa2_eth_fq *fq)
 420 {
 421         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 422         u8 fd_format = dpaa2_fd_get_format(fd);
 423         void *vaddr;
 424         struct sk_buff *skb;
 425         struct rtnl_link_stats64 *percpu_stats;
 426         struct dpaa2_eth_drv_stats *percpu_extras;
 427         struct device *dev = priv->net_dev->dev.parent;
 428         struct dpaa2_fas *fas;
 429         void *buf_data;
 430         u32 status = 0;
 431         u32 xdp_act;
 432
 433         /* Tracing point */
 434         trace_dpaa2_rx_fd(priv->net_dev, fd);
 435
 436         vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
 437         dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
 438                                 DMA_BIDIRECTIONAL);
 439
 440         fas = dpaa2_get_fas(vaddr, false);
 441         prefetch(fas);
 442         buf_data = vaddr + dpaa2_fd_get_offset(fd);
 443         prefetch(buf_data);
 444
 445         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 446         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 447
 448         if (fd_format == dpaa2_fd_single) {
 449                 xdp_act = dpaa2_eth_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
 450                 if (xdp_act != XDP_PASS) {
 451                         percpu_stats->rx_packets++;
 452                         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 453                         return;
 454                 }
 455
 456                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 457                                DMA_BIDIRECTIONAL);
 458                 skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
 459         } else if (fd_format == dpaa2_fd_sg) {
 460                 WARN_ON(priv->xdp_prog);
 461
 462                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 463                                DMA_BIDIRECTIONAL);
 464                 skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
 465                 free_pages((unsigned long)vaddr, 0);
 466                 percpu_extras->rx_sg_frames++;
 467                 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
 468         } else {
 469                 /* We don't support any other format */
 470                 goto err_frame_format;
 471         }
 472
 473         if (unlikely(!skb))
 474                 goto err_build_skb;
 475
 476         prefetch(skb->data);
 477
 478         /* Get the timestamp value */
 479         if (priv->rx_tstamp) {
 480                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
 481                 __le64 *ts = dpaa2_get_ts(vaddr, false);
 482                 u64 ns;
 483
 484                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 485
 486                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 487                 shhwtstamps->hwtstamp = ns_to_ktime(ns);
 488         }
 489
 490         /* Check if we need to validate the L4 csum */
 491         if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
 492                 status = le32_to_cpu(fas->status);
 493                 dpaa2_eth_validate_rx_csum(priv, status, skb);
 494         }
 495
 496         skb->protocol = eth_type_trans(skb, priv->net_dev);
 497         skb_record_rx_queue(skb, fq->flowid);
 498
 499         percpu_stats->rx_packets++;
 500         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 501
 502         list_add_tail(&skb->list, ch->rx_list);
 503
 504         return;
 505
 506 err_build_skb:
 507         dpaa2_eth_free_rx_fd(priv, fd, vaddr);
 508 err_frame_format:
 509         percpu_stats->rx_dropped++;
 510 }
 511
 512 /* Consume all frames pull-dequeued into the store. This is the simplest way to
 513  * make sure we don't accidentally issue another volatile dequeue which would
 514  * overwrite (leak) frames already in the store.
 515  *
 516  * Observance of NAPI budget is not our concern, leaving that to the caller.
 517  */
 518 static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch,
 519                                     struct dpaa2_eth_fq **src)
 520 {
 521         struct dpaa2_eth_priv *priv = ch->priv;
 522         struct dpaa2_eth_fq *fq = NULL;
 523         struct dpaa2_dq *dq;
 524         const struct dpaa2_fd *fd;
 525         int cleaned = 0, retries = 0;
 526         int is_last;
 527
 528         do {
 529                 dq = dpaa2_io_store_next(ch->store, &is_last);
 530                 if (unlikely(!dq)) {
 531                         /* If we're here, we *must* have placed a
 532                          * volatile dequeue comnmand, so keep reading through
 533                          * the store until we get some sort of valid response
 534                          * token (either a valid frame or an "empty dequeue")
 535                          */
 536                         if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
 537                                 netdev_err_once(priv->net_dev,
 538                                                 "Unable to read a valid dequeue response\n");
 539                                 return -ETIMEDOUT;
 540                         }
 541                         continue;
 542                 }
 543
 544                 fd = dpaa2_dq_fd(dq);
 545                 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
 546
 547                 fq->consume(priv, ch, fd, fq);
 548                 cleaned++;
 549                 retries = 0;
 550         } while (!is_last);
 551
 552         if (!cleaned)
 553                 return 0;
 554
 555         fq->stats.frames += cleaned;
 556         ch->stats.frames += cleaned;
 557
 558         /* A dequeue operation only pulls frames from a single queue
 559          * into the store. Return the frame queue as an out param.
 560          */
 561         if (src)
 562                 *src = fq;
 563
 564         return cleaned;
 565 }
 566
 567 static int dpaa2_eth_ptp_parse(struct sk_buff *skb,
 568                                u8 *msgtype, u8 *twostep, u8 *udp,
 569                                u16 *correction_offset,
 570                                u16 *origintimestamp_offset)
 571 {
 572         unsigned int ptp_class;
 573         struct ptp_header *hdr;
 574         unsigned int type;
 575         u8 *base;
 576
 577         ptp_class = ptp_classify_raw(skb);
 578         if (ptp_class == PTP_CLASS_NONE)
 579                 return -EINVAL;
 580
 581         hdr = ptp_parse_header(skb, ptp_class);
 582         if (!hdr)
 583                 return -EINVAL;
 584
 585         *msgtype = ptp_get_msgtype(hdr, ptp_class);
 586         *twostep = hdr->flag_field[0] & 0x2;
 587
 588         type = ptp_class & PTP_CLASS_PMASK;
 589         if (type == PTP_CLASS_IPV4 ||
 590             type == PTP_CLASS_IPV6)
 591                 *udp = 1;
 592         else
 593                 *udp = 0;
 594
 595         base = skb_mac_header(skb);
 596         *correction_offset = (u8 *)&hdr->correction - base;
 597         *origintimestamp_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
 598
 599         return 0;
 600 }
 601
 602 /* Configure the egress frame annotation for timestamp update */
 603 static void dpaa2_eth_enable_tx_tstamp(struct dpaa2_eth_priv *priv,
 604                                        struct dpaa2_fd *fd,
 605                                        void *buf_start,
 606                                        struct sk_buff *skb)
 607 {
 608         struct ptp_tstamp origin_timestamp;
 609         struct dpni_single_step_cfg cfg;
 610         u8 msgtype, twostep, udp;
 611         struct dpaa2_faead *faead;
 612         struct dpaa2_fas *fas;
 613         struct timespec64 ts;
 614         u16 offset1, offset2;
 615         u32 ctrl, frc;
 616         __le64 *ns;
 617         u8 *data;
 618
 619         /* Mark the egress frame annotation area as valid */
 620         frc = dpaa2_fd_get_frc(fd);
 621         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 622
 623         /* Set hardware annotation size */
 624         ctrl = dpaa2_fd_get_ctrl(fd);
 625         dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
 626
 627         /* enable UPD (update prepanded data) bit in FAEAD field of
 628          * hardware frame annotation area
 629          */
 630         ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
 631         faead = dpaa2_get_faead(buf_start, true);
 632         faead->ctrl = cpu_to_le32(ctrl);
 633
 634         if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
 635                 if (dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
 636                                         &offset1, &offset2) ||
 637                     msgtype != 0 || twostep) {
 638                         WARN_ONCE(1, "Bad packet for one-step timestamping\n");
 639                         return;
 640                 }
 641
 642                 /* Mark the frame annotation status as valid */
 643                 frc = dpaa2_fd_get_frc(fd);
 644                 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FASV);
 645
 646                 /* Mark the PTP flag for one step timestamping */
 647                 fas = dpaa2_get_fas(buf_start, true);
 648                 fas->status = cpu_to_le32(DPAA2_FAS_PTP);
 649
 650                 dpaa2_ptp->caps.gettime64(&dpaa2_ptp->caps, &ts);
 651                 ns = dpaa2_get_ts(buf_start, true);
 652                 *ns = cpu_to_le64(timespec64_to_ns(&ts) /
 653                                   DPAA2_PTP_CLK_PERIOD_NS);
 654
 655                 /* Update current time to PTP message originTimestamp field */
 656                 ns_to_ptp_tstamp(&origin_timestamp, le64_to_cpup(ns));
 657                 data = skb_mac_header(skb);
 658                 *(__be16 *)(data + offset2) = htons(origin_timestamp.sec_msb);
 659                 *(__be32 *)(data + offset2 + 2) =
 660                         htonl(origin_timestamp.sec_lsb);
 661                 *(__be32 *)(data + offset2 + 6) = htonl(origin_timestamp.nsec);
 662
 663                 cfg.en = 1;
 664                 cfg.ch_update = udp;
 665                 cfg.offset = offset1;
 666                 cfg.peer_delay = 0;
 667
 668                 if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token,
 669                                              &cfg))
 670                         WARN_ONCE(1, "Failed to set single step register");
 671         }
 672 }
 673
 674 /* Create a frame descriptor based on a fragmented skb */
 675 static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv,
 676                                  struct sk_buff *skb,
 677                                  struct dpaa2_fd *fd,
 678                                  void **swa_addr)
 679 {
 680         struct device *dev = priv->net_dev->dev.parent;
 681         void *sgt_buf = NULL;
 682         dma_addr_t addr;
 683         int nr_frags = skb_shinfo(skb)->nr_frags;
 684         struct dpaa2_sg_entry *sgt;
 685         int i, err;
 686         int sgt_buf_size;
 687         struct scatterlist *scl, *crt_scl;
 688         int num_sg;
 689         int num_dma_bufs;
 690         struct dpaa2_eth_swa *swa;
 691
 692         /* Create and map scatterlist.
 693          * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
 694          * to go beyond nr_frags+1.
 695          * Note: We don't support chained scatterlists
 696          */
 697         if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
 698                 return -EINVAL;
 699
 700         scl = kmalloc_array(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
 701         if (unlikely(!scl))
 702                 return -ENOMEM;
 703
 704         sg_init_table(scl, nr_frags + 1);
 705         num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
 706         if (unlikely(num_sg < 0)) {
 707                 err = -ENOMEM;
 708                 goto dma_map_sg_failed;
 709         }
 710         num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 711         if (unlikely(!num_dma_bufs)) {
 712                 err = -ENOMEM;
 713                 goto dma_map_sg_failed;
 714         }
 715
 716         /* Prepare the HW SGT structure */
 717         sgt_buf_size = priv->tx_data_offset +
 718                        sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
 719         sgt_buf = napi_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
 720         if (unlikely(!sgt_buf)) {
 721                 err = -ENOMEM;
 722                 goto sgt_buf_alloc_failed;
 723         }
 724         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 725         memset(sgt_buf, 0, sgt_buf_size);
 726
 727         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 728
 729         /* Fill in the HW SGT structure.
 730          *
 731          * sgt_buf is zeroed out, so the following fields are implicit
 732          * in all sgt entries:
 733          *   - offset is 0
 734          *   - format is 'dpaa2_sg_single'
 735          */
 736         for_each_sg(scl, crt_scl, num_dma_bufs, i) {
 737                 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
 738                 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
 739         }
 740         dpaa2_sg_set_final(&sgt[i - 1], true);
 741
 742         /* Store the skb backpointer in the SGT buffer.
 743          * Fit the scatterlist and the number of buffers alongside the
 744          * skb backpointer in the software annotation area. We'll need
 745          * all of them on Tx Conf.
 746          */
 747         *swa_addr = (void *)sgt_buf;
 748         swa = (struct dpaa2_eth_swa *)sgt_buf;
 749         swa->type = DPAA2_ETH_SWA_SG;
 750         swa->sg.skb = skb;
 751         swa->sg.scl = scl;
 752         swa->sg.num_sg = num_sg;
 753         swa->sg.sgt_size = sgt_buf_size;
 754
 755         /* Separately map the SGT buffer */
 756         addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 757         if (unlikely(dma_mapping_error(dev, addr))) {
 758                 err = -ENOMEM;
 759                 goto dma_map_single_failed;
 760         }
 761         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 762         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 763         dpaa2_fd_set_addr(fd, addr);
 764         dpaa2_fd_set_len(fd, skb->len);
 765         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 766
 767         return 0;
 768
 769 dma_map_single_failed:
 770         skb_free_frag(sgt_buf);
 771 sgt_buf_alloc_failed:
 772         dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 773 dma_map_sg_failed:
 774         kfree(scl);
 775         return err;
 776 }
 777
 778 /* Create a SG frame descriptor based on a linear skb.
 779  *
 780  * This function is used on the Tx path when the skb headroom is not large
 781  * enough for the HW requirements, thus instead of realloc-ing the skb we
 782  * create a SG frame descriptor with only one entry.
 783  */
 784 static int dpaa2_eth_build_sg_fd_single_buf(struct dpaa2_eth_priv *priv,
 785                                             struct sk_buff *skb,
 786                                             struct dpaa2_fd *fd,
 787                                             void **swa_addr)
 788 {
 789         struct device *dev = priv->net_dev->dev.parent;
 790         struct dpaa2_eth_sgt_cache *sgt_cache;
 791         struct dpaa2_sg_entry *sgt;
 792         struct dpaa2_eth_swa *swa;
 793         dma_addr_t addr, sgt_addr;
 794         void *sgt_buf = NULL;
 795         int sgt_buf_size;
 796         int err;
 797
 798         /* Prepare the HW SGT structure */
 799         sgt_cache = this_cpu_ptr(priv->sgt_cache);
 800         sgt_buf_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry);
 801
 802         if (sgt_cache->count == 0)
 803                 sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN,
 804                                   GFP_ATOMIC);
 805         else
 806                 sgt_buf = sgt_cache->buf[--sgt_cache->count];
 807         if (unlikely(!sgt_buf))
 808                 return -ENOMEM;
 809
 810         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 811         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 812
 813         addr = dma_map_single(dev, skb->data, skb->len, DMA_BIDIRECTIONAL);
 814         if (unlikely(dma_mapping_error(dev, addr))) {
 815                 err = -ENOMEM;
 816                 goto data_map_failed;
 817         }
 818
 819         /* Fill in the HW SGT structure */
 820         dpaa2_sg_set_addr(sgt, addr);
 821         dpaa2_sg_set_len(sgt, skb->len);
 822         dpaa2_sg_set_final(sgt, true);
 823
 824         /* Store the skb backpointer in the SGT buffer */
 825         *swa_addr = (void *)sgt_buf;
 826         swa = (struct dpaa2_eth_swa *)sgt_buf;
 827         swa->type = DPAA2_ETH_SWA_SINGLE;
 828         swa->single.skb = skb;
 829         swa->sg.sgt_size = sgt_buf_size;
 830
 831         /* Separately map the SGT buffer */
 832         sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 833         if (unlikely(dma_mapping_error(dev, sgt_addr))) {
 834                 err = -ENOMEM;
 835                 goto sgt_map_failed;
 836         }
 837
 838         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 839         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 840         dpaa2_fd_set_addr(fd, sgt_addr);
 841         dpaa2_fd_set_len(fd, skb->len);
 842         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 843
 844         return 0;
 845
 846 sgt_map_failed:
 847         dma_unmap_single(dev, addr, skb->len, DMA_BIDIRECTIONAL);
 848 data_map_failed:
 849         if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
 850                 kfree(sgt_buf);
 851         else
 852                 sgt_cache->buf[sgt_cache->count++] = sgt_buf;
 853
 854         return err;
 855 }
 856
 857 /* Create a frame descriptor based on a linear skb */
 858 static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv,
 859                                      struct sk_buff *skb,
 860                                      struct dpaa2_fd *fd,
 861                                      void **swa_addr)
 862 {
 863         struct device *dev = priv->net_dev->dev.parent;
 864         u8 *buffer_start, *aligned_start;
 865         struct dpaa2_eth_swa *swa;
 866         dma_addr_t addr;
 867
 868         buffer_start = skb->data - dpaa2_eth_needed_headroom(skb);
 869
 870         /* If there's enough room to align the FD address, do it.
 871          * It will help hardware optimize accesses.
 872          */
 873         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
 874                                   DPAA2_ETH_TX_BUF_ALIGN);
 875         if (aligned_start >= skb->head)
 876                 buffer_start = aligned_start;
 877
 878         /* Store a backpointer to the skb at the beginning of the buffer
 879          * (in the private data area) such that we can release it
 880          * on Tx confirm
 881          */
 882         *swa_addr = (void *)buffer_start;
 883         swa = (struct dpaa2_eth_swa *)buffer_start;
 884         swa->type = DPAA2_ETH_SWA_SINGLE;
 885         swa->single.skb = skb;
 886
 887         addr = dma_map_single(dev, buffer_start,
 888                               skb_tail_pointer(skb) - buffer_start,
 889                               DMA_BIDIRECTIONAL);
 890         if (unlikely(dma_mapping_error(dev, addr)))
 891                 return -ENOMEM;
 892
 893         dpaa2_fd_set_addr(fd, addr);
 894         dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
 895         dpaa2_fd_set_len(fd, skb->len);
 896         dpaa2_fd_set_format(fd, dpaa2_fd_single);
 897         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 898
 899         return 0;
 900 }
 901
 902 /* FD freeing routine on the Tx path
 903  *
 904  * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
 905  * back-pointed to is also freed.
 906  * This can be called either from dpaa2_eth_tx_conf() or on the error path of
 907  * dpaa2_eth_tx().
 908  */
 909 static void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv,
 910                                  struct dpaa2_eth_fq *fq,
 911                                  const struct dpaa2_fd *fd, bool in_napi)
 912 {
 913         struct device *dev = priv->net_dev->dev.parent;
 914         dma_addr_t fd_addr, sg_addr;
 915         struct sk_buff *skb = NULL;
 916         unsigned char *buffer_start;
 917         struct dpaa2_eth_swa *swa;
 918         u8 fd_format = dpaa2_fd_get_format(fd);
 919         u32 fd_len = dpaa2_fd_get_len(fd);
 920
 921         struct dpaa2_eth_sgt_cache *sgt_cache;
 922         struct dpaa2_sg_entry *sgt;
 923
 924         fd_addr = dpaa2_fd_get_addr(fd);
 925         buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
 926         swa = (struct dpaa2_eth_swa *)buffer_start;
 927
 928         if (fd_format == dpaa2_fd_single) {
 929                 if (swa->type == DPAA2_ETH_SWA_SINGLE) {
 930                         skb = swa->single.skb;
 931                         /* Accessing the skb buffer is safe before dma unmap,
 932                          * because we didn't map the actual skb shell.
 933                          */
 934                         dma_unmap_single(dev, fd_addr,
 935                                          skb_tail_pointer(skb) - buffer_start,
 936                                          DMA_BIDIRECTIONAL);
 937                 } else {
 938                         WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type");
 939                         dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
 940                                          DMA_BIDIRECTIONAL);
 941                 }
 942         } else if (fd_format == dpaa2_fd_sg) {
 943                 if (swa->type == DPAA2_ETH_SWA_SG) {
 944                         skb = swa->sg.skb;
 945
 946                         /* Unmap the scatterlist */
 947                         dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg,
 948                                      DMA_BIDIRECTIONAL);
 949                         kfree(swa->sg.scl);
 950
 951                         /* Unmap the SGT buffer */
 952                         dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
 953                                          DMA_BIDIRECTIONAL);
 954                 } else {
 955                         skb = swa->single.skb;
 956
 957                         /* Unmap the SGT Buffer */
 958                         dma_unmap_single(dev, fd_addr, swa->single.sgt_size,
 959                                          DMA_BIDIRECTIONAL);
 960
 961                         sgt = (struct dpaa2_sg_entry *)(buffer_start +
 962                                                         priv->tx_data_offset);
 963                         sg_addr = dpaa2_sg_get_addr(sgt);
 964                         dma_unmap_single(dev, sg_addr, skb->len, DMA_BIDIRECTIONAL);
 965                 }
 966         } else {
 967                 netdev_dbg(priv->net_dev, "Invalid FD format\n");
 968                 return;
 969         }
 970
 971         if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) {
 972                 fq->dq_frames++;
 973                 fq->dq_bytes += fd_len;
 974         }
 975
 976         if (swa->type == DPAA2_ETH_SWA_XDP) {
 977                 xdp_return_frame(swa->xdp.xdpf);
 978                 return;
 979         }
 980
 981         /* Get the timestamp value */
 982         if (skb->cb[0] == TX_TSTAMP) {
 983                 struct skb_shared_hwtstamps shhwtstamps;
 984                 __le64 *ts = dpaa2_get_ts(buffer_start, true);
 985                 u64 ns;
 986
 987                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 988
 989                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 990                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
 991                 skb_tstamp_tx(skb, &shhwtstamps);
 992         } else if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
 993                 mutex_unlock(&priv->onestep_tstamp_lock);
 994         }
 995
 996         /* Free SGT buffer allocated on tx */
 997         if (fd_format != dpaa2_fd_single) {
 998                 sgt_cache = this_cpu_ptr(priv->sgt_cache);
 999                 if (swa->type == DPAA2_ETH_SWA_SG) {
1000                         skb_free_frag(buffer_start);
1001                 } else {
1002                         if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
1003                                 kfree(buffer_start);
1004                         else
1005                                 sgt_cache->buf[sgt_cache->count++] = buffer_start;
1006                 }
1007         }
1008
1009         /* Move on with skb release */
1010         napi_consume_skb(skb, in_napi);
1011 }
1012
1013 static netdev_tx_t __dpaa2_eth_tx(struct sk_buff *skb,
1014                                   struct net_device *net_dev)
1015 {
1016         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1017         struct dpaa2_fd fd;
1018         struct rtnl_link_stats64 *percpu_stats;
1019         struct dpaa2_eth_drv_stats *percpu_extras;
1020         struct dpaa2_eth_fq *fq;
1021         struct netdev_queue *nq;
1022         u16 queue_mapping;
1023         unsigned int needed_headroom;
1024         u32 fd_len;
1025         u8 prio = 0;
1026         int err, i;
1027         void *swa;
1028
1029         percpu_stats = this_cpu_ptr(priv->percpu_stats);
1030         percpu_extras = this_cpu_ptr(priv->percpu_extras);
1031
1032         needed_headroom = dpaa2_eth_needed_headroom(skb);
1033
1034         /* We'll be holding a back-reference to the skb until Tx Confirmation;
1035          * we don't want that overwritten by a concurrent Tx with a cloned skb.
1036          */
1037         skb = skb_unshare(skb, GFP_ATOMIC);
1038         if (unlikely(!skb)) {
1039                 /* skb_unshare() has already freed the skb */
1040                 percpu_stats->tx_dropped++;
1041                 return NETDEV_TX_OK;
1042         }
1043
1044         /* Setup the FD fields */
1045         memset(&fd, 0, sizeof(fd));
1046
1047         if (skb_is_nonlinear(skb)) {
1048                 err = dpaa2_eth_build_sg_fd(priv, skb, &fd, &swa);
1049                 percpu_extras->tx_sg_frames++;
1050                 percpu_extras->tx_sg_bytes += skb->len;
1051         } else if (skb_headroom(skb) < needed_headroom) {
1052                 err = dpaa2_eth_build_sg_fd_single_buf(priv, skb, &fd, &swa);
1053                 percpu_extras->tx_sg_frames++;
1054                 percpu_extras->tx_sg_bytes += skb->len;
1055                 percpu_extras->tx_converted_sg_frames++;
1056                 percpu_extras->tx_converted_sg_bytes += skb->len;
1057         } else {
1058                 err = dpaa2_eth_build_single_fd(priv, skb, &fd, &swa);
1059         }
1060
1061         if (unlikely(err)) {
1062                 percpu_stats->tx_dropped++;
1063                 goto err_build_fd;
1064         }
1065
1066         if (skb->cb[0])
1067                 dpaa2_eth_enable_tx_tstamp(priv, &fd, swa, skb);
1068
1069         /* Tracing point */
1070         trace_dpaa2_tx_fd(net_dev, &fd);
1071
1072         /* TxConf FQ selection relies on queue id from the stack.
1073          * In case of a forwarded frame from another DPNI interface, we choose
1074          * a queue affined to the same core that processed the Rx frame
1075          */
1076         queue_mapping = skb_get_queue_mapping(skb);
1077
1078         if (net_dev->num_tc) {
1079                 prio = netdev_txq_to_tc(net_dev, queue_mapping);
1080                 /* Hardware interprets priority level 0 as being the highest,
1081                  * so we need to do a reverse mapping to the netdev tc index
1082                  */
1083                 prio = net_dev->num_tc - prio - 1;
1084                 /* We have only one FQ array entry for all Tx hardware queues
1085                  * with the same flow id (but different priority levels)
1086                  */
1087                 queue_mapping %= dpaa2_eth_queue_count(priv);
1088         }
1089         fq = &priv->fq[queue_mapping];
1090
1091         fd_len = dpaa2_fd_get_len(&fd);
1092         nq = netdev_get_tx_queue(net_dev, queue_mapping);
1093         netdev_tx_sent_queue(nq, fd_len);
1094
1095         /* Everything that happens after this enqueues might race with
1096          * the Tx confirmation callback for this frame
1097          */
1098         for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
1099                 err = priv->enqueue(priv, fq, &fd, prio, 1, NULL);
1100                 if (err != -EBUSY)
1101                         break;
1102         }
1103         percpu_extras->tx_portal_busy += i;
1104         if (unlikely(err < 0)) {
1105                 percpu_stats->tx_errors++;
1106                 /* Clean up everything, including freeing the skb */
1107                 dpaa2_eth_free_tx_fd(priv, fq, &fd, false);
1108                 netdev_tx_completed_queue(nq, 1, fd_len);
1109         } else {
1110                 percpu_stats->tx_packets++;
1111                 percpu_stats->tx_bytes += fd_len;
1112         }
1113
1114         return NETDEV_TX_OK;
1115
1116 err_build_fd:
1117         dev_kfree_skb(skb);
1118
1119         return NETDEV_TX_OK;
1120 }
1121
1122 static void dpaa2_eth_tx_onestep_tstamp(struct work_struct *work)
1123 {
1124         struct dpaa2_eth_priv *priv = container_of(work, struct dpaa2_eth_priv,
1125                                                    tx_onestep_tstamp);
1126         struct sk_buff *skb;
1127
1128         while (true) {
1129                 skb = skb_dequeue(&priv->tx_skbs);
1130                 if (!skb)
1131                         return;
1132
1133                 /* Lock just before TX one-step timestamping packet,
1134                  * and release the lock in dpaa2_eth_free_tx_fd when
1135                  * confirm the packet has been sent on hardware, or
1136                  * when clean up during transmit failure.
1137                  */
1138                 mutex_lock(&priv->onestep_tstamp_lock);
1139                 __dpaa2_eth_tx(skb, priv->net_dev);
1140         }
1141 }
1142
1143 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
1144 {
1145         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1146         u8 msgtype, twostep, udp;
1147         u16 offset1, offset2;
1148
1149         /* Utilize skb->cb[0] for timestamping request per skb */
1150         skb->cb[0] = 0;
1151
1152         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && dpaa2_ptp) {
1153                 if (priv->tx_tstamp_type == HWTSTAMP_TX_ON)
1154                         skb->cb[0] = TX_TSTAMP;
1155                 else if (priv->tx_tstamp_type == HWTSTAMP_TX_ONESTEP_SYNC)
1156                         skb->cb[0] = TX_TSTAMP_ONESTEP_SYNC;
1157         }
1158
1159         /* TX for one-step timestamping PTP Sync packet */
1160         if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
1161                 if (!dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
1162                                          &offset1, &offset2))
1163                         if (msgtype == 0 && twostep == 0) {
1164                                 skb_queue_tail(&priv->tx_skbs, skb);
1165                                 queue_work(priv->dpaa2_ptp_wq,
1166                                            &priv->tx_onestep_tstamp);
1167                                 return NETDEV_TX_OK;
1168                         }
1169                 /* Use two-step timestamping if not one-step timestamping
1170                  * PTP Sync packet
1171                  */
1172                 skb->cb[0] = TX_TSTAMP;
1173         }
1174
1175         /* TX for other packets */
1176         return __dpaa2_eth_tx(skb, net_dev);
1177 }
1178
1179 /* Tx confirmation frame processing routine */
1180 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
1181                               struct dpaa2_eth_channel *ch __always_unused,
1182                               const struct dpaa2_fd *fd,
1183                               struct dpaa2_eth_fq *fq)
1184 {
1185         struct rtnl_link_stats64 *percpu_stats;
1186         struct dpaa2_eth_drv_stats *percpu_extras;
1187         u32 fd_len = dpaa2_fd_get_len(fd);
1188         u32 fd_errors;
1189
1190         /* Tracing point */
1191         trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
1192
1193         percpu_extras = this_cpu_ptr(priv->percpu_extras);
1194         percpu_extras->tx_conf_frames++;
1195         percpu_extras->tx_conf_bytes += fd_len;
1196
1197         /* Check frame errors in the FD field */
1198         fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
1199         dpaa2_eth_free_tx_fd(priv, fq, fd, true);
1200
1201         if (likely(!fd_errors))
1202                 return;
1203
1204         if (net_ratelimit())
1205                 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
1206                            fd_errors);
1207
1208         percpu_stats = this_cpu_ptr(priv->percpu_stats);
1209         /* Tx-conf logically pertains to the egress path. */
1210         percpu_stats->tx_errors++;
1211 }
1212
1213 static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
1214 {
1215         int err;
1216
1217         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1218                                DPNI_OFF_RX_L3_CSUM, enable);
1219         if (err) {
1220                 netdev_err(priv->net_dev,
1221                            "dpni_set_offload(RX_L3_CSUM) failed\n");
1222                 return err;
1223         }
1224
1225         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1226                                DPNI_OFF_RX_L4_CSUM, enable);
1227         if (err) {
1228                 netdev_err(priv->net_dev,
1229                            "dpni_set_offload(RX_L4_CSUM) failed\n");
1230                 return err;
1231         }
1232
1233         return 0;
1234 }
1235
1236 static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
1237 {
1238         int err;
1239
1240         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1241                                DPNI_OFF_TX_L3_CSUM, enable);
1242         if (err) {
1243                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
1244                 return err;
1245         }
1246
1247         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1248                                DPNI_OFF_TX_L4_CSUM, enable);
1249         if (err) {
1250                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
1251                 return err;
1252         }
1253
1254         return 0;
1255 }
1256
1257 /* Perform a single release command to add buffers
1258  * to the specified buffer pool
1259  */
1260 static int dpaa2_eth_add_bufs(struct dpaa2_eth_priv *priv,
1261                               struct dpaa2_eth_channel *ch, u16 bpid)
1262 {
1263         struct device *dev = priv->net_dev->dev.parent;
1264         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1265         struct page *page;
1266         dma_addr_t addr;
1267         int retries = 0;
1268         int i, err;
1269
1270         for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
1271                 /* Allocate buffer visible to WRIOP + skb shared info +
1272                  * alignment padding
1273                  */
1274                 /* allocate one page for each Rx buffer. WRIOP sees
1275                  * the entire page except for a tailroom reserved for
1276                  * skb shared info
1277                  */
1278                 page = dev_alloc_pages(0);
1279                 if (!page)
1280                         goto err_alloc;
1281
1282                 addr = dma_map_page(dev, page, 0, priv->rx_buf_size,
1283                                     DMA_BIDIRECTIONAL);
1284                 if (unlikely(dma_mapping_error(dev, addr)))
1285                         goto err_map;
1286
1287                 buf_array[i] = addr;
1288
1289                 /* tracing point */
1290                 trace_dpaa2_eth_buf_seed(priv->net_dev,
1291                                          page, DPAA2_ETH_RX_BUF_RAW_SIZE,
1292                                          addr, priv->rx_buf_size,
1293                                          bpid);
1294         }
1295
1296 release_bufs:
1297         /* In case the portal is busy, retry until successful */
1298         while ((err = dpaa2_io_service_release(ch->dpio, bpid,
1299                                                buf_array, i)) == -EBUSY) {
1300                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1301                         break;
1302                 cpu_relax();
1303         }
1304
1305         /* If release command failed, clean up and bail out;
1306          * not much else we can do about it
1307          */
1308         if (err) {
1309                 dpaa2_eth_free_bufs(priv, buf_array, i);
1310                 return 0;
1311         }
1312
1313         return i;
1314
1315 err_map:
1316         __free_pages(page, 0);
1317 err_alloc:
1318         /* If we managed to allocate at least some buffers,
1319          * release them to hardware
1320          */
1321         if (i)
1322                 goto release_bufs;
1323
1324         return 0;
1325 }
1326
1327 static int dpaa2_eth_seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
1328 {
1329         int i, j;
1330         int new_count;
1331
1332         for (j = 0; j < priv->num_channels; j++) {
1333                 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
1334                      i += DPAA2_ETH_BUFS_PER_CMD) {
1335                         new_count = dpaa2_eth_add_bufs(priv, priv->channel[j], bpid);
1336                         priv->channel[j]->buf_count += new_count;
1337
1338                         if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
1339                                 return -ENOMEM;
1340                         }
1341                 }
1342         }
1343
1344         return 0;
1345 }
1346
1347 /*
1348  * Drain the specified number of buffers from the DPNI's private buffer pool.
1349  * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
1350  */
1351 static void dpaa2_eth_drain_bufs(struct dpaa2_eth_priv *priv, int count)
1352 {
1353         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1354         int retries = 0;
1355         int ret;
1356
1357         do {
1358                 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
1359                                                buf_array, count);
1360                 if (ret < 0) {
1361                         if (ret == -EBUSY &&
1362                             retries++ < DPAA2_ETH_SWP_BUSY_RETRIES)
1363                                 continue;
1364                         netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
1365                         return;
1366                 }
1367                 dpaa2_eth_free_bufs(priv, buf_array, ret);
1368                 retries = 0;
1369         } while (ret);
1370 }
1371
1372 static void dpaa2_eth_drain_pool(struct dpaa2_eth_priv *priv)
1373 {
1374         int i;
1375
1376         dpaa2_eth_drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
1377         dpaa2_eth_drain_bufs(priv, 1);
1378
1379         for (i = 0; i < priv->num_channels; i++)
1380                 priv->channel[i]->buf_count = 0;
1381 }
1382
1383 /* Function is called from softirq context only, so we don't need to guard
1384  * the access to percpu count
1385  */
1386 static int dpaa2_eth_refill_pool(struct dpaa2_eth_priv *priv,
1387                                  struct dpaa2_eth_channel *ch,
1388                                  u16 bpid)
1389 {
1390         int new_count;
1391
1392         if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
1393                 return 0;
1394
1395         do {
1396                 new_count = dpaa2_eth_add_bufs(priv, ch, bpid);
1397                 if (unlikely(!new_count)) {
1398                         /* Out of memory; abort for now, we'll try later on */
1399                         break;
1400                 }
1401                 ch->buf_count += new_count;
1402         } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
1403
1404         if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
1405                 return -ENOMEM;
1406
1407         return 0;
1408 }
1409
1410 static void dpaa2_eth_sgt_cache_drain(struct dpaa2_eth_priv *priv)
1411 {
1412         struct dpaa2_eth_sgt_cache *sgt_cache;
1413         u16 count;
1414         int k, i;
1415
1416         for_each_possible_cpu(k) {
1417                 sgt_cache = per_cpu_ptr(priv->sgt_cache, k);
1418                 count = sgt_cache->count;
1419
1420                 for (i = 0; i < count; i++)
1421                         kfree(sgt_cache->buf[i]);
1422                 sgt_cache->count = 0;
1423         }
1424 }
1425
1426 static int dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch)
1427 {
1428         int err;
1429         int dequeues = -1;
1430
1431         /* Retry while portal is busy */
1432         do {
1433                 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
1434                                                     ch->store);
1435                 dequeues++;
1436                 cpu_relax();
1437         } while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES);
1438
1439         ch->stats.dequeue_portal_busy += dequeues;
1440         if (unlikely(err))
1441                 ch->stats.pull_err++;
1442
1443         return err;
1444 }
1445
1446 /* NAPI poll routine
1447  *
1448  * Frames are dequeued from the QMan channel associated with this NAPI context.
1449  * Rx, Tx confirmation and (if configured) Rx error frames all count
1450  * towards the NAPI budget.
1451  */
1452 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
1453 {
1454         struct dpaa2_eth_channel *ch;
1455         struct dpaa2_eth_priv *priv;
1456         int rx_cleaned = 0, txconf_cleaned = 0;
1457         struct dpaa2_eth_fq *fq, *txc_fq = NULL;
1458         struct netdev_queue *nq;
1459         int store_cleaned, work_done;
1460         struct list_head rx_list;
1461         int retries = 0;
1462         u16 flowid;
1463         int err;
1464
1465         ch = container_of(napi, struct dpaa2_eth_channel, napi);
1466         ch->xdp.res = 0;
1467         priv = ch->priv;
1468
1469         INIT_LIST_HEAD(&rx_list);
1470         ch->rx_list = &rx_list;
1471
1472         do {
1473                 err = dpaa2_eth_pull_channel(ch);
1474                 if (unlikely(err))
1475                         break;
1476
1477                 /* Refill pool if appropriate */
1478                 dpaa2_eth_refill_pool(priv, ch, priv->bpid);
1479
1480                 store_cleaned = dpaa2_eth_consume_frames(ch, &fq);
1481                 if (store_cleaned <= 0)
1482                         break;
1483                 if (fq->type == DPAA2_RX_FQ) {
1484                         rx_cleaned += store_cleaned;
1485                         flowid = fq->flowid;
1486                 } else {
1487                         txconf_cleaned += store_cleaned;
1488                         /* We have a single Tx conf FQ on this channel */
1489                         txc_fq = fq;
1490                 }
1491
1492                 /* If we either consumed the whole NAPI budget with Rx frames
1493                  * or we reached the Tx confirmations threshold, we're done.
1494                  */
1495                 if (rx_cleaned >= budget ||
1496                     txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) {
1497                         work_done = budget;
1498                         goto out;
1499                 }
1500         } while (store_cleaned);
1501
1502         /* We didn't consume the entire budget, so finish napi and
1503          * re-enable data availability notifications
1504          */
1505         napi_complete_done(napi, rx_cleaned);
1506         do {
1507                 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
1508                 cpu_relax();
1509         } while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES);
1510         WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
1511                   ch->nctx.desired_cpu);
1512
1513         work_done = max(rx_cleaned, 1);
1514
1515 out:
1516         netif_receive_skb_list(ch->rx_list);
1517
1518         if (txc_fq && txc_fq->dq_frames) {
1519                 nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid);
1520                 netdev_tx_completed_queue(nq, txc_fq->dq_frames,
1521                                           txc_fq->dq_bytes);
1522                 txc_fq->dq_frames = 0;
1523                 txc_fq->dq_bytes = 0;
1524         }
1525
1526         if (ch->xdp.res & XDP_REDIRECT)
1527                 xdp_do_flush_map();
1528         else if (rx_cleaned && ch->xdp.res & XDP_TX)
1529                 dpaa2_eth_xdp_tx_flush(priv, ch, &priv->fq[flowid]);
1530
1531         return work_done;
1532 }
1533
1534 static void dpaa2_eth_enable_ch_napi(struct dpaa2_eth_priv *priv)
1535 {
1536         struct dpaa2_eth_channel *ch;
1537         int i;
1538
1539         for (i = 0; i < priv->num_channels; i++) {
1540                 ch = priv->channel[i];
1541                 napi_enable(&ch->napi);
1542         }
1543 }
1544
1545 static void dpaa2_eth_disable_ch_napi(struct dpaa2_eth_priv *priv)
1546 {
1547         struct dpaa2_eth_channel *ch;
1548         int i;
1549
1550         for (i = 0; i < priv->num_channels; i++) {
1551                 ch = priv->channel[i];
1552                 napi_disable(&ch->napi);
1553         }
1554 }
1555
1556 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
1557                                bool tx_pause, bool pfc)
1558 {
1559         struct dpni_taildrop td = {0};
1560         struct dpaa2_eth_fq *fq;
1561         int i, err;
1562
1563         /* FQ taildrop: threshold is in bytes, per frame queue. Enabled if
1564          * flow control is disabled (as it might interfere with either the
1565          * buffer pool depletion trigger for pause frames or with the group
1566          * congestion trigger for PFC frames)
1567          */
1568         td.enable = !tx_pause;
1569         if (priv->rx_fqtd_enabled == td.enable)
1570                 goto set_cgtd;
1571
1572         td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH;
1573         td.units = DPNI_CONGESTION_UNIT_BYTES;
1574
1575         for (i = 0; i < priv->num_fqs; i++) {
1576                 fq = &priv->fq[i];
1577                 if (fq->type != DPAA2_RX_FQ)
1578                         continue;
1579                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1580                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
1581                                         fq->tc, fq->flowid, &td);
1582                 if (err) {
1583                         netdev_err(priv->net_dev,
1584                                    "dpni_set_taildrop(FQ) failed\n");
1585                         return;
1586                 }
1587         }
1588
1589         priv->rx_fqtd_enabled = td.enable;
1590
1591 set_cgtd:
1592         /* Congestion group taildrop: threshold is in frames, per group
1593          * of FQs belonging to the same traffic class
1594          * Enabled if general Tx pause disabled or if PFCs are enabled
1595          * (congestion group threhsold for PFC generation is lower than the
1596          * CG taildrop threshold, so it won't interfere with it; we also
1597          * want frames in non-PFC enabled traffic classes to be kept in check)
1598          */
1599         td.enable = !tx_pause || (tx_pause && pfc);
1600         if (priv->rx_cgtd_enabled == td.enable)
1601                 return;
1602
1603         td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv);
1604         td.units = DPNI_CONGESTION_UNIT_FRAMES;
1605         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
1606                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1607                                         DPNI_CP_GROUP, DPNI_QUEUE_RX,
1608                                         i, 0, &td);
1609                 if (err) {
1610                         netdev_err(priv->net_dev,
1611                                    "dpni_set_taildrop(CG) failed\n");
1612                         return;
1613                 }
1614         }
1615
1616         priv->rx_cgtd_enabled = td.enable;
1617 }
1618
1619 static int dpaa2_eth_link_state_update(struct dpaa2_eth_priv *priv)
1620 {
1621         struct dpni_link_state state = {0};
1622         bool tx_pause;
1623         int err;
1624
1625         err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
1626         if (unlikely(err)) {
1627                 netdev_err(priv->net_dev,
1628                            "dpni_get_link_state() failed\n");
1629                 return err;
1630         }
1631
1632         /* If Tx pause frame settings have changed, we need to update
1633          * Rx FQ taildrop configuration as well. We configure taildrop
1634          * only when pause frame generation is disabled.
1635          */
1636         tx_pause = dpaa2_eth_tx_pause_enabled(state.options);
1637         dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled);
1638
1639         /* When we manage the MAC/PHY using phylink there is no need
1640          * to manually update the netif_carrier.
1641          */
1642         if (priv->mac)
1643                 goto out;
1644
1645         /* Chech link state; speed / duplex changes are not treated yet */
1646         if (priv->link_state.up == state.up)
1647                 goto out;
1648
1649         if (state.up) {
1650                 netif_carrier_on(priv->net_dev);
1651                 netif_tx_start_all_queues(priv->net_dev);
1652         } else {
1653                 netif_tx_stop_all_queues(priv->net_dev);
1654                 netif_carrier_off(priv->net_dev);
1655         }
1656
1657         netdev_info(priv->net_dev, "Link Event: state %s\n",
1658                     state.up ? "up" : "down");
1659
1660 out:
1661         priv->link_state = state;
1662
1663         return 0;
1664 }
1665
1666 static int dpaa2_eth_open(struct net_device *net_dev)
1667 {
1668         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1669         int err;
1670
1671         err = dpaa2_eth_seed_pool(priv, priv->bpid);
1672         if (err) {
1673                 /* Not much to do; the buffer pool, though not filled up,
1674                  * may still contain some buffers which would enable us
1675                  * to limp on.
1676                  */
1677                 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1678                            priv->dpbp_dev->obj_desc.id, priv->bpid);
1679         }
1680
1681         if (!priv->mac) {
1682                 /* We'll only start the txqs when the link is actually ready;
1683                  * make sure we don't race against the link up notification,
1684                  * which may come immediately after dpni_enable();
1685                  */
1686                 netif_tx_stop_all_queues(net_dev);
1687
1688                 /* Also, explicitly set carrier off, otherwise
1689                  * netif_carrier_ok() will return true and cause 'ip link show'
1690                  * to report the LOWER_UP flag, even though the link
1691                  * notification wasn't even received.
1692                  */
1693                 netif_carrier_off(net_dev);
1694         }
1695         dpaa2_eth_enable_ch_napi(priv);
1696
1697         err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1698         if (err < 0) {
1699                 netdev_err(net_dev, "dpni_enable() failed\n");
1700                 goto enable_err;
1701         }
1702
1703         if (!priv->mac) {
1704                 /* If the DPMAC object has already processed the link up
1705                  * interrupt, we have to learn the link state ourselves.
1706                  */
1707                 err = dpaa2_eth_link_state_update(priv);
1708                 if (err < 0) {
1709                         netdev_err(net_dev, "Can't update link state\n");
1710                         goto link_state_err;
1711                 }
1712         } else {
1713                 phylink_start(priv->mac->phylink);
1714         }
1715
1716         return 0;
1717
1718 link_state_err:
1719 enable_err:
1720         dpaa2_eth_disable_ch_napi(priv);
1721         dpaa2_eth_drain_pool(priv);
1722         return err;
1723 }
1724
1725 /* Total number of in-flight frames on ingress queues */
1726 static u32 dpaa2_eth_ingress_fq_count(struct dpaa2_eth_priv *priv)
1727 {
1728         struct dpaa2_eth_fq *fq;
1729         u32 fcnt = 0, bcnt = 0, total = 0;
1730         int i, err;
1731
1732         for (i = 0; i < priv->num_fqs; i++) {
1733                 fq = &priv->fq[i];
1734                 err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
1735                 if (err) {
1736                         netdev_warn(priv->net_dev, "query_fq_count failed");
1737                         break;
1738                 }
1739                 total += fcnt;
1740         }
1741
1742         return total;
1743 }
1744
1745 static void dpaa2_eth_wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv)
1746 {
1747         int retries = 10;
1748         u32 pending;
1749
1750         do {
1751                 pending = dpaa2_eth_ingress_fq_count(priv);
1752                 if (pending)
1753                         msleep(100);
1754         } while (pending && --retries);
1755 }
1756
1757 #define DPNI_TX_PENDING_VER_MAJOR       7
1758 #define DPNI_TX_PENDING_VER_MINOR       13
1759 static void dpaa2_eth_wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv)
1760 {
1761         union dpni_statistics stats;
1762         int retries = 10;
1763         int err;
1764
1765         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR,
1766                                    DPNI_TX_PENDING_VER_MINOR) < 0)
1767                 goto out;
1768
1769         do {
1770                 err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6,
1771                                           &stats);
1772                 if (err)
1773                         goto out;
1774                 if (stats.page_6.tx_pending_frames == 0)
1775                         return;
1776         } while (--retries);
1777
1778 out:
1779         msleep(500);
1780 }
1781
1782 static int dpaa2_eth_stop(struct net_device *net_dev)
1783 {
1784         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1785         int dpni_enabled = 0;
1786         int retries = 10;
1787
1788         if (!priv->mac) {
1789                 netif_tx_stop_all_queues(net_dev);
1790                 netif_carrier_off(net_dev);
1791         } else {
1792                 phylink_stop(priv->mac->phylink);
1793         }
1794
1795         /* On dpni_disable(), the MC firmware will:
1796          * - stop MAC Rx and wait for all Rx frames to be enqueued to software
1797          * - cut off WRIOP dequeues from egress FQs and wait until transmission
1798          * of all in flight Tx frames is finished (and corresponding Tx conf
1799          * frames are enqueued back to software)
1800          *
1801          * Before calling dpni_disable(), we wait for all Tx frames to arrive
1802          * on WRIOP. After it finishes, wait until all remaining frames on Rx
1803          * and Tx conf queues are consumed on NAPI poll.
1804          */
1805         dpaa2_eth_wait_for_egress_fq_empty(priv);
1806
1807         do {
1808                 dpni_disable(priv->mc_io, 0, priv->mc_token);
1809                 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1810                 if (dpni_enabled)
1811                         /* Allow the hardware some slack */
1812                         msleep(100);
1813         } while (dpni_enabled && --retries);
1814         if (!retries) {
1815                 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1816                 /* Must go on and disable NAPI nonetheless, so we don't crash at
1817                  * the next "ifconfig up"
1818                  */
1819         }
1820
1821         dpaa2_eth_wait_for_ingress_fq_empty(priv);
1822         dpaa2_eth_disable_ch_napi(priv);
1823
1824         /* Empty the buffer pool */
1825         dpaa2_eth_drain_pool(priv);
1826
1827         /* Empty the Scatter-Gather Buffer cache */
1828         dpaa2_eth_sgt_cache_drain(priv);
1829
1830         return 0;
1831 }
1832
1833 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1834 {
1835         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1836         struct device *dev = net_dev->dev.parent;
1837         int err;
1838
1839         err = eth_mac_addr(net_dev, addr);
1840         if (err < 0) {
1841                 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1842                 return err;
1843         }
1844
1845         err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1846                                         net_dev->dev_addr);
1847         if (err) {
1848                 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1849                 return err;
1850         }
1851
1852         return 0;
1853 }
1854
1855 /** Fill in counters maintained by the GPP driver. These may be different from
1856  * the hardware counters obtained by ethtool.
1857  */
1858 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1859                                 struct rtnl_link_stats64 *stats)
1860 {
1861         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1862         struct rtnl_link_stats64 *percpu_stats;
1863         u64 *cpustats;
1864         u64 *netstats = (u64 *)stats;
1865         int i, j;
1866         int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1867
1868         for_each_possible_cpu(i) {
1869                 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1870                 cpustats = (u64 *)percpu_stats;
1871                 for (j = 0; j < num; j++)
1872                         netstats[j] += cpustats[j];
1873         }
1874 }
1875
1876 /* Copy mac unicast addresses from @net_dev to @priv.
1877  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1878  */
1879 static void dpaa2_eth_add_uc_hw_addr(const struct net_device *net_dev,
1880                                      struct dpaa2_eth_priv *priv)
1881 {
1882         struct netdev_hw_addr *ha;
1883         int err;
1884
1885         netdev_for_each_uc_addr(ha, net_dev) {
1886                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1887                                         ha->addr);
1888                 if (err)
1889                         netdev_warn(priv->net_dev,
1890                                     "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1891                                     ha->addr, err);
1892         }
1893 }
1894
1895 /* Copy mac multicast addresses from @net_dev to @priv
1896  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1897  */
1898 static void dpaa2_eth_add_mc_hw_addr(const struct net_device *net_dev,
1899                                      struct dpaa2_eth_priv *priv)
1900 {
1901         struct netdev_hw_addr *ha;
1902         int err;
1903
1904         netdev_for_each_mc_addr(ha, net_dev) {
1905                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1906                                         ha->addr);
1907                 if (err)
1908                         netdev_warn(priv->net_dev,
1909                                     "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1910                                     ha->addr, err);
1911         }
1912 }
1913
1914 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1915 {
1916         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1917         int uc_count = netdev_uc_count(net_dev);
1918         int mc_count = netdev_mc_count(net_dev);
1919         u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1920         u32 options = priv->dpni_attrs.options;
1921         u16 mc_token = priv->mc_token;
1922         struct fsl_mc_io *mc_io = priv->mc_io;
1923         int err;
1924
1925         /* Basic sanity checks; these probably indicate a misconfiguration */
1926         if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1927                 netdev_info(net_dev,
1928                             "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1929                             max_mac);
1930
1931         /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1932         if (uc_count > max_mac) {
1933                 netdev_info(net_dev,
1934                             "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1935                             uc_count, max_mac);
1936                 goto force_promisc;
1937         }
1938         if (mc_count + uc_count > max_mac) {
1939                 netdev_info(net_dev,
1940                             "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1941                             uc_count + mc_count, max_mac);
1942                 goto force_mc_promisc;
1943         }
1944
1945         /* Adjust promisc settings due to flag combinations */
1946         if (net_dev->flags & IFF_PROMISC)
1947                 goto force_promisc;
1948         if (net_dev->flags & IFF_ALLMULTI) {
1949                 /* First, rebuild unicast filtering table. This should be done
1950                  * in promisc mode, in order to avoid frame loss while we
1951                  * progressively add entries to the table.
1952                  * We don't know whether we had been in promisc already, and
1953                  * making an MC call to find out is expensive; so set uc promisc
1954                  * nonetheless.
1955                  */
1956                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1957                 if (err)
1958                         netdev_warn(net_dev, "Can't set uc promisc\n");
1959
1960                 /* Actual uc table reconstruction. */
1961                 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1962                 if (err)
1963                         netdev_warn(net_dev, "Can't clear uc filters\n");
1964                 dpaa2_eth_add_uc_hw_addr(net_dev, priv);
1965
1966                 /* Finally, clear uc promisc and set mc promisc as requested. */
1967                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1968                 if (err)
1969                         netdev_warn(net_dev, "Can't clear uc promisc\n");
1970                 goto force_mc_promisc;
1971         }
1972
1973         /* Neither unicast, nor multicast promisc will be on... eventually.
1974          * For now, rebuild mac filtering tables while forcing both of them on.
1975          */
1976         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1977         if (err)
1978                 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
1979         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1980         if (err)
1981                 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
1982
1983         /* Actual mac filtering tables reconstruction */
1984         err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
1985         if (err)
1986                 netdev_warn(net_dev, "Can't clear mac filters\n");
1987         dpaa2_eth_add_mc_hw_addr(net_dev, priv);
1988         dpaa2_eth_add_uc_hw_addr(net_dev, priv);
1989
1990         /* Now we can clear both ucast and mcast promisc, without risking
1991          * to drop legitimate frames anymore.
1992          */
1993         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1994         if (err)
1995                 netdev_warn(net_dev, "Can't clear ucast promisc\n");
1996         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
1997         if (err)
1998                 netdev_warn(net_dev, "Can't clear mcast promisc\n");
1999
2000         return;
2001
2002 force_promisc:
2003         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2004         if (err)
2005                 netdev_warn(net_dev, "Can't set ucast promisc\n");
2006 force_mc_promisc:
2007         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
2008         if (err)
2009                 netdev_warn(net_dev, "Can't set mcast promisc\n");
2010 }
2011
2012 static int dpaa2_eth_set_features(struct net_device *net_dev,
2013                                   netdev_features_t features)
2014 {
2015         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2016         netdev_features_t changed = features ^ net_dev->features;
2017         bool enable;
2018         int err;
2019
2020         if (changed & NETIF_F_RXCSUM) {
2021                 enable = !!(features & NETIF_F_RXCSUM);
2022                 err = dpaa2_eth_set_rx_csum(priv, enable);
2023                 if (err)
2024                         return err;
2025         }
2026
2027         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2028                 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
2029                 err = dpaa2_eth_set_tx_csum(priv, enable);
2030                 if (err)
2031                         return err;
2032         }
2033
2034         return 0;
2035 }
2036
2037 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2038 {
2039         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2040         struct hwtstamp_config config;
2041
2042         if (!dpaa2_ptp)
2043                 return -EINVAL;
2044
2045         if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
2046                 return -EFAULT;
2047
2048         switch (config.tx_type) {
2049         case HWTSTAMP_TX_OFF:
2050         case HWTSTAMP_TX_ON:
2051         case HWTSTAMP_TX_ONESTEP_SYNC:
2052                 priv->tx_tstamp_type = config.tx_type;
2053                 break;
2054         default:
2055                 return -ERANGE;
2056         }
2057
2058         if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
2059                 priv->rx_tstamp = false;
2060         } else {
2061                 priv->rx_tstamp = true;
2062                 /* TS is set for all frame types, not only those requested */
2063                 config.rx_filter = HWTSTAMP_FILTER_ALL;
2064         }
2065
2066         return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
2067                         -EFAULT : 0;
2068 }
2069
2070 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2071 {
2072         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2073
2074         if (cmd == SIOCSHWTSTAMP)
2075                 return dpaa2_eth_ts_ioctl(dev, rq, cmd);
2076
2077         if (priv->mac)
2078                 return phylink_mii_ioctl(priv->mac->phylink, rq, cmd);
2079
2080         return -EOPNOTSUPP;
2081 }
2082
2083 static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu)
2084 {
2085         int mfl, linear_mfl;
2086
2087         mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2088         linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE -
2089                      dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM;
2090
2091         if (mfl > linear_mfl) {
2092                 netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n",
2093                             linear_mfl - VLAN_ETH_HLEN);
2094                 return false;
2095         }
2096
2097         return true;
2098 }
2099
2100 static int dpaa2_eth_set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp)
2101 {
2102         int mfl, err;
2103
2104         /* We enforce a maximum Rx frame length based on MTU only if we have
2105          * an XDP program attached (in order to avoid Rx S/G frames).
2106          * Otherwise, we accept all incoming frames as long as they are not
2107          * larger than maximum size supported in hardware
2108          */
2109         if (has_xdp)
2110                 mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2111         else
2112                 mfl = DPAA2_ETH_MFL;
2113
2114         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl);
2115         if (err) {
2116                 netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n");
2117                 return err;
2118         }
2119
2120         return 0;
2121 }
2122
2123 static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu)
2124 {
2125         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2126         int err;
2127
2128         if (!priv->xdp_prog)
2129                 goto out;
2130
2131         if (!xdp_mtu_valid(priv, new_mtu))
2132                 return -EINVAL;
2133
2134         err = dpaa2_eth_set_rx_mfl(priv, new_mtu, true);
2135         if (err)
2136                 return err;
2137
2138 out:
2139         dev->mtu = new_mtu;
2140         return 0;
2141 }
2142
2143 static int dpaa2_eth_update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp)
2144 {
2145         struct dpni_buffer_layout buf_layout = {0};
2146         int err;
2147
2148         err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token,
2149                                      DPNI_QUEUE_RX, &buf_layout);
2150         if (err) {
2151                 netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n");
2152                 return err;
2153         }
2154
2155         /* Reserve extra headroom for XDP header size changes */
2156         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) +
2157                                     (has_xdp ? XDP_PACKET_HEADROOM : 0);
2158         buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM;
2159         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2160                                      DPNI_QUEUE_RX, &buf_layout);
2161         if (err) {
2162                 netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n");
2163                 return err;
2164         }
2165
2166         return 0;
2167 }
2168
2169 static int dpaa2_eth_setup_xdp(struct net_device *dev, struct bpf_prog *prog)
2170 {
2171         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2172         struct dpaa2_eth_channel *ch;
2173         struct bpf_prog *old;
2174         bool up, need_update;
2175         int i, err;
2176
2177         if (prog && !xdp_mtu_valid(priv, dev->mtu))
2178                 return -EINVAL;
2179
2180         if (prog)
2181                 bpf_prog_add(prog, priv->num_channels);
2182
2183         up = netif_running(dev);
2184         need_update = (!!priv->xdp_prog != !!prog);
2185
2186         if (up)
2187                 dpaa2_eth_stop(dev);
2188
2189         /* While in xdp mode, enforce a maximum Rx frame size based on MTU.
2190          * Also, when switching between xdp/non-xdp modes we need to reconfigure
2191          * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
2192          * so we are sure no old format buffers will be used from now on.
2193          */
2194         if (need_update) {
2195                 err = dpaa2_eth_set_rx_mfl(priv, dev->mtu, !!prog);
2196                 if (err)
2197                         goto out_err;
2198                 err = dpaa2_eth_update_rx_buffer_headroom(priv, !!prog);
2199                 if (err)
2200                         goto out_err;
2201         }
2202
2203         old = xchg(&priv->xdp_prog, prog);
2204         if (old)
2205                 bpf_prog_put(old);
2206
2207         for (i = 0; i < priv->num_channels; i++) {
2208                 ch = priv->channel[i];
2209                 old = xchg(&ch->xdp.prog, prog);
2210                 if (old)
2211                         bpf_prog_put(old);
2212         }
2213
2214         if (up) {
2215                 err = dpaa2_eth_open(dev);
2216                 if (err)
2217                         return err;
2218         }
2219
2220         return 0;
2221
2222 out_err:
2223         if (prog)
2224                 bpf_prog_sub(prog, priv->num_channels);
2225         if (up)
2226                 dpaa2_eth_open(dev);
2227
2228         return err;
2229 }
2230
2231 static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2232 {
2233         switch (xdp->command) {
2234         case XDP_SETUP_PROG:
2235                 return dpaa2_eth_setup_xdp(dev, xdp->prog);
2236         default:
2237                 return -EINVAL;
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev,
2244                                    struct xdp_frame *xdpf,
2245                                    struct dpaa2_fd *fd)
2246 {
2247         struct device *dev = net_dev->dev.parent;
2248         unsigned int needed_headroom;
2249         struct dpaa2_eth_swa *swa;
2250         void *buffer_start, *aligned_start;
2251         dma_addr_t addr;
2252
2253         /* We require a minimum headroom to be able to transmit the frame.
2254          * Otherwise return an error and let the original net_device handle it
2255          */
2256         needed_headroom = dpaa2_eth_needed_headroom(NULL);
2257         if (xdpf->headroom < needed_headroom)
2258                 return -EINVAL;
2259
2260         /* Setup the FD fields */
2261         memset(fd, 0, sizeof(*fd));
2262
2263         /* Align FD address, if possible */
2264         buffer_start = xdpf->data - needed_headroom;
2265         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
2266                                   DPAA2_ETH_TX_BUF_ALIGN);
2267         if (aligned_start >= xdpf->data - xdpf->headroom)
2268                 buffer_start = aligned_start;
2269
2270         swa = (struct dpaa2_eth_swa *)buffer_start;
2271         /* fill in necessary fields here */
2272         swa->type = DPAA2_ETH_SWA_XDP;
2273         swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start;
2274         swa->xdp.xdpf = xdpf;
2275
2276         addr = dma_map_single(dev, buffer_start,
2277                               swa->xdp.dma_size,
2278                               DMA_BIDIRECTIONAL);
2279         if (unlikely(dma_mapping_error(dev, addr)))
2280                 return -ENOMEM;
2281
2282         dpaa2_fd_set_addr(fd, addr);
2283         dpaa2_fd_set_offset(fd, xdpf->data - buffer_start);
2284         dpaa2_fd_set_len(fd, xdpf->len);
2285         dpaa2_fd_set_format(fd, dpaa2_fd_single);
2286         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
2287
2288         return 0;
2289 }
2290
2291 static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n,
2292                               struct xdp_frame **frames, u32 flags)
2293 {
2294         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2295         struct dpaa2_eth_xdp_fds *xdp_redirect_fds;
2296         struct rtnl_link_stats64 *percpu_stats;
2297         struct dpaa2_eth_fq *fq;
2298         struct dpaa2_fd *fds;
2299         int enqueued, i, err;
2300
2301         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2302                 return -EINVAL;
2303
2304         if (!netif_running(net_dev))
2305                 return -ENETDOWN;
2306
2307         fq = &priv->fq[smp_processor_id()];
2308         xdp_redirect_fds = &fq->xdp_redirect_fds;
2309         fds = xdp_redirect_fds->fds;
2310
2311         percpu_stats = this_cpu_ptr(priv->percpu_stats);
2312
2313         /* create a FD for each xdp_frame in the list received */
2314         for (i = 0; i < n; i++) {
2315                 err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]);
2316                 if (err)
2317                         break;
2318         }
2319         xdp_redirect_fds->num = i;
2320
2321         /* enqueue all the frame descriptors */
2322         enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds);
2323
2324         /* update statistics */
2325         percpu_stats->tx_packets += enqueued;
2326         for (i = 0; i < enqueued; i++)
2327                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
2328         for (i = enqueued; i < n; i++)
2329                 xdp_return_frame_rx_napi(frames[i]);
2330
2331         return enqueued;
2332 }
2333
2334 static int update_xps(struct dpaa2_eth_priv *priv)
2335 {
2336         struct net_device *net_dev = priv->net_dev;
2337         struct cpumask xps_mask;
2338         struct dpaa2_eth_fq *fq;
2339         int i, num_queues, netdev_queues;
2340         int err = 0;
2341
2342         num_queues = dpaa2_eth_queue_count(priv);
2343         netdev_queues = (net_dev->num_tc ? : 1) * num_queues;
2344
2345         /* The first <num_queues> entries in priv->fq array are Tx/Tx conf
2346          * queues, so only process those
2347          */
2348         for (i = 0; i < netdev_queues; i++) {
2349                 fq = &priv->fq[i % num_queues];
2350
2351                 cpumask_clear(&xps_mask);
2352                 cpumask_set_cpu(fq->target_cpu, &xps_mask);
2353
2354                 err = netif_set_xps_queue(net_dev, &xps_mask, i);
2355                 if (err) {
2356                         netdev_warn_once(net_dev, "Error setting XPS queue\n");
2357                         break;
2358                 }
2359         }
2360
2361         return err;
2362 }
2363
2364 static int dpaa2_eth_setup_mqprio(struct net_device *net_dev,
2365                                   struct tc_mqprio_qopt *mqprio)
2366 {
2367         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2368         u8 num_tc, num_queues;
2369         int i;
2370
2371         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2372         num_queues = dpaa2_eth_queue_count(priv);
2373         num_tc = mqprio->num_tc;
2374
2375         if (num_tc == net_dev->num_tc)
2376                 return 0;
2377
2378         if (num_tc  > dpaa2_eth_tc_count(priv)) {
2379                 netdev_err(net_dev, "Max %d traffic classes supported\n",
2380                            dpaa2_eth_tc_count(priv));
2381                 return -EOPNOTSUPP;
2382         }
2383
2384         if (!num_tc) {
2385                 netdev_reset_tc(net_dev);
2386                 netif_set_real_num_tx_queues(net_dev, num_queues);
2387                 goto out;
2388         }
2389
2390         netdev_set_num_tc(net_dev, num_tc);
2391         netif_set_real_num_tx_queues(net_dev, num_tc * num_queues);
2392
2393         for (i = 0; i < num_tc; i++)
2394                 netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues);
2395
2396 out:
2397         update_xps(priv);
2398
2399         return 0;
2400 }
2401
2402 #define bps_to_mbits(rate) (div_u64((rate), 1000000) * 8)
2403
2404 static int dpaa2_eth_setup_tbf(struct net_device *net_dev, struct tc_tbf_qopt_offload *p)
2405 {
2406         struct tc_tbf_qopt_offload_replace_params *cfg = &p->replace_params;
2407         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2408         struct dpni_tx_shaping_cfg tx_cr_shaper = { 0 };
2409         struct dpni_tx_shaping_cfg tx_er_shaper = { 0 };
2410         int err;
2411
2412         if (p->command == TC_TBF_STATS)
2413                 return -EOPNOTSUPP;
2414
2415         /* Only per port Tx shaping */
2416         if (p->parent != TC_H_ROOT)
2417                 return -EOPNOTSUPP;
2418
2419         if (p->command == TC_TBF_REPLACE) {
2420                 if (cfg->max_size > DPAA2_ETH_MAX_BURST_SIZE) {
2421                         netdev_err(net_dev, "burst size cannot be greater than %d\n",
2422                                    DPAA2_ETH_MAX_BURST_SIZE);
2423                         return -EINVAL;
2424                 }
2425
2426                 tx_cr_shaper.max_burst_size = cfg->max_size;
2427                 /* The TBF interface is in bytes/s, whereas DPAA2 expects the
2428                  * rate in Mbits/s
2429                  */
2430                 tx_cr_shaper.rate_limit = bps_to_mbits(cfg->rate.rate_bytes_ps);
2431         }
2432
2433         err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &tx_cr_shaper,
2434                                   &tx_er_shaper, 0);
2435         if (err) {
2436                 netdev_err(net_dev, "dpni_set_tx_shaping() = %d\n", err);
2437                 return err;
2438         }
2439
2440         return 0;
2441 }
2442
2443 static int dpaa2_eth_setup_tc(struct net_device *net_dev,
2444                               enum tc_setup_type type, void *type_data)
2445 {
2446         switch (type) {
2447         case TC_SETUP_QDISC_MQPRIO:
2448                 return dpaa2_eth_setup_mqprio(net_dev, type_data);
2449         case TC_SETUP_QDISC_TBF:
2450                 return dpaa2_eth_setup_tbf(net_dev, type_data);
2451         default:
2452                 return -EOPNOTSUPP;
2453         }
2454 }
2455
2456 static const struct net_device_ops dpaa2_eth_ops = {
2457         .ndo_open = dpaa2_eth_open,
2458         .ndo_start_xmit = dpaa2_eth_tx,
2459         .ndo_stop = dpaa2_eth_stop,
2460         .ndo_set_mac_address = dpaa2_eth_set_addr,
2461         .ndo_get_stats64 = dpaa2_eth_get_stats,
2462         .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
2463         .ndo_set_features = dpaa2_eth_set_features,
2464         .ndo_do_ioctl = dpaa2_eth_ioctl,
2465         .ndo_change_mtu = dpaa2_eth_change_mtu,
2466         .ndo_bpf = dpaa2_eth_xdp,
2467         .ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
2468         .ndo_setup_tc = dpaa2_eth_setup_tc,
2469 };
2470
2471 static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx)
2472 {
2473         struct dpaa2_eth_channel *ch;
2474
2475         ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
2476
2477         /* Update NAPI statistics */
2478         ch->stats.cdan++;
2479
2480         napi_schedule(&ch->napi);
2481 }
2482
2483 /* Allocate and configure a DPCON object */
2484 static struct fsl_mc_device *dpaa2_eth_setup_dpcon(struct dpaa2_eth_priv *priv)
2485 {
2486         struct fsl_mc_device *dpcon;
2487         struct device *dev = priv->net_dev->dev.parent;
2488         int err;
2489
2490         err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
2491                                      FSL_MC_POOL_DPCON, &dpcon);
2492         if (err) {
2493                 if (err == -ENXIO)
2494                         err = -EPROBE_DEFER;
2495                 else
2496                         dev_info(dev, "Not enough DPCONs, will go on as-is\n");
2497                 return ERR_PTR(err);
2498         }
2499
2500         err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
2501         if (err) {
2502                 dev_err(dev, "dpcon_open() failed\n");
2503                 goto free;
2504         }
2505
2506         err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
2507         if (err) {
2508                 dev_err(dev, "dpcon_reset() failed\n");
2509                 goto close;
2510         }
2511
2512         err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
2513         if (err) {
2514                 dev_err(dev, "dpcon_enable() failed\n");
2515                 goto close;
2516         }
2517
2518         return dpcon;
2519
2520 close:
2521         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2522 free:
2523         fsl_mc_object_free(dpcon);
2524
2525         return ERR_PTR(err);
2526 }
2527
2528 static void dpaa2_eth_free_dpcon(struct dpaa2_eth_priv *priv,
2529                                  struct fsl_mc_device *dpcon)
2530 {
2531         dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
2532         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2533         fsl_mc_object_free(dpcon);
2534 }
2535
2536 static struct dpaa2_eth_channel *dpaa2_eth_alloc_channel(struct dpaa2_eth_priv *priv)
2537 {
2538         struct dpaa2_eth_channel *channel;
2539         struct dpcon_attr attr;
2540         struct device *dev = priv->net_dev->dev.parent;
2541         int err;
2542
2543         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2544         if (!channel)
2545                 return NULL;
2546
2547         channel->dpcon = dpaa2_eth_setup_dpcon(priv);
2548         if (IS_ERR(channel->dpcon)) {
2549                 err = PTR_ERR(channel->dpcon);
2550                 goto err_setup;
2551         }
2552
2553         err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
2554                                    &attr);
2555         if (err) {
2556                 dev_err(dev, "dpcon_get_attributes() failed\n");
2557                 goto err_get_attr;
2558         }
2559
2560         channel->dpcon_id = attr.id;
2561         channel->ch_id = attr.qbman_ch_id;
2562         channel->priv = priv;
2563
2564         return channel;
2565
2566 err_get_attr:
2567         dpaa2_eth_free_dpcon(priv, channel->dpcon);
2568 err_setup:
2569         kfree(channel);
2570         return ERR_PTR(err);
2571 }
2572
2573 static void dpaa2_eth_free_channel(struct dpaa2_eth_priv *priv,
2574                                    struct dpaa2_eth_channel *channel)
2575 {
2576         dpaa2_eth_free_dpcon(priv, channel->dpcon);
2577         kfree(channel);
2578 }
2579
2580 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
2581  * and register data availability notifications
2582  */
2583 static int dpaa2_eth_setup_dpio(struct dpaa2_eth_priv *priv)
2584 {
2585         struct dpaa2_io_notification_ctx *nctx;
2586         struct dpaa2_eth_channel *channel;
2587         struct dpcon_notification_cfg dpcon_notif_cfg;
2588         struct device *dev = priv->net_dev->dev.parent;
2589         int i, err;
2590
2591         /* We want the ability to spread ingress traffic (RX, TX conf) to as
2592          * many cores as possible, so we need one channel for each core
2593          * (unless there's fewer queues than cores, in which case the extra
2594          * channels would be wasted).
2595          * Allocate one channel per core and register it to the core's
2596          * affine DPIO. If not enough channels are available for all cores
2597          * or if some cores don't have an affine DPIO, there will be no
2598          * ingress frame processing on those cores.
2599          */
2600         cpumask_clear(&priv->dpio_cpumask);
2601         for_each_online_cpu(i) {
2602                 /* Try to allocate a channel */
2603                 channel = dpaa2_eth_alloc_channel(priv);
2604                 if (IS_ERR_OR_NULL(channel)) {
2605                         err = PTR_ERR_OR_ZERO(channel);
2606                         if (err != -EPROBE_DEFER)
2607                                 dev_info(dev,
2608                                          "No affine channel for cpu %d and above\n", i);
2609                         goto err_alloc_ch;
2610                 }
2611
2612                 priv->channel[priv->num_channels] = channel;
2613
2614                 nctx = &channel->nctx;
2615                 nctx->is_cdan = 1;
2616                 nctx->cb = dpaa2_eth_cdan_cb;
2617                 nctx->id = channel->ch_id;
2618                 nctx->desired_cpu = i;
2619
2620                 /* Register the new context */
2621                 channel->dpio = dpaa2_io_service_select(i);
2622                 err = dpaa2_io_service_register(channel->dpio, nctx, dev);
2623                 if (err) {
2624                         dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
2625                         /* If no affine DPIO for this core, there's probably
2626                          * none available for next cores either. Signal we want
2627                          * to retry later, in case the DPIO devices weren't
2628                          * probed yet.
2629                          */
2630                         err = -EPROBE_DEFER;
2631                         goto err_service_reg;
2632                 }
2633
2634                 /* Register DPCON notification with MC */
2635                 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
2636                 dpcon_notif_cfg.priority = 0;
2637                 dpcon_notif_cfg.user_ctx = nctx->qman64;
2638                 err = dpcon_set_notification(priv->mc_io, 0,
2639                                              channel->dpcon->mc_handle,
2640                                              &dpcon_notif_cfg);
2641                 if (err) {
2642                         dev_err(dev, "dpcon_set_notification failed()\n");
2643                         goto err_set_cdan;
2644                 }
2645
2646                 /* If we managed to allocate a channel and also found an affine
2647                  * DPIO for this core, add it to the final mask
2648                  */
2649                 cpumask_set_cpu(i, &priv->dpio_cpumask);
2650                 priv->num_channels++;
2651
2652                 /* Stop if we already have enough channels to accommodate all
2653                  * RX and TX conf queues
2654                  */
2655                 if (priv->num_channels == priv->dpni_attrs.num_queues)
2656                         break;
2657         }
2658
2659         return 0;
2660
2661 err_set_cdan:
2662         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2663 err_service_reg:
2664         dpaa2_eth_free_channel(priv, channel);
2665 err_alloc_ch:
2666         if (err == -EPROBE_DEFER) {
2667                 for (i = 0; i < priv->num_channels; i++) {
2668                         channel = priv->channel[i];
2669                         nctx = &channel->nctx;
2670                         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2671                         dpaa2_eth_free_channel(priv, channel);
2672                 }
2673                 priv->num_channels = 0;
2674                 return err;
2675         }
2676
2677         if (cpumask_empty(&priv->dpio_cpumask)) {
2678                 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
2679                 return -ENODEV;
2680         }
2681
2682         dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
2683                  cpumask_pr_args(&priv->dpio_cpumask));
2684
2685         return 0;
2686 }
2687
2688 static void dpaa2_eth_free_dpio(struct dpaa2_eth_priv *priv)
2689 {
2690         struct device *dev = priv->net_dev->dev.parent;
2691         struct dpaa2_eth_channel *ch;
2692         int i;
2693
2694         /* deregister CDAN notifications and free channels */
2695         for (i = 0; i < priv->num_channels; i++) {
2696                 ch = priv->channel[i];
2697                 dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev);
2698                 dpaa2_eth_free_channel(priv, ch);
2699         }
2700 }
2701
2702 static struct dpaa2_eth_channel *dpaa2_eth_get_affine_channel(struct dpaa2_eth_priv *priv,
2703                                                               int cpu)
2704 {
2705         struct device *dev = priv->net_dev->dev.parent;
2706         int i;
2707
2708         for (i = 0; i < priv->num_channels; i++)
2709                 if (priv->channel[i]->nctx.desired_cpu == cpu)
2710                         return priv->channel[i];
2711
2712         /* We should never get here. Issue a warning and return
2713          * the first channel, because it's still better than nothing
2714          */
2715         dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
2716
2717         return priv->channel[0];
2718 }
2719
2720 static void dpaa2_eth_set_fq_affinity(struct dpaa2_eth_priv *priv)
2721 {
2722         struct device *dev = priv->net_dev->dev.parent;
2723         struct dpaa2_eth_fq *fq;
2724         int rx_cpu, txc_cpu;
2725         int i;
2726
2727         /* For each FQ, pick one channel/CPU to deliver frames to.
2728          * This may well change at runtime, either through irqbalance or
2729          * through direct user intervention.
2730          */
2731         rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
2732
2733         for (i = 0; i < priv->num_fqs; i++) {
2734                 fq = &priv->fq[i];
2735                 switch (fq->type) {
2736                 case DPAA2_RX_FQ:
2737                         fq->target_cpu = rx_cpu;
2738                         rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
2739                         if (rx_cpu >= nr_cpu_ids)
2740                                 rx_cpu = cpumask_first(&priv->dpio_cpumask);
2741                         break;
2742                 case DPAA2_TX_CONF_FQ:
2743                         fq->target_cpu = txc_cpu;
2744                         txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
2745                         if (txc_cpu >= nr_cpu_ids)
2746                                 txc_cpu = cpumask_first(&priv->dpio_cpumask);
2747                         break;
2748                 default:
2749                         dev_err(dev, "Unknown FQ type: %d\n", fq->type);
2750                 }
2751                 fq->channel = dpaa2_eth_get_affine_channel(priv, fq->target_cpu);
2752         }
2753
2754         update_xps(priv);
2755 }
2756
2757 static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv)
2758 {
2759         int i, j;
2760
2761         /* We have one TxConf FQ per Tx flow.
2762          * The number of Tx and Rx queues is the same.
2763          * Tx queues come first in the fq array.
2764          */
2765         for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2766                 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
2767                 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
2768                 priv->fq[priv->num_fqs++].flowid = (u16)i;
2769         }
2770
2771         for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2772                 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2773                         priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
2774                         priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
2775                         priv->fq[priv->num_fqs].tc = (u8)j;
2776                         priv->fq[priv->num_fqs++].flowid = (u16)i;
2777                 }
2778         }
2779
2780         /* For each FQ, decide on which core to process incoming frames */
2781         dpaa2_eth_set_fq_affinity(priv);
2782 }
2783
2784 /* Allocate and configure one buffer pool for each interface */
2785 static int dpaa2_eth_setup_dpbp(struct dpaa2_eth_priv *priv)
2786 {
2787         int err;
2788         struct fsl_mc_device *dpbp_dev;
2789         struct device *dev = priv->net_dev->dev.parent;
2790         struct dpbp_attr dpbp_attrs;
2791
2792         err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
2793                                      &dpbp_dev);
2794         if (err) {
2795                 if (err == -ENXIO)
2796                         err = -EPROBE_DEFER;
2797                 else
2798                         dev_err(dev, "DPBP device allocation failed\n");
2799                 return err;
2800         }
2801
2802         priv->dpbp_dev = dpbp_dev;
2803
2804         err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
2805                         &dpbp_dev->mc_handle);
2806         if (err) {
2807                 dev_err(dev, "dpbp_open() failed\n");
2808                 goto err_open;
2809         }
2810
2811         err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
2812         if (err) {
2813                 dev_err(dev, "dpbp_reset() failed\n");
2814                 goto err_reset;
2815         }
2816
2817         err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
2818         if (err) {
2819                 dev_err(dev, "dpbp_enable() failed\n");
2820                 goto err_enable;
2821         }
2822
2823         err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
2824                                   &dpbp_attrs);
2825         if (err) {
2826                 dev_err(dev, "dpbp_get_attributes() failed\n");
2827                 goto err_get_attr;
2828         }
2829         priv->bpid = dpbp_attrs.bpid;
2830
2831         return 0;
2832
2833 err_get_attr:
2834         dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
2835 err_enable:
2836 err_reset:
2837         dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
2838 err_open:
2839         fsl_mc_object_free(dpbp_dev);
2840
2841         return err;
2842 }
2843
2844 static void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv)
2845 {
2846         dpaa2_eth_drain_pool(priv);
2847         dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2848         dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2849         fsl_mc_object_free(priv->dpbp_dev);
2850 }
2851
2852 static int dpaa2_eth_set_buffer_layout(struct dpaa2_eth_priv *priv)
2853 {
2854         struct device *dev = priv->net_dev->dev.parent;
2855         struct dpni_buffer_layout buf_layout = {0};
2856         u16 rx_buf_align;
2857         int err;
2858
2859         /* We need to check for WRIOP version 1.0.0, but depending on the MC
2860          * version, this number is not always provided correctly on rev1.
2861          * We need to check for both alternatives in this situation.
2862          */
2863         if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
2864             priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
2865                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
2866         else
2867                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
2868
2869         /* We need to ensure that the buffer size seen by WRIOP is a multiple
2870          * of 64 or 256 bytes depending on the WRIOP version.
2871          */
2872         priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align);
2873
2874         /* tx buffer */
2875         buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
2876         buf_layout.pass_timestamp = true;
2877         buf_layout.pass_frame_status = true;
2878         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
2879                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
2880                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2881         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2882                                      DPNI_QUEUE_TX, &buf_layout);
2883         if (err) {
2884                 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
2885                 return err;
2886         }
2887
2888         /* tx-confirm buffer */
2889         buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
2890                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2891         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2892                                      DPNI_QUEUE_TX_CONFIRM, &buf_layout);
2893         if (err) {
2894                 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
2895                 return err;
2896         }
2897
2898         /* Now that we've set our tx buffer layout, retrieve the minimum
2899          * required tx data offset.
2900          */
2901         err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
2902                                       &priv->tx_data_offset);
2903         if (err) {
2904                 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
2905                 return err;
2906         }
2907
2908         if ((priv->tx_data_offset % 64) != 0)
2909                 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
2910                          priv->tx_data_offset);
2911
2912         /* rx buffer */
2913         buf_layout.pass_frame_status = true;
2914         buf_layout.pass_parser_result = true;
2915         buf_layout.data_align = rx_buf_align;
2916         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
2917         buf_layout.private_data_size = 0;
2918         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
2919                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2920                              DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
2921                              DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
2922                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2923         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2924                                      DPNI_QUEUE_RX, &buf_layout);
2925         if (err) {
2926                 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
2927                 return err;
2928         }
2929
2930         return 0;
2931 }
2932
2933 #define DPNI_ENQUEUE_FQID_VER_MAJOR     7
2934 #define DPNI_ENQUEUE_FQID_VER_MINOR     9
2935
2936 static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv,
2937                                        struct dpaa2_eth_fq *fq,
2938                                        struct dpaa2_fd *fd, u8 prio,
2939                                        u32 num_frames __always_unused,
2940                                        int *frames_enqueued)
2941 {
2942         int err;
2943
2944         err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
2945                                           priv->tx_qdid, prio,
2946                                           fq->tx_qdbin, fd);
2947         if (!err && frames_enqueued)
2948                 *frames_enqueued = 1;
2949         return err;
2950 }
2951
2952 static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv,
2953                                                 struct dpaa2_eth_fq *fq,
2954                                                 struct dpaa2_fd *fd,
2955                                                 u8 prio, u32 num_frames,
2956                                                 int *frames_enqueued)
2957 {
2958         int err;
2959
2960         err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio,
2961                                                    fq->tx_fqid[prio],
2962                                                    fd, num_frames);
2963
2964         if (err == 0)
2965                 return -EBUSY;
2966
2967         if (frames_enqueued)
2968                 *frames_enqueued = err;
2969         return 0;
2970 }
2971
2972 static void dpaa2_eth_set_enqueue_mode(struct dpaa2_eth_priv *priv)
2973 {
2974         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
2975                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
2976                 priv->enqueue = dpaa2_eth_enqueue_qd;
2977         else
2978                 priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
2979 }
2980
2981 static int dpaa2_eth_set_pause(struct dpaa2_eth_priv *priv)
2982 {
2983         struct device *dev = priv->net_dev->dev.parent;
2984         struct dpni_link_cfg link_cfg = {0};
2985         int err;
2986
2987         /* Get the default link options so we don't override other flags */
2988         err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2989         if (err) {
2990                 dev_err(dev, "dpni_get_link_cfg() failed\n");
2991                 return err;
2992         }
2993
2994         /* By default, enable both Rx and Tx pause frames */
2995         link_cfg.options |= DPNI_LINK_OPT_PAUSE;
2996         link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2997         err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2998         if (err) {
2999                 dev_err(dev, "dpni_set_link_cfg() failed\n");
3000                 return err;
3001         }
3002
3003         priv->link_state.options = link_cfg.options;
3004
3005         return 0;
3006 }
3007
3008 static void dpaa2_eth_update_tx_fqids(struct dpaa2_eth_priv *priv)
3009 {
3010         struct dpni_queue_id qid = {0};
3011         struct dpaa2_eth_fq *fq;
3012         struct dpni_queue queue;
3013         int i, j, err;
3014
3015         /* We only use Tx FQIDs for FQID-based enqueue, so check
3016          * if DPNI version supports it before updating FQIDs
3017          */
3018         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
3019                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
3020                 return;
3021
3022         for (i = 0; i < priv->num_fqs; i++) {
3023                 fq = &priv->fq[i];
3024                 if (fq->type != DPAA2_TX_CONF_FQ)
3025                         continue;
3026                 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
3027                         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3028                                              DPNI_QUEUE_TX, j, fq->flowid,
3029                                              &queue, &qid);
3030                         if (err)
3031                                 goto out_err;
3032
3033                         fq->tx_fqid[j] = qid.fqid;
3034                         if (fq->tx_fqid[j] == 0)
3035                                 goto out_err;
3036                 }
3037         }
3038
3039         priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
3040
3041         return;
3042
3043 out_err:
3044         netdev_info(priv->net_dev,
3045                     "Error reading Tx FQID, fallback to QDID-based enqueue\n");
3046         priv->enqueue = dpaa2_eth_enqueue_qd;
3047 }
3048
3049 /* Configure ingress classification based on VLAN PCP */
3050 static int dpaa2_eth_set_vlan_qos(struct dpaa2_eth_priv *priv)
3051 {
3052         struct device *dev = priv->net_dev->dev.parent;
3053         struct dpkg_profile_cfg kg_cfg = {0};
3054         struct dpni_qos_tbl_cfg qos_cfg = {0};
3055         struct dpni_rule_cfg key_params;
3056         void *dma_mem, *key, *mask;
3057         u8 key_size = 2;        /* VLAN TCI field */
3058         int i, pcp, err;
3059
3060         /* VLAN-based classification only makes sense if we have multiple
3061          * traffic classes.
3062          * Also, we need to extract just the 3-bit PCP field from the VLAN
3063          * header and we can only do that by using a mask
3064          */
3065         if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) {
3066                 dev_dbg(dev, "VLAN-based QoS classification not supported\n");
3067                 return -EOPNOTSUPP;
3068         }
3069
3070         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3071         if (!dma_mem)
3072                 return -ENOMEM;
3073
3074         kg_cfg.num_extracts = 1;
3075         kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
3076         kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
3077         kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
3078         kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
3079
3080         err = dpni_prepare_key_cfg(&kg_cfg, dma_mem);
3081         if (err) {
3082                 dev_err(dev, "dpni_prepare_key_cfg failed\n");
3083                 goto out_free_tbl;
3084         }
3085
3086         /* set QoS table */
3087         qos_cfg.default_tc = 0;
3088         qos_cfg.discard_on_miss = 0;
3089         qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
3090                                               DPAA2_CLASSIFIER_DMA_SIZE,
3091                                               DMA_TO_DEVICE);
3092         if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
3093                 dev_err(dev, "QoS table DMA mapping failed\n");
3094                 err = -ENOMEM;
3095                 goto out_free_tbl;
3096         }
3097
3098         err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
3099         if (err) {
3100                 dev_err(dev, "dpni_set_qos_table failed\n");
3101                 goto out_unmap_tbl;
3102         }
3103
3104         /* Add QoS table entries */
3105         key = kzalloc(key_size * 2, GFP_KERNEL);
3106         if (!key) {
3107                 err = -ENOMEM;
3108                 goto out_unmap_tbl;
3109         }
3110         mask = key + key_size;
3111         *(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK);
3112
3113         key_params.key_iova = dma_map_single(dev, key, key_size * 2,
3114                                              DMA_TO_DEVICE);
3115         if (dma_mapping_error(dev, key_params.key_iova)) {
3116                 dev_err(dev, "Qos table entry DMA mapping failed\n");
3117                 err = -ENOMEM;
3118                 goto out_free_key;
3119         }
3120
3121         key_params.mask_iova = key_params.key_iova + key_size;
3122         key_params.key_size = key_size;
3123
3124         /* We add rules for PCP-based distribution starting with highest
3125          * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic
3126          * classes to accommodate all priority levels, the lowest ones end up
3127          * on TC 0 which was configured as default
3128          */
3129         for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) {
3130                 *(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT);
3131                 dma_sync_single_for_device(dev, key_params.key_iova,
3132                                            key_size * 2, DMA_TO_DEVICE);
3133
3134                 err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
3135                                          &key_params, i, i);
3136                 if (err) {
3137                         dev_err(dev, "dpni_add_qos_entry failed\n");
3138                         dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token);
3139                         goto out_unmap_key;
3140                 }
3141         }
3142
3143         priv->vlan_cls_enabled = true;
3144
3145         /* Table and key memory is not persistent, clean everything up after
3146          * configuration is finished
3147          */
3148 out_unmap_key:
3149         dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE);
3150 out_free_key:
3151         kfree(key);
3152 out_unmap_tbl:
3153         dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3154                          DMA_TO_DEVICE);
3155 out_free_tbl:
3156         kfree(dma_mem);
3157
3158         return err;
3159 }
3160
3161 /* Configure the DPNI object this interface is associated with */
3162 static int dpaa2_eth_setup_dpni(struct fsl_mc_device *ls_dev)
3163 {
3164         struct device *dev = &ls_dev->dev;
3165         struct dpaa2_eth_priv *priv;
3166         struct net_device *net_dev;
3167         int err;
3168
3169         net_dev = dev_get_drvdata(dev);
3170         priv = netdev_priv(net_dev);
3171
3172         /* get a handle for the DPNI object */
3173         err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
3174         if (err) {
3175                 dev_err(dev, "dpni_open() failed\n");
3176                 return err;
3177         }
3178
3179         /* Check if we can work with this DPNI object */
3180         err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
3181                                    &priv->dpni_ver_minor);
3182         if (err) {
3183                 dev_err(dev, "dpni_get_api_version() failed\n");
3184                 goto close;
3185         }
3186         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
3187                 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
3188                         priv->dpni_ver_major, priv->dpni_ver_minor,
3189                         DPNI_VER_MAJOR, DPNI_VER_MINOR);
3190                 err = -ENOTSUPP;
3191                 goto close;
3192         }
3193
3194         ls_dev->mc_io = priv->mc_io;
3195         ls_dev->mc_handle = priv->mc_token;
3196
3197         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3198         if (err) {
3199                 dev_err(dev, "dpni_reset() failed\n");
3200                 goto close;
3201         }
3202
3203         err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
3204                                   &priv->dpni_attrs);
3205         if (err) {
3206                 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
3207                 goto close;
3208         }
3209
3210         err = dpaa2_eth_set_buffer_layout(priv);
3211         if (err)
3212                 goto close;
3213
3214         dpaa2_eth_set_enqueue_mode(priv);
3215
3216         /* Enable pause frame support */
3217         if (dpaa2_eth_has_pause_support(priv)) {
3218                 err = dpaa2_eth_set_pause(priv);
3219                 if (err)
3220                         goto close;
3221         }
3222
3223         err = dpaa2_eth_set_vlan_qos(priv);
3224         if (err && err != -EOPNOTSUPP)
3225                 goto close;
3226
3227         priv->cls_rules = devm_kcalloc(dev, dpaa2_eth_fs_count(priv),
3228                                        sizeof(struct dpaa2_eth_cls_rule),
3229                                        GFP_KERNEL);
3230         if (!priv->cls_rules) {
3231                 err = -ENOMEM;
3232                 goto close;
3233         }
3234
3235         return 0;
3236
3237 close:
3238         dpni_close(priv->mc_io, 0, priv->mc_token);
3239
3240         return err;
3241 }
3242
3243 static void dpaa2_eth_free_dpni(struct dpaa2_eth_priv *priv)
3244 {
3245         int err;
3246
3247         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3248         if (err)
3249                 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
3250                             err);
3251
3252         dpni_close(priv->mc_io, 0, priv->mc_token);
3253 }
3254
3255 static int dpaa2_eth_setup_rx_flow(struct dpaa2_eth_priv *priv,
3256                                    struct dpaa2_eth_fq *fq)
3257 {
3258         struct device *dev = priv->net_dev->dev.parent;
3259         struct dpni_queue queue;
3260         struct dpni_queue_id qid;
3261         int err;
3262
3263         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3264                              DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
3265         if (err) {
3266                 dev_err(dev, "dpni_get_queue(RX) failed\n");
3267                 return err;
3268         }
3269
3270         fq->fqid = qid.fqid;
3271
3272         queue.destination.id = fq->channel->dpcon_id;
3273         queue.destination.type = DPNI_DEST_DPCON;
3274         queue.destination.priority = 1;
3275         queue.user_context = (u64)(uintptr_t)fq;
3276         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3277                              DPNI_QUEUE_RX, fq->tc, fq->flowid,
3278                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3279                              &queue);
3280         if (err) {
3281                 dev_err(dev, "dpni_set_queue(RX) failed\n");
3282                 return err;
3283         }
3284
3285         /* xdp_rxq setup */
3286         /* only once for each channel */
3287         if (fq->tc > 0)
3288                 return 0;
3289
3290         err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev,
3291                                fq->flowid);
3292         if (err) {
3293                 dev_err(dev, "xdp_rxq_info_reg failed\n");
3294                 return err;
3295         }
3296
3297         err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq,
3298                                          MEM_TYPE_PAGE_ORDER0, NULL);
3299         if (err) {
3300                 dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n");
3301                 return err;
3302         }
3303
3304         return 0;
3305 }
3306
3307 static int dpaa2_eth_setup_tx_flow(struct dpaa2_eth_priv *priv,
3308                                    struct dpaa2_eth_fq *fq)
3309 {
3310         struct device *dev = priv->net_dev->dev.parent;
3311         struct dpni_queue queue;
3312         struct dpni_queue_id qid;
3313         int i, err;
3314
3315         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3316                 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3317                                      DPNI_QUEUE_TX, i, fq->flowid,
3318                                      &queue, &qid);
3319                 if (err) {
3320                         dev_err(dev, "dpni_get_queue(TX) failed\n");
3321                         return err;
3322                 }
3323                 fq->tx_fqid[i] = qid.fqid;
3324         }
3325
3326         /* All Tx queues belonging to the same flowid have the same qdbin */
3327         fq->tx_qdbin = qid.qdbin;
3328
3329         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3330                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3331                              &queue, &qid);
3332         if (err) {
3333                 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
3334                 return err;
3335         }
3336
3337         fq->fqid = qid.fqid;
3338
3339         queue.destination.id = fq->channel->dpcon_id;
3340         queue.destination.type = DPNI_DEST_DPCON;
3341         queue.destination.priority = 0;
3342         queue.user_context = (u64)(uintptr_t)fq;
3343         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3344                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3345                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3346                              &queue);
3347         if (err) {
3348                 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
3349                 return err;
3350         }
3351
3352         return 0;
3353 }
3354
3355 /* Supported header fields for Rx hash distribution key */
3356 static const struct dpaa2_eth_dist_fields dist_fields[] = {
3357         {
3358                 /* L2 header */
3359                 .rxnfc_field = RXH_L2DA,
3360                 .cls_prot = NET_PROT_ETH,
3361                 .cls_field = NH_FLD_ETH_DA,
3362                 .id = DPAA2_ETH_DIST_ETHDST,
3363                 .size = 6,
3364         }, {
3365                 .cls_prot = NET_PROT_ETH,
3366                 .cls_field = NH_FLD_ETH_SA,
3367                 .id = DPAA2_ETH_DIST_ETHSRC,
3368                 .size = 6,
3369         }, {
3370                 /* This is the last ethertype field parsed:
3371                  * depending on frame format, it can be the MAC ethertype
3372                  * or the VLAN etype.
3373                  */
3374                 .cls_prot = NET_PROT_ETH,
3375                 .cls_field = NH_FLD_ETH_TYPE,
3376                 .id = DPAA2_ETH_DIST_ETHTYPE,
3377                 .size = 2,
3378         }, {
3379                 /* VLAN header */
3380                 .rxnfc_field = RXH_VLAN,
3381                 .cls_prot = NET_PROT_VLAN,
3382                 .cls_field = NH_FLD_VLAN_TCI,
3383                 .id = DPAA2_ETH_DIST_VLAN,
3384                 .size = 2,
3385         }, {
3386                 /* IP header */
3387                 .rxnfc_field = RXH_IP_SRC,
3388                 .cls_prot = NET_PROT_IP,
3389                 .cls_field = NH_FLD_IP_SRC,
3390                 .id = DPAA2_ETH_DIST_IPSRC,
3391                 .size = 4,
3392         }, {
3393                 .rxnfc_field = RXH_IP_DST,
3394                 .cls_prot = NET_PROT_IP,
3395                 .cls_field = NH_FLD_IP_DST,
3396                 .id = DPAA2_ETH_DIST_IPDST,
3397                 .size = 4,
3398         }, {
3399                 .rxnfc_field = RXH_L3_PROTO,
3400                 .cls_prot = NET_PROT_IP,
3401                 .cls_field = NH_FLD_IP_PROTO,
3402                 .id = DPAA2_ETH_DIST_IPPROTO,
3403                 .size = 1,
3404         }, {
3405                 /* Using UDP ports, this is functionally equivalent to raw
3406                  * byte pairs from L4 header.
3407                  */
3408                 .rxnfc_field = RXH_L4_B_0_1,
3409                 .cls_prot = NET_PROT_UDP,
3410                 .cls_field = NH_FLD_UDP_PORT_SRC,
3411                 .id = DPAA2_ETH_DIST_L4SRC,
3412                 .size = 2,
3413         }, {
3414                 .rxnfc_field = RXH_L4_B_2_3,
3415                 .cls_prot = NET_PROT_UDP,
3416                 .cls_field = NH_FLD_UDP_PORT_DST,
3417                 .id = DPAA2_ETH_DIST_L4DST,
3418                 .size = 2,
3419         },
3420 };
3421
3422 /* Configure the Rx hash key using the legacy API */
3423 static int dpaa2_eth_config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3424 {
3425         struct device *dev = priv->net_dev->dev.parent;
3426         struct dpni_rx_tc_dist_cfg dist_cfg;
3427         int i, err = 0;
3428
3429         memset(&dist_cfg, 0, sizeof(dist_cfg));
3430
3431         dist_cfg.key_cfg_iova = key;
3432         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3433         dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
3434
3435         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3436                 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token,
3437                                           i, &dist_cfg);
3438                 if (err) {
3439                         dev_err(dev, "dpni_set_rx_tc_dist failed\n");
3440                         break;
3441                 }
3442         }
3443
3444         return err;
3445 }
3446
3447 /* Configure the Rx hash key using the new API */
3448 static int dpaa2_eth_config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3449 {
3450         struct device *dev = priv->net_dev->dev.parent;
3451         struct dpni_rx_dist_cfg dist_cfg;
3452         int i, err = 0;
3453
3454         memset(&dist_cfg, 0, sizeof(dist_cfg));
3455
3456         dist_cfg.key_cfg_iova = key;
3457         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3458         dist_cfg.enable = 1;
3459
3460         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3461                 dist_cfg.tc = i;
3462                 err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token,
3463                                             &dist_cfg);
3464                 if (err) {
3465                         dev_err(dev, "dpni_set_rx_hash_dist failed\n");
3466                         break;
3467                 }
3468         }
3469
3470         return err;
3471 }
3472
3473 /* Configure the Rx flow classification key */
3474 static int dpaa2_eth_config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3475 {
3476         struct device *dev = priv->net_dev->dev.parent;
3477         struct dpni_rx_dist_cfg dist_cfg;
3478         int i, err = 0;
3479
3480         memset(&dist_cfg, 0, sizeof(dist_cfg));
3481
3482         dist_cfg.key_cfg_iova = key;
3483         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3484         dist_cfg.enable = 1;
3485
3486         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3487                 dist_cfg.tc = i;
3488                 err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token,
3489                                           &dist_cfg);
3490                 if (err) {
3491                         dev_err(dev, "dpni_set_rx_fs_dist failed\n");
3492                         break;
3493                 }
3494         }
3495
3496         return err;
3497 }
3498
3499 /* Size of the Rx flow classification key */
3500 int dpaa2_eth_cls_key_size(u64 fields)
3501 {
3502         int i, size = 0;
3503
3504         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3505                 if (!(fields & dist_fields[i].id))
3506                         continue;
3507                 size += dist_fields[i].size;
3508         }
3509
3510         return size;
3511 }
3512
3513 /* Offset of header field in Rx classification key */
3514 int dpaa2_eth_cls_fld_off(int prot, int field)
3515 {
3516         int i, off = 0;
3517
3518         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3519                 if (dist_fields[i].cls_prot == prot &&
3520                     dist_fields[i].cls_field == field)
3521                         return off;
3522                 off += dist_fields[i].size;
3523         }
3524
3525         WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n");
3526         return 0;
3527 }
3528
3529 /* Prune unused fields from the classification rule.
3530  * Used when masking is not supported
3531  */
3532 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields)
3533 {
3534         int off = 0, new_off = 0;
3535         int i, size;
3536
3537         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3538                 size = dist_fields[i].size;
3539                 if (dist_fields[i].id & fields) {
3540                         memcpy(key_mem + new_off, key_mem + off, size);
3541                         new_off += size;
3542                 }
3543                 off += size;
3544         }
3545 }
3546
3547 /* Set Rx distribution (hash or flow classification) key
3548  * flags is a combination of RXH_ bits
3549  */
3550 static int dpaa2_eth_set_dist_key(struct net_device *net_dev,
3551                                   enum dpaa2_eth_rx_dist type, u64 flags)
3552 {
3553         struct device *dev = net_dev->dev.parent;
3554         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3555         struct dpkg_profile_cfg cls_cfg;
3556         u32 rx_hash_fields = 0;
3557         dma_addr_t key_iova;
3558         u8 *dma_mem;
3559         int i;
3560         int err = 0;
3561
3562         memset(&cls_cfg, 0, sizeof(cls_cfg));
3563
3564         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3565                 struct dpkg_extract *key =
3566                         &cls_cfg.extracts[cls_cfg.num_extracts];
3567
3568                 /* For both Rx hashing and classification keys
3569                  * we set only the selected fields.
3570                  */
3571                 if (!(flags & dist_fields[i].id))
3572                         continue;
3573                 if (type == DPAA2_ETH_RX_DIST_HASH)
3574                         rx_hash_fields |= dist_fields[i].rxnfc_field;
3575
3576                 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
3577                         dev_err(dev, "error adding key extraction rule, too many rules?\n");
3578                         return -E2BIG;
3579                 }
3580
3581                 key->type = DPKG_EXTRACT_FROM_HDR;
3582                 key->extract.from_hdr.prot = dist_fields[i].cls_prot;
3583                 key->extract.from_hdr.type = DPKG_FULL_FIELD;
3584                 key->extract.from_hdr.field = dist_fields[i].cls_field;
3585                 cls_cfg.num_extracts++;
3586         }
3587
3588         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3589         if (!dma_mem)
3590                 return -ENOMEM;
3591
3592         err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
3593         if (err) {
3594                 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
3595                 goto free_key;
3596         }
3597
3598         /* Prepare for setting the rx dist */
3599         key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE,
3600                                   DMA_TO_DEVICE);
3601         if (dma_mapping_error(dev, key_iova)) {
3602                 dev_err(dev, "DMA mapping failed\n");
3603                 err = -ENOMEM;
3604                 goto free_key;
3605         }
3606
3607         if (type == DPAA2_ETH_RX_DIST_HASH) {
3608                 if (dpaa2_eth_has_legacy_dist(priv))
3609                         err = dpaa2_eth_config_legacy_hash_key(priv, key_iova);
3610                 else
3611                         err = dpaa2_eth_config_hash_key(priv, key_iova);
3612         } else {
3613                 err = dpaa2_eth_config_cls_key(priv, key_iova);
3614         }
3615
3616         dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3617                          DMA_TO_DEVICE);
3618         if (!err && type == DPAA2_ETH_RX_DIST_HASH)
3619                 priv->rx_hash_fields = rx_hash_fields;
3620
3621 free_key:
3622         kfree(dma_mem);
3623         return err;
3624 }
3625
3626 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
3627 {
3628         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3629         u64 key = 0;
3630         int i;
3631
3632         if (!dpaa2_eth_hash_enabled(priv))
3633                 return -EOPNOTSUPP;
3634
3635         for (i = 0; i < ARRAY_SIZE(dist_fields); i++)
3636                 if (dist_fields[i].rxnfc_field & flags)
3637                         key |= dist_fields[i].id;
3638
3639         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key);
3640 }
3641
3642 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags)
3643 {
3644         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags);
3645 }
3646
3647 static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv)
3648 {
3649         struct device *dev = priv->net_dev->dev.parent;
3650         int err;
3651
3652         /* Check if we actually support Rx flow classification */
3653         if (dpaa2_eth_has_legacy_dist(priv)) {
3654                 dev_dbg(dev, "Rx cls not supported by current MC version\n");
3655                 return -EOPNOTSUPP;
3656         }
3657
3658         if (!dpaa2_eth_fs_enabled(priv)) {
3659                 dev_dbg(dev, "Rx cls disabled in DPNI options\n");
3660                 return -EOPNOTSUPP;
3661         }
3662
3663         if (!dpaa2_eth_hash_enabled(priv)) {
3664                 dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n");
3665                 return -EOPNOTSUPP;
3666         }
3667
3668         /* If there is no support for masking in the classification table,
3669          * we don't set a default key, as it will depend on the rules
3670          * added by the user at runtime.
3671          */
3672         if (!dpaa2_eth_fs_mask_enabled(priv))
3673                 goto out;
3674
3675         err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL);
3676         if (err)
3677                 return err;
3678
3679 out:
3680         priv->rx_cls_enabled = 1;
3681
3682         return 0;
3683 }
3684
3685 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
3686  * frame queues and channels
3687  */
3688 static int dpaa2_eth_bind_dpni(struct dpaa2_eth_priv *priv)
3689 {
3690         struct net_device *net_dev = priv->net_dev;
3691         struct device *dev = net_dev->dev.parent;
3692         struct dpni_pools_cfg pools_params;
3693         struct dpni_error_cfg err_cfg;
3694         int err = 0;
3695         int i;
3696
3697         pools_params.num_dpbp = 1;
3698         pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
3699         pools_params.pools[0].backup_pool = 0;
3700         pools_params.pools[0].buffer_size = priv->rx_buf_size;
3701         err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
3702         if (err) {
3703                 dev_err(dev, "dpni_set_pools() failed\n");
3704                 return err;
3705         }
3706
3707         /* have the interface implicitly distribute traffic based on
3708          * the default hash key
3709          */
3710         err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
3711         if (err && err != -EOPNOTSUPP)
3712                 dev_err(dev, "Failed to configure hashing\n");
3713
3714         /* Configure the flow classification key; it includes all
3715          * supported header fields and cannot be modified at runtime
3716          */
3717         err = dpaa2_eth_set_default_cls(priv);
3718         if (err && err != -EOPNOTSUPP)
3719                 dev_err(dev, "Failed to configure Rx classification key\n");
3720
3721         /* Configure handling of error frames */
3722         err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
3723         err_cfg.set_frame_annotation = 1;
3724         err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
3725         err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
3726                                        &err_cfg);
3727         if (err) {
3728                 dev_err(dev, "dpni_set_errors_behavior failed\n");
3729                 return err;
3730         }
3731
3732         /* Configure Rx and Tx conf queues to generate CDANs */
3733         for (i = 0; i < priv->num_fqs; i++) {
3734                 switch (priv->fq[i].type) {
3735                 case DPAA2_RX_FQ:
3736                         err = dpaa2_eth_setup_rx_flow(priv, &priv->fq[i]);
3737                         break;
3738                 case DPAA2_TX_CONF_FQ:
3739                         err = dpaa2_eth_setup_tx_flow(priv, &priv->fq[i]);
3740                         break;
3741                 default:
3742                         dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
3743                         return -EINVAL;
3744                 }
3745                 if (err)
3746                         return err;
3747         }
3748
3749         err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
3750                             DPNI_QUEUE_TX, &priv->tx_qdid);
3751         if (err) {
3752                 dev_err(dev, "dpni_get_qdid() failed\n");
3753                 return err;
3754         }
3755
3756         return 0;
3757 }
3758
3759 /* Allocate rings for storing incoming frame descriptors */
3760 static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv)
3761 {
3762         struct net_device *net_dev = priv->net_dev;
3763         struct device *dev = net_dev->dev.parent;
3764         int i;
3765
3766         for (i = 0; i < priv->num_channels; i++) {
3767                 priv->channel[i]->store =
3768                         dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
3769                 if (!priv->channel[i]->store) {
3770                         netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
3771                         goto err_ring;
3772                 }
3773         }
3774
3775         return 0;
3776
3777 err_ring:
3778         for (i = 0; i < priv->num_channels; i++) {
3779                 if (!priv->channel[i]->store)
3780                         break;
3781                 dpaa2_io_store_destroy(priv->channel[i]->store);
3782         }
3783
3784         return -ENOMEM;
3785 }
3786
3787 static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv)
3788 {
3789         int i;
3790
3791         for (i = 0; i < priv->num_channels; i++)
3792                 dpaa2_io_store_destroy(priv->channel[i]->store);
3793 }
3794
3795 static int dpaa2_eth_set_mac_addr(struct dpaa2_eth_priv *priv)
3796 {
3797         struct net_device *net_dev = priv->net_dev;
3798         struct device *dev = net_dev->dev.parent;
3799         u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
3800         int err;
3801
3802         /* Get firmware address, if any */
3803         err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
3804         if (err) {
3805                 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
3806                 return err;
3807         }
3808
3809         /* Get DPNI attributes address, if any */
3810         err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3811                                         dpni_mac_addr);
3812         if (err) {
3813                 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
3814                 return err;
3815         }
3816
3817         /* First check if firmware has any address configured by bootloader */
3818         if (!is_zero_ether_addr(mac_addr)) {
3819                 /* If the DPMAC addr != DPNI addr, update it */
3820                 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
3821                         err = dpni_set_primary_mac_addr(priv->mc_io, 0,
3822                                                         priv->mc_token,
3823                                                         mac_addr);
3824                         if (err) {
3825                                 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3826                                 return err;
3827                         }
3828                 }
3829                 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
3830         } else if (is_zero_ether_addr(dpni_mac_addr)) {
3831                 /* No MAC address configured, fill in net_dev->dev_addr
3832                  * with a random one
3833                  */
3834                 eth_hw_addr_random(net_dev);
3835                 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
3836
3837                 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3838                                                 net_dev->dev_addr);
3839                 if (err) {
3840                         dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3841                         return err;
3842                 }
3843
3844                 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
3845                  * practical purposes, this will be our "permanent" mac address,
3846                  * at least until the next reboot. This move will also permit
3847                  * register_netdevice() to properly fill up net_dev->perm_addr.
3848                  */
3849                 net_dev->addr_assign_type = NET_ADDR_PERM;
3850         } else {
3851                 /* NET_ADDR_PERM is default, all we have to do is
3852                  * fill in the device addr.
3853                  */
3854                 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
3855         }
3856
3857         return 0;
3858 }
3859
3860 static int dpaa2_eth_netdev_init(struct net_device *net_dev)
3861 {
3862         struct device *dev = net_dev->dev.parent;
3863         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3864         u32 options = priv->dpni_attrs.options;
3865         u64 supported = 0, not_supported = 0;
3866         u8 bcast_addr[ETH_ALEN];
3867         u8 num_queues;
3868         int err;
3869
3870         net_dev->netdev_ops = &dpaa2_eth_ops;
3871         net_dev->ethtool_ops = &dpaa2_ethtool_ops;
3872
3873         err = dpaa2_eth_set_mac_addr(priv);
3874         if (err)
3875                 return err;
3876
3877         /* Explicitly add the broadcast address to the MAC filtering table */
3878         eth_broadcast_addr(bcast_addr);
3879         err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
3880         if (err) {
3881                 dev_err(dev, "dpni_add_mac_addr() failed\n");
3882                 return err;
3883         }
3884
3885         /* Set MTU upper limit; lower limit is 68B (default value) */
3886         net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
3887         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
3888                                         DPAA2_ETH_MFL);
3889         if (err) {
3890                 dev_err(dev, "dpni_set_max_frame_length() failed\n");
3891                 return err;
3892         }
3893
3894         /* Set actual number of queues in the net device */
3895         num_queues = dpaa2_eth_queue_count(priv);
3896         err = netif_set_real_num_tx_queues(net_dev, num_queues);
3897         if (err) {
3898                 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
3899                 return err;
3900         }
3901         err = netif_set_real_num_rx_queues(net_dev, num_queues);
3902         if (err) {
3903                 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
3904                 return err;
3905         }
3906
3907         /* Capabilities listing */
3908         supported |= IFF_LIVE_ADDR_CHANGE;
3909
3910         if (options & DPNI_OPT_NO_MAC_FILTER)
3911                 not_supported |= IFF_UNICAST_FLT;
3912         else
3913                 supported |= IFF_UNICAST_FLT;
3914
3915         net_dev->priv_flags |= supported;
3916         net_dev->priv_flags &= ~not_supported;
3917
3918         /* Features */
3919         net_dev->features = NETIF_F_RXCSUM |
3920                             NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3921                             NETIF_F_SG | NETIF_F_HIGHDMA |
3922                             NETIF_F_LLTX | NETIF_F_HW_TC;
3923         net_dev->hw_features = net_dev->features;
3924
3925         return 0;
3926 }
3927
3928 static int dpaa2_eth_poll_link_state(void *arg)
3929 {
3930         struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
3931         int err;
3932
3933         while (!kthread_should_stop()) {
3934                 err = dpaa2_eth_link_state_update(priv);
3935                 if (unlikely(err))
3936                         return err;
3937
3938                 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
3939         }
3940
3941         return 0;
3942 }
3943
3944 static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv)
3945 {
3946         struct fsl_mc_device *dpni_dev, *dpmac_dev;
3947         struct dpaa2_mac *mac;
3948         int err;
3949
3950         dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
3951         dpmac_dev = fsl_mc_get_endpoint(dpni_dev);
3952         if (IS_ERR_OR_NULL(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type)
3953                 return 0;
3954
3955         if (dpaa2_mac_is_type_fixed(dpmac_dev, priv->mc_io))
3956                 return 0;
3957
3958         mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL);
3959         if (!mac)
3960                 return -ENOMEM;
3961
3962         mac->mc_dev = dpmac_dev;
3963         mac->mc_io = priv->mc_io;
3964         mac->net_dev = priv->net_dev;
3965
3966         err = dpaa2_mac_connect(mac);
3967         if (err) {
3968                 netdev_err(priv->net_dev, "Error connecting to the MAC endpoint\n");
3969                 kfree(mac);
3970                 return err;
3971         }
3972         priv->mac = mac;
3973
3974         return 0;
3975 }
3976
3977 static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv)
3978 {
3979         if (!priv->mac)
3980                 return;
3981
3982         dpaa2_mac_disconnect(priv->mac);
3983         kfree(priv->mac);
3984         priv->mac = NULL;
3985 }
3986
3987 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
3988 {
3989         u32 status = ~0;
3990         struct device *dev = (struct device *)arg;
3991         struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
3992         struct net_device *net_dev = dev_get_drvdata(dev);
3993         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3994         int err;
3995
3996         err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
3997                                   DPNI_IRQ_INDEX, &status);
3998         if (unlikely(err)) {
3999                 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
4000                 return IRQ_HANDLED;
4001         }
4002
4003         if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
4004                 dpaa2_eth_link_state_update(netdev_priv(net_dev));
4005
4006         if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) {
4007                 dpaa2_eth_set_mac_addr(netdev_priv(net_dev));
4008                 dpaa2_eth_update_tx_fqids(priv);
4009
4010                 rtnl_lock();
4011                 if (priv->mac)
4012                         dpaa2_eth_disconnect_mac(priv);
4013                 else
4014                         dpaa2_eth_connect_mac(priv);
4015                 rtnl_unlock();
4016         }
4017
4018         return IRQ_HANDLED;
4019 }
4020
4021 static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev)
4022 {
4023         int err = 0;
4024         struct fsl_mc_device_irq *irq;
4025
4026         err = fsl_mc_allocate_irqs(ls_dev);
4027         if (err) {
4028                 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
4029                 return err;
4030         }
4031
4032         irq = ls_dev->irqs[0];
4033         err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
4034                                         NULL, dpni_irq0_handler_thread,
4035                                         IRQF_NO_SUSPEND | IRQF_ONESHOT,
4036                                         dev_name(&ls_dev->dev), &ls_dev->dev);
4037         if (err < 0) {
4038                 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
4039                 goto free_mc_irq;
4040         }
4041
4042         err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
4043                                 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED |
4044                                 DPNI_IRQ_EVENT_ENDPOINT_CHANGED);
4045         if (err < 0) {
4046                 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
4047                 goto free_irq;
4048         }
4049
4050         err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
4051                                   DPNI_IRQ_INDEX, 1);
4052         if (err < 0) {
4053                 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
4054                 goto free_irq;
4055         }
4056
4057         return 0;
4058
4059 free_irq:
4060         devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
4061 free_mc_irq:
4062         fsl_mc_free_irqs(ls_dev);
4063
4064         return err;
4065 }
4066
4067 static void dpaa2_eth_add_ch_napi(struct dpaa2_eth_priv *priv)
4068 {
4069         int i;
4070         struct dpaa2_eth_channel *ch;
4071
4072         for (i = 0; i < priv->num_channels; i++) {
4073                 ch = priv->channel[i];
4074                 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
4075                 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
4076                                NAPI_POLL_WEIGHT);
4077         }
4078 }
4079
4080 static void dpaa2_eth_del_ch_napi(struct dpaa2_eth_priv *priv)
4081 {
4082         int i;
4083         struct dpaa2_eth_channel *ch;
4084
4085         for (i = 0; i < priv->num_channels; i++) {
4086                 ch = priv->channel[i];
4087                 netif_napi_del(&ch->napi);
4088         }
4089 }
4090
4091 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
4092 {
4093         struct device *dev;
4094         struct net_device *net_dev = NULL;
4095         struct dpaa2_eth_priv *priv = NULL;
4096         int err = 0;
4097
4098         dev = &dpni_dev->dev;
4099
4100         /* Net device */
4101         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
4102         if (!net_dev) {
4103                 dev_err(dev, "alloc_etherdev_mq() failed\n");
4104                 return -ENOMEM;
4105         }
4106
4107         SET_NETDEV_DEV(net_dev, dev);
4108         dev_set_drvdata(dev, net_dev);
4109
4110         priv = netdev_priv(net_dev);
4111         priv->net_dev = net_dev;
4112
4113         priv->iommu_domain = iommu_get_domain_for_dev(dev);
4114
4115         priv->tx_tstamp_type = HWTSTAMP_TX_OFF;
4116         priv->rx_tstamp = false;
4117
4118         priv->dpaa2_ptp_wq = alloc_workqueue("dpaa2_ptp_wq", 0, 0);
4119         if (!priv->dpaa2_ptp_wq) {
4120                 err = -ENOMEM;
4121                 goto err_wq_alloc;
4122         }
4123
4124         INIT_WORK(&priv->tx_onestep_tstamp, dpaa2_eth_tx_onestep_tstamp);
4125
4126         skb_queue_head_init(&priv->tx_skbs);
4127
4128         /* Obtain a MC portal */
4129         err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
4130                                      &priv->mc_io);
4131         if (err) {
4132                 if (err == -ENXIO)
4133                         err = -EPROBE_DEFER;
4134                 else
4135                         dev_err(dev, "MC portal allocation failed\n");
4136                 goto err_portal_alloc;
4137         }
4138
4139         /* MC objects initialization and configuration */
4140         err = dpaa2_eth_setup_dpni(dpni_dev);
4141         if (err)
4142                 goto err_dpni_setup;
4143
4144         err = dpaa2_eth_setup_dpio(priv);
4145         if (err)
4146                 goto err_dpio_setup;
4147
4148         dpaa2_eth_setup_fqs(priv);
4149
4150         err = dpaa2_eth_setup_dpbp(priv);
4151         if (err)
4152                 goto err_dpbp_setup;
4153
4154         err = dpaa2_eth_bind_dpni(priv);
4155         if (err)
4156                 goto err_bind;
4157
4158         /* Add a NAPI context for each channel */
4159         dpaa2_eth_add_ch_napi(priv);
4160
4161         /* Percpu statistics */
4162         priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
4163         if (!priv->percpu_stats) {
4164                 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
4165                 err = -ENOMEM;
4166                 goto err_alloc_percpu_stats;
4167         }
4168         priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
4169         if (!priv->percpu_extras) {
4170                 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
4171                 err = -ENOMEM;
4172                 goto err_alloc_percpu_extras;
4173         }
4174
4175         priv->sgt_cache = alloc_percpu(*priv->sgt_cache);
4176         if (!priv->sgt_cache) {
4177                 dev_err(dev, "alloc_percpu(sgt_cache) failed\n");
4178                 err = -ENOMEM;
4179                 goto err_alloc_sgt_cache;
4180         }
4181
4182         err = dpaa2_eth_netdev_init(net_dev);
4183         if (err)
4184                 goto err_netdev_init;
4185
4186         /* Configure checksum offload based on current interface flags */
4187         err = dpaa2_eth_set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
4188         if (err)
4189                 goto err_csum;
4190
4191         err = dpaa2_eth_set_tx_csum(priv,
4192                                     !!(net_dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
4193         if (err)
4194                 goto err_csum;
4195
4196         err = dpaa2_eth_alloc_rings(priv);
4197         if (err)
4198                 goto err_alloc_rings;
4199
4200 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
4201         if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) {
4202                 priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4203                 net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
4204         } else {
4205                 dev_dbg(dev, "PFC not supported\n");
4206         }
4207 #endif
4208
4209         err = dpaa2_eth_setup_irqs(dpni_dev);
4210         if (err) {
4211                 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
4212                 priv->poll_thread = kthread_run(dpaa2_eth_poll_link_state, priv,
4213                                                 "%s_poll_link", net_dev->name);
4214                 if (IS_ERR(priv->poll_thread)) {
4215                         dev_err(dev, "Error starting polling thread\n");
4216                         goto err_poll_thread;
4217                 }
4218                 priv->do_link_poll = true;
4219         }
4220
4221         err = dpaa2_eth_connect_mac(priv);
4222         if (err)
4223                 goto err_connect_mac;
4224
4225         err = register_netdev(net_dev);
4226         if (err < 0) {
4227                 dev_err(dev, "register_netdev() failed\n");
4228                 goto err_netdev_reg;
4229         }
4230
4231 #ifdef CONFIG_DEBUG_FS
4232         dpaa2_dbg_add(priv);
4233 #endif
4234
4235         dev_info(dev, "Probed interface %s\n", net_dev->name);
4236         return 0;
4237
4238 err_netdev_reg:
4239         dpaa2_eth_disconnect_mac(priv);
4240 err_connect_mac:
4241         if (priv->do_link_poll)
4242                 kthread_stop(priv->poll_thread);
4243         else
4244                 fsl_mc_free_irqs(dpni_dev);
4245 err_poll_thread:
4246         dpaa2_eth_free_rings(priv);
4247 err_alloc_rings:
4248 err_csum:
4249 err_netdev_init:
4250         free_percpu(priv->sgt_cache);
4251 err_alloc_sgt_cache:
4252         free_percpu(priv->percpu_extras);
4253 err_alloc_percpu_extras:
4254         free_percpu(priv->percpu_stats);
4255 err_alloc_percpu_stats:
4256         dpaa2_eth_del_ch_napi(priv);
4257 err_bind:
4258         dpaa2_eth_free_dpbp(priv);
4259 err_dpbp_setup:
4260         dpaa2_eth_free_dpio(priv);
4261 err_dpio_setup:
4262         dpaa2_eth_free_dpni(priv);
4263 err_dpni_setup:
4264         fsl_mc_portal_free(priv->mc_io);
4265 err_portal_alloc:
4266         destroy_workqueue(priv->dpaa2_ptp_wq);
4267 err_wq_alloc:
4268         dev_set_drvdata(dev, NULL);
4269         free_netdev(net_dev);
4270
4271         return err;
4272 }
4273
4274 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
4275 {
4276         struct device *dev;
4277         struct net_device *net_dev;
4278         struct dpaa2_eth_priv *priv;
4279
4280         dev = &ls_dev->dev;
4281         net_dev = dev_get_drvdata(dev);
4282         priv = netdev_priv(net_dev);
4283
4284 #ifdef CONFIG_DEBUG_FS
4285         dpaa2_dbg_remove(priv);
4286 #endif
4287         rtnl_lock();
4288         dpaa2_eth_disconnect_mac(priv);
4289         rtnl_unlock();
4290
4291         unregister_netdev(net_dev);
4292
4293         if (priv->do_link_poll)
4294                 kthread_stop(priv->poll_thread);
4295         else
4296                 fsl_mc_free_irqs(ls_dev);
4297
4298         dpaa2_eth_free_rings(priv);
4299         free_percpu(priv->sgt_cache);
4300         free_percpu(priv->percpu_stats);
4301         free_percpu(priv->percpu_extras);
4302
4303         dpaa2_eth_del_ch_napi(priv);
4304         dpaa2_eth_free_dpbp(priv);
4305         dpaa2_eth_free_dpio(priv);
4306         dpaa2_eth_free_dpni(priv);
4307
4308         fsl_mc_portal_free(priv->mc_io);
4309
4310         free_netdev(net_dev);
4311
4312         dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
4313
4314         return 0;
4315 }
4316
4317 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
4318         {
4319                 .vendor = FSL_MC_VENDOR_FREESCALE,
4320                 .obj_type = "dpni",
4321         },
4322         { .vendor = 0x0 }
4323 };
4324 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
4325
4326 static struct fsl_mc_driver dpaa2_eth_driver = {
4327         .driver = {
4328                 .name = KBUILD_MODNAME,
4329                 .owner = THIS_MODULE,
4330         },
4331         .probe = dpaa2_eth_probe,
4332         .remove = dpaa2_eth_remove,
4333         .match_id_table = dpaa2_eth_match_id_table
4334 };
4335
4336 static int __init dpaa2_eth_driver_init(void)
4337 {
4338         int err;
4339
4340         dpaa2_eth_dbg_init();
4341         err = fsl_mc_driver_register(&dpaa2_eth_driver);
4342         if (err) {
4343                 dpaa2_eth_dbg_exit();
4344                 return err;
4345         }
4346
4347         return 0;
4348 }
4349
4350 static void __exit dpaa2_eth_driver_exit(void)
4351 {
4352         dpaa2_eth_dbg_exit();
4353         fsl_mc_driver_unregister(&dpaa2_eth_driver);
4354 }
4355
4356 module_init(dpaa2_eth_driver_init);
4357 module_exit(dpaa2_eth_driver_exit);