drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright © 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/onenand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/dmaengine.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/gpio.h>
  39
  40 #include <asm/mach/flash.h>
  41 #include <linux/platform_data/mtd-onenand-omap2.h>
  42
  43 #define DRIVER_NAME "omap2-onenand"
  44
  45 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  46
  47 struct omap2_onenand {
  48         struct platform_device *pdev;
  49         int gpmc_cs;
  50         unsigned long phys_base;
  51         unsigned int mem_size;
  52         int gpio_irq;
  53         struct mtd_info mtd;
  54         struct onenand_chip onenand;
  55         struct completion irq_done;
  56         struct completion dma_done;
  57         struct dma_chan *dma_chan;
  58         int freq;
  59         int (*setup)(void __iomem *base, int *freq_ptr);
  60 };
  61
  62 static void omap2_onenand_dma_complete_func(void *completion)
  63 {
  64         complete(completion);
  65 }
  66
  67 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  68 {
  69         struct omap2_onenand *c = dev_id;
  70
  71         complete(&c->irq_done);
  72
  73         return IRQ_HANDLED;
  74 }
  75
  76 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  77 {
  78         return readw(c->onenand.base + reg);
  79 }
  80
  81 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  82                              int reg)
  83 {
  84         writew(value, c->onenand.base + reg);
  85 }
  86
  87 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
  88 {
  89         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
  90                msg, state, ctrl, intr);
  91 }
  92
  93 static void wait_warn(char *msg, int state, unsigned int ctrl,
  94                       unsigned int intr)
  95 {
  96         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
  97                "intr 0x%04x\n", msg, state, ctrl, intr);
  98 }
  99
 100 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 101 {
 102         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 103         struct onenand_chip *this = mtd->priv;
 104         unsigned int intr = 0;
 105         unsigned int ctrl, ctrl_mask;
 106         unsigned long timeout;
 107         u32 syscfg;
 108
 109         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 110             state == FL_VERIFYING_ERASE) {
 111                 int i = 21;
 112                 unsigned int intr_flags = ONENAND_INT_MASTER;
 113
 114                 switch (state) {
 115                 case FL_RESETING:
 116                         intr_flags |= ONENAND_INT_RESET;
 117                         break;
 118                 case FL_PREPARING_ERASE:
 119                         intr_flags |= ONENAND_INT_ERASE;
 120                         break;
 121                 case FL_VERIFYING_ERASE:
 122                         i = 101;
 123                         break;
 124                 }
 125
 126                 while (--i) {
 127                         udelay(1);
 128                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 129                         if (intr & ONENAND_INT_MASTER)
 130                                 break;
 131                 }
 132                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 133                 if (ctrl & ONENAND_CTRL_ERROR) {
 134                         wait_err("controller error", state, ctrl, intr);
 135                         return -EIO;
 136                 }
 137                 if ((intr & intr_flags) == intr_flags)
 138                         return 0;
 139                 /* Continue in wait for interrupt branch */
 140         }
 141
 142         if (state != FL_READING) {
 143                 int result;
 144
 145                 /* Turn interrupts on */
 146                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 147                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 148                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 149                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 150                         /* Add a delay to let GPIO settle */
 151                         syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 152                 }
 153
 154                 reinit_completion(&c->irq_done);
 155                 if (c->gpio_irq) {
 156                         result = gpio_get_value(c->gpio_irq);
 157                         if (result == -1) {
 158                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 159                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 160                                 wait_err("gpio error", state, ctrl, intr);
 161                                 return -EIO;
 162                         }
 163                 } else
 164                         result = 0;
 165                 if (result == 0) {
 166                         int retry_cnt = 0;
 167 retry:
 168                         if (!wait_for_completion_io_timeout(&c->irq_done,
 169                                                 msecs_to_jiffies(20))) {
 170                                 /* Timeout after 20ms */
 171                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 172                                 if (ctrl & ONENAND_CTRL_ONGO &&
 173                                     !this->ongoing) {
 174                                         /*
 175                                          * The operation seems to be still going
 176                                          * so give it some more time.
 177                                          */
 178                                         retry_cnt += 1;
 179                                         if (retry_cnt < 3)
 180                                                 goto retry;
 181                                         intr = read_reg(c,
 182                                                         ONENAND_REG_INTERRUPT);
 183                                         wait_err("timeout", state, ctrl, intr);
 184                                         return -EIO;
 185                                 }
 186                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 187                                 if ((intr & ONENAND_INT_MASTER) == 0)
 188                                         wait_warn("timeout", state, ctrl, intr);
 189                         }
 190                 }
 191         } else {
 192                 int retry_cnt = 0;
 193
 194                 /* Turn interrupts off */
 195                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 196                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 197                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 198
 199                 timeout = jiffies + msecs_to_jiffies(20);
 200                 while (1) {
 201                         if (time_before(jiffies, timeout)) {
 202                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 203                                 if (intr & ONENAND_INT_MASTER)
 204                                         break;
 205                         } else {
 206                                 /* Timeout after 20ms */
 207                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 208                                 if (ctrl & ONENAND_CTRL_ONGO) {
 209                                         /*
 210                                          * The operation seems to be still going
 211                                          * so give it some more time.
 212                                          */
 213                                         retry_cnt += 1;
 214                                         if (retry_cnt < 3) {
 215                                                 timeout = jiffies +
 216                                                           msecs_to_jiffies(20);
 217                                                 continue;
 218                                         }
 219                                 }
 220                                 break;
 221                         }
 222                 }
 223         }
 224
 225         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 226         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 227
 228         if (intr & ONENAND_INT_READ) {
 229                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 230
 231                 if (ecc) {
 232                         unsigned int addr1, addr8;
 233
 234                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 235                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 236                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 237                                 printk(KERN_ERR "onenand_wait: ECC error = "
 238                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 239                                        ecc, addr1, addr8);
 240                                 mtd->ecc_stats.failed++;
 241                                 return -EBADMSG;
 242                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 243                                 printk(KERN_NOTICE "onenand_wait: correctable "
 244                                        "ECC error = 0x%04x, addr1 %#x, "
 245                                        "addr8 %#x\n", ecc, addr1, addr8);
 246                                 mtd->ecc_stats.corrected++;
 247                         }
 248                 }
 249         } else if (state == FL_READING) {
 250                 wait_err("timeout", state, ctrl, intr);
 251                 return -EIO;
 252         }
 253
 254         if (ctrl & ONENAND_CTRL_ERROR) {
 255                 wait_err("controller error", state, ctrl, intr);
 256                 if (ctrl & ONENAND_CTRL_LOCK)
 257                         printk(KERN_ERR "onenand_wait: "
 258                                         "Device is write protected!!!\n");
 259                 return -EIO;
 260         }
 261
 262         ctrl_mask = 0xFE9F;
 263         if (this->ongoing)
 264                 ctrl_mask &= ~0x8000;
 265
 266         if (ctrl & ctrl_mask)
 267                 wait_warn("unexpected controller status", state, ctrl, intr);
 268
 269         return 0;
 270 }
 271
 272 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 273 {
 274         struct onenand_chip *this = mtd->priv;
 275
 276         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 277                 if (area == ONENAND_DATARAM)
 278                         return this->writesize;
 279                 if (area == ONENAND_SPARERAM)
 280                         return mtd->oobsize;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 287                                              dma_addr_t src, dma_addr_t dst,
 288                                              size_t count)
 289 {
 290         struct dma_async_tx_descriptor *tx;
 291         dma_cookie_t cookie;
 292
 293         tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
 294         if (!tx) {
 295                 dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
 296                 return -EIO;
 297         }
 298
 299         reinit_completion(&c->dma_done);
 300
 301         tx->callback = omap2_onenand_dma_complete_func;
 302         tx->callback_param = &c->dma_done;
 303
 304         cookie = tx->tx_submit(tx);
 305         if (dma_submit_error(cookie)) {
 306                 dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
 307                 return -EIO;
 308         }
 309
 310         dma_async_issue_pending(c->dma_chan);
 311
 312         if (!wait_for_completion_io_timeout(&c->dma_done,
 313                                             msecs_to_jiffies(20))) {
 314                 dmaengine_terminate_sync(c->dma_chan);
 315                 return -ETIMEDOUT;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 322                                         unsigned char *buffer, int offset,
 323                                         size_t count)
 324 {
 325         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 326         struct onenand_chip *this = mtd->priv;
 327         dma_addr_t dma_src, dma_dst;
 328         int bram_offset;
 329         void *buf = (void *)buffer;
 330         size_t xtra;
 331         int ret;
 332
 333         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 334         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 335                 goto out_copy;
 336
 337         /* panic_write() may be in an interrupt context */
 338         if (in_interrupt() || oops_in_progress)
 339                 goto out_copy;
 340
 341         if (buf >= high_memory) {
 342                 struct page *p1;
 343
 344                 if (((size_t)buf & PAGE_MASK) !=
 345                     ((size_t)(buf + count - 1) & PAGE_MASK))
 346                         goto out_copy;
 347                 p1 = vmalloc_to_page(buf);
 348                 if (!p1)
 349                         goto out_copy;
 350                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 351         }
 352
 353         xtra = count & 3;
 354         if (xtra) {
 355                 count -= xtra;
 356                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 357         }
 358
 359         dma_src = c->phys_base + bram_offset;
 360         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 361         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 362                 dev_err(&c->pdev->dev,
 363                         "Couldn't DMA map a %d byte buffer\n",
 364                         count);
 365                 goto out_copy;
 366         }
 367
 368         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 369         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 370
 371         if (ret) {
 372                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 373                 goto out_copy;
 374         }
 375
 376         return 0;
 377
 378 out_copy:
 379         memcpy(buf, this->base + bram_offset, count);
 380         return 0;
 381 }
 382
 383 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 384                                          const unsigned char *buffer,
 385                                          int offset, size_t count)
 386 {
 387         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 388         struct onenand_chip *this = mtd->priv;
 389         dma_addr_t dma_src, dma_dst;
 390         int bram_offset;
 391         void *buf = (void *)buffer;
 392         int ret;
 393
 394         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 395         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 396                 goto out_copy;
 397
 398         /* panic_write() may be in an interrupt context */
 399         if (in_interrupt() || oops_in_progress)
 400                 goto out_copy;
 401
 402         if (buf >= high_memory) {
 403                 struct page *p1;
 404
 405                 if (((size_t)buf & PAGE_MASK) !=
 406                     ((size_t)(buf + count - 1) & PAGE_MASK))
 407                         goto out_copy;
 408                 p1 = vmalloc_to_page(buf);
 409                 if (!p1)
 410                         goto out_copy;
 411                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 412         }
 413
 414         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 415         dma_dst = c->phys_base + bram_offset;
 416         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 417                 dev_err(&c->pdev->dev,
 418                         "Couldn't DMA map a %d byte buffer\n",
 419                         count);
 420                 return -1;
 421         }
 422
 423         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 424         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 425
 426         if (ret) {
 427                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 428                 goto out_copy;
 429         }
 430
 431         return 0;
 432
 433 out_copy:
 434         memcpy(this->base + bram_offset, buf, count);
 435         return 0;
 436 }
 437
 438 static struct platform_driver omap2_onenand_driver;
 439
 440 static void omap2_onenand_shutdown(struct platform_device *pdev)
 441 {
 442         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 443
 444         /* With certain content in the buffer RAM, the OMAP boot ROM code
 445          * can recognize the flash chip incorrectly. Zero it out before
 446          * soft reset.
 447          */
 448         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 449 }
 450
 451 static int omap2_onenand_probe(struct platform_device *pdev)
 452 {
 453         struct omap_onenand_platform_data *pdata;
 454         struct omap2_onenand *c;
 455         struct onenand_chip *this;
 456         int r;
 457         struct resource *res;
 458
 459         pdata = dev_get_platdata(&pdev->dev);
 460         if (pdata == NULL) {
 461                 dev_err(&pdev->dev, "platform data missing\n");
 462                 return -ENODEV;
 463         }
 464
 465         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 466         if (!c)
 467                 return -ENOMEM;
 468
 469         init_completion(&c->irq_done);
 470         init_completion(&c->dma_done);
 471         c->gpmc_cs = pdata->cs;
 472         c->gpio_irq = pdata->gpio_irq;
 473         if (pdata->dma_channel < 0) {
 474                 /* if -1, don't use DMA */
 475                 c->gpio_irq = 0;
 476         }
 477
 478         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 479         if (res == NULL) {
 480                 r = -EINVAL;
 481                 dev_err(&pdev->dev, "error getting memory resource\n");
 482                 goto err_kfree;
 483         }
 484
 485         c->phys_base = res->start;
 486         c->mem_size = resource_size(res);
 487
 488         if (request_mem_region(c->phys_base, c->mem_size,
 489                                pdev->dev.driver->name) == NULL) {
 490                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 491                                                 c->phys_base, c->mem_size);
 492                 r = -EBUSY;
 493                 goto err_kfree;
 494         }
 495         c->onenand.base = ioremap(c->phys_base, c->mem_size);
 496         if (c->onenand.base == NULL) {
 497                 r = -ENOMEM;
 498                 goto err_release_mem_region;
 499         }
 500
 501         if (pdata->onenand_setup != NULL) {
 502                 r = pdata->onenand_setup(c->onenand.base, &c->freq);
 503                 if (r < 0) {
 504                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 505                                 "%d\n", r);
 506                         goto err_iounmap;
 507                 }
 508                 c->setup = pdata->onenand_setup;
 509         }
 510
 511         if (c->gpio_irq) {
 512                 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
 513                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 514                                 "OneNAND\n", c->gpio_irq);
 515                         goto err_iounmap;
 516         }
 517         gpio_direction_input(c->gpio_irq);
 518
 519         if ((r = request_irq(gpio_to_irq(c->gpio_irq),
 520                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 521                              pdev->dev.driver->name, c)) < 0)
 522                 goto err_release_gpio;
 523         }
 524
 525         if (pdata->dma_channel >= 0) {
 526                 dma_cap_mask_t mask;
 527
 528                 dma_cap_zero(mask);
 529                 dma_cap_set(DMA_MEMCPY, mask);
 530
 531                 c->dma_chan = dma_request_channel(mask, NULL, NULL);
 532                 if (!c->dma_chan)
 533                         dev_info(&pdev->dev,
 534                                  "failed to allocate DMA for OneNAND, "
 535                                  "using PIO instead\n");
 536         }
 537
 538         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 539                  "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
 540                  c->onenand.base, c->freq);
 541
 542         c->pdev = pdev;
 543         c->mtd.priv = &c->onenand;
 544
 545         c->mtd.dev.parent = &pdev->dev;
 546         mtd_set_of_node(&c->mtd, pdata->of_node);
 547
 548         this = &c->onenand;
 549         if (c->dma_chan) {
 550                 this->wait = omap2_onenand_wait;
 551                 this->read_bufferram = omap2_onenand_read_bufferram;
 552                 this->write_bufferram = omap2_onenand_write_bufferram;
 553         }
 554
 555         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 556                 goto err_release_dma;
 557
 558         r = mtd_device_register(&c->mtd, NULL, 0);
 559         if (r)
 560                 goto err_release_onenand;
 561
 562         platform_set_drvdata(pdev, c);
 563
 564         return 0;
 565
 566 err_release_onenand:
 567         onenand_release(&c->mtd);
 568 err_release_dma:
 569         if (c->dma_chan)
 570                 dma_release_channel(c->dma_chan);
 571         if (c->gpio_irq)
 572                 free_irq(gpio_to_irq(c->gpio_irq), c);
 573 err_release_gpio:
 574         if (c->gpio_irq)
 575                 gpio_free(c->gpio_irq);
 576 err_iounmap:
 577         iounmap(c->onenand.base);
 578 err_release_mem_region:
 579         release_mem_region(c->phys_base, c->mem_size);
 580 err_kfree:
 581         kfree(c);
 582
 583         return r;
 584 }
 585
 586 static int omap2_onenand_remove(struct platform_device *pdev)
 587 {
 588         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 589
 590         onenand_release(&c->mtd);
 591         if (c->dma_chan)
 592                 dma_release_channel(c->dma_chan);
 593         omap2_onenand_shutdown(pdev);
 594         if (c->gpio_irq) {
 595                 free_irq(gpio_to_irq(c->gpio_irq), c);
 596                 gpio_free(c->gpio_irq);
 597         }
 598         iounmap(c->onenand.base);
 599         release_mem_region(c->phys_base, c->mem_size);
 600         kfree(c);
 601
 602         return 0;
 603 }
 604
 605 static struct platform_driver omap2_onenand_driver = {
 606         .probe          = omap2_onenand_probe,
 607         .remove         = omap2_onenand_remove,
 608         .shutdown       = omap2_onenand_shutdown,
 609         .driver         = {
 610                 .name   = DRIVER_NAME,
 611         },
 612 };
 613
 614 module_platform_driver(omap2_onenand_driver);
 615
 616 MODULE_ALIAS("platform:" DRIVER_NAME);
 617 MODULE_LICENSE("GPL");
 618 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 619 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");