2 * OneNAND driver for OMAP2 / OMAP3
4 * Copyright © 2005-2006 Nokia Corporation
6 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
7 * IRQ and DMA support written by Timo Teras
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; see the file COPYING. If not, write to the Free Software
20 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/onenand.h>
28 #include <linux/mtd/partitions.h>
29 #include <linux/of_device.h>
30 #include <linux/omap-gpmc.h>
31 #include <linux/platform_device.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/dmaengine.h>
37 #include <linux/slab.h>
38 #include <linux/gpio/consumer.h>
40 #include <asm/mach/flash.h>
42 #define DRIVER_NAME "omap2-onenand"
44 #define ONENAND_BUFRAM_SIZE (1024 * 5)
46 struct omap2_onenand {
47 struct platform_device *pdev;
49 unsigned long phys_base;
50 struct gpio_desc *int_gpiod;
52 struct onenand_chip onenand;
53 struct completion irq_done;
54 struct completion dma_done;
55 struct dma_chan *dma_chan;
58 static void omap2_onenand_dma_complete_func(void *completion)
63 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
65 struct omap2_onenand *c = dev_id;
67 complete(&c->irq_done);
72 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
74 return readw(c->onenand.base + reg);
77 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
80 writew(value, c->onenand.base + reg);
83 static int omap2_onenand_set_cfg(struct omap2_onenand *c,
85 int latency, int burst_len)
87 unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
89 reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
92 case 0: /* continuous */
95 reg |= ONENAND_SYS_CFG1_BL_4;
98 reg |= ONENAND_SYS_CFG1_BL_8;
101 reg |= ONENAND_SYS_CFG1_BL_16;
104 reg |= ONENAND_SYS_CFG1_BL_32;
111 reg |= ONENAND_SYS_CFG1_HF;
113 reg |= ONENAND_SYS_CFG1_VHF;
115 reg |= ONENAND_SYS_CFG1_SYNC_READ;
117 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
119 write_reg(c, reg, ONENAND_REG_SYS_CFG1);
124 static int omap2_onenand_get_freq(int ver)
126 switch ((ver >> 4) & 0xf) {
142 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
144 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
145 msg, state, ctrl, intr);
148 static void wait_warn(char *msg, int state, unsigned int ctrl,
151 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
152 "intr 0x%04x\n", msg, state, ctrl, intr);
155 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
157 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
158 struct onenand_chip *this = mtd->priv;
159 unsigned int intr = 0;
160 unsigned int ctrl, ctrl_mask;
161 unsigned long timeout;
164 if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
165 state == FL_VERIFYING_ERASE) {
167 unsigned int intr_flags = ONENAND_INT_MASTER;
171 intr_flags |= ONENAND_INT_RESET;
173 case FL_PREPARING_ERASE:
174 intr_flags |= ONENAND_INT_ERASE;
176 case FL_VERIFYING_ERASE:
183 intr = read_reg(c, ONENAND_REG_INTERRUPT);
184 if (intr & ONENAND_INT_MASTER)
187 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
188 if (ctrl & ONENAND_CTRL_ERROR) {
189 wait_err("controller error", state, ctrl, intr);
192 if ((intr & intr_flags) == intr_flags)
194 /* Continue in wait for interrupt branch */
197 if (state != FL_READING) {
200 /* Turn interrupts on */
201 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
202 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
203 syscfg |= ONENAND_SYS_CFG1_IOBE;
204 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
205 /* Add a delay to let GPIO settle */
206 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
209 reinit_completion(&c->irq_done);
210 result = gpiod_get_value(c->int_gpiod);
212 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
213 intr = read_reg(c, ONENAND_REG_INTERRUPT);
214 wait_err("gpio error", state, ctrl, intr);
216 } else if (result == 0) {
219 if (!wait_for_completion_io_timeout(&c->irq_done,
220 msecs_to_jiffies(20))) {
221 /* Timeout after 20ms */
222 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
223 if (ctrl & ONENAND_CTRL_ONGO &&
226 * The operation seems to be still going
227 * so give it some more time.
233 ONENAND_REG_INTERRUPT);
234 wait_err("timeout", state, ctrl, intr);
237 intr = read_reg(c, ONENAND_REG_INTERRUPT);
238 if ((intr & ONENAND_INT_MASTER) == 0)
239 wait_warn("timeout", state, ctrl, intr);
245 /* Turn interrupts off */
246 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
247 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
248 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
250 timeout = jiffies + msecs_to_jiffies(20);
252 if (time_before(jiffies, timeout)) {
253 intr = read_reg(c, ONENAND_REG_INTERRUPT);
254 if (intr & ONENAND_INT_MASTER)
257 /* Timeout after 20ms */
258 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
259 if (ctrl & ONENAND_CTRL_ONGO) {
261 * The operation seems to be still going
262 * so give it some more time.
267 msecs_to_jiffies(20);
276 intr = read_reg(c, ONENAND_REG_INTERRUPT);
277 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
279 if (intr & ONENAND_INT_READ) {
280 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
283 unsigned int addr1, addr8;
285 addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
286 addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
287 if (ecc & ONENAND_ECC_2BIT_ALL) {
288 printk(KERN_ERR "onenand_wait: ECC error = "
289 "0x%04x, addr1 %#x, addr8 %#x\n",
291 mtd->ecc_stats.failed++;
293 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
294 printk(KERN_NOTICE "onenand_wait: correctable "
295 "ECC error = 0x%04x, addr1 %#x, "
296 "addr8 %#x\n", ecc, addr1, addr8);
297 mtd->ecc_stats.corrected++;
300 } else if (state == FL_READING) {
301 wait_err("timeout", state, ctrl, intr);
305 if (ctrl & ONENAND_CTRL_ERROR) {
306 wait_err("controller error", state, ctrl, intr);
307 if (ctrl & ONENAND_CTRL_LOCK)
308 printk(KERN_ERR "onenand_wait: "
309 "Device is write protected!!!\n");
315 ctrl_mask &= ~0x8000;
317 if (ctrl & ctrl_mask)
318 wait_warn("unexpected controller status", state, ctrl, intr);
323 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
325 struct onenand_chip *this = mtd->priv;
327 if (ONENAND_CURRENT_BUFFERRAM(this)) {
328 if (area == ONENAND_DATARAM)
329 return this->writesize;
330 if (area == ONENAND_SPARERAM)
337 static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
338 dma_addr_t src, dma_addr_t dst,
341 struct dma_async_tx_descriptor *tx;
344 tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
346 dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
350 reinit_completion(&c->dma_done);
352 tx->callback = omap2_onenand_dma_complete_func;
353 tx->callback_param = &c->dma_done;
355 cookie = tx->tx_submit(tx);
356 if (dma_submit_error(cookie)) {
357 dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
361 dma_async_issue_pending(c->dma_chan);
363 if (!wait_for_completion_io_timeout(&c->dma_done,
364 msecs_to_jiffies(20))) {
365 dmaengine_terminate_sync(c->dma_chan);
372 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
373 unsigned char *buffer, int offset,
376 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
377 struct onenand_chip *this = mtd->priv;
378 dma_addr_t dma_src, dma_dst;
380 void *buf = (void *)buffer;
384 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
385 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
388 /* panic_write() may be in an interrupt context */
389 if (in_interrupt() || oops_in_progress)
392 if (buf >= high_memory) {
395 if (((size_t)buf & PAGE_MASK) !=
396 ((size_t)(buf + count - 1) & PAGE_MASK))
398 p1 = vmalloc_to_page(buf);
401 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
407 memcpy(buf + count, this->base + bram_offset + count, xtra);
410 dma_src = c->phys_base + bram_offset;
411 dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
412 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
413 dev_err(&c->pdev->dev,
414 "Couldn't DMA map a %d byte buffer\n",
419 ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
420 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
423 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
430 memcpy(buf, this->base + bram_offset, count);
434 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
435 const unsigned char *buffer,
436 int offset, size_t count)
438 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
439 struct onenand_chip *this = mtd->priv;
440 dma_addr_t dma_src, dma_dst;
442 void *buf = (void *)buffer;
445 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
446 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
449 /* panic_write() may be in an interrupt context */
450 if (in_interrupt() || oops_in_progress)
453 if (buf >= high_memory) {
456 if (((size_t)buf & PAGE_MASK) !=
457 ((size_t)(buf + count - 1) & PAGE_MASK))
459 p1 = vmalloc_to_page(buf);
462 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
465 dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
466 dma_dst = c->phys_base + bram_offset;
467 if (dma_mapping_error(&c->pdev->dev, dma_src)) {
468 dev_err(&c->pdev->dev,
469 "Couldn't DMA map a %d byte buffer\n",
474 ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
475 dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
478 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
485 memcpy(this->base + bram_offset, buf, count);
489 static void omap2_onenand_shutdown(struct platform_device *pdev)
491 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
493 /* With certain content in the buffer RAM, the OMAP boot ROM code
494 * can recognize the flash chip incorrectly. Zero it out before
497 memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
500 static int omap2_onenand_probe(struct platform_device *pdev)
504 int freq, latency, r;
505 struct resource *res;
506 struct omap2_onenand *c;
507 struct gpmc_onenand_info info;
508 struct device *dev = &pdev->dev;
509 struct device_node *np = dev->of_node;
511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
513 dev_err(dev, "error getting memory resource\n");
517 r = of_property_read_u32(np, "reg", &val);
519 dev_err(dev, "reg not found in DT\n");
523 c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
527 init_completion(&c->irq_done);
528 init_completion(&c->dma_done);
530 c->phys_base = res->start;
532 c->onenand.base = devm_ioremap_resource(dev, res);
533 if (IS_ERR(c->onenand.base))
534 return PTR_ERR(c->onenand.base);
536 c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
537 if (IS_ERR(c->int_gpiod)) {
538 r = PTR_ERR(c->int_gpiod);
539 /* Just try again if this happens */
540 if (r != -EPROBE_DEFER)
541 dev_err(dev, "error getting gpio: %d\n", r);
546 r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
547 omap2_onenand_interrupt,
548 IRQF_TRIGGER_RISING, "onenand", c);
552 c->onenand.wait = omap2_onenand_wait;
556 dma_cap_set(DMA_MEMCPY, mask);
558 c->dma_chan = dma_request_channel(mask, NULL, NULL);
560 c->onenand.read_bufferram = omap2_onenand_read_bufferram;
561 c->onenand.write_bufferram = omap2_onenand_write_bufferram;
565 c->mtd.priv = &c->onenand;
566 c->mtd.dev.parent = dev;
567 mtd_set_of_node(&c->mtd, dev->of_node);
569 dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
570 c->gpmc_cs, c->phys_base, c->onenand.base,
571 c->dma_chan ? "DMA" : "PIO");
573 if ((r = onenand_scan(&c->mtd, 1)) < 0)
574 goto err_release_dma;
576 freq = omap2_onenand_get_freq(c->onenand.version_id);
591 default: /* 40 MHz or lower */
596 r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
597 freq, latency, &info);
599 goto err_release_onenand;
601 r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
602 latency, info.burst_len);
604 goto err_release_onenand;
606 if (info.sync_read || info.sync_write)
607 dev_info(dev, "optimized timings for %d MHz\n", freq);
610 r = mtd_device_register(&c->mtd, NULL, 0);
612 goto err_release_onenand;
614 platform_set_drvdata(pdev, c);
619 onenand_release(&c->mtd);
622 dma_release_channel(c->dma_chan);
627 static int omap2_onenand_remove(struct platform_device *pdev)
629 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
631 onenand_release(&c->mtd);
633 dma_release_channel(c->dma_chan);
634 omap2_onenand_shutdown(pdev);
639 static const struct of_device_id omap2_onenand_id_table[] = {
640 { .compatible = "ti,omap2-onenand", },
643 MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
645 static struct platform_driver omap2_onenand_driver = {
646 .probe = omap2_onenand_probe,
647 .remove = omap2_onenand_remove,
648 .shutdown = omap2_onenand_shutdown,
651 .of_match_table = omap2_onenand_id_table,
655 module_platform_driver(omap2_onenand_driver);
657 MODULE_ALIAS("platform:" DRIVER_NAME);
658 MODULE_LICENSE("GPL");
659 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
660 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");