1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atmel MultiMedia Card Interface driver
5 * Copyright (C) 2004-2008 Atmel Corporation
7 #include <linux/blkdev.h>
9 #include <linux/debugfs.h>
10 #include <linux/device.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/types.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/sdio.h>
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <asm/cacheflush.h>
41 #include <asm/unaligned.h>
44 * Superset of MCI IP registers integrated in Atmel AT91 Processor
45 * Registers and bitfields marked with [2] are only available in MCI2
48 /* MCI Register Definitions */
49 #define ATMCI_CR 0x0000 /* Control */
50 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55 #define ATMCI_MR 0x0004 /* Mode */
56 #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57 #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59 #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60 #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61 #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63 #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64 #define ATMCI_DTOR 0x0008 /* Data Timeout */
65 #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66 #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67 #define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68 #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69 #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70 #define ATMCI_SDCSEL_MASK (3 << 0)
71 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74 #define ATMCI_SDCBUS_MASK (3 << 6)
75 #define ATMCI_ARGR 0x0010 /* Command Argument */
76 #define ATMCI_CMDR 0x0014 /* Command */
77 #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78 #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81 #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82 #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83 #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84 #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85 #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86 #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87 #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88 #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89 #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90 #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91 #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93 #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94 #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95 #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96 #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97 #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98 #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99 #define ATMCI_BLKR 0x0018 /* Block */
100 #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101 #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102 #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103 #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104 #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105 #define ATMCI_RSPR 0x0020 /* Response 0 */
106 #define ATMCI_RSPR1 0x0024 /* Response 1 */
107 #define ATMCI_RSPR2 0x0028 /* Response 2 */
108 #define ATMCI_RSPR3 0x002c /* Response 3 */
109 #define ATMCI_RDR 0x0030 /* Receive Data */
110 #define ATMCI_TDR 0x0034 /* Transmit Data */
111 #define ATMCI_SR 0x0040 /* Status */
112 #define ATMCI_IER 0x0044 /* Interrupt Enable */
113 #define ATMCI_IDR 0x0048 /* Interrupt Disable */
114 #define ATMCI_IMR 0x004c /* Interrupt Mask */
115 #define ATMCI_CMDRDY BIT(0) /* Command Ready */
116 #define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117 #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118 #define ATMCI_BLKE BIT(3) /* Data Block Ended */
119 #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120 #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121 #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122 #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123 #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124 #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125 #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126 #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127 #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128 #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129 #define ATMCI_RINDE BIT(16) /* Response Index Error */
130 #define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131 #define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132 #define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133 #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134 #define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135 #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136 #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137 #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138 #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139 #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140 #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141 #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142 #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143 #define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144 #define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145 #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146 #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147 #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148 #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149 #define ATMCI_CFG 0x0054 /* Configuration[2] */
150 #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151 #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152 #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153 #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155 #define ATMCI_WP_EN BIT(0) /* WP Enable */
156 #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157 #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158 #define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159 #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160 #define ATMCI_VERSION 0x00FC /* Version */
161 #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
163 /* This is not including the FIFO Aperture on MCI2 */
164 #define ATMCI_REGS_SIZE 0x100
166 /* Register access macros */
167 #define atmci_readl(port, reg) \
168 __raw_readl((port)->regs + reg)
169 #define atmci_writel(port, reg, value) \
170 __raw_writel((value), (port)->regs + reg)
172 #define AUTOSUSPEND_DELAY 50
174 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
175 #define ATMCI_DMA_THRESHOLD 16
184 enum atmel_mci_state {
188 STATE_WAITING_NOTBUSY,
193 enum atmci_xfer_dir {
203 struct atmel_mci_caps {
204 bool has_dma_conf_reg;
210 bool has_odd_clk_div;
211 bool has_bad_data_ordering;
212 bool need_reset_after_xfer;
213 bool need_blksz_mul_4;
214 bool need_notbusy_for_read_ops;
217 struct atmel_mci_dma {
218 struct dma_chan *chan;
219 struct dma_async_tx_descriptor *data_desc;
223 * struct atmel_mci - MMC controller state shared between all slots
224 * @lock: Spinlock protecting the queue and associated data.
225 * @regs: Pointer to MMIO registers.
226 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
227 * @pio_offset: Offset into the current scatterlist entry.
228 * @buffer: Buffer used if we don't have the r/w proof capability. We
229 * don't have the time to switch pdc buffers so we have to use only
230 * one buffer for the full transaction.
231 * @buf_size: size of the buffer.
232 * @phys_buf_addr: buffer address needed for pdc.
233 * @cur_slot: The slot which is currently using the controller.
234 * @mrq: The request currently being processed on @cur_slot,
235 * or NULL if the controller is idle.
236 * @cmd: The command currently being sent to the card, or NULL.
237 * @data: The data currently being transferred, or NULL if no data
238 * transfer is in progress.
239 * @data_size: just data->blocks * data->blksz.
240 * @dma: DMA client state.
241 * @data_chan: DMA channel being used for the current data transfer.
242 * @cmd_status: Snapshot of SR taken upon completion of the current
243 * command. Only valid when EVENT_CMD_COMPLETE is pending.
244 * @data_status: Snapshot of SR taken upon completion of the current
245 * data transfer. Only valid when EVENT_DATA_COMPLETE or
246 * EVENT_DATA_ERROR is pending.
247 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
249 * @tasklet: Tasklet running the request state machine.
250 * @pending_events: Bitmask of events flagged by the interrupt handler
251 * to be processed by the tasklet.
252 * @completed_events: Bitmask of events which the state machine has
254 * @state: Tasklet state.
255 * @queue: List of slots waiting for access to the controller.
256 * @need_clock_update: Update the clock rate before the next request.
257 * @need_reset: Reset controller before next request.
258 * @timer: Timer to balance the data timeout error flag which cannot rise.
259 * @mode_reg: Value of the MR register.
260 * @cfg_reg: Value of the CFG register.
261 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
262 * rate and timeout calculations.
263 * @mapbase: Physical address of the MMIO registers.
264 * @mck: The peripheral bus clock hooked up to the MMC controller.
265 * @pdev: Platform device associated with the MMC controller.
266 * @slot: Slots sharing this MMC controller.
267 * @caps: MCI capabilities depending on MCI version.
268 * @prepare_data: function to setup MCI before data transfer which
269 * depends on MCI capabilities.
270 * @submit_data: function to start data transfer which depends on MCI
272 * @stop_transfer: function to stop data transfer which depends on MCI
278 * @lock is a softirq-safe spinlock protecting @queue as well as
279 * @cur_slot, @mrq and @state. These must always be updated
280 * at the same time while holding @lock.
282 * @lock also protects mode_reg and need_clock_update since these are
283 * used to synchronize mode register updates with the queue
286 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
287 * and must always be written at the same time as the slot is added to
290 * @pending_events and @completed_events are accessed using atomic bit
291 * operations, so they don't need any locking.
293 * None of the fields touched by the interrupt handler need any
294 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
295 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
296 * interrupts must be disabled and @data_status updated with a
297 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
298 * CMDRDY interrupt must be disabled and @cmd_status updated with a
299 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
300 * bytes_xfered field of @data must be written. This is ensured by
307 struct scatterlist *sg;
309 unsigned int pio_offset;
310 unsigned int *buffer;
311 unsigned int buf_size;
312 dma_addr_t buf_phys_addr;
314 struct atmel_mci_slot *cur_slot;
315 struct mmc_request *mrq;
316 struct mmc_command *cmd;
317 struct mmc_data *data;
318 unsigned int data_size;
320 struct atmel_mci_dma dma;
321 struct dma_chan *data_chan;
322 struct dma_slave_config dma_conf;
328 struct tasklet_struct tasklet;
329 unsigned long pending_events;
330 unsigned long completed_events;
331 enum atmel_mci_state state;
332 struct list_head queue;
334 bool need_clock_update;
336 struct timer_list timer;
339 unsigned long bus_hz;
340 unsigned long mapbase;
342 struct platform_device *pdev;
344 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
346 struct atmel_mci_caps caps;
348 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
349 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
350 void (*stop_transfer)(struct atmel_mci *host);
354 * struct atmel_mci_slot - MMC slot state
355 * @mmc: The mmc_host representing this slot.
356 * @host: The MMC controller this slot is using.
357 * @sdc_reg: Value of SDCR to be written before using this slot.
358 * @sdio_irq: SDIO irq mask for this slot.
359 * @mrq: mmc_request currently being processed or waiting to be
360 * processed, or NULL when the slot is idle.
361 * @queue_node: List node for placing this node in the @queue list of
363 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
364 * @flags: Random state bits associated with the slot.
365 * @detect_pin: GPIO pin used for card detection, or negative if not
367 * @wp_pin: GPIO pin used for card write protect sending, or negative
369 * @detect_is_active_high: The state of the detect pin when it is active.
370 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
372 struct atmel_mci_slot {
373 struct mmc_host *mmc;
374 struct atmel_mci *host;
379 struct mmc_request *mrq;
380 struct list_head queue_node;
384 #define ATMCI_CARD_PRESENT 0
385 #define ATMCI_CARD_NEED_INIT 1
386 #define ATMCI_SHUTDOWN 2
390 bool detect_is_active_high;
392 struct timer_list detect_timer;
395 #define atmci_test_and_clear_pending(host, event) \
396 test_and_clear_bit(event, &host->pending_events)
397 #define atmci_set_completed(host, event) \
398 set_bit(event, &host->completed_events)
399 #define atmci_set_pending(host, event) \
400 set_bit(event, &host->pending_events)
403 * The debugfs stuff below is mostly optimized away when
404 * CONFIG_DEBUG_FS is not set.
406 static int atmci_req_show(struct seq_file *s, void *v)
408 struct atmel_mci_slot *slot = s->private;
409 struct mmc_request *mrq;
410 struct mmc_command *cmd;
411 struct mmc_command *stop;
412 struct mmc_data *data;
414 /* Make sure we get a consistent snapshot */
415 spin_lock_bh(&slot->host->lock);
425 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
426 cmd->opcode, cmd->arg, cmd->flags,
427 cmd->resp[0], cmd->resp[1], cmd->resp[2],
428 cmd->resp[3], cmd->error);
430 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
431 data->bytes_xfered, data->blocks,
432 data->blksz, data->flags, data->error);
435 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
436 stop->opcode, stop->arg, stop->flags,
437 stop->resp[0], stop->resp[1], stop->resp[2],
438 stop->resp[3], stop->error);
441 spin_unlock_bh(&slot->host->lock);
446 DEFINE_SHOW_ATTRIBUTE(atmci_req);
448 static void atmci_show_status_reg(struct seq_file *s,
449 const char *regname, u32 value)
451 static const char *sr_bit[] = {
482 seq_printf(s, "%s:\t0x%08x", regname, value);
483 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
484 if (value & (1 << i)) {
486 seq_printf(s, " %s", sr_bit[i]);
488 seq_puts(s, " UNKNOWN");
494 static int atmci_regs_show(struct seq_file *s, void *v)
496 struct atmel_mci *host = s->private;
501 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
505 pm_runtime_get_sync(&host->pdev->dev);
508 * Grab a more or less consistent snapshot. Note that we're
509 * not disabling interrupts, so IMR and SR may not be
512 spin_lock_bh(&host->lock);
513 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
514 spin_unlock_bh(&host->lock);
516 pm_runtime_mark_last_busy(&host->pdev->dev);
517 pm_runtime_put_autosuspend(&host->pdev->dev);
519 seq_printf(s, "MR:\t0x%08x%s%s ",
521 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
522 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
523 if (host->caps.has_odd_clk_div)
524 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
525 ((buf[ATMCI_MR / 4] & 0xff) << 1)
526 | ((buf[ATMCI_MR / 4] >> 16) & 1));
528 seq_printf(s, "CLKDIV=%u\n",
529 (buf[ATMCI_MR / 4] & 0xff));
530 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
531 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
532 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
533 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
535 buf[ATMCI_BLKR / 4] & 0xffff,
536 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
537 if (host->caps.has_cstor_reg)
538 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
540 /* Don't read RSPR and RDR; it will consume the data there */
542 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
543 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
545 if (host->caps.has_dma_conf_reg) {
548 val = buf[ATMCI_DMA / 4];
549 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
552 1 << (((val >> 4) & 3) + 1) : 1,
553 val & ATMCI_DMAEN ? " DMAEN" : "");
555 if (host->caps.has_cfg_reg) {
558 val = buf[ATMCI_CFG / 4];
559 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
561 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
562 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
563 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
564 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
572 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
574 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
576 struct mmc_host *mmc = slot->mmc;
577 struct atmel_mci *host = slot->host;
581 root = mmc->debugfs_root;
585 node = debugfs_create_file("regs", S_IRUSR, root, host,
592 node = debugfs_create_file("req", S_IRUSR, root, slot,
597 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
601 node = debugfs_create_x32("pending_events", S_IRUSR, root,
602 (u32 *)&host->pending_events);
606 node = debugfs_create_x32("completed_events", S_IRUSR, root,
607 (u32 *)&host->completed_events);
614 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
617 #if defined(CONFIG_OF)
618 static const struct of_device_id atmci_dt_ids[] = {
619 { .compatible = "atmel,hsmci" },
623 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
625 static struct mci_platform_data*
626 atmci_of_init(struct platform_device *pdev)
628 struct device_node *np = pdev->dev.of_node;
629 struct device_node *cnp;
630 struct mci_platform_data *pdata;
634 dev_err(&pdev->dev, "device node not found\n");
635 return ERR_PTR(-EINVAL);
638 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
640 return ERR_PTR(-ENOMEM);
642 for_each_child_of_node(np, cnp) {
643 if (of_property_read_u32(cnp, "reg", &slot_id)) {
644 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
649 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
650 dev_warn(&pdev->dev, "can't have more than %d slots\n",
656 if (of_property_read_u32(cnp, "bus-width",
657 &pdata->slot[slot_id].bus_width))
658 pdata->slot[slot_id].bus_width = 1;
660 pdata->slot[slot_id].detect_pin =
661 of_get_named_gpio(cnp, "cd-gpios", 0);
663 pdata->slot[slot_id].detect_is_active_high =
664 of_property_read_bool(cnp, "cd-inverted");
666 pdata->slot[slot_id].non_removable =
667 of_property_read_bool(cnp, "non-removable");
669 pdata->slot[slot_id].wp_pin =
670 of_get_named_gpio(cnp, "wp-gpios", 0);
675 #else /* CONFIG_OF */
676 static inline struct mci_platform_data*
677 atmci_of_init(struct platform_device *dev)
679 return ERR_PTR(-EINVAL);
683 static inline unsigned int atmci_get_version(struct atmel_mci *host)
685 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
689 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
690 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
691 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
694 * This can be done by finding most significant bit set.
696 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
697 unsigned int maxburst)
699 unsigned int version = atmci_get_version(host);
700 unsigned int offset = 2;
702 if (version >= 0x600)
706 return fls(maxburst) - offset;
711 static void atmci_timeout_timer(struct timer_list *t)
713 struct atmel_mci *host;
715 host = from_timer(host, t, timer);
717 dev_dbg(&host->pdev->dev, "software timeout\n");
719 if (host->mrq->cmd->data) {
720 host->mrq->cmd->data->error = -ETIMEDOUT;
723 * With some SDIO modules, sometimes DMA transfer hangs. If
724 * stop_transfer() is not called then the DMA request is not
725 * removed, following ones are queued and never computed.
727 if (host->state == STATE_DATA_XFER)
728 host->stop_transfer(host);
730 host->mrq->cmd->error = -ETIMEDOUT;
733 host->need_reset = 1;
734 host->state = STATE_END_REQUEST;
736 tasklet_schedule(&host->tasklet);
739 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
743 * It is easier here to use us instead of ns for the timeout,
744 * it prevents from overflows during calculation.
746 unsigned int us = DIV_ROUND_UP(ns, 1000);
748 /* Maximum clock frequency is host->bus_hz/2 */
749 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
752 static void atmci_set_timeout(struct atmel_mci *host,
753 struct atmel_mci_slot *slot, struct mmc_data *data)
755 static unsigned dtomul_to_shift[] = {
756 0, 4, 7, 8, 10, 12, 16, 20
762 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
763 + data->timeout_clks;
765 for (dtomul = 0; dtomul < 8; dtomul++) {
766 unsigned shift = dtomul_to_shift[dtomul];
767 dtocyc = (timeout + (1 << shift) - 1) >> shift;
777 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
778 dtocyc << dtomul_to_shift[dtomul]);
779 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
783 * Return mask with command flags to be enabled for this command.
785 static u32 atmci_prepare_command(struct mmc_host *mmc,
786 struct mmc_command *cmd)
788 struct mmc_data *data;
791 cmd->error = -EINPROGRESS;
793 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
795 if (cmd->flags & MMC_RSP_PRESENT) {
796 if (cmd->flags & MMC_RSP_136)
797 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
799 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
803 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
804 * it's too difficult to determine whether this is an ACMD or
805 * not. Better make it 64.
807 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
809 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
810 cmdr |= ATMCI_CMDR_OPDCMD;
814 cmdr |= ATMCI_CMDR_START_XFER;
816 if (cmd->opcode == SD_IO_RW_EXTENDED) {
817 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
819 if (data->blocks > 1)
820 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
822 cmdr |= ATMCI_CMDR_BLOCK;
825 if (data->flags & MMC_DATA_READ)
826 cmdr |= ATMCI_CMDR_TRDIR_READ;
832 static void atmci_send_command(struct atmel_mci *host,
833 struct mmc_command *cmd, u32 cmd_flags)
838 dev_vdbg(&host->pdev->dev,
839 "start command: ARGR=0x%08x CMDR=0x%08x\n",
840 cmd->arg, cmd_flags);
842 atmci_writel(host, ATMCI_ARGR, cmd->arg);
843 atmci_writel(host, ATMCI_CMDR, cmd_flags);
846 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
848 dev_dbg(&host->pdev->dev, "send stop command\n");
849 atmci_send_command(host, data->stop, host->stop_cmdr);
850 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
854 * Configure given PDC buffer taking care of alignement issues.
855 * Update host->data_size and host->sg.
857 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
858 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
860 u32 pointer_reg, counter_reg;
861 unsigned int buf_size;
863 if (dir == XFER_RECEIVE) {
864 pointer_reg = ATMEL_PDC_RPR;
865 counter_reg = ATMEL_PDC_RCR;
867 pointer_reg = ATMEL_PDC_TPR;
868 counter_reg = ATMEL_PDC_TCR;
871 if (buf_nb == PDC_SECOND_BUF) {
872 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
873 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
876 if (!host->caps.has_rwproof) {
877 buf_size = host->buf_size;
878 atmci_writel(host, pointer_reg, host->buf_phys_addr);
880 buf_size = sg_dma_len(host->sg);
881 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
884 if (host->data_size <= buf_size) {
885 if (host->data_size & 0x3) {
886 /* If size is different from modulo 4, transfer bytes */
887 atmci_writel(host, counter_reg, host->data_size);
888 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
890 /* Else transfer 32-bits words */
891 atmci_writel(host, counter_reg, host->data_size / 4);
895 /* We assume the size of a page is 32-bits aligned */
896 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
897 host->data_size -= sg_dma_len(host->sg);
899 host->sg = sg_next(host->sg);
904 * Configure PDC buffer according to the data size ie configuring one or two
905 * buffers. Don't use this function if you want to configure only the second
906 * buffer. In this case, use atmci_pdc_set_single_buf.
908 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
910 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
912 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
916 * Unmap sg lists, called when transfer is finished.
918 static void atmci_pdc_cleanup(struct atmel_mci *host)
920 struct mmc_data *data = host->data;
923 dma_unmap_sg(&host->pdev->dev,
924 data->sg, data->sg_len,
925 mmc_get_dma_dir(data));
929 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
930 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
931 * interrupt needed for both transfer directions.
933 static void atmci_pdc_complete(struct atmel_mci *host)
935 int transfer_size = host->data->blocks * host->data->blksz;
938 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
940 if ((!host->caps.has_rwproof)
941 && (host->data->flags & MMC_DATA_READ)) {
942 if (host->caps.has_bad_data_ordering)
943 for (i = 0; i < transfer_size; i++)
944 host->buffer[i] = swab32(host->buffer[i]);
945 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
946 host->buffer, transfer_size);
949 atmci_pdc_cleanup(host);
951 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
952 atmci_set_pending(host, EVENT_XFER_COMPLETE);
953 tasklet_schedule(&host->tasklet);
956 static void atmci_dma_cleanup(struct atmel_mci *host)
958 struct mmc_data *data = host->data;
961 dma_unmap_sg(host->dma.chan->device->dev,
962 data->sg, data->sg_len,
963 mmc_get_dma_dir(data));
967 * This function is called by the DMA driver from tasklet context.
969 static void atmci_dma_complete(void *arg)
971 struct atmel_mci *host = arg;
972 struct mmc_data *data = host->data;
974 dev_vdbg(&host->pdev->dev, "DMA complete\n");
976 if (host->caps.has_dma_conf_reg)
977 /* Disable DMA hardware handshaking on MCI */
978 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
980 atmci_dma_cleanup(host);
983 * If the card was removed, data will be NULL. No point trying
984 * to send the stop command or waiting for NBUSY in this case.
987 dev_dbg(&host->pdev->dev,
988 "(%s) set pending xfer complete\n", __func__);
989 atmci_set_pending(host, EVENT_XFER_COMPLETE);
990 tasklet_schedule(&host->tasklet);
993 * Regardless of what the documentation says, we have
994 * to wait for NOTBUSY even after block read
997 * When the DMA transfer is complete, the controller
998 * may still be reading the CRC from the card, i.e.
999 * the data transfer is still in progress and we
1000 * haven't seen all the potential error bits yet.
1002 * The interrupt handler will schedule a different
1003 * tasklet to finish things up when the data transfer
1004 * is completely done.
1006 * We may not complete the mmc request here anyway
1007 * because the mmc layer may call back and cause us to
1008 * violate the "don't submit new operations from the
1009 * completion callback" rule of the dma engine
1012 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1017 * Returns a mask of interrupt flags to be enabled after the whole
1018 * request has been prepared.
1020 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1024 data->error = -EINPROGRESS;
1026 host->sg = data->sg;
1027 host->sg_len = data->sg_len;
1029 host->data_chan = NULL;
1031 iflags = ATMCI_DATA_ERROR_FLAGS;
1034 * Errata: MMC data write operation with less than 12
1035 * bytes is impossible.
1037 * Errata: MCI Transmit Data Register (TDR) FIFO
1038 * corruption when length is not multiple of 4.
1040 if (data->blocks * data->blksz < 12
1041 || (data->blocks * data->blksz) & 3)
1042 host->need_reset = true;
1044 host->pio_offset = 0;
1045 if (data->flags & MMC_DATA_READ)
1046 iflags |= ATMCI_RXRDY;
1048 iflags |= ATMCI_TXRDY;
1054 * Set interrupt flags and set block length into the MCI mode register even
1055 * if this value is also accessible in the MCI block register. It seems to be
1056 * necessary before the High Speed MCI version. It also map sg and configure
1060 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1065 data->error = -EINPROGRESS;
1068 host->sg = data->sg;
1069 iflags = ATMCI_DATA_ERROR_FLAGS;
1071 /* Enable pdc mode */
1072 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1074 if (data->flags & MMC_DATA_READ)
1075 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1077 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1080 tmp = atmci_readl(host, ATMCI_MR);
1082 tmp |= ATMCI_BLKLEN(data->blksz);
1083 atmci_writel(host, ATMCI_MR, tmp);
1086 host->data_size = data->blocks * data->blksz;
1087 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1088 mmc_get_dma_dir(data));
1090 if ((!host->caps.has_rwproof)
1091 && (host->data->flags & MMC_DATA_WRITE)) {
1092 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1093 host->buffer, host->data_size);
1094 if (host->caps.has_bad_data_ordering)
1095 for (i = 0; i < host->data_size; i++)
1096 host->buffer[i] = swab32(host->buffer[i]);
1099 if (host->data_size)
1100 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1101 XFER_RECEIVE : XFER_TRANSMIT);
1106 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1108 struct dma_chan *chan;
1109 struct dma_async_tx_descriptor *desc;
1110 struct scatterlist *sg;
1112 enum dma_transfer_direction slave_dirn;
1117 data->error = -EINPROGRESS;
1119 WARN_ON(host->data);
1123 iflags = ATMCI_DATA_ERROR_FLAGS;
1126 * We don't do DMA on "complex" transfers, i.e. with
1127 * non-word-aligned buffers or lengths. Also, we don't bother
1128 * with all the DMA setup overhead for short transfers.
1130 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1131 return atmci_prepare_data(host, data);
1132 if (data->blksz & 3)
1133 return atmci_prepare_data(host, data);
1135 for_each_sg(data->sg, sg, data->sg_len, i) {
1136 if (sg->offset & 3 || sg->length & 3)
1137 return atmci_prepare_data(host, data);
1140 /* If we don't have a channel, we can't do DMA */
1141 chan = host->dma.chan;
1143 host->data_chan = chan;
1148 if (data->flags & MMC_DATA_READ) {
1149 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1150 maxburst = atmci_convert_chksize(host,
1151 host->dma_conf.src_maxburst);
1153 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1154 maxburst = atmci_convert_chksize(host,
1155 host->dma_conf.dst_maxburst);
1158 if (host->caps.has_dma_conf_reg)
1159 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1162 sglen = dma_map_sg(chan->device->dev, data->sg,
1163 data->sg_len, mmc_get_dma_dir(data));
1165 dmaengine_slave_config(chan, &host->dma_conf);
1166 desc = dmaengine_prep_slave_sg(chan,
1167 data->sg, sglen, slave_dirn,
1168 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1172 host->dma.data_desc = desc;
1173 desc->callback = atmci_dma_complete;
1174 desc->callback_param = host;
1178 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1179 mmc_get_dma_dir(data));
1184 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1190 * Start PDC according to transfer direction.
1193 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1195 if (data->flags & MMC_DATA_READ)
1196 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1198 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1202 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1204 struct dma_chan *chan = host->data_chan;
1205 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1208 dmaengine_submit(desc);
1209 dma_async_issue_pending(chan);
1213 static void atmci_stop_transfer(struct atmel_mci *host)
1215 dev_dbg(&host->pdev->dev,
1216 "(%s) set pending xfer complete\n", __func__);
1217 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1218 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1222 * Stop data transfer because error(s) occurred.
1224 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1226 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1229 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1231 struct dma_chan *chan = host->data_chan;
1234 dmaengine_terminate_all(chan);
1235 atmci_dma_cleanup(host);
1237 /* Data transfer was stopped by the interrupt handler */
1238 dev_dbg(&host->pdev->dev,
1239 "(%s) set pending xfer complete\n", __func__);
1240 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1241 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1246 * Start a request: prepare data if needed, prepare the command and activate
1249 static void atmci_start_request(struct atmel_mci *host,
1250 struct atmel_mci_slot *slot)
1252 struct mmc_request *mrq;
1253 struct mmc_command *cmd;
1254 struct mmc_data *data;
1259 host->cur_slot = slot;
1262 host->pending_events = 0;
1263 host->completed_events = 0;
1264 host->cmd_status = 0;
1265 host->data_status = 0;
1267 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1269 if (host->need_reset || host->caps.need_reset_after_xfer) {
1270 iflags = atmci_readl(host, ATMCI_IMR);
1271 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1272 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1273 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1274 atmci_writel(host, ATMCI_MR, host->mode_reg);
1275 if (host->caps.has_cfg_reg)
1276 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1277 atmci_writel(host, ATMCI_IER, iflags);
1278 host->need_reset = false;
1280 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1282 iflags = atmci_readl(host, ATMCI_IMR);
1283 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1284 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1287 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1288 /* Send init sequence (74 clock cycles) */
1289 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1290 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1296 atmci_set_timeout(host, slot, data);
1298 /* Must set block count/size before sending command */
1299 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1300 | ATMCI_BLKLEN(data->blksz));
1301 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1302 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1304 iflags |= host->prepare_data(host, data);
1307 iflags |= ATMCI_CMDRDY;
1309 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1312 * DMA transfer should be started before sending the command to avoid
1313 * unexpected errors especially for read operations in SDIO mode.
1314 * Unfortunately, in PDC mode, command has to be sent before starting
1317 if (host->submit_data != &atmci_submit_data_dma)
1318 atmci_send_command(host, cmd, cmdflags);
1321 host->submit_data(host, data);
1323 if (host->submit_data == &atmci_submit_data_dma)
1324 atmci_send_command(host, cmd, cmdflags);
1327 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1328 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1329 if (!(data->flags & MMC_DATA_WRITE))
1330 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1331 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1335 * We could have enabled interrupts earlier, but I suspect
1336 * that would open up a nice can of interesting race
1337 * conditions (e.g. command and data complete, but stop not
1340 atmci_writel(host, ATMCI_IER, iflags);
1342 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1345 static void atmci_queue_request(struct atmel_mci *host,
1346 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1348 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1351 spin_lock_bh(&host->lock);
1353 if (host->state == STATE_IDLE) {
1354 host->state = STATE_SENDING_CMD;
1355 atmci_start_request(host, slot);
1357 dev_dbg(&host->pdev->dev, "queue request\n");
1358 list_add_tail(&slot->queue_node, &host->queue);
1360 spin_unlock_bh(&host->lock);
1363 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1365 struct atmel_mci_slot *slot = mmc_priv(mmc);
1366 struct atmel_mci *host = slot->host;
1367 struct mmc_data *data;
1370 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1373 * We may "know" the card is gone even though there's still an
1374 * electrical connection. If so, we really need to communicate
1375 * this to the MMC core since there won't be any more
1376 * interrupts as the card is completely removed. Otherwise,
1377 * the MMC core might believe the card is still there even
1378 * though the card was just removed very slowly.
1380 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1381 mrq->cmd->error = -ENOMEDIUM;
1382 mmc_request_done(mmc, mrq);
1386 /* We don't support multiple blocks of weird lengths. */
1388 if (data && data->blocks > 1 && data->blksz & 3) {
1389 mrq->cmd->error = -EINVAL;
1390 mmc_request_done(mmc, mrq);
1393 atmci_queue_request(host, slot, mrq);
1396 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1398 struct atmel_mci_slot *slot = mmc_priv(mmc);
1399 struct atmel_mci *host = slot->host;
1402 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1403 switch (ios->bus_width) {
1404 case MMC_BUS_WIDTH_1:
1405 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1407 case MMC_BUS_WIDTH_4:
1408 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1410 case MMC_BUS_WIDTH_8:
1411 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1416 unsigned int clock_min = ~0U;
1419 spin_lock_bh(&host->lock);
1420 if (!host->mode_reg) {
1421 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1422 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1423 if (host->caps.has_cfg_reg)
1424 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1428 * Use mirror of ios->clock to prevent race with mmc
1429 * core ios update when finding the minimum.
1431 slot->clock = ios->clock;
1432 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1433 if (host->slot[i] && host->slot[i]->clock
1434 && host->slot[i]->clock < clock_min)
1435 clock_min = host->slot[i]->clock;
1438 /* Calculate clock divider */
1439 if (host->caps.has_odd_clk_div) {
1440 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1442 dev_warn(&mmc->class_dev,
1443 "clock %u too fast; using %lu\n",
1444 clock_min, host->bus_hz / 2);
1446 } else if (clkdiv > 511) {
1447 dev_warn(&mmc->class_dev,
1448 "clock %u too slow; using %lu\n",
1449 clock_min, host->bus_hz / (511 + 2));
1452 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1453 | ATMCI_MR_CLKODD(clkdiv & 1);
1455 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1457 dev_warn(&mmc->class_dev,
1458 "clock %u too slow; using %lu\n",
1459 clock_min, host->bus_hz / (2 * 256));
1462 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1466 * WRPROOF and RDPROOF prevent overruns/underruns by
1467 * stopping the clock when the FIFO is full/empty.
1468 * This state is not expected to last for long.
1470 if (host->caps.has_rwproof)
1471 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1473 if (host->caps.has_cfg_reg) {
1474 /* setup High Speed mode in relation with card capacity */
1475 if (ios->timing == MMC_TIMING_SD_HS)
1476 host->cfg_reg |= ATMCI_CFG_HSMODE;
1478 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1481 if (list_empty(&host->queue)) {
1482 atmci_writel(host, ATMCI_MR, host->mode_reg);
1483 if (host->caps.has_cfg_reg)
1484 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1486 host->need_clock_update = true;
1489 spin_unlock_bh(&host->lock);
1491 bool any_slot_active = false;
1493 spin_lock_bh(&host->lock);
1495 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1496 if (host->slot[i] && host->slot[i]->clock) {
1497 any_slot_active = true;
1501 if (!any_slot_active) {
1502 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1503 if (host->mode_reg) {
1504 atmci_readl(host, ATMCI_MR);
1508 spin_unlock_bh(&host->lock);
1511 switch (ios->power_mode) {
1513 if (!IS_ERR(mmc->supply.vmmc))
1514 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1517 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1518 if (!IS_ERR(mmc->supply.vmmc))
1519 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1526 static int atmci_get_ro(struct mmc_host *mmc)
1528 int read_only = -ENOSYS;
1529 struct atmel_mci_slot *slot = mmc_priv(mmc);
1531 if (gpio_is_valid(slot->wp_pin)) {
1532 read_only = gpio_get_value(slot->wp_pin);
1533 dev_dbg(&mmc->class_dev, "card is %s\n",
1534 read_only ? "read-only" : "read-write");
1540 static int atmci_get_cd(struct mmc_host *mmc)
1542 int present = -ENOSYS;
1543 struct atmel_mci_slot *slot = mmc_priv(mmc);
1545 if (gpio_is_valid(slot->detect_pin)) {
1546 present = !(gpio_get_value(slot->detect_pin) ^
1547 slot->detect_is_active_high);
1548 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1549 present ? "" : "not ");
1555 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1557 struct atmel_mci_slot *slot = mmc_priv(mmc);
1558 struct atmel_mci *host = slot->host;
1561 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1563 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1566 static const struct mmc_host_ops atmci_ops = {
1567 .request = atmci_request,
1568 .set_ios = atmci_set_ios,
1569 .get_ro = atmci_get_ro,
1570 .get_cd = atmci_get_cd,
1571 .enable_sdio_irq = atmci_enable_sdio_irq,
1574 /* Called with host->lock held */
1575 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1576 __releases(&host->lock)
1577 __acquires(&host->lock)
1579 struct atmel_mci_slot *slot = NULL;
1580 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1582 WARN_ON(host->cmd || host->data);
1585 * Update the MMC clock rate if necessary. This may be
1586 * necessary if set_ios() is called when a different slot is
1587 * busy transferring data.
1589 if (host->need_clock_update) {
1590 atmci_writel(host, ATMCI_MR, host->mode_reg);
1591 if (host->caps.has_cfg_reg)
1592 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1595 host->cur_slot->mrq = NULL;
1597 if (!list_empty(&host->queue)) {
1598 slot = list_entry(host->queue.next,
1599 struct atmel_mci_slot, queue_node);
1600 list_del(&slot->queue_node);
1601 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1602 mmc_hostname(slot->mmc));
1603 host->state = STATE_SENDING_CMD;
1604 atmci_start_request(host, slot);
1606 dev_vdbg(&host->pdev->dev, "list empty\n");
1607 host->state = STATE_IDLE;
1610 del_timer(&host->timer);
1612 spin_unlock(&host->lock);
1613 mmc_request_done(prev_mmc, mrq);
1614 spin_lock(&host->lock);
1617 static void atmci_command_complete(struct atmel_mci *host,
1618 struct mmc_command *cmd)
1620 u32 status = host->cmd_status;
1622 /* Read the response from the card (up to 16 bytes) */
1623 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1624 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1625 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1626 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1628 if (status & ATMCI_RTOE)
1629 cmd->error = -ETIMEDOUT;
1630 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1631 cmd->error = -EILSEQ;
1632 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1634 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1635 if (host->caps.need_blksz_mul_4) {
1636 cmd->error = -EINVAL;
1637 host->need_reset = 1;
1643 static void atmci_detect_change(struct timer_list *t)
1645 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1650 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1651 * freeing the interrupt. We must not re-enable the interrupt
1652 * if it has been freed, and if we're shutting down, it
1653 * doesn't really matter whether the card is present or not.
1656 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1659 enable_irq(gpio_to_irq(slot->detect_pin));
1660 present = !(gpio_get_value(slot->detect_pin) ^
1661 slot->detect_is_active_high);
1662 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1664 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1665 present, present_old);
1667 if (present != present_old) {
1668 struct atmel_mci *host = slot->host;
1669 struct mmc_request *mrq;
1671 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1672 present ? "inserted" : "removed");
1674 spin_lock(&host->lock);
1677 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1679 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1681 /* Clean up queue if present */
1684 if (mrq == host->mrq) {
1686 * Reset controller to terminate any ongoing
1687 * commands or data transfers.
1689 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1690 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1691 atmci_writel(host, ATMCI_MR, host->mode_reg);
1692 if (host->caps.has_cfg_reg)
1693 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1698 switch (host->state) {
1701 case STATE_SENDING_CMD:
1702 mrq->cmd->error = -ENOMEDIUM;
1704 host->stop_transfer(host);
1706 case STATE_DATA_XFER:
1707 mrq->data->error = -ENOMEDIUM;
1708 host->stop_transfer(host);
1710 case STATE_WAITING_NOTBUSY:
1711 mrq->data->error = -ENOMEDIUM;
1713 case STATE_SENDING_STOP:
1714 mrq->stop->error = -ENOMEDIUM;
1716 case STATE_END_REQUEST:
1720 atmci_request_end(host, mrq);
1722 list_del(&slot->queue_node);
1723 mrq->cmd->error = -ENOMEDIUM;
1725 mrq->data->error = -ENOMEDIUM;
1727 mrq->stop->error = -ENOMEDIUM;
1729 spin_unlock(&host->lock);
1730 mmc_request_done(slot->mmc, mrq);
1731 spin_lock(&host->lock);
1734 spin_unlock(&host->lock);
1736 mmc_detect_change(slot->mmc, 0);
1740 static void atmci_tasklet_func(unsigned long priv)
1742 struct atmel_mci *host = (struct atmel_mci *)priv;
1743 struct mmc_request *mrq = host->mrq;
1744 struct mmc_data *data = host->data;
1745 enum atmel_mci_state state = host->state;
1746 enum atmel_mci_state prev_state;
1749 spin_lock(&host->lock);
1751 state = host->state;
1753 dev_vdbg(&host->pdev->dev,
1754 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1755 state, host->pending_events, host->completed_events,
1756 atmci_readl(host, ATMCI_IMR));
1760 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1766 case STATE_SENDING_CMD:
1768 * Command has been sent, we are waiting for command
1769 * ready. Then we have three next states possible:
1770 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1771 * command needing it or DATA_XFER if there is data.
1773 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1774 if (!atmci_test_and_clear_pending(host,
1778 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1780 atmci_set_completed(host, EVENT_CMD_RDY);
1781 atmci_command_complete(host, mrq->cmd);
1783 dev_dbg(&host->pdev->dev,
1784 "command with data transfer");
1786 * If there is a command error don't start
1789 if (mrq->cmd->error) {
1790 host->stop_transfer(host);
1792 atmci_writel(host, ATMCI_IDR,
1793 ATMCI_TXRDY | ATMCI_RXRDY
1794 | ATMCI_DATA_ERROR_FLAGS);
1795 state = STATE_END_REQUEST;
1797 state = STATE_DATA_XFER;
1798 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1799 dev_dbg(&host->pdev->dev,
1800 "command response need waiting notbusy");
1801 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1802 state = STATE_WAITING_NOTBUSY;
1804 state = STATE_END_REQUEST;
1808 case STATE_DATA_XFER:
1809 if (atmci_test_and_clear_pending(host,
1810 EVENT_DATA_ERROR)) {
1811 dev_dbg(&host->pdev->dev, "set completed data error\n");
1812 atmci_set_completed(host, EVENT_DATA_ERROR);
1813 state = STATE_END_REQUEST;
1818 * A data transfer is in progress. The event expected
1819 * to move to the next state depends of data transfer
1820 * type (PDC or DMA). Once transfer done we can move
1821 * to the next step which is WAITING_NOTBUSY in write
1822 * case and directly SENDING_STOP in read case.
1824 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1825 if (!atmci_test_and_clear_pending(host,
1826 EVENT_XFER_COMPLETE))
1829 dev_dbg(&host->pdev->dev,
1830 "(%s) set completed xfer complete\n",
1832 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1834 if (host->caps.need_notbusy_for_read_ops ||
1835 (host->data->flags & MMC_DATA_WRITE)) {
1836 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1837 state = STATE_WAITING_NOTBUSY;
1838 } else if (host->mrq->stop) {
1839 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1840 atmci_send_stop_cmd(host, data);
1841 state = STATE_SENDING_STOP;
1844 data->bytes_xfered = data->blocks * data->blksz;
1846 state = STATE_END_REQUEST;
1850 case STATE_WAITING_NOTBUSY:
1852 * We can be in the state for two reasons: a command
1853 * requiring waiting not busy signal (stop command
1854 * included) or a write operation. In the latest case,
1855 * we need to send a stop command.
1857 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1858 if (!atmci_test_and_clear_pending(host,
1862 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1863 atmci_set_completed(host, EVENT_NOTBUSY);
1867 * For some commands such as CMD53, even if
1868 * there is data transfer, there is no stop
1871 if (host->mrq->stop) {
1872 atmci_writel(host, ATMCI_IER,
1874 atmci_send_stop_cmd(host, data);
1875 state = STATE_SENDING_STOP;
1878 data->bytes_xfered = data->blocks
1881 state = STATE_END_REQUEST;
1884 state = STATE_END_REQUEST;
1887 case STATE_SENDING_STOP:
1889 * In this state, it is important to set host->data to
1890 * NULL (which is tested in the waiting notbusy state)
1891 * in order to go to the end request state instead of
1892 * sending stop again.
1894 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1895 if (!atmci_test_and_clear_pending(host,
1899 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1901 data->bytes_xfered = data->blocks * data->blksz;
1903 atmci_command_complete(host, mrq->stop);
1904 if (mrq->stop->error) {
1905 host->stop_transfer(host);
1906 atmci_writel(host, ATMCI_IDR,
1907 ATMCI_TXRDY | ATMCI_RXRDY
1908 | ATMCI_DATA_ERROR_FLAGS);
1909 state = STATE_END_REQUEST;
1911 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1912 state = STATE_WAITING_NOTBUSY;
1917 case STATE_END_REQUEST:
1918 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1919 | ATMCI_DATA_ERROR_FLAGS);
1920 status = host->data_status;
1921 if (unlikely(status)) {
1922 host->stop_transfer(host);
1925 if (status & ATMCI_DTOE) {
1926 data->error = -ETIMEDOUT;
1927 } else if (status & ATMCI_DCRCE) {
1928 data->error = -EILSEQ;
1935 atmci_request_end(host, host->mrq);
1936 goto unlock; /* atmci_request_end() sets host->state */
1939 } while (state != prev_state);
1941 host->state = state;
1944 spin_unlock(&host->lock);
1947 static void atmci_read_data_pio(struct atmel_mci *host)
1949 struct scatterlist *sg = host->sg;
1950 unsigned int offset = host->pio_offset;
1951 struct mmc_data *data = host->data;
1954 unsigned int nbytes = 0;
1957 value = atmci_readl(host, ATMCI_RDR);
1958 if (likely(offset + 4 <= sg->length)) {
1959 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1964 if (offset == sg->length) {
1965 flush_dcache_page(sg_page(sg));
1966 host->sg = sg = sg_next(sg);
1968 if (!sg || !host->sg_len)
1974 unsigned int remaining = sg->length - offset;
1976 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1977 nbytes += remaining;
1979 flush_dcache_page(sg_page(sg));
1980 host->sg = sg = sg_next(sg);
1982 if (!sg || !host->sg_len)
1985 offset = 4 - remaining;
1986 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1991 status = atmci_readl(host, ATMCI_SR);
1992 if (status & ATMCI_DATA_ERROR_FLAGS) {
1993 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1994 | ATMCI_DATA_ERROR_FLAGS));
1995 host->data_status = status;
1996 data->bytes_xfered += nbytes;
1999 } while (status & ATMCI_RXRDY);
2001 host->pio_offset = offset;
2002 data->bytes_xfered += nbytes;
2007 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2008 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2009 data->bytes_xfered += nbytes;
2011 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2014 static void atmci_write_data_pio(struct atmel_mci *host)
2016 struct scatterlist *sg = host->sg;
2017 unsigned int offset = host->pio_offset;
2018 struct mmc_data *data = host->data;
2021 unsigned int nbytes = 0;
2024 if (likely(offset + 4 <= sg->length)) {
2025 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2026 atmci_writel(host, ATMCI_TDR, value);
2030 if (offset == sg->length) {
2031 host->sg = sg = sg_next(sg);
2033 if (!sg || !host->sg_len)
2039 unsigned int remaining = sg->length - offset;
2042 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2043 nbytes += remaining;
2045 host->sg = sg = sg_next(sg);
2047 if (!sg || !host->sg_len) {
2048 atmci_writel(host, ATMCI_TDR, value);
2052 offset = 4 - remaining;
2053 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2055 atmci_writel(host, ATMCI_TDR, value);
2059 status = atmci_readl(host, ATMCI_SR);
2060 if (status & ATMCI_DATA_ERROR_FLAGS) {
2061 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2062 | ATMCI_DATA_ERROR_FLAGS));
2063 host->data_status = status;
2064 data->bytes_xfered += nbytes;
2067 } while (status & ATMCI_TXRDY);
2069 host->pio_offset = offset;
2070 data->bytes_xfered += nbytes;
2075 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2076 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2077 data->bytes_xfered += nbytes;
2079 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2082 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2086 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2087 struct atmel_mci_slot *slot = host->slot[i];
2088 if (slot && (status & slot->sdio_irq)) {
2089 mmc_signal_sdio_irq(slot->mmc);
2095 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2097 struct atmel_mci *host = dev_id;
2098 u32 status, mask, pending;
2099 unsigned int pass_count = 0;
2102 status = atmci_readl(host, ATMCI_SR);
2103 mask = atmci_readl(host, ATMCI_IMR);
2104 pending = status & mask;
2108 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2109 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2110 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2111 | ATMCI_RXRDY | ATMCI_TXRDY
2112 | ATMCI_ENDRX | ATMCI_ENDTX
2113 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2115 host->data_status = status;
2116 dev_dbg(&host->pdev->dev, "set pending data error\n");
2118 atmci_set_pending(host, EVENT_DATA_ERROR);
2119 tasklet_schedule(&host->tasklet);
2122 if (pending & ATMCI_TXBUFE) {
2123 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2124 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2125 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2127 * We can receive this interruption before having configured
2128 * the second pdc buffer, so we need to reconfigure first and
2129 * second buffers again
2131 if (host->data_size) {
2132 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2133 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2134 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2136 atmci_pdc_complete(host);
2138 } else if (pending & ATMCI_ENDTX) {
2139 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2140 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2142 if (host->data_size) {
2143 atmci_pdc_set_single_buf(host,
2144 XFER_TRANSMIT, PDC_SECOND_BUF);
2145 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2149 if (pending & ATMCI_RXBUFF) {
2150 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2151 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2152 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2154 * We can receive this interruption before having configured
2155 * the second pdc buffer, so we need to reconfigure first and
2156 * second buffers again
2158 if (host->data_size) {
2159 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2160 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2161 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2163 atmci_pdc_complete(host);
2165 } else if (pending & ATMCI_ENDRX) {
2166 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2167 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2169 if (host->data_size) {
2170 atmci_pdc_set_single_buf(host,
2171 XFER_RECEIVE, PDC_SECOND_BUF);
2172 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2177 * First mci IPs, so mainly the ones having pdc, have some
2178 * issues with the notbusy signal. You can't get it after
2179 * data transmission if you have not sent a stop command.
2180 * The appropriate workaround is to use the BLKE signal.
2182 if (pending & ATMCI_BLKE) {
2183 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2184 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2186 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2187 atmci_set_pending(host, EVENT_NOTBUSY);
2188 tasklet_schedule(&host->tasklet);
2191 if (pending & ATMCI_NOTBUSY) {
2192 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2193 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2195 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2196 atmci_set_pending(host, EVENT_NOTBUSY);
2197 tasklet_schedule(&host->tasklet);
2200 if (pending & ATMCI_RXRDY)
2201 atmci_read_data_pio(host);
2202 if (pending & ATMCI_TXRDY)
2203 atmci_write_data_pio(host);
2205 if (pending & ATMCI_CMDRDY) {
2206 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2207 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2208 host->cmd_status = status;
2210 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2211 atmci_set_pending(host, EVENT_CMD_RDY);
2212 tasklet_schedule(&host->tasklet);
2215 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2216 atmci_sdio_interrupt(host, status);
2218 } while (pass_count++ < 5);
2220 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2223 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2225 struct atmel_mci_slot *slot = dev_id;
2228 * Disable interrupts until the pin has stabilized and check
2229 * the state then. Use mod_timer() since we may be in the
2230 * middle of the timer routine when this interrupt triggers.
2232 disable_irq_nosync(irq);
2233 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2238 static int atmci_init_slot(struct atmel_mci *host,
2239 struct mci_slot_pdata *slot_data, unsigned int id,
2240 u32 sdc_reg, u32 sdio_irq)
2242 struct mmc_host *mmc;
2243 struct atmel_mci_slot *slot;
2245 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2249 slot = mmc_priv(mmc);
2252 slot->detect_pin = slot_data->detect_pin;
2253 slot->wp_pin = slot_data->wp_pin;
2254 slot->detect_is_active_high = slot_data->detect_is_active_high;
2255 slot->sdc_reg = sdc_reg;
2256 slot->sdio_irq = sdio_irq;
2258 dev_dbg(&mmc->class_dev,
2259 "slot[%u]: bus_width=%u, detect_pin=%d, "
2260 "detect_is_active_high=%s, wp_pin=%d\n",
2261 id, slot_data->bus_width, slot_data->detect_pin,
2262 slot_data->detect_is_active_high ? "true" : "false",
2265 mmc->ops = &atmci_ops;
2266 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2267 mmc->f_max = host->bus_hz / 2;
2268 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2270 mmc->caps |= MMC_CAP_SDIO_IRQ;
2271 if (host->caps.has_highspeed)
2272 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2274 * Without the read/write proof capability, it is strongly suggested to
2275 * use only one bit for data to prevent fifo underruns and overruns
2276 * which will corrupt data.
2278 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2279 mmc->caps |= MMC_CAP_4_BIT_DATA;
2280 if (slot_data->bus_width >= 8)
2281 mmc->caps |= MMC_CAP_8_BIT_DATA;
2284 if (atmci_get_version(host) < 0x200) {
2285 mmc->max_segs = 256;
2286 mmc->max_blk_size = 4095;
2287 mmc->max_blk_count = 256;
2288 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2289 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2292 mmc->max_req_size = 32768 * 512;
2293 mmc->max_blk_size = 32768;
2294 mmc->max_blk_count = 512;
2297 /* Assume card is present initially */
2298 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2299 if (gpio_is_valid(slot->detect_pin)) {
2300 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2302 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2303 slot->detect_pin = -EBUSY;
2304 } else if (gpio_get_value(slot->detect_pin) ^
2305 slot->detect_is_active_high) {
2306 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2310 if (!gpio_is_valid(slot->detect_pin)) {
2311 if (slot_data->non_removable)
2312 mmc->caps |= MMC_CAP_NONREMOVABLE;
2314 mmc->caps |= MMC_CAP_NEEDS_POLL;
2317 if (gpio_is_valid(slot->wp_pin)) {
2318 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2320 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2321 slot->wp_pin = -EBUSY;
2325 host->slot[id] = slot;
2326 mmc_regulator_get_supply(mmc);
2329 if (gpio_is_valid(slot->detect_pin)) {
2332 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2334 ret = request_irq(gpio_to_irq(slot->detect_pin),
2335 atmci_detect_interrupt,
2336 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2337 "mmc-detect", slot);
2339 dev_dbg(&mmc->class_dev,
2340 "could not request IRQ %d for detect pin\n",
2341 gpio_to_irq(slot->detect_pin));
2342 slot->detect_pin = -EBUSY;
2346 atmci_init_debugfs(slot);
2351 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2354 /* Debugfs stuff is cleaned up by mmc core */
2356 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2359 mmc_remove_host(slot->mmc);
2361 if (gpio_is_valid(slot->detect_pin)) {
2362 int pin = slot->detect_pin;
2364 free_irq(gpio_to_irq(pin), slot);
2365 del_timer_sync(&slot->detect_timer);
2368 slot->host->slot[id] = NULL;
2369 mmc_free_host(slot->mmc);
2372 static int atmci_configure_dma(struct atmel_mci *host)
2374 host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2377 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2378 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2379 dma_cap_mask_t mask;
2381 if (!pdata || !pdata->dma_filter)
2385 dma_cap_set(DMA_SLAVE, mask);
2387 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2389 if (!host->dma.chan)
2390 host->dma.chan = ERR_PTR(-ENODEV);
2393 if (IS_ERR(host->dma.chan))
2394 return PTR_ERR(host->dma.chan);
2396 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2397 dma_chan_name(host->dma.chan));
2399 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2400 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2401 host->dma_conf.src_maxburst = 1;
2402 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2403 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2404 host->dma_conf.dst_maxburst = 1;
2405 host->dma_conf.device_fc = false;
2411 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2412 * HSMCI provides DMA support and a new config register but no more supports
2415 static void atmci_get_cap(struct atmel_mci *host)
2417 unsigned int version;
2419 version = atmci_get_version(host);
2420 dev_info(&host->pdev->dev,
2421 "version: 0x%x\n", version);
2423 host->caps.has_dma_conf_reg = 0;
2424 host->caps.has_pdc = 1;
2425 host->caps.has_cfg_reg = 0;
2426 host->caps.has_cstor_reg = 0;
2427 host->caps.has_highspeed = 0;
2428 host->caps.has_rwproof = 0;
2429 host->caps.has_odd_clk_div = 0;
2430 host->caps.has_bad_data_ordering = 1;
2431 host->caps.need_reset_after_xfer = 1;
2432 host->caps.need_blksz_mul_4 = 1;
2433 host->caps.need_notbusy_for_read_ops = 0;
2435 /* keep only major version number */
2436 switch (version & 0xf00) {
2439 host->caps.has_odd_clk_div = 1;
2442 host->caps.has_dma_conf_reg = 1;
2443 host->caps.has_pdc = 0;
2444 host->caps.has_cfg_reg = 1;
2445 host->caps.has_cstor_reg = 1;
2446 host->caps.has_highspeed = 1;
2448 host->caps.has_rwproof = 1;
2449 host->caps.need_blksz_mul_4 = 0;
2450 host->caps.need_notbusy_for_read_ops = 1;
2452 host->caps.has_bad_data_ordering = 0;
2453 host->caps.need_reset_after_xfer = 0;
2457 host->caps.has_pdc = 0;
2458 dev_warn(&host->pdev->dev,
2459 "Unmanaged mci version, set minimum capabilities\n");
2464 static int atmci_probe(struct platform_device *pdev)
2466 struct mci_platform_data *pdata;
2467 struct atmel_mci *host;
2468 struct resource *regs;
2469 unsigned int nr_slots;
2473 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2476 pdata = pdev->dev.platform_data;
2478 pdata = atmci_of_init(pdev);
2479 if (IS_ERR(pdata)) {
2480 dev_err(&pdev->dev, "platform data not available\n");
2481 return PTR_ERR(pdata);
2485 irq = platform_get_irq(pdev, 0);
2489 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2494 spin_lock_init(&host->lock);
2495 INIT_LIST_HEAD(&host->queue);
2497 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2498 if (IS_ERR(host->mck))
2499 return PTR_ERR(host->mck);
2501 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2505 ret = clk_prepare_enable(host->mck);
2509 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2510 host->bus_hz = clk_get_rate(host->mck);
2512 host->mapbase = regs->start;
2514 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2516 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2518 clk_disable_unprepare(host->mck);
2522 /* Get MCI capabilities and set operations according to it */
2523 atmci_get_cap(host);
2524 ret = atmci_configure_dma(host);
2525 if (ret == -EPROBE_DEFER)
2526 goto err_dma_probe_defer;
2528 host->prepare_data = &atmci_prepare_data_dma;
2529 host->submit_data = &atmci_submit_data_dma;
2530 host->stop_transfer = &atmci_stop_transfer_dma;
2531 } else if (host->caps.has_pdc) {
2532 dev_info(&pdev->dev, "using PDC\n");
2533 host->prepare_data = &atmci_prepare_data_pdc;
2534 host->submit_data = &atmci_submit_data_pdc;
2535 host->stop_transfer = &atmci_stop_transfer_pdc;
2537 dev_info(&pdev->dev, "using PIO\n");
2538 host->prepare_data = &atmci_prepare_data;
2539 host->submit_data = &atmci_submit_data;
2540 host->stop_transfer = &atmci_stop_transfer;
2543 platform_set_drvdata(pdev, host);
2545 timer_setup(&host->timer, atmci_timeout_timer, 0);
2547 pm_runtime_get_noresume(&pdev->dev);
2548 pm_runtime_set_active(&pdev->dev);
2549 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2550 pm_runtime_use_autosuspend(&pdev->dev);
2551 pm_runtime_enable(&pdev->dev);
2553 /* We need at least one slot to succeed */
2556 if (pdata->slot[0].bus_width) {
2557 ret = atmci_init_slot(host, &pdata->slot[0],
2558 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2561 host->buf_size = host->slot[0]->mmc->max_req_size;
2564 if (pdata->slot[1].bus_width) {
2565 ret = atmci_init_slot(host, &pdata->slot[1],
2566 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2569 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2571 host->slot[1]->mmc->max_req_size;
2576 dev_err(&pdev->dev, "init failed: no slot defined\n");
2580 if (!host->caps.has_rwproof) {
2581 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2582 &host->buf_phys_addr,
2584 if (!host->buffer) {
2586 dev_err(&pdev->dev, "buffer allocation failed\n");
2591 dev_info(&pdev->dev,
2592 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2593 host->mapbase, irq, nr_slots);
2595 pm_runtime_mark_last_busy(&host->pdev->dev);
2596 pm_runtime_put_autosuspend(&pdev->dev);
2601 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2603 atmci_cleanup_slot(host->slot[i], i);
2606 clk_disable_unprepare(host->mck);
2608 pm_runtime_disable(&pdev->dev);
2609 pm_runtime_put_noidle(&pdev->dev);
2611 del_timer_sync(&host->timer);
2612 if (!IS_ERR(host->dma.chan))
2613 dma_release_channel(host->dma.chan);
2614 err_dma_probe_defer:
2615 free_irq(irq, host);
2619 static int atmci_remove(struct platform_device *pdev)
2621 struct atmel_mci *host = platform_get_drvdata(pdev);
2624 pm_runtime_get_sync(&pdev->dev);
2627 dma_free_coherent(&pdev->dev, host->buf_size,
2628 host->buffer, host->buf_phys_addr);
2630 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2632 atmci_cleanup_slot(host->slot[i], i);
2635 atmci_writel(host, ATMCI_IDR, ~0UL);
2636 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2637 atmci_readl(host, ATMCI_SR);
2639 del_timer_sync(&host->timer);
2640 if (!IS_ERR(host->dma.chan))
2641 dma_release_channel(host->dma.chan);
2643 free_irq(platform_get_irq(pdev, 0), host);
2645 clk_disable_unprepare(host->mck);
2647 pm_runtime_disable(&pdev->dev);
2648 pm_runtime_put_noidle(&pdev->dev);
2654 static int atmci_runtime_suspend(struct device *dev)
2656 struct atmel_mci *host = dev_get_drvdata(dev);
2658 clk_disable_unprepare(host->mck);
2660 pinctrl_pm_select_sleep_state(dev);
2665 static int atmci_runtime_resume(struct device *dev)
2667 struct atmel_mci *host = dev_get_drvdata(dev);
2669 pinctrl_pm_select_default_state(dev);
2671 return clk_prepare_enable(host->mck);
2675 static const struct dev_pm_ops atmci_dev_pm_ops = {
2676 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2677 pm_runtime_force_resume)
2678 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2681 static struct platform_driver atmci_driver = {
2682 .probe = atmci_probe,
2683 .remove = atmci_remove,
2685 .name = "atmel_mci",
2686 .of_match_table = of_match_ptr(atmci_dt_ids),
2687 .pm = &atmci_dev_pm_ops,
2690 module_platform_driver(atmci_driver);
2692 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2693 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2694 MODULE_LICENSE("GPL v2");