drivers/mfd/intel-lpss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel Sunrisepoint LPSS core support.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  *
   7  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   8  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   9  *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
  10  *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/idr.h>
  18 #include <linux/io.h>
  19 #include <linux/ioport.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/mfd/core.h>
  23 #include <linux/pm_qos.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/property.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/io-64-nonatomic-lo-hi.h>
  28
  29 #include <linux/dma/idma64.h>
  30
  31 #include "intel-lpss.h"
  32
  33 #define LPSS_DEV_OFFSET         0x000
  34 #define LPSS_DEV_SIZE           0x200
  35 #define LPSS_PRIV_OFFSET        0x200
  36 #define LPSS_PRIV_SIZE          0x100
  37 #define LPSS_PRIV_REG_COUNT     (LPSS_PRIV_SIZE / 4)
  38 #define LPSS_IDMA64_OFFSET      0x800
  39 #define LPSS_IDMA64_SIZE        0x800
  40
  41 /* Offsets from lpss->priv */
  42 #define LPSS_PRIV_RESETS                0x04
  43 #define LPSS_PRIV_RESETS_IDMA           BIT(2)
  44 #define LPSS_PRIV_RESETS_FUNC           0x3
  45
  46 #define LPSS_PRIV_ACTIVELTR             0x10
  47 #define LPSS_PRIV_IDLELTR               0x14
  48
  49 #define LPSS_PRIV_LTR_REQ               BIT(15)
  50 #define LPSS_PRIV_LTR_SCALE_MASK        0xc00
  51 #define LPSS_PRIV_LTR_SCALE_1US         0x800
  52 #define LPSS_PRIV_LTR_SCALE_32US        0xc00
  53 #define LPSS_PRIV_LTR_VALUE_MASK        0x3ff
  54
  55 #define LPSS_PRIV_SSP_REG               0x20
  56 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN   BIT(0)
  57
  58 #define LPSS_PRIV_REMAP_ADDR            0x40
  59
  60 #define LPSS_PRIV_CAPS                  0xfc
  61 #define LPSS_PRIV_CAPS_NO_IDMA          BIT(8)
  62 #define LPSS_PRIV_CAPS_TYPE_SHIFT       4
  63 #define LPSS_PRIV_CAPS_TYPE_MASK        (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
  64
  65 /* This matches the type field in CAPS register */
  66 enum intel_lpss_dev_type {
  67         LPSS_DEV_I2C = 0,
  68         LPSS_DEV_UART,
  69         LPSS_DEV_SPI,
  70 };
  71
  72 struct intel_lpss {
  73         const struct intel_lpss_platform_info *info;
  74         enum intel_lpss_dev_type type;
  75         struct clk *clk;
  76         struct clk_lookup *clock;
  77         struct mfd_cell *cell;
  78         struct device *dev;
  79         void __iomem *priv;
  80         u32 priv_ctx[LPSS_PRIV_REG_COUNT];
  81         int devid;
  82         u32 caps;
  83         u32 active_ltr;
  84         u32 idle_ltr;
  85         struct dentry *debugfs;
  86 };
  87
  88 static const struct resource intel_lpss_dev_resources[] = {
  89         DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
  90         DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
  91         DEFINE_RES_IRQ(0),
  92 };
  93
  94 static const struct resource intel_lpss_idma64_resources[] = {
  95         DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
  96         DEFINE_RES_IRQ(0),
  97 };
  98
  99 /*
 100  * Cells needs to be ordered so that the iDMA is created first. This is
 101  * because we need to be sure the DMA is available when the host controller
 102  * driver is probed.
 103  */
 104 static const struct mfd_cell intel_lpss_idma64_cell = {
 105         .name = LPSS_IDMA64_DRIVER_NAME,
 106         .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
 107         .resources = intel_lpss_idma64_resources,
 108 };
 109
 110 static const struct mfd_cell intel_lpss_i2c_cell = {
 111         .name = "i2c_designware",
 112         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 113         .resources = intel_lpss_dev_resources,
 114 };
 115
 116 static const struct mfd_cell intel_lpss_uart_cell = {
 117         .name = "dw-apb-uart",
 118         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 119         .resources = intel_lpss_dev_resources,
 120 };
 121
 122 static const struct mfd_cell intel_lpss_spi_cell = {
 123         .name = "pxa2xx-spi",
 124         .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
 125         .resources = intel_lpss_dev_resources,
 126 };
 127
 128 static DEFINE_IDA(intel_lpss_devid_ida);
 129 static struct dentry *intel_lpss_debugfs;
 130
 131 static int intel_lpss_request_dma_module(const char *name)
 132 {
 133         static bool intel_lpss_dma_requested;
 134
 135         if (intel_lpss_dma_requested)
 136                 return 0;
 137
 138         intel_lpss_dma_requested = true;
 139         return request_module("%s", name);
 140 }
 141
 142 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
 143 {
 144         lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 145         lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
 146 }
 147
 148 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
 149 {
 150         struct dentry *dir;
 151
 152         dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
 153         if (IS_ERR(dir))
 154                 return PTR_ERR(dir);
 155
 156         /* Cache the values into lpss structure */
 157         intel_lpss_cache_ltr(lpss);
 158
 159         debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
 160         debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
 161         debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
 162
 163         lpss->debugfs = dir;
 164         return 0;
 165 }
 166
 167 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
 168 {
 169         debugfs_remove_recursive(lpss->debugfs);
 170 }
 171
 172 static void intel_lpss_ltr_set(struct device *dev, s32 val)
 173 {
 174         struct intel_lpss *lpss = dev_get_drvdata(dev);
 175         u32 ltr;
 176
 177         /*
 178          * Program latency tolerance (LTR) accordingly what has been asked
 179          * by the PM QoS layer or disable it in case we were passed
 180          * negative value or PM_QOS_LATENCY_ANY.
 181          */
 182         ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
 183
 184         if (val == PM_QOS_LATENCY_ANY || val < 0) {
 185                 ltr &= ~LPSS_PRIV_LTR_REQ;
 186         } else {
 187                 ltr |= LPSS_PRIV_LTR_REQ;
 188                 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
 189                 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
 190
 191                 if (val > LPSS_PRIV_LTR_VALUE_MASK)
 192                         ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
 193                 else
 194                         ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
 195         }
 196
 197         if (ltr == lpss->active_ltr)
 198                 return;
 199
 200         writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
 201         writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
 202
 203         /* Cache the values into lpss structure */
 204         intel_lpss_cache_ltr(lpss);
 205 }
 206
 207 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
 208 {
 209         lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
 210         dev_pm_qos_expose_latency_tolerance(lpss->dev);
 211 }
 212
 213 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
 214 {
 215         dev_pm_qos_hide_latency_tolerance(lpss->dev);
 216         lpss->dev->power.set_latency_tolerance = NULL;
 217 }
 218
 219 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
 220 {
 221         const struct mfd_cell *cell;
 222         unsigned int type;
 223
 224         type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
 225         type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
 226
 227         switch (type) {
 228         case LPSS_DEV_I2C:
 229                 cell = &intel_lpss_i2c_cell;
 230                 break;
 231         case LPSS_DEV_UART:
 232                 cell = &intel_lpss_uart_cell;
 233                 break;
 234         case LPSS_DEV_SPI:
 235                 cell = &intel_lpss_spi_cell;
 236                 break;
 237         default:
 238                 return -ENODEV;
 239         }
 240
 241         lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
 242         if (!lpss->cell)
 243                 return -ENOMEM;
 244
 245         lpss->type = type;
 246
 247         return 0;
 248 }
 249
 250 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
 251 {
 252         return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
 253 }
 254
 255 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
 256 {
 257         resource_size_t addr = lpss->info->mem->start;
 258
 259         lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
 260 }
 261
 262 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
 263 {
 264         u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
 265
 266         /* Bring out the device from reset */
 267         writel(value, lpss->priv + LPSS_PRIV_RESETS);
 268 }
 269
 270 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
 271 {
 272         u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
 273
 274         /* Set the device in reset state */
 275         writel(0, lpss->priv + LPSS_PRIV_RESETS);
 276
 277         intel_lpss_deassert_reset(lpss);
 278
 279         intel_lpss_set_remap_addr(lpss);
 280
 281         if (!intel_lpss_has_idma(lpss))
 282                 return;
 283
 284         /* Make sure that SPI multiblock DMA transfers are re-enabled */
 285         if (lpss->type == LPSS_DEV_SPI)
 286                 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
 287 }
 288
 289 static void intel_lpss_unregister_clock_tree(struct clk *clk)
 290 {
 291         struct clk *parent;
 292
 293         while (clk) {
 294                 parent = clk_get_parent(clk);
 295                 clk_unregister(clk);
 296                 clk = parent;
 297         }
 298 }
 299
 300 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
 301                                              const char *devname,
 302                                              struct clk **clk)
 303 {
 304         char name[32];
 305         struct clk *tmp = *clk;
 306
 307         snprintf(name, sizeof(name), "%s-enable", devname);
 308         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
 309                                 lpss->priv, 0, 0, NULL);
 310         if (IS_ERR(tmp))
 311                 return PTR_ERR(tmp);
 312
 313         snprintf(name, sizeof(name), "%s-div", devname);
 314         tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
 315                                               0, lpss->priv, 1, 15, 16, 15, 0,
 316                                               NULL);
 317         if (IS_ERR(tmp))
 318                 return PTR_ERR(tmp);
 319         *clk = tmp;
 320
 321         snprintf(name, sizeof(name), "%s-update", devname);
 322         tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
 323                                 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
 324         if (IS_ERR(tmp))
 325                 return PTR_ERR(tmp);
 326         *clk = tmp;
 327
 328         return 0;
 329 }
 330
 331 static int intel_lpss_register_clock(struct intel_lpss *lpss)
 332 {
 333         const struct mfd_cell *cell = lpss->cell;
 334         struct clk *clk;
 335         char devname[24];
 336         int ret;
 337
 338         if (!lpss->info->clk_rate)
 339                 return 0;
 340
 341         /* Root clock */
 342         clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
 343                                       lpss->info->clk_rate);
 344         if (IS_ERR(clk))
 345                 return PTR_ERR(clk);
 346
 347         snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
 348
 349         /*
 350          * Support for clock divider only if it has some preset value.
 351          * Otherwise we assume that the divider is not used.
 352          */
 353         if (lpss->type != LPSS_DEV_I2C) {
 354                 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
 355                 if (ret)
 356                         goto err_clk_register;
 357         }
 358
 359         ret = -ENOMEM;
 360
 361         /* Clock for the host controller */
 362         lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
 363         if (!lpss->clock)
 364                 goto err_clk_register;
 365
 366         lpss->clk = clk;
 367
 368         return 0;
 369
 370 err_clk_register:
 371         intel_lpss_unregister_clock_tree(clk);
 372
 373         return ret;
 374 }
 375
 376 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
 377 {
 378         if (IS_ERR_OR_NULL(lpss->clk))
 379                 return;
 380
 381         clkdev_drop(lpss->clock);
 382         intel_lpss_unregister_clock_tree(lpss->clk);
 383 }
 384
 385 int intel_lpss_probe(struct device *dev,
 386                      const struct intel_lpss_platform_info *info)
 387 {
 388         struct intel_lpss *lpss;
 389         int ret;
 390
 391         if (!info || !info->mem || info->irq <= 0)
 392                 return -EINVAL;
 393
 394         lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
 395         if (!lpss)
 396                 return -ENOMEM;
 397
 398         lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
 399                                   LPSS_PRIV_SIZE);
 400         if (!lpss->priv)
 401                 return -ENOMEM;
 402
 403         lpss->info = info;
 404         lpss->dev = dev;
 405         lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
 406
 407         dev_set_drvdata(dev, lpss);
 408
 409         ret = intel_lpss_assign_devs(lpss);
 410         if (ret)
 411                 return ret;
 412
 413         lpss->cell->properties = info->properties;
 414
 415         intel_lpss_init_dev(lpss);
 416
 417         lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
 418         if (lpss->devid < 0)
 419                 return lpss->devid;
 420
 421         ret = intel_lpss_register_clock(lpss);
 422         if (ret)
 423                 goto err_clk_register;
 424
 425         intel_lpss_ltr_expose(lpss);
 426
 427         ret = intel_lpss_debugfs_add(lpss);
 428         if (ret)
 429                 dev_warn(dev, "Failed to create debugfs entries\n");
 430
 431         if (intel_lpss_has_idma(lpss)) {
 432                 /*
 433                  * Ensure the DMA driver is loaded before the host
 434                  * controller device appears, so that the host controller
 435                  * driver can request its DMA channels as early as
 436                  * possible.
 437                  *
 438                  * If the DMA module is not there that's OK as well.
 439                  */
 440                 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
 441
 442                 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
 443                                       1, info->mem, info->irq, NULL);
 444                 if (ret)
 445                         dev_warn(dev, "Failed to add %s, fallback to PIO\n",
 446                                  LPSS_IDMA64_DRIVER_NAME);
 447         }
 448
 449         ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
 450                               1, info->mem, info->irq, NULL);
 451         if (ret)
 452                 goto err_remove_ltr;
 453
 454         dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
 455
 456         return 0;
 457
 458 err_remove_ltr:
 459         intel_lpss_debugfs_remove(lpss);
 460         intel_lpss_ltr_hide(lpss);
 461         intel_lpss_unregister_clock(lpss);
 462
 463 err_clk_register:
 464         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 465
 466         return ret;
 467 }
 468 EXPORT_SYMBOL_GPL(intel_lpss_probe);
 469
 470 void intel_lpss_remove(struct device *dev)
 471 {
 472         struct intel_lpss *lpss = dev_get_drvdata(dev);
 473
 474         mfd_remove_devices(dev);
 475         intel_lpss_debugfs_remove(lpss);
 476         intel_lpss_ltr_hide(lpss);
 477         intel_lpss_unregister_clock(lpss);
 478         ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
 479 }
 480 EXPORT_SYMBOL_GPL(intel_lpss_remove);
 481
 482 static int resume_lpss_device(struct device *dev, void *data)
 483 {
 484         if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
 485                 pm_runtime_resume(dev);
 486
 487         return 0;
 488 }
 489
 490 int intel_lpss_prepare(struct device *dev)
 491 {
 492         /*
 493          * Resume both child devices before entering system sleep. This
 494          * ensures that they are in proper state before they get suspended.
 495          */
 496         device_for_each_child_reverse(dev, NULL, resume_lpss_device);
 497         return 0;
 498 }
 499 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
 500
 501 int intel_lpss_suspend(struct device *dev)
 502 {
 503         struct intel_lpss *lpss = dev_get_drvdata(dev);
 504         unsigned int i;
 505
 506         /* Save device context */
 507         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
 508                 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
 509
 510         /*
 511          * If the device type is not UART, then put the controller into
 512          * reset. UART cannot be put into reset since S3/S0ix fail when
 513          * no_console_suspend flag is enabled.
 514          */
 515         if (lpss->type != LPSS_DEV_UART)
 516                 writel(0, lpss->priv + LPSS_PRIV_RESETS);
 517
 518         return 0;
 519 }
 520 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
 521
 522 int intel_lpss_resume(struct device *dev)
 523 {
 524         struct intel_lpss *lpss = dev_get_drvdata(dev);
 525         unsigned int i;
 526
 527         intel_lpss_deassert_reset(lpss);
 528
 529         /* Restore device context */
 530         for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
 531                 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
 532
 533         return 0;
 534 }
 535 EXPORT_SYMBOL_GPL(intel_lpss_resume);
 536
 537 static int __init intel_lpss_init(void)
 538 {
 539         intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
 540         return 0;
 541 }
 542 module_init(intel_lpss_init);
 543
 544 static void __exit intel_lpss_exit(void)
 545 {
 546         debugfs_remove(intel_lpss_debugfs);
 547 }
 548 module_exit(intel_lpss_exit);
 549
 550 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 551 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 552 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
 553 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
 554 MODULE_DESCRIPTION("Intel LPSS core driver");
 555 MODULE_LICENSE("GPL v2");