6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #ifndef OMAP3_ISP_CORE_H
18 #define OMAP3_ISP_CORE_H
20 #include <media/omap3isp.h>
21 #include <media/v4l2-device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/device.h>
25 #include <linux/iommu.h>
26 #include <linux/platform_device.h>
27 #include <linux/wait.h>
32 #include "ispresizer.h"
33 #include "isppreview.h"
34 #include "ispcsiphy.h"
38 #define ISP_TOK_TERM 0xFFFFFFFF /*
39 * terminating token for ISP
42 #define to_isp_device(ptr_module) \
43 container_of(ptr_module, struct isp_device, isp_##ptr_module)
44 #define to_device(ptr_module) \
45 (to_isp_device(ptr_module)->dev)
47 enum isp_mem_resources {
56 OMAP3_ISP_IOMEM_CSI2A_REGS1,
57 OMAP3_ISP_IOMEM_CSIPHY2,
58 OMAP3_ISP_IOMEM_CSI2A_REGS2,
59 OMAP3_ISP_IOMEM_CSI2C_REGS1,
60 OMAP3_ISP_IOMEM_CSIPHY1,
61 OMAP3_ISP_IOMEM_CSI2C_REGS2,
65 enum isp_sbl_resource {
66 OMAP3_ISP_SBL_CSI1_READ = 0x1,
67 OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
68 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
69 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
70 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
71 OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
72 OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
73 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
74 OMAP3_ISP_SBL_RESIZER_READ = 0x100,
75 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
78 enum isp_subclk_resource {
79 OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
80 OMAP3_ISP_SUBCLK_AEWB = (1 << 1),
81 OMAP3_ISP_SUBCLK_AF = (1 << 2),
82 OMAP3_ISP_SUBCLK_HIST = (1 << 3),
83 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4),
84 OMAP3_ISP_SUBCLK_RESIZER = (1 << 5),
87 /* ISP: OMAP 34xx ES 1.0 */
88 #define ISP_REVISION_1_0 0x10
89 /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
90 #define ISP_REVISION_2_0 0x20
91 /* ISP2P: OMAP 36xx */
92 #define ISP_REVISION_15_0 0xF0
94 #define ISP_PHY_TYPE_3430 0
95 #define ISP_PHY_TYPE_3630 1
100 * struct isp_res_mapping - Map ISP io resources to ISP revision.
101 * @isp_rev: ISP_REVISION_x_x
102 * @map: bitmap for enum isp_mem_resources
103 * @syscon_offset: offset of the syscon register for 343x / 3630
104 * (CONTROL_CSIRXFE / CONTROL_CAMERA_PHY_CTRL, respectively)
105 * from the syscon base address
106 * @phy_type: ISP_PHY_TYPE_{3430,3630}
108 struct isp_res_mapping {
116 * struct isp_reg - Structure for ISP register values.
117 * @reg: 32-bit Register address.
118 * @val: 32-bit Register value.
121 enum isp_mem_resources mmio_range;
132 struct isp_device *isp;
134 struct clk_lookup *lookup;
138 spinlock_t lock; /* Protects enabled and divider */
140 unsigned int divider;
144 * struct isp_device - ISP device structure.
145 * @dev: Device pointer specific to the OMAP3 ISP.
146 * @revision: Stores current ISP module revision.
147 * @irq_num: Currently used IRQ number.
148 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
150 * @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register
152 * @syscon: Regmap for the syscon register space
153 * @syscon_offset: Offset of the CSIPHY control register in syscon
154 * @phy_type: ISP_PHY_TYPE_{3430,3630}
155 * @mapping: IOMMU mapping
156 * @stat_lock: Spinlock for handling statistics
157 * @isp_mutex: Mutex for serializing requests to ISP.
158 * @stop_failure: Indicates that an entity failed to stop.
159 * @crashed: Bitmask of crashed entities (indexed by entity ID)
160 * @has_context: Context has been saved at least once and can be restored.
161 * @ref_count: Reference count for handling multiple ISP requests.
162 * @cam_ick: Pointer to camera interface clock structure.
163 * @cam_mclk: Pointer to camera functional clock structure.
164 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
165 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
166 * @xclks: External clocks provided by the ISP
167 * @irq: Currently attached ISP ISR callbacks information structure.
168 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
169 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
170 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
172 * @isp_res: Pointer to current settings for ISP Resizer.
173 * @isp_prev: Pointer to current settings for ISP Preview.
174 * @isp_ccdc: Pointer to current settings for ISP CCDC.
175 * @platform_cb: ISP driver callback function pointers for platform code
177 * This structure is used to store the OMAP ISP Information.
180 struct v4l2_device v4l2_dev;
181 struct media_device media_dev;
185 /* platform HW resources */
186 struct isp_platform_data *pdata;
187 unsigned int irq_num;
189 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
190 unsigned long mmio_hist_base_phys;
191 struct regmap *syscon;
195 struct dma_iommu_mapping *mapping;
198 spinlock_t stat_lock; /* common lock for statistic drivers */
199 struct mutex isp_mutex; /* For handling ref_count field */
204 unsigned int autoidle;
205 #define ISP_CLK_CAM_ICK 0
206 #define ISP_CLK_CAM_MCLK 1
207 #define ISP_CLK_CSI2_FCK 2
208 #define ISP_CLK_L3_ICK 3
209 struct clk *clock[4];
210 struct isp_xclk xclks[2];
213 struct ispstat isp_af;
214 struct ispstat isp_aewb;
215 struct ispstat isp_hist;
216 struct isp_res_device isp_res;
217 struct isp_prev_device isp_prev;
218 struct isp_ccdc_device isp_ccdc;
219 struct isp_csi2_device isp_csi2a;
220 struct isp_csi2_device isp_csi2c;
221 struct isp_ccp2_device isp_ccp2;
222 struct isp_csiphy isp_csiphy1;
223 struct isp_csiphy isp_csiphy2;
225 unsigned int sbl_resources;
226 unsigned int subclk_resources;
229 #define v4l2_dev_to_isp_device(dev) \
230 container_of(dev, struct isp_device, v4l2_dev)
232 void omap3isp_hist_dma_done(struct isp_device *isp);
234 void omap3isp_flush(struct isp_device *isp);
236 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
239 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
242 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
243 enum isp_pipeline_stream_state state);
244 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
245 void omap3isp_configure_bridge(struct isp_device *isp,
246 enum ccdc_input_entity input,
247 const struct isp_parallel_cfg *buscfg,
248 unsigned int shift, unsigned int bridge);
250 struct isp_device *omap3isp_get(struct isp_device *isp);
251 void omap3isp_put(struct isp_device *isp);
253 void omap3isp_print_status(struct isp_device *isp);
255 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
256 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
258 void omap3isp_subclk_enable(struct isp_device *isp,
259 enum isp_subclk_resource res);
260 void omap3isp_subclk_disable(struct isp_device *isp,
261 enum isp_subclk_resource res);
263 int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
265 int omap3isp_register_entities(struct platform_device *pdev,
266 struct v4l2_device *v4l2_dev);
267 void omap3isp_unregister_entities(struct platform_device *pdev);
270 * isp_reg_readl - Read value of an OMAP3 ISP register
271 * @isp: Device pointer specific to the OMAP3 ISP.
272 * @isp_mmio_range: Range to which the register offset refers to.
273 * @reg_offset: Register offset to read from.
275 * Returns an unsigned 32 bit value with the required register contents.
278 u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
281 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
285 * isp_reg_writel - Write value to an OMAP3 ISP register
286 * @isp: Device pointer specific to the OMAP3 ISP.
287 * @reg_value: 32 bit value to write to the register.
288 * @isp_mmio_range: Range to which the register offset refers to.
289 * @reg_offset: Register offset to write into.
292 void isp_reg_writel(struct isp_device *isp, u32 reg_value,
293 enum isp_mem_resources isp_mmio_range, u32 reg_offset)
295 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
299 * isp_reg_clr - Clear individual bits in an OMAP3 ISP register
300 * @isp: Device pointer specific to the OMAP3 ISP.
301 * @mmio_range: Range to which the register offset refers to.
302 * @reg: Register offset to work on.
303 * @clr_bits: 32 bit value which would be cleared in the register.
306 void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
307 u32 reg, u32 clr_bits)
309 u32 v = isp_reg_readl(isp, mmio_range, reg);
311 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
315 * isp_reg_set - Set individual bits in an OMAP3 ISP register
316 * @isp: Device pointer specific to the OMAP3 ISP.
317 * @mmio_range: Range to which the register offset refers to.
318 * @reg: Register offset to work on.
319 * @set_bits: 32 bit value which would be set in the register.
322 void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
323 u32 reg, u32 set_bits)
325 u32 v = isp_reg_readl(isp, mmio_range, reg);
327 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
331 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
332 * @isp: Device pointer specific to the OMAP3 ISP.
333 * @mmio_range: Range to which the register offset refers to.
334 * @reg: Register offset to work on.
335 * @clr_bits: 32 bit value which would be cleared in the register.
336 * @set_bits: 32 bit value which would be set in the register.
338 * The clear operation is done first, and then the set operation.
341 void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
342 u32 reg, u32 clr_bits, u32 set_bits)
344 u32 v = isp_reg_readl(isp, mmio_range, reg);
346 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
349 static inline enum v4l2_buf_type
350 isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
352 if (pad >= subdev->entity.num_pads)
355 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
356 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
358 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
361 #endif /* OMAP3_ISP_CORE_H */