drivers/irqchip/irq-gic-v3-its.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/acpi_iort.h>
   9 #include <linux/bitmap.h>
  10 #include <linux/cpu.h>
  11 #include <linux/crash_dump.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-iommu.h>
  14 #include <linux/efi.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/list.h>
  18 #include <linux/log2.h>
  19 #include <linux/memblock.h>
  20 #include <linux/mm.h>
  21 #include <linux/msi.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_pci.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/percpu.h>
  28 #include <linux/slab.h>
  29 #include <linux/syscore_ops.h>
  30
  31 #include <linux/irqchip.h>
  32 #include <linux/irqchip/arm-gic-v3.h>
  33 #include <linux/irqchip/arm-gic-v4.h>
  34
  35 #include <asm/cputype.h>
  36 #include <asm/exception.h>
  37
  38 #include "irq-gic-common.h"
  39
  40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  41 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  42 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
  43 #define ITS_FLAGS_SAVE_SUSPEND_STATE            (1ULL << 3)
  44
  45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  46 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED      (1 << 1)
  47
  48 static u32 lpi_id_bits;
  49
  50 /*
  51  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
  52  * deal with (one configuration byte per interrupt). PENDBASE has to
  53  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  54  */
  55 #define LPI_NRBITS              lpi_id_bits
  56 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
  57 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  58
  59 #define LPI_PROP_DEFAULT_PRIO   GICD_INT_DEF_PRI
  60
  61 /*
  62  * Collection structure - just an ID, and a redistributor address to
  63  * ping. We use one per CPU as a bag of interrupts assigned to this
  64  * CPU.
  65  */
  66 struct its_collection {
  67         u64                     target_address;
  68         u16                     col_id;
  69 };
  70
  71 /*
  72  * The ITS_BASER structure - contains memory information, cached
  73  * value of BASER register configuration and ITS page size.
  74  */
  75 struct its_baser {
  76         void            *base;
  77         u64             val;
  78         u32             order;
  79         u32             psz;
  80 };
  81
  82 struct its_device;
  83
  84 /*
  85  * The ITS structure - contains most of the infrastructure, with the
  86  * top-level MSI domain, the command queue, the collections, and the
  87  * list of devices writing to it.
  88  *
  89  * dev_alloc_lock has to be taken for device allocations, while the
  90  * spinlock must be taken to parse data structures such as the device
  91  * list.
  92  */
  93 struct its_node {
  94         raw_spinlock_t          lock;
  95         struct mutex            dev_alloc_lock;
  96         struct list_head        entry;
  97         void __iomem            *base;
  98         phys_addr_t             phys_base;
  99         struct its_cmd_block    *cmd_base;
 100         struct its_cmd_block    *cmd_write;
 101         struct its_baser        tables[GITS_BASER_NR_REGS];
 102         struct its_collection   *collections;
 103         struct fwnode_handle    *fwnode_handle;
 104         u64                     (*get_msi_base)(struct its_device *its_dev);
 105         u64                     cbaser_save;
 106         u32                     ctlr_save;
 107         struct list_head        its_device_list;
 108         u64                     flags;
 109         unsigned long           list_nr;
 110         u32                     ite_size;
 111         u32                     device_ids;
 112         int                     numa_node;
 113         unsigned int            msi_domain_flags;
 114         u32                     pre_its_base; /* for Socionext Synquacer */
 115         bool                    is_v4;
 116         int                     vlpi_redist_offset;
 117 };
 118
 119 #define ITS_ITT_ALIGN           SZ_256
 120
 121 /* The maximum number of VPEID bits supported by VLPI commands */
 122 #define ITS_MAX_VPEID_BITS      (16)
 123 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
 124
 125 /* Convert page order to size in bytes */
 126 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
 127
 128 struct event_lpi_map {
 129         unsigned long           *lpi_map;
 130         u16                     *col_map;
 131         irq_hw_number_t         lpi_base;
 132         int                     nr_lpis;
 133         struct mutex            vlpi_lock;
 134         struct its_vm           *vm;
 135         struct its_vlpi_map     *vlpi_maps;
 136         int                     nr_vlpis;
 137 };
 138
 139 /*
 140  * The ITS view of a device - belongs to an ITS, owns an interrupt
 141  * translation table, and a list of interrupts.  If it some of its
 142  * LPIs are injected into a guest (GICv4), the event_map.vm field
 143  * indicates which one.
 144  */
 145 struct its_device {
 146         struct list_head        entry;
 147         struct its_node         *its;
 148         struct event_lpi_map    event_map;
 149         void                    *itt;
 150         u32                     nr_ites;
 151         u32                     device_id;
 152         bool                    shared;
 153 };
 154
 155 static struct {
 156         raw_spinlock_t          lock;
 157         struct its_device       *dev;
 158         struct its_vpe          **vpes;
 159         int                     next_victim;
 160 } vpe_proxy;
 161
 162 static LIST_HEAD(its_nodes);
 163 static DEFINE_RAW_SPINLOCK(its_lock);
 164 static struct rdists *gic_rdists;
 165 static struct irq_domain *its_parent;
 166
 167 static unsigned long its_list_map;
 168 static u16 vmovp_seq_num;
 169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
 170
 171 static DEFINE_IDA(its_vpeid_ida);
 172
 173 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 174 #define gic_data_rdist_cpu(cpu)         (per_cpu_ptr(gic_rdists->rdist, cpu))
 175 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 176 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
 177
 178 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 179                                                u32 event)
 180 {
 181         struct its_node *its = its_dev->its;
 182
 183         return its->collections + its_dev->event_map.col_map[event];
 184 }
 185
 186 static struct its_collection *valid_col(struct its_collection *col)
 187 {
 188         if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
 189                 return NULL;
 190
 191         return col;
 192 }
 193
 194 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
 195 {
 196         if (valid_col(its->collections + vpe->col_idx))
 197                 return vpe;
 198
 199         return NULL;
 200 }
 201
 202 /*
 203  * ITS command descriptors - parameters to be encoded in a command
 204  * block.
 205  */
 206 struct its_cmd_desc {
 207         union {
 208                 struct {
 209                         struct its_device *dev;
 210                         u32 event_id;
 211                 } its_inv_cmd;
 212
 213                 struct {
 214                         struct its_device *dev;
 215                         u32 event_id;
 216                 } its_clear_cmd;
 217
 218                 struct {
 219                         struct its_device *dev;
 220                         u32 event_id;
 221                 } its_int_cmd;
 222
 223                 struct {
 224                         struct its_device *dev;
 225                         int valid;
 226                 } its_mapd_cmd;
 227
 228                 struct {
 229                         struct its_collection *col;
 230                         int valid;
 231                 } its_mapc_cmd;
 232
 233                 struct {
 234                         struct its_device *dev;
 235                         u32 phys_id;
 236                         u32 event_id;
 237                 } its_mapti_cmd;
 238
 239                 struct {
 240                         struct its_device *dev;
 241                         struct its_collection *col;
 242                         u32 event_id;
 243                 } its_movi_cmd;
 244
 245                 struct {
 246                         struct its_device *dev;
 247                         u32 event_id;
 248                 } its_discard_cmd;
 249
 250                 struct {
 251                         struct its_collection *col;
 252                 } its_invall_cmd;
 253
 254                 struct {
 255                         struct its_vpe *vpe;
 256                 } its_vinvall_cmd;
 257
 258                 struct {
 259                         struct its_vpe *vpe;
 260                         struct its_collection *col;
 261                         bool valid;
 262                 } its_vmapp_cmd;
 263
 264                 struct {
 265                         struct its_vpe *vpe;
 266                         struct its_device *dev;
 267                         u32 virt_id;
 268                         u32 event_id;
 269                         bool db_enabled;
 270                 } its_vmapti_cmd;
 271
 272                 struct {
 273                         struct its_vpe *vpe;
 274                         struct its_device *dev;
 275                         u32 event_id;
 276                         bool db_enabled;
 277                 } its_vmovi_cmd;
 278
 279                 struct {
 280                         struct its_vpe *vpe;
 281                         struct its_collection *col;
 282                         u16 seq_num;
 283                         u16 its_list;
 284                 } its_vmovp_cmd;
 285         };
 286 };
 287
 288 /*
 289  * The ITS command block, which is what the ITS actually parses.
 290  */
 291 struct its_cmd_block {
 292         u64     raw_cmd[4];
 293 };
 294
 295 #define ITS_CMD_QUEUE_SZ                SZ_64K
 296 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 297
 298 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
 299                                                     struct its_cmd_block *,
 300                                                     struct its_cmd_desc *);
 301
 302 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
 303                                               struct its_cmd_block *,
 304                                               struct its_cmd_desc *);
 305
 306 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
 307 {
 308         u64 mask = GENMASK_ULL(h, l);
 309         *raw_cmd &= ~mask;
 310         *raw_cmd |= (val << l) & mask;
 311 }
 312
 313 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 314 {
 315         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
 316 }
 317
 318 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 319 {
 320         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
 321 }
 322
 323 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 324 {
 325         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
 326 }
 327
 328 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 329 {
 330         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
 331 }
 332
 333 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 334 {
 335         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
 336 }
 337
 338 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 339 {
 340         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
 341 }
 342
 343 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 344 {
 345         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
 346 }
 347
 348 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 349 {
 350         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
 351 }
 352
 353 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 354 {
 355         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
 356 }
 357
 358 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
 359 {
 360         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
 361 }
 362
 363 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
 364 {
 365         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
 366 }
 367
 368 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
 369 {
 370         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
 371 }
 372
 373 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
 374 {
 375         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
 376 }
 377
 378 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
 379 {
 380         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
 381 }
 382
 383 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
 384 {
 385         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
 386 }
 387
 388 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
 389 {
 390         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
 391 }
 392
 393 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
 394 {
 395         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
 396 }
 397
 398 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 399 {
 400         /* Let's fixup BE commands */
 401         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 402         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 403         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 404         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 405 }
 406
 407 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
 408                                                  struct its_cmd_block *cmd,
 409                                                  struct its_cmd_desc *desc)
 410 {
 411         unsigned long itt_addr;
 412         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 413
 414         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 415         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 416
 417         its_encode_cmd(cmd, GITS_CMD_MAPD);
 418         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 419         its_encode_size(cmd, size - 1);
 420         its_encode_itt(cmd, itt_addr);
 421         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 422
 423         its_fixup_cmd(cmd);
 424
 425         return NULL;
 426 }
 427
 428 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
 429                                                  struct its_cmd_block *cmd,
 430                                                  struct its_cmd_desc *desc)
 431 {
 432         its_encode_cmd(cmd, GITS_CMD_MAPC);
 433         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 434         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 435         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 436
 437         its_fixup_cmd(cmd);
 438
 439         return desc->its_mapc_cmd.col;
 440 }
 441
 442 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
 443                                                   struct its_cmd_block *cmd,
 444                                                   struct its_cmd_desc *desc)
 445 {
 446         struct its_collection *col;
 447
 448         col = dev_event_to_col(desc->its_mapti_cmd.dev,
 449                                desc->its_mapti_cmd.event_id);
 450
 451         its_encode_cmd(cmd, GITS_CMD_MAPTI);
 452         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
 453         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
 454         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
 455         its_encode_collection(cmd, col->col_id);
 456
 457         its_fixup_cmd(cmd);
 458
 459         return valid_col(col);
 460 }
 461
 462 static struct its_collection *its_build_movi_cmd(struct its_node *its,
 463                                                  struct its_cmd_block *cmd,
 464                                                  struct its_cmd_desc *desc)
 465 {
 466         struct its_collection *col;
 467
 468         col = dev_event_to_col(desc->its_movi_cmd.dev,
 469                                desc->its_movi_cmd.event_id);
 470
 471         its_encode_cmd(cmd, GITS_CMD_MOVI);
 472         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 473         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 474         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 475
 476         its_fixup_cmd(cmd);
 477
 478         return valid_col(col);
 479 }
 480
 481 static struct its_collection *its_build_discard_cmd(struct its_node *its,
 482                                                     struct its_cmd_block *cmd,
 483                                                     struct its_cmd_desc *desc)
 484 {
 485         struct its_collection *col;
 486
 487         col = dev_event_to_col(desc->its_discard_cmd.dev,
 488                                desc->its_discard_cmd.event_id);
 489
 490         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 491         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 492         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 493
 494         its_fixup_cmd(cmd);
 495
 496         return valid_col(col);
 497 }
 498
 499 static struct its_collection *its_build_inv_cmd(struct its_node *its,
 500                                                 struct its_cmd_block *cmd,
 501                                                 struct its_cmd_desc *desc)
 502 {
 503         struct its_collection *col;
 504
 505         col = dev_event_to_col(desc->its_inv_cmd.dev,
 506                                desc->its_inv_cmd.event_id);
 507
 508         its_encode_cmd(cmd, GITS_CMD_INV);
 509         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 510         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 511
 512         its_fixup_cmd(cmd);
 513
 514         return valid_col(col);
 515 }
 516
 517 static struct its_collection *its_build_int_cmd(struct its_node *its,
 518                                                 struct its_cmd_block *cmd,
 519                                                 struct its_cmd_desc *desc)
 520 {
 521         struct its_collection *col;
 522
 523         col = dev_event_to_col(desc->its_int_cmd.dev,
 524                                desc->its_int_cmd.event_id);
 525
 526         its_encode_cmd(cmd, GITS_CMD_INT);
 527         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 528         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 529
 530         its_fixup_cmd(cmd);
 531
 532         return valid_col(col);
 533 }
 534
 535 static struct its_collection *its_build_clear_cmd(struct its_node *its,
 536                                                   struct its_cmd_block *cmd,
 537                                                   struct its_cmd_desc *desc)
 538 {
 539         struct its_collection *col;
 540
 541         col = dev_event_to_col(desc->its_clear_cmd.dev,
 542                                desc->its_clear_cmd.event_id);
 543
 544         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 545         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 546         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 547
 548         its_fixup_cmd(cmd);
 549
 550         return valid_col(col);
 551 }
 552
 553 static struct its_collection *its_build_invall_cmd(struct its_node *its,
 554                                                    struct its_cmd_block *cmd,
 555                                                    struct its_cmd_desc *desc)
 556 {
 557         its_encode_cmd(cmd, GITS_CMD_INVALL);
 558         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 559
 560         its_fixup_cmd(cmd);
 561
 562         return NULL;
 563 }
 564
 565 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
 566                                              struct its_cmd_block *cmd,
 567                                              struct its_cmd_desc *desc)
 568 {
 569         its_encode_cmd(cmd, GITS_CMD_VINVALL);
 570         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
 571
 572         its_fixup_cmd(cmd);
 573
 574         return valid_vpe(its, desc->its_vinvall_cmd.vpe);
 575 }
 576
 577 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
 578                                            struct its_cmd_block *cmd,
 579                                            struct its_cmd_desc *desc)
 580 {
 581         unsigned long vpt_addr;
 582         u64 target;
 583
 584         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
 585         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
 586
 587         its_encode_cmd(cmd, GITS_CMD_VMAPP);
 588         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
 589         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
 590         its_encode_target(cmd, target);
 591         its_encode_vpt_addr(cmd, vpt_addr);
 592         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
 593
 594         its_fixup_cmd(cmd);
 595
 596         return valid_vpe(its, desc->its_vmapp_cmd.vpe);
 597 }
 598
 599 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
 600                                             struct its_cmd_block *cmd,
 601                                             struct its_cmd_desc *desc)
 602 {
 603         u32 db;
 604
 605         if (desc->its_vmapti_cmd.db_enabled)
 606                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
 607         else
 608                 db = 1023;
 609
 610         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
 611         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
 612         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
 613         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
 614         its_encode_db_phys_id(cmd, db);
 615         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
 616
 617         its_fixup_cmd(cmd);
 618
 619         return valid_vpe(its, desc->its_vmapti_cmd.vpe);
 620 }
 621
 622 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
 623                                            struct its_cmd_block *cmd,
 624                                            struct its_cmd_desc *desc)
 625 {
 626         u32 db;
 627
 628         if (desc->its_vmovi_cmd.db_enabled)
 629                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
 630         else
 631                 db = 1023;
 632
 633         its_encode_cmd(cmd, GITS_CMD_VMOVI);
 634         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
 635         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
 636         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
 637         its_encode_db_phys_id(cmd, db);
 638         its_encode_db_valid(cmd, true);
 639
 640         its_fixup_cmd(cmd);
 641
 642         return valid_vpe(its, desc->its_vmovi_cmd.vpe);
 643 }
 644
 645 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
 646                                            struct its_cmd_block *cmd,
 647                                            struct its_cmd_desc *desc)
 648 {
 649         u64 target;
 650
 651         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
 652         its_encode_cmd(cmd, GITS_CMD_VMOVP);
 653         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
 654         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
 655         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
 656         its_encode_target(cmd, target);
 657
 658         its_fixup_cmd(cmd);
 659
 660         return valid_vpe(its, desc->its_vmovp_cmd.vpe);
 661 }
 662
 663 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 664                                  struct its_cmd_block *ptr)
 665 {
 666         return (ptr - its->cmd_base) * sizeof(*ptr);
 667 }
 668
 669 static int its_queue_full(struct its_node *its)
 670 {
 671         int widx;
 672         int ridx;
 673
 674         widx = its->cmd_write - its->cmd_base;
 675         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 676
 677         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 678         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 679                 return 1;
 680
 681         return 0;
 682 }
 683
 684 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 685 {
 686         struct its_cmd_block *cmd;
 687         u32 count = 1000000;    /* 1s! */
 688
 689         while (its_queue_full(its)) {
 690                 count--;
 691                 if (!count) {
 692                         pr_err_ratelimited("ITS queue not draining\n");
 693                         return NULL;
 694                 }
 695                 cpu_relax();
 696                 udelay(1);
 697         }
 698
 699         cmd = its->cmd_write++;
 700
 701         /* Handle queue wrapping */
 702         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 703                 its->cmd_write = its->cmd_base;
 704
 705         /* Clear command  */
 706         cmd->raw_cmd[0] = 0;
 707         cmd->raw_cmd[1] = 0;
 708         cmd->raw_cmd[2] = 0;
 709         cmd->raw_cmd[3] = 0;
 710
 711         return cmd;
 712 }
 713
 714 static struct its_cmd_block *its_post_commands(struct its_node *its)
 715 {
 716         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 717
 718         writel_relaxed(wr, its->base + GITS_CWRITER);
 719
 720         return its->cmd_write;
 721 }
 722
 723 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 724 {
 725         /*
 726          * Make sure the commands written to memory are observable by
 727          * the ITS.
 728          */
 729         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 730                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
 731         else
 732                 dsb(ishst);
 733 }
 734
 735 static int its_wait_for_range_completion(struct its_node *its,
 736                                          u64    prev_idx,
 737                                          struct its_cmd_block *to)
 738 {
 739         u64 rd_idx, to_idx, linear_idx;
 740         u32 count = 1000000;    /* 1s! */
 741
 742         /* Linearize to_idx if the command set has wrapped around */
 743         to_idx = its_cmd_ptr_to_offset(its, to);
 744         if (to_idx < prev_idx)
 745                 to_idx += ITS_CMD_QUEUE_SZ;
 746
 747         linear_idx = prev_idx;
 748
 749         while (1) {
 750                 s64 delta;
 751
 752                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 753
 754                 /*
 755                  * Compute the read pointer progress, taking the
 756                  * potential wrap-around into account.
 757                  */
 758                 delta = rd_idx - prev_idx;
 759                 if (rd_idx < prev_idx)
 760                         delta += ITS_CMD_QUEUE_SZ;
 761
 762                 linear_idx += delta;
 763                 if (linear_idx >= to_idx)
 764                         break;
 765
 766                 count--;
 767                 if (!count) {
 768                         pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
 769                                            to_idx, linear_idx);
 770                         return -1;
 771                 }
 772                 prev_idx = rd_idx;
 773                 cpu_relax();
 774                 udelay(1);
 775         }
 776
 777         return 0;
 778 }
 779
 780 /* Warning, macro hell follows */
 781 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
 782 void name(struct its_node *its,                                         \
 783           buildtype builder,                                            \
 784           struct its_cmd_desc *desc)                                    \
 785 {                                                                       \
 786         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
 787         synctype *sync_obj;                                             \
 788         unsigned long flags;                                            \
 789         u64 rd_idx;                                                     \
 790                                                                         \
 791         raw_spin_lock_irqsave(&its->lock, flags);                       \
 792                                                                         \
 793         cmd = its_allocate_entry(its);                                  \
 794         if (!cmd) {             /* We're soooooo screewed... */         \
 795                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
 796                 return;                                                 \
 797         }                                                               \
 798         sync_obj = builder(its, cmd, desc);                             \
 799         its_flush_cmd(its, cmd);                                        \
 800                                                                         \
 801         if (sync_obj) {                                                 \
 802                 sync_cmd = its_allocate_entry(its);                     \
 803                 if (!sync_cmd)                                          \
 804                         goto post;                                      \
 805                                                                         \
 806                 buildfn(its, sync_cmd, sync_obj);                       \
 807                 its_flush_cmd(its, sync_cmd);                           \
 808         }                                                               \
 809                                                                         \
 810 post:                                                                   \
 811         rd_idx = readl_relaxed(its->base + GITS_CREADR);                \
 812         next_cmd = its_post_commands(its);                              \
 813         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
 814                                                                         \
 815         if (its_wait_for_range_completion(its, rd_idx, next_cmd))       \
 816                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
 817 }
 818
 819 static void its_build_sync_cmd(struct its_node *its,
 820                                struct its_cmd_block *sync_cmd,
 821                                struct its_collection *sync_col)
 822 {
 823         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 824         its_encode_target(sync_cmd, sync_col->target_address);
 825
 826         its_fixup_cmd(sync_cmd);
 827 }
 828
 829 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
 830                              struct its_collection, its_build_sync_cmd)
 831
 832 static void its_build_vsync_cmd(struct its_node *its,
 833                                 struct its_cmd_block *sync_cmd,
 834                                 struct its_vpe *sync_vpe)
 835 {
 836         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
 837         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
 838
 839         its_fixup_cmd(sync_cmd);
 840 }
 841
 842 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
 843                              struct its_vpe, its_build_vsync_cmd)
 844
 845 static void its_send_int(struct its_device *dev, u32 event_id)
 846 {
 847         struct its_cmd_desc desc;
 848
 849         desc.its_int_cmd.dev = dev;
 850         desc.its_int_cmd.event_id = event_id;
 851
 852         its_send_single_command(dev->its, its_build_int_cmd, &desc);
 853 }
 854
 855 static void its_send_clear(struct its_device *dev, u32 event_id)
 856 {
 857         struct its_cmd_desc desc;
 858
 859         desc.its_clear_cmd.dev = dev;
 860         desc.its_clear_cmd.event_id = event_id;
 861
 862         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
 863 }
 864
 865 static void its_send_inv(struct its_device *dev, u32 event_id)
 866 {
 867         struct its_cmd_desc desc;
 868
 869         desc.its_inv_cmd.dev = dev;
 870         desc.its_inv_cmd.event_id = event_id;
 871
 872         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 873 }
 874
 875 static void its_send_mapd(struct its_device *dev, int valid)
 876 {
 877         struct its_cmd_desc desc;
 878
 879         desc.its_mapd_cmd.dev = dev;
 880         desc.its_mapd_cmd.valid = !!valid;
 881
 882         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 883 }
 884
 885 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 886                           int valid)
 887 {
 888         struct its_cmd_desc desc;
 889
 890         desc.its_mapc_cmd.col = col;
 891         desc.its_mapc_cmd.valid = !!valid;
 892
 893         its_send_single_command(its, its_build_mapc_cmd, &desc);
 894 }
 895
 896 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
 897 {
 898         struct its_cmd_desc desc;
 899
 900         desc.its_mapti_cmd.dev = dev;
 901         desc.its_mapti_cmd.phys_id = irq_id;
 902         desc.its_mapti_cmd.event_id = id;
 903
 904         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
 905 }
 906
 907 static void its_send_movi(struct its_device *dev,
 908                           struct its_collection *col, u32 id)
 909 {
 910         struct its_cmd_desc desc;
 911
 912         desc.its_movi_cmd.dev = dev;
 913         desc.its_movi_cmd.col = col;
 914         desc.its_movi_cmd.event_id = id;
 915
 916         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 917 }
 918
 919 static void its_send_discard(struct its_device *dev, u32 id)
 920 {
 921         struct its_cmd_desc desc;
 922
 923         desc.its_discard_cmd.dev = dev;
 924         desc.its_discard_cmd.event_id = id;
 925
 926         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 927 }
 928
 929 static void its_send_invall(struct its_node *its, struct its_collection *col)
 930 {
 931         struct its_cmd_desc desc;
 932
 933         desc.its_invall_cmd.col = col;
 934
 935         its_send_single_command(its, its_build_invall_cmd, &desc);
 936 }
 937
 938 static void its_send_vmapti(struct its_device *dev, u32 id)
 939 {
 940         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 941         struct its_cmd_desc desc;
 942
 943         desc.its_vmapti_cmd.vpe = map->vpe;
 944         desc.its_vmapti_cmd.dev = dev;
 945         desc.its_vmapti_cmd.virt_id = map->vintid;
 946         desc.its_vmapti_cmd.event_id = id;
 947         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
 948
 949         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
 950 }
 951
 952 static void its_send_vmovi(struct its_device *dev, u32 id)
 953 {
 954         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 955         struct its_cmd_desc desc;
 956
 957         desc.its_vmovi_cmd.vpe = map->vpe;
 958         desc.its_vmovi_cmd.dev = dev;
 959         desc.its_vmovi_cmd.event_id = id;
 960         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
 961
 962         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
 963 }
 964
 965 static void its_send_vmapp(struct its_node *its,
 966                            struct its_vpe *vpe, bool valid)
 967 {
 968         struct its_cmd_desc desc;
 969
 970         desc.its_vmapp_cmd.vpe = vpe;
 971         desc.its_vmapp_cmd.valid = valid;
 972         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
 973
 974         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
 975 }
 976
 977 static void its_send_vmovp(struct its_vpe *vpe)
 978 {
 979         struct its_cmd_desc desc;
 980         struct its_node *its;
 981         unsigned long flags;
 982         int col_id = vpe->col_idx;
 983
 984         desc.its_vmovp_cmd.vpe = vpe;
 985         desc.its_vmovp_cmd.its_list = (u16)its_list_map;
 986
 987         if (!its_list_map) {
 988                 its = list_first_entry(&its_nodes, struct its_node, entry);
 989                 desc.its_vmovp_cmd.seq_num = 0;
 990                 desc.its_vmovp_cmd.col = &its->collections[col_id];
 991                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
 992                 return;
 993         }
 994
 995         /*
 996          * Yet another marvel of the architecture. If using the
 997          * its_list "feature", we need to make sure that all ITSs
 998          * receive all VMOVP commands in the same order. The only way
 999          * to guarantee this is to make vmovp a serialization point.
1000          *
1001          * Wall <-- Head.
1002          */
1003         raw_spin_lock_irqsave(&vmovp_lock, flags);
1004
1005         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1006
1007         /* Emit VMOVPs */
1008         list_for_each_entry(its, &its_nodes, entry) {
1009                 if (!its->is_v4)
1010                         continue;
1011
1012                 if (!vpe->its_vm->vlpi_count[its->list_nr])
1013                         continue;
1014
1015                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1016                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1017         }
1018
1019         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1020 }
1021
1022 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1023 {
1024         struct its_cmd_desc desc;
1025
1026         desc.its_vinvall_cmd.vpe = vpe;
1027         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1028 }
1029
1030 /*
1031  * irqchip functions - assumes MSI, mostly.
1032  */
1033
1034 static inline u32 its_get_event_id(struct irq_data *d)
1035 {
1036         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1037         return d->hwirq - its_dev->event_map.lpi_base;
1038 }
1039
1040 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1041 {
1042         irq_hw_number_t hwirq;
1043         void *va;
1044         u8 *cfg;
1045
1046         if (irqd_is_forwarded_to_vcpu(d)) {
1047                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1048                 u32 event = its_get_event_id(d);
1049                 struct its_vlpi_map *map;
1050
1051                 va = page_address(its_dev->event_map.vm->vprop_page);
1052                 map = &its_dev->event_map.vlpi_maps[event];
1053                 hwirq = map->vintid;
1054
1055                 /* Remember the updated property */
1056                 map->properties &= ~clr;
1057                 map->properties |= set | LPI_PROP_GROUP1;
1058         } else {
1059                 va = gic_rdists->prop_table_va;
1060                 hwirq = d->hwirq;
1061         }
1062
1063         cfg = va + hwirq - 8192;
1064         *cfg &= ~clr;
1065         *cfg |= set | LPI_PROP_GROUP1;
1066
1067         /*
1068          * Make the above write visible to the redistributors.
1069          * And yes, we're flushing exactly: One. Single. Byte.
1070          * Humpf...
1071          */
1072         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1073                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1074         else
1075                 dsb(ishst);
1076 }
1077
1078 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1079 {
1080         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1081
1082         lpi_write_config(d, clr, set);
1083         its_send_inv(its_dev, its_get_event_id(d));
1084 }
1085
1086 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1087 {
1088         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1089         u32 event = its_get_event_id(d);
1090
1091         if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1092                 return;
1093
1094         its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1095
1096         /*
1097          * More fun with the architecture:
1098          *
1099          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1100          * value or to 1023, depending on the enable bit. But that
1101          * would be issueing a mapping for an /existing/ DevID+EventID
1102          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1103          * to the /same/ vPE, using this opportunity to adjust the
1104          * doorbell. Mouahahahaha. We loves it, Precious.
1105          */
1106         its_send_vmovi(its_dev, event);
1107 }
1108
1109 static void its_mask_irq(struct irq_data *d)
1110 {
1111         if (irqd_is_forwarded_to_vcpu(d))
1112                 its_vlpi_set_doorbell(d, false);
1113
1114         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1115 }
1116
1117 static void its_unmask_irq(struct irq_data *d)
1118 {
1119         if (irqd_is_forwarded_to_vcpu(d))
1120                 its_vlpi_set_doorbell(d, true);
1121
1122         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1123 }
1124
1125 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1126                             bool force)
1127 {
1128         unsigned int cpu;
1129         const struct cpumask *cpu_mask = cpu_online_mask;
1130         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1131         struct its_collection *target_col;
1132         u32 id = its_get_event_id(d);
1133
1134         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1135         if (irqd_is_forwarded_to_vcpu(d))
1136                 return -EINVAL;
1137
1138        /* lpi cannot be routed to a redistributor that is on a foreign node */
1139         if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1140                 if (its_dev->its->numa_node >= 0) {
1141                         cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1142                         if (!cpumask_intersects(mask_val, cpu_mask))
1143                                 return -EINVAL;
1144                 }
1145         }
1146
1147         cpu = cpumask_any_and(mask_val, cpu_mask);
1148
1149         if (cpu >= nr_cpu_ids)
1150                 return -EINVAL;
1151
1152         /* don't set the affinity when the target cpu is same as current one */
1153         if (cpu != its_dev->event_map.col_map[id]) {
1154                 target_col = &its_dev->its->collections[cpu];
1155                 its_send_movi(its_dev, target_col, id);
1156                 its_dev->event_map.col_map[id] = cpu;
1157                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1158         }
1159
1160         return IRQ_SET_MASK_OK_DONE;
1161 }
1162
1163 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1164 {
1165         struct its_node *its = its_dev->its;
1166
1167         return its->phys_base + GITS_TRANSLATER;
1168 }
1169
1170 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1171 {
1172         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1173         struct its_node *its;
1174         u64 addr;
1175
1176         its = its_dev->its;
1177         addr = its->get_msi_base(its_dev);
1178
1179         msg->address_lo         = lower_32_bits(addr);
1180         msg->address_hi         = upper_32_bits(addr);
1181         msg->data               = its_get_event_id(d);
1182
1183         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1184 }
1185
1186 static int its_irq_set_irqchip_state(struct irq_data *d,
1187                                      enum irqchip_irq_state which,
1188                                      bool state)
1189 {
1190         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1191         u32 event = its_get_event_id(d);
1192
1193         if (which != IRQCHIP_STATE_PENDING)
1194                 return -EINVAL;
1195
1196         if (state)
1197                 its_send_int(its_dev, event);
1198         else
1199                 its_send_clear(its_dev, event);
1200
1201         return 0;
1202 }
1203
1204 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1205 {
1206         unsigned long flags;
1207
1208         /* Not using the ITS list? Everything is always mapped. */
1209         if (!its_list_map)
1210                 return;
1211
1212         raw_spin_lock_irqsave(&vmovp_lock, flags);
1213
1214         /*
1215          * If the VM wasn't mapped yet, iterate over the vpes and get
1216          * them mapped now.
1217          */
1218         vm->vlpi_count[its->list_nr]++;
1219
1220         if (vm->vlpi_count[its->list_nr] == 1) {
1221                 int i;
1222
1223                 for (i = 0; i < vm->nr_vpes; i++) {
1224                         struct its_vpe *vpe = vm->vpes[i];
1225                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1226
1227                         /* Map the VPE to the first possible CPU */
1228                         vpe->col_idx = cpumask_first(cpu_online_mask);
1229                         its_send_vmapp(its, vpe, true);
1230                         its_send_vinvall(its, vpe);
1231                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1232                 }
1233         }
1234
1235         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1236 }
1237
1238 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1239 {
1240         unsigned long flags;
1241
1242         /* Not using the ITS list? Everything is always mapped. */
1243         if (!its_list_map)
1244                 return;
1245
1246         raw_spin_lock_irqsave(&vmovp_lock, flags);
1247
1248         if (!--vm->vlpi_count[its->list_nr]) {
1249                 int i;
1250
1251                 for (i = 0; i < vm->nr_vpes; i++)
1252                         its_send_vmapp(its, vm->vpes[i], false);
1253         }
1254
1255         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1256 }
1257
1258 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1259 {
1260         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1261         u32 event = its_get_event_id(d);
1262         int ret = 0;
1263
1264         if (!info->map)
1265                 return -EINVAL;
1266
1267         mutex_lock(&its_dev->event_map.vlpi_lock);
1268
1269         if (!its_dev->event_map.vm) {
1270                 struct its_vlpi_map *maps;
1271
1272                 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1273                                GFP_KERNEL);
1274                 if (!maps) {
1275                         ret = -ENOMEM;
1276                         goto out;
1277                 }
1278
1279                 its_dev->event_map.vm = info->map->vm;
1280                 its_dev->event_map.vlpi_maps = maps;
1281         } else if (its_dev->event_map.vm != info->map->vm) {
1282                 ret = -EINVAL;
1283                 goto out;
1284         }
1285
1286         /* Get our private copy of the mapping information */
1287         its_dev->event_map.vlpi_maps[event] = *info->map;
1288
1289         if (irqd_is_forwarded_to_vcpu(d)) {
1290                 /* Already mapped, move it around */
1291                 its_send_vmovi(its_dev, event);
1292         } else {
1293                 /* Ensure all the VPEs are mapped on this ITS */
1294                 its_map_vm(its_dev->its, info->map->vm);
1295
1296                 /*
1297                  * Flag the interrupt as forwarded so that we can
1298                  * start poking the virtual property table.
1299                  */
1300                 irqd_set_forwarded_to_vcpu(d);
1301
1302                 /* Write out the property to the prop table */
1303                 lpi_write_config(d, 0xff, info->map->properties);
1304
1305                 /* Drop the physical mapping */
1306                 its_send_discard(its_dev, event);
1307
1308                 /* and install the virtual one */
1309                 its_send_vmapti(its_dev, event);
1310
1311                 /* Increment the number of VLPIs */
1312                 its_dev->event_map.nr_vlpis++;
1313         }
1314
1315 out:
1316         mutex_unlock(&its_dev->event_map.vlpi_lock);
1317         return ret;
1318 }
1319
1320 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1321 {
1322         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1323         u32 event = its_get_event_id(d);
1324         int ret = 0;
1325
1326         mutex_lock(&its_dev->event_map.vlpi_lock);
1327
1328         if (!its_dev->event_map.vm ||
1329             !its_dev->event_map.vlpi_maps[event].vm) {
1330                 ret = -EINVAL;
1331                 goto out;
1332         }
1333
1334         /* Copy our mapping information to the incoming request */
1335         *info->map = its_dev->event_map.vlpi_maps[event];
1336
1337 out:
1338         mutex_unlock(&its_dev->event_map.vlpi_lock);
1339         return ret;
1340 }
1341
1342 static int its_vlpi_unmap(struct irq_data *d)
1343 {
1344         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1345         u32 event = its_get_event_id(d);
1346         int ret = 0;
1347
1348         mutex_lock(&its_dev->event_map.vlpi_lock);
1349
1350         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1351                 ret = -EINVAL;
1352                 goto out;
1353         }
1354
1355         /* Drop the virtual mapping */
1356         its_send_discard(its_dev, event);
1357
1358         /* and restore the physical one */
1359         irqd_clr_forwarded_to_vcpu(d);
1360         its_send_mapti(its_dev, d->hwirq, event);
1361         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1362                                     LPI_PROP_ENABLED |
1363                                     LPI_PROP_GROUP1));
1364
1365         /* Potentially unmap the VM from this ITS */
1366         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1367
1368         /*
1369          * Drop the refcount and make the device available again if
1370          * this was the last VLPI.
1371          */
1372         if (!--its_dev->event_map.nr_vlpis) {
1373                 its_dev->event_map.vm = NULL;
1374                 kfree(its_dev->event_map.vlpi_maps);
1375         }
1376
1377 out:
1378         mutex_unlock(&its_dev->event_map.vlpi_lock);
1379         return ret;
1380 }
1381
1382 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1383 {
1384         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1385
1386         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1387                 return -EINVAL;
1388
1389         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1390                 lpi_update_config(d, 0xff, info->config);
1391         else
1392                 lpi_write_config(d, 0xff, info->config);
1393         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1394
1395         return 0;
1396 }
1397
1398 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1399 {
1400         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1401         struct its_cmd_info *info = vcpu_info;
1402
1403         /* Need a v4 ITS */
1404         if (!its_dev->its->is_v4)
1405                 return -EINVAL;
1406
1407         /* Unmap request? */
1408         if (!info)
1409                 return its_vlpi_unmap(d);
1410
1411         switch (info->cmd_type) {
1412         case MAP_VLPI:
1413                 return its_vlpi_map(d, info);
1414
1415         case GET_VLPI:
1416                 return its_vlpi_get(d, info);
1417
1418         case PROP_UPDATE_VLPI:
1419         case PROP_UPDATE_AND_INV_VLPI:
1420                 return its_vlpi_prop_update(d, info);
1421
1422         default:
1423                 return -EINVAL;
1424         }
1425 }
1426
1427 static struct irq_chip its_irq_chip = {
1428         .name                   = "ITS",
1429         .irq_mask               = its_mask_irq,
1430         .irq_unmask             = its_unmask_irq,
1431         .irq_eoi                = irq_chip_eoi_parent,
1432         .irq_set_affinity       = its_set_affinity,
1433         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1434         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1435         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1436 };
1437
1438
1439 /*
1440  * How we allocate LPIs:
1441  *
1442  * lpi_range_list contains ranges of LPIs that are to available to
1443  * allocate from. To allocate LPIs, just pick the first range that
1444  * fits the required allocation, and reduce it by the required
1445  * amount. Once empty, remove the range from the list.
1446  *
1447  * To free a range of LPIs, add a free range to the list, sort it and
1448  * merge the result if the new range happens to be adjacent to an
1449  * already free block.
1450  *
1451  * The consequence of the above is that allocation is cost is low, but
1452  * freeing is expensive. We assumes that freeing rarely occurs.
1453  */
1454 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
1455
1456 static DEFINE_MUTEX(lpi_range_lock);
1457 static LIST_HEAD(lpi_range_list);
1458
1459 struct lpi_range {
1460         struct list_head        entry;
1461         u32                     base_id;
1462         u32                     span;
1463 };
1464
1465 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1466 {
1467         struct lpi_range *range;
1468
1469         range = kmalloc(sizeof(*range), GFP_KERNEL);
1470         if (range) {
1471                 range->base_id = base;
1472                 range->span = span;
1473         }
1474
1475         return range;
1476 }
1477
1478 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1479 {
1480         struct lpi_range *range, *tmp;
1481         int err = -ENOSPC;
1482
1483         mutex_lock(&lpi_range_lock);
1484
1485         list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1486                 if (range->span >= nr_lpis) {
1487                         *base = range->base_id;
1488                         range->base_id += nr_lpis;
1489                         range->span -= nr_lpis;
1490
1491                         if (range->span == 0) {
1492                                 list_del(&range->entry);
1493                                 kfree(range);
1494                         }
1495
1496                         err = 0;
1497                         break;
1498                 }
1499         }
1500
1501         mutex_unlock(&lpi_range_lock);
1502
1503         pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1504         return err;
1505 }
1506
1507 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1508 {
1509         if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1510                 return;
1511         if (a->base_id + a->span != b->base_id)
1512                 return;
1513         b->base_id = a->base_id;
1514         b->span += a->span;
1515         list_del(&a->entry);
1516         kfree(a);
1517 }
1518
1519 static int free_lpi_range(u32 base, u32 nr_lpis)
1520 {
1521         struct lpi_range *new, *old;
1522
1523         new = mk_lpi_range(base, nr_lpis);
1524         if (!new)
1525                 return -ENOMEM;
1526
1527         mutex_lock(&lpi_range_lock);
1528
1529         list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1530                 if (old->base_id < base)
1531                         break;
1532         }
1533         /*
1534          * old is the last element with ->base_id smaller than base,
1535          * so new goes right after it. If there are no elements with
1536          * ->base_id smaller than base, &old->entry ends up pointing
1537          * at the head of the list, and inserting new it the start of
1538          * the list is the right thing to do in that case as well.
1539          */
1540         list_add(&new->entry, &old->entry);
1541         /*
1542          * Now check if we can merge with the preceding and/or
1543          * following ranges.
1544          */
1545         merge_lpi_ranges(old, new);
1546         merge_lpi_ranges(new, list_next_entry(new, entry));
1547
1548         mutex_unlock(&lpi_range_lock);
1549         return 0;
1550 }
1551
1552 static int __init its_lpi_init(u32 id_bits)
1553 {
1554         u32 lpis = (1UL << id_bits) - 8192;
1555         u32 numlpis;
1556         int err;
1557
1558         numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1559
1560         if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1561                 lpis = numlpis;
1562                 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1563                         lpis);
1564         }
1565
1566         /*
1567          * Initializing the allocator is just the same as freeing the
1568          * full range of LPIs.
1569          */
1570         err = free_lpi_range(8192, lpis);
1571         pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1572         return err;
1573 }
1574
1575 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1576 {
1577         unsigned long *bitmap = NULL;
1578         int err = 0;
1579
1580         do {
1581                 err = alloc_lpi_range(nr_irqs, base);
1582                 if (!err)
1583                         break;
1584
1585                 nr_irqs /= 2;
1586         } while (nr_irqs > 0);
1587
1588         if (!nr_irqs)
1589                 err = -ENOSPC;
1590
1591         if (err)
1592                 goto out;
1593
1594         bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1595         if (!bitmap)
1596                 goto out;
1597
1598         *nr_ids = nr_irqs;
1599
1600 out:
1601         if (!bitmap)
1602                 *base = *nr_ids = 0;
1603
1604         return bitmap;
1605 }
1606
1607 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1608 {
1609         WARN_ON(free_lpi_range(base, nr_ids));
1610         kfree(bitmap);
1611 }
1612
1613 static void gic_reset_prop_table(void *va)
1614 {
1615         /* Priority 0xa0, Group-1, disabled */
1616         memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1617
1618         /* Make sure the GIC will observe the written configuration */
1619         gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1620 }
1621
1622 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1623 {
1624         struct page *prop_page;
1625
1626         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1627         if (!prop_page)
1628                 return NULL;
1629
1630         gic_reset_prop_table(page_address(prop_page));
1631
1632         return prop_page;
1633 }
1634
1635 static void its_free_prop_table(struct page *prop_page)
1636 {
1637         free_pages((unsigned long)page_address(prop_page),
1638                    get_order(LPI_PROPBASE_SZ));
1639 }
1640
1641 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1642 {
1643         phys_addr_t start, end, addr_end;
1644         u64 i;
1645
1646         /*
1647          * We don't bother checking for a kdump kernel as by
1648          * construction, the LPI tables are out of this kernel's
1649          * memory map.
1650          */
1651         if (is_kdump_kernel())
1652                 return true;
1653
1654         addr_end = addr + size - 1;
1655
1656         for_each_reserved_mem_region(i, &start, &end) {
1657                 if (addr >= start && addr_end <= end)
1658                         return true;
1659         }
1660
1661         /* Not found, not a good sign... */
1662         pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1663                 &addr, &addr_end);
1664         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1665         return false;
1666 }
1667
1668 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1669 {
1670         if (efi_enabled(EFI_CONFIG_TABLES))
1671                 return efi_mem_reserve_persistent(addr, size);
1672
1673         return 0;
1674 }
1675
1676 static int __init its_setup_lpi_prop_table(void)
1677 {
1678         if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1679                 u64 val;
1680
1681                 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1682                 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1683
1684                 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1685                 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1686                                                      LPI_PROPBASE_SZ,
1687                                                      MEMREMAP_WB);
1688                 gic_reset_prop_table(gic_rdists->prop_table_va);
1689         } else {
1690                 struct page *page;
1691
1692                 lpi_id_bits = min_t(u32,
1693                                     GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1694                                     ITS_MAX_LPI_NRBITS);
1695                 page = its_allocate_prop_table(GFP_NOWAIT);
1696                 if (!page) {
1697                         pr_err("Failed to allocate PROPBASE\n");
1698                         return -ENOMEM;
1699                 }
1700
1701                 gic_rdists->prop_table_pa = page_to_phys(page);
1702                 gic_rdists->prop_table_va = page_address(page);
1703                 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1704                                           LPI_PROPBASE_SZ));
1705         }
1706
1707         pr_info("GICv3: using LPI property table @%pa\n",
1708                 &gic_rdists->prop_table_pa);
1709
1710         return its_lpi_init(lpi_id_bits);
1711 }
1712
1713 static const char *its_base_type_string[] = {
1714         [GITS_BASER_TYPE_DEVICE]        = "Devices",
1715         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
1716         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
1717         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
1718         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
1719         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
1720         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
1721 };
1722
1723 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1724 {
1725         u32 idx = baser - its->tables;
1726
1727         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1728 }
1729
1730 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1731                             u64 val)
1732 {
1733         u32 idx = baser - its->tables;
1734
1735         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1736         baser->val = its_read_baser(its, baser);
1737 }
1738
1739 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1740                            u64 cache, u64 shr, u32 psz, u32 order,
1741                            bool indirect)
1742 {
1743         u64 val = its_read_baser(its, baser);
1744         u64 esz = GITS_BASER_ENTRY_SIZE(val);
1745         u64 type = GITS_BASER_TYPE(val);
1746         u64 baser_phys, tmp;
1747         u32 alloc_pages;
1748         struct page *page;
1749         void *base;
1750
1751 retry_alloc_baser:
1752         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1753         if (alloc_pages > GITS_BASER_PAGES_MAX) {
1754                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1755                         &its->phys_base, its_base_type_string[type],
1756                         alloc_pages, GITS_BASER_PAGES_MAX);
1757                 alloc_pages = GITS_BASER_PAGES_MAX;
1758                 order = get_order(GITS_BASER_PAGES_MAX * psz);
1759         }
1760
1761         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1762         if (!page)
1763                 return -ENOMEM;
1764
1765         base = (void *)page_address(page);
1766         baser_phys = virt_to_phys(base);
1767
1768         /* Check if the physical address of the memory is above 48bits */
1769         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1770
1771                 /* 52bit PA is supported only when PageSize=64K */
1772                 if (psz != SZ_64K) {
1773                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1774                         free_pages((unsigned long)base, order);
1775                         return -ENXIO;
1776                 }
1777
1778                 /* Convert 52bit PA to 48bit field */
1779                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1780         }
1781
1782 retry_baser:
1783         val = (baser_phys                                        |
1784                 (type << GITS_BASER_TYPE_SHIFT)                  |
1785                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
1786                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
1787                 cache                                            |
1788                 shr                                              |
1789                 GITS_BASER_VALID);
1790
1791         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
1792
1793         switch (psz) {
1794         case SZ_4K:
1795                 val |= GITS_BASER_PAGE_SIZE_4K;
1796                 break;
1797         case SZ_16K:
1798                 val |= GITS_BASER_PAGE_SIZE_16K;
1799                 break;
1800         case SZ_64K:
1801                 val |= GITS_BASER_PAGE_SIZE_64K;
1802                 break;
1803         }
1804
1805         its_write_baser(its, baser, val);
1806         tmp = baser->val;
1807
1808         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1809                 /*
1810                  * Shareability didn't stick. Just use
1811                  * whatever the read reported, which is likely
1812                  * to be the only thing this redistributor
1813                  * supports. If that's zero, make it
1814                  * non-cacheable as well.
1815                  */
1816                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1817                 if (!shr) {
1818                         cache = GITS_BASER_nC;
1819                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1820                 }
1821                 goto retry_baser;
1822         }
1823
1824         if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1825                 /*
1826                  * Page size didn't stick. Let's try a smaller
1827                  * size and retry. If we reach 4K, then
1828                  * something is horribly wrong...
1829                  */
1830                 free_pages((unsigned long)base, order);
1831                 baser->base = NULL;
1832
1833                 switch (psz) {
1834                 case SZ_16K:
1835                         psz = SZ_4K;
1836                         goto retry_alloc_baser;
1837                 case SZ_64K:
1838                         psz = SZ_16K;
1839                         goto retry_alloc_baser;
1840                 }
1841         }
1842
1843         if (val != tmp) {
1844                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1845                        &its->phys_base, its_base_type_string[type],
1846                        val, tmp);
1847                 free_pages((unsigned long)base, order);
1848                 return -ENXIO;
1849         }
1850
1851         baser->order = order;
1852         baser->base = base;
1853         baser->psz = psz;
1854         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1855
1856         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1857                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1858                 its_base_type_string[type],
1859                 (unsigned long)virt_to_phys(base),
1860                 indirect ? "indirect" : "flat", (int)esz,
1861                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1862
1863         return 0;
1864 }
1865
1866 static bool its_parse_indirect_baser(struct its_node *its,
1867                                      struct its_baser *baser,
1868                                      u32 psz, u32 *order, u32 ids)
1869 {
1870         u64 tmp = its_read_baser(its, baser);
1871         u64 type = GITS_BASER_TYPE(tmp);
1872         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1873         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1874         u32 new_order = *order;
1875         bool indirect = false;
1876
1877         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1878         if ((esz << ids) > (psz * 2)) {
1879                 /*
1880                  * Find out whether hw supports a single or two-level table by
1881                  * table by reading bit at offset '62' after writing '1' to it.
1882                  */
1883                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1884                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1885
1886                 if (indirect) {
1887                         /*
1888                          * The size of the lvl2 table is equal to ITS page size
1889                          * which is 'psz'. For computing lvl1 table size,
1890                          * subtract ID bits that sparse lvl2 table from 'ids'
1891                          * which is reported by ITS hardware times lvl1 table
1892                          * entry size.
1893                          */
1894                         ids -= ilog2(psz / (int)esz);
1895                         esz = GITS_LVL1_ENTRY_SIZE;
1896                 }
1897         }
1898
1899         /*
1900          * Allocate as many entries as required to fit the
1901          * range of device IDs that the ITS can grok... The ID
1902          * space being incredibly sparse, this results in a
1903          * massive waste of memory if two-level device table
1904          * feature is not supported by hardware.
1905          */
1906         new_order = max_t(u32, get_order(esz << ids), new_order);
1907         if (new_order >= MAX_ORDER) {
1908                 new_order = MAX_ORDER - 1;
1909                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1910                 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1911                         &its->phys_base, its_base_type_string[type],
1912                         its->device_ids, ids);
1913         }
1914
1915         *order = new_order;
1916
1917         return indirect;
1918 }
1919
1920 static void its_free_tables(struct its_node *its)
1921 {
1922         int i;
1923
1924         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1925                 if (its->tables[i].base) {
1926                         free_pages((unsigned long)its->tables[i].base,
1927                                    its->tables[i].order);
1928                         its->tables[i].base = NULL;
1929                 }
1930         }
1931 }
1932
1933 static int its_alloc_tables(struct its_node *its)
1934 {
1935         u64 shr = GITS_BASER_InnerShareable;
1936         u64 cache = GITS_BASER_RaWaWb;
1937         u32 psz = SZ_64K;
1938         int err, i;
1939
1940         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1941                 /* erratum 24313: ignore memory access type */
1942                 cache = GITS_BASER_nCnB;
1943
1944         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1945                 struct its_baser *baser = its->tables + i;
1946                 u64 val = its_read_baser(its, baser);
1947                 u64 type = GITS_BASER_TYPE(val);
1948                 u32 order = get_order(psz);
1949                 bool indirect = false;
1950
1951                 switch (type) {
1952                 case GITS_BASER_TYPE_NONE:
1953                         continue;
1954
1955                 case GITS_BASER_TYPE_DEVICE:
1956                         indirect = its_parse_indirect_baser(its, baser,
1957                                                             psz, &order,
1958                                                             its->device_ids);
1959                         break;
1960
1961                 case GITS_BASER_TYPE_VCPU:
1962                         indirect = its_parse_indirect_baser(its, baser,
1963                                                             psz, &order,
1964                                                             ITS_MAX_VPEID_BITS);
1965                         break;
1966                 }
1967
1968                 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1969                 if (err < 0) {
1970                         its_free_tables(its);
1971                         return err;
1972                 }
1973
1974                 /* Update settings which will be used for next BASERn */
1975                 psz = baser->psz;
1976                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1977                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int its_alloc_collections(struct its_node *its)
1984 {
1985         int i;
1986
1987         its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1988                                    GFP_KERNEL);
1989         if (!its->collections)
1990                 return -ENOMEM;
1991
1992         for (i = 0; i < nr_cpu_ids; i++)
1993                 its->collections[i].target_address = ~0ULL;
1994
1995         return 0;
1996 }
1997
1998 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1999 {
2000         struct page *pend_page;
2001
2002         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2003                                 get_order(LPI_PENDBASE_SZ));
2004         if (!pend_page)
2005                 return NULL;
2006
2007         /* Make sure the GIC will observe the zero-ed page */
2008         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2009
2010         return pend_page;
2011 }
2012
2013 static void its_free_pending_table(struct page *pt)
2014 {
2015         free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2016 }
2017
2018 /*
2019  * Booting with kdump and LPIs enabled is generally fine. Any other
2020  * case is wrong in the absence of firmware/EFI support.
2021  */
2022 static bool enabled_lpis_allowed(void)
2023 {
2024         phys_addr_t addr;
2025         u64 val;
2026
2027         /* Check whether the property table is in a reserved region */
2028         val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2029         addr = val & GENMASK_ULL(51, 12);
2030
2031         return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2032 }
2033
2034 static int __init allocate_lpi_tables(void)
2035 {
2036         u64 val;
2037         int err, cpu;
2038
2039         /*
2040          * If LPIs are enabled while we run this from the boot CPU,
2041          * flag the RD tables as pre-allocated if the stars do align.
2042          */
2043         val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2044         if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2045                 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2046                                       RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2047                 pr_info("GICv3: Using preallocated redistributor tables\n");
2048         }
2049
2050         err = its_setup_lpi_prop_table();
2051         if (err)
2052                 return err;
2053
2054         /*
2055          * We allocate all the pending tables anyway, as we may have a
2056          * mix of RDs that have had LPIs enabled, and some that
2057          * don't. We'll free the unused ones as each CPU comes online.
2058          */
2059         for_each_possible_cpu(cpu) {
2060                 struct page *pend_page;
2061
2062                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2063                 if (!pend_page) {
2064                         pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2065                         return -ENOMEM;
2066                 }
2067
2068                 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2069         }
2070
2071         return 0;
2072 }
2073
2074 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2075 {
2076         u32 count = 1000000;    /* 1s! */
2077         bool clean;
2078         u64 val;
2079
2080         val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2081         val &= ~GICR_VPENDBASER_Valid;
2082         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2083
2084         do {
2085                 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2086                 clean = !(val & GICR_VPENDBASER_Dirty);
2087                 if (!clean) {
2088                         count--;
2089                         cpu_relax();
2090                         udelay(1);
2091                 }
2092         } while (!clean && count);
2093
2094         return val;
2095 }
2096
2097 static void its_cpu_init_lpis(void)
2098 {
2099         void __iomem *rbase = gic_data_rdist_rd_base();
2100         struct page *pend_page;
2101         phys_addr_t paddr;
2102         u64 val, tmp;
2103
2104         if (gic_data_rdist()->lpi_enabled)
2105                 return;
2106
2107         val = readl_relaxed(rbase + GICR_CTLR);
2108         if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2109             (val & GICR_CTLR_ENABLE_LPIS)) {
2110                 /*
2111                  * Check that we get the same property table on all
2112                  * RDs. If we don't, this is hopeless.
2113                  */
2114                 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2115                 paddr &= GENMASK_ULL(51, 12);
2116                 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2117                         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2118
2119                 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2120                 paddr &= GENMASK_ULL(51, 16);
2121
2122                 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2123                 its_free_pending_table(gic_data_rdist()->pend_page);
2124                 gic_data_rdist()->pend_page = NULL;
2125
2126                 goto out;
2127         }
2128
2129         pend_page = gic_data_rdist()->pend_page;
2130         paddr = page_to_phys(pend_page);
2131         WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2132
2133         /* set PROPBASE */
2134         val = (gic_rdists->prop_table_pa |
2135                GICR_PROPBASER_InnerShareable |
2136                GICR_PROPBASER_RaWaWb |
2137                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2138
2139         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2140         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2141
2142         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2143                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2144                         /*
2145                          * The HW reports non-shareable, we must
2146                          * remove the cacheability attributes as
2147                          * well.
2148                          */
2149                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2150                                  GICR_PROPBASER_CACHEABILITY_MASK);
2151                         val |= GICR_PROPBASER_nC;
2152                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2153                 }
2154                 pr_info_once("GIC: using cache flushing for LPI property table\n");
2155                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2156         }
2157
2158         /* set PENDBASE */
2159         val = (page_to_phys(pend_page) |
2160                GICR_PENDBASER_InnerShareable |
2161                GICR_PENDBASER_RaWaWb);
2162
2163         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2164         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2165
2166         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2167                 /*
2168                  * The HW reports non-shareable, we must remove the
2169                  * cacheability attributes as well.
2170                  */
2171                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2172                          GICR_PENDBASER_CACHEABILITY_MASK);
2173                 val |= GICR_PENDBASER_nC;
2174                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2175         }
2176
2177         /* Enable LPIs */
2178         val = readl_relaxed(rbase + GICR_CTLR);
2179         val |= GICR_CTLR_ENABLE_LPIS;
2180         writel_relaxed(val, rbase + GICR_CTLR);
2181
2182         if (gic_rdists->has_vlpis) {
2183                 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2184
2185                 /*
2186                  * It's possible for CPU to receive VLPIs before it is
2187                  * sheduled as a vPE, especially for the first CPU, and the
2188                  * VLPI with INTID larger than 2^(IDbits+1) will be considered
2189                  * as out of range and dropped by GIC.
2190                  * So we initialize IDbits to known value to avoid VLPI drop.
2191                  */
2192                 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2193                 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2194                         smp_processor_id(), val);
2195                 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2196
2197                 /*
2198                  * Also clear Valid bit of GICR_VPENDBASER, in case some
2199                  * ancient programming gets left in and has possibility of
2200                  * corrupting memory.
2201                  */
2202                 val = its_clear_vpend_valid(vlpi_base);
2203                 WARN_ON(val & GICR_VPENDBASER_Dirty);
2204         }
2205
2206         /* Make sure the GIC has seen the above */
2207         dsb(sy);
2208 out:
2209         gic_data_rdist()->lpi_enabled = true;
2210         pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2211                 smp_processor_id(),
2212                 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2213                 &paddr);
2214 }
2215
2216 static void its_cpu_init_collection(struct its_node *its)
2217 {
2218         int cpu = smp_processor_id();
2219         u64 target;
2220
2221         /* avoid cross node collections and its mapping */
2222         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2223                 struct device_node *cpu_node;
2224
2225                 cpu_node = of_get_cpu_node(cpu, NULL);
2226                 if (its->numa_node != NUMA_NO_NODE &&
2227                         its->numa_node != of_node_to_nid(cpu_node))
2228                         return;
2229         }
2230
2231         /*
2232          * We now have to bind each collection to its target
2233          * redistributor.
2234          */
2235         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2236                 /*
2237                  * This ITS wants the physical address of the
2238                  * redistributor.
2239                  */
2240                 target = gic_data_rdist()->phys_base;
2241         } else {
2242                 /* This ITS wants a linear CPU number. */
2243                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2244                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2245         }
2246
2247         /* Perform collection mapping */
2248         its->collections[cpu].target_address = target;
2249         its->collections[cpu].col_id = cpu;
2250
2251         its_send_mapc(its, &its->collections[cpu], 1);
2252         its_send_invall(its, &its->collections[cpu]);
2253 }
2254
2255 static void its_cpu_init_collections(void)
2256 {
2257         struct its_node *its;
2258
2259         raw_spin_lock(&its_lock);
2260
2261         list_for_each_entry(its, &its_nodes, entry)
2262                 its_cpu_init_collection(its);
2263
2264         raw_spin_unlock(&its_lock);
2265 }
2266
2267 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2268 {
2269         struct its_device *its_dev = NULL, *tmp;
2270         unsigned long flags;
2271
2272         raw_spin_lock_irqsave(&its->lock, flags);
2273
2274         list_for_each_entry(tmp, &its->its_device_list, entry) {
2275                 if (tmp->device_id == dev_id) {
2276                         its_dev = tmp;
2277                         break;
2278                 }
2279         }
2280
2281         raw_spin_unlock_irqrestore(&its->lock, flags);
2282
2283         return its_dev;
2284 }
2285
2286 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2287 {
2288         int i;
2289
2290         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2291                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2292                         return &its->tables[i];
2293         }
2294
2295         return NULL;
2296 }
2297
2298 static bool its_alloc_table_entry(struct its_node *its,
2299                                   struct its_baser *baser, u32 id)
2300 {
2301         struct page *page;
2302         u32 esz, idx;
2303         __le64 *table;
2304
2305         /* Don't allow device id that exceeds single, flat table limit */
2306         esz = GITS_BASER_ENTRY_SIZE(baser->val);
2307         if (!(baser->val & GITS_BASER_INDIRECT))
2308                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2309
2310         /* Compute 1st level table index & check if that exceeds table limit */
2311         idx = id >> ilog2(baser->psz / esz);
2312         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2313                 return false;
2314
2315         table = baser->base;
2316
2317         /* Allocate memory for 2nd level table */
2318         if (!table[idx]) {
2319                 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2320                                         get_order(baser->psz));
2321                 if (!page)
2322                         return false;
2323
2324                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2325                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2326                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
2327
2328                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2329
2330                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2331                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2332                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2333
2334                 /* Ensure updated table contents are visible to ITS hardware */
2335                 dsb(sy);
2336         }
2337
2338         return true;
2339 }
2340
2341 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2342 {
2343         struct its_baser *baser;
2344
2345         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2346
2347         /* Don't allow device id that exceeds ITS hardware limit */
2348         if (!baser)
2349                 return (ilog2(dev_id) < its->device_ids);
2350
2351         return its_alloc_table_entry(its, baser, dev_id);
2352 }
2353
2354 static bool its_alloc_vpe_table(u32 vpe_id)
2355 {
2356         struct its_node *its;
2357
2358         /*
2359          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2360          * could try and only do it on ITSs corresponding to devices
2361          * that have interrupts targeted at this VPE, but the
2362          * complexity becomes crazy (and you have tons of memory
2363          * anyway, right?).
2364          */
2365         list_for_each_entry(its, &its_nodes, entry) {
2366                 struct its_baser *baser;
2367
2368                 if (!its->is_v4)
2369                         continue;
2370
2371                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2372                 if (!baser)
2373                         return false;
2374
2375                 if (!its_alloc_table_entry(its, baser, vpe_id))
2376                         return false;
2377         }
2378
2379         return true;
2380 }
2381
2382 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2383                                             int nvecs, bool alloc_lpis)
2384 {
2385         struct its_device *dev;
2386         unsigned long *lpi_map = NULL;
2387         unsigned long flags;
2388         u16 *col_map = NULL;
2389         void *itt;
2390         int lpi_base;
2391         int nr_lpis;
2392         int nr_ites;
2393         int sz;
2394
2395         if (!its_alloc_device_table(its, dev_id))
2396                 return NULL;
2397
2398         if (WARN_ON(!is_power_of_2(nvecs)))
2399                 nvecs = roundup_pow_of_two(nvecs);
2400
2401         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2402         /*
2403          * Even if the device wants a single LPI, the ITT must be
2404          * sized as a power of two (and you need at least one bit...).
2405          */
2406         nr_ites = max(2, nvecs);
2407         sz = nr_ites * its->ite_size;
2408         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2409         itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2410         if (alloc_lpis) {
2411                 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2412                 if (lpi_map)
2413                         col_map = kcalloc(nr_lpis, sizeof(*col_map),
2414                                           GFP_KERNEL);
2415         } else {
2416                 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2417                 nr_lpis = 0;
2418                 lpi_base = 0;
2419         }
2420
2421         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
2422                 kfree(dev);
2423                 kfree(itt);
2424                 kfree(lpi_map);
2425                 kfree(col_map);
2426                 return NULL;
2427         }
2428
2429         gic_flush_dcache_to_poc(itt, sz);
2430
2431         dev->its = its;
2432         dev->itt = itt;
2433         dev->nr_ites = nr_ites;
2434         dev->event_map.lpi_map = lpi_map;
2435         dev->event_map.col_map = col_map;
2436         dev->event_map.lpi_base = lpi_base;
2437         dev->event_map.nr_lpis = nr_lpis;
2438         mutex_init(&dev->event_map.vlpi_lock);
2439         dev->device_id = dev_id;
2440         INIT_LIST_HEAD(&dev->entry);
2441
2442         raw_spin_lock_irqsave(&its->lock, flags);
2443         list_add(&dev->entry, &its->its_device_list);
2444         raw_spin_unlock_irqrestore(&its->lock, flags);
2445
2446         /* Map device to its ITT */
2447         its_send_mapd(dev, 1);
2448
2449         return dev;
2450 }
2451
2452 static void its_free_device(struct its_device *its_dev)
2453 {
2454         unsigned long flags;
2455
2456         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2457         list_del(&its_dev->entry);
2458         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2459         kfree(its_dev->itt);
2460         kfree(its_dev);
2461 }
2462
2463 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2464 {
2465         int idx;
2466
2467         idx = bitmap_find_free_region(dev->event_map.lpi_map,
2468                                       dev->event_map.nr_lpis,
2469                                       get_count_order(nvecs));
2470         if (idx < 0)
2471                 return -ENOSPC;
2472
2473         *hwirq = dev->event_map.lpi_base + idx;
2474         set_bit(idx, dev->event_map.lpi_map);
2475
2476         return 0;
2477 }
2478
2479 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2480                            int nvec, msi_alloc_info_t *info)
2481 {
2482         struct its_node *its;
2483         struct its_device *its_dev;
2484         struct msi_domain_info *msi_info;
2485         u32 dev_id;
2486         int err = 0;
2487
2488         /*
2489          * We ignore "dev" entirely, and rely on the dev_id that has
2490          * been passed via the scratchpad. This limits this domain's
2491          * usefulness to upper layers that definitely know that they
2492          * are built on top of the ITS.
2493          */
2494         dev_id = info->scratchpad[0].ul;
2495
2496         msi_info = msi_get_domain_info(domain);
2497         its = msi_info->data;
2498
2499         if (!gic_rdists->has_direct_lpi &&
2500             vpe_proxy.dev &&
2501             vpe_proxy.dev->its == its &&
2502             dev_id == vpe_proxy.dev->device_id) {
2503                 /* Bad luck. Get yourself a better implementation */
2504                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2505                           dev_id);
2506                 return -EINVAL;
2507         }
2508
2509         mutex_lock(&its->dev_alloc_lock);
2510         its_dev = its_find_device(its, dev_id);
2511         if (its_dev) {
2512                 /*
2513                  * We already have seen this ID, probably through
2514                  * another alias (PCI bridge of some sort). No need to
2515                  * create the device.
2516                  */
2517                 its_dev->shared = true;
2518                 pr_debug("Reusing ITT for devID %x\n", dev_id);
2519                 goto out;
2520         }
2521
2522         its_dev = its_create_device(its, dev_id, nvec, true);
2523         if (!its_dev) {
2524                 err = -ENOMEM;
2525                 goto out;
2526         }
2527
2528         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2529 out:
2530         mutex_unlock(&its->dev_alloc_lock);
2531         info->scratchpad[0].ptr = its_dev;
2532         return err;
2533 }
2534
2535 static struct msi_domain_ops its_msi_domain_ops = {
2536         .msi_prepare    = its_msi_prepare,
2537 };
2538
2539 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2540                                     unsigned int virq,
2541                                     irq_hw_number_t hwirq)
2542 {
2543         struct irq_fwspec fwspec;
2544
2545         if (irq_domain_get_of_node(domain->parent)) {
2546                 fwspec.fwnode = domain->parent->fwnode;
2547                 fwspec.param_count = 3;
2548                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2549                 fwspec.param[1] = hwirq;
2550                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2551         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2552                 fwspec.fwnode = domain->parent->fwnode;
2553                 fwspec.param_count = 2;
2554                 fwspec.param[0] = hwirq;
2555                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2556         } else {
2557                 return -EINVAL;
2558         }
2559
2560         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2561 }
2562
2563 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2564                                 unsigned int nr_irqs, void *args)
2565 {
2566         msi_alloc_info_t *info = args;
2567         struct its_device *its_dev = info->scratchpad[0].ptr;
2568         struct its_node *its = its_dev->its;
2569         irq_hw_number_t hwirq;
2570         int err;
2571         int i;
2572
2573         err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2574         if (err)
2575                 return err;
2576
2577         err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2578         if (err)
2579                 return err;
2580
2581         for (i = 0; i < nr_irqs; i++) {
2582                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2583                 if (err)
2584                         return err;
2585
2586                 irq_domain_set_hwirq_and_chip(domain, virq + i,
2587                                               hwirq + i, &its_irq_chip, its_dev);
2588                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2589                 pr_debug("ID:%d pID:%d vID:%d\n",
2590                          (int)(hwirq + i - its_dev->event_map.lpi_base),
2591                          (int)(hwirq + i), virq + i);
2592         }
2593
2594         return 0;
2595 }
2596
2597 static int its_irq_domain_activate(struct irq_domain *domain,
2598                                    struct irq_data *d, bool reserve)
2599 {
2600         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2601         u32 event = its_get_event_id(d);
2602         const struct cpumask *cpu_mask = cpu_online_mask;
2603         int cpu;
2604
2605         /* get the cpu_mask of local node */
2606         if (its_dev->its->numa_node >= 0)
2607                 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2608
2609         /* Bind the LPI to the first possible CPU */
2610         cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2611         if (cpu >= nr_cpu_ids) {
2612                 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2613                         return -EINVAL;
2614
2615                 cpu = cpumask_first(cpu_online_mask);
2616         }
2617
2618         its_dev->event_map.col_map[event] = cpu;
2619         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2620
2621         /* Map the GIC IRQ and event to the device */
2622         its_send_mapti(its_dev, d->hwirq, event);
2623         return 0;
2624 }
2625
2626 static void its_irq_domain_deactivate(struct irq_domain *domain,
2627                                       struct irq_data *d)
2628 {
2629         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2630         u32 event = its_get_event_id(d);
2631
2632         /* Stop the delivery of interrupts */
2633         its_send_discard(its_dev, event);
2634 }
2635
2636 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2637                                 unsigned int nr_irqs)
2638 {
2639         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2640         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2641         struct its_node *its = its_dev->its;
2642         int i;
2643
2644         for (i = 0; i < nr_irqs; i++) {
2645                 struct irq_data *data = irq_domain_get_irq_data(domain,
2646                                                                 virq + i);
2647                 u32 event = its_get_event_id(data);
2648
2649                 /* Mark interrupt index as unused */
2650                 clear_bit(event, its_dev->event_map.lpi_map);
2651
2652                 /* Nuke the entry in the domain */
2653                 irq_domain_reset_irq_data(data);
2654         }
2655
2656         mutex_lock(&its->dev_alloc_lock);
2657
2658         /*
2659          * If all interrupts have been freed, start mopping the
2660          * floor. This is conditionned on the device not being shared.
2661          */
2662         if (!its_dev->shared &&
2663             bitmap_empty(its_dev->event_map.lpi_map,
2664                          its_dev->event_map.nr_lpis)) {
2665                 its_lpi_free(its_dev->event_map.lpi_map,
2666                              its_dev->event_map.lpi_base,
2667                              its_dev->event_map.nr_lpis);
2668                 kfree(its_dev->event_map.col_map);
2669
2670                 /* Unmap device/itt */
2671                 its_send_mapd(its_dev, 0);
2672                 its_free_device(its_dev);
2673         }
2674
2675         mutex_unlock(&its->dev_alloc_lock);
2676
2677         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2678 }
2679
2680 static const struct irq_domain_ops its_domain_ops = {
2681         .alloc                  = its_irq_domain_alloc,
2682         .free                   = its_irq_domain_free,
2683         .activate               = its_irq_domain_activate,
2684         .deactivate             = its_irq_domain_deactivate,
2685 };
2686
2687 /*
2688  * This is insane.
2689  *
2690  * If a GICv4 doesn't implement Direct LPIs (which is extremely
2691  * likely), the only way to perform an invalidate is to use a fake
2692  * device to issue an INV command, implying that the LPI has first
2693  * been mapped to some event on that device. Since this is not exactly
2694  * cheap, we try to keep that mapping around as long as possible, and
2695  * only issue an UNMAP if we're short on available slots.
2696  *
2697  * Broken by design(tm).
2698  */
2699 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2700 {
2701         /* Already unmapped? */
2702         if (vpe->vpe_proxy_event == -1)
2703                 return;
2704
2705         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2706         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2707
2708         /*
2709          * We don't track empty slots at all, so let's move the
2710          * next_victim pointer if we can quickly reuse that slot
2711          * instead of nuking an existing entry. Not clear that this is
2712          * always a win though, and this might just generate a ripple
2713          * effect... Let's just hope VPEs don't migrate too often.
2714          */
2715         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2716                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2717
2718         vpe->vpe_proxy_event = -1;
2719 }
2720
2721 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2722 {
2723         if (!gic_rdists->has_direct_lpi) {
2724                 unsigned long flags;
2725
2726                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2727                 its_vpe_db_proxy_unmap_locked(vpe);
2728                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2729         }
2730 }
2731
2732 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2733 {
2734         /* Already mapped? */
2735         if (vpe->vpe_proxy_event != -1)
2736                 return;
2737
2738         /* This slot was already allocated. Kick the other VPE out. */
2739         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2740                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2741
2742         /* Map the new VPE instead */
2743         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2744         vpe->vpe_proxy_event = vpe_proxy.next_victim;
2745         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2746
2747         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2748         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2749 }
2750
2751 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2752 {
2753         unsigned long flags;
2754         struct its_collection *target_col;
2755
2756         if (gic_rdists->has_direct_lpi) {
2757                 void __iomem *rdbase;
2758
2759                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2760                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2761                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2762                         cpu_relax();
2763
2764                 return;
2765         }
2766
2767         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2768
2769         its_vpe_db_proxy_map_locked(vpe);
2770
2771         target_col = &vpe_proxy.dev->its->collections[to];
2772         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2773         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2774
2775         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2776 }
2777
2778 static int its_vpe_set_affinity(struct irq_data *d,
2779                                 const struct cpumask *mask_val,
2780                                 bool force)
2781 {
2782         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2783         int cpu = cpumask_first(mask_val);
2784
2785         /*
2786          * Changing affinity is mega expensive, so let's be as lazy as
2787          * we can and only do it if we really have to. Also, if mapped
2788          * into the proxy device, we need to move the doorbell
2789          * interrupt to its new location.
2790          */
2791         if (vpe->col_idx != cpu) {
2792                 int from = vpe->col_idx;
2793
2794                 vpe->col_idx = cpu;
2795                 its_send_vmovp(vpe);
2796                 its_vpe_db_proxy_move(vpe, from, cpu);
2797         }
2798
2799         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2800
2801         return IRQ_SET_MASK_OK_DONE;
2802 }
2803
2804 static void its_vpe_schedule(struct its_vpe *vpe)
2805 {
2806         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2807         u64 val;
2808
2809         /* Schedule the VPE */
2810         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2811                 GENMASK_ULL(51, 12);
2812         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2813         val |= GICR_VPROPBASER_RaWb;
2814         val |= GICR_VPROPBASER_InnerShareable;
2815         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2816
2817         val  = virt_to_phys(page_address(vpe->vpt_page)) &
2818                 GENMASK_ULL(51, 16);
2819         val |= GICR_VPENDBASER_RaWaWb;
2820         val |= GICR_VPENDBASER_NonShareable;
2821         /*
2822          * There is no good way of finding out if the pending table is
2823          * empty as we can race against the doorbell interrupt very
2824          * easily. So in the end, vpe->pending_last is only an
2825          * indication that the vcpu has something pending, not one
2826          * that the pending table is empty. A good implementation
2827          * would be able to read its coarse map pretty quickly anyway,
2828          * making this a tolerable issue.
2829          */
2830         val |= GICR_VPENDBASER_PendingLast;
2831         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2832         val |= GICR_VPENDBASER_Valid;
2833         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2834 }
2835
2836 static void its_vpe_deschedule(struct its_vpe *vpe)
2837 {
2838         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2839         u64 val;
2840
2841         val = its_clear_vpend_valid(vlpi_base);
2842
2843         if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2844                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2845                 vpe->idai = false;
2846                 vpe->pending_last = true;
2847         } else {
2848                 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2849                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2850         }
2851 }
2852
2853 static void its_vpe_invall(struct its_vpe *vpe)
2854 {
2855         struct its_node *its;
2856
2857         list_for_each_entry(its, &its_nodes, entry) {
2858                 if (!its->is_v4)
2859                         continue;
2860
2861                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2862                         continue;
2863
2864                 /*
2865                  * Sending a VINVALL to a single ITS is enough, as all
2866                  * we need is to reach the redistributors.
2867                  */
2868                 its_send_vinvall(its, vpe);
2869                 return;
2870         }
2871 }
2872
2873 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2874 {
2875         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2876         struct its_cmd_info *info = vcpu_info;
2877
2878         switch (info->cmd_type) {
2879         case SCHEDULE_VPE:
2880                 its_vpe_schedule(vpe);
2881                 return 0;
2882
2883         case DESCHEDULE_VPE:
2884                 its_vpe_deschedule(vpe);
2885                 return 0;
2886
2887         case INVALL_VPE:
2888                 its_vpe_invall(vpe);
2889                 return 0;
2890
2891         default:
2892                 return -EINVAL;
2893         }
2894 }
2895
2896 static void its_vpe_send_cmd(struct its_vpe *vpe,
2897                              void (*cmd)(struct its_device *, u32))
2898 {
2899         unsigned long flags;
2900
2901         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2902
2903         its_vpe_db_proxy_map_locked(vpe);
2904         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2905
2906         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2907 }
2908
2909 static void its_vpe_send_inv(struct irq_data *d)
2910 {
2911         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2912
2913         if (gic_rdists->has_direct_lpi) {
2914                 void __iomem *rdbase;
2915
2916                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2917                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2918                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2919                         cpu_relax();
2920         } else {
2921                 its_vpe_send_cmd(vpe, its_send_inv);
2922         }
2923 }
2924
2925 static void its_vpe_mask_irq(struct irq_data *d)
2926 {
2927         /*
2928          * We need to unmask the LPI, which is described by the parent
2929          * irq_data. Instead of calling into the parent (which won't
2930          * exactly do the right thing, let's simply use the
2931          * parent_data pointer. Yes, I'm naughty.
2932          */
2933         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2934         its_vpe_send_inv(d);
2935 }
2936
2937 static void its_vpe_unmask_irq(struct irq_data *d)
2938 {
2939         /* Same hack as above... */
2940         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2941         its_vpe_send_inv(d);
2942 }
2943
2944 static int its_vpe_set_irqchip_state(struct irq_data *d,
2945                                      enum irqchip_irq_state which,
2946                                      bool state)
2947 {
2948         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2949
2950         if (which != IRQCHIP_STATE_PENDING)
2951                 return -EINVAL;
2952
2953         if (gic_rdists->has_direct_lpi) {
2954                 void __iomem *rdbase;
2955
2956                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2957                 if (state) {
2958                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2959                 } else {
2960                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2961                         while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2962                                 cpu_relax();
2963                 }
2964         } else {
2965                 if (state)
2966                         its_vpe_send_cmd(vpe, its_send_int);
2967                 else
2968                         its_vpe_send_cmd(vpe, its_send_clear);
2969         }
2970
2971         return 0;
2972 }
2973
2974 static struct irq_chip its_vpe_irq_chip = {
2975         .name                   = "GICv4-vpe",
2976         .irq_mask               = its_vpe_mask_irq,
2977         .irq_unmask             = its_vpe_unmask_irq,
2978         .irq_eoi                = irq_chip_eoi_parent,
2979         .irq_set_affinity       = its_vpe_set_affinity,
2980         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
2981         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
2982 };
2983
2984 static int its_vpe_id_alloc(void)
2985 {
2986         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2987 }
2988
2989 static void its_vpe_id_free(u16 id)
2990 {
2991         ida_simple_remove(&its_vpeid_ida, id);
2992 }
2993
2994 static int its_vpe_init(struct its_vpe *vpe)
2995 {
2996         struct page *vpt_page;
2997         int vpe_id;
2998
2999         /* Allocate vpe_id */
3000         vpe_id = its_vpe_id_alloc();
3001         if (vpe_id < 0)
3002                 return vpe_id;
3003
3004         /* Allocate VPT */
3005         vpt_page = its_allocate_pending_table(GFP_KERNEL);
3006         if (!vpt_page) {
3007                 its_vpe_id_free(vpe_id);
3008                 return -ENOMEM;
3009         }
3010
3011         if (!its_alloc_vpe_table(vpe_id)) {
3012                 its_vpe_id_free(vpe_id);
3013                 its_free_pending_table(vpt_page);
3014                 return -ENOMEM;
3015         }
3016
3017         vpe->vpe_id = vpe_id;
3018         vpe->vpt_page = vpt_page;
3019         vpe->vpe_proxy_event = -1;
3020
3021         return 0;
3022 }
3023
3024 static void its_vpe_teardown(struct its_vpe *vpe)
3025 {
3026         its_vpe_db_proxy_unmap(vpe);
3027         its_vpe_id_free(vpe->vpe_id);
3028         its_free_pending_table(vpe->vpt_page);
3029 }
3030
3031 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3032                                     unsigned int virq,
3033                                     unsigned int nr_irqs)
3034 {
3035         struct its_vm *vm = domain->host_data;
3036         int i;
3037
3038         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3039
3040         for (i = 0; i < nr_irqs; i++) {
3041                 struct irq_data *data = irq_domain_get_irq_data(domain,
3042                                                                 virq + i);
3043                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3044
3045                 BUG_ON(vm != vpe->its_vm);
3046
3047                 clear_bit(data->hwirq, vm->db_bitmap);
3048                 its_vpe_teardown(vpe);
3049                 irq_domain_reset_irq_data(data);
3050         }
3051
3052         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3053                 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3054                 its_free_prop_table(vm->vprop_page);
3055         }
3056 }
3057
3058 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3059                                     unsigned int nr_irqs, void *args)
3060 {
3061         struct its_vm *vm = args;
3062         unsigned long *bitmap;
3063         struct page *vprop_page;
3064         int base, nr_ids, i, err = 0;
3065
3066         BUG_ON(!vm);
3067
3068         bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3069         if (!bitmap)
3070                 return -ENOMEM;
3071
3072         if (nr_ids < nr_irqs) {
3073                 its_lpi_free(bitmap, base, nr_ids);
3074                 return -ENOMEM;
3075         }
3076
3077         vprop_page = its_allocate_prop_table(GFP_KERNEL);
3078         if (!vprop_page) {
3079                 its_lpi_free(bitmap, base, nr_ids);
3080                 return -ENOMEM;
3081         }
3082
3083         vm->db_bitmap = bitmap;
3084         vm->db_lpi_base = base;
3085         vm->nr_db_lpis = nr_ids;
3086         vm->vprop_page = vprop_page;
3087
3088         for (i = 0; i < nr_irqs; i++) {
3089                 vm->vpes[i]->vpe_db_lpi = base + i;
3090                 err = its_vpe_init(vm->vpes[i]);
3091                 if (err)
3092                         break;
3093                 err = its_irq_gic_domain_alloc(domain, virq + i,
3094                                                vm->vpes[i]->vpe_db_lpi);
3095                 if (err)
3096                         break;
3097                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3098                                               &its_vpe_irq_chip, vm->vpes[i]);
3099                 set_bit(i, bitmap);
3100         }
3101
3102         if (err) {
3103                 if (i > 0)
3104                         its_vpe_irq_domain_free(domain, virq, i - 1);
3105
3106                 its_lpi_free(bitmap, base, nr_ids);
3107                 its_free_prop_table(vprop_page);
3108         }
3109
3110         return err;
3111 }
3112
3113 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3114                                        struct irq_data *d, bool reserve)
3115 {
3116         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3117         struct its_node *its;
3118
3119         /* If we use the list map, we issue VMAPP on demand... */
3120         if (its_list_map)
3121                 return 0;
3122
3123         /* Map the VPE to the first possible CPU */
3124         vpe->col_idx = cpumask_first(cpu_online_mask);
3125
3126         list_for_each_entry(its, &its_nodes, entry) {
3127                 if (!its->is_v4)
3128                         continue;
3129
3130                 its_send_vmapp(its, vpe, true);
3131                 its_send_vinvall(its, vpe);
3132         }
3133
3134         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3135
3136         return 0;
3137 }
3138
3139 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3140                                           struct irq_data *d)
3141 {
3142         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3143         struct its_node *its;
3144
3145         /*
3146          * If we use the list map, we unmap the VPE once no VLPIs are
3147          * associated with the VM.
3148          */
3149         if (its_list_map)
3150                 return;
3151
3152         list_for_each_entry(its, &its_nodes, entry) {
3153                 if (!its->is_v4)
3154                         continue;
3155
3156                 its_send_vmapp(its, vpe, false);
3157         }
3158 }
3159
3160 static const struct irq_domain_ops its_vpe_domain_ops = {
3161         .alloc                  = its_vpe_irq_domain_alloc,
3162         .free                   = its_vpe_irq_domain_free,
3163         .activate               = its_vpe_irq_domain_activate,
3164         .deactivate             = its_vpe_irq_domain_deactivate,
3165 };
3166
3167 static int its_force_quiescent(void __iomem *base)
3168 {
3169         u32 count = 1000000;    /* 1s */
3170         u32 val;
3171
3172         val = readl_relaxed(base + GITS_CTLR);
3173         /*
3174          * GIC architecture specification requires the ITS to be both
3175          * disabled and quiescent for writes to GITS_BASER<n> or
3176          * GITS_CBASER to not have UNPREDICTABLE results.
3177          */
3178         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3179                 return 0;
3180
3181         /* Disable the generation of all interrupts to this ITS */
3182         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3183         writel_relaxed(val, base + GITS_CTLR);
3184
3185         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3186         while (1) {
3187                 val = readl_relaxed(base + GITS_CTLR);
3188                 if (val & GITS_CTLR_QUIESCENT)
3189                         return 0;
3190
3191                 count--;
3192                 if (!count)
3193                         return -EBUSY;
3194
3195                 cpu_relax();
3196                 udelay(1);
3197         }
3198 }
3199
3200 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3201 {
3202         struct its_node *its = data;
3203
3204         /* erratum 22375: only alloc 8MB table size */
3205         its->device_ids = 0x14;         /* 20 bits, 8MB */
3206         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3207
3208         return true;
3209 }
3210
3211 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3212 {
3213         struct its_node *its = data;
3214
3215         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3216
3217         return true;
3218 }
3219
3220 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3221 {
3222         struct its_node *its = data;
3223
3224         /* On QDF2400, the size of the ITE is 16Bytes */
3225         its->ite_size = 16;
3226
3227         return true;
3228 }
3229
3230 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3231 {
3232         struct its_node *its = its_dev->its;
3233
3234         /*
3235          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3236          * which maps 32-bit writes targeted at a separate window of
3237          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3238          * with device ID taken from bits [device_id_bits + 1:2] of
3239          * the window offset.
3240          */
3241         return its->pre_its_base + (its_dev->device_id << 2);
3242 }
3243
3244 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3245 {
3246         struct its_node *its = data;
3247         u32 pre_its_window[2];
3248         u32 ids;
3249
3250         if (!fwnode_property_read_u32_array(its->fwnode_handle,
3251                                            "socionext,synquacer-pre-its",
3252                                            pre_its_window,
3253                                            ARRAY_SIZE(pre_its_window))) {
3254
3255                 its->pre_its_base = pre_its_window[0];
3256                 its->get_msi_base = its_irq_get_msi_base_pre_its;
3257
3258                 ids = ilog2(pre_its_window[1]) - 2;
3259                 if (its->device_ids > ids)
3260                         its->device_ids = ids;
3261
3262                 /* the pre-ITS breaks isolation, so disable MSI remapping */
3263                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3264                 return true;
3265         }
3266         return false;
3267 }
3268
3269 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3270 {
3271         struct its_node *its = data;
3272
3273         /*
3274          * Hip07 insists on using the wrong address for the VLPI
3275          * page. Trick it into doing the right thing...
3276          */
3277         its->vlpi_redist_offset = SZ_128K;
3278         return true;
3279 }
3280
3281 static const struct gic_quirk its_quirks[] = {
3282 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3283         {
3284                 .desc   = "ITS: Cavium errata 22375, 24313",
3285                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
3286                 .mask   = 0xffff0fff,
3287                 .init   = its_enable_quirk_cavium_22375,
3288         },
3289 #endif
3290 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3291         {
3292                 .desc   = "ITS: Cavium erratum 23144",
3293                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
3294                 .mask   = 0xffff0fff,
3295                 .init   = its_enable_quirk_cavium_23144,
3296         },
3297 #endif
3298 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3299         {
3300                 .desc   = "ITS: QDF2400 erratum 0065",
3301                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
3302                 .mask   = 0xffffffff,
3303                 .init   = its_enable_quirk_qdf2400_e0065,
3304         },
3305 #endif
3306 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3307         {
3308                 /*
3309                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3310                  * implementation, but with a 'pre-ITS' added that requires
3311                  * special handling in software.
3312                  */
3313                 .desc   = "ITS: Socionext Synquacer pre-ITS",
3314                 .iidr   = 0x0001143b,
3315                 .mask   = 0xffffffff,
3316                 .init   = its_enable_quirk_socionext_synquacer,
3317         },
3318 #endif
3319 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3320         {
3321                 .desc   = "ITS: Hip07 erratum 161600802",
3322                 .iidr   = 0x00000004,
3323                 .mask   = 0xffffffff,
3324                 .init   = its_enable_quirk_hip07_161600802,
3325         },
3326 #endif
3327         {
3328         }
3329 };
3330
3331 static void its_enable_quirks(struct its_node *its)
3332 {
3333         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3334
3335         gic_enable_quirks(iidr, its_quirks, its);
3336 }
3337
3338 static int its_save_disable(void)
3339 {
3340         struct its_node *its;
3341         int err = 0;
3342
3343         raw_spin_lock(&its_lock);
3344         list_for_each_entry(its, &its_nodes, entry) {
3345                 void __iomem *base;
3346
3347                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3348                         continue;
3349
3350                 base = its->base;
3351                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3352                 err = its_force_quiescent(base);
3353                 if (err) {
3354                         pr_err("ITS@%pa: failed to quiesce: %d\n",
3355                                &its->phys_base, err);
3356                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3357                         goto err;
3358                 }
3359
3360                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3361         }
3362
3363 err:
3364         if (err) {
3365                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3366                         void __iomem *base;
3367
3368                         if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3369                                 continue;
3370
3371                         base = its->base;
3372                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3373                 }
3374         }
3375         raw_spin_unlock(&its_lock);
3376
3377         return err;
3378 }
3379
3380 static void its_restore_enable(void)
3381 {
3382         struct its_node *its;
3383         int ret;
3384
3385         raw_spin_lock(&its_lock);
3386         list_for_each_entry(its, &its_nodes, entry) {
3387                 void __iomem *base;
3388                 int i;
3389
3390                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3391                         continue;
3392
3393                 base = its->base;
3394
3395                 /*
3396                  * Make sure that the ITS is disabled. If it fails to quiesce,
3397                  * don't restore it since writing to CBASER or BASER<n>
3398                  * registers is undefined according to the GIC v3 ITS
3399                  * Specification.
3400                  */
3401                 ret = its_force_quiescent(base);
3402                 if (ret) {
3403                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3404                                &its->phys_base, ret);
3405                         continue;
3406                 }
3407
3408                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3409
3410                 /*
3411                  * Writing CBASER resets CREADR to 0, so make CWRITER and
3412                  * cmd_write line up with it.
3413                  */
3414                 its->cmd_write = its->cmd_base;
3415                 gits_write_cwriter(0, base + GITS_CWRITER);
3416
3417                 /* Restore GITS_BASER from the value cache. */
3418                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3419                         struct its_baser *baser = &its->tables[i];
3420
3421                         if (!(baser->val & GITS_BASER_VALID))
3422                                 continue;
3423
3424                         its_write_baser(its, baser, baser->val);
3425                 }
3426                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3427
3428                 /*
3429                  * Reinit the collection if it's stored in the ITS. This is
3430                  * indicated by the col_id being less than the HCC field.
3431                  * CID < HCC as specified in the GIC v3 Documentation.
3432                  */
3433                 if (its->collections[smp_processor_id()].col_id <
3434                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3435                         its_cpu_init_collection(its);
3436         }
3437         raw_spin_unlock(&its_lock);
3438 }
3439
3440 static struct syscore_ops its_syscore_ops = {
3441         .suspend = its_save_disable,
3442         .resume = its_restore_enable,
3443 };
3444
3445 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3446 {
3447         struct irq_domain *inner_domain;
3448         struct msi_domain_info *info;
3449
3450         info = kzalloc(sizeof(*info), GFP_KERNEL);
3451         if (!info)
3452                 return -ENOMEM;
3453
3454         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3455         if (!inner_domain) {
3456                 kfree(info);
3457                 return -ENOMEM;
3458         }
3459
3460         inner_domain->parent = its_parent;
3461         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3462         inner_domain->flags |= its->msi_domain_flags;
3463         info->ops = &its_msi_domain_ops;
3464         info->data = its;
3465         inner_domain->host_data = info;
3466
3467         return 0;
3468 }
3469
3470 static int its_init_vpe_domain(void)
3471 {
3472         struct its_node *its;
3473         u32 devid;
3474         int entries;
3475
3476         if (gic_rdists->has_direct_lpi) {
3477                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3478                 return 0;
3479         }
3480
3481         /* Any ITS will do, even if not v4 */
3482         its = list_first_entry(&its_nodes, struct its_node, entry);
3483
3484         entries = roundup_pow_of_two(nr_cpu_ids);
3485         vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3486                                  GFP_KERNEL);
3487         if (!vpe_proxy.vpes) {
3488                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3489                 return -ENOMEM;
3490         }
3491
3492         /* Use the last possible DevID */
3493         devid = GENMASK(its->device_ids - 1, 0);
3494         vpe_proxy.dev = its_create_device(its, devid, entries, false);
3495         if (!vpe_proxy.dev) {
3496                 kfree(vpe_proxy.vpes);
3497                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3498                 return -ENOMEM;
3499         }
3500
3501         BUG_ON(entries > vpe_proxy.dev->nr_ites);
3502
3503         raw_spin_lock_init(&vpe_proxy.lock);
3504         vpe_proxy.next_victim = 0;
3505         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3506                 devid, vpe_proxy.dev->nr_ites);
3507
3508         return 0;
3509 }
3510
3511 static int __init its_compute_its_list_map(struct resource *res,
3512                                            void __iomem *its_base)
3513 {
3514         int its_number;
3515         u32 ctlr;
3516
3517         /*
3518          * This is assumed to be done early enough that we're
3519          * guaranteed to be single-threaded, hence no
3520          * locking. Should this change, we should address
3521          * this.
3522          */
3523         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3524         if (its_number >= GICv4_ITS_LIST_MAX) {
3525                 pr_err("ITS@%pa: No ITSList entry available!\n",
3526                        &res->start);
3527                 return -EINVAL;
3528         }
3529
3530         ctlr = readl_relaxed(its_base + GITS_CTLR);
3531         ctlr &= ~GITS_CTLR_ITS_NUMBER;
3532         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3533         writel_relaxed(ctlr, its_base + GITS_CTLR);
3534         ctlr = readl_relaxed(its_base + GITS_CTLR);
3535         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3536                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3537                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3538         }
3539
3540         if (test_and_set_bit(its_number, &its_list_map)) {
3541                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3542                        &res->start, its_number);
3543                 return -EINVAL;
3544         }
3545
3546         return its_number;
3547 }
3548
3549 static int __init its_probe_one(struct resource *res,
3550                                 struct fwnode_handle *handle, int numa_node)
3551 {
3552         struct its_node *its;
3553         void __iomem *its_base;
3554         u32 val, ctlr;
3555         u64 baser, tmp, typer;
3556         struct page *page;
3557         int err;
3558
3559         its_base = ioremap(res->start, resource_size(res));
3560         if (!its_base) {
3561                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3562                 return -ENOMEM;
3563         }
3564
3565         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3566         if (val != 0x30 && val != 0x40) {
3567                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3568                 err = -ENODEV;
3569                 goto out_unmap;
3570         }
3571
3572         err = its_force_quiescent(its_base);
3573         if (err) {
3574                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3575                 goto out_unmap;
3576         }
3577
3578         pr_info("ITS %pR\n", res);
3579
3580         its = kzalloc(sizeof(*its), GFP_KERNEL);
3581         if (!its) {
3582                 err = -ENOMEM;
3583                 goto out_unmap;
3584         }
3585
3586         raw_spin_lock_init(&its->lock);
3587         mutex_init(&its->dev_alloc_lock);
3588         INIT_LIST_HEAD(&its->entry);
3589         INIT_LIST_HEAD(&its->its_device_list);
3590         typer = gic_read_typer(its_base + GITS_TYPER);
3591         its->base = its_base;
3592         its->phys_base = res->start;
3593         its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3594         its->device_ids = GITS_TYPER_DEVBITS(typer);
3595         its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3596         if (its->is_v4) {
3597                 if (!(typer & GITS_TYPER_VMOVP)) {
3598                         err = its_compute_its_list_map(res, its_base);
3599                         if (err < 0)
3600                                 goto out_free_its;
3601
3602                         its->list_nr = err;
3603
3604                         pr_info("ITS@%pa: Using ITS number %d\n",
3605                                 &res->start, err);
3606                 } else {
3607                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3608                 }
3609         }
3610
3611         its->numa_node = numa_node;
3612
3613         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3614                                 get_order(ITS_CMD_QUEUE_SZ));
3615         if (!page) {
3616                 err = -ENOMEM;
3617                 goto out_free_its;
3618         }
3619         its->cmd_base = (void *)page_address(page);
3620         its->cmd_write = its->cmd_base;
3621         its->fwnode_handle = handle;
3622         its->get_msi_base = its_irq_get_msi_base;
3623         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3624
3625         its_enable_quirks(its);
3626
3627         err = its_alloc_tables(its);
3628         if (err)
3629                 goto out_free_cmd;
3630
3631         err = its_alloc_collections(its);
3632         if (err)
3633                 goto out_free_tables;
3634
3635         baser = (virt_to_phys(its->cmd_base)    |
3636                  GITS_CBASER_RaWaWb             |
3637                  GITS_CBASER_InnerShareable     |
3638                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3639                  GITS_CBASER_VALID);
3640
3641         gits_write_cbaser(baser, its->base + GITS_CBASER);
3642         tmp = gits_read_cbaser(its->base + GITS_CBASER);
3643
3644         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3645                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3646                         /*
3647                          * The HW reports non-shareable, we must
3648                          * remove the cacheability attributes as
3649                          * well.
3650                          */
3651                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3652                                    GITS_CBASER_CACHEABILITY_MASK);
3653                         baser |= GITS_CBASER_nC;
3654                         gits_write_cbaser(baser, its->base + GITS_CBASER);
3655                 }
3656                 pr_info("ITS: using cache flushing for cmd queue\n");
3657                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3658         }
3659
3660         gits_write_cwriter(0, its->base + GITS_CWRITER);
3661         ctlr = readl_relaxed(its->base + GITS_CTLR);
3662         ctlr |= GITS_CTLR_ENABLE;
3663         if (its->is_v4)
3664                 ctlr |= GITS_CTLR_ImDe;
3665         writel_relaxed(ctlr, its->base + GITS_CTLR);
3666
3667         if (GITS_TYPER_HCC(typer))
3668                 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3669
3670         err = its_init_domain(handle, its);
3671         if (err)
3672                 goto out_free_tables;
3673
3674         raw_spin_lock(&its_lock);
3675         list_add(&its->entry, &its_nodes);
3676         raw_spin_unlock(&its_lock);
3677
3678         return 0;
3679
3680 out_free_tables:
3681         its_free_tables(its);
3682 out_free_cmd:
3683         free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3684 out_free_its:
3685         kfree(its);
3686 out_unmap:
3687         iounmap(its_base);
3688         pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3689         return err;
3690 }
3691
3692 static bool gic_rdists_supports_plpis(void)
3693 {
3694         return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3695 }
3696
3697 static int redist_disable_lpis(void)
3698 {
3699         void __iomem *rbase = gic_data_rdist_rd_base();
3700         u64 timeout = USEC_PER_SEC;
3701         u64 val;
3702
3703         if (!gic_rdists_supports_plpis()) {
3704                 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3705                 return -ENXIO;
3706         }
3707
3708         val = readl_relaxed(rbase + GICR_CTLR);
3709         if (!(val & GICR_CTLR_ENABLE_LPIS))
3710                 return 0;
3711
3712         /*
3713          * If coming via a CPU hotplug event, we don't need to disable
3714          * LPIs before trying to re-enable them. They are already
3715          * configured and all is well in the world.
3716          *
3717          * If running with preallocated tables, there is nothing to do.
3718          */
3719         if (gic_data_rdist()->lpi_enabled ||
3720             (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3721                 return 0;
3722
3723         /*
3724          * From that point on, we only try to do some damage control.
3725          */
3726         pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3727                 smp_processor_id());
3728         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3729
3730         /* Disable LPIs */
3731         val &= ~GICR_CTLR_ENABLE_LPIS;
3732         writel_relaxed(val, rbase + GICR_CTLR);
3733
3734         /* Make sure any change to GICR_CTLR is observable by the GIC */
3735         dsb(sy);
3736
3737         /*
3738          * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3739          * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3740          * Error out if we time out waiting for RWP to clear.
3741          */
3742         while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3743                 if (!timeout) {
3744                         pr_err("CPU%d: Timeout while disabling LPIs\n",
3745                                smp_processor_id());
3746                         return -ETIMEDOUT;
3747                 }
3748                 udelay(1);
3749                 timeout--;
3750         }
3751
3752         /*
3753          * After it has been written to 1, it is IMPLEMENTATION
3754          * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3755          * cleared to 0. Error out if clearing the bit failed.
3756          */
3757         if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3758                 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3759                 return -EBUSY;
3760         }
3761
3762         return 0;
3763 }
3764
3765 int its_cpu_init(void)
3766 {
3767         if (!list_empty(&its_nodes)) {
3768                 int ret;
3769
3770                 ret = redist_disable_lpis();
3771                 if (ret)
3772                         return ret;
3773
3774                 its_cpu_init_lpis();
3775                 its_cpu_init_collections();
3776         }
3777
3778         return 0;
3779 }
3780
3781 static const struct of_device_id its_device_id[] = {
3782         {       .compatible     = "arm,gic-v3-its",     },
3783         {},
3784 };
3785
3786 static int __init its_of_probe(struct device_node *node)
3787 {
3788         struct device_node *np;
3789         struct resource res;
3790
3791         for (np = of_find_matching_node(node, its_device_id); np;
3792              np = of_find_matching_node(np, its_device_id)) {
3793                 if (!of_device_is_available(np))
3794                         continue;
3795                 if (!of_property_read_bool(np, "msi-controller")) {
3796                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3797                                 np);
3798                         continue;
3799                 }
3800
3801                 if (of_address_to_resource(np, 0, &res)) {
3802                         pr_warn("%pOF: no regs?\n", np);
3803                         continue;
3804                 }
3805
3806                 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3807         }
3808         return 0;
3809 }
3810
3811 #ifdef CONFIG_ACPI
3812
3813 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3814
3815 #ifdef CONFIG_ACPI_NUMA
3816 struct its_srat_map {
3817         /* numa node id */
3818         u32     numa_node;
3819         /* GIC ITS ID */
3820         u32     its_id;
3821 };
3822
3823 static struct its_srat_map *its_srat_maps __initdata;
3824 static int its_in_srat __initdata;
3825
3826 static int __init acpi_get_its_numa_node(u32 its_id)
3827 {
3828         int i;
3829
3830         for (i = 0; i < its_in_srat; i++) {
3831                 if (its_id == its_srat_maps[i].its_id)
3832                         return its_srat_maps[i].numa_node;
3833         }
3834         return NUMA_NO_NODE;
3835 }
3836
3837 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3838                                           const unsigned long end)
3839 {
3840         return 0;
3841 }
3842
3843 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3844                          const unsigned long end)
3845 {
3846         int node;
3847         struct acpi_srat_gic_its_affinity *its_affinity;
3848
3849         its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3850         if (!its_affinity)
3851                 return -EINVAL;
3852
3853         if (its_affinity->header.length < sizeof(*its_affinity)) {
3854                 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3855                         its_affinity->header.length);
3856                 return -EINVAL;
3857         }
3858
3859         node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3860
3861         if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3862                 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3863                 return 0;
3864         }
3865
3866         its_srat_maps[its_in_srat].numa_node = node;
3867         its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3868         its_in_srat++;
3869         pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3870                 its_affinity->proximity_domain, its_affinity->its_id, node);
3871
3872         return 0;
3873 }
3874
3875 static void __init acpi_table_parse_srat_its(void)
3876 {
3877         int count;
3878
3879         count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3880                         sizeof(struct acpi_table_srat),
3881                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3882                         gic_acpi_match_srat_its, 0);
3883         if (count <= 0)
3884                 return;
3885
3886         its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3887                                       GFP_KERNEL);
3888         if (!its_srat_maps) {
3889                 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3890                 return;
3891         }
3892
3893         acpi_table_parse_entries(ACPI_SIG_SRAT,
3894                         sizeof(struct acpi_table_srat),
3895                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3896                         gic_acpi_parse_srat_its, 0);
3897 }
3898
3899 /* free the its_srat_maps after ITS probing */
3900 static void __init acpi_its_srat_maps_free(void)
3901 {
3902         kfree(its_srat_maps);
3903 }
3904 #else
3905 static void __init acpi_table_parse_srat_its(void)      { }
3906 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3907 static void __init acpi_its_srat_maps_free(void) { }
3908 #endif
3909
3910 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3911                                           const unsigned long end)
3912 {
3913         struct acpi_madt_generic_translator *its_entry;
3914         struct fwnode_handle *dom_handle;
3915         struct resource res;
3916         int err;
3917
3918         its_entry = (struct acpi_madt_generic_translator *)header;
3919         memset(&res, 0, sizeof(res));
3920         res.start = its_entry->base_address;
3921         res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3922         res.flags = IORESOURCE_MEM;
3923
3924         dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3925         if (!dom_handle) {
3926                 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3927                        &res.start);
3928                 return -ENOMEM;
3929         }
3930
3931         err = iort_register_domain_token(its_entry->translation_id, res.start,
3932                                          dom_handle);
3933         if (err) {
3934                 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3935                        &res.start, its_entry->translation_id);
3936                 goto dom_err;
3937         }
3938
3939         err = its_probe_one(&res, dom_handle,
3940                         acpi_get_its_numa_node(its_entry->translation_id));
3941         if (!err)
3942                 return 0;
3943
3944         iort_deregister_domain_token(its_entry->translation_id);
3945 dom_err:
3946         irq_domain_free_fwnode(dom_handle);
3947         return err;
3948 }
3949
3950 static void __init its_acpi_probe(void)
3951 {
3952         acpi_table_parse_srat_its();
3953         acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3954                               gic_acpi_parse_madt_its, 0);
3955         acpi_its_srat_maps_free();
3956 }
3957 #else
3958 static void __init its_acpi_probe(void) { }
3959 #endif
3960
3961 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3962                     struct irq_domain *parent_domain)
3963 {
3964         struct device_node *of_node;
3965         struct its_node *its;
3966         bool has_v4 = false;
3967         int err;
3968
3969         its_parent = parent_domain;
3970         of_node = to_of_node(handle);
3971         if (of_node)
3972                 its_of_probe(of_node);
3973         else
3974                 its_acpi_probe();
3975
3976         if (list_empty(&its_nodes)) {
3977                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3978                 return -ENXIO;
3979         }
3980
3981         gic_rdists = rdists;
3982
3983         err = allocate_lpi_tables();
3984         if (err)
3985                 return err;
3986
3987         list_for_each_entry(its, &its_nodes, entry)
3988                 has_v4 |= its->is_v4;
3989
3990         if (has_v4 & rdists->has_vlpis) {
3991                 if (its_init_vpe_domain() ||
3992                     its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3993                         rdists->has_vlpis = false;
3994                         pr_err("ITS: Disabling GICv4 support\n");
3995                 }
3996         }
3997
3998         register_syscore_ops(&its_syscore_ops);
3999
4000         return 0;
4001 }