drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <drm/drm_atomic.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_atomic_uapi.h>
  35 #include <drm/drm_print.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <linux/clk.h>
  38 #include <drm/drm_fb_cma_helper.h>
  39 #include <linux/component.h>
  40 #include <linux/of_device.h>
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc_state {
  45         struct drm_crtc_state base;
  46         /* Dlist area for this CRTC configuration. */
  47         struct drm_mm_node mm;
  48         bool feed_txp;
  49         bool txp_armed;
  50
  51         struct {
  52                 unsigned int left;
  53                 unsigned int right;
  54                 unsigned int top;
  55                 unsigned int bottom;
  56         } margins;
  57 };
  58
  59 static inline struct vc4_crtc_state *
  60 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  61 {
  62         return (struct vc4_crtc_state *)crtc_state;
  63 }
  64
  65 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  66 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  67
  68 static const struct debugfs_reg32 crtc_regs[] = {
  69         VC4_REG32(PV_CONTROL),
  70         VC4_REG32(PV_V_CONTROL),
  71         VC4_REG32(PV_VSYNCD_EVEN),
  72         VC4_REG32(PV_HORZA),
  73         VC4_REG32(PV_HORZB),
  74         VC4_REG32(PV_VERTA),
  75         VC4_REG32(PV_VERTB),
  76         VC4_REG32(PV_VERTA_EVEN),
  77         VC4_REG32(PV_VERTB_EVEN),
  78         VC4_REG32(PV_INTEN),
  79         VC4_REG32(PV_INTSTAT),
  80         VC4_REG32(PV_STAT),
  81         VC4_REG32(PV_HACT_ACT),
  82 };
  83
  84 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
  85                              bool in_vblank_irq, int *vpos, int *hpos,
  86                              ktime_t *stime, ktime_t *etime,
  87                              const struct drm_display_mode *mode)
  88 {
  89         struct vc4_dev *vc4 = to_vc4_dev(dev);
  90         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
  91         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  92         u32 val;
  93         int fifo_lines;
  94         int vblank_lines;
  95         bool ret = false;
  96
  97         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
  98
  99         /* Get optional system timestamp before query. */
 100         if (stime)
 101                 *stime = ktime_get();
 102
 103         /*
 104          * Read vertical scanline which is currently composed for our
 105          * pixelvalve by the HVS, and also the scaler status.
 106          */
 107         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 108
 109         /* Get optional system timestamp after query. */
 110         if (etime)
 111                 *etime = ktime_get();
 112
 113         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 114
 115         /* Vertical position of hvs composed scanline. */
 116         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 117         *hpos = 0;
 118
 119         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 120                 *vpos /= 2;
 121
 122                 /* Use hpos to correct for field offset in interlaced mode. */
 123                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 124                         *hpos += mode->crtc_htotal / 2;
 125         }
 126
 127         /* This is the offset we need for translating hvs -> pv scanout pos. */
 128         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 129
 130         if (fifo_lines > 0)
 131                 ret = true;
 132
 133         /* HVS more than fifo_lines into frame for compositing? */
 134         if (*vpos > fifo_lines) {
 135                 /*
 136                  * We are in active scanout and can get some meaningful results
 137                  * from HVS. The actual PV scanout can not trail behind more
 138                  * than fifo_lines as that is the fifo's capacity. Assume that
 139                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 140                  * refilling the fifo and PV consuming from the fifo, ie.
 141                  * whenever the PV consumes and frees up a scanline in the
 142                  * fifo, the HVS will immediately refill it, therefore
 143                  * incrementing vpos. Therefore we choose HVS read position -
 144                  * fifo size in scanlines as a estimate of the real scanout
 145                  * position of the PV.
 146                  */
 147                 *vpos -= fifo_lines + 1;
 148
 149                 return ret;
 150         }
 151
 152         /*
 153          * Less: This happens when we are in vblank and the HVS, after getting
 154          * the VSTART restart signal from the PV, just started refilling its
 155          * fifo with new lines from the top-most lines of the new framebuffers.
 156          * The PV does not scan out in vblank, so does not remove lines from
 157          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 158          * We can't get meaningful readings wrt. scanline position of the PV
 159          * and need to make things up in a approximative but consistent way.
 160          */
 161         vblank_lines = mode->vtotal - mode->vdisplay;
 162
 163         if (in_vblank_irq) {
 164                 /*
 165                  * Assume the irq handler got called close to first
 166                  * line of vblank, so PV has about a full vblank
 167                  * scanlines to go, and as a base timestamp use the
 168                  * one taken at entry into vblank irq handler, so it
 169                  * is not affected by random delays due to lock
 170                  * contention on event_lock or vblank_time lock in
 171                  * the core.
 172                  */
 173                 *vpos = -vblank_lines;
 174
 175                 if (stime)
 176                         *stime = vc4_crtc->t_vblank;
 177                 if (etime)
 178                         *etime = vc4_crtc->t_vblank;
 179
 180                 /*
 181                  * If the HVS fifo is not yet full then we know for certain
 182                  * we are at the very beginning of vblank, as the hvs just
 183                  * started refilling, and the stime and etime timestamps
 184                  * truly correspond to start of vblank.
 185                  *
 186                  * Unfortunately there's no way to report this to upper levels
 187                  * and make it more useful.
 188                  */
 189         } else {
 190                 /*
 191                  * No clue where we are inside vblank. Return a vpos of zero,
 192                  * which will cause calling code to just return the etime
 193                  * timestamp uncorrected. At least this is no worse than the
 194                  * standard fallback.
 195                  */
 196                 *vpos = 0;
 197         }
 198
 199         return ret;
 200 }
 201
 202 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 203 {
 204         drm_crtc_cleanup(crtc);
 205 }
 206
 207 static void
 208 vc4_crtc_lut_load(struct drm_crtc *crtc)
 209 {
 210         struct drm_device *dev = crtc->dev;
 211         struct vc4_dev *vc4 = to_vc4_dev(dev);
 212         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 213         u32 i;
 214
 215         /* The LUT memory is laid out with each HVS channel in order,
 216          * each of which takes 256 writes for R, 256 for G, then 256
 217          * for B.
 218          */
 219         HVS_WRITE(SCALER_GAMADDR,
 220                   SCALER_GAMADDR_AUTOINC |
 221                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 222
 223         for (i = 0; i < crtc->gamma_size; i++)
 224                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 225         for (i = 0; i < crtc->gamma_size; i++)
 226                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 227         for (i = 0; i < crtc->gamma_size; i++)
 228                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 229 }
 230
 231 static void
 232 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 233 {
 234         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 235         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 236         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 237         u32 i;
 238
 239         for (i = 0; i < length; i++) {
 240                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 241                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 242                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 243         }
 244
 245         vc4_crtc_lut_load(crtc);
 246 }
 247
 248 static u32 vc4_get_fifo_full_level(u32 format)
 249 {
 250         static const u32 fifo_len_bytes = 64;
 251         static const u32 hvs_latency_pix = 6;
 252
 253         switch (format) {
 254         case PV_CONTROL_FORMAT_DSIV_16:
 255         case PV_CONTROL_FORMAT_DSIC_16:
 256                 return fifo_len_bytes - 2 * hvs_latency_pix;
 257         case PV_CONTROL_FORMAT_DSIV_18:
 258                 return fifo_len_bytes - 14;
 259         case PV_CONTROL_FORMAT_24:
 260         case PV_CONTROL_FORMAT_DSIV_24:
 261         default:
 262                 return fifo_len_bytes - 3 * hvs_latency_pix;
 263         }
 264 }
 265
 266 /*
 267  * Returns the encoder attached to the CRTC.
 268  *
 269  * VC4 can only scan out to one encoder at a time, while the DRM core
 270  * allows drivers to push pixels to more than one encoder from the
 271  * same CRTC.
 272  */
 273 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 274 {
 275         struct drm_connector *connector;
 276         struct drm_connector_list_iter conn_iter;
 277
 278         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 279         drm_for_each_connector_iter(connector, &conn_iter) {
 280                 if (connector->state->crtc == crtc) {
 281                         drm_connector_list_iter_end(&conn_iter);
 282                         return connector->encoder;
 283                 }
 284         }
 285         drm_connector_list_iter_end(&conn_iter);
 286
 287         return NULL;
 288 }
 289
 290 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 291 {
 292         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 293         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 294         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 295         struct drm_crtc_state *state = crtc->state;
 296         struct drm_display_mode *mode = &state->adjusted_mode;
 297         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 298         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 299         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 300                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 301         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 302
 303         /* Reset the PV fifo. */
 304         CRTC_WRITE(PV_CONTROL, 0);
 305         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 306         CRTC_WRITE(PV_CONTROL, 0);
 307
 308         CRTC_WRITE(PV_HORZA,
 309                    VC4_SET_FIELD((mode->htotal -
 310                                   mode->hsync_end) * pixel_rep,
 311                                  PV_HORZA_HBP) |
 312                    VC4_SET_FIELD((mode->hsync_end -
 313                                   mode->hsync_start) * pixel_rep,
 314                                  PV_HORZA_HSYNC));
 315         CRTC_WRITE(PV_HORZB,
 316                    VC4_SET_FIELD((mode->hsync_start -
 317                                   mode->hdisplay) * pixel_rep,
 318                                  PV_HORZB_HFP) |
 319                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 320
 321         CRTC_WRITE(PV_VERTA,
 322                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 323                                  PV_VERTA_VBP) |
 324                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 325                                  PV_VERTA_VSYNC));
 326         CRTC_WRITE(PV_VERTB,
 327                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 328                                  PV_VERTB_VFP) |
 329                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 330
 331         if (interlace) {
 332                 CRTC_WRITE(PV_VERTA_EVEN,
 333                            VC4_SET_FIELD(mode->crtc_vtotal -
 334                                          mode->crtc_vsync_end - 1,
 335                                          PV_VERTA_VBP) |
 336                            VC4_SET_FIELD(mode->crtc_vsync_end -
 337                                          mode->crtc_vsync_start,
 338                                          PV_VERTA_VSYNC));
 339                 CRTC_WRITE(PV_VERTB_EVEN,
 340                            VC4_SET_FIELD(mode->crtc_vsync_start -
 341                                          mode->crtc_vdisplay,
 342                                          PV_VERTB_VFP) |
 343                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 344
 345                 /* We set up first field even mode for HDMI.  VEC's
 346                  * NTSC mode would want first field odd instead, once
 347                  * we support it (to do so, set ODD_FIRST and put the
 348                  * delay in VSYNCD_EVEN instead).
 349                  */
 350                 CRTC_WRITE(PV_V_CONTROL,
 351                            PV_VCONTROL_CONTINUOUS |
 352                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 353                            PV_VCONTROL_INTERLACE |
 354                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 355                                          PV_VCONTROL_ODD_DELAY));
 356                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 357         } else {
 358                 CRTC_WRITE(PV_V_CONTROL,
 359                            PV_VCONTROL_CONTINUOUS |
 360                            (is_dsi ? PV_VCONTROL_DSI : 0));
 361         }
 362
 363         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 364
 365         CRTC_WRITE(PV_CONTROL,
 366                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 367                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 368                                  PV_CONTROL_FIFO_LEVEL) |
 369                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 370                    PV_CONTROL_CLR_AT_START |
 371                    PV_CONTROL_TRIGGER_UNDERFLOW |
 372                    PV_CONTROL_WAIT_HSTART |
 373                    VC4_SET_FIELD(vc4_encoder->clock_select,
 374                                  PV_CONTROL_CLK_SELECT) |
 375                    PV_CONTROL_FIFO_CLR |
 376                    PV_CONTROL_EN);
 377 }
 378
 379 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         struct vc4_dev *vc4 = to_vc4_dev(dev);
 383         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 384         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 385         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 386         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 387         bool debug_dump_regs = false;
 388
 389         if (debug_dump_regs) {
 390                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 391                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 392                          drm_crtc_index(crtc));
 393                 drm_print_regset32(&p, &vc4_crtc->regset);
 394         }
 395
 396         if (vc4_crtc->channel == 2) {
 397                 u32 dispctrl;
 398                 u32 dsp3_mux;
 399
 400                 /*
 401                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 402                  * FIFO X'.
 403                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 404                  *
 405                  * DSP3 is connected to FIFO2 unless the transposer is
 406                  * enabled. In this case, FIFO 2 is directly accessed by the
 407                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 408                  * route.
 409                  */
 410                 if (vc4_state->feed_txp)
 411                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 412                 else
 413                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 414
 415                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 416                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 417                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 418         }
 419
 420         if (!vc4_state->feed_txp)
 421                 vc4_crtc_config_pv(crtc);
 422
 423         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 424                   SCALER_DISPBKGND_AUTOHS |
 425                   SCALER_DISPBKGND_GAMMA |
 426                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 427
 428         /* Reload the LUT, since the SRAMs would have been disabled if
 429          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 430          */
 431         vc4_crtc_lut_load(crtc);
 432
 433         if (debug_dump_regs) {
 434                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 435                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 436                          drm_crtc_index(crtc));
 437                 drm_print_regset32(&p, &vc4_crtc->regset);
 438         }
 439 }
 440
 441 static void require_hvs_enabled(struct drm_device *dev)
 442 {
 443         struct vc4_dev *vc4 = to_vc4_dev(dev);
 444
 445         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 446                      SCALER_DISPCTRL_ENABLE);
 447 }
 448
 449 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 450                                     struct drm_crtc_state *old_state)
 451 {
 452         struct drm_device *dev = crtc->dev;
 453         struct vc4_dev *vc4 = to_vc4_dev(dev);
 454         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 455         u32 chan = vc4_crtc->channel;
 456         int ret;
 457         require_hvs_enabled(dev);
 458
 459         /* Disable vblank irq handling before crtc is disabled. */
 460         drm_crtc_vblank_off(crtc);
 461
 462         CRTC_WRITE(PV_V_CONTROL,
 463                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 464         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 465         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 466
 467         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 468             SCALER_DISPCTRLX_ENABLE) {
 469                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 470                           SCALER_DISPCTRLX_RESET);
 471
 472                 /* While the docs say that reset is self-clearing, it
 473                  * seems it doesn't actually.
 474                  */
 475                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 476         }
 477
 478         /* Once we leave, the scaler should be disabled and its fifo empty. */
 479
 480         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 481
 482         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 483                                    SCALER_DISPSTATX_MODE) !=
 484                      SCALER_DISPSTATX_MODE_DISABLED);
 485
 486         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 487                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 488                      SCALER_DISPSTATX_EMPTY);
 489
 490         /*
 491          * Make sure we issue a vblank event after disabling the CRTC if
 492          * someone was waiting it.
 493          */
 494         if (crtc->state->event) {
 495                 unsigned long flags;
 496
 497                 spin_lock_irqsave(&dev->event_lock, flags);
 498                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 499                 crtc->state->event = NULL;
 500                 spin_unlock_irqrestore(&dev->event_lock, flags);
 501         }
 502 }
 503
 504 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 505 {
 506         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 507
 508         vc4_state->txp_armed = true;
 509 }
 510
 511 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 512 {
 513         struct drm_device *dev = crtc->dev;
 514         struct vc4_dev *vc4 = to_vc4_dev(dev);
 515         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 516         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 517
 518         if (crtc->state->event) {
 519                 unsigned long flags;
 520
 521                 crtc->state->event->pipe = drm_crtc_index(crtc);
 522
 523                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 524
 525                 spin_lock_irqsave(&dev->event_lock, flags);
 526
 527                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 528                         vc4_crtc->event = crtc->state->event;
 529                         crtc->state->event = NULL;
 530                 }
 531
 532                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 533                           vc4_state->mm.start);
 534
 535                 spin_unlock_irqrestore(&dev->event_lock, flags);
 536         } else {
 537                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 538                           vc4_state->mm.start);
 539         }
 540 }
 541
 542 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 543                                    struct drm_crtc_state *old_state)
 544 {
 545         struct drm_device *dev = crtc->dev;
 546         struct vc4_dev *vc4 = to_vc4_dev(dev);
 547         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 548         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 549         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 550
 551         require_hvs_enabled(dev);
 552
 553         /* Enable vblank irq handling before crtc is started otherwise
 554          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 555          */
 556         drm_crtc_vblank_on(crtc);
 557         vc4_crtc_update_dlist(crtc);
 558
 559         /* Turn on the scaler, which will wait for vstart to start
 560          * compositing.
 561          * When feeding the transposer, we should operate in oneshot
 562          * mode.
 563          */
 564         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 565                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 566                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 567                   SCALER_DISPCTRLX_ENABLE |
 568                   (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
 569
 570         /* When feeding the transposer block the pixelvalve is unneeded and
 571          * should not be enabled.
 572          */
 573         if (!vc4_state->feed_txp)
 574                 CRTC_WRITE(PV_V_CONTROL,
 575                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 576 }
 577
 578 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 579                                                 const struct drm_display_mode *mode)
 580 {
 581         /* Do not allow doublescan modes from user space */
 582         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 583                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 584                               crtc->base.id);
 585                 return MODE_NO_DBLESCAN;
 586         }
 587
 588         return MODE_OK;
 589 }
 590
 591 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 592                           unsigned int *left, unsigned int *right,
 593                           unsigned int *top, unsigned int *bottom)
 594 {
 595         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 596         struct drm_connector_state *conn_state;
 597         struct drm_connector *conn;
 598         int i;
 599
 600         *left = vc4_state->margins.left;
 601         *right = vc4_state->margins.right;
 602         *top = vc4_state->margins.top;
 603         *bottom = vc4_state->margins.bottom;
 604
 605         /* We have to interate over all new connector states because
 606          * vc4_crtc_get_margins() might be called before
 607          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 608          * might be outdated.
 609          */
 610         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 611                 if (conn_state->crtc != state->crtc)
 612                         continue;
 613
 614                 *left = conn_state->tv.margins.left;
 615                 *right = conn_state->tv.margins.right;
 616                 *top = conn_state->tv.margins.top;
 617                 *bottom = conn_state->tv.margins.bottom;
 618                 break;
 619         }
 620 }
 621
 622 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 623                                  struct drm_crtc_state *state)
 624 {
 625         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 626         struct drm_device *dev = crtc->dev;
 627         struct vc4_dev *vc4 = to_vc4_dev(dev);
 628         struct drm_plane *plane;
 629         unsigned long flags;
 630         const struct drm_plane_state *plane_state;
 631         struct drm_connector *conn;
 632         struct drm_connector_state *conn_state;
 633         u32 dlist_count = 0;
 634         int ret, i;
 635
 636         /* The pixelvalve can only feed one encoder (and encoders are
 637          * 1:1 with connectors.)
 638          */
 639         if (hweight32(state->connector_mask) > 1)
 640                 return -EINVAL;
 641
 642         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 643                 dlist_count += vc4_plane_dlist_size(plane_state);
 644
 645         dlist_count++; /* Account for SCALER_CTL0_END. */
 646
 647         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 648         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 649                                  dlist_count);
 650         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 651         if (ret)
 652                 return ret;
 653
 654         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 655                 if (conn_state->crtc != crtc)
 656                         continue;
 657
 658                 /* The writeback connector is implemented using the transposer
 659                  * block which is directly taking its data from the HVS FIFO.
 660                  */
 661                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 662                         state->no_vblank = true;
 663                         vc4_state->feed_txp = true;
 664                 } else {
 665                         state->no_vblank = false;
 666                         vc4_state->feed_txp = false;
 667                 }
 668
 669                 vc4_state->margins.left = conn_state->tv.margins.left;
 670                 vc4_state->margins.right = conn_state->tv.margins.right;
 671                 vc4_state->margins.top = conn_state->tv.margins.top;
 672                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 673                 break;
 674         }
 675
 676         return 0;
 677 }
 678
 679 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 680                                   struct drm_crtc_state *old_state)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct vc4_dev *vc4 = to_vc4_dev(dev);
 684         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 685         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 686         struct drm_plane *plane;
 687         struct vc4_plane_state *vc4_plane_state;
 688         bool debug_dump_regs = false;
 689         bool enable_bg_fill = false;
 690         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 691         u32 __iomem *dlist_next = dlist_start;
 692
 693         if (debug_dump_regs) {
 694                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 695                 vc4_hvs_dump_state(dev);
 696         }
 697
 698         /* Copy all the active planes' dlist contents to the hardware dlist. */
 699         drm_atomic_crtc_for_each_plane(plane, crtc) {
 700                 /* Is this the first active plane? */
 701                 if (dlist_next == dlist_start) {
 702                         /* We need to enable background fill when a plane
 703                          * could be alpha blending from the background, i.e.
 704                          * where no other plane is underneath. It suffices to
 705                          * consider the first active plane here since we set
 706                          * needs_bg_fill such that either the first plane
 707                          * already needs it or all planes on top blend from
 708                          * the first or a lower plane.
 709                          */
 710                         vc4_plane_state = to_vc4_plane_state(plane->state);
 711                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 712                 }
 713
 714                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 715         }
 716
 717         writel(SCALER_CTL0_END, dlist_next);
 718         dlist_next++;
 719
 720         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 721
 722         if (enable_bg_fill)
 723                 /* This sets a black background color fill, as is the case
 724                  * with other DRM drivers.
 725                  */
 726                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 727                           HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
 728                           SCALER_DISPBKGND_FILL);
 729
 730         /* Only update DISPLIST if the CRTC was already running and is not
 731          * being disabled.
 732          * vc4_crtc_enable() takes care of updating the dlist just after
 733          * re-enabling VBLANK interrupts and before enabling the engine.
 734          * If the CRTC is being disabled, there's no point in updating this
 735          * information.
 736          */
 737         if (crtc->state->active && old_state->active)
 738                 vc4_crtc_update_dlist(crtc);
 739
 740         if (crtc->state->color_mgmt_changed) {
 741                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
 742
 743                 if (crtc->state->gamma_lut) {
 744                         vc4_crtc_update_gamma_lut(crtc);
 745                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 746                 } else {
 747                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 748                          * in hardware, which is the same as a linear lut that
 749                          * DRM expects us to use in absence of a user lut.
 750                          */
 751                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 752                 }
 753                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
 754         }
 755
 756         if (debug_dump_regs) {
 757                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 758                 vc4_hvs_dump_state(dev);
 759         }
 760 }
 761
 762 static int vc4_enable_vblank(struct drm_crtc *crtc)
 763 {
 764         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 765
 766         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 767
 768         return 0;
 769 }
 770
 771 static void vc4_disable_vblank(struct drm_crtc *crtc)
 772 {
 773         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 774
 775         CRTC_WRITE(PV_INTEN, 0);
 776 }
 777
 778 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 779 {
 780         struct drm_crtc *crtc = &vc4_crtc->base;
 781         struct drm_device *dev = crtc->dev;
 782         struct vc4_dev *vc4 = to_vc4_dev(dev);
 783         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 784         u32 chan = vc4_crtc->channel;
 785         unsigned long flags;
 786
 787         spin_lock_irqsave(&dev->event_lock, flags);
 788         if (vc4_crtc->event &&
 789             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 790              vc4_state->feed_txp)) {
 791                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 792                 vc4_crtc->event = NULL;
 793                 drm_crtc_vblank_put(crtc);
 794
 795                 /* Wait for the page flip to unmask the underrun to ensure that
 796                  * the display list was updated by the hardware. Before that
 797                  * happens, the HVS will be using the previous display list with
 798                  * the CRTC and encoder already reconfigured, leading to
 799                  * underruns. This can be seen when reconfiguring the CRTC.
 800                  */
 801                 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
 802         }
 803         spin_unlock_irqrestore(&dev->event_lock, flags);
 804 }
 805
 806 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 807 {
 808         crtc->t_vblank = ktime_get();
 809         drm_crtc_handle_vblank(&crtc->base);
 810         vc4_crtc_handle_page_flip(crtc);
 811 }
 812
 813 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 814 {
 815         struct vc4_crtc *vc4_crtc = data;
 816         u32 stat = CRTC_READ(PV_INTSTAT);
 817         irqreturn_t ret = IRQ_NONE;
 818
 819         if (stat & PV_INT_VFP_START) {
 820                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 821                 vc4_crtc_handle_vblank(vc4_crtc);
 822                 ret = IRQ_HANDLED;
 823         }
 824
 825         return ret;
 826 }
 827
 828 struct vc4_async_flip_state {
 829         struct drm_crtc *crtc;
 830         struct drm_framebuffer *fb;
 831         struct drm_framebuffer *old_fb;
 832         struct drm_pending_vblank_event *event;
 833
 834         struct vc4_seqno_cb cb;
 835 };
 836
 837 /* Called when the V3D execution for the BO being flipped to is done, so that
 838  * we can actually update the plane's address to point to it.
 839  */
 840 static void
 841 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 842 {
 843         struct vc4_async_flip_state *flip_state =
 844                 container_of(cb, struct vc4_async_flip_state, cb);
 845         struct drm_crtc *crtc = flip_state->crtc;
 846         struct drm_device *dev = crtc->dev;
 847         struct vc4_dev *vc4 = to_vc4_dev(dev);
 848         struct drm_plane *plane = crtc->primary;
 849
 850         vc4_plane_async_set_fb(plane, flip_state->fb);
 851         if (flip_state->event) {
 852                 unsigned long flags;
 853
 854                 spin_lock_irqsave(&dev->event_lock, flags);
 855                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 856                 spin_unlock_irqrestore(&dev->event_lock, flags);
 857         }
 858
 859         drm_crtc_vblank_put(crtc);
 860         drm_framebuffer_put(flip_state->fb);
 861
 862         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 863          * when the planes are updated through the async update path.
 864          * FIXME: we should move to generic async-page-flip when it's
 865          * available, so that we can get rid of this hand-made cleanup_fb()
 866          * logic.
 867          */
 868         if (flip_state->old_fb) {
 869                 struct drm_gem_cma_object *cma_bo;
 870                 struct vc4_bo *bo;
 871
 872                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 873                 bo = to_vc4_bo(&cma_bo->base);
 874                 vc4_bo_dec_usecnt(bo);
 875                 drm_framebuffer_put(flip_state->old_fb);
 876         }
 877
 878         kfree(flip_state);
 879
 880         up(&vc4->async_modeset);
 881 }
 882
 883 /* Implements async (non-vblank-synced) page flips.
 884  *
 885  * The page flip ioctl needs to return immediately, so we grab the
 886  * modeset semaphore on the pipe, and queue the address update for
 887  * when V3D is done with the BO being flipped to.
 888  */
 889 static int vc4_async_page_flip(struct drm_crtc *crtc,
 890                                struct drm_framebuffer *fb,
 891                                struct drm_pending_vblank_event *event,
 892                                uint32_t flags)
 893 {
 894         struct drm_device *dev = crtc->dev;
 895         struct vc4_dev *vc4 = to_vc4_dev(dev);
 896         struct drm_plane *plane = crtc->primary;
 897         int ret = 0;
 898         struct vc4_async_flip_state *flip_state;
 899         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 900         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 901
 902         /* Increment the BO usecnt here, so that we never end up with an
 903          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 904          * plane is later updated through the non-async path.
 905          * FIXME: we should move to generic async-page-flip when it's
 906          * available, so that we can get rid of this hand-made prepare_fb()
 907          * logic.
 908          */
 909         ret = vc4_bo_inc_usecnt(bo);
 910         if (ret)
 911                 return ret;
 912
 913         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 914         if (!flip_state) {
 915                 vc4_bo_dec_usecnt(bo);
 916                 return -ENOMEM;
 917         }
 918
 919         drm_framebuffer_get(fb);
 920         flip_state->fb = fb;
 921         flip_state->crtc = crtc;
 922         flip_state->event = event;
 923
 924         /* Make sure all other async modesetes have landed. */
 925         ret = down_interruptible(&vc4->async_modeset);
 926         if (ret) {
 927                 drm_framebuffer_put(fb);
 928                 vc4_bo_dec_usecnt(bo);
 929                 kfree(flip_state);
 930                 return ret;
 931         }
 932
 933         /* Save the current FB before it's replaced by the new one in
 934          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 935          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 936          * it consistent.
 937          * FIXME: we should move to generic async-page-flip when it's
 938          * available, so that we can get rid of this hand-made cleanup_fb()
 939          * logic.
 940          */
 941         flip_state->old_fb = plane->state->fb;
 942         if (flip_state->old_fb)
 943                 drm_framebuffer_get(flip_state->old_fb);
 944
 945         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 946
 947         /* Immediately update the plane's legacy fb pointer, so that later
 948          * modeset prep sees the state that will be present when the semaphore
 949          * is released.
 950          */
 951         drm_atomic_set_fb_for_plane(plane->state, fb);
 952
 953         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 954                            vc4_async_page_flip_complete);
 955
 956         /* Driver takes ownership of state on successful async commit. */
 957         return 0;
 958 }
 959
 960 static int vc4_page_flip(struct drm_crtc *crtc,
 961                          struct drm_framebuffer *fb,
 962                          struct drm_pending_vblank_event *event,
 963                          uint32_t flags,
 964                          struct drm_modeset_acquire_ctx *ctx)
 965 {
 966         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 967                 return vc4_async_page_flip(crtc, fb, event, flags);
 968         else
 969                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 970 }
 971
 972 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 973 {
 974         struct vc4_crtc_state *vc4_state, *old_vc4_state;
 975
 976         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 977         if (!vc4_state)
 978                 return NULL;
 979
 980         old_vc4_state = to_vc4_crtc_state(crtc->state);
 981         vc4_state->feed_txp = old_vc4_state->feed_txp;
 982         vc4_state->margins = old_vc4_state->margins;
 983
 984         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 985         return &vc4_state->base;
 986 }
 987
 988 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 989                                    struct drm_crtc_state *state)
 990 {
 991         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 992         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 993
 994         if (vc4_state->mm.allocated) {
 995                 unsigned long flags;
 996
 997                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 998                 drm_mm_remove_node(&vc4_state->mm);
 999                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1000
1001         }
1002
1003         drm_atomic_helper_crtc_destroy_state(crtc, state);
1004 }
1005
1006 static void
1007 vc4_crtc_reset(struct drm_crtc *crtc)
1008 {
1009         if (crtc->state)
1010                 vc4_crtc_destroy_state(crtc, crtc->state);
1011
1012         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1013         if (crtc->state)
1014                 crtc->state->crtc = crtc;
1015 }
1016
1017 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1018         .set_config = drm_atomic_helper_set_config,
1019         .destroy = vc4_crtc_destroy,
1020         .page_flip = vc4_page_flip,
1021         .set_property = NULL,
1022         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1023         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1024         .reset = vc4_crtc_reset,
1025         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1026         .atomic_destroy_state = vc4_crtc_destroy_state,
1027         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1028         .enable_vblank = vc4_enable_vblank,
1029         .disable_vblank = vc4_disable_vblank,
1030 };
1031
1032 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1033         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1034         .mode_valid = vc4_crtc_mode_valid,
1035         .atomic_check = vc4_crtc_atomic_check,
1036         .atomic_flush = vc4_crtc_atomic_flush,
1037         .atomic_enable = vc4_crtc_atomic_enable,
1038         .atomic_disable = vc4_crtc_atomic_disable,
1039 };
1040
1041 static const struct vc4_crtc_data pv0_data = {
1042         .hvs_channel = 0,
1043         .debugfs_name = "crtc0_regs",
1044         .encoder_types = {
1045                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1046                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1047         },
1048 };
1049
1050 static const struct vc4_crtc_data pv1_data = {
1051         .hvs_channel = 2,
1052         .debugfs_name = "crtc1_regs",
1053         .encoder_types = {
1054                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1055                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1056         },
1057 };
1058
1059 static const struct vc4_crtc_data pv2_data = {
1060         .hvs_channel = 1,
1061         .debugfs_name = "crtc2_regs",
1062         .encoder_types = {
1063                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1064                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1065         },
1066 };
1067
1068 static const struct of_device_id vc4_crtc_dt_match[] = {
1069         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1070         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1071         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1072         {}
1073 };
1074
1075 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1076                                         struct drm_crtc *crtc)
1077 {
1078         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1079         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1080         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1081         struct drm_encoder *encoder;
1082
1083         drm_for_each_encoder(encoder, drm) {
1084                 struct vc4_encoder *vc4_encoder;
1085                 int i;
1086
1087                 /* HVS FIFO2 can feed the TXP IP. */
1088                 if (crtc_data->hvs_channel == 2 &&
1089                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1090                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1091                         continue;
1092                 }
1093
1094                 vc4_encoder = to_vc4_encoder(encoder);
1095                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1096                         if (vc4_encoder->type == encoder_types[i]) {
1097                                 vc4_encoder->clock_select = i;
1098                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1099                                 break;
1100                         }
1101                 }
1102         }
1103 }
1104
1105 static void
1106 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1107 {
1108         struct drm_device *drm = vc4_crtc->base.dev;
1109         struct vc4_dev *vc4 = to_vc4_dev(drm);
1110         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1111         /* Top/base are supposed to be 4-pixel aligned, but the
1112          * Raspberry Pi firmware fills the low bits (which are
1113          * presumably ignored).
1114          */
1115         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1116         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1117
1118         vc4_crtc->cob_size = top - base + 4;
1119 }
1120
1121 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1122 {
1123         struct platform_device *pdev = to_platform_device(dev);
1124         struct drm_device *drm = dev_get_drvdata(master);
1125         struct vc4_crtc *vc4_crtc;
1126         struct drm_crtc *crtc;
1127         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1128         const struct of_device_id *match;
1129         int ret, i;
1130
1131         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1132         if (!vc4_crtc)
1133                 return -ENOMEM;
1134         crtc = &vc4_crtc->base;
1135
1136         match = of_match_device(vc4_crtc_dt_match, dev);
1137         if (!match)
1138                 return -ENODEV;
1139         vc4_crtc->data = match->data;
1140         vc4_crtc->pdev = pdev;
1141
1142         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1143         if (IS_ERR(vc4_crtc->regs))
1144                 return PTR_ERR(vc4_crtc->regs);
1145
1146         vc4_crtc->regset.base = vc4_crtc->regs;
1147         vc4_crtc->regset.regs = crtc_regs;
1148         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1149
1150         /* For now, we create just the primary and the legacy cursor
1151          * planes.  We should be able to stack more planes on easily,
1152          * but to do that we would need to compute the bandwidth
1153          * requirement of the plane configuration, and reject ones
1154          * that will take too much.
1155          */
1156         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1157         if (IS_ERR(primary_plane)) {
1158                 dev_err(dev, "failed to construct primary plane\n");
1159                 ret = PTR_ERR(primary_plane);
1160                 goto err;
1161         }
1162
1163         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1164                                   &vc4_crtc_funcs, NULL);
1165         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1166         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1167         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1168         drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1169
1170         /* We support CTM, but only for one CRTC at a time. It's therefore
1171          * implemented as private driver state in vc4_kms, not here.
1172          */
1173         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1174
1175         /* Set up some arbitrary number of planes.  We're not limited
1176          * by a set number of physical registers, just the space in
1177          * the HVS (16k) and how small an plane can be (28 bytes).
1178          * However, each plane we set up takes up some memory, and
1179          * increases the cost of looping over planes, which atomic
1180          * modesetting does quite a bit.  As a result, we pick a
1181          * modest number of planes to expose, that should hopefully
1182          * still cover any sane usecase.
1183          */
1184         for (i = 0; i < 8; i++) {
1185                 struct drm_plane *plane =
1186                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1187
1188                 if (IS_ERR(plane))
1189                         continue;
1190
1191                 plane->possible_crtcs = drm_crtc_mask(crtc);
1192         }
1193
1194         /* Set up the legacy cursor after overlay initialization,
1195          * since we overlay planes on the CRTC in the order they were
1196          * initialized.
1197          */
1198         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1199         if (!IS_ERR(cursor_plane)) {
1200                 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1201                 crtc->cursor = cursor_plane;
1202         }
1203
1204         vc4_crtc_get_cob_allocation(vc4_crtc);
1205
1206         CRTC_WRITE(PV_INTEN, 0);
1207         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1208         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1209                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1210         if (ret)
1211                 goto err_destroy_planes;
1212
1213         vc4_set_crtc_possible_masks(drm, crtc);
1214
1215         for (i = 0; i < crtc->gamma_size; i++) {
1216                 vc4_crtc->lut_r[i] = i;
1217                 vc4_crtc->lut_g[i] = i;
1218                 vc4_crtc->lut_b[i] = i;
1219         }
1220
1221         platform_set_drvdata(pdev, vc4_crtc);
1222
1223         vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1224                                  &vc4_crtc->regset);
1225
1226         return 0;
1227
1228 err_destroy_planes:
1229         list_for_each_entry_safe(destroy_plane, temp,
1230                                  &drm->mode_config.plane_list, head) {
1231                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1232                     destroy_plane->funcs->destroy(destroy_plane);
1233         }
1234 err:
1235         return ret;
1236 }
1237
1238 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1239                             void *data)
1240 {
1241         struct platform_device *pdev = to_platform_device(dev);
1242         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1243
1244         vc4_crtc_destroy(&vc4_crtc->base);
1245
1246         CRTC_WRITE(PV_INTEN, 0);
1247
1248         platform_set_drvdata(pdev, NULL);
1249 }
1250
1251 static const struct component_ops vc4_crtc_ops = {
1252         .bind   = vc4_crtc_bind,
1253         .unbind = vc4_crtc_unbind,
1254 };
1255
1256 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1257 {
1258         return component_add(&pdev->dev, &vc4_crtc_ops);
1259 }
1260
1261 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1262 {
1263         component_del(&pdev->dev, &vc4_crtc_ops);
1264         return 0;
1265 }
1266
1267 struct platform_driver vc4_crtc_driver = {
1268         .probe = vc4_crtc_dev_probe,
1269         .remove = vc4_crtc_dev_remove,
1270         .driver = {
1271                 .name = "vc4_crtc",
1272                 .of_match_table = vc4_crtc_dt_match,
1273         },
1274 };