drivers/gpu/drm/nouveau/include/nvif/cl9097.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVIF_CL9097_H__
   3 #define __NVIF_CL9097_H__
   4
   5 #define FERMI_A_ZBC_COLOR                                                  0x00
   6 #define FERMI_A_ZBC_DEPTH                                                  0x01
   7
   8 struct fermi_a_zbc_color_v0 {
   9         __u8  version;
  10 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
  11 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
  12 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
  13 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
  14 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
  15 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
  16 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
  17 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
  18 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
  19 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
  20 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
  21 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
  22 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
  23 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
  24 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
  25 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
  26 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
  27 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
  28 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
  29         __u8  format;
  30         __u8  index;
  31         __u8  pad03[5];
  32         __u32 ds[4];
  33         __u32 l2[4];
  34 };
  35
  36 struct fermi_a_zbc_depth_v0 {
  37         __u8  version;
  38 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
  39         __u8  format;
  40         __u8  index;
  41         __u8  pad03[5];
  42         __u32 ds;
  43         __u32 l2;
  44 };
  45 #endif