drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29 #include "handles.h"
  30
  31 #include <linux/dma-mapping.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/component.h>
  34 #include <linux/iopoll.h>
  35
  36 #include <drm/display/drm_dp_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_eld.h>
  42 #include <drm/drm_fb_helper.h>
  43 #include <drm/drm_fixed.h>
  44 #include <drm/drm_probe_helper.h>
  45 #include <drm/drm_vblank.h>
  46
  47 #include <nvif/push507c.h>
  48
  49 #include <nvif/class.h>
  50 #include <nvif/cl0002.h>
  51 #include <nvif/event.h>
  52 #include <nvif/if0012.h>
  53 #include <nvif/if0014.h>
  54 #include <nvif/timer.h>
  55
  56 #include <nvhw/class/cl507c.h>
  57 #include <nvhw/class/cl507d.h>
  58 #include <nvhw/class/cl837d.h>
  59 #include <nvhw/class/cl887d.h>
  60 #include <nvhw/class/cl907d.h>
  61 #include <nvhw/class/cl917d.h>
  62
  63 #include "nouveau_drv.h"
  64 #include "nouveau_dma.h"
  65 #include "nouveau_gem.h"
  66 #include "nouveau_connector.h"
  67 #include "nouveau_encoder.h"
  68 #include "nouveau_fence.h"
  69 #include "nv50_display.h"
  70
  71 /******************************************************************************
  72  * EVO channel
  73  *****************************************************************************/
  74
  75 static int
  76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  77                  const s32 *oclass, u8 head, void *data, u32 size,
  78                  struct nv50_chan *chan)
  79 {
  80         struct nvif_sclass *sclass;
  81         int ret, i, n;
  82
  83         chan->device = device;
  84
  85         ret = n = nvif_object_sclass_get(disp, &sclass);
  86         if (ret < 0)
  87                 return ret;
  88
  89         while (oclass[0]) {
  90                 for (i = 0; i < n; i++) {
  91                         if (sclass[i].oclass == oclass[0]) {
  92                                 ret = nvif_object_ctor(disp, "kmsChan", 0,
  93                                                        oclass[0], data, size,
  94                                                        &chan->user);
  95                                 if (ret == 0)
  96                                         nvif_object_map(&chan->user, NULL, 0);
  97                                 nvif_object_sclass_put(&sclass);
  98                                 return ret;
  99                         }
 100                 }
 101                 oclass++;
 102         }
 103
 104         nvif_object_sclass_put(&sclass);
 105         return -ENOSYS;
 106 }
 107
 108 static void
 109 nv50_chan_destroy(struct nv50_chan *chan)
 110 {
 111         nvif_object_dtor(&chan->user);
 112 }
 113
 114 /******************************************************************************
 115  * DMA EVO channel
 116  *****************************************************************************/
 117
 118 void
 119 nv50_dmac_destroy(struct nv50_dmac *dmac)
 120 {
 121         nvif_object_dtor(&dmac->vram);
 122         nvif_object_dtor(&dmac->sync);
 123
 124         nv50_chan_destroy(&dmac->base);
 125
 126         nvif_mem_dtor(&dmac->_push.mem);
 127 }
 128
 129 static void
 130 nv50_dmac_kick(struct nvif_push *push)
 131 {
 132         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 133
 134         dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
 135         if (dmac->put != dmac->cur) {
 136                 /* Push buffer fetches are not coherent with BAR1, we need to ensure
 137                  * writes have been flushed right through to VRAM before writing PUT.
 138                  */
 139                 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
 140                         struct nvif_device *device = dmac->base.device;
 141                         nvif_wr32(&device->object, 0x070000, 0x00000001);
 142                         nvif_msec(device, 2000,
 143                                 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 144                                         break;
 145                         );
 146                 }
 147
 148                 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
 149                 dmac->put = dmac->cur;
 150         }
 151
 152         push->bgn = push->cur;
 153 }
 154
 155 static int
 156 nv50_dmac_free(struct nv50_dmac *dmac)
 157 {
 158         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 159         if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
 160                 return get - dmac->cur - 5;
 161         return dmac->max - dmac->cur;
 162 }
 163
 164 static int
 165 nv50_dmac_wind(struct nv50_dmac *dmac)
 166 {
 167         /* Wait for GET to depart from the beginning of the push buffer to
 168          * prevent writing PUT == GET, which would be ignored by HW.
 169          */
 170         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 171         if (get == 0) {
 172                 /* Corner-case, HW idle, but non-committed work pending. */
 173                 if (dmac->put == 0)
 174                         nv50_dmac_kick(dmac->push);
 175
 176                 if (nvif_msec(dmac->base.device, 2000,
 177                         if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
 178                                 break;
 179                 ) < 0)
 180                         return -ETIMEDOUT;
 181         }
 182
 183         PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
 184         dmac->cur = 0;
 185         return 0;
 186 }
 187
 188 static int
 189 nv50_dmac_wait(struct nvif_push *push, u32 size)
 190 {
 191         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 192         int free;
 193
 194         if (WARN_ON(size > dmac->max))
 195                 return -EINVAL;
 196
 197         dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
 198         if (dmac->cur + size >= dmac->max) {
 199                 int ret = nv50_dmac_wind(dmac);
 200                 if (ret)
 201                         return ret;
 202
 203                 push->cur = dmac->_push.mem.object.map.ptr;
 204                 push->cur = push->cur + dmac->cur;
 205                 nv50_dmac_kick(push);
 206         }
 207
 208         if (nvif_msec(dmac->base.device, 2000,
 209                 if ((free = nv50_dmac_free(dmac)) >= size)
 210                         break;
 211         ) < 0) {
 212                 WARN_ON(1);
 213                 return -ETIMEDOUT;
 214         }
 215
 216         push->bgn = dmac->_push.mem.object.map.ptr;
 217         push->bgn = push->bgn + dmac->cur;
 218         push->cur = push->bgn;
 219         push->end = push->cur + free;
 220         return 0;
 221 }
 222
 223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
 224 static int nv50_dmac_vram_pushbuf = -1;
 225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
 226
 227 int
 228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 229                  const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
 230                  struct nv50_dmac *dmac)
 231 {
 232         struct nouveau_cli *cli = (void *)device->object.client;
 233         struct nvif_disp_chan_v0 *args = data;
 234         u8 type = NVIF_MEM_COHERENT;
 235         int ret;
 236
 237         mutex_init(&dmac->lock);
 238
 239         /* Pascal added support for 47-bit physical addresses, but some
 240          * parts of EVO still only accept 40-bit PAs.
 241          *
 242          * To avoid issues on systems with large amounts of RAM, and on
 243          * systems where an IOMMU maps pages at a high address, we need
 244          * to allocate push buffers in VRAM instead.
 245          *
 246          * This appears to match NVIDIA's behaviour on Pascal.
 247          */
 248         if ((nv50_dmac_vram_pushbuf > 0) ||
 249             (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
 250                 type |= NVIF_MEM_VRAM;
 251
 252         ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
 253                                 &dmac->_push.mem);
 254         if (ret)
 255                 return ret;
 256
 257         dmac->ptr = dmac->_push.mem.object.map.ptr;
 258         dmac->_push.wait = nv50_dmac_wait;
 259         dmac->_push.kick = nv50_dmac_kick;
 260         dmac->push = &dmac->_push;
 261         dmac->push->bgn = dmac->_push.mem.object.map.ptr;
 262         dmac->push->cur = dmac->push->bgn;
 263         dmac->push->end = dmac->push->bgn;
 264         dmac->max = 0x1000/4 - 1;
 265
 266         /* EVO channels are affected by a HW bug where the last 12 DWORDs
 267          * of the push buffer aren't able to be used safely.
 268          */
 269         if (disp->oclass < GV100_DISP)
 270                 dmac->max -= 12;
 271
 272         args->pushbuf = nvif_handle(&dmac->_push.mem.object);
 273
 274         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 275                                &dmac->base);
 276         if (ret)
 277                 return ret;
 278
 279         if (syncbuf < 0)
 280                 return 0;
 281
 282         ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
 283                                NV_DMA_IN_MEMORY,
 284                                &(struct nv_dma_v0) {
 285                                         .target = NV_DMA_V0_TARGET_VRAM,
 286                                         .access = NV_DMA_V0_ACCESS_RDWR,
 287                                         .start = syncbuf + 0x0000,
 288                                         .limit = syncbuf + 0x0fff,
 289                                }, sizeof(struct nv_dma_v0),
 290                                &dmac->sync);
 291         if (ret)
 292                 return ret;
 293
 294         ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
 295                                NV_DMA_IN_MEMORY,
 296                                &(struct nv_dma_v0) {
 297                                         .target = NV_DMA_V0_TARGET_VRAM,
 298                                         .access = NV_DMA_V0_ACCESS_RDWR,
 299                                         .start = 0,
 300                                         .limit = device->info.ram_user - 1,
 301                                }, sizeof(struct nv_dma_v0),
 302                                &dmac->vram);
 303         if (ret)
 304                 return ret;
 305
 306         return ret;
 307 }
 308
 309 /******************************************************************************
 310  * Output path helpers
 311  *****************************************************************************/
 312 static void
 313 nv50_outp_dump_caps(struct nouveau_drm *drm,
 314                     struct nouveau_encoder *outp)
 315 {
 316         NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
 317                  outp->base.base.name, outp->caps.dp_interlace);
 318 }
 319
 320 static int
 321 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 322                             struct drm_crtc_state *crtc_state,
 323                             struct drm_connector_state *conn_state,
 324                             struct drm_display_mode *native_mode)
 325 {
 326         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 327         struct drm_display_mode *mode = &crtc_state->mode;
 328         struct drm_connector *connector = conn_state->connector;
 329         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 330         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 331
 332         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 333         asyc->scaler.full = false;
 334         if (!native_mode)
 335                 return 0;
 336
 337         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 338                 switch (connector->connector_type) {
 339                 case DRM_MODE_CONNECTOR_LVDS:
 340                 case DRM_MODE_CONNECTOR_eDP:
 341                         /* Don't force scaler for EDID modes with
 342                          * same size as the native one (e.g. different
 343                          * refresh rate)
 344                          */
 345                         if (mode->hdisplay == native_mode->hdisplay &&
 346                             mode->vdisplay == native_mode->vdisplay &&
 347                             mode->type & DRM_MODE_TYPE_DRIVER)
 348                                 break;
 349                         mode = native_mode;
 350                         asyc->scaler.full = true;
 351                         break;
 352                 default:
 353                         break;
 354                 }
 355         } else {
 356                 mode = native_mode;
 357         }
 358
 359         if (!drm_mode_equal(adjusted_mode, mode)) {
 360                 drm_mode_copy(adjusted_mode, mode);
 361                 crtc_state->mode_changed = true;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static void
 368 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
 369 {
 370         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 371         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 372         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
 373         unsigned int max_rate, mode_rate;
 374
 375         switch (nv_encoder->dcb->type) {
 376         case DCB_OUTPUT_DP:
 377                 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
 378
 379                 /* we don't support more than 10 anyway */
 380                 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
 381
 382                 /* reduce the bpc until it works out */
 383                 while (asyh->or.bpc > 6) {
 384                         mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
 385                         if (mode_rate <= max_rate)
 386                                 break;
 387
 388                         asyh->or.bpc -= 2;
 389                 }
 390                 break;
 391         default:
 392                 break;
 393         }
 394 }
 395
 396 static int
 397 nv50_outp_atomic_check(struct drm_encoder *encoder,
 398                        struct drm_crtc_state *crtc_state,
 399                        struct drm_connector_state *conn_state)
 400 {
 401         struct drm_connector *connector = conn_state->connector;
 402         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 403         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 404         int ret;
 405
 406         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 407                                           nv_connector->native_mode);
 408         if (ret)
 409                 return ret;
 410
 411         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 412                 asyh->or.bpc = connector->display_info.bpc;
 413
 414         /* We might have to reduce the bpc */
 415         nv50_outp_atomic_fix_depth(encoder, crtc_state);
 416
 417         return 0;
 418 }
 419
 420 struct nouveau_connector *
 421 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 422 {
 423         struct drm_connector *connector;
 424         struct drm_connector_state *connector_state;
 425         struct drm_encoder *encoder = to_drm_encoder(outp);
 426         int i;
 427
 428         for_each_new_connector_in_state(state, connector, connector_state, i) {
 429                 if (connector_state->best_encoder == encoder)
 430                         return nouveau_connector(connector);
 431         }
 432
 433         return NULL;
 434 }
 435
 436 struct nouveau_connector *
 437 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 438 {
 439         struct drm_connector *connector;
 440         struct drm_connector_state *connector_state;
 441         struct drm_encoder *encoder = to_drm_encoder(outp);
 442         int i;
 443
 444         for_each_old_connector_in_state(state, connector, connector_state, i) {
 445                 if (connector_state->best_encoder == encoder)
 446                         return nouveau_connector(connector);
 447         }
 448
 449         return NULL;
 450 }
 451
 452 static struct nouveau_crtc *
 453 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
 454 {
 455         struct drm_crtc *crtc;
 456         struct drm_crtc_state *crtc_state;
 457         const u32 mask = drm_encoder_mask(&outp->base.base);
 458         int i;
 459
 460         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 461                 if (crtc_state->encoder_mask & mask)
 462                         return nouveau_crtc(crtc);
 463         }
 464
 465         return NULL;
 466 }
 467
 468 /******************************************************************************
 469  * DAC
 470  *****************************************************************************/
 471 static void
 472 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 473 {
 474         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 475         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 476         const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
 477
 478         core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
 479         nv_encoder->crtc = NULL;
 480 }
 481
 482 static void
 483 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 484 {
 485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 486         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
 487         struct nv50_head_atom *asyh =
 488                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
 489         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 490         u32 ctrl = 0;
 491
 492         switch (nv_crtc->index) {
 493         case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
 494         case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
 495         case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
 496         case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
 497         default:
 498                 WARN_ON(1);
 499                 break;
 500         }
 501
 502         ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
 503
 504         if (!nvif_outp_acquired(&nv_encoder->outp))
 505                 nvif_outp_acquire_dac(&nv_encoder->outp);
 506
 507         core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
 508         asyh->or.depth = 0;
 509
 510         nv_encoder->crtc = &nv_crtc->base;
 511 }
 512
 513 static enum drm_connector_status
 514 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 515 {
 516         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 517         u32 loadval;
 518         int ret;
 519
 520         loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
 521         if (loadval == 0)
 522                 loadval = 340;
 523
 524         ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
 525         if (ret <= 0)
 526                 return connector_status_disconnected;
 527
 528         return connector_status_connected;
 529 }
 530
 531 static const struct drm_encoder_helper_funcs
 532 nv50_dac_help = {
 533         .atomic_check = nv50_outp_atomic_check,
 534         .atomic_enable = nv50_dac_atomic_enable,
 535         .atomic_disable = nv50_dac_atomic_disable,
 536         .detect = nv50_dac_detect
 537 };
 538
 539 static void
 540 nv50_dac_destroy(struct drm_encoder *encoder)
 541 {
 542         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 543
 544         nvif_outp_dtor(&nv_encoder->outp);
 545
 546         drm_encoder_cleanup(encoder);
 547         kfree(encoder);
 548 }
 549
 550 static const struct drm_encoder_funcs
 551 nv50_dac_func = {
 552         .destroy = nv50_dac_destroy,
 553 };
 554
 555 static int
 556 nv50_dac_create(struct nouveau_encoder *nv_encoder)
 557 {
 558         struct drm_connector *connector = &nv_encoder->conn->base;
 559         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 560         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 561         struct nvkm_i2c_bus *bus;
 562         struct drm_encoder *encoder;
 563         struct dcb_output *dcbe = nv_encoder->dcb;
 564         int type = DRM_MODE_ENCODER_DAC;
 565
 566         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 567         if (bus)
 568                 nv_encoder->i2c = &bus->i2c;
 569
 570         encoder = to_drm_encoder(nv_encoder);
 571         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 572                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 573         drm_encoder_helper_add(encoder, &nv50_dac_help);
 574
 575         drm_connector_attach_encoder(connector, encoder);
 576         return 0;
 577 }
 578
 579 /*
 580  * audio component binding for ELD notification
 581  */
 582 static void
 583 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 584                                 int dev_id)
 585 {
 586         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 587                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 588                                                  port, dev_id);
 589 }
 590
 591 static int
 592 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 593                              bool *enabled, unsigned char *buf, int max_bytes)
 594 {
 595         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 596         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 597         struct drm_encoder *encoder;
 598         struct nouveau_encoder *nv_encoder;
 599         struct nouveau_crtc *nv_crtc;
 600         int ret = 0;
 601
 602         *enabled = false;
 603
 604         mutex_lock(&drm->audio.lock);
 605
 606         drm_for_each_encoder(encoder, drm->dev) {
 607                 struct nouveau_connector *nv_connector = NULL;
 608
 609                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
 610                         continue; /* TODO */
 611
 612                 nv_encoder = nouveau_encoder(encoder);
 613                 nv_connector = nv_encoder->conn;
 614                 nv_crtc = nouveau_crtc(nv_encoder->crtc);
 615
 616                 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
 617                         continue;
 618
 619                 *enabled = nv_encoder->audio.enabled;
 620                 if (*enabled) {
 621                         ret = drm_eld_size(nv_connector->base.eld);
 622                         memcpy(buf, nv_connector->base.eld,
 623                                min(max_bytes, ret));
 624                 }
 625                 break;
 626         }
 627
 628         mutex_unlock(&drm->audio.lock);
 629
 630         return ret;
 631 }
 632
 633 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 634         .get_eld = nv50_audio_component_get_eld,
 635 };
 636
 637 static int
 638 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 639                           void *data)
 640 {
 641         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 642         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 643         struct drm_audio_component *acomp = data;
 644
 645         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 646                 return -ENOMEM;
 647
 648         drm_modeset_lock_all(drm_dev);
 649         acomp->ops = &nv50_audio_component_ops;
 650         acomp->dev = kdev;
 651         drm->audio.component = acomp;
 652         drm_modeset_unlock_all(drm_dev);
 653         return 0;
 654 }
 655
 656 static void
 657 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 658                             void *data)
 659 {
 660         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 661         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 662         struct drm_audio_component *acomp = data;
 663
 664         drm_modeset_lock_all(drm_dev);
 665         drm->audio.component = NULL;
 666         acomp->ops = NULL;
 667         acomp->dev = NULL;
 668         drm_modeset_unlock_all(drm_dev);
 669 }
 670
 671 static const struct component_ops nv50_audio_component_bind_ops = {
 672         .bind   = nv50_audio_component_bind,
 673         .unbind = nv50_audio_component_unbind,
 674 };
 675
 676 static void
 677 nv50_audio_component_init(struct nouveau_drm *drm)
 678 {
 679         if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 680                 return;
 681
 682         drm->audio.component_registered = true;
 683         mutex_init(&drm->audio.lock);
 684 }
 685
 686 static void
 687 nv50_audio_component_fini(struct nouveau_drm *drm)
 688 {
 689         if (!drm->audio.component_registered)
 690                 return;
 691
 692         component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 693         drm->audio.component_registered = false;
 694         mutex_destroy(&drm->audio.lock);
 695 }
 696
 697 /******************************************************************************
 698  * Audio
 699  *****************************************************************************/
 700 static bool
 701 nv50_audio_supported(struct drm_encoder *encoder)
 702 {
 703         struct nv50_disp *disp = nv50_disp(encoder->dev);
 704
 705         if (disp->disp->object.oclass <= GT200_DISP ||
 706             disp->disp->object.oclass == GT206_DISP)
 707                 return false;
 708
 709         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
 710                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 711
 712                 switch (nv_encoder->dcb->type) {
 713                 case DCB_OUTPUT_TMDS:
 714                 case DCB_OUTPUT_DP:
 715                         break;
 716                 default:
 717                         return false;
 718                 }
 719         }
 720
 721         return true;
 722 }
 723
 724 static void
 725 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 726 {
 727         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 728         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 729         struct nvif_outp *outp = &nv_encoder->outp;
 730
 731         if (!nv50_audio_supported(encoder))
 732                 return;
 733
 734         mutex_lock(&drm->audio.lock);
 735         if (nv_encoder->audio.enabled) {
 736                 nv_encoder->audio.enabled = false;
 737                 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
 738         }
 739         mutex_unlock(&drm->audio.lock);
 740
 741         nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
 742 }
 743
 744 static void
 745 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 746                   struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 747                   struct drm_display_mode *mode)
 748 {
 749         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 750         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 751         struct nvif_outp *outp = &nv_encoder->outp;
 752
 753         if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid))
 754                 return;
 755
 756         mutex_lock(&drm->audio.lock);
 757
 758         nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
 759                           drm_eld_size(nv_connector->base.eld));
 760         nv_encoder->audio.enabled = true;
 761
 762         mutex_unlock(&drm->audio.lock);
 763
 764         nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
 765 }
 766
 767 /******************************************************************************
 768  * HDMI
 769  *****************************************************************************/
 770 static void
 771 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 772                  struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 773                  struct drm_display_mode *mode, bool hda)
 774 {
 775         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 776         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 777         struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
 778         union hdmi_infoframe infoframe = { 0 };
 779         const u8 rekey = 56; /* binary driver, and tegra, constant */
 780         u32 max_ac_packet;
 781         struct {
 782                 struct nvif_outp_infoframe_v0 infoframe;
 783                 u8 data[17];
 784         } args = { 0 };
 785         int ret, size;
 786
 787         max_ac_packet  = mode->htotal - mode->hdisplay;
 788         max_ac_packet -= rekey;
 789         max_ac_packet -= 18; /* constant from tegra */
 790         max_ac_packet /= 32;
 791
 792         if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
 793                 const bool high_tmds_clock_ratio = mode->clock > 340000;
 794                 u8 scdc;
 795
 796                 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
 797                 if (ret < 0) {
 798                         NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 799                         return;
 800                 }
 801
 802                 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 803                 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
 804                         scdc |= SCDC_SCRAMBLING_ENABLE;
 805                 if (high_tmds_clock_ratio)
 806                         scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
 807
 808                 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
 809                 if (ret < 0)
 810                         NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 811                                  scdc, ret);
 812         }
 813
 814         ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true, max_ac_packet, rekey,
 815                              mode->clock, hdmi->scdc.supported, hdmi->scdc.scrambling.supported,
 816                              hdmi->scdc.scrambling.low_rates);
 817         if (ret)
 818                 return;
 819
 820         /* AVI InfoFrame. */
 821         args.infoframe.version = 0;
 822         args.infoframe.head = nv_crtc->index;
 823
 824         if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
 825                 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
 826                                                    HDMI_QUANTIZATION_RANGE_FULL);
 827
 828                 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
 829         } else {
 830                 size = 0;
 831         }
 832
 833         nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
 834
 835         /* Vendor InfoFrame. */
 836         memset(&args.data, 0, sizeof(args.data));
 837         if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
 838                                                          &nv_connector->base, mode))
 839                 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
 840         else
 841                 size = 0;
 842
 843         nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
 844
 845         nv_encoder->hdmi.enabled = true;
 846 }
 847
 848 /******************************************************************************
 849  * MST
 850  *****************************************************************************/
 851 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 852 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 853 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 854
 855 struct nv50_mstc {
 856         struct nv50_mstm *mstm;
 857         struct drm_dp_mst_port *port;
 858         struct drm_connector connector;
 859
 860         struct drm_display_mode *native;
 861         struct edid *edid;
 862 };
 863
 864 struct nv50_msto {
 865         struct drm_encoder encoder;
 866
 867         /* head is statically assigned on msto creation */
 868         struct nv50_head *head;
 869         struct nv50_mstc *mstc;
 870         bool disabled;
 871         bool enabled;
 872
 873         u32 display_id;
 874 };
 875
 876 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
 877 {
 878         struct nv50_msto *msto;
 879
 880         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
 881                 return nouveau_encoder(encoder);
 882
 883         msto = nv50_msto(encoder);
 884         if (!msto->mstc)
 885                 return NULL;
 886         return msto->mstc->mstm->outp;
 887 }
 888
 889 static void
 890 nv50_msto_cleanup(struct drm_atomic_state *state,
 891                   struct drm_dp_mst_topology_state *new_mst_state,
 892                   struct drm_dp_mst_topology_mgr *mgr,
 893                   struct nv50_msto *msto)
 894 {
 895         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 896         struct drm_dp_mst_atomic_payload *new_payload =
 897                 drm_atomic_get_mst_payload_state(new_mst_state, msto->mstc->port);
 898         struct drm_dp_mst_topology_state *old_mst_state =
 899                 drm_atomic_get_old_mst_topology_state(state, mgr);
 900         const struct drm_dp_mst_atomic_payload *old_payload =
 901                 drm_atomic_get_mst_payload_state(old_mst_state, msto->mstc->port);
 902         struct nv50_mstc *mstc = msto->mstc;
 903         struct nv50_mstm *mstm = mstc->mstm;
 904
 905         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 906
 907         if (msto->disabled) {
 908                 if (msto->head->func->display_id) {
 909                         nvif_outp_dp_mst_id_put(&mstm->outp->outp, msto->display_id);
 910                         msto->display_id = 0;
 911                 }
 912
 913                 msto->mstc = NULL;
 914                 msto->disabled = false;
 915                 drm_dp_remove_payload_part2(mgr, new_mst_state, old_payload, new_payload);
 916         } else if (msto->enabled) {
 917                 drm_dp_add_payload_part2(mgr, state, new_payload);
 918                 msto->enabled = false;
 919         }
 920 }
 921
 922 static void
 923 nv50_msto_prepare(struct drm_atomic_state *state,
 924                   struct drm_dp_mst_topology_state *mst_state,
 925                   struct drm_dp_mst_topology_mgr *mgr,
 926                   struct nv50_msto *msto)
 927 {
 928         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 929         struct nv50_mstc *mstc = msto->mstc;
 930         struct nv50_mstm *mstm = mstc->mstm;
 931         struct drm_dp_mst_atomic_payload *payload;
 932         int ret = 0;
 933
 934         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 935
 936         payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
 937
 938         if (msto->disabled) {
 939                 drm_dp_remove_payload_part1(mgr, mst_state, payload);
 940                 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
 941                 ret = 1;
 942         } else {
 943                 if (msto->enabled)
 944                         ret = drm_dp_add_payload_part1(mgr, mst_state, payload);
 945         }
 946
 947         if (ret == 0) {
 948                 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
 949                                       payload->vc_start_slot, payload->time_slots,
 950                                       payload->pbn,
 951                                       payload->time_slots * dfixed_trunc(mst_state->pbn_div));
 952         } else {
 953                 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
 954         }
 955 }
 956
 957 static int
 958 nv50_msto_atomic_check(struct drm_encoder *encoder,
 959                        struct drm_crtc_state *crtc_state,
 960                        struct drm_connector_state *conn_state)
 961 {
 962         struct drm_atomic_state *state = crtc_state->state;
 963         struct drm_connector *connector = conn_state->connector;
 964         struct drm_dp_mst_topology_state *mst_state;
 965         struct nv50_mstc *mstc = nv50_mstc(connector);
 966         struct nv50_mstm *mstm = mstc->mstm;
 967         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 968         int slots;
 969         int ret;
 970
 971         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 972                                           mstc->native);
 973         if (ret)
 974                 return ret;
 975
 976         if (!drm_atomic_crtc_needs_modeset(crtc_state))
 977                 return 0;
 978
 979         /*
 980          * When restoring duplicated states, we need to make sure that the bw
 981          * remains the same and avoid recalculating it, as the connector's bpc
 982          * may have changed after the state was duplicated
 983          */
 984         if (!state->duplicated) {
 985                 const int clock = crtc_state->adjusted_mode.clock;
 986
 987                 asyh->or.bpc = connector->display_info.bpc;
 988                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
 989         }
 990
 991         mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
 992         if (IS_ERR(mst_state))
 993                 return PTR_ERR(mst_state);
 994
 995         if (!mst_state->pbn_div.full) {
 996                 struct nouveau_encoder *outp = mstc->mstm->outp;
 997
 998                 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
 999                                                               outp->dp.link_bw, outp->dp.link_nr);
1000         }
1001
1002         slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
1003         if (slots < 0)
1004                 return slots;
1005
1006         asyh->dp.tu = slots;
1007
1008         return 0;
1009 }
1010
1011 static u8
1012 nv50_dp_bpc_to_depth(unsigned int bpc)
1013 {
1014         switch (bpc) {
1015         case  6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1016         case  8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1017         case 10:
1018         default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1019         }
1020 }
1021
1022 static void
1023 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1024 {
1025         struct nv50_msto *msto = nv50_msto(encoder);
1026         struct nv50_head *head = msto->head;
1027         struct nv50_head_atom *asyh =
1028                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1029         struct nv50_mstc *mstc = NULL;
1030         struct nv50_mstm *mstm = NULL;
1031         struct drm_connector *connector;
1032         struct drm_connector_list_iter conn_iter;
1033         u8 proto;
1034
1035         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1036         drm_for_each_connector_iter(connector, &conn_iter) {
1037                 if (connector->state->best_encoder == &msto->encoder) {
1038                         mstc = nv50_mstc(connector);
1039                         mstm = mstc->mstm;
1040                         break;
1041                 }
1042         }
1043         drm_connector_list_iter_end(&conn_iter);
1044
1045         if (WARN_ON(!mstc))
1046                 return;
1047
1048         if (!mstm->links++) {
1049                 nvif_outp_acquire_sor(&mstm->outp->outp, false /*TODO: MST audio... */);
1050                 nouveau_dp_train(mstm->outp, true, 0, 0);
1051         }
1052
1053         if (head->func->display_id) {
1054                 if (!WARN_ON(nvif_outp_dp_mst_id_get(&mstm->outp->outp, &msto->display_id)))
1055                         head->func->display_id(head, msto->display_id);
1056         }
1057
1058         if (mstm->outp->outp.or.link & 1)
1059                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1060         else
1061                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1062
1063         mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1064                            nv50_dp_bpc_to_depth(asyh->or.bpc));
1065
1066         msto->mstc = mstc;
1067         msto->enabled = true;
1068         mstm->modified = true;
1069 }
1070
1071 static void
1072 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1073 {
1074         struct nv50_msto *msto = nv50_msto(encoder);
1075         struct nv50_mstc *mstc = msto->mstc;
1076         struct nv50_mstm *mstm = mstc->mstm;
1077
1078         if (msto->head->func->display_id)
1079                 msto->head->func->display_id(msto->head, 0);
1080
1081         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1082         mstm->modified = true;
1083         if (!--mstm->links)
1084                 mstm->disabled = true;
1085         msto->disabled = true;
1086 }
1087
1088 static const struct drm_encoder_helper_funcs
1089 nv50_msto_help = {
1090         .atomic_disable = nv50_msto_atomic_disable,
1091         .atomic_enable = nv50_msto_atomic_enable,
1092         .atomic_check = nv50_msto_atomic_check,
1093 };
1094
1095 static void
1096 nv50_msto_destroy(struct drm_encoder *encoder)
1097 {
1098         struct nv50_msto *msto = nv50_msto(encoder);
1099         drm_encoder_cleanup(&msto->encoder);
1100         kfree(msto);
1101 }
1102
1103 static const struct drm_encoder_funcs
1104 nv50_msto = {
1105         .destroy = nv50_msto_destroy,
1106 };
1107
1108 static struct nv50_msto *
1109 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1110 {
1111         struct nv50_msto *msto;
1112         int ret;
1113
1114         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1115         if (!msto)
1116                 return ERR_PTR(-ENOMEM);
1117
1118         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1119                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1120         if (ret) {
1121                 kfree(msto);
1122                 return ERR_PTR(ret);
1123         }
1124
1125         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1126         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1127         msto->head = head;
1128         return msto;
1129 }
1130
1131 static struct drm_encoder *
1132 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1133                               struct drm_atomic_state *state)
1134 {
1135         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1136                                                                                          connector);
1137         struct nv50_mstc *mstc = nv50_mstc(connector);
1138         struct drm_crtc *crtc = connector_state->crtc;
1139
1140         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1141                 return NULL;
1142
1143         return &nv50_head(crtc)->msto->encoder;
1144 }
1145
1146 static enum drm_mode_status
1147 nv50_mstc_mode_valid(struct drm_connector *connector,
1148                      struct drm_display_mode *mode)
1149 {
1150         struct nv50_mstc *mstc = nv50_mstc(connector);
1151         struct nouveau_encoder *outp = mstc->mstm->outp;
1152
1153         /* TODO: calculate the PBN from the dotclock and validate against the
1154          * MSTB's max possible PBN
1155          */
1156
1157         return nv50_dp_mode_valid(outp, mode, NULL);
1158 }
1159
1160 static int
1161 nv50_mstc_get_modes(struct drm_connector *connector)
1162 {
1163         struct nv50_mstc *mstc = nv50_mstc(connector);
1164         int ret = 0;
1165
1166         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1167         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1168         if (mstc->edid)
1169                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1170
1171         /*
1172          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1173          * to 8 to save bandwidth on the topology. In the future, we'll want
1174          * to properly fix this by dynamically selecting the highest possible
1175          * bpc that would fit in the topology
1176          */
1177         if (connector->display_info.bpc)
1178                 connector->display_info.bpc =
1179                         clamp(connector->display_info.bpc, 6U, 8U);
1180         else
1181                 connector->display_info.bpc = 8;
1182
1183         if (mstc->native)
1184                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1185         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1186         return ret;
1187 }
1188
1189 static int
1190 nv50_mstc_atomic_check(struct drm_connector *connector,
1191                        struct drm_atomic_state *state)
1192 {
1193         struct nv50_mstc *mstc = nv50_mstc(connector);
1194         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1195
1196         return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
1197 }
1198
1199 static int
1200 nv50_mstc_detect(struct drm_connector *connector,
1201                  struct drm_modeset_acquire_ctx *ctx, bool force)
1202 {
1203         struct nv50_mstc *mstc = nv50_mstc(connector);
1204         int ret;
1205
1206         if (drm_connector_is_unregistered(connector))
1207                 return connector_status_disconnected;
1208
1209         ret = pm_runtime_get_sync(connector->dev->dev);
1210         if (ret < 0 && ret != -EACCES) {
1211                 pm_runtime_put_autosuspend(connector->dev->dev);
1212                 return connector_status_disconnected;
1213         }
1214
1215         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1216                                      mstc->port);
1217         if (ret != connector_status_connected)
1218                 goto out;
1219
1220 out:
1221         pm_runtime_mark_last_busy(connector->dev->dev);
1222         pm_runtime_put_autosuspend(connector->dev->dev);
1223         return ret;
1224 }
1225
1226 static const struct drm_connector_helper_funcs
1227 nv50_mstc_help = {
1228         .get_modes = nv50_mstc_get_modes,
1229         .mode_valid = nv50_mstc_mode_valid,
1230         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1231         .atomic_check = nv50_mstc_atomic_check,
1232         .detect_ctx = nv50_mstc_detect,
1233 };
1234
1235 static void
1236 nv50_mstc_destroy(struct drm_connector *connector)
1237 {
1238         struct nv50_mstc *mstc = nv50_mstc(connector);
1239
1240         drm_connector_cleanup(&mstc->connector);
1241         drm_dp_mst_put_port_malloc(mstc->port);
1242
1243         kfree(mstc);
1244 }
1245
1246 static const struct drm_connector_funcs
1247 nv50_mstc = {
1248         .reset = nouveau_conn_reset,
1249         .fill_modes = drm_helper_probe_single_connector_modes,
1250         .destroy = nv50_mstc_destroy,
1251         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1252         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1253         .atomic_set_property = nouveau_conn_atomic_set_property,
1254         .atomic_get_property = nouveau_conn_atomic_get_property,
1255 };
1256
1257 static int
1258 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1259               const char *path, struct nv50_mstc **pmstc)
1260 {
1261         struct drm_device *dev = mstm->outp->base.base.dev;
1262         struct drm_crtc *crtc;
1263         struct nv50_mstc *mstc;
1264         int ret;
1265
1266         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1267                 return -ENOMEM;
1268         mstc->mstm = mstm;
1269         mstc->port = port;
1270
1271         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1272                                  DRM_MODE_CONNECTOR_DisplayPort);
1273         if (ret) {
1274                 kfree(*pmstc);
1275                 *pmstc = NULL;
1276                 return ret;
1277         }
1278
1279         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1280
1281         mstc->connector.funcs->reset(&mstc->connector);
1282         nouveau_conn_attach_properties(&mstc->connector);
1283
1284         drm_for_each_crtc(crtc, dev) {
1285                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1286                         continue;
1287
1288                 drm_connector_attach_encoder(&mstc->connector,
1289                                              &nv50_head(crtc)->msto->encoder);
1290         }
1291
1292         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1293         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1294         drm_connector_set_path_property(&mstc->connector, path);
1295         drm_dp_mst_get_port_malloc(port);
1296         return 0;
1297 }
1298
1299 static void
1300 nv50_mstm_cleanup(struct drm_atomic_state *state,
1301                   struct drm_dp_mst_topology_state *mst_state,
1302                   struct nv50_mstm *mstm)
1303 {
1304         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1305         struct drm_encoder *encoder;
1306
1307         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1308         drm_dp_check_act_status(&mstm->mgr);
1309
1310         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1311                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1312                         struct nv50_msto *msto = nv50_msto(encoder);
1313                         struct nv50_mstc *mstc = msto->mstc;
1314                         if (mstc && mstc->mstm == mstm)
1315                                 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
1316                 }
1317         }
1318
1319         if (mstm->disabled) {
1320                 nouveau_dp_power_down(mstm->outp);
1321                 nvif_outp_release(&mstm->outp->outp);
1322                 mstm->disabled = false;
1323         }
1324
1325         mstm->modified = false;
1326 }
1327
1328 static void
1329 nv50_mstm_prepare(struct drm_atomic_state *state,
1330                   struct drm_dp_mst_topology_state *mst_state,
1331                   struct nv50_mstm *mstm)
1332 {
1333         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1334         struct drm_encoder *encoder;
1335
1336         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1337
1338         /* Disable payloads first */
1339         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1340                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1341                         struct nv50_msto *msto = nv50_msto(encoder);
1342                         struct nv50_mstc *mstc = msto->mstc;
1343                         if (mstc && mstc->mstm == mstm && msto->disabled)
1344                                 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1345                 }
1346         }
1347
1348         /* Add payloads for new heads, while also updating the start slots of any unmodified (but
1349          * active) heads that may have had their VC slots shifted left after the previous step
1350          */
1351         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1352                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1353                         struct nv50_msto *msto = nv50_msto(encoder);
1354                         struct nv50_mstc *mstc = msto->mstc;
1355                         if (mstc && mstc->mstm == mstm && !msto->disabled)
1356                                 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1357                 }
1358         }
1359 }
1360
1361 static struct drm_connector *
1362 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1363                         struct drm_dp_mst_port *port, const char *path)
1364 {
1365         struct nv50_mstm *mstm = nv50_mstm(mgr);
1366         struct nv50_mstc *mstc;
1367         int ret;
1368
1369         ret = nv50_mstc_new(mstm, port, path, &mstc);
1370         if (ret)
1371                 return NULL;
1372
1373         return &mstc->connector;
1374 }
1375
1376 static const struct drm_dp_mst_topology_cbs
1377 nv50_mstm = {
1378         .add_connector = nv50_mstm_add_connector,
1379 };
1380
1381 bool
1382 nv50_mstm_service(struct nouveau_drm *drm,
1383                   struct nouveau_connector *nv_connector,
1384                   struct nv50_mstm *mstm)
1385 {
1386         struct drm_dp_aux *aux = &nv_connector->aux;
1387         bool handled = true, ret = true;
1388         int rc;
1389         u8 esi[8] = {};
1390
1391         while (handled) {
1392                 u8 ack[8] = {};
1393
1394                 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1395                 if (rc != 8) {
1396                         ret = false;
1397                         break;
1398                 }
1399
1400                 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1401                 if (!handled)
1402                         break;
1403
1404                 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1405
1406                 if (rc != 1) {
1407                         ret = false;
1408                         break;
1409                 }
1410
1411                 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1412         }
1413
1414         if (!ret)
1415                 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1416                          nv_connector->base.name, rc);
1417
1418         return ret;
1419 }
1420
1421 void
1422 nv50_mstm_remove(struct nv50_mstm *mstm)
1423 {
1424         mstm->is_mst = false;
1425         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1426 }
1427
1428 int
1429 nv50_mstm_detect(struct nouveau_encoder *outp)
1430 {
1431         struct nv50_mstm *mstm = outp->dp.mstm;
1432         struct drm_dp_aux *aux;
1433         int ret;
1434
1435         if (!mstm || !mstm->can_mst)
1436                 return 0;
1437
1438         aux = mstm->mgr.aux;
1439
1440         /* Clear any leftover MST state we didn't set ourselves by first
1441          * disabling MST if it was already enabled
1442          */
1443         ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1444         if (ret < 0)
1445                 return ret;
1446
1447         /* And start enabling */
1448         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1449         if (ret)
1450                 return ret;
1451
1452         mstm->is_mst = true;
1453         return 1;
1454 }
1455
1456 static void
1457 nv50_mstm_fini(struct nouveau_encoder *outp)
1458 {
1459         struct nv50_mstm *mstm = outp->dp.mstm;
1460
1461         if (!mstm)
1462                 return;
1463
1464         /* Don't change the MST state of this connector until we've finished
1465          * resuming, since we can't safely grab hpd_irq_lock in our resume
1466          * path to protect mstm->is_mst without potentially deadlocking
1467          */
1468         mutex_lock(&outp->dp.hpd_irq_lock);
1469         mstm->suspended = true;
1470         mutex_unlock(&outp->dp.hpd_irq_lock);
1471
1472         if (mstm->is_mst)
1473                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1474 }
1475
1476 static void
1477 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1478 {
1479         struct nv50_mstm *mstm = outp->dp.mstm;
1480         int ret = 0;
1481
1482         if (!mstm)
1483                 return;
1484
1485         if (mstm->is_mst) {
1486                 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1487                 if (ret == -1)
1488                         nv50_mstm_remove(mstm);
1489         }
1490
1491         mutex_lock(&outp->dp.hpd_irq_lock);
1492         mstm->suspended = false;
1493         mutex_unlock(&outp->dp.hpd_irq_lock);
1494
1495         if (ret == -1)
1496                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1497 }
1498
1499 static void
1500 nv50_mstm_del(struct nv50_mstm **pmstm)
1501 {
1502         struct nv50_mstm *mstm = *pmstm;
1503         if (mstm) {
1504                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1505                 kfree(*pmstm);
1506                 *pmstm = NULL;
1507         }
1508 }
1509
1510 static int
1511 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1512               int conn_base_id, struct nv50_mstm **pmstm)
1513 {
1514         const int max_payloads = hweight8(outp->dcb->heads);
1515         struct drm_device *dev = outp->base.base.dev;
1516         struct nv50_mstm *mstm;
1517         int ret;
1518
1519         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1520                 return -ENOMEM;
1521         mstm->outp = outp;
1522         mstm->mgr.cbs = &nv50_mstm;
1523
1524         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1525                                            max_payloads, conn_base_id);
1526         if (ret)
1527                 return ret;
1528
1529         return 0;
1530 }
1531
1532 /******************************************************************************
1533  * SOR
1534  *****************************************************************************/
1535 static void
1536 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1537                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1538 {
1539         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1540         struct nv50_core *core = disp->core;
1541
1542         if (!asyh) {
1543                 nv_encoder->ctrl &= ~BIT(head);
1544                 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1545                         nv_encoder->ctrl = 0;
1546         } else {
1547                 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1548                 nv_encoder->ctrl |= BIT(head);
1549                 asyh->or.depth = depth;
1550         }
1551
1552         core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1553 }
1554
1555 /* TODO: Should we extend this to PWM-only backlights?
1556  * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1557  * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1558  * fixed time delay from the vbios…
1559  */
1560 static void
1561 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1562 {
1563         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1564         struct nv50_head *head = nv50_head(nv_encoder->crtc);
1565 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1566         struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1567         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1568         struct nouveau_backlight *backlight = nv_connector->backlight;
1569         struct drm_dp_aux *aux = &nv_connector->aux;
1570         int ret;
1571
1572         if (backlight && backlight->uses_dpcd) {
1573                 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1574                 if (ret < 0)
1575                         NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1576                                  nv_connector->base.base.id, nv_connector->base.name, ret);
1577         }
1578 #endif
1579
1580         if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && nv_encoder->hdmi.enabled) {
1581                 nvif_outp_hdmi(&nv_encoder->outp, head->base.index,
1582                                false, 0, 0, 0, false, false, false);
1583                 nv_encoder->hdmi.enabled = false;
1584         }
1585
1586         if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1587                 nouveau_dp_power_down(nv_encoder);
1588
1589         if (head->func->display_id)
1590                 head->func->display_id(head, 0);
1591
1592         nv_encoder->update(nv_encoder, head->base.index, NULL, 0, 0);
1593         nv50_audio_disable(encoder, &head->base);
1594         nv_encoder->crtc = NULL;
1595 }
1596
1597 // common/inc/displayport/displayport.h
1598 #define DP_CONFIG_WATERMARK_ADJUST                   2
1599 #define DP_CONFIG_WATERMARK_LIMIT                   20
1600 #define DP_CONFIG_INCREASED_WATERMARK_ADJUST         8
1601 #define DP_CONFIG_INCREASED_WATERMARK_LIMIT         22
1602
1603 static bool
1604 nv50_sor_dp_watermark_sst(struct nouveau_encoder *outp,
1605                           struct nv50_head *head, struct nv50_head_atom *asyh)
1606 {
1607         bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP;
1608         u64 minRate = outp->dp.link_bw * 1000;
1609         unsigned tuSize = 64;
1610         unsigned waterMark;
1611         unsigned hBlankSym;
1612         unsigned vBlankSym;
1613         unsigned watermarkAdjust = DP_CONFIG_WATERMARK_ADJUST;
1614         unsigned watermarkMinimum = DP_CONFIG_WATERMARK_LIMIT;
1615         // depth is multiplied by 16 in case of DSC enable
1616         s32 hblank_symbols;
1617         // number of link clocks per line.
1618         int vblank_symbols        = 0;
1619         bool bEnableDsc = false;
1620         unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1621         unsigned rasterWidth = asyh->mode.h.active;
1622         unsigned depth = asyh->or.bpc * 3;
1623         unsigned DSC_FACTOR = bEnableDsc ? 16 : 1;
1624         u64 pixelClockHz = asyh->mode.clock * 1000;
1625         u64 PrecisionFactor = 100000, ratioF, watermarkF;
1626         u32 numLanesPerLink = outp->dp.link_nr;
1627         u32 numSymbolsPerLine;
1628         u32 BlankingBits;
1629         u32 surfaceWidthPerLink;
1630         u32 PixelSteeringBits;
1631         u64 NumBlankingLinkClocks;
1632         u32 MinHBlank;
1633
1634         if (outp->outp.info.dp.increased_wm) {
1635                 watermarkAdjust = DP_CONFIG_INCREASED_WATERMARK_ADJUST;
1636                 watermarkMinimum = DP_CONFIG_INCREASED_WATERMARK_LIMIT;
1637         }
1638
1639         if ((pixelClockHz * depth) >= (8 * minRate * outp->dp.link_nr * DSC_FACTOR))
1640         {
1641                 return false;
1642         }
1643
1644         //
1645         // For DSC, if (pclk * bpp) < (1/64 * orclk * 8 * lanes) then some TU may end up with
1646         // 0 active symbols. This may cause HW hang. Bug 200379426
1647         //
1648         if ((bEnableDsc) &&
1649             ((pixelClockHz * depth) < div_u64(8 * minRate * outp->dp.link_nr * DSC_FACTOR, 64)))
1650         {
1651                 return false;
1652         }
1653
1654         //
1655         //  Perform the SST calculation.
1656         //      For auto mode the watermark calculation does not need to track accumulated error the
1657         //      formulas for manual mode will not work.  So below calculation was extracted from the DTB.
1658         //
1659         ratioF = div_u64((u64)pixelClockHz * depth * PrecisionFactor, DSC_FACTOR);
1660
1661         ratioF = div_u64(ratioF, 8 * (u64) minRate * outp->dp.link_nr);
1662
1663         if (PrecisionFactor < ratioF) // Assert if we will end up with a negative number in below
1664                 return false;
1665
1666         watermarkF = div_u64(ratioF * tuSize * (PrecisionFactor - ratioF), PrecisionFactor);
1667         waterMark = (unsigned)(watermarkAdjust + (div_u64(2 * div_u64(depth * PrecisionFactor, 8 * numLanesPerLink * DSC_FACTOR) + watermarkF, PrecisionFactor)));
1668
1669         //
1670         //  Bounds check the watermark
1671         //
1672         numSymbolsPerLine = div_u64(surfaceWidth * depth, 8 * outp->dp.link_nr * DSC_FACTOR);
1673
1674         if (WARN_ON(waterMark > 39 || waterMark > numSymbolsPerLine))
1675                 return false;
1676
1677         //
1678         //  Clamp the low side
1679         //
1680         if (waterMark < watermarkMinimum)
1681                 waterMark = watermarkMinimum;
1682
1683         //Bits to send BS/BE/Extra symbols due to pixel padding
1684         //Also accounts for enhanced framing.
1685         BlankingBits = 3*8*numLanesPerLink + (enhancedFraming ? 3*8*numLanesPerLink : 0);
1686
1687         //VBID/MVID/MAUD sent 4 times all the time
1688         BlankingBits += 3*8*4;
1689
1690         surfaceWidthPerLink = surfaceWidth;
1691
1692         //Extra bits sent due to pixel steering
1693         u32 remain;
1694         div_u64_rem(surfaceWidthPerLink, numLanesPerLink, &remain);
1695         PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0;
1696
1697         BlankingBits += PixelSteeringBits;
1698         NumBlankingLinkClocks = div_u64((u64)BlankingBits * PrecisionFactor, (8 * numLanesPerLink));
1699         MinHBlank = (u32)(div_u64(div_u64(NumBlankingLinkClocks * pixelClockHz, minRate), PrecisionFactor));
1700         MinHBlank += 12;
1701
1702         if (WARN_ON(MinHBlank > rasterWidth - surfaceWidth))
1703                 return false;
1704
1705         // Bug 702290 - Active Width should be greater than 60
1706         if (WARN_ON(surfaceWidth <= 60))
1707                 return false;
1708
1709
1710         hblank_symbols = (s32)(div_u64((u64)(rasterWidth - surfaceWidth - MinHBlank) * minRate, pixelClockHz));
1711
1712         //reduce HBlank Symbols to account for secondary data packet
1713         hblank_symbols -= 1; //Stuffer latency to send BS
1714         hblank_symbols -= 3; //SPKT latency to send data to stuffer
1715
1716         hblank_symbols -= numLanesPerLink == 1 ? 9  : numLanesPerLink == 2 ? 6 : 3;
1717
1718         hBlankSym = (hblank_symbols < 0) ? 0 : hblank_symbols;
1719
1720         // Refer to dev_disp.ref for more information.
1721         // # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - SetRasterBlankStart.X - 40) * link_clk / pclk) - Y - 1;
1722         // where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39
1723         if (surfaceWidth < 40)
1724         {
1725                 vblank_symbols = 0;
1726         }
1727         else
1728         {
1729                 vblank_symbols = (s32)((div_u64((u64)(surfaceWidth - 40) * minRate, pixelClockHz))) - 1;
1730
1731                 vblank_symbols -= numLanesPerLink == 1 ? 39  : numLanesPerLink == 2 ? 21 : 12;
1732         }
1733
1734         vBlankSym = (vblank_symbols < 0) ? 0 : vblank_symbols;
1735
1736         return nvif_outp_dp_sst(&outp->outp, head->base.index, waterMark, hBlankSym, vBlankSym);
1737 }
1738
1739 static void
1740 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1741 {
1742         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1743         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1744         struct nv50_head_atom *asyh =
1745                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1746         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1747         struct nv50_disp *disp = nv50_disp(encoder->dev);
1748         struct nv50_head *head = nv50_head(&nv_crtc->base);
1749         struct nvif_outp *outp = &nv_encoder->outp;
1750         struct drm_device *dev = encoder->dev;
1751         struct nouveau_drm *drm = nouveau_drm(dev);
1752         struct nouveau_connector *nv_connector;
1753 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1754         struct nouveau_backlight *backlight;
1755 #endif
1756         struct nvbios *bios = &drm->vbios;
1757         bool lvds_dual = false, lvds_8bpc = false, hda = false;
1758         u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1759         u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1760
1761         nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1762         nv_encoder->crtc = &nv_crtc->base;
1763
1764         if ((disp->disp->object.oclass == GT214_DISP ||
1765              disp->disp->object.oclass >= GF110_DISP) &&
1766             nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
1767             drm_detect_monitor_audio(nv_connector->edid))
1768                 hda = true;
1769
1770         if (!nvif_outp_acquired(outp))
1771                 nvif_outp_acquire_sor(outp, hda);
1772
1773         switch (nv_encoder->dcb->type) {
1774         case DCB_OUTPUT_TMDS:
1775                 if (disp->disp->object.oclass != NV50_DISP &&
1776                     drm_detect_hdmi_monitor(nv_connector->edid))
1777                         nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1778
1779                 if (nv_encoder->outp.or.link & 1) {
1780                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1781                         /* Only enable dual-link if:
1782                          *  - Need to (i.e. rate > 165MHz)
1783                          *  - DCB says we can
1784                          *  - Not an HDMI monitor, since there's no dual-link
1785                          *    on HDMI.
1786                          */
1787                         if (mode->clock >= 165000 &&
1788                             nv_encoder->dcb->duallink_possible &&
1789                             !drm_detect_hdmi_monitor(nv_connector->edid))
1790                                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1791                 } else {
1792                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1793                 }
1794                 break;
1795         case DCB_OUTPUT_LVDS:
1796                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1797
1798                 if (bios->fp_no_ddc) {
1799                         lvds_dual = bios->fp.dual_link;
1800                         lvds_8bpc = bios->fp.if_is_24bit;
1801                 } else {
1802                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1803                                 if (((u8 *)nv_connector->edid)[121] == 2)
1804                                         lvds_dual = true;
1805                         } else
1806                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1807                                 lvds_dual = true;
1808                         }
1809
1810                         if (lvds_dual) {
1811                                 if (bios->fp.strapless_is_24bit & 2)
1812                                         lvds_8bpc = true;
1813                         } else {
1814                                 if (bios->fp.strapless_is_24bit & 1)
1815                                         lvds_8bpc = true;
1816                         }
1817
1818                         if (asyh->or.bpc == 8)
1819                                 lvds_8bpc = true;
1820                 }
1821
1822                 nvif_outp_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
1823                 break;
1824         case DCB_OUTPUT_DP:
1825                 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1826                 nv50_sor_dp_watermark_sst(nv_encoder, head, asyh);
1827                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1828
1829                 if (nv_encoder->outp.or.link & 1)
1830                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1831                 else
1832                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1833
1834 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1835                 backlight = nv_connector->backlight;
1836                 if (backlight && backlight->uses_dpcd)
1837                         drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1838                                                  (u16)backlight->dev->props.brightness);
1839 #endif
1840
1841                 break;
1842         default:
1843                 BUG();
1844                 break;
1845         }
1846
1847         if (head->func->display_id)
1848                 head->func->display_id(head, BIT(nv_encoder->outp.id));
1849
1850         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1851 }
1852
1853 static const struct drm_encoder_helper_funcs
1854 nv50_sor_help = {
1855         .atomic_check = nv50_outp_atomic_check,
1856         .atomic_enable = nv50_sor_atomic_enable,
1857         .atomic_disable = nv50_sor_atomic_disable,
1858 };
1859
1860 static void
1861 nv50_sor_destroy(struct drm_encoder *encoder)
1862 {
1863         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1864
1865         nv50_mstm_del(&nv_encoder->dp.mstm);
1866         drm_encoder_cleanup(encoder);
1867
1868         if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1869                 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1870
1871         nvif_outp_dtor(&nv_encoder->outp);
1872         kfree(encoder);
1873 }
1874
1875 static const struct drm_encoder_funcs
1876 nv50_sor_func = {
1877         .destroy = nv50_sor_destroy,
1878 };
1879
1880 static int
1881 nv50_sor_create(struct nouveau_encoder *nv_encoder)
1882 {
1883         struct drm_connector *connector = &nv_encoder->conn->base;
1884         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1885         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1886         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1887         struct drm_encoder *encoder;
1888         struct dcb_output *dcbe = nv_encoder->dcb;
1889         struct nv50_disp *disp = nv50_disp(connector->dev);
1890         int type, ret;
1891
1892         switch (dcbe->type) {
1893         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1894         case DCB_OUTPUT_TMDS:
1895         case DCB_OUTPUT_DP:
1896         default:
1897                 type = DRM_MODE_ENCODER_TMDS;
1898                 break;
1899         }
1900
1901         nv_encoder->update = nv50_sor_update;
1902
1903         encoder = to_drm_encoder(nv_encoder);
1904         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1905                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1906         drm_encoder_helper_add(encoder, &nv50_sor_help);
1907
1908         drm_connector_attach_encoder(connector, encoder);
1909
1910         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1911         nv50_outp_dump_caps(drm, nv_encoder);
1912
1913         if (dcbe->type == DCB_OUTPUT_DP) {
1914                 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1915
1916                 if (disp->disp->object.oclass < GF110_DISP) {
1917                         /* HW has no support for address-only
1918                          * transactions, so we're required to
1919                          * use custom I2C-over-AUX code.
1920                          */
1921                         struct nvkm_i2c_aux *aux;
1922
1923                         aux = nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1924                         if (!aux)
1925                                 return -EINVAL;
1926
1927                         nv_encoder->i2c = &aux->i2c;
1928                 } else {
1929                         nv_encoder->i2c = &nv_connector->aux.ddc;
1930                 }
1931
1932                 if (nv_connector->type != DCB_CONNECTOR_eDP && nv_encoder->outp.info.dp.mst) {
1933                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1934                                             16, nv_connector->base.base.id,
1935                                             &nv_encoder->dp.mstm);
1936                         if (ret)
1937                                 return ret;
1938                 }
1939         } else
1940         if (nv_encoder->outp.info.ddc != NVIF_OUTP_DDC_INVALID) {
1941                 struct nvkm_i2c_bus *bus =
1942                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1943                 if (bus)
1944                         nv_encoder->i2c = &bus->i2c;
1945         }
1946
1947         return 0;
1948 }
1949
1950 /******************************************************************************
1951  * PIOR
1952  *****************************************************************************/
1953 static int
1954 nv50_pior_atomic_check(struct drm_encoder *encoder,
1955                        struct drm_crtc_state *crtc_state,
1956                        struct drm_connector_state *conn_state)
1957 {
1958         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1959         if (ret)
1960                 return ret;
1961         crtc_state->adjusted_mode.clock *= 2;
1962         return 0;
1963 }
1964
1965 static void
1966 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1967 {
1968         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1969         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1970         const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1971
1972         core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
1973         nv_encoder->crtc = NULL;
1974 }
1975
1976 static void
1977 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1978 {
1979         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1980         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1981         struct nv50_head_atom *asyh =
1982                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1983         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1984         u32 ctrl = 0;
1985
1986         switch (nv_crtc->index) {
1987         case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1988         case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1989         default:
1990                 WARN_ON(1);
1991                 break;
1992         }
1993
1994         switch (asyh->or.bpc) {
1995         case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1996         case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1997         case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1998         default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1999         }
2000
2001         if (!nvif_outp_acquired(&nv_encoder->outp))
2002                 nvif_outp_acquire_pior(&nv_encoder->outp);
2003
2004         switch (nv_encoder->dcb->type) {
2005         case DCB_OUTPUT_TMDS:
2006                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
2007                 break;
2008         case DCB_OUTPUT_DP:
2009                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
2010                 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6);
2011                 break;
2012         default:
2013                 BUG();
2014                 break;
2015         }
2016
2017         core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2018         nv_encoder->crtc = &nv_crtc->base;
2019 }
2020
2021 static const struct drm_encoder_helper_funcs
2022 nv50_pior_help = {
2023         .atomic_check = nv50_pior_atomic_check,
2024         .atomic_enable = nv50_pior_atomic_enable,
2025         .atomic_disable = nv50_pior_atomic_disable,
2026 };
2027
2028 static void
2029 nv50_pior_destroy(struct drm_encoder *encoder)
2030 {
2031         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2032
2033         nvif_outp_dtor(&nv_encoder->outp);
2034
2035         drm_encoder_cleanup(encoder);
2036
2037         mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
2038         kfree(encoder);
2039 }
2040
2041 static const struct drm_encoder_funcs
2042 nv50_pior_func = {
2043         .destroy = nv50_pior_destroy,
2044 };
2045
2046 static int
2047 nv50_pior_create(struct nouveau_encoder *nv_encoder)
2048 {
2049         struct drm_connector *connector = &nv_encoder->conn->base;
2050         struct drm_device *dev = connector->dev;
2051         struct nouveau_drm *drm = nouveau_drm(dev);
2052         struct nv50_disp *disp = nv50_disp(dev);
2053         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2054         struct nvkm_i2c_bus *bus = NULL;
2055         struct nvkm_i2c_aux *aux = NULL;
2056         struct i2c_adapter *ddc;
2057         struct drm_encoder *encoder;
2058         struct dcb_output *dcbe = nv_encoder->dcb;
2059         int type;
2060
2061         switch (dcbe->type) {
2062         case DCB_OUTPUT_TMDS:
2063                 bus  = nvkm_i2c_bus_find(i2c, nv_encoder->outp.info.ddc);
2064                 ddc  = bus ? &bus->i2c : NULL;
2065                 type = DRM_MODE_ENCODER_TMDS;
2066                 break;
2067         case DCB_OUTPUT_DP:
2068                 aux  = nvkm_i2c_aux_find(i2c, nv_encoder->outp.info.dp.aux);
2069                 ddc  = aux ? &aux->i2c : NULL;
2070                 type = DRM_MODE_ENCODER_TMDS;
2071                 break;
2072         default:
2073                 return -ENODEV;
2074         }
2075
2076         nv_encoder->i2c = ddc;
2077
2078         mutex_init(&nv_encoder->dp.hpd_irq_lock);
2079
2080         encoder = to_drm_encoder(nv_encoder);
2081         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2082                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2083         drm_encoder_helper_add(encoder, &nv50_pior_help);
2084
2085         drm_connector_attach_encoder(connector, encoder);
2086
2087         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2088         nv50_outp_dump_caps(drm, nv_encoder);
2089
2090         return 0;
2091 }
2092
2093 /******************************************************************************
2094  * Atomic
2095  *****************************************************************************/
2096
2097 static void
2098 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2099 {
2100         struct drm_dp_mst_topology_mgr *mgr;
2101         struct drm_dp_mst_topology_state *mst_state;
2102         struct nouveau_drm *drm = nouveau_drm(state->dev);
2103         struct nv50_disp *disp = nv50_disp(drm->dev);
2104         struct nv50_atom *atom = nv50_atom(state);
2105         struct nv50_core *core = disp->core;
2106         struct nv50_outp_atom *outp;
2107         struct nv50_mstm *mstm;
2108         int i;
2109
2110         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2111
2112         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
2113                 mstm = nv50_mstm(mgr);
2114                 if (mstm->modified)
2115                         nv50_mstm_prepare(state, mst_state, mstm);
2116         }
2117
2118         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2119         core->func->update(core, interlock, true);
2120         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2121                                        disp->core->chan.base.device))
2122                 NV_ERROR(drm, "core notifier timeout\n");
2123
2124         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
2125                 mstm = nv50_mstm(mgr);
2126                 if (mstm->modified)
2127                         nv50_mstm_cleanup(state, mst_state, mstm);
2128         }
2129
2130         list_for_each_entry(outp, &atom->outp, head) {
2131                 if (outp->encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2132                         struct nouveau_encoder *nv_encoder = nouveau_encoder(outp->encoder);
2133
2134                         if (outp->enabled) {
2135                                 nv50_audio_enable(outp->encoder, nouveau_crtc(nv_encoder->crtc),
2136                                                   nv_encoder->conn, NULL, NULL);
2137                                 outp->enabled = outp->disabled = false;
2138                         } else {
2139                                 if (outp->disabled) {
2140                                         nvif_outp_release(&nv_encoder->outp);
2141                                         outp->disabled = false;
2142                                 }
2143                         }
2144                 }
2145         }
2146 }
2147
2148 static void
2149 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2150 {
2151         struct drm_plane_state *new_plane_state;
2152         struct drm_plane *plane;
2153         int i;
2154
2155         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2156                 struct nv50_wndw *wndw = nv50_wndw(plane);
2157                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2158                         if (wndw->func->update)
2159                                 wndw->func->update(wndw, interlock);
2160                 }
2161         }
2162 }
2163
2164 static void
2165 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2166 {
2167         struct drm_device *dev = state->dev;
2168         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2169         struct drm_crtc *crtc;
2170         struct drm_plane_state *new_plane_state;
2171         struct drm_plane *plane;
2172         struct nouveau_drm *drm = nouveau_drm(dev);
2173         struct nv50_disp *disp = nv50_disp(dev);
2174         struct nv50_atom *atom = nv50_atom(state);
2175         struct nv50_core *core = disp->core;
2176         struct nv50_outp_atom *outp, *outt;
2177         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2178         int i;
2179         bool flushed = false;
2180
2181         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2182         nv50_crc_atomic_stop_reporting(state);
2183         drm_atomic_helper_wait_for_fences(dev, state, false);
2184         drm_atomic_helper_wait_for_dependencies(state);
2185         drm_dp_mst_atomic_wait_for_dependencies(state);
2186         drm_atomic_helper_update_legacy_modeset_state(dev, state);
2187         drm_atomic_helper_calc_timestamping_constants(state);
2188
2189         if (atom->lock_core)
2190                 mutex_lock(&disp->mutex);
2191
2192         /* Disable head(s). */
2193         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2194                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2195                 struct nv50_head *head = nv50_head(crtc);
2196
2197                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2198                           asyh->clr.mask, asyh->set.mask);
2199
2200                 if (old_crtc_state->active && !new_crtc_state->active) {
2201                         pm_runtime_put_noidle(dev->dev);
2202                         drm_crtc_vblank_off(crtc);
2203                 }
2204
2205                 if (asyh->clr.mask) {
2206                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
2207                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2208                 }
2209         }
2210
2211         /* Disable plane(s). */
2212         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2213                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2214                 struct nv50_wndw *wndw = nv50_wndw(plane);
2215
2216                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2217                           asyw->clr.mask, asyw->set.mask);
2218                 if (!asyw->clr.mask)
2219                         continue;
2220
2221                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2222         }
2223
2224         /* Disable output path(s). */
2225         list_for_each_entry(outp, &atom->outp, head) {
2226                 const struct drm_encoder_helper_funcs *help;
2227                 struct drm_encoder *encoder;
2228
2229                 encoder = outp->encoder;
2230                 help = encoder->helper_private;
2231
2232                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2233                           outp->clr.mask, outp->set.mask);
2234
2235                 if (outp->clr.mask) {
2236                         help->atomic_disable(encoder, state);
2237                         outp->disabled = true;
2238                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2239                 }
2240         }
2241
2242         /* Flush disable. */
2243         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2244                 if (atom->flush_disable) {
2245                         nv50_disp_atomic_commit_wndw(state, interlock);
2246                         nv50_disp_atomic_commit_core(state, interlock);
2247                         memset(interlock, 0x00, sizeof(interlock));
2248
2249                         flushed = true;
2250                 }
2251         }
2252
2253         if (flushed)
2254                 nv50_crc_atomic_release_notifier_contexts(state);
2255         nv50_crc_atomic_init_notifier_contexts(state);
2256
2257         /* Update output path(s). */
2258         list_for_each_entry(outp, &atom->outp, head) {
2259                 const struct drm_encoder_helper_funcs *help;
2260                 struct drm_encoder *encoder;
2261
2262                 encoder = outp->encoder;
2263                 help = encoder->helper_private;
2264
2265                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2266                           outp->set.mask, outp->clr.mask);
2267
2268                 if (outp->set.mask) {
2269                         help->atomic_enable(encoder, state);
2270                         outp->enabled = true;
2271                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2272                 }
2273         }
2274
2275         /* Update head(s). */
2276         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2277                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2278                 struct nv50_head *head = nv50_head(crtc);
2279
2280                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2281                           asyh->set.mask, asyh->clr.mask);
2282
2283                 if (asyh->set.mask) {
2284                         nv50_head_flush_set(head, asyh);
2285                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2286                 }
2287
2288                 if (new_crtc_state->active) {
2289                         if (!old_crtc_state->active) {
2290                                 drm_crtc_vblank_on(crtc);
2291                                 pm_runtime_get_noresume(dev->dev);
2292                         }
2293                         if (new_crtc_state->event)
2294                                 drm_crtc_vblank_get(crtc);
2295                 }
2296         }
2297
2298         /* Update window->head assignment.
2299          *
2300          * This has to happen in an update that's not interlocked with
2301          * any window channels to avoid hitting HW error checks.
2302          *
2303          *TODO: Proper handling of window ownership (Turing apparently
2304          *      supports non-fixed mappings).
2305          */
2306         if (core->assign_windows) {
2307                 core->func->wndw.owner(core);
2308                 nv50_disp_atomic_commit_core(state, interlock);
2309                 core->assign_windows = false;
2310                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2311         }
2312
2313         /* Finish updating head(s)...
2314          *
2315          * NVD is rather picky about both where window assignments can change,
2316          * *and* about certain core and window channel states matching.
2317          *
2318          * The EFI GOP driver on newer GPUs configures window channels with a
2319          * different output format to what we do, and the core channel update
2320          * in the assign_windows case above would result in a state mismatch.
2321          *
2322          * Delay some of the head update until after that point to workaround
2323          * the issue.  This only affects the initial modeset.
2324          *
2325          * TODO: handle this better when adding flexible window mapping
2326          */
2327         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2328                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2329                 struct nv50_head *head = nv50_head(crtc);
2330
2331                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2332                           asyh->set.mask, asyh->clr.mask);
2333
2334                 if (asyh->set.mask) {
2335                         nv50_head_flush_set_wndw(head, asyh);
2336                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2337                 }
2338         }
2339
2340         /* Update plane(s). */
2341         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2342                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2343                 struct nv50_wndw *wndw = nv50_wndw(plane);
2344
2345                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2346                           asyw->set.mask, asyw->clr.mask);
2347                 if ( !asyw->set.mask &&
2348                     (!asyw->clr.mask || atom->flush_disable))
2349                         continue;
2350
2351                 nv50_wndw_flush_set(wndw, interlock, asyw);
2352         }
2353
2354         /* Flush update. */
2355         nv50_disp_atomic_commit_wndw(state, interlock);
2356
2357         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2358                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2359                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2360                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2361                     !atom->state.legacy_cursor_update)
2362                         nv50_disp_atomic_commit_core(state, interlock);
2363                 else
2364                         disp->core->func->update(disp->core, interlock, false);
2365         }
2366
2367         if (atom->lock_core)
2368                 mutex_unlock(&disp->mutex);
2369
2370         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2371                 list_del(&outp->head);
2372                 kfree(outp);
2373         }
2374
2375         /* Wait for HW to signal completion. */
2376         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2377                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2378                 struct nv50_wndw *wndw = nv50_wndw(plane);
2379                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2380                 if (ret)
2381                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2382         }
2383
2384         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2385                 if (new_crtc_state->event) {
2386                         unsigned long flags;
2387                         /* Get correct count/ts if racing with vblank irq */
2388                         if (new_crtc_state->active)
2389                                 drm_crtc_accurate_vblank_count(crtc);
2390                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2391                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2392                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2393
2394                         new_crtc_state->event = NULL;
2395                         if (new_crtc_state->active)
2396                                 drm_crtc_vblank_put(crtc);
2397                 }
2398         }
2399
2400         nv50_crc_atomic_start_reporting(state);
2401         if (!flushed)
2402                 nv50_crc_atomic_release_notifier_contexts(state);
2403
2404         drm_atomic_helper_commit_hw_done(state);
2405         drm_atomic_helper_cleanup_planes(dev, state);
2406         drm_atomic_helper_commit_cleanup_done(state);
2407         drm_atomic_state_put(state);
2408
2409         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2410         pm_runtime_mark_last_busy(dev->dev);
2411         pm_runtime_put_autosuspend(dev->dev);
2412 }
2413
2414 static void
2415 nv50_disp_atomic_commit_work(struct work_struct *work)
2416 {
2417         struct drm_atomic_state *state =
2418                 container_of(work, typeof(*state), commit_work);
2419         nv50_disp_atomic_commit_tail(state);
2420 }
2421
2422 static int
2423 nv50_disp_atomic_commit(struct drm_device *dev,
2424                         struct drm_atomic_state *state, bool nonblock)
2425 {
2426         struct drm_plane_state *new_plane_state;
2427         struct drm_plane *plane;
2428         int ret, i;
2429
2430         ret = pm_runtime_get_sync(dev->dev);
2431         if (ret < 0 && ret != -EACCES) {
2432                 pm_runtime_put_autosuspend(dev->dev);
2433                 return ret;
2434         }
2435
2436         ret = drm_atomic_helper_setup_commit(state, nonblock);
2437         if (ret)
2438                 goto done;
2439
2440         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2441
2442         ret = drm_atomic_helper_prepare_planes(dev, state);
2443         if (ret)
2444                 goto done;
2445
2446         if (!nonblock) {
2447                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2448                 if (ret)
2449                         goto err_cleanup;
2450         }
2451
2452         ret = drm_atomic_helper_swap_state(state, true);
2453         if (ret)
2454                 goto err_cleanup;
2455
2456         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2457                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2458                 struct nv50_wndw *wndw = nv50_wndw(plane);
2459
2460                 if (asyw->set.image)
2461                         nv50_wndw_ntfy_enable(wndw, asyw);
2462         }
2463
2464         drm_atomic_state_get(state);
2465
2466         /*
2467          * Grab another RPM ref for the commit tail, which will release the
2468          * ref when it's finished
2469          */
2470         pm_runtime_get_noresume(dev->dev);
2471
2472         if (nonblock)
2473                 queue_work(system_unbound_wq, &state->commit_work);
2474         else
2475                 nv50_disp_atomic_commit_tail(state);
2476
2477 err_cleanup:
2478         if (ret)
2479                 drm_atomic_helper_cleanup_planes(dev, state);
2480 done:
2481         pm_runtime_put_autosuspend(dev->dev);
2482         return ret;
2483 }
2484
2485 static struct nv50_outp_atom *
2486 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2487 {
2488         struct nv50_outp_atom *outp;
2489
2490         list_for_each_entry(outp, &atom->outp, head) {
2491                 if (outp->encoder == encoder)
2492                         return outp;
2493         }
2494
2495         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2496         if (!outp)
2497                 return ERR_PTR(-ENOMEM);
2498
2499         list_add(&outp->head, &atom->outp);
2500         outp->encoder = encoder;
2501         return outp;
2502 }
2503
2504 static int
2505 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2506                                 struct drm_connector_state *old_connector_state)
2507 {
2508         struct drm_encoder *encoder = old_connector_state->best_encoder;
2509         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2510         struct drm_crtc *crtc;
2511         struct nv50_outp_atom *outp;
2512
2513         if (!(crtc = old_connector_state->crtc))
2514                 return 0;
2515
2516         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2517         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2518         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2519                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2520                 if (IS_ERR(outp))
2521                         return PTR_ERR(outp);
2522
2523                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST ||
2524                     nouveau_encoder(outp->encoder)->dcb->type == DCB_OUTPUT_DP)
2525                         atom->flush_disable = true;
2526                 outp->clr.ctrl = true;
2527                 atom->lock_core = true;
2528         }
2529
2530         return 0;
2531 }
2532
2533 static int
2534 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2535                                 struct drm_connector_state *connector_state)
2536 {
2537         struct drm_encoder *encoder = connector_state->best_encoder;
2538         struct drm_crtc_state *new_crtc_state;
2539         struct drm_crtc *crtc;
2540         struct nv50_outp_atom *outp;
2541
2542         if (!(crtc = connector_state->crtc))
2543                 return 0;
2544
2545         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2546         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2547                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2548                 if (IS_ERR(outp))
2549                         return PTR_ERR(outp);
2550
2551                 outp->set.ctrl = true;
2552                 atom->lock_core = true;
2553         }
2554
2555         return 0;
2556 }
2557
2558 static int
2559 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2560 {
2561         struct nv50_atom *atom = nv50_atom(state);
2562         struct nv50_core *core = nv50_disp(dev)->core;
2563         struct drm_connector_state *old_connector_state, *new_connector_state;
2564         struct drm_connector *connector;
2565         struct drm_crtc_state *new_crtc_state;
2566         struct drm_crtc *crtc;
2567         struct nv50_head *head;
2568         struct nv50_head_atom *asyh;
2569         int ret, i;
2570
2571         if (core->assign_windows && core->func->head->static_wndw_map) {
2572                 drm_for_each_crtc(crtc, dev) {
2573                         new_crtc_state = drm_atomic_get_crtc_state(state,
2574                                                                    crtc);
2575                         if (IS_ERR(new_crtc_state))
2576                                 return PTR_ERR(new_crtc_state);
2577
2578                         head = nv50_head(crtc);
2579                         asyh = nv50_head_atom(new_crtc_state);
2580                         core->func->head->static_wndw_map(head, asyh);
2581                 }
2582         }
2583
2584         /* We need to handle colour management on a per-plane basis. */
2585         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2586                 if (new_crtc_state->color_mgmt_changed) {
2587                         ret = drm_atomic_add_affected_planes(state, crtc);
2588                         if (ret)
2589                                 return ret;
2590                 }
2591         }
2592
2593         ret = drm_atomic_helper_check(dev, state);
2594         if (ret)
2595                 return ret;
2596
2597         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2598                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2599                 if (ret)
2600                         return ret;
2601
2602                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2603                 if (ret)
2604                         return ret;
2605         }
2606
2607         ret = drm_dp_mst_atomic_check(state);
2608         if (ret)
2609                 return ret;
2610
2611         nv50_crc_atomic_check_outp(atom);
2612
2613         return 0;
2614 }
2615
2616 static void
2617 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2618 {
2619         struct nv50_atom *atom = nv50_atom(state);
2620         struct nv50_outp_atom *outp, *outt;
2621
2622         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2623                 list_del(&outp->head);
2624                 kfree(outp);
2625         }
2626
2627         drm_atomic_state_default_clear(state);
2628 }
2629
2630 static void
2631 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2632 {
2633         struct nv50_atom *atom = nv50_atom(state);
2634         drm_atomic_state_default_release(&atom->state);
2635         kfree(atom);
2636 }
2637
2638 static struct drm_atomic_state *
2639 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2640 {
2641         struct nv50_atom *atom;
2642         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2643             drm_atomic_state_init(dev, &atom->state) < 0) {
2644                 kfree(atom);
2645                 return NULL;
2646         }
2647         INIT_LIST_HEAD(&atom->outp);
2648         return &atom->state;
2649 }
2650
2651 static const struct drm_mode_config_funcs
2652 nv50_disp_func = {
2653         .fb_create = nouveau_user_framebuffer_create,
2654         .output_poll_changed = drm_fb_helper_output_poll_changed,
2655         .atomic_check = nv50_disp_atomic_check,
2656         .atomic_commit = nv50_disp_atomic_commit,
2657         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2658         .atomic_state_clear = nv50_disp_atomic_state_clear,
2659         .atomic_state_free = nv50_disp_atomic_state_free,
2660 };
2661
2662 static const struct drm_mode_config_helper_funcs
2663 nv50_disp_helper_func = {
2664         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2665 };
2666
2667 /******************************************************************************
2668  * Init
2669  *****************************************************************************/
2670
2671 static void
2672 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2673 {
2674         struct nouveau_drm *drm = nouveau_drm(dev);
2675         struct drm_encoder *encoder;
2676
2677         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2678                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2679                         nv50_mstm_fini(nouveau_encoder(encoder));
2680         }
2681
2682         if (!runtime)
2683                 cancel_work_sync(&drm->hpd_work);
2684 }
2685
2686 static inline void
2687 nv50_display_read_hw_or_state(struct drm_device *dev, struct nv50_disp *disp,
2688                               struct nouveau_encoder *outp)
2689 {
2690         struct drm_crtc *crtc;
2691         struct drm_connector_list_iter conn_iter;
2692         struct drm_connector *conn;
2693         struct nv50_head_atom *armh;
2694         const u32 encoder_mask = drm_encoder_mask(&outp->base.base);
2695         bool found_conn = false, found_head = false;
2696         u8 proto;
2697         int head_idx;
2698         int ret;
2699
2700         switch (outp->dcb->type) {
2701         case DCB_OUTPUT_TMDS:
2702                 ret = nvif_outp_inherit_tmds(&outp->outp, &proto);
2703                 break;
2704         case DCB_OUTPUT_DP:
2705                 ret = nvif_outp_inherit_dp(&outp->outp, &proto);
2706                 break;
2707         case DCB_OUTPUT_LVDS:
2708                 ret = nvif_outp_inherit_lvds(&outp->outp, &proto);
2709                 break;
2710         case DCB_OUTPUT_ANALOG:
2711                 ret = nvif_outp_inherit_rgb_crt(&outp->outp, &proto);
2712                 break;
2713         default:
2714                 drm_dbg_kms(dev, "Readback for %s not implemented yet, skipping\n",
2715                             outp->base.base.name);
2716                 drm_WARN_ON(dev, true);
2717                 return;
2718         }
2719
2720         if (ret < 0)
2721                 return;
2722
2723         head_idx = ret;
2724
2725         drm_for_each_crtc(crtc, dev) {
2726                 if (crtc->index != head_idx)
2727                         continue;
2728
2729                 armh = nv50_head_atom(crtc->state);
2730                 found_head = true;
2731                 break;
2732         }
2733         if (drm_WARN_ON(dev, !found_head))
2734                 return;
2735
2736         /* Figure out which connector is being used by this encoder */
2737         drm_connector_list_iter_begin(dev, &conn_iter);
2738         nouveau_for_each_non_mst_connector_iter(conn, &conn_iter) {
2739                 if (nouveau_connector(conn)->index == outp->dcb->connector) {
2740                         found_conn = true;
2741                         break;
2742                 }
2743         }
2744         drm_connector_list_iter_end(&conn_iter);
2745         if (drm_WARN_ON(dev, !found_conn))
2746                 return;
2747
2748         armh->state.encoder_mask = encoder_mask;
2749         armh->state.connector_mask = drm_connector_mask(conn);
2750         armh->state.active = true;
2751         armh->state.enable = true;
2752         pm_runtime_get_noresume(dev->dev);
2753
2754         outp->crtc = crtc;
2755         outp->ctrl = NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto) | BIT(crtc->index);
2756
2757         drm_connector_get(conn);
2758         conn->state->crtc = crtc;
2759         conn->state->best_encoder = &outp->base.base;
2760 }
2761
2762 /* Read back the currently programmed display state */
2763 static void
2764 nv50_display_read_hw_state(struct nouveau_drm *drm)
2765 {
2766         struct drm_device *dev = drm->dev;
2767         struct drm_encoder *encoder;
2768         struct drm_modeset_acquire_ctx ctx;
2769         struct nv50_disp *disp = nv50_disp(dev);
2770         int ret;
2771
2772         DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
2773
2774         drm_for_each_encoder(encoder, dev) {
2775                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
2776                         continue;
2777
2778                 nv50_display_read_hw_or_state(dev, disp, nouveau_encoder(encoder));
2779         }
2780
2781         DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
2782 }
2783
2784 static int
2785 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2786 {
2787         struct nv50_core *core = nv50_disp(dev)->core;
2788         struct drm_encoder *encoder;
2789
2790         if (resume || runtime)
2791                 core->func->init(core);
2792
2793         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2794                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2795                         struct nouveau_encoder *nv_encoder =
2796                                 nouveau_encoder(encoder);
2797                         nv50_mstm_init(nv_encoder, runtime);
2798                 }
2799         }
2800
2801         if (!resume)
2802                 nv50_display_read_hw_state(nouveau_drm(dev));
2803
2804         return 0;
2805 }
2806
2807 static void
2808 nv50_display_destroy(struct drm_device *dev)
2809 {
2810         struct nv50_disp *disp = nv50_disp(dev);
2811
2812         nv50_audio_component_fini(nouveau_drm(dev));
2813
2814         nvif_object_unmap(&disp->caps);
2815         nvif_object_dtor(&disp->caps);
2816         nv50_core_del(&disp->core);
2817
2818         nouveau_bo_unmap(disp->sync);
2819         if (disp->sync)
2820                 nouveau_bo_unpin(disp->sync);
2821         nouveau_bo_ref(NULL, &disp->sync);
2822
2823         nouveau_display(dev)->priv = NULL;
2824         kfree(disp);
2825 }
2826
2827 int
2828 nv50_display_create(struct drm_device *dev)
2829 {
2830         struct nouveau_drm *drm = nouveau_drm(dev);
2831         struct drm_connector *connector, *tmp;
2832         struct nv50_disp *disp;
2833         int ret, i;
2834         bool has_mst = false;
2835
2836         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2837         if (!disp)
2838                 return -ENOMEM;
2839
2840         mutex_init(&disp->mutex);
2841
2842         nouveau_display(dev)->priv = disp;
2843         nouveau_display(dev)->dtor = nv50_display_destroy;
2844         nouveau_display(dev)->init = nv50_display_init;
2845         nouveau_display(dev)->fini = nv50_display_fini;
2846         disp->disp = &nouveau_display(dev)->disp;
2847         dev->mode_config.funcs = &nv50_disp_func;
2848         dev->mode_config.helper_private = &nv50_disp_helper_func;
2849         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2850         dev->mode_config.normalize_zpos = true;
2851
2852         /* small shared memory area we use for notifiers and semaphores */
2853         ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2854                              NOUVEAU_GEM_DOMAIN_VRAM,
2855                              0, 0x0000, NULL, NULL, &disp->sync);
2856         if (!ret) {
2857                 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2858                 if (!ret) {
2859                         ret = nouveau_bo_map(disp->sync);
2860                         if (ret)
2861                                 nouveau_bo_unpin(disp->sync);
2862                 }
2863                 if (ret)
2864                         nouveau_bo_ref(NULL, &disp->sync);
2865         }
2866
2867         if (ret)
2868                 goto out;
2869
2870         /* allocate master evo channel */
2871         ret = nv50_core_new(drm, &disp->core);
2872         if (ret)
2873                 goto out;
2874
2875         disp->core->func->init(disp->core);
2876         if (disp->core->func->caps_init) {
2877                 ret = disp->core->func->caps_init(drm, disp);
2878                 if (ret)
2879                         goto out;
2880         }
2881
2882         /* Assign the correct format modifiers */
2883         if (disp->disp->object.oclass >= TU102_DISP)
2884                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2885         else
2886         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2887                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2888         else
2889                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2890
2891         /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2892          * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2893          * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2894          * small page allocations in prepare_fb(). When this is implemented, we should also force
2895          * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2896          * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2897          * large pages.
2898          */
2899         if (disp->disp->object.oclass >= GM107_DISP) {
2900                 dev->mode_config.cursor_width = 256;
2901                 dev->mode_config.cursor_height = 256;
2902         } else if (disp->disp->object.oclass >= GK104_DISP) {
2903                 dev->mode_config.cursor_width = 128;
2904                 dev->mode_config.cursor_height = 128;
2905         } else {
2906                 dev->mode_config.cursor_width = 64;
2907                 dev->mode_config.cursor_height = 64;
2908         }
2909
2910         /* create encoder/connector objects based on VBIOS DCB table */
2911         for_each_set_bit(i, &disp->disp->outp_mask, sizeof(disp->disp->outp_mask) * 8) {
2912                 struct nouveau_encoder *outp;
2913
2914                 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2915                 if (!outp)
2916                         break;
2917
2918                 ret = nvif_outp_ctor(disp->disp, "kmsOutp", i, &outp->outp);
2919                 if (ret) {
2920                         kfree(outp);
2921                         continue;
2922                 }
2923
2924                 connector = nouveau_connector_create(dev, outp->outp.info.conn);
2925                 if (IS_ERR(connector)) {
2926                         nvif_outp_dtor(&outp->outp);
2927                         kfree(outp);
2928                         continue;
2929                 }
2930
2931                 outp->base.base.possible_crtcs = outp->outp.info.heads;
2932                 outp->base.base.possible_clones = 0;
2933                 outp->conn = nouveau_connector(connector);
2934
2935                 outp->dcb = kzalloc(sizeof(*outp->dcb), GFP_KERNEL);
2936                 if (!outp->dcb)
2937                         break;
2938
2939                 switch (outp->outp.info.proto) {
2940                 case NVIF_OUTP_RGB_CRT:
2941                         outp->dcb->type = DCB_OUTPUT_ANALOG;
2942                         outp->dcb->crtconf.maxfreq = outp->outp.info.rgb_crt.freq_max;
2943                         break;
2944                 case NVIF_OUTP_TMDS:
2945                         outp->dcb->type = DCB_OUTPUT_TMDS;
2946                         outp->dcb->duallink_possible = outp->outp.info.tmds.dual;
2947                         break;
2948                 case NVIF_OUTP_LVDS:
2949                         outp->dcb->type = DCB_OUTPUT_LVDS;
2950                         outp->dcb->lvdsconf.use_acpi_for_edid = outp->outp.info.lvds.acpi_edid;
2951                         break;
2952                 case NVIF_OUTP_DP:
2953                         outp->dcb->type = DCB_OUTPUT_DP;
2954                         outp->dcb->dpconf.link_nr = outp->outp.info.dp.link_nr;
2955                         outp->dcb->dpconf.link_bw = outp->outp.info.dp.link_bw;
2956                         if (outp->outp.info.dp.mst)
2957                                 has_mst = true;
2958                         break;
2959                 default:
2960                         WARN_ON(1);
2961                         continue;
2962                 }
2963
2964                 outp->dcb->heads = outp->outp.info.heads;
2965                 outp->dcb->connector = outp->outp.info.conn;
2966                 outp->dcb->i2c_index = outp->outp.info.ddc;
2967
2968                 switch (outp->outp.info.type) {
2969                 case NVIF_OUTP_DAC : ret = nv50_dac_create(outp); break;
2970                 case NVIF_OUTP_SOR : ret = nv50_sor_create(outp); break;
2971                 case NVIF_OUTP_PIOR: ret = nv50_pior_create(outp); break;
2972                 default:
2973                         WARN_ON(1);
2974                         continue;
2975                 }
2976
2977                 if (ret) {
2978                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2979                                 i, outp->outp.info.type, outp->outp.info.proto, ret);
2980                 }
2981         }
2982
2983         /* cull any connectors we created that don't have an encoder */
2984         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2985                 if (connector->possible_encoders)
2986                         continue;
2987
2988                 NV_WARN(drm, "%s has no encoders, removing\n",
2989                         connector->name);
2990                 connector->funcs->destroy(connector);
2991         }
2992
2993         /* create crtc objects to represent the hw heads */
2994         for_each_set_bit(i, &disp->disp->head_mask, sizeof(disp->disp->head_mask) * 8) {
2995                 struct nv50_head *head;
2996
2997                 head = nv50_head_create(dev, i);
2998                 if (IS_ERR(head)) {
2999                         ret = PTR_ERR(head);
3000                         goto out;
3001                 }
3002
3003                 if (has_mst) {
3004                         head->msto = nv50_msto_new(dev, head, i);
3005                         if (IS_ERR(head->msto)) {
3006                                 ret = PTR_ERR(head->msto);
3007                                 head->msto = NULL;
3008                                 goto out;
3009                         }
3010
3011                         /*
3012                          * FIXME: This is a hack to workaround the following
3013                          * issues:
3014                          *
3015                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
3016                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
3017                          *
3018                          * Once these issues are closed, this should be
3019                          * removed
3020                          */
3021                         head->msto->encoder.possible_crtcs = disp->disp->head_mask;
3022                 }
3023         }
3024
3025         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
3026         dev->vblank_disable_immediate = true;
3027
3028         nv50_audio_component_init(drm);
3029
3030 out:
3031         if (ret)
3032                 nv50_display_destroy(dev);
3033         return ret;
3034 }
3035
3036 /******************************************************************************
3037  * Format modifiers
3038  *****************************************************************************/
3039
3040 /****************************************************************
3041  *            Log2(block height) ----------------------------+  *
3042  *            Page Kind ----------------------------------+  |  *
3043  *            Gob Height/Page Kind Generation ------+     |  |  *
3044  *                          Sector layout -------+  |     |  |  *
3045  *                          Compression ------+  |  |     |  |  */
3046 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
3047         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
3048         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
3049         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
3050         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
3051         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
3052         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
3053         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
3054         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
3055         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
3056         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
3057         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
3058         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
3059         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
3060         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
3061         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
3062         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
3063         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
3064         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
3065         DRM_FORMAT_MOD_LINEAR,
3066         DRM_FORMAT_MOD_INVALID
3067 };
3068
3069 /****************************************************************
3070  *            Log2(block height) ----------------------------+  *
3071  *            Page Kind ----------------------------------+  |  *
3072  *            Gob Height/Page Kind Generation ------+     |  |  *
3073  *                          Sector layout -------+  |     |  |  *
3074  *                          Compression ------+  |  |     |  |  */
3075 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
3076         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
3077         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
3078         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
3079         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
3080         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
3081         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
3082         DRM_FORMAT_MOD_LINEAR,
3083         DRM_FORMAT_MOD_INVALID
3084 };