1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/cpufreq.h>
14 #include <linux/module.h>
15 #include <linux/component.h>
16 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/list.h>
21 #include <linux/iommu.h>
22 #include <linux/types.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_device.h>
25 #include <linux/sizes.h>
26 #include <linux/kthread.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/msm_drm.h>
34 #include <drm/drm_gem.h>
41 struct msm_perf_state;
42 struct msm_gem_submit;
43 struct msm_fence_context;
44 struct msm_gem_address_space;
49 #define MAX_ENCODERS 8
51 #define MAX_CONNECTORS 8
53 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
55 struct msm_file_private {
57 struct list_head submitqueues;
59 struct msm_gem_address_space *aspace;
63 enum msm_mdp_plane_property {
66 PLANE_PROP_PREMULTIPLIED,
70 #define MSM_GPU_MAX_RINGS 4
71 #define MAX_H_TILES_PER_DISPLAY 2
74 * enum msm_display_caps - features/capabilities supported by displays
75 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
76 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
77 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
78 * @MSM_DISPLAY_CAP_EDID: EDID supported
80 enum msm_display_caps {
81 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
82 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
83 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
84 MSM_DISPLAY_CAP_EDID = BIT(3),
88 * enum msm_event_wait - type of HW events to wait for
89 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
90 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
91 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
94 MSM_ENC_COMMIT_DONE = 0,
100 * struct msm_display_topology - defines a display topology pipeline
101 * @num_lm: number of layer mixers used
102 * @num_enc: number of compression encoder blocks used
103 * @num_intf: number of interfaces the panel is mounted on
105 struct msm_display_topology {
113 * struct msm_display_info - defines display properties
114 * @intf_type: DRM_MODE_ENCODER_ type
115 * @capabilities: Bitmask of display flags
116 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
117 * @h_tile_instance: Controller instance used per tile. Number of elements is
118 * based on num_of_h_tiles
119 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
120 * used instead of panel TE in cmd mode panels
122 struct msm_display_info {
124 uint32_t capabilities;
125 uint32_t num_of_h_tiles;
126 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
127 bool is_te_using_watchdog_timer;
130 /* Commit/Event thread specific structure */
131 struct msm_drm_thread {
132 struct drm_device *dev;
133 unsigned int crtc_id;
134 struct kthread_worker *worker;
137 struct msm_drm_private {
139 struct drm_device *dev;
143 /* subordinate devices, if present: */
144 struct platform_device *gpu_pdev;
146 /* top level MDSS wrapper device (for MDP5/DPU only) */
147 struct msm_mdss *mdss;
149 /* possibly this should be in the kms component, but it is
150 * shared by both mdp4 and mdp5..
154 /* eDP is for mdp5 only, but kms has not been created
155 * when edp_bind() and edp_init() are called. Here is the only
156 * place to keep the edp instance.
160 /* DSI is shared by mdp4 and mdp5 */
161 struct msm_dsi *dsi[2];
165 /* when we have more than one 'msm_gpu' these need to be an array: */
167 struct msm_file_private *lastctx;
168 /* gpu is only set on open(), but we need this info earlier */
171 struct drm_fb_helper *fbdev;
173 struct msm_rd_state *rd; /* debugfs to dump all submits */
174 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
175 struct msm_perf_state *perf;
177 /* list of GEM objects: */
178 struct list_head inactive_list;
180 /* worker for delayed free of objects: */
181 struct work_struct free_work;
182 struct llist_head free_list;
184 struct workqueue_struct *wq;
186 unsigned int num_planes;
187 struct drm_plane *planes[MAX_PLANES];
189 unsigned int num_crtcs;
190 struct drm_crtc *crtcs[MAX_CRTCS];
192 struct msm_drm_thread event_thread[MAX_CRTCS];
194 unsigned int num_encoders;
195 struct drm_encoder *encoders[MAX_ENCODERS];
197 unsigned int num_bridges;
198 struct drm_bridge *bridges[MAX_BRIDGES];
200 unsigned int num_connectors;
201 struct drm_connector *connectors[MAX_CONNECTORS];
204 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
206 /* VRAM carveout, used when no IOMMU: */
210 /* NOTE: mm managed at the page level, size is in # of pages
211 * and position mm_node->start is in # of pages:
214 spinlock_t lock; /* Protects drm_mm node allocation/removal */
217 struct notifier_block vmap_notifier;
218 struct shrinker shrinker;
220 struct drm_atomic_state *pm_state;
224 uint32_t pixel_format;
227 struct msm_pending_timer;
229 int msm_atomic_prepare_fb(struct drm_plane *plane,
230 struct drm_plane_state *new_state);
231 void msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
232 struct msm_kms *kms, int crtc_idx);
233 void msm_atomic_commit_tail(struct drm_atomic_state *state);
234 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
235 void msm_atomic_state_clear(struct drm_atomic_state *state);
236 void msm_atomic_state_free(struct drm_atomic_state *state);
238 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
239 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
241 int msm_gem_init_vma(struct msm_gem_address_space *aspace,
242 struct msm_gem_vma *vma, int npages,
243 u64 range_start, u64 range_end);
244 void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
245 struct msm_gem_vma *vma);
246 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
247 struct msm_gem_vma *vma);
248 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
249 struct msm_gem_vma *vma, int prot,
250 struct sg_table *sgt, int npages);
251 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
252 struct msm_gem_vma *vma);
255 struct msm_gem_address_space *
256 msm_gem_address_space_get(struct msm_gem_address_space *aspace);
258 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
260 struct msm_gem_address_space *
261 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
262 u64 va_start, u64 size);
264 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
265 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
267 bool msm_use_mmu(struct drm_device *dev);
269 void msm_gem_submit_free(struct msm_gem_submit *submit);
270 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
271 struct drm_file *file);
273 void msm_gem_shrinker_init(struct drm_device *dev);
274 void msm_gem_shrinker_cleanup(struct drm_device *dev);
276 int msm_gem_mmap_obj(struct drm_gem_object *obj,
277 struct vm_area_struct *vma);
278 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
279 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
280 int msm_gem_get_iova(struct drm_gem_object *obj,
281 struct msm_gem_address_space *aspace, uint64_t *iova);
282 int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
283 struct msm_gem_address_space *aspace, uint64_t *iova,
284 u64 range_start, u64 range_end);
285 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
286 struct msm_gem_address_space *aspace, uint64_t *iova);
287 uint64_t msm_gem_iova(struct drm_gem_object *obj,
288 struct msm_gem_address_space *aspace);
289 void msm_gem_unpin_iova(struct drm_gem_object *obj,
290 struct msm_gem_address_space *aspace);
291 struct page **msm_gem_get_pages(struct drm_gem_object *obj);
292 void msm_gem_put_pages(struct drm_gem_object *obj);
293 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
294 struct drm_mode_create_dumb *args);
295 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
296 uint32_t handle, uint64_t *offset);
297 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
298 void *msm_gem_prime_vmap(struct drm_gem_object *obj);
299 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
300 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
301 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
302 struct dma_buf_attachment *attach, struct sg_table *sg);
303 int msm_gem_prime_pin(struct drm_gem_object *obj);
304 void msm_gem_prime_unpin(struct drm_gem_object *obj);
305 void *msm_gem_get_vaddr(struct drm_gem_object *obj);
306 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
307 void msm_gem_put_vaddr(struct drm_gem_object *obj);
308 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
309 int msm_gem_sync_object(struct drm_gem_object *obj,
310 struct msm_fence_context *fctx, bool exclusive);
311 void msm_gem_active_get(struct drm_gem_object *obj, struct msm_gpu *gpu);
312 void msm_gem_active_put(struct drm_gem_object *obj);
313 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
314 int msm_gem_cpu_fini(struct drm_gem_object *obj);
315 void msm_gem_free_object(struct drm_gem_object *obj);
316 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
317 uint32_t size, uint32_t flags, uint32_t *handle, char *name);
318 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
319 uint32_t size, uint32_t flags);
320 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
321 uint32_t size, uint32_t flags);
322 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
323 uint32_t flags, struct msm_gem_address_space *aspace,
324 struct drm_gem_object **bo, uint64_t *iova);
325 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
326 uint32_t flags, struct msm_gem_address_space *aspace,
327 struct drm_gem_object **bo, uint64_t *iova);
328 void msm_gem_kernel_put(struct drm_gem_object *bo,
329 struct msm_gem_address_space *aspace, bool locked);
330 struct drm_gem_object *msm_gem_import(struct drm_device *dev,
331 struct dma_buf *dmabuf, struct sg_table *sgt);
332 void msm_gem_free_work(struct work_struct *work);
335 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
337 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
338 struct msm_gem_address_space *aspace);
339 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
340 struct msm_gem_address_space *aspace);
341 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
342 struct msm_gem_address_space *aspace, int plane);
343 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
344 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
345 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
346 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
347 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
348 int w, int h, int p, uint32_t format);
350 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
351 void msm_fbdev_free(struct drm_device *dev);
354 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
355 struct drm_encoder *encoder);
356 void __init msm_hdmi_register(void);
357 void __exit msm_hdmi_unregister(void);
360 void __init msm_edp_register(void);
361 void __exit msm_edp_unregister(void);
362 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
363 struct drm_encoder *encoder);
366 #ifdef CONFIG_DRM_MSM_DSI
367 void __init msm_dsi_register(void);
368 void __exit msm_dsi_unregister(void);
369 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
370 struct drm_encoder *encoder);
372 static inline void __init msm_dsi_register(void)
375 static inline void __exit msm_dsi_unregister(void)
378 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
379 struct drm_device *dev,
380 struct drm_encoder *encoder)
386 #ifdef CONFIG_DRM_MSM_DP
387 int __init msm_dp_register(void);
388 void __exit msm_dp_unregister(void);
389 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
390 struct drm_encoder *encoder);
391 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
392 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
393 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
394 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
395 struct drm_display_mode *mode,
396 struct drm_display_mode *adjusted_mode);
397 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
399 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
402 static inline int __init msm_dp_register(void)
406 static inline void __exit msm_dp_unregister(void)
409 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
410 struct drm_device *dev,
411 struct drm_encoder *encoder)
415 static inline int msm_dp_display_enable(struct msm_dp *dp,
416 struct drm_encoder *encoder)
420 static inline int msm_dp_display_disable(struct msm_dp *dp,
421 struct drm_encoder *encoder)
425 static inline void msm_dp_display_mode_set(struct msm_dp *dp,
426 struct drm_encoder *encoder,
427 struct drm_display_mode *mode,
428 struct drm_display_mode *adjusted_mode)
432 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
436 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
437 struct drm_minor *minor)
443 void __init msm_mdp_register(void);
444 void __exit msm_mdp_unregister(void);
445 void __init msm_dpu_register(void);
446 void __exit msm_dpu_unregister(void);
448 #ifdef CONFIG_DEBUG_FS
449 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
450 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
451 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
452 int msm_debugfs_late_init(struct drm_device *dev);
453 int msm_rd_debugfs_init(struct drm_minor *minor);
454 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
456 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
457 const char *fmt, ...);
458 int msm_perf_debugfs_init(struct drm_minor *minor);
459 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
461 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
463 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
464 struct msm_gem_submit *submit,
465 const char *fmt, ...) {}
466 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
467 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
470 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
472 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
474 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
475 const char *dbgname);
476 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
477 const char *dbgname);
478 void msm_writel(u32 data, void __iomem *addr);
479 u32 msm_readl(const void __iomem *addr);
481 struct msm_gpu_submitqueue;
482 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
483 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
485 int msm_submitqueue_create(struct drm_device *drm,
486 struct msm_file_private *ctx,
487 u32 prio, u32 flags, u32 *id);
488 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
489 struct drm_msm_submitqueue_query *args);
490 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
491 void msm_submitqueue_close(struct msm_file_private *ctx);
493 void msm_submitqueue_destroy(struct kref *kref);
495 static inline void __msm_file_private_destroy(struct kref *kref)
497 struct msm_file_private *ctx = container_of(kref,
498 struct msm_file_private, ref);
500 msm_gem_address_space_put(ctx->aspace);
504 static inline void msm_file_private_put(struct msm_file_private *ctx)
506 kref_put(&ctx->ref, __msm_file_private_destroy);
509 static inline struct msm_file_private *msm_file_private_get(
510 struct msm_file_private *ctx)
516 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
517 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
519 static inline int align_pitch(int width, int bpp)
521 int bytespp = (bpp + 7) / 8;
522 /* adreno needs pitch aligned to 32 pixels: */
523 return bytespp * ALIGN(width, 32);
526 /* for the generated headers: */
527 #define INVALID_IDX(idx) ({BUG(); 0;})
528 #define fui(x) ({BUG(); 0;})
529 #define util_float_to_half(x) ({BUG(); 0;})
532 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
534 /* for conditionally setting boolean flag(s): */
535 #define COND(bool, val) ((bool) ? (val) : 0)
537 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
539 ktime_t now = ktime_get();
540 unsigned long remaining_jiffies;
542 if (ktime_compare(*timeout, now) < 0) {
543 remaining_jiffies = 0;
545 ktime_t rem = ktime_sub(*timeout, now);
546 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
549 return remaining_jiffies;
552 #endif /* __MSM_DRV_H__ */