drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <asm/barrier.h>
   7 #include <drm/drmP.h>
   8 #include <drm/drm_atomic_helper.h>
   9 #include <drm/drm_plane_helper.h>
  10 #include <drm/drm_probe_helper.h>
  11 #include <linux/clk.h>
  12 #include <linux/pm_runtime.h>
  13 #include <soc/mediatek/smi.h>
  14
  15 #include "mtk_drm_drv.h"
  16 #include "mtk_drm_crtc.h"
  17 #include "mtk_drm_ddp.h"
  18 #include "mtk_drm_ddp_comp.h"
  19 #include "mtk_drm_gem.h"
  20 #include "mtk_drm_plane.h"
  21
  22 /**
  23  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  24  * @base: crtc object.
  25  * @enabled: records whether crtc_enable succeeded
  26  * @planes: array of 4 drm_plane structures, one for each overlay plane
  27  * @pending_planes: whether any plane has pending changes to be applied
  28  * @config_regs: memory mapped mmsys configuration register space
  29  * @mutex: handle to one of the ten disp_mutex streams
  30  * @ddp_comp_nr: number of components in ddp_comp
  31  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  32  */
  33 struct mtk_drm_crtc {
  34         struct drm_crtc                 base;
  35         bool                            enabled;
  36
  37         bool                            pending_needs_vblank;
  38         struct drm_pending_vblank_event *event;
  39
  40         struct drm_plane                *planes;
  41         unsigned int                    layer_nr;
  42         bool                            pending_planes;
  43
  44         void __iomem                    *config_regs;
  45         struct mtk_disp_mutex           *mutex;
  46         unsigned int                    ddp_comp_nr;
  47         struct mtk_ddp_comp             **ddp_comp;
  48 };
  49
  50 struct mtk_crtc_state {
  51         struct drm_crtc_state           base;
  52
  53         bool                            pending_config;
  54         unsigned int                    pending_width;
  55         unsigned int                    pending_height;
  56         unsigned int                    pending_vrefresh;
  57 };
  58
  59 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  60 {
  61         return container_of(c, struct mtk_drm_crtc, base);
  62 }
  63
  64 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  65 {
  66         return container_of(s, struct mtk_crtc_state, base);
  67 }
  68
  69 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  70 {
  71         struct drm_crtc *crtc = &mtk_crtc->base;
  72         unsigned long flags;
  73
  74         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  75         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  76         drm_crtc_vblank_put(crtc);
  77         mtk_crtc->event = NULL;
  78         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  79 }
  80
  81 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  82 {
  83         drm_crtc_handle_vblank(&mtk_crtc->base);
  84         if (mtk_crtc->pending_needs_vblank) {
  85                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
  86                 mtk_crtc->pending_needs_vblank = false;
  87         }
  88 }
  89
  90 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
  91 {
  92         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
  93         int i;
  94
  95         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
  96                 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
  97
  98         mtk_disp_mutex_put(mtk_crtc->mutex);
  99
 100         drm_crtc_cleanup(crtc);
 101 }
 102
 103 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 104 {
 105         struct mtk_crtc_state *state;
 106
 107         if (crtc->state) {
 108                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 109
 110                 state = to_mtk_crtc_state(crtc->state);
 111                 memset(state, 0, sizeof(*state));
 112         } else {
 113                 state = kzalloc(sizeof(*state), GFP_KERNEL);
 114                 if (!state)
 115                         return;
 116                 crtc->state = &state->base;
 117         }
 118
 119         state->base.crtc = crtc;
 120 }
 121
 122 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 123 {
 124         struct mtk_crtc_state *state;
 125
 126         state = kzalloc(sizeof(*state), GFP_KERNEL);
 127         if (!state)
 128                 return NULL;
 129
 130         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 131
 132         WARN_ON(state->base.crtc != crtc);
 133         state->base.crtc = crtc;
 134
 135         return &state->base;
 136 }
 137
 138 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 139                                        struct drm_crtc_state *state)
 140 {
 141         __drm_atomic_helper_crtc_destroy_state(state);
 142         kfree(to_mtk_crtc_state(state));
 143 }
 144
 145 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 146                                     const struct drm_display_mode *mode,
 147                                     struct drm_display_mode *adjusted_mode)
 148 {
 149         /* Nothing to do here, but this callback is mandatory. */
 150         return true;
 151 }
 152
 153 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 154 {
 155         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 156
 157         state->pending_width = crtc->mode.hdisplay;
 158         state->pending_height = crtc->mode.vdisplay;
 159         state->pending_vrefresh = crtc->mode.vrefresh;
 160         wmb();  /* Make sure the above parameters are set before update */
 161         state->pending_config = true;
 162 }
 163
 164 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 165 {
 166         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 167         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 168
 169         mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);
 170
 171         return 0;
 172 }
 173
 174 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 175 {
 176         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 177         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 178
 179         mtk_ddp_comp_disable_vblank(comp);
 180 }
 181
 182 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 183 {
 184         int ret;
 185         int i;
 186
 187         DRM_DEBUG_DRIVER("%s\n", __func__);
 188         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 189                 ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
 190                 if (ret) {
 191                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 192                         goto err;
 193                 }
 194         }
 195
 196         return 0;
 197 err:
 198         while (--i >= 0)
 199                 clk_disable(mtk_crtc->ddp_comp[i]->clk);
 200         return ret;
 201 }
 202
 203 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 204 {
 205         int i;
 206
 207         DRM_DEBUG_DRIVER("%s\n", __func__);
 208         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 209                 clk_disable(mtk_crtc->ddp_comp[i]->clk);
 210 }
 211
 212 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 213 {
 214         struct drm_crtc *crtc = &mtk_crtc->base;
 215         struct drm_connector *connector;
 216         struct drm_encoder *encoder;
 217         struct drm_connector_list_iter conn_iter;
 218         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 219         int ret;
 220         int i;
 221
 222         DRM_DEBUG_DRIVER("%s\n", __func__);
 223         if (WARN_ON(!crtc->state))
 224                 return -EINVAL;
 225
 226         width = crtc->state->adjusted_mode.hdisplay;
 227         height = crtc->state->adjusted_mode.vdisplay;
 228         vrefresh = crtc->state->adjusted_mode.vrefresh;
 229
 230         drm_for_each_encoder(encoder, crtc->dev) {
 231                 if (encoder->crtc != crtc)
 232                         continue;
 233
 234                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 235                 drm_for_each_connector_iter(connector, &conn_iter) {
 236                         if (connector->encoder != encoder)
 237                                 continue;
 238                         if (connector->display_info.bpc != 0 &&
 239                             bpc > connector->display_info.bpc)
 240                                 bpc = connector->display_info.bpc;
 241                 }
 242                 drm_connector_list_iter_end(&conn_iter);
 243         }
 244
 245         ret = pm_runtime_get_sync(crtc->dev->dev);
 246         if (ret < 0) {
 247                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 248                 return ret;
 249         }
 250
 251         ret = mtk_disp_mutex_prepare(mtk_crtc->mutex);
 252         if (ret < 0) {
 253                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 254                 goto err_pm_runtime_put;
 255         }
 256
 257         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 258         if (ret < 0) {
 259                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 260                 goto err_mutex_unprepare;
 261         }
 262
 263         DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
 264         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 265                 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
 266                                          mtk_crtc->ddp_comp[i]->id,
 267                                          mtk_crtc->ddp_comp[i + 1]->id);
 268                 mtk_disp_mutex_add_comp(mtk_crtc->mutex,
 269                                         mtk_crtc->ddp_comp[i]->id);
 270         }
 271         mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 272         mtk_disp_mutex_enable(mtk_crtc->mutex);
 273
 274         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 275                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 276
 277                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
 278                 mtk_ddp_comp_start(comp);
 279         }
 280
 281         /* Initially configure all planes */
 282         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 283                 struct drm_plane *plane = &mtk_crtc->planes[i];
 284                 struct mtk_plane_state *plane_state;
 285
 286                 plane_state = to_mtk_plane_state(plane->state);
 287                 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i,
 288                                           plane_state);
 289         }
 290
 291         return 0;
 292
 293 err_mutex_unprepare:
 294         mtk_disp_mutex_unprepare(mtk_crtc->mutex);
 295 err_pm_runtime_put:
 296         pm_runtime_put(crtc->dev->dev);
 297         return ret;
 298 }
 299
 300 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 301 {
 302         struct drm_device *drm = mtk_crtc->base.dev;
 303         int i;
 304
 305         DRM_DEBUG_DRIVER("%s\n", __func__);
 306         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 307                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 308         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 309                 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
 310                                            mtk_crtc->ddp_comp[i]->id);
 311         mtk_disp_mutex_disable(mtk_crtc->mutex);
 312         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 313                 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
 314                                               mtk_crtc->ddp_comp[i]->id,
 315                                               mtk_crtc->ddp_comp[i + 1]->id);
 316                 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
 317                                            mtk_crtc->ddp_comp[i]->id);
 318         }
 319         mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 320         mtk_crtc_ddp_clk_disable(mtk_crtc);
 321         mtk_disp_mutex_unprepare(mtk_crtc->mutex);
 322
 323         pm_runtime_put(drm->dev);
 324 }
 325
 326 static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
 327 {
 328         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 329         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 330         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 331         unsigned int i;
 332
 333         /*
 334          * TODO: instead of updating the registers here, we should prepare
 335          * working registers in atomic_commit and let the hardware command
 336          * queue update module registers on vblank.
 337          */
 338         if (state->pending_config) {
 339                 mtk_ddp_comp_config(comp, state->pending_width,
 340                                     state->pending_height,
 341                                     state->pending_vrefresh, 0);
 342
 343                 state->pending_config = false;
 344         }
 345
 346         if (mtk_crtc->pending_planes) {
 347                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 348                         struct drm_plane *plane = &mtk_crtc->planes[i];
 349                         struct mtk_plane_state *plane_state;
 350
 351                         plane_state = to_mtk_plane_state(plane->state);
 352
 353                         if (plane_state->pending.config) {
 354                                 mtk_ddp_comp_layer_config(comp, i, plane_state);
 355                                 plane_state->pending.config = false;
 356                         }
 357                 }
 358                 mtk_crtc->pending_planes = false;
 359         }
 360 }
 361
 362 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 363                                        struct drm_crtc_state *old_state)
 364 {
 365         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 366         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 367         int ret;
 368
 369         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 370
 371         ret = mtk_smi_larb_get(comp->larb_dev);
 372         if (ret) {
 373                 DRM_ERROR("Failed to get larb: %d\n", ret);
 374                 return;
 375         }
 376
 377         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 378         if (ret) {
 379                 mtk_smi_larb_put(comp->larb_dev);
 380                 return;
 381         }
 382
 383         drm_crtc_vblank_on(crtc);
 384         mtk_crtc->enabled = true;
 385 }
 386
 387 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 388                                         struct drm_crtc_state *old_state)
 389 {
 390         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 391         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 392         int i;
 393
 394         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 395         if (!mtk_crtc->enabled)
 396                 return;
 397
 398         /* Set all pending plane state to disabled */
 399         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 400                 struct drm_plane *plane = &mtk_crtc->planes[i];
 401                 struct mtk_plane_state *plane_state;
 402
 403                 plane_state = to_mtk_plane_state(plane->state);
 404                 plane_state->pending.enable = false;
 405                 plane_state->pending.config = true;
 406         }
 407         mtk_crtc->pending_planes = true;
 408
 409         /* Wait for planes to be disabled */
 410         drm_crtc_wait_one_vblank(crtc);
 411
 412         drm_crtc_vblank_off(crtc);
 413         mtk_crtc_ddp_hw_fini(mtk_crtc);
 414         mtk_smi_larb_put(comp->larb_dev);
 415
 416         mtk_crtc->enabled = false;
 417 }
 418
 419 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 420                                       struct drm_crtc_state *old_crtc_state)
 421 {
 422         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 423         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 424
 425         if (mtk_crtc->event && state->base.event)
 426                 DRM_ERROR("new event while there is still a pending event\n");
 427
 428         if (state->base.event) {
 429                 state->base.event->pipe = drm_crtc_index(crtc);
 430                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 431                 mtk_crtc->event = state->base.event;
 432                 state->base.event = NULL;
 433         }
 434 }
 435
 436 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 437                                       struct drm_crtc_state *old_crtc_state)
 438 {
 439         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 440         struct mtk_drm_private *priv = crtc->dev->dev_private;
 441         unsigned int pending_planes = 0;
 442         int i;
 443
 444         if (mtk_crtc->event)
 445                 mtk_crtc->pending_needs_vblank = true;
 446         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 447                 struct drm_plane *plane = &mtk_crtc->planes[i];
 448                 struct mtk_plane_state *plane_state;
 449
 450                 plane_state = to_mtk_plane_state(plane->state);
 451                 if (plane_state->pending.dirty) {
 452                         plane_state->pending.config = true;
 453                         plane_state->pending.dirty = false;
 454                         pending_planes |= BIT(i);
 455                 }
 456         }
 457         if (pending_planes)
 458                 mtk_crtc->pending_planes = true;
 459         if (crtc->state->color_mgmt_changed)
 460                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 461                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 462
 463         if (priv->data->shadow_register) {
 464                 mtk_disp_mutex_acquire(mtk_crtc->mutex);
 465                 mtk_crtc_ddp_config(crtc);
 466                 mtk_disp_mutex_release(mtk_crtc->mutex);
 467         }
 468 }
 469
 470 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 471         .set_config             = drm_atomic_helper_set_config,
 472         .page_flip              = drm_atomic_helper_page_flip,
 473         .destroy                = mtk_drm_crtc_destroy,
 474         .reset                  = mtk_drm_crtc_reset,
 475         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 476         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 477         .gamma_set              = drm_atomic_helper_legacy_gamma_set,
 478         .enable_vblank          = mtk_drm_crtc_enable_vblank,
 479         .disable_vblank         = mtk_drm_crtc_disable_vblank,
 480 };
 481
 482 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 483         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 484         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 485         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 486         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 487         .atomic_enable  = mtk_drm_crtc_atomic_enable,
 488         .atomic_disable = mtk_drm_crtc_atomic_disable,
 489 };
 490
 491 static int mtk_drm_crtc_init(struct drm_device *drm,
 492                              struct mtk_drm_crtc *mtk_crtc,
 493                              struct drm_plane *primary,
 494                              struct drm_plane *cursor, unsigned int pipe)
 495 {
 496         int ret;
 497
 498         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 499                                         &mtk_crtc_funcs, NULL);
 500         if (ret)
 501                 goto err_cleanup_crtc;
 502
 503         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 504
 505         return 0;
 506
 507 err_cleanup_crtc:
 508         drm_crtc_cleanup(&mtk_crtc->base);
 509         return ret;
 510 }
 511
 512 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
 513 {
 514         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 515         struct mtk_drm_private *priv = crtc->dev->dev_private;
 516
 517         if (!priv->data->shadow_register)
 518                 mtk_crtc_ddp_config(crtc);
 519
 520         mtk_drm_finish_page_flip(mtk_crtc);
 521 }
 522
 523 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 524                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 525 {
 526         struct mtk_drm_private *priv = drm_dev->dev_private;
 527         struct device *dev = drm_dev->dev;
 528         struct mtk_drm_crtc *mtk_crtc;
 529         enum drm_plane_type type;
 530         unsigned int zpos;
 531         int pipe = priv->num_pipes;
 532         int ret;
 533         int i;
 534
 535         if (!path)
 536                 return 0;
 537
 538         for (i = 0; i < path_len; i++) {
 539                 enum mtk_ddp_comp_id comp_id = path[i];
 540                 struct device_node *node;
 541
 542                 node = priv->comp_node[comp_id];
 543                 if (!node) {
 544                         dev_info(dev,
 545                                  "Not creating crtc %d because component %d is disabled or missing\n",
 546                                  pipe, comp_id);
 547                         return 0;
 548                 }
 549         }
 550
 551         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 552         if (!mtk_crtc)
 553                 return -ENOMEM;
 554
 555         mtk_crtc->config_regs = priv->config_regs;
 556         mtk_crtc->ddp_comp_nr = path_len;
 557         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 558                                                 sizeof(*mtk_crtc->ddp_comp),
 559                                                 GFP_KERNEL);
 560         if (!mtk_crtc->ddp_comp)
 561                 return -ENOMEM;
 562
 563         mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe);
 564         if (IS_ERR(mtk_crtc->mutex)) {
 565                 ret = PTR_ERR(mtk_crtc->mutex);
 566                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 567                 return ret;
 568         }
 569
 570         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 571                 enum mtk_ddp_comp_id comp_id = path[i];
 572                 struct mtk_ddp_comp *comp;
 573                 struct device_node *node;
 574
 575                 node = priv->comp_node[comp_id];
 576                 comp = priv->ddp_comp[comp_id];
 577                 if (!comp) {
 578                         dev_err(dev, "Component %pOF not initialized\n", node);
 579                         ret = -ENODEV;
 580                         goto unprepare;
 581                 }
 582
 583                 ret = clk_prepare(comp->clk);
 584                 if (ret) {
 585                         dev_err(dev,
 586                                 "Failed to prepare clock for component %pOF: %d\n",
 587                                 node, ret);
 588                         goto unprepare;
 589                 }
 590
 591                 mtk_crtc->ddp_comp[i] = comp;
 592         }
 593
 594         mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
 595         mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr,
 596                                         sizeof(struct drm_plane),
 597                                         GFP_KERNEL);
 598
 599         for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
 600                 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
 601                                 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
 602                                                 DRM_PLANE_TYPE_OVERLAY;
 603                 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
 604                                      BIT(pipe), type);
 605                 if (ret)
 606                         goto unprepare;
 607         }
 608
 609         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
 610                                 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
 611                                 NULL, pipe);
 612         if (ret < 0)
 613                 goto unprepare;
 614         drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
 615         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
 616         priv->num_pipes++;
 617
 618         return 0;
 619
 620 unprepare:
 621         while (--i >= 0)
 622                 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
 623
 624         return ret;
 625 }