drivers/gpu/drm/mcde/mcde_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <linux/clk.h>
   3 #include <linux/component.h>
   4 #include <linux/delay.h>
   5 #include <linux/io.h>
   6 #include <linux/mfd/syscon.h>
   7 #include <linux/module.h>
   8 #include <linux/of.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/regmap.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <video/mipi_display.h>
  13
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_bridge.h>
  16 #include <drm/drm_device.h>
  17 #include <drm/drm_drv.h>
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_mipi_dsi.h>
  20 #include <drm/drm_modeset_helper_vtables.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drm_print.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #include "mcde_drm.h"
  27 #include "mcde_dsi_regs.h"
  28
  29 #define DSI_DEFAULT_LP_FREQ_HZ  19200000
  30 #define DSI_DEFAULT_HS_FREQ_HZ  420160000
  31
  32 /* PRCMU DSI reset registers */
  33 #define PRCM_DSI_SW_RESET 0x324
  34 #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
  35 #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
  36 #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
  37
  38 struct mcde_dsi {
  39         struct device *dev;
  40         struct mcde *mcde;
  41         struct drm_bridge bridge;
  42         struct drm_panel *panel;
  43         struct drm_bridge *bridge_out;
  44         struct mipi_dsi_host dsi_host;
  45         struct mipi_dsi_device *mdsi;
  46         struct clk *hs_clk;
  47         struct clk *lp_clk;
  48         unsigned long hs_freq;
  49         unsigned long lp_freq;
  50         bool unused;
  51
  52         void __iomem *regs;
  53         struct regmap *prcmu;
  54 };
  55
  56 static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge)
  57 {
  58         return container_of(bridge, struct mcde_dsi, bridge);
  59 }
  60
  61 static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h)
  62 {
  63         return container_of(h, struct mcde_dsi, dsi_host);
  64 }
  65
  66 bool mcde_dsi_irq(struct mipi_dsi_device *mdsi)
  67 {
  68         struct mcde_dsi *d;
  69         u32 val;
  70         bool te_received = false;
  71
  72         d = host_to_mcde_dsi(mdsi->host);
  73
  74         dev_dbg(d->dev, "%s called\n", __func__);
  75
  76         val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);
  77         if (val)
  78                 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);
  79         if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
  80                 dev_dbg(d->dev, "direct command write completed\n");
  81         if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) {
  82                 te_received = true;
  83                 dev_dbg(d->dev, "direct command TE received\n");
  84         }
  85         if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED)
  86                 dev_err(d->dev, "direct command ACK ERR received\n");
  87         if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)
  88                 dev_err(d->dev, "direct command read ERR received\n");
  89         /* Mask off the ACK value and clear status */
  90         writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
  91
  92         val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);
  93         if (val)
  94                 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);
  95         if (val & DSI_CMD_MODE_STS_ERR_NO_TE)
  96                 /* This happens all the time (safe to ignore) */
  97                 dev_dbg(d->dev, "CMD mode no TE\n");
  98         if (val & DSI_CMD_MODE_STS_ERR_TE_MISS)
  99                 /* This happens all the time (safe to ignore) */
 100                 dev_dbg(d->dev, "CMD mode TE miss\n");
 101         if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN)
 102                 dev_err(d->dev, "CMD mode SD1 underrun\n");
 103         if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN)
 104                 dev_err(d->dev, "CMD mode SD2 underrun\n");
 105         if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD)
 106                 dev_err(d->dev, "CMD mode unwanted RD\n");
 107         writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
 108
 109         val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);
 110         if (val)
 111                 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);
 112         writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
 113
 114         val = readl(d->regs + DSI_TG_STS_FLAG);
 115         if (val)
 116                 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);
 117         writel(val, d->regs + DSI_TG_STS_CLR);
 118
 119         val = readl(d->regs + DSI_VID_MODE_STS_FLAG);
 120         if (val)
 121                 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val);
 122         if (val & DSI_VID_MODE_STS_VSG_RUNNING)
 123                 dev_dbg(d->dev, "VID mode VSG running\n");
 124         if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA)
 125                 dev_err(d->dev, "VID mode missing data\n");
 126         if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC)
 127                 dev_err(d->dev, "VID mode missing HSYNC\n");
 128         if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC)
 129                 dev_err(d->dev, "VID mode missing VSYNC\n");
 130         if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH)
 131                 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n");
 132         if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT)
 133                 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n");
 134         if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE |
 135                    DSI_VID_MODE_STS_ERR_LINEWRITE |
 136                    DSI_VID_MODE_STS_ERR_LONGREAD))
 137                 dev_err(d->dev, "VID mode read/write error\n");
 138         if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH)
 139                 dev_err(d->dev, "VID mode received packets differ from expected size\n");
 140         if (val & DSI_VID_MODE_STS_VSG_RECOVERY)
 141                 dev_err(d->dev, "VID mode VSG in recovery mode\n");
 142         writel(val, d->regs + DSI_VID_MODE_STS_CLR);
 143
 144         return te_received;
 145 }
 146
 147 static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d)
 148 {
 149         d->mcde->mdsi = d->mdsi;
 150
 151         d->mcde->video_mode = !!(d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO);
 152         /* Enable use of the TE signal for all command mode panels */
 153         d->mcde->te_sync = !d->mcde->video_mode;
 154 }
 155
 156 static int mcde_dsi_host_attach(struct mipi_dsi_host *host,
 157                                 struct mipi_dsi_device *mdsi)
 158 {
 159         struct mcde_dsi *d = host_to_mcde_dsi(host);
 160
 161         if (mdsi->lanes < 1 || mdsi->lanes > 2) {
 162                 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n");
 163                 return -EINVAL;
 164         }
 165
 166         dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);
 167         /* MIPI_DSI_FMT_RGB88 etc */
 168         dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format,
 169                  mipi_dsi_pixel_format_to_bpp(mdsi->format));
 170         dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags);
 171
 172         d->mdsi = mdsi;
 173         if (d->mcde)
 174                 mcde_dsi_attach_to_mcde(d);
 175
 176         return 0;
 177 }
 178
 179 static int mcde_dsi_host_detach(struct mipi_dsi_host *host,
 180                                 struct mipi_dsi_device *mdsi)
 181 {
 182         struct mcde_dsi *d = host_to_mcde_dsi(host);
 183
 184         d->mdsi = NULL;
 185         if (d->mcde)
 186                 d->mcde->mdsi = NULL;
 187
 188         return 0;
 189 }
 190
 191 #define MCDE_DSI_HOST_IS_READ(type)                         \
 192         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 193          (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 194          (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 195          (type == MIPI_DSI_DCS_READ))
 196
 197 static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host,
 198                                       const struct mipi_dsi_msg *msg)
 199 {
 200         struct mcde_dsi *d = host_to_mcde_dsi(host);
 201         const u32 loop_delay_us = 10; /* us */
 202         const u8 *tx = msg->tx_buf;
 203         u32 loop_counter;
 204         size_t txlen = msg->tx_len;
 205         size_t rxlen = msg->rx_len;
 206         u32 val;
 207         int ret;
 208         int i;
 209
 210         if (txlen > 16) {
 211                 dev_err(d->dev,
 212                         "dunno how to write more than 16 bytes yet\n");
 213                 return -EIO;
 214         }
 215         if (rxlen > 4) {
 216                 dev_err(d->dev,
 217                         "dunno how to read more than 4 bytes yet\n");
 218                 return -EIO;
 219         }
 220
 221         dev_dbg(d->dev,
 222                 "message to channel %d, write %zd bytes read %zd bytes\n",
 223                 msg->channel, txlen, rxlen);
 224
 225         /* Command "nature" */
 226         if (MCDE_DSI_HOST_IS_READ(msg->type))
 227                 /* MCTL_MAIN_DATA_CTL already set up */
 228                 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;
 229         else
 230                 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;
 231         /*
 232          * More than 2 bytes will not fit in a single packet, so it's
 233          * time to set the "long not short" bit. One byte is used by
 234          * the MIPI DCS command leaving just one byte for the payload
 235          * in a short package.
 236          */
 237         if (mipi_dsi_packet_format_is_long(msg->type))
 238                 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
 239         val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
 240         val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
 241         val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
 242         val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
 243         writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
 244
 245         /* MIPI DCS command is part of the data */
 246         if (txlen > 0) {
 247                 val = 0;
 248                 for (i = 0; i < 4 && i < txlen; i++)
 249                         val |= tx[i] << (i * 8);
 250         }
 251         writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
 252         if (txlen > 4) {
 253                 val = 0;
 254                 for (i = 0; i < 4 && (i + 4) < txlen; i++)
 255                         val |= tx[i + 4] << (i * 8);
 256                 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
 257         }
 258         if (txlen > 8) {
 259                 val = 0;
 260                 for (i = 0; i < 4 && (i + 8) < txlen; i++)
 261                         val |= tx[i + 8] << (i * 8);
 262                 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
 263         }
 264         if (txlen > 12) {
 265                 val = 0;
 266                 for (i = 0; i < 4 && (i + 12) < txlen; i++)
 267                         val |= tx[i + 12] << (i * 8);
 268                 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
 269         }
 270
 271         writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
 272         writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
 273         /* Send command */
 274         writel(1, d->regs + DSI_DIRECT_CMD_SEND);
 275
 276         loop_counter = 1000 * 1000 / loop_delay_us;
 277         if (MCDE_DSI_HOST_IS_READ(msg->type)) {
 278                 /* Read command */
 279                 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
 280                          (DSI_DIRECT_CMD_STS_READ_COMPLETED |
 281                           DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR))
 282                        && --loop_counter)
 283                         usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
 284                 if (!loop_counter) {
 285                         dev_err(d->dev, "DSI read timeout!\n");
 286                         return -ETIME;
 287                 }
 288         } else {
 289                 /* Writing only */
 290                 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
 291                          DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
 292                        && --loop_counter)
 293                         usleep_range(loop_delay_us, (loop_delay_us * 3) / 2);
 294
 295                 if (!loop_counter) {
 296                         dev_err(d->dev, "DSI write timeout!\n");
 297                         return -ETIME;
 298                 }
 299         }
 300
 301         val = readl(d->regs + DSI_DIRECT_CMD_STS);
 302         if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
 303                 dev_err(d->dev, "read completed with error\n");
 304                 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
 305                 return -EIO;
 306         }
 307         if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
 308                 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
 309                 dev_err(d->dev, "error during transmission: %04x\n",
 310                         val);
 311                 return -EIO;
 312         }
 313
 314         if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
 315                 /* Return number of bytes written */
 316                 ret = txlen;
 317         } else {
 318                 /* OK this is a read command, get the response */
 319                 u32 rdsz;
 320                 u32 rddat;
 321                 u8 *rx = msg->rx_buf;
 322
 323                 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
 324                 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK;
 325                 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
 326                 if (rdsz < rxlen) {
 327                         dev_err(d->dev, "read error, requested %zd got %d\n",
 328                                 rxlen, rdsz);
 329                         return -EIO;
 330                 }
 331                 /* FIXME: read more than 4 bytes */
 332                 for (i = 0; i < 4 && i < rxlen; i++)
 333                         rx[i] = (rddat >> (i * 8)) & 0xff;
 334                 ret = rdsz;
 335         }
 336
 337         writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
 338         writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
 339
 340         return ret;
 341 }
 342
 343 static const struct mipi_dsi_host_ops mcde_dsi_host_ops = {
 344         .attach = mcde_dsi_host_attach,
 345         .detach = mcde_dsi_host_detach,
 346         .transfer = mcde_dsi_host_transfer,
 347 };
 348
 349 /* This sends a direct (short) command to request TE */
 350 void mcde_dsi_te_request(struct mipi_dsi_device *mdsi)
 351 {
 352         struct mcde_dsi *d;
 353         u32 val;
 354
 355         d = host_to_mcde_dsi(mdsi->host);
 356
 357         /* Command "nature" TE request */
 358         val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ;
 359         val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
 360         val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
 361         val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
 362         val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM <<
 363                 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
 364         writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
 365
 366         /* Clear TE reveived and error status bits and enables them */
 367         writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR |
 368                DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR,
 369                d->regs + DSI_DIRECT_CMD_STS_CLR);
 370         val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);
 371         val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN;
 372         val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN;
 373         writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
 374
 375         /* Clear and enable no TE or TE missing status */
 376         writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR |
 377                DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR,
 378                d->regs + DSI_CMD_MODE_STS_CLR);
 379         val = readl(d->regs + DSI_CMD_MODE_STS_CTL);
 380         val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN;
 381         val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN;
 382         writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
 383
 384         /* Send this TE request command */
 385         writel(1, d->regs + DSI_DIRECT_CMD_SEND);
 386 }
 387
 388 static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
 389                                       const struct drm_display_mode *mode)
 390 {
 391         u8 bpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format);
 392         u64 bpl;
 393         u32 hfp;
 394         u32 hbp;
 395         u32 hsa;
 396         u32 blkline_pck, line_duration;
 397         u32 blkeol_pck, blkeol_duration;
 398         u32 val;
 399
 400         val = 0;
 401         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 402                 val |= DSI_VID_MAIN_CTL_BURST_MODE;
 403         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
 404                 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE;
 405                 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL;
 406         }
 407         /* RGB header and pixel mode */
 408         switch (d->mdsi->format) {
 409         case MIPI_DSI_FMT_RGB565:
 410                 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 <<
 411                         DSI_VID_MAIN_CTL_HEADER_SHIFT;
 412                 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS;
 413                 break;
 414         case MIPI_DSI_FMT_RGB666_PACKED:
 415                 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 <<
 416                         DSI_VID_MAIN_CTL_HEADER_SHIFT;
 417                 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS;
 418                 break;
 419         case MIPI_DSI_FMT_RGB666:
 420                 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18
 421                         << DSI_VID_MAIN_CTL_HEADER_SHIFT;
 422                 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE;
 423                 break;
 424         case MIPI_DSI_FMT_RGB888:
 425                 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 <<
 426                         DSI_VID_MAIN_CTL_HEADER_SHIFT;
 427                 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS;
 428                 break;
 429         default:
 430                 dev_err(d->dev, "unknown pixel mode\n");
 431                 return;
 432         }
 433
 434         /* TODO: TVG could be enabled here */
 435
 436         /* Send blanking packet */
 437         val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0;
 438         /* Send EOL packet */
 439         val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0;
 440         /* Recovery mode 1 */
 441         val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT;
 442         /* All other fields zero */
 443         writel(val, d->regs + DSI_VID_MAIN_CTL);
 444
 445         /* Vertical frame parameters are pretty straight-forward */
 446         val = mode->vdisplay << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;
 447         /* vertical front porch */
 448         val |= (mode->vsync_start - mode->vdisplay)
 449                 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT;
 450         /* vertical sync active */
 451         val |= (mode->vsync_end - mode->vsync_start)
 452                 << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
 453         /* vertical back porch */
 454         val |= (mode->vtotal - mode->vsync_end)
 455                 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT;
 456         writel(val, d->regs + DSI_VID_VSIZE);
 457
 458         /*
 459          * Horizontal frame parameters:
 460          * horizontal resolution is given in pixels and must be re-calculated
 461          * into bytes since this is what the hardware expects.
 462          *
 463          * 6 + 2 is HFP header + checksum
 464          */
 465         hfp = (mode->hsync_start - mode->hdisplay) * bpp - 6 - 2;
 466         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
 467                 /*
 468                  * 6 is HBP header + checksum
 469                  * 4 is RGB header + checksum
 470                  */
 471                 hbp = (mode->htotal - mode->hsync_end) * bpp - 4 - 6;
 472                 /*
 473                  * 6 is HBP header + checksum
 474                  * 4 is HSW packet bytes
 475                  * 4 is RGB header + checksum
 476                  */
 477                 hsa = (mode->hsync_end - mode->hsync_start) * bpp - 4 - 4 - 6;
 478         } else {
 479                 /*
 480                  * HBP includes both back porch and sync
 481                  * 6 is HBP header + checksum
 482                  * 4 is HSW packet bytes
 483                  * 4 is RGB header + checksum
 484                  */
 485                 hbp = (mode->htotal - mode->hsync_start) * bpp - 4 - 4 - 6;
 486                 /* HSA is not considered in this mode and set to 0 */
 487                 hsa = 0;
 488         }
 489         dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u\n",
 490                 hfp, hbp, hsa);
 491
 492         /* Frame parameters: horizontal sync active */
 493         val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT;
 494         /* horizontal back porch */
 495         val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT;
 496         /* horizontal front porch */
 497         val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT;
 498         writel(val, d->regs + DSI_VID_HSIZE1);
 499
 500         /* RGB data length (bytes on one scanline) */
 501         val = mode->hdisplay * (bpp / 8);
 502         writel(val, d->regs + DSI_VID_HSIZE2);
 503
 504         /* TODO: further adjustments for TVG mode here */
 505
 506         /*
 507          * EOL packet length from bits per line calculations: pixel clock
 508          * is given in kHz, calculate the time between two pixels in
 509          * picoseconds.
 510          */
 511         bpl = mode->clock * mode->htotal;
 512         bpl *= (d->hs_freq / 8);
 513         do_div(bpl, 1000000); /* microseconds */
 514         do_div(bpl, 1000000); /* seconds */
 515         bpl *= d->mdsi->lanes;
 516         dev_dbg(d->dev, "calculated bytes per line: %llu\n", bpl);
 517         /*
 518          * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes
 519          * 4 is short packet for vsync/hsync
 520          */
 521         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
 522                 /* Fixme: isn't the hsync width in pixels? */
 523                 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6;
 524                 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT;
 525                 writel(val, d->regs + DSI_VID_BLKSIZE2);
 526         } else {
 527                 blkline_pck = bpl - 4 - 6;
 528                 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT;
 529                 writel(val, d->regs + DSI_VID_BLKSIZE1);
 530         }
 531
 532         line_duration = (blkline_pck + 6) / d->mdsi->lanes;
 533         dev_dbg(d->dev, "line duration %u\n", line_duration);
 534         val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;
 535         /*
 536          * This is the time to perform LP->HS on D-PHY
 537          * FIXME: nowhere to get this from: DT property on the DSI?
 538          */
 539         val |= 0 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
 540         writel(val, d->regs + DSI_VID_DPHY_TIME);
 541
 542         /* Calculate block end of line */
 543         blkeol_pck = bpl - mode->hdisplay * bpp - 6;
 544         blkeol_duration = (blkeol_pck + 6) / d->mdsi->lanes;
 545         dev_dbg(d->dev, "blkeol pck: %u, duration: %u\n",
 546                  blkeol_pck, blkeol_duration);
 547
 548         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 549                 /* Set up EOL clock for burst mode */
 550                 val = readl(d->regs + DSI_VID_BLKSIZE1);
 551                 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;
 552                 writel(val, d->regs + DSI_VID_BLKSIZE1);
 553                 writel(blkeol_pck, d->regs + DSI_VID_VCA_SETTING2);
 554
 555                 writel(blkeol_duration, d->regs + DSI_VID_PCK_TIME);
 556                 writel(blkeol_duration - 6, d->regs + DSI_VID_VCA_SETTING1);
 557         }
 558
 559         /* Maximum line limit */
 560         val = readl(d->regs + DSI_VID_VCA_SETTING2);
 561         val |= blkline_pck <<
 562                 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT;
 563         writel(val, d->regs + DSI_VID_VCA_SETTING2);
 564
 565 }
 566
 567 static void mcde_dsi_start(struct mcde_dsi *d)
 568 {
 569         unsigned long hs_freq;
 570         u32 val;
 571         int i;
 572
 573         /* No integration mode */
 574         writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);
 575
 576         /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */
 577         val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN |
 578                 DSI_MCTL_MAIN_DATA_CTL_BTA_EN |
 579                 DSI_MCTL_MAIN_DATA_CTL_READ_EN |
 580                 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN;
 581         if (d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
 582                 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN;
 583         writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
 584
 585         /* Set a high command timeout, clear other fields */
 586         val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT;
 587         writel(val, d->regs + DSI_CMD_MODE_CTL);
 588
 589         /*
 590          * UI_X4 is described as "unit interval times four"
 591          * I guess since DSI packets are 4 bytes wide, one unit
 592          * is one byte.
 593          */
 594         hs_freq = clk_get_rate(d->hs_clk);
 595         hs_freq /= 1000000; /* MHz */
 596         val = 4000 / hs_freq;
 597         dev_dbg(d->dev, "UI value: %d\n", val);
 598         val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT;
 599         val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK;
 600         writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
 601
 602         /*
 603          * Enable clocking: 0x0f (something?) between each burst,
 604          * enable the second lane if needed, enable continuous clock if
 605          * needed, enable switch into ULPM (ultra-low power mode) on
 606          * all the lines.
 607          */
 608         val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT;
 609         if (d->mdsi->lanes == 2)
 610                 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN;
 611         if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
 612                 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS;
 613         val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN |
 614                 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN |
 615                 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN;
 616         writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
 617
 618         val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) |
 619                 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT);
 620         writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
 621
 622         writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,
 623                d->regs + DSI_DPHY_LANES_TRIM);
 624
 625         /* High PHY timeout */
 626         val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) |
 627                 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) |
 628                 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT);
 629         writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
 630
 631         val = DSI_MCTL_MAIN_EN_PLL_START |
 632                 DSI_MCTL_MAIN_EN_CKLANE_EN |
 633                 DSI_MCTL_MAIN_EN_DAT1_EN |
 634                 DSI_MCTL_MAIN_EN_IF1_EN;
 635         if (d->mdsi->lanes == 2)
 636                 val |= DSI_MCTL_MAIN_EN_DAT2_EN;
 637         writel(val, d->regs + DSI_MCTL_MAIN_EN);
 638
 639         /* Wait for the PLL to lock and the clock and data lines to come up */
 640         i = 0;
 641         val = DSI_MCTL_MAIN_STS_PLL_LOCK |
 642                 DSI_MCTL_MAIN_STS_CLKLANE_READY |
 643                 DSI_MCTL_MAIN_STS_DAT1_READY;
 644         if (d->mdsi->lanes == 2)
 645                 val |= DSI_MCTL_MAIN_STS_DAT2_READY;
 646         while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {
 647                 /* Sleep for a millisecond */
 648                 usleep_range(1000, 1500);
 649                 if (i++ == 100) {
 650                         dev_warn(d->dev, "DSI lanes did not start up\n");
 651                         return;
 652                 }
 653         }
 654
 655         /* TODO needed? */
 656
 657         /* Command mode, clear IF1 ID */
 658         val = readl(d->regs + DSI_CMD_MODE_CTL);
 659         /*
 660          * If we enable low-power mode here, with
 661          * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
 662          * then display updates become really slow.
 663          */
 664         val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
 665         writel(val, d->regs + DSI_CMD_MODE_CTL);
 666
 667         /* Wait for DSI PHY to initialize */
 668         usleep_range(100, 200);
 669         dev_info(d->dev, "DSI link enabled\n");
 670 }
 671
 672
 673 static void mcde_dsi_bridge_enable(struct drm_bridge *bridge)
 674 {
 675         struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
 676         u32 val;
 677
 678         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 679                 /* Enable video mode */
 680                 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
 681                 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
 682                 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
 683         }
 684
 685         dev_info(d->dev, "enable DSI master\n");
 686 };
 687
 688 static void mcde_dsi_bridge_pre_enable(struct drm_bridge *bridge)
 689 {
 690         struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
 691         unsigned long hs_freq, lp_freq;
 692         u32 val;
 693         int ret;
 694
 695         /* Copy maximum clock frequencies */
 696         if (d->mdsi->lp_rate)
 697                 lp_freq = d->mdsi->lp_rate;
 698         else
 699                 lp_freq = DSI_DEFAULT_LP_FREQ_HZ;
 700         if (d->mdsi->hs_rate)
 701                 hs_freq = d->mdsi->hs_rate;
 702         else
 703                 hs_freq = DSI_DEFAULT_HS_FREQ_HZ;
 704
 705         /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */
 706         d->lp_freq = clk_round_rate(d->lp_clk, lp_freq);
 707         ret = clk_set_rate(d->lp_clk, d->lp_freq);
 708         if (ret)
 709                 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n",
 710                         d->lp_freq);
 711
 712         d->hs_freq = clk_round_rate(d->hs_clk, hs_freq);
 713         ret = clk_set_rate(d->hs_clk, d->hs_freq);
 714         if (ret)
 715                 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n",
 716                         d->hs_freq);
 717
 718         /* Start clocks */
 719         ret = clk_prepare_enable(d->lp_clk);
 720         if (ret)
 721                 dev_err(d->dev, "failed to enable LP clock\n");
 722         else
 723                 dev_info(d->dev, "DSI LP clock rate %lu Hz\n",
 724                          d->lp_freq);
 725         ret = clk_prepare_enable(d->hs_clk);
 726         if (ret)
 727                 dev_err(d->dev, "failed to enable HS clock\n");
 728         else
 729                 dev_info(d->dev, "DSI HS clock rate %lu Hz\n",
 730                          d->hs_freq);
 731
 732         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 733                 /* Put IF1 into video mode */
 734                 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
 735                 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE;
 736                 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
 737
 738                 /* Disable command mode on IF1 */
 739                 val = readl(d->regs + DSI_CMD_MODE_CTL);
 740                 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN;
 741                 writel(val, d->regs + DSI_CMD_MODE_CTL);
 742
 743                 /* Enable some error interrupts */
 744                 val = readl(d->regs + DSI_VID_MODE_STS_CTL);
 745                 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;
 746                 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;
 747                 writel(val, d->regs + DSI_VID_MODE_STS_CTL);
 748         } else {
 749                 /* Command mode, clear IF1 ID */
 750                 val = readl(d->regs + DSI_CMD_MODE_CTL);
 751                 /*
 752                  * If we enable low-power mode here with
 753                  * val |= DSI_CMD_MODE_CTL_IF1_LP_EN
 754                  * the display updates become really slow.
 755                  */
 756                 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
 757                 writel(val, d->regs + DSI_CMD_MODE_CTL);
 758         }
 759 }
 760
 761 static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge,
 762                                      const struct drm_display_mode *mode,
 763                                      const struct drm_display_mode *adj)
 764 {
 765         struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
 766
 767         if (!d->mdsi) {
 768                 dev_err(d->dev, "no DSI device attached to encoder!\n");
 769                 return;
 770         }
 771
 772         dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n",
 773                  mode->hdisplay, mode->vdisplay, mode->clock * 1000,
 774                  (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD"
 775                 );
 776
 777         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
 778                 mcde_dsi_setup_video_mode(d, mode);
 779 }
 780
 781 static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d)
 782 {
 783         u32 val;
 784         int i;
 785
 786         /*
 787          * Wait until we get out of command mode
 788          * CSM = Command State Machine
 789          */
 790         i = 0;
 791         val = DSI_CMD_MODE_STS_CSM_RUNNING;
 792         while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {
 793                 /* Sleep for a millisecond */
 794                 usleep_range(1000, 2000);
 795                 if (i++ == 100) {
 796                         dev_warn(d->dev,
 797                                  "could not get out of command mode\n");
 798                         return;
 799                 }
 800         }
 801 }
 802
 803 static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d)
 804 {
 805         u32 val;
 806         int i;
 807
 808         /* Wait until we get out og video mode */
 809         i = 0;
 810         val = DSI_VID_MODE_STS_VSG_RUNNING;
 811         while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {
 812                 /* Sleep for a millisecond */
 813                 usleep_range(1000, 2000);
 814                 if (i++ == 100) {
 815                         dev_warn(d->dev,
 816                                  "could not get out of video mode\n");
 817                         return;
 818                 }
 819         }
 820 }
 821
 822 static void mcde_dsi_bridge_disable(struct drm_bridge *bridge)
 823 {
 824         struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
 825         u32 val;
 826
 827         /* Disable all error interrupts */
 828         writel(0, d->regs + DSI_VID_MODE_STS_CTL);
 829
 830         if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 831                 /* Stop video mode */
 832                 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
 833                 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN;
 834                 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
 835                 mcde_dsi_wait_for_video_mode_stop(d);
 836         } else {
 837                 /* Stop command mode */
 838                 mcde_dsi_wait_for_command_mode_stop(d);
 839         }
 840
 841         /* Stop clocks */
 842         clk_disable_unprepare(d->hs_clk);
 843         clk_disable_unprepare(d->lp_clk);
 844 }
 845
 846 static int mcde_dsi_bridge_attach(struct drm_bridge *bridge)
 847 {
 848         struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
 849         struct drm_device *drm = bridge->dev;
 850         int ret;
 851
 852         if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {
 853                 dev_err(d->dev, "we need atomic updates\n");
 854                 return -ENOTSUPP;
 855         }
 856
 857         /* Attach the DSI bridge to the output (panel etc) bridge */
 858         ret = drm_bridge_attach(bridge->encoder, d->bridge_out, bridge);
 859         if (ret) {
 860                 dev_err(d->dev, "failed to attach the DSI bridge\n");
 861                 return ret;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = {
 868         .attach = mcde_dsi_bridge_attach,
 869         .mode_set = mcde_dsi_bridge_mode_set,
 870         .disable = mcde_dsi_bridge_disable,
 871         .enable = mcde_dsi_bridge_enable,
 872         .pre_enable = mcde_dsi_bridge_pre_enable,
 873 };
 874
 875 static int mcde_dsi_bind(struct device *dev, struct device *master,
 876                          void *data)
 877 {
 878         struct drm_device *drm = data;
 879         struct mcde *mcde = drm->dev_private;
 880         struct mcde_dsi *d = dev_get_drvdata(dev);
 881         struct device_node *child;
 882         struct drm_panel *panel = NULL;
 883         struct drm_bridge *bridge = NULL;
 884
 885         if (!of_get_available_child_count(dev->of_node)) {
 886                 dev_info(dev, "unused DSI interface\n");
 887                 d->unused = true;
 888                 return 0;
 889         }
 890         d->mcde = mcde;
 891         /* If the display attached before binding, set this up */
 892         if (d->mdsi)
 893                 mcde_dsi_attach_to_mcde(d);
 894
 895         /* Obtain the clocks */
 896         d->hs_clk = devm_clk_get(dev, "hs");
 897         if (IS_ERR(d->hs_clk)) {
 898                 dev_err(dev, "unable to get HS clock\n");
 899                 return PTR_ERR(d->hs_clk);
 900         }
 901
 902         d->lp_clk = devm_clk_get(dev, "lp");
 903         if (IS_ERR(d->lp_clk)) {
 904                 dev_err(dev, "unable to get LP clock\n");
 905                 return PTR_ERR(d->lp_clk);
 906         }
 907
 908         /* Assert RESET through the PRCMU, active low */
 909         /* FIXME: which DSI block? */
 910         regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
 911                            PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
 912
 913         usleep_range(100, 200);
 914
 915         /* De-assert RESET again */
 916         regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
 917                            PRCM_DSI_SW_RESET_DSI0_SW_RESETN,
 918                            PRCM_DSI_SW_RESET_DSI0_SW_RESETN);
 919
 920         /* Start up the hardware */
 921         mcde_dsi_start(d);
 922
 923         /* Look for a panel as a child to this node */
 924         for_each_available_child_of_node(dev->of_node, child) {
 925                 panel = of_drm_find_panel(child);
 926                 if (IS_ERR(panel)) {
 927                         dev_err(dev, "failed to find panel try bridge (%ld)\n",
 928                                 PTR_ERR(panel));
 929                         panel = NULL;
 930
 931                         bridge = of_drm_find_bridge(child);
 932                         if (IS_ERR(bridge)) {
 933                                 dev_err(dev, "failed to find bridge (%ld)\n",
 934                                         PTR_ERR(bridge));
 935                                 return PTR_ERR(bridge);
 936                         }
 937                 }
 938         }
 939         if (panel) {
 940                 bridge = drm_panel_bridge_add_typed(panel,
 941                                                     DRM_MODE_CONNECTOR_DSI);
 942                 if (IS_ERR(bridge)) {
 943                         dev_err(dev, "error adding panel bridge\n");
 944                         return PTR_ERR(bridge);
 945                 }
 946                 dev_info(dev, "connected to panel\n");
 947                 d->panel = panel;
 948         } else if (bridge) {
 949                 /* TODO: AV8100 HDMI encoder goes here for example */
 950                 dev_info(dev, "connected to non-panel bridge (unsupported)\n");
 951                 return -ENODEV;
 952         } else {
 953                 dev_err(dev, "no panel or bridge\n");
 954                 return -ENODEV;
 955         }
 956
 957         d->bridge_out = bridge;
 958
 959         /* Create a bridge for this DSI channel */
 960         d->bridge.funcs = &mcde_dsi_bridge_funcs;
 961         d->bridge.of_node = dev->of_node;
 962         drm_bridge_add(&d->bridge);
 963
 964         /* TODO: first come first serve, use a list */
 965         mcde->bridge = &d->bridge;
 966
 967         dev_info(dev, "initialized MCDE DSI bridge\n");
 968
 969         return 0;
 970 }
 971
 972 static void mcde_dsi_unbind(struct device *dev, struct device *master,
 973                             void *data)
 974 {
 975         struct mcde_dsi *d = dev_get_drvdata(dev);
 976
 977         if (d->panel)
 978                 drm_panel_bridge_remove(d->bridge_out);
 979         regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
 980                            PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
 981 }
 982
 983 static const struct component_ops mcde_dsi_component_ops = {
 984         .bind   = mcde_dsi_bind,
 985         .unbind = mcde_dsi_unbind,
 986 };
 987
 988 static int mcde_dsi_probe(struct platform_device *pdev)
 989 {
 990         struct device *dev = &pdev->dev;
 991         struct mcde_dsi *d;
 992         struct mipi_dsi_host *host;
 993         struct resource *res;
 994         u32 dsi_id;
 995         int ret;
 996
 997         d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
 998         if (!d)
 999                 return -ENOMEM;
1000         d->dev = dev;
1001         platform_set_drvdata(pdev, d);
1002
1003         /* Get a handle on the PRCMU so we can do reset */
1004         d->prcmu =
1005                 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu");
1006         if (IS_ERR(d->prcmu)) {
1007                 dev_err(dev, "no PRCMU regmap\n");
1008                 return PTR_ERR(d->prcmu);
1009         }
1010
1011         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012         d->regs = devm_ioremap_resource(dev, res);
1013         if (IS_ERR(d->regs)) {
1014                 dev_err(dev, "no DSI regs\n");
1015                 return PTR_ERR(d->regs);
1016         }
1017
1018         dsi_id = readl(d->regs + DSI_ID_REG);
1019         dev_info(dev, "HW revision 0x%08x\n", dsi_id);
1020
1021         host = &d->dsi_host;
1022         host->dev = dev;
1023         host->ops = &mcde_dsi_host_ops;
1024         ret = mipi_dsi_host_register(host);
1025         if (ret < 0) {
1026                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1027                 return ret;
1028         }
1029         dev_info(dev, "registered DSI host\n");
1030
1031         platform_set_drvdata(pdev, d);
1032         return component_add(dev, &mcde_dsi_component_ops);
1033 }
1034
1035 static int mcde_dsi_remove(struct platform_device *pdev)
1036 {
1037         struct mcde_dsi *d = platform_get_drvdata(pdev);
1038
1039         component_del(&pdev->dev, &mcde_dsi_component_ops);
1040         mipi_dsi_host_unregister(&d->dsi_host);
1041
1042         return 0;
1043 }
1044
1045 static const struct of_device_id mcde_dsi_of_match[] = {
1046         {
1047                 .compatible = "ste,mcde-dsi",
1048         },
1049         {},
1050 };
1051
1052 struct platform_driver mcde_dsi_driver = {
1053         .driver = {
1054                 .name           = "mcde-dsi",
1055                 .of_match_table = of_match_ptr(mcde_dsi_of_match),
1056         },
1057         .probe = mcde_dsi_probe,
1058         .remove = mcde_dsi_remove,
1059 };