2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/sched/clock.h>
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_dp_dual_mode_helper.h>
35 #include <drm/drm_dp_mst_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_rect.h>
40 #include <drm/drm_vblank.h>
41 #include <drm/i915_drm.h>
42 #include <drm/i915_mei_hdcp_interface.h>
43 #include <media/cec-notifier.h>
50 * Display related stuff
53 /* these are outputs from the chip - integrated only
54 external chips are via DVO or SDVO output */
55 enum intel_output_type {
56 INTEL_OUTPUT_UNUSED = 0,
57 INTEL_OUTPUT_ANALOG = 1,
59 INTEL_OUTPUT_SDVO = 3,
60 INTEL_OUTPUT_LVDS = 4,
61 INTEL_OUTPUT_TVOUT = 5,
62 INTEL_OUTPUT_HDMI = 6,
66 INTEL_OUTPUT_DDI = 10,
67 INTEL_OUTPUT_DP_MST = 11,
70 struct intel_framebuffer {
71 struct drm_framebuffer base;
72 struct intel_rotation_info rot_info;
74 /* for each plane in the normal GTT view */
78 /* for each plane in the rotated GTT view */
81 unsigned int pitch; /* pixels */
86 struct drm_fb_helper helper;
87 struct intel_framebuffer *fb;
89 unsigned long vma_flags;
90 async_cookie_t cookie;
93 /* Whether or not fbdev hpd processing is temporarily suspended */
94 bool hpd_suspended : 1;
95 /* Set when a hotplug was received while HPD processing was
100 /* Protects hpd_suspended */
101 struct mutex hpd_lock;
104 struct intel_encoder {
105 struct drm_encoder base;
107 enum intel_output_type type;
109 unsigned int cloneable;
110 bool (*hotplug)(struct intel_encoder *encoder,
111 struct intel_connector *connector);
112 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
113 struct intel_crtc_state *,
114 struct drm_connector_state *);
115 int (*compute_config)(struct intel_encoder *,
116 struct intel_crtc_state *,
117 struct drm_connector_state *);
118 void (*pre_pll_enable)(struct intel_encoder *,
119 const struct intel_crtc_state *,
120 const struct drm_connector_state *);
121 void (*pre_enable)(struct intel_encoder *,
122 const struct intel_crtc_state *,
123 const struct drm_connector_state *);
124 void (*enable)(struct intel_encoder *,
125 const struct intel_crtc_state *,
126 const struct drm_connector_state *);
127 void (*disable)(struct intel_encoder *,
128 const struct intel_crtc_state *,
129 const struct drm_connector_state *);
130 void (*post_disable)(struct intel_encoder *,
131 const struct intel_crtc_state *,
132 const struct drm_connector_state *);
133 void (*post_pll_disable)(struct intel_encoder *,
134 const struct intel_crtc_state *,
135 const struct drm_connector_state *);
136 void (*update_pipe)(struct intel_encoder *,
137 const struct intel_crtc_state *,
138 const struct drm_connector_state *);
139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
143 /* Reconstructs the equivalent mode flags for the current hardware
144 * state. This must be called _after_ display->get_pipe_config has
145 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
146 * be set correctly before calling this function. */
147 void (*get_config)(struct intel_encoder *,
148 struct intel_crtc_state *pipe_config);
150 * Acquires the power domains needed for an active encoder during
151 * hardware state readout.
153 void (*get_power_domains)(struct intel_encoder *encoder,
154 struct intel_crtc_state *crtc_state);
156 * Called during system suspend after all pending requests for the
157 * encoder are flushed (for example for DP AUX transactions) and
158 * device interrupts are disabled.
160 void (*suspend)(struct intel_encoder *);
162 enum hpd_pin hpd_pin;
163 enum intel_display_power_domain power_domain;
164 /* for communication with audio component; protected by av_mutex */
165 const struct drm_connector *audio_connector;
169 struct drm_display_mode *fixed_mode;
170 struct drm_display_mode *downclock_mode;
179 bool combination_mode; /* gen 2/4 only */
181 bool alternate_pwm_increment; /* lpt+ */
184 bool util_pin_active_low; /* bxt+ */
185 u8 controller; /* bxt+ only */
186 struct pwm_device *pwm;
188 struct backlight_device *device;
190 /* Connector and platform specific backlight functions */
191 int (*setup)(struct intel_connector *connector, enum pipe pipe);
192 u32 (*get)(struct intel_connector *connector);
193 void (*set)(const struct drm_connector_state *conn_state, u32 level);
194 void (*disable)(const struct drm_connector_state *conn_state);
195 void (*enable)(const struct intel_crtc_state *crtc_state,
196 const struct drm_connector_state *conn_state);
197 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
198 void (*power)(struct intel_connector *, bool enable);
202 struct intel_digital_port;
204 enum check_link_response {
205 HDCP_LINK_PROTECTED = 0,
206 HDCP_TOPOLOGY_CHANGE,
207 HDCP_LINK_INTEGRITY_FAILURE,
212 * This structure serves as a translation layer between the generic HDCP code
213 * and the bus-specific code. What that means is that HDCP over HDMI differs
214 * from HDCP over DP, so to account for these differences, we need to
215 * communicate with the receiver through this shim.
217 * For completeness, the 2 buses differ in the following ways:
219 * HDCP registers on the receiver are set via DP AUX for DP, and
220 * they are set via DDC for HDMI.
221 * - Receiver register offsets
222 * The offsets of the registers are different for DP vs. HDMI
223 * - Receiver register masks/offsets
224 * For instance, the ready bit for the KSV fifo is in a different
225 * place on DP vs HDMI
226 * - Receiver register names
227 * Seriously. In the DP spec, the 16-bit register containing
228 * downstream information is called BINFO, on HDMI it's called
229 * BSTATUS. To confuse matters further, DP has a BSTATUS register
230 * with a completely different definition.
232 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
233 * be read 3 keys at a time
235 * Since Aksv is hidden in hardware, there's different procedures
236 * to send it over DP AUX vs DDC
238 struct intel_hdcp_shim {
239 /* Outputs the transmitter's An and Aksv values to the receiver. */
240 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
242 /* Reads the receiver's key selection vector */
243 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
246 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
247 * definitions are the same in the respective specs, but the names are
248 * different. Call it BSTATUS since that's the name the HDMI spec
249 * uses and it was there first.
251 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
254 /* Determines whether a repeater is present downstream */
255 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
256 bool *repeater_present);
258 /* Reads the receiver's Ri' value */
259 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
261 /* Determines if the receiver's KSV FIFO is ready for consumption */
262 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
265 /* Reads the ksv fifo for num_downstream devices */
266 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
267 int num_downstream, u8 *ksv_fifo);
269 /* Reads a 32-bit part of V' from the receiver */
270 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
273 /* Enables HDCP signalling on the port */
274 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
277 /* Ensures the link is still protected */
278 bool (*check_link)(struct intel_digital_port *intel_dig_port);
280 /* Detects panel's hdcp capability. This is optional for HDMI. */
281 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
284 /* HDCP adaptation(DP/HDMI) required on the port */
285 enum hdcp_wired_protocol protocol;
287 /* Detects whether sink is HDCP2.2 capable */
288 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
291 /* Write HDCP2.2 messages */
292 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
293 void *buf, size_t size);
295 /* Read HDCP2.2 messages */
296 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
297 u8 msg_id, void *buf, size_t size);
300 * Implementation of DP HDCP2.2 Errata for the communication of stream
301 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
302 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
304 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
305 bool is_repeater, u8 type);
307 /* HDCP2.2 Link Integrity Check */
308 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
312 const struct intel_hdcp_shim *shim;
313 /* Mutex for hdcp state of the connector */
316 struct delayed_work check_work;
317 struct work_struct prop_work;
319 /* HDCP1.4 Encryption status */
322 /* HDCP2.2 related definitions */
323 /* Flag indicates whether this connector supports HDCP2.2 or not. */
324 bool hdcp2_supported;
326 /* HDCP2.2 Encryption status */
327 bool hdcp2_encrypted;
330 * Content Stream Type defined by content owner. TYPE0(0x0) content can
331 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
332 * content can flow only through a link protected by HDCP2.2.
335 struct hdcp_port_data port_data;
341 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
342 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
343 * When it rolls over re-auth has to be triggered.
348 * Count of RepeaterAuth_Stream_Manage msg propagated.
349 * Initialized to 0 on AKE_INIT. Incremented after every successful
350 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
351 * over re-Auth has to be triggered.
356 * Work queue to signal the CP_IRQ. Used for the waiters to read the
357 * available information from HDCP DP sink.
359 wait_queue_head_t cp_irq_queue;
360 atomic_t cp_irq_count;
361 int cp_irq_count_cached;
364 struct intel_connector {
365 struct drm_connector base;
367 * The fixed encoder this connector is connected to.
369 struct intel_encoder *encoder;
371 /* ACPI device id for ACPI and driver cooperation */
374 /* Reads out the current hw, returning true if the connector is enabled
375 * and active (i.e. dpms ON state). */
376 bool (*get_hw_state)(struct intel_connector *);
378 /* Panel info for eDP and LVDS */
379 struct intel_panel panel;
381 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
383 struct edid *detect_edid;
385 /* since POLL and HPD connectors may use the same HPD line keep the native
386 state of connector->polled in case hotplug storm detection changes it */
389 void *port; /* store this opaque as its illegal to dereference it */
391 struct intel_dp *mst_port;
393 /* Work struct to schedule a uevent on link train failure */
394 struct work_struct modeset_retry_work;
396 struct intel_hdcp hdcp;
399 struct intel_digital_connector_state {
400 struct drm_connector_state base;
402 enum hdmi_force_audio force_audio;
406 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
420 struct intel_atomic_state {
421 struct drm_atomic_state base;
425 * Logical state of cdclk (used for all scaling, watermark,
426 * etc. calculations and checks). This is computed as if all
427 * enabled crtcs were active.
429 struct intel_cdclk_state logical;
432 * Actual state of cdclk, can be different from the logical
433 * state only when all crtc's are DPMS off.
435 struct intel_cdclk_state actual;
438 bool force_min_cdclk_changed;
439 /* pipe to which cd2x update is synchronized */
443 bool dpll_set, modeset;
446 * Does this transaction change the pipes that are active? This mask
447 * tracks which CRTC's have changed their active state at the end of
448 * the transaction (not counting the temporary disable during modesets).
449 * This mask should only be non-zero when intel_state->modeset is true,
450 * but the converse is not necessarily true; simply changing a mode may
451 * not flip the final active status of any CRTC's
453 unsigned int active_pipe_changes;
455 unsigned int active_crtcs;
456 /* minimum acceptable cdclk for each pipe */
457 int min_cdclk[I915_MAX_PIPES];
458 /* minimum acceptable voltage level for each pipe */
459 u8 min_voltage_level[I915_MAX_PIPES];
461 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
464 * Current watermarks can't be trusted during hardware readout, so
465 * don't bother calculating intermediate watermarks.
467 bool skip_intermediate_wm;
469 bool rps_interactive;
472 struct skl_ddb_values wm_results;
474 struct i915_sw_fence commit_ready;
476 struct llist_node freed;
479 struct intel_plane_state {
480 struct drm_plane_state base;
481 struct i915_ggtt_view view;
482 struct i915_vma *vma;
484 #define PLANE_HAS_FENCE BIT(0)
490 * bytes for 0/180 degree rotation
491 * pixels for 90/270 degree rotation
497 /* plane control register */
500 /* plane color control register */
505 * = -1 : not using a scaler
506 * >= 0 : using a scalers
508 * plane requiring a scaler:
509 * - During check_plane, its bit is set in
510 * crtc_state->scaler_state.scaler_users by calling helper function
511 * update_scaler_plane.
512 * - scaler_id indicates the scaler it got assigned.
514 * plane doesn't require a scaler:
515 * - this can happen when scaling is no more required or plane simply
517 * - During check_plane, corresponding bit is reset in
518 * crtc_state->scaler_state.scaler_users by calling helper function
519 * update_scaler_plane.
526 * ICL planar formats require 2 planes that are updated as pairs.
527 * This member is used to make sure the other plane is also updated
528 * when required, and for update_slave() to find the correct
529 * plane_state to pass as argument.
531 struct intel_plane *linked_plane;
535 * If set don't update use the linked plane's state for updating
536 * this plane during atomic commit with the update_slave() callback.
538 * It's also used by the watermark code to ignore wm calculations on
539 * this plane. They're calculated by the linked plane's wm code.
543 struct drm_intel_sprite_colorkey ckey;
546 struct intel_initial_plane_config {
547 struct intel_framebuffer *fb;
554 struct intel_scaler {
559 struct intel_crtc_scaler_state {
560 #define SKL_NUM_SCALERS 2
561 struct intel_scaler scalers[SKL_NUM_SCALERS];
564 * scaler_users: keeps track of users requesting scalers on this crtc.
566 * If a bit is set, a user is using a scaler.
567 * Here user can be a plane or crtc as defined below:
568 * bits 0-30 - plane (bit position is index from drm_plane_index)
571 * Instead of creating a new index to cover planes and crtc, using
572 * existing drm_plane_index for planes which is well less than 31
573 * planes and bit 31 for crtc. This should be fine to cover all
576 * intel_atomic_setup_scalers will setup available scalers to users
577 * requesting scalers. It will gracefully fail if request exceeds
580 #define SKL_CRTC_INDEX 31
581 unsigned scaler_users;
583 /* scaler used by crtc for panel fitting purpose */
587 /* drm_mode->private_flags */
588 #define I915_MODE_FLAG_INHERITED (1<<0)
589 /* Flag to get scanline using frame time stamps */
590 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
591 /* Flag to use the scanline counter instead of the pixel counter */
592 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
594 struct intel_pipe_wm {
595 struct intel_wm_level wm[5];
599 bool sprites_enabled;
603 struct skl_plane_wm {
604 struct skl_wm_level wm[8];
605 struct skl_wm_level uv_wm[8];
606 struct skl_wm_level trans_wm;
611 struct skl_plane_wm planes[I915_MAX_PLANES];
618 VLV_WM_LEVEL_DDR_DVFS,
622 struct vlv_wm_state {
623 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
624 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
629 struct vlv_fifo_state {
630 u16 plane[I915_MAX_PLANES];
640 struct g4x_wm_state {
641 struct g4x_pipe_wm wm;
643 struct g4x_sr_wm hpll;
649 struct intel_crtc_wm_state {
653 * Intermediate watermarks; these can be
654 * programmed immediately since they satisfy
655 * both the current configuration we're
656 * switching away from and the new
657 * configuration we're switching to.
659 struct intel_pipe_wm intermediate;
662 * Optimal watermarks, programmed post-vblank
663 * when this state is committed.
665 struct intel_pipe_wm optimal;
669 /* gen9+ only needs 1-step wm programming */
670 struct skl_pipe_wm optimal;
671 struct skl_ddb_entry ddb;
672 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
673 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
677 /* "raw" watermarks (not inverted) */
678 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
679 /* intermediate watermarks (inverted) */
680 struct vlv_wm_state intermediate;
681 /* optimal watermarks (inverted) */
682 struct vlv_wm_state optimal;
683 /* display FIFO split */
684 struct vlv_fifo_state fifo_state;
688 /* "raw" watermarks */
689 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
690 /* intermediate watermarks */
691 struct g4x_wm_state intermediate;
692 /* optimal watermarks */
693 struct g4x_wm_state optimal;
698 * Platforms with two-step watermark programming will need to
699 * update watermark programming post-vblank to switch from the
700 * safe intermediate watermarks to the optimal final
703 bool need_postvbl_update;
706 enum intel_output_format {
707 INTEL_OUTPUT_FORMAT_INVALID,
708 INTEL_OUTPUT_FORMAT_RGB,
709 INTEL_OUTPUT_FORMAT_YCBCR420,
710 INTEL_OUTPUT_FORMAT_YCBCR444,
713 struct intel_crtc_state {
714 struct drm_crtc_state base;
717 * quirks - bitfield with hw state readout quirks
719 * For various reasons the hw state readout code might not be able to
720 * completely faithfully read out the current state. These cases are
721 * tracked with quirk flags so that fastboot and state checker can act
724 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
725 unsigned long quirks;
727 unsigned fb_bits; /* framebuffers to flip */
728 bool update_pipe; /* can a fast modeset be performed? */
730 bool update_wm_pre, update_wm_post; /* watermarks are updated */
731 bool fb_changed; /* fb on any of the planes is changed */
732 bool fifo_changed; /* FIFO split is changed */
734 /* Pipe source size (ie. panel fitter input size)
735 * All planes will be positioned inside this space,
736 * and get clipped at the edges. */
737 int pipe_src_w, pipe_src_h;
740 * Pipe pixel rate, adjusted for
741 * panel fitter/pipe scaler downscaling.
743 unsigned int pixel_rate;
745 /* Whether to set up the PCH/FDI. Note that we never allow sharing
746 * between pch encoders and cpu encoders. */
747 bool has_pch_encoder;
749 /* Are we sending infoframes on the attached port */
752 /* CPU Transcoder for the pipe. Currently this can only differ from the
753 * pipe on Haswell and later (where we have a special eDP transcoder)
754 * and Broxton (where we have special DSI transcoders). */
755 enum transcoder cpu_transcoder;
758 * Use reduced/limited/broadcast rbg range, compressing from the full
759 * range fed into the crtcs.
761 bool limited_color_range;
763 /* Bitmask of encoder types (enum intel_output_type)
764 * driven by the pipe.
766 unsigned int output_types;
768 /* Whether we should send NULL infoframes. Required for audio. */
771 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
772 * has_dp_encoder is set. */
776 * Enable dithering, used when the selected pipe bpp doesn't match the
782 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
783 * compliance video pattern tests.
784 * Disable dither only if it is a compliance test request for
787 bool dither_force_disable;
789 /* Controls for the clock computation, to override various stages. */
792 /* SDVO TV has a bunch of special case. To make multifunction encoders
793 * work correctly, we need to track this at runtime.*/
797 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
798 * required. This is set in the 2nd loop of calling encoder's
799 * ->compute_config if the first pick doesn't work out.
803 /* Settings for the intel dpll used on pretty much everything but
807 /* Selected dpll when shared or NULL. */
808 struct intel_shared_dpll *shared_dpll;
810 /* Actual register state of the dpll, for shared dpll cross-checking. */
811 struct intel_dpll_hw_state dpll_hw_state;
813 /* DSI PLL registers */
819 struct intel_link_m_n dp_m_n;
821 /* m2_n2 for eDP downclock */
822 struct intel_link_m_n dp_m2_n2;
829 * Frequence the dpll for the port should run at. Differs from the
830 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
831 * already multiplied by pixel_multiplier.
835 /* Used by SDVO (and if we ever fix it, HDMI). */
836 unsigned pixel_multiplier;
841 * Used by platforms having DP/HDMI PHY with programmable lane
842 * latency optimization.
844 u8 lane_lat_optim_mask;
846 /* minimum acceptable voltage level */
847 u8 min_voltage_level;
849 /* Panel fitter controls for gen2-gen4 + VLV */
853 u32 lvds_border_bits;
856 /* Panel fitter placement and size for Ironlake+ */
864 /* FDI configuration, only valid if has_pch_encoder is set. */
866 struct intel_link_m_n fdi_m_n;
878 struct intel_crtc_scaler_state scaler_state;
880 /* w/a for waiting 2 vblanks during crtc enable */
881 enum pipe hsw_workaround_pipe;
883 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
886 struct intel_crtc_wm_state wm;
888 u32 data_rate[I915_MAX_PLANES];
890 /* Gamma mode programmed on the pipe */
894 /* CSC mode programmed on the pipe */
901 /* bitmask of visible planes (enum plane_id) */
906 /* bitmask of planes that will be updated during the commit */
912 union hdmi_infoframe avi;
913 union hdmi_infoframe spd;
914 union hdmi_infoframe hdmi;
917 /* HDMI scrambling status */
918 bool hdmi_scrambling;
920 /* HDMI High TMDS char rate ratio */
921 bool hdmi_high_tmds_clock_ratio;
923 /* Output format RGB/YCBCR etc */
924 enum intel_output_format output_format;
926 /* Output down scaling is done in LSPCON device */
927 bool lspcon_downsampling;
929 /* enable pipe gamma? */
932 /* enable pipe csc? */
935 /* Display Stream compression state */
937 bool compression_enable;
942 struct drm_dsc_config dp_dsc_cfg;
944 /* Forward Error correction State */
949 struct drm_crtc base;
952 * Whether the crtc and the connected output pipeline is active. Implies
953 * that crtc->enabled is set, i.e. the current mode configuration has
954 * some outputs connected to this crtc.
958 unsigned long long enabled_power_domains;
959 struct intel_overlay *overlay;
961 struct intel_crtc_state *config;
963 /* Access to these should be protected by dev_priv->irq_lock. */
964 bool cpu_fifo_underrun_disabled;
965 bool pch_fifo_underrun_disabled;
967 /* per-pipe watermark state */
969 /* watermarks currently being used */
971 struct intel_pipe_wm ilk;
972 struct vlv_wm_state vlv;
973 struct g4x_wm_state g4x;
980 unsigned start_vbl_count;
981 ktime_t start_vbl_time;
982 int min_vbl, max_vbl;
986 /* scalers available on this crtc */
991 struct drm_plane base;
992 enum i9xx_plane_id i9xx_plane;
1000 u32 base, cntl, size;
1004 * NOTE: Do not place new plane state fields here (e.g., when adding
1005 * new plane properties). New runtime state should now be placed in
1006 * the intel_plane_state structure and accessed via plane_state.
1009 unsigned int (*max_stride)(struct intel_plane *plane,
1010 u32 pixel_format, u64 modifier,
1011 unsigned int rotation);
1012 void (*update_plane)(struct intel_plane *plane,
1013 const struct intel_crtc_state *crtc_state,
1014 const struct intel_plane_state *plane_state);
1015 void (*update_slave)(struct intel_plane *plane,
1016 const struct intel_crtc_state *crtc_state,
1017 const struct intel_plane_state *plane_state);
1018 void (*disable_plane)(struct intel_plane *plane,
1019 const struct intel_crtc_state *crtc_state);
1020 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1021 int (*check_plane)(struct intel_crtc_state *crtc_state,
1022 struct intel_plane_state *plane_state);
1025 struct intel_watermark_params {
1033 struct cxsr_latency {
1034 bool is_desktop : 1;
1039 u16 display_hpll_disable;
1041 u16 cursor_hpll_disable;
1044 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1045 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1046 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1047 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1048 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1049 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1050 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1051 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1052 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1055 i915_reg_t hdmi_reg;
1058 enum drm_dp_dual_mode_type type;
1063 struct intel_connector *attached_connector;
1064 struct cec_notifier *cec_notifier;
1067 struct intel_dp_mst_encoder;
1068 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1071 * enum link_m_n_set:
1072 * When platform provides two set of M_N registers for dp, we can
1073 * program them and switch between them incase of DRRS.
1074 * But When only one such register is provided, we have to program the
1075 * required divider value on that registers itself based on the DRRS state.
1077 * M1_N1 : Program dp_m_n on M1_N1 registers
1078 * dp_m2_n2 on M2_N2 registers (If supported)
1080 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1081 * M2_N2 registers are not supported
1085 /* Sets the m1_n1 and m2_n2 */
1090 struct intel_dp_compliance_data {
1093 u16 hdisplay, vdisplay;
1097 struct intel_dp_compliance {
1098 unsigned long test_type;
1099 struct intel_dp_compliance_data test_data;
1106 i915_reg_t output_reg;
1114 bool reset_link_params;
1115 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1116 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1117 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1118 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1119 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1122 int num_source_rates;
1123 const int *source_rates;
1124 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1126 int sink_rates[DP_MAX_SUPPORTED_RATES];
1127 bool use_rate_select;
1128 /* intersection of source and sink rates */
1129 int num_common_rates;
1130 int common_rates[DP_MAX_SUPPORTED_RATES];
1131 /* Max lane count for the current link */
1132 int max_link_lane_count;
1133 /* Max rate for the current link */
1135 /* sink or branch descriptor */
1136 struct drm_dp_desc desc;
1137 struct drm_dp_aux aux;
1139 int panel_power_up_delay;
1140 int panel_power_down_delay;
1141 int panel_power_cycle_delay;
1142 int backlight_on_delay;
1143 int backlight_off_delay;
1144 struct delayed_work panel_vdd_work;
1145 bool want_panel_vdd;
1146 unsigned long last_power_on;
1147 unsigned long last_backlight_off;
1148 ktime_t panel_power_off_time;
1150 struct notifier_block edp_notifier;
1153 * Pipe whose power sequencer is currently locked into
1154 * this port. Only relevant on VLV/CHV.
1158 * Pipe currently driving the port. Used for preventing
1159 * the use of the PPS for any pipe currentrly driving
1160 * external DP as that will mess things up on VLV.
1162 enum pipe active_pipe;
1164 * Set if the sequencer may be reset due to a power transition,
1165 * requiring a reinitialization. Only relevant on BXT.
1168 struct edp_power_seq pps_delays;
1170 bool can_mst; /* this port supports mst */
1172 int active_mst_links;
1173 /* connector directly attached - won't be use for modeset in mst world */
1174 struct intel_connector *attached_connector;
1176 /* mst connector list */
1177 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1178 struct drm_dp_mst_topology_mgr mst_mgr;
1180 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1182 * This function returns the value we have to program the AUX_CTL
1183 * register with to kick off an AUX transaction.
1185 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1186 u32 aux_clock_divider);
1188 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1189 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1191 /* This is called before a link training is starterd */
1192 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1194 /* Displayport compliance testing */
1195 struct intel_dp_compliance compliance;
1197 /* Display stream compression testing */
1201 enum lspcon_vendor {
1203 LSPCON_VENDOR_PARADE
1206 struct intel_lspcon {
1208 enum drm_lspcon_mode mode;
1209 enum lspcon_vendor vendor;
1212 struct intel_digital_port {
1213 struct intel_encoder base;
1214 u32 saved_port_bits;
1216 struct intel_hdmi hdmi;
1217 struct intel_lspcon lspcon;
1218 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1219 bool release_cl2_override;
1221 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1223 enum intel_display_power_domain ddi_io_power_domain;
1224 bool tc_legacy_port:1;
1225 enum tc_port_type tc_type;
1227 void (*write_infoframe)(struct intel_encoder *encoder,
1228 const struct intel_crtc_state *crtc_state,
1230 const void *frame, ssize_t len);
1231 void (*read_infoframe)(struct intel_encoder *encoder,
1232 const struct intel_crtc_state *crtc_state,
1234 void *frame, ssize_t len);
1235 void (*set_infoframes)(struct intel_encoder *encoder,
1237 const struct intel_crtc_state *crtc_state,
1238 const struct drm_connector_state *conn_state);
1239 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1240 const struct intel_crtc_state *pipe_config);
1243 struct intel_dp_mst_encoder {
1244 struct intel_encoder base;
1246 struct intel_digital_port *primary;
1247 struct intel_connector *connector;
1250 static inline enum dpio_channel
1251 vlv_dport_to_channel(struct intel_digital_port *dport)
1253 switch (dport->base.port) {
1264 static inline enum dpio_phy
1265 vlv_dport_to_phy(struct intel_digital_port *dport)
1267 switch (dport->base.port) {
1278 static inline enum dpio_channel
1279 vlv_pipe_to_channel(enum pipe pipe)
1292 static inline struct intel_crtc *
1293 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1295 return dev_priv->pipe_to_crtc_mapping[pipe];
1298 static inline struct intel_crtc *
1299 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1301 return dev_priv->plane_to_crtc_mapping[plane];
1304 struct intel_load_detect_pipe {
1305 struct drm_atomic_state *restore_state;
1308 static inline struct intel_encoder *
1309 intel_attached_encoder(struct drm_connector *connector)
1311 return to_intel_connector(connector)->encoder;
1314 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1316 switch (encoder->type) {
1317 case INTEL_OUTPUT_DDI:
1318 case INTEL_OUTPUT_DP:
1319 case INTEL_OUTPUT_EDP:
1320 case INTEL_OUTPUT_HDMI:
1327 static inline struct intel_digital_port *
1328 enc_to_dig_port(struct drm_encoder *encoder)
1330 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1332 if (intel_encoder_is_dig_port(intel_encoder))
1333 return container_of(encoder, struct intel_digital_port,
1339 static inline struct intel_digital_port *
1340 conn_to_dig_port(struct intel_connector *connector)
1342 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1345 static inline struct intel_dp_mst_encoder *
1346 enc_to_mst(struct drm_encoder *encoder)
1348 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1351 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1353 return &enc_to_dig_port(encoder)->dp;
1356 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1358 switch (encoder->type) {
1359 case INTEL_OUTPUT_DP:
1360 case INTEL_OUTPUT_EDP:
1362 case INTEL_OUTPUT_DDI:
1363 /* Skip pure HDMI/DVI DDI encoders */
1364 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1370 static inline struct intel_lspcon *
1371 enc_to_intel_lspcon(struct drm_encoder *encoder)
1373 return &enc_to_dig_port(encoder)->lspcon;
1376 static inline struct intel_digital_port *
1377 dp_to_dig_port(struct intel_dp *intel_dp)
1379 return container_of(intel_dp, struct intel_digital_port, dp);
1382 static inline struct intel_lspcon *
1383 dp_to_lspcon(struct intel_dp *intel_dp)
1385 return &dp_to_dig_port(intel_dp)->lspcon;
1388 static inline struct drm_i915_private *
1389 dp_to_i915(struct intel_dp *intel_dp)
1391 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1394 static inline struct intel_digital_port *
1395 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1397 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1400 static inline struct intel_plane_state *
1401 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1402 struct intel_plane *plane)
1404 struct drm_plane_state *ret =
1405 drm_atomic_get_plane_state(&state->base, &plane->base);
1408 return ERR_CAST(ret);
1410 return to_intel_plane_state(ret);
1413 static inline struct intel_plane_state *
1414 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1415 struct intel_plane *plane)
1417 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1421 static inline struct intel_plane_state *
1422 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1423 struct intel_plane *plane)
1425 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1429 static inline struct intel_crtc_state *
1430 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1431 struct intel_crtc *crtc)
1433 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1437 static inline struct intel_crtc_state *
1438 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1439 struct intel_crtc *crtc)
1441 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1445 /* intel_display.c */
1446 void intel_plane_destroy(struct drm_plane *plane);
1447 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1448 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1449 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1450 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1451 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1452 const char *name, u32 reg, int ref_freq);
1453 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1454 const char *name, u32 reg);
1455 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1456 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1457 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1458 unsigned int intel_fb_xy_to_linear(int x, int y,
1459 const struct intel_plane_state *state,
1461 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1462 int color_plane, unsigned int height);
1463 void intel_add_fb_offsets(int *x, int *y,
1464 const struct intel_plane_state *state, int plane);
1465 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1466 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
1467 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1468 void intel_mark_busy(struct drm_i915_private *dev_priv);
1469 void intel_mark_idle(struct drm_i915_private *dev_priv);
1470 int intel_display_suspend(struct drm_device *dev);
1471 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1472 void intel_encoder_destroy(struct drm_encoder *encoder);
1473 struct drm_display_mode *
1474 intel_encoder_current_mode(struct intel_encoder *encoder);
1475 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1476 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1477 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1479 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1480 struct drm_file *file_priv);
1481 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1484 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1485 enum intel_output_type type)
1487 return crtc_state->output_types & (1 << type);
1490 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1492 return crtc_state->output_types &
1493 ((1 << INTEL_OUTPUT_DP) |
1494 (1 << INTEL_OUTPUT_DP_MST) |
1495 (1 << INTEL_OUTPUT_EDP));
1498 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 drm_wait_one_vblank(&dev_priv->drm, pipe);
1503 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1505 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1508 intel_wait_for_vblank(dev_priv, pipe);
1511 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1513 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1514 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1515 struct intel_digital_port *dport,
1516 unsigned int expected_mask);
1517 int intel_get_load_detect_pipe(struct drm_connector *connector,
1518 const struct drm_display_mode *mode,
1519 struct intel_load_detect_pipe *old,
1520 struct drm_modeset_acquire_ctx *ctx);
1521 void intel_release_load_detect_pipe(struct drm_connector *connector,
1522 struct intel_load_detect_pipe *old,
1523 struct drm_modeset_acquire_ctx *ctx);
1525 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1526 const struct i915_ggtt_view *view,
1528 unsigned long *out_flags);
1529 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1530 struct drm_framebuffer *
1531 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1532 struct drm_mode_fb_cmd2 *mode_cmd);
1533 int intel_prepare_plane_fb(struct drm_plane *plane,
1534 struct drm_plane_state *new_state);
1535 void intel_cleanup_plane_fb(struct drm_plane *plane,
1536 struct drm_plane_state *old_state);
1537 int intel_plane_atomic_get_property(struct drm_plane *plane,
1538 const struct drm_plane_state *state,
1539 struct drm_property *property,
1541 int intel_plane_atomic_set_property(struct drm_plane *plane,
1542 struct drm_plane_state *state,
1543 struct drm_property *property,
1545 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1546 struct drm_crtc_state *crtc_state,
1547 const struct intel_plane_state *old_plane_state,
1548 struct drm_plane_state *plane_state);
1550 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1553 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1554 const struct dpll *dpll);
1555 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1556 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1558 /* modesetting asserts */
1559 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1561 void assert_pll(struct drm_i915_private *dev_priv,
1562 enum pipe pipe, bool state);
1563 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1564 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1565 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1566 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1567 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1568 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1569 enum pipe pipe, bool state);
1570 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1571 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1572 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1573 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1574 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1575 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1576 void intel_finish_reset(struct drm_i915_private *dev_priv);
1577 unsigned int skl_cdclk_get_vco(unsigned int freq);
1578 void intel_dp_get_m_n(struct intel_crtc *crtc,
1579 struct intel_crtc_state *pipe_config);
1580 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1581 enum link_m_n_set m_n);
1582 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
1583 const struct intel_crtc_state *crtc_state);
1584 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1585 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1586 struct dpll *best_clock);
1587 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1589 bool intel_crtc_active(struct intel_crtc *crtc);
1590 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1591 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1592 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1593 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1594 enum intel_display_power_domain
1595 intel_aux_power_domain(struct intel_digital_port *dig_port);
1596 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1597 struct intel_crtc_state *pipe_config);
1598 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1599 struct intel_crtc_state *crtc_state);
1601 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1602 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1603 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1606 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1608 return i915_ggtt_offset(state->vma);
1611 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1612 const struct intel_plane_state *plane_state);
1613 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1614 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1615 const struct intel_plane_state *plane_state);
1616 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1617 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1619 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1620 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1621 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1622 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1623 u32 pixel_format, u64 modifier,
1624 unsigned int rotation);
1625 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
1627 /* intel_runtime_pm.c */
1628 #define BITS_PER_WAKEREF \
1629 BITS_PER_TYPE(struct_member(struct i915_runtime_pm, wakeref_count))
1630 #define INTEL_RPM_WAKELOCK_SHIFT (BITS_PER_WAKEREF / 2)
1631 #define INTEL_RPM_WAKELOCK_BIAS (1 << INTEL_RPM_WAKELOCK_SHIFT)
1632 #define INTEL_RPM_RAW_WAKEREF_MASK (INTEL_RPM_WAKELOCK_BIAS - 1)
1635 intel_rpm_raw_wakeref_count(int wakeref_count)
1637 return wakeref_count & INTEL_RPM_RAW_WAKEREF_MASK;
1641 intel_rpm_wakelock_count(int wakeref_count)
1643 return wakeref_count >> INTEL_RPM_WAKELOCK_SHIFT;
1647 assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
1649 WARN_ONCE(rpm->suspended,
1650 "Device suspended during HW access\n");
1654 ____assert_rpm_raw_wakeref_held(struct i915_runtime_pm *rpm, int wakeref_count)
1656 assert_rpm_device_not_suspended(rpm);
1657 WARN_ONCE(!intel_rpm_raw_wakeref_count(wakeref_count),
1658 "RPM raw-wakeref not held\n");
1662 ____assert_rpm_wakelock_held(struct i915_runtime_pm *rpm, int wakeref_count)
1664 ____assert_rpm_raw_wakeref_held(rpm, wakeref_count);
1665 WARN_ONCE(!intel_rpm_wakelock_count(wakeref_count),
1666 "RPM wakelock ref not held during HW access\n");
1670 assert_rpm_raw_wakeref_held(struct drm_i915_private *i915)
1672 struct i915_runtime_pm *rpm = &i915->runtime_pm;
1674 ____assert_rpm_raw_wakeref_held(rpm, atomic_read(&rpm->wakeref_count));
1678 __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
1680 ____assert_rpm_wakelock_held(rpm, atomic_read(&rpm->wakeref_count));
1684 assert_rpm_wakelock_held(struct drm_i915_private *i915)
1686 __assert_rpm_wakelock_held(&i915->runtime_pm);
1690 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1691 * @i915: i915 device instance
1693 * This function disable asserts that check if we hold an RPM wakelock
1694 * reference, while keeping the device-not-suspended checks still enabled.
1695 * It's meant to be used only in special circumstances where our rule about
1696 * the wakelock refcount wrt. the device power state doesn't hold. According
1697 * to this rule at any point where we access the HW or want to keep the HW in
1698 * an active state we must hold an RPM wakelock reference acquired via one of
1699 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1700 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1701 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1702 * users should avoid using this function.
1704 * Any calls to this function must have a symmetric call to
1705 * enable_rpm_wakeref_asserts().
1708 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
1710 atomic_add(INTEL_RPM_WAKELOCK_BIAS + 1,
1711 &i915->runtime_pm.wakeref_count);
1715 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1716 * @i915: i915 device instance
1718 * This function re-enables the RPM assert checks after disabling them with
1719 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1720 * circumstances otherwise its use should be avoided.
1722 * Any calls to this function must have a symmetric call to
1723 * disable_rpm_wakeref_asserts().
1726 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
1728 atomic_sub(INTEL_RPM_WAKELOCK_BIAS + 1,
1729 &i915->runtime_pm.wakeref_count);
1732 #endif /* __INTEL_DRV_H__ */