2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
59 bool expired__ = time_after(jiffies, timeout__); \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #define _wait_for_atomic(COND, US, ATOMIC) \
88 int cpu, ret, timeout = (US) * 1000; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93 cpu = smp_processor_id(); \
95 base = local_clock(); \
97 u64 now = local_clock(); \
104 if (now - base >= timeout) { \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
121 #define wait_for_us(COND, US) \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
126 ret__ = _wait_for((COND), (US), 10); \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
132 #define wait_for_atomic_us(COND, US) \
134 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 BUILD_BUG_ON((US) > 50000); \
136 _wait_for_atomic((COND), (US), 1); \
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
145 * Display related stuff
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
163 /* these are outputs from the chip - integrated only
164 external chips are via DVO or SDVO output */
165 enum intel_output_type {
166 INTEL_OUTPUT_UNUSED = 0,
167 INTEL_OUTPUT_ANALOG = 1,
168 INTEL_OUTPUT_DVO = 2,
169 INTEL_OUTPUT_SDVO = 3,
170 INTEL_OUTPUT_LVDS = 4,
171 INTEL_OUTPUT_TVOUT = 5,
172 INTEL_OUTPUT_HDMI = 6,
174 INTEL_OUTPUT_EDP = 8,
175 INTEL_OUTPUT_DSI = 9,
176 INTEL_OUTPUT_UNKNOWN = 10,
177 INTEL_OUTPUT_DP_MST = 11,
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
185 #define INTEL_DSI_VIDEO_MODE 0
186 #define INTEL_DSI_COMMAND_MODE 1
188 struct intel_framebuffer {
189 struct drm_framebuffer base;
190 struct drm_i915_gem_object *obj;
191 struct intel_rotation_info rot_info;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch; /* pixels */
205 struct drm_fb_helper helper;
206 struct intel_framebuffer *fb;
207 struct i915_vma *vma;
208 async_cookie_t cookie;
212 struct intel_encoder {
213 struct drm_encoder base;
215 enum intel_output_type type;
217 unsigned int cloneable;
218 void (*hot_plug)(struct intel_encoder *);
219 bool (*compute_config)(struct intel_encoder *,
220 struct intel_crtc_state *,
221 struct drm_connector_state *);
222 void (*pre_pll_enable)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 void (*pre_enable)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*enable)(struct intel_encoder *,
229 struct intel_crtc_state *,
230 struct drm_connector_state *);
231 void (*disable)(struct intel_encoder *,
232 struct intel_crtc_state *,
233 struct drm_connector_state *);
234 void (*post_disable)(struct intel_encoder *,
235 struct intel_crtc_state *,
236 struct drm_connector_state *);
237 void (*post_pll_disable)(struct intel_encoder *,
238 struct intel_crtc_state *,
239 struct drm_connector_state *);
240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */
243 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
244 /* Reconstructs the equivalent mode flags for the current hardware
245 * state. This must be called _after_ display->get_pipe_config has
246 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247 * be set correctly before calling this function. */
248 void (*get_config)(struct intel_encoder *,
249 struct intel_crtc_state *pipe_config);
250 /* Returns a mask of power domains that need to be referenced as part
251 * of the hardware state readout code. */
252 u64 (*get_power_domains)(struct intel_encoder *encoder);
254 * Called during system suspend after all pending requests for the
255 * encoder are flushed (for example for DP AUX transactions) and
256 * device interrupts are disabled.
258 void (*suspend)(struct intel_encoder *);
260 enum hpd_pin hpd_pin;
261 enum intel_display_power_domain power_domain;
262 /* for communication with audio component; protected by av_mutex */
263 const struct drm_connector *audio_connector;
267 struct drm_display_mode *fixed_mode;
268 struct drm_display_mode *downclock_mode;
278 bool combination_mode; /* gen 2/4 only */
280 bool alternate_pwm_increment; /* lpt+ */
283 bool util_pin_active_low; /* bxt+ */
284 u8 controller; /* bxt+ only */
285 struct pwm_device *pwm;
287 struct backlight_device *device;
289 /* Connector and platform specific backlight functions */
290 int (*setup)(struct intel_connector *connector, enum pipe pipe);
291 uint32_t (*get)(struct intel_connector *connector);
292 void (*set)(struct intel_connector *connector, uint32_t level);
293 void (*disable)(struct intel_connector *connector);
294 void (*enable)(struct intel_connector *connector);
295 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
297 void (*power)(struct intel_connector *, bool enable);
301 struct intel_connector {
302 struct drm_connector base;
304 * The fixed encoder this connector is connected to.
306 struct intel_encoder *encoder;
308 /* ACPI device id for ACPI and driver cooperation */
311 /* Reads out the current hw, returning true if the connector is enabled
312 * and active (i.e. dpms ON state). */
313 bool (*get_hw_state)(struct intel_connector *);
315 /* Panel info for eDP and LVDS */
316 struct intel_panel panel;
318 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
320 struct edid *detect_edid;
322 /* since POLL and HPD connectors may use the same HPD line keep the native
323 state of connector->polled in case hotplug storm detection changes it */
326 void *port; /* store this opaque as its illegal to dereference it */
328 struct intel_dp *mst_port;
330 /* Work struct to schedule a uevent on link train failure */
331 struct work_struct modeset_retry_work;
346 struct intel_atomic_state {
347 struct drm_atomic_state base;
351 * Logical state of cdclk (used for all scaling, watermark,
352 * etc. calculations and checks). This is computed as if all
353 * enabled crtcs were active.
355 struct intel_cdclk_state logical;
358 * Actual state of cdclk, can be different from the logical
359 * state only when all crtc's are DPMS off.
361 struct intel_cdclk_state actual;
364 bool dpll_set, modeset;
367 * Does this transaction change the pipes that are active? This mask
368 * tracks which CRTC's have changed their active state at the end of
369 * the transaction (not counting the temporary disable during modesets).
370 * This mask should only be non-zero when intel_state->modeset is true,
371 * but the converse is not necessarily true; simply changing a mode may
372 * not flip the final active status of any CRTC's
374 unsigned int active_pipe_changes;
376 unsigned int active_crtcs;
377 unsigned int min_pixclk[I915_MAX_PIPES];
379 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
382 * Current watermarks can't be trusted during hardware readout, so
383 * don't bother calculating intermediate watermarks.
385 bool skip_intermediate_wm;
388 struct skl_wm_values wm_results;
390 struct i915_sw_fence commit_ready;
392 struct llist_node freed;
395 struct intel_plane_state {
396 struct drm_plane_state base;
397 struct drm_rect clip;
398 struct i915_vma *vma;
409 /* plane control register */
414 * = -1 : not using a scaler
415 * >= 0 : using a scalers
417 * plane requiring a scaler:
418 * - During check_plane, its bit is set in
419 * crtc_state->scaler_state.scaler_users by calling helper function
420 * update_scaler_plane.
421 * - scaler_id indicates the scaler it got assigned.
423 * plane doesn't require a scaler:
424 * - this can happen when scaling is no more required or plane simply
426 * - During check_plane, corresponding bit is reset in
427 * crtc_state->scaler_state.scaler_users by calling helper function
428 * update_scaler_plane.
432 struct drm_intel_sprite_colorkey ckey;
435 struct intel_initial_plane_config {
436 struct intel_framebuffer *fb;
442 #define SKL_MIN_SRC_W 8
443 #define SKL_MAX_SRC_W 4096
444 #define SKL_MIN_SRC_H 8
445 #define SKL_MAX_SRC_H 4096
446 #define SKL_MIN_DST_W 8
447 #define SKL_MAX_DST_W 4096
448 #define SKL_MIN_DST_H 8
449 #define SKL_MAX_DST_H 4096
451 struct intel_scaler {
456 struct intel_crtc_scaler_state {
457 #define SKL_NUM_SCALERS 2
458 struct intel_scaler scalers[SKL_NUM_SCALERS];
461 * scaler_users: keeps track of users requesting scalers on this crtc.
463 * If a bit is set, a user is using a scaler.
464 * Here user can be a plane or crtc as defined below:
465 * bits 0-30 - plane (bit position is index from drm_plane_index)
468 * Instead of creating a new index to cover planes and crtc, using
469 * existing drm_plane_index for planes which is well less than 31
470 * planes and bit 31 for crtc. This should be fine to cover all
473 * intel_atomic_setup_scalers will setup available scalers to users
474 * requesting scalers. It will gracefully fail if request exceeds
477 #define SKL_CRTC_INDEX 31
478 unsigned scaler_users;
480 /* scaler used by crtc for panel fitting purpose */
484 /* drm_mode->private_flags */
485 #define I915_MODE_FLAG_INHERITED 1
487 struct intel_pipe_wm {
488 struct intel_wm_level wm[5];
489 struct intel_wm_level raw_wm[5];
493 bool sprites_enabled;
497 struct skl_plane_wm {
498 struct skl_wm_level wm[8];
499 struct skl_wm_level trans_wm;
503 struct skl_plane_wm planes[I915_MAX_PLANES];
510 VLV_WM_LEVEL_DDR_DVFS,
514 struct vlv_wm_state {
515 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
516 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
521 struct vlv_fifo_state {
522 u16 plane[I915_MAX_PLANES];
532 struct g4x_wm_state {
533 struct g4x_pipe_wm wm;
535 struct g4x_sr_wm hpll;
541 struct intel_crtc_wm_state {
545 * Intermediate watermarks; these can be
546 * programmed immediately since they satisfy
547 * both the current configuration we're
548 * switching away from and the new
549 * configuration we're switching to.
551 struct intel_pipe_wm intermediate;
554 * Optimal watermarks, programmed post-vblank
555 * when this state is committed.
557 struct intel_pipe_wm optimal;
561 /* gen9+ only needs 1-step wm programming */
562 struct skl_pipe_wm optimal;
563 struct skl_ddb_entry ddb;
567 /* "raw" watermarks (not inverted) */
568 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
569 /* intermediate watermarks (inverted) */
570 struct vlv_wm_state intermediate;
571 /* optimal watermarks (inverted) */
572 struct vlv_wm_state optimal;
573 /* display FIFO split */
574 struct vlv_fifo_state fifo_state;
578 /* "raw" watermarks */
579 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
580 /* intermediate watermarks */
581 struct g4x_wm_state intermediate;
582 /* optimal watermarks */
583 struct g4x_wm_state optimal;
588 * Platforms with two-step watermark programming will need to
589 * update watermark programming post-vblank to switch from the
590 * safe intermediate watermarks to the optimal final
593 bool need_postvbl_update;
596 struct intel_crtc_state {
597 struct drm_crtc_state base;
600 * quirks - bitfield with hw state readout quirks
602 * For various reasons the hw state readout code might not be able to
603 * completely faithfully read out the current state. These cases are
604 * tracked with quirk flags so that fastboot and state checker can act
607 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
608 unsigned long quirks;
610 unsigned fb_bits; /* framebuffers to flip */
611 bool update_pipe; /* can a fast modeset be performed? */
613 bool update_wm_pre, update_wm_post; /* watermarks are updated */
614 bool fb_changed; /* fb on any of the planes is changed */
615 bool fifo_changed; /* FIFO split is changed */
617 /* Pipe source size (ie. panel fitter input size)
618 * All planes will be positioned inside this space,
619 * and get clipped at the edges. */
620 int pipe_src_w, pipe_src_h;
623 * Pipe pixel rate, adjusted for
624 * panel fitter/pipe scaler downscaling.
626 unsigned int pixel_rate;
628 /* Whether to set up the PCH/FDI. Note that we never allow sharing
629 * between pch encoders and cpu encoders. */
630 bool has_pch_encoder;
632 /* Are we sending infoframes on the attached port */
635 /* CPU Transcoder for the pipe. Currently this can only differ from the
636 * pipe on Haswell and later (where we have a special eDP transcoder)
637 * and Broxton (where we have special DSI transcoders). */
638 enum transcoder cpu_transcoder;
641 * Use reduced/limited/broadcast rbg range, compressing from the full
642 * range fed into the crtcs.
644 bool limited_color_range;
646 /* Bitmask of encoder types (enum intel_output_type)
647 * driven by the pipe.
649 unsigned int output_types;
651 /* Whether we should send NULL infoframes. Required for audio. */
654 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
655 * has_dp_encoder is set. */
659 * Enable dithering, used when the selected pipe bpp doesn't match the
665 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
666 * compliance video pattern tests.
667 * Disable dither only if it is a compliance test request for
670 bool dither_force_disable;
672 /* Controls for the clock computation, to override various stages. */
675 /* SDVO TV has a bunch of special case. To make multifunction encoders
676 * work correctly, we need to track this at runtime.*/
680 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
681 * required. This is set in the 2nd loop of calling encoder's
682 * ->compute_config if the first pick doesn't work out.
686 /* Settings for the intel dpll used on pretty much everything but
690 /* Selected dpll when shared or NULL. */
691 struct intel_shared_dpll *shared_dpll;
693 /* Actual register state of the dpll, for shared dpll cross-checking. */
694 struct intel_dpll_hw_state dpll_hw_state;
696 /* DSI PLL registers */
702 struct intel_link_m_n dp_m_n;
704 /* m2_n2 for eDP downclock */
705 struct intel_link_m_n dp_m2_n2;
709 * Frequence the dpll for the port should run at. Differs from the
710 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
711 * already multiplied by pixel_multiplier.
715 /* Used by SDVO (and if we ever fix it, HDMI). */
716 unsigned pixel_multiplier;
721 * Used by platforms having DP/HDMI PHY with programmable lane
722 * latency optimization.
724 uint8_t lane_lat_optim_mask;
726 /* Panel fitter controls for gen2-gen4 + VLV */
730 u32 lvds_border_bits;
733 /* Panel fitter placement and size for Ironlake+ */
741 /* FDI configuration, only valid if has_pch_encoder is set. */
743 struct intel_link_m_n fdi_m_n;
753 struct intel_crtc_scaler_state scaler_state;
755 /* w/a for waiting 2 vblanks during crtc enable */
756 enum pipe hsw_workaround_pipe;
758 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
761 struct intel_crtc_wm_state wm;
763 /* Gamma mode programmed on the pipe */
766 /* bitmask of visible planes (enum plane_id) */
769 /* HDMI scrambling status */
770 bool hdmi_scrambling;
772 /* HDMI High TMDS char rate ratio */
773 bool hdmi_high_tmds_clock_ratio;
777 struct drm_crtc base;
780 u8 lut_r[256], lut_g[256], lut_b[256];
782 * Whether the crtc and the connected output pipeline is active. Implies
783 * that crtc->enabled is set, i.e. the current mode configuration has
784 * some outputs connected to this crtc.
789 unsigned long long enabled_power_domains;
790 struct intel_overlay *overlay;
791 struct intel_flip_work *flip_work;
793 atomic_t unpin_work_count;
795 /* Display surface base address adjustement for pageflips. Note that on
796 * gen4+ this only adjusts up to a tile, offsets within a tile are
797 * handled in the hw itself (with the TILEOFF register). */
802 struct intel_crtc_state *config;
804 /* global reset count when the last flip was submitted */
805 unsigned int reset_count;
807 /* Access to these should be protected by dev_priv->irq_lock. */
808 bool cpu_fifo_underrun_disabled;
809 bool pch_fifo_underrun_disabled;
811 /* per-pipe watermark state */
813 /* watermarks currently being used */
815 struct intel_pipe_wm ilk;
816 struct vlv_wm_state vlv;
817 struct g4x_wm_state g4x;
824 unsigned start_vbl_count;
825 ktime_t start_vbl_time;
826 int min_vbl, max_vbl;
830 /* scalers available on this crtc */
835 struct drm_plane base;
841 uint32_t frontbuffer_bit;
844 u32 base, cntl, size;
848 * NOTE: Do not place new plane state fields here (e.g., when adding
849 * new plane properties). New runtime state should now be placed in
850 * the intel_plane_state structure and accessed via plane_state.
853 void (*update_plane)(struct intel_plane *plane,
854 const struct intel_crtc_state *crtc_state,
855 const struct intel_plane_state *plane_state);
856 void (*disable_plane)(struct intel_plane *plane,
857 struct intel_crtc *crtc);
858 int (*check_plane)(struct intel_plane *plane,
859 struct intel_crtc_state *crtc_state,
860 struct intel_plane_state *state);
863 struct intel_watermark_params {
871 struct cxsr_latency {
877 u16 display_hpll_disable;
879 u16 cursor_hpll_disable;
882 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
883 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
884 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
885 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
886 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
887 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
888 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
889 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
890 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
896 enum drm_dp_dual_mode_type type;
899 bool limited_color_range;
900 bool color_range_auto;
903 enum hdmi_force_audio force_audio;
904 bool rgb_quant_range_selectable;
905 struct intel_connector *attached_connector;
906 void (*write_infoframe)(struct drm_encoder *encoder,
907 const struct intel_crtc_state *crtc_state,
908 enum hdmi_infoframe_type type,
909 const void *frame, ssize_t len);
910 void (*set_infoframes)(struct drm_encoder *encoder,
912 const struct intel_crtc_state *crtc_state,
913 const struct drm_connector_state *conn_state);
914 bool (*infoframe_enabled)(struct drm_encoder *encoder,
915 const struct intel_crtc_state *pipe_config);
918 struct intel_dp_mst_encoder;
919 #define DP_MAX_DOWNSTREAM_PORTS 0x10
923 * When platform provides two set of M_N registers for dp, we can
924 * program them and switch between them incase of DRRS.
925 * But When only one such register is provided, we have to program the
926 * required divider value on that registers itself based on the DRRS state.
928 * M1_N1 : Program dp_m_n on M1_N1 registers
929 * dp_m2_n2 on M2_N2 registers (If supported)
931 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
932 * M2_N2 registers are not supported
936 /* Sets the m1_n1 and m2_n2 */
941 struct intel_dp_desc {
949 struct intel_dp_compliance_data {
951 uint8_t video_pattern;
952 uint16_t hdisplay, vdisplay;
956 struct intel_dp_compliance {
957 unsigned long test_type;
958 struct intel_dp_compliance_data test_data;
965 i915_reg_t output_reg;
966 i915_reg_t aux_ch_ctl_reg;
967 i915_reg_t aux_ch_data_reg[5];
975 bool channel_eq_status;
976 bool reset_link_params;
977 enum hdmi_force_audio force_audio;
978 bool limited_color_range;
979 bool color_range_auto;
980 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
981 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
982 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
983 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
985 int num_source_rates;
986 const int *source_rates;
987 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
989 int sink_rates[DP_MAX_SUPPORTED_RATES];
990 bool use_rate_select;
991 /* intersection of source and sink rates */
992 int num_common_rates;
993 int common_rates[DP_MAX_SUPPORTED_RATES];
994 /* Max lane count for the current link */
995 int max_link_lane_count;
996 /* Max rate for the current link */
998 /* sink or branch descriptor */
999 struct intel_dp_desc desc;
1000 struct drm_dp_aux aux;
1001 enum intel_display_power_domain aux_power_domain;
1002 uint8_t train_set[4];
1003 int panel_power_up_delay;
1004 int panel_power_down_delay;
1005 int panel_power_cycle_delay;
1006 int backlight_on_delay;
1007 int backlight_off_delay;
1008 struct delayed_work panel_vdd_work;
1009 bool want_panel_vdd;
1010 unsigned long last_power_on;
1011 unsigned long last_backlight_off;
1012 ktime_t panel_power_off_time;
1014 struct notifier_block edp_notifier;
1017 * Pipe whose power sequencer is currently locked into
1018 * this port. Only relevant on VLV/CHV.
1022 * Pipe currently driving the port. Used for preventing
1023 * the use of the PPS for any pipe currentrly driving
1024 * external DP as that will mess things up on VLV.
1026 enum pipe active_pipe;
1028 * Set if the sequencer may be reset due to a power transition,
1029 * requiring a reinitialization. Only relevant on BXT.
1032 struct edp_power_seq pps_delays;
1034 bool can_mst; /* this port supports mst */
1036 int active_mst_links;
1037 /* connector directly attached - won't be use for modeset in mst world */
1038 struct intel_connector *attached_connector;
1040 /* mst connector list */
1041 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1042 struct drm_dp_mst_topology_mgr mst_mgr;
1044 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1046 * This function returns the value we have to program the AUX_CTL
1047 * register with to kick off an AUX transaction.
1049 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1052 uint32_t aux_clock_divider);
1054 /* This is called before a link training is starterd */
1055 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1057 /* Displayport compliance testing */
1058 struct intel_dp_compliance compliance;
1061 struct intel_lspcon {
1063 enum drm_lspcon_mode mode;
1066 struct intel_digital_port {
1067 struct intel_encoder base;
1069 u32 saved_port_bits;
1071 struct intel_hdmi hdmi;
1072 struct intel_lspcon lspcon;
1073 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1074 bool release_cl2_override;
1076 enum intel_display_power_domain ddi_io_power_domain;
1079 struct intel_dp_mst_encoder {
1080 struct intel_encoder base;
1082 struct intel_digital_port *primary;
1083 struct intel_connector *connector;
1086 static inline enum dpio_channel
1087 vlv_dport_to_channel(struct intel_digital_port *dport)
1089 switch (dport->port) {
1100 static inline enum dpio_phy
1101 vlv_dport_to_phy(struct intel_digital_port *dport)
1103 switch (dport->port) {
1114 static inline enum dpio_channel
1115 vlv_pipe_to_channel(enum pipe pipe)
1128 static inline struct intel_crtc *
1129 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 return dev_priv->pipe_to_crtc_mapping[pipe];
1134 static inline struct intel_crtc *
1135 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1137 return dev_priv->plane_to_crtc_mapping[plane];
1140 struct intel_flip_work {
1141 struct work_struct unpin_work;
1142 struct work_struct mmio_work;
1144 struct drm_crtc *crtc;
1145 struct i915_vma *old_vma;
1146 struct drm_framebuffer *old_fb;
1147 struct drm_i915_gem_object *pending_flip_obj;
1148 struct drm_pending_vblank_event *event;
1152 struct drm_i915_gem_request *flip_queued_req;
1153 u32 flip_queued_vblank;
1154 u32 flip_ready_vblank;
1155 unsigned int rotation;
1158 struct intel_load_detect_pipe {
1159 struct drm_atomic_state *restore_state;
1162 static inline struct intel_encoder *
1163 intel_attached_encoder(struct drm_connector *connector)
1165 return to_intel_connector(connector)->encoder;
1168 static inline struct intel_digital_port *
1169 enc_to_dig_port(struct drm_encoder *encoder)
1171 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1173 switch (intel_encoder->type) {
1174 case INTEL_OUTPUT_UNKNOWN:
1175 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1176 case INTEL_OUTPUT_DP:
1177 case INTEL_OUTPUT_EDP:
1178 case INTEL_OUTPUT_HDMI:
1179 return container_of(encoder, struct intel_digital_port,
1186 static inline struct intel_dp_mst_encoder *
1187 enc_to_mst(struct drm_encoder *encoder)
1189 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1192 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1194 return &enc_to_dig_port(encoder)->dp;
1197 static inline struct intel_digital_port *
1198 dp_to_dig_port(struct intel_dp *intel_dp)
1200 return container_of(intel_dp, struct intel_digital_port, dp);
1203 static inline struct intel_lspcon *
1204 dp_to_lspcon(struct intel_dp *intel_dp)
1206 return &dp_to_dig_port(intel_dp)->lspcon;
1209 static inline struct intel_digital_port *
1210 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1212 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1215 /* intel_fifo_underrun.c */
1216 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool enable);
1218 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1219 enum transcoder pch_transcoder,
1221 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1223 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1224 enum transcoder pch_transcoder);
1225 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1226 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1229 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1230 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1231 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1232 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1233 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1234 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1235 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1236 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1237 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1238 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1240 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1243 return mask & ~i915->rps.pm_intrmsk_mbz;
1246 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1247 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1248 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1251 * We only use drm_irq_uninstall() at unload and VT switch, so
1252 * this is the only thing we need to check.
1254 return dev_priv->pm.irqs_enabled;
1257 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1258 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1259 unsigned int pipe_mask);
1260 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1261 unsigned int pipe_mask);
1262 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1263 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1264 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1267 void intel_crt_init(struct drm_i915_private *dev_priv);
1268 void intel_crt_reset(struct drm_encoder *encoder);
1271 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1272 struct intel_crtc_state *old_crtc_state,
1273 struct drm_connector_state *old_conn_state);
1274 void hsw_fdi_link_train(struct intel_crtc *crtc,
1275 const struct intel_crtc_state *crtc_state);
1276 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1277 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1278 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1279 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1280 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1281 enum transcoder cpu_transcoder);
1282 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1283 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1284 struct intel_encoder *
1285 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1286 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1287 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1288 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1289 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1290 struct intel_crtc *intel_crtc);
1291 void intel_ddi_get_config(struct intel_encoder *encoder,
1292 struct intel_crtc_state *pipe_config);
1294 void intel_ddi_clock_get(struct intel_encoder *encoder,
1295 struct intel_crtc_state *pipe_config);
1296 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1298 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1299 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1301 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1302 int plane, unsigned int height);
1305 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1306 void intel_audio_codec_enable(struct intel_encoder *encoder,
1307 const struct intel_crtc_state *crtc_state,
1308 const struct drm_connector_state *conn_state);
1309 void intel_audio_codec_disable(struct intel_encoder *encoder);
1310 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1311 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1312 void intel_audio_init(struct drm_i915_private *dev_priv);
1313 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1316 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1317 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1318 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1319 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1320 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1321 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1322 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1323 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1324 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1325 const struct intel_cdclk_state *b);
1326 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1327 const struct intel_cdclk_state *cdclk_state);
1329 /* intel_display.c */
1330 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1331 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1332 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1333 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1334 const char *name, u32 reg, int ref_freq);
1335 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1336 const char *name, u32 reg);
1337 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1338 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1339 extern const struct drm_plane_funcs intel_plane_funcs;
1340 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1341 unsigned int intel_fb_xy_to_linear(int x, int y,
1342 const struct intel_plane_state *state,
1344 void intel_add_fb_offsets(int *x, int *y,
1345 const struct intel_plane_state *state, int plane);
1346 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1347 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1348 void intel_mark_busy(struct drm_i915_private *dev_priv);
1349 void intel_mark_idle(struct drm_i915_private *dev_priv);
1350 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1351 int intel_display_suspend(struct drm_device *dev);
1352 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1353 void intel_encoder_destroy(struct drm_encoder *encoder);
1354 int intel_connector_init(struct intel_connector *);
1355 struct intel_connector *intel_connector_alloc(void);
1356 bool intel_connector_get_hw_state(struct intel_connector *connector);
1357 void intel_connector_attach_encoder(struct intel_connector *connector,
1358 struct intel_encoder *encoder);
1359 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1360 struct drm_crtc *crtc);
1361 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1362 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv);
1364 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1367 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1368 enum intel_output_type type)
1370 return crtc_state->output_types & (1 << type);
1373 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1375 return crtc_state->output_types &
1376 ((1 << INTEL_OUTPUT_DP) |
1377 (1 << INTEL_OUTPUT_DP_MST) |
1378 (1 << INTEL_OUTPUT_EDP));
1381 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1383 drm_wait_one_vblank(&dev_priv->drm, pipe);
1386 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1388 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1391 intel_wait_for_vblank(dev_priv, pipe);
1394 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1396 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1397 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1398 struct intel_digital_port *dport,
1399 unsigned int expected_mask);
1400 int intel_get_load_detect_pipe(struct drm_connector *connector,
1401 struct drm_display_mode *mode,
1402 struct intel_load_detect_pipe *old,
1403 struct drm_modeset_acquire_ctx *ctx);
1404 void intel_release_load_detect_pipe(struct drm_connector *connector,
1405 struct intel_load_detect_pipe *old,
1406 struct drm_modeset_acquire_ctx *ctx);
1408 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1409 void intel_unpin_fb_vma(struct i915_vma *vma);
1410 struct drm_framebuffer *
1411 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1412 struct drm_mode_fb_cmd2 *mode_cmd);
1413 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1414 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1415 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1416 int intel_prepare_plane_fb(struct drm_plane *plane,
1417 struct drm_plane_state *new_state);
1418 void intel_cleanup_plane_fb(struct drm_plane *plane,
1419 struct drm_plane_state *old_state);
1420 int intel_plane_atomic_get_property(struct drm_plane *plane,
1421 const struct drm_plane_state *state,
1422 struct drm_property *property,
1424 int intel_plane_atomic_set_property(struct drm_plane *plane,
1425 struct drm_plane_state *state,
1426 struct drm_property *property,
1428 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1429 struct drm_plane_state *plane_state);
1431 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1434 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1435 const struct dpll *dpll);
1436 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1437 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1439 /* modesetting asserts */
1440 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1442 void assert_pll(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, bool state);
1444 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1445 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1446 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1447 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1448 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1449 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, bool state);
1451 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1452 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1453 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1454 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1455 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1456 u32 intel_compute_tile_offset(int *x, int *y,
1457 const struct intel_plane_state *state, int plane);
1458 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1459 void intel_finish_reset(struct drm_i915_private *dev_priv);
1460 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1461 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1462 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1463 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1464 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1465 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1466 unsigned int skl_cdclk_get_vco(unsigned int freq);
1467 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1468 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1469 void intel_dp_get_m_n(struct intel_crtc *crtc,
1470 struct intel_crtc_state *pipe_config);
1471 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1472 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1473 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1474 struct dpll *best_clock);
1475 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1477 bool intel_crtc_active(struct intel_crtc *crtc);
1478 void hsw_enable_ips(struct intel_crtc *crtc);
1479 void hsw_disable_ips(struct intel_crtc *crtc);
1480 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1481 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1482 struct intel_crtc_state *pipe_config);
1484 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1485 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1487 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1489 return i915_ggtt_offset(state->vma);
1492 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1493 const struct intel_plane_state *plane_state);
1494 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1495 unsigned int rotation);
1496 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1497 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1500 void intel_csr_ucode_init(struct drm_i915_private *);
1501 void intel_csr_load_program(struct drm_i915_private *);
1502 void intel_csr_ucode_fini(struct drm_i915_private *);
1503 void intel_csr_ucode_suspend(struct drm_i915_private *);
1504 void intel_csr_ucode_resume(struct drm_i915_private *);
1507 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1509 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1510 struct intel_connector *intel_connector);
1511 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1512 int link_rate, uint8_t lane_count,
1514 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1515 int link_rate, uint8_t lane_count);
1516 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1517 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1518 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1519 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1520 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1521 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1522 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1523 bool intel_dp_compute_config(struct intel_encoder *encoder,
1524 struct intel_crtc_state *pipe_config,
1525 struct drm_connector_state *conn_state);
1526 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1527 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1529 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1530 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1531 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1532 void intel_edp_panel_on(struct intel_dp *intel_dp);
1533 void intel_edp_panel_off(struct intel_dp *intel_dp);
1534 void intel_dp_mst_suspend(struct drm_device *dev);
1535 void intel_dp_mst_resume(struct drm_device *dev);
1536 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1537 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1538 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1539 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1540 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1541 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1542 void intel_plane_destroy(struct drm_plane *plane);
1543 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1544 struct intel_crtc_state *crtc_state);
1545 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1546 struct intel_crtc_state *crtc_state);
1547 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1548 unsigned int frontbuffer_bits);
1549 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1550 unsigned int frontbuffer_bits);
1553 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1554 uint8_t dp_train_pat);
1556 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1557 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1559 intel_dp_voltage_max(struct intel_dp *intel_dp);
1561 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1562 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1563 uint8_t *link_bw, uint8_t *rate_select);
1564 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1566 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1568 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1570 return ~((1 << lane_count) - 1) & 0xf;
1573 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1574 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1575 struct intel_dp_desc *desc);
1576 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1577 int intel_dp_link_required(int pixel_clock, int bpp);
1578 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1579 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1580 struct intel_digital_port *port);
1582 /* intel_dp_aux_backlight.c */
1583 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1585 /* intel_dp_mst.c */
1586 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1587 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1589 void intel_dsi_init(struct drm_i915_private *dev_priv);
1591 /* intel_dsi_dcs_backlight.c */
1592 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1595 void intel_dvo_init(struct drm_i915_private *dev_priv);
1596 /* intel_hotplug.c */
1597 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1600 /* legacy fbdev emulation in intel_fbdev.c */
1601 #ifdef CONFIG_DRM_FBDEV_EMULATION
1602 extern int intel_fbdev_init(struct drm_device *dev);
1603 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1604 extern void intel_fbdev_fini(struct drm_device *dev);
1605 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1606 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1607 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1609 static inline int intel_fbdev_init(struct drm_device *dev)
1614 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1618 static inline void intel_fbdev_fini(struct drm_device *dev)
1622 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1626 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1630 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1636 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1637 struct drm_atomic_state *state);
1638 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1639 void intel_fbc_pre_update(struct intel_crtc *crtc,
1640 struct intel_crtc_state *crtc_state,
1641 struct intel_plane_state *plane_state);
1642 void intel_fbc_post_update(struct intel_crtc *crtc);
1643 void intel_fbc_init(struct drm_i915_private *dev_priv);
1644 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1645 void intel_fbc_enable(struct intel_crtc *crtc,
1646 struct intel_crtc_state *crtc_state,
1647 struct intel_plane_state *plane_state);
1648 void intel_fbc_disable(struct intel_crtc *crtc);
1649 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1650 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1651 unsigned int frontbuffer_bits,
1652 enum fb_op_origin origin);
1653 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1654 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1655 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1656 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1659 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1661 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1662 struct intel_connector *intel_connector);
1663 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1664 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1665 struct intel_crtc_state *pipe_config,
1666 struct drm_connector_state *conn_state);
1667 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1668 struct drm_connector *connector,
1669 bool high_tmds_clock_ratio,
1671 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1675 void intel_lvds_init(struct drm_i915_private *dev_priv);
1676 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1677 bool intel_is_dual_link_lvds(struct drm_device *dev);
1681 int intel_connector_update_modes(struct drm_connector *connector,
1683 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1684 void intel_attach_force_audio_property(struct drm_connector *connector);
1685 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1686 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1689 /* intel_overlay.c */
1690 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1691 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1692 int intel_overlay_switch_off(struct intel_overlay *overlay);
1693 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1694 struct drm_file *file_priv);
1695 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1696 struct drm_file *file_priv);
1697 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1701 int intel_panel_init(struct intel_panel *panel,
1702 struct drm_display_mode *fixed_mode,
1703 struct drm_display_mode *downclock_mode);
1704 void intel_panel_fini(struct intel_panel *panel);
1705 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1706 struct drm_display_mode *adjusted_mode);
1707 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1708 struct intel_crtc_state *pipe_config,
1710 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1711 struct intel_crtc_state *pipe_config,
1713 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1714 u32 level, u32 max);
1715 int intel_panel_setup_backlight(struct drm_connector *connector,
1717 void intel_panel_enable_backlight(struct intel_connector *connector);
1718 void intel_panel_disable_backlight(struct intel_connector *connector);
1719 void intel_panel_destroy_backlight(struct drm_connector *connector);
1720 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1721 extern struct drm_display_mode *intel_find_panel_downclock(
1722 struct drm_i915_private *dev_priv,
1723 struct drm_display_mode *fixed_mode,
1724 struct drm_connector *connector);
1726 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1727 int intel_backlight_device_register(struct intel_connector *connector);
1728 void intel_backlight_device_unregister(struct intel_connector *connector);
1729 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1730 static int intel_backlight_device_register(struct intel_connector *connector)
1734 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1737 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1741 void intel_psr_enable(struct intel_dp *intel_dp);
1742 void intel_psr_disable(struct intel_dp *intel_dp);
1743 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1744 unsigned frontbuffer_bits);
1745 void intel_psr_flush(struct drm_i915_private *dev_priv,
1746 unsigned frontbuffer_bits,
1747 enum fb_op_origin origin);
1748 void intel_psr_init(struct drm_i915_private *dev_priv);
1749 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1750 unsigned frontbuffer_bits);
1752 /* intel_runtime_pm.c */
1753 int intel_power_domains_init(struct drm_i915_private *);
1754 void intel_power_domains_fini(struct drm_i915_private *);
1755 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1756 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1757 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1758 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1759 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1760 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1762 intel_display_power_domain_str(enum intel_display_power_domain domain);
1764 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1765 enum intel_display_power_domain domain);
1766 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1767 enum intel_display_power_domain domain);
1768 void intel_display_power_get(struct drm_i915_private *dev_priv,
1769 enum intel_display_power_domain domain);
1770 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1771 enum intel_display_power_domain domain);
1772 void intel_display_power_put(struct drm_i915_private *dev_priv,
1773 enum intel_display_power_domain domain);
1776 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1778 WARN_ONCE(dev_priv->pm.suspended,
1779 "Device suspended during HW access\n");
1783 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1785 assert_rpm_device_not_suspended(dev_priv);
1786 WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1787 "RPM wakelock ref not held during HW access");
1791 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1792 * @dev_priv: i915 device instance
1794 * This function disable asserts that check if we hold an RPM wakelock
1795 * reference, while keeping the device-not-suspended checks still enabled.
1796 * It's meant to be used only in special circumstances where our rule about
1797 * the wakelock refcount wrt. the device power state doesn't hold. According
1798 * to this rule at any point where we access the HW or want to keep the HW in
1799 * an active state we must hold an RPM wakelock reference acquired via one of
1800 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1801 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1802 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1803 * users should avoid using this function.
1805 * Any calls to this function must have a symmetric call to
1806 * enable_rpm_wakeref_asserts().
1809 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1811 atomic_inc(&dev_priv->pm.wakeref_count);
1815 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1816 * @dev_priv: i915 device instance
1818 * This function re-enables the RPM assert checks after disabling them with
1819 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1820 * circumstances otherwise its use should be avoided.
1822 * Any calls to this function must have a symmetric call to
1823 * disable_rpm_wakeref_asserts().
1826 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1828 atomic_dec(&dev_priv->pm.wakeref_count);
1831 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1832 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1833 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1834 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1836 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1838 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1839 bool override, unsigned int mask);
1840 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1841 enum dpio_channel ch, bool override);
1845 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1846 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1847 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1848 void intel_update_watermarks(struct intel_crtc *crtc);
1849 void intel_init_pm(struct drm_i915_private *dev_priv);
1850 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1851 void intel_pm_setup(struct drm_i915_private *dev_priv);
1852 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1853 void intel_gpu_ips_teardown(void);
1854 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1855 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1856 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1857 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1858 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1859 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1860 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1861 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1862 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1863 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1864 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1865 struct intel_rps_client *rps,
1866 unsigned long submitted);
1867 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1868 void g4x_wm_get_hw_state(struct drm_device *dev);
1869 void vlv_wm_get_hw_state(struct drm_device *dev);
1870 void ilk_wm_get_hw_state(struct drm_device *dev);
1871 void skl_wm_get_hw_state(struct drm_device *dev);
1872 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1873 struct skl_ddb_allocation *ddb /* out */);
1874 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1875 struct skl_pipe_wm *out);
1876 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1877 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1878 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1879 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1880 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1881 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1882 const struct skl_wm_level *l2);
1883 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1884 const struct skl_ddb_entry *ddb,
1886 bool ilk_disable_lp_wm(struct drm_device *dev);
1887 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1888 static inline int intel_enable_rc6(void)
1890 return i915.enable_rc6;
1894 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1895 i915_reg_t reg, enum port port);
1898 /* intel_sprite.c */
1899 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1901 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1902 enum pipe pipe, int plane);
1903 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1904 struct drm_file *file_priv);
1905 void intel_pipe_update_start(struct intel_crtc *crtc);
1906 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1909 void intel_tv_init(struct drm_i915_private *dev_priv);
1911 /* intel_atomic.c */
1912 int intel_connector_atomic_get_property(struct drm_connector *connector,
1913 const struct drm_connector_state *state,
1914 struct drm_property *property,
1916 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1917 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1918 struct drm_crtc_state *state);
1919 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1920 void intel_atomic_state_clear(struct drm_atomic_state *);
1922 static inline struct intel_crtc_state *
1923 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1924 struct intel_crtc *crtc)
1926 struct drm_crtc_state *crtc_state;
1927 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1928 if (IS_ERR(crtc_state))
1929 return ERR_CAST(crtc_state);
1931 return to_intel_crtc_state(crtc_state);
1934 static inline struct intel_crtc_state *
1935 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1936 struct intel_crtc *crtc)
1938 struct drm_crtc_state *crtc_state;
1940 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1943 return to_intel_crtc_state(crtc_state);
1948 static inline struct intel_plane_state *
1949 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1950 struct intel_plane *plane)
1952 struct drm_plane_state *plane_state;
1954 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1956 return to_intel_plane_state(plane_state);
1959 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1960 struct intel_crtc *intel_crtc,
1961 struct intel_crtc_state *crtc_state);
1963 /* intel_atomic_plane.c */
1964 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1965 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1966 void intel_plane_destroy_state(struct drm_plane *plane,
1967 struct drm_plane_state *state);
1968 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1969 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1970 struct intel_plane_state *intel_state);
1973 void intel_color_init(struct drm_crtc *crtc);
1974 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1975 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1976 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1978 /* intel_lspcon.c */
1979 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1980 void lspcon_resume(struct intel_lspcon *lspcon);
1981 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1983 /* intel_pipe_crc.c */
1984 int intel_pipe_crc_create(struct drm_minor *minor);
1985 #ifdef CONFIG_DEBUG_FS
1986 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1987 size_t *values_cnt);
1989 #define intel_crtc_set_crc_source NULL
1991 extern const struct file_operations i915_display_crc_ctl_fops;
1992 #endif /* __INTEL_DRV_H__ */