drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display_limits.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_shrinker.h"
  44 #include "gem/i915_gem_stolen.h"
  45
  46 #include "gt/intel_engine.h"
  47 #include "gt/intel_gt_types.h"
  48 #include "gt/intel_region_lmem.h"
  49 #include "gt/intel_workarounds.h"
  50 #include "gt/uc/intel_uc.h"
  51
  52 #include "soc/intel_pch.h"
  53
  54 #include "i915_drm_client.h"
  55 #include "i915_gem.h"
  56 #include "i915_gpu_error.h"
  57 #include "i915_params.h"
  58 #include "i915_perf_types.h"
  59 #include "i915_scheduler.h"
  60 #include "i915_utils.h"
  61 #include "intel_device_info.h"
  62 #include "intel_memory_region.h"
  63 #include "intel_runtime_pm.h"
  64 #include "intel_step.h"
  65 #include "intel_uncore.h"
  66
  67 struct drm_i915_clock_gating_funcs;
  68 struct vlv_s0ix_state;
  69 struct intel_pxp;
  70
  71 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  72
  73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
  74 struct i915_dsm {
  75         /*
  76          * The start and end of DSM which we can optionally use to create GEM
  77          * objects backed by stolen memory.
  78          *
  79          * Note that usable_size tells us exactly how much of this we are
  80          * actually allowed to use, given that some portion of it is in fact
  81          * reserved for use by hardware functions.
  82          */
  83         struct resource stolen;
  84
  85         /*
  86          * Reserved portion of DSM.
  87          */
  88         struct resource reserved;
  89
  90         /*
  91          * Total size minus reserved ranges.
  92          *
  93          * DSM is segmented in hardware with different portions offlimits to
  94          * certain functions.
  95          *
  96          * The drm_mm is initialised to the total accessible range, as found
  97          * from the PCI config. On Broadwell+, this is further restricted to
  98          * avoid the first page! The upper end of DSM is reserved for hardware
  99          * functions and similarly removed from the accessible range.
 100          */
 101         resource_size_t usable_size;
 102 };
 103
 104 struct i915_suspend_saved_registers {
 105         u32 saveDSPARB;
 106         u32 saveSWF0[16];
 107         u32 saveSWF1[16];
 108         u32 saveSWF3[3];
 109         u16 saveGCDGMBUS;
 110 };
 111
 112 #define MAX_L3_SLICES 2
 113 struct intel_l3_parity {
 114         u32 *remap_info[MAX_L3_SLICES];
 115         struct work_struct error_work;
 116         int which_slice;
 117 };
 118
 119 struct i915_gem_mm {
 120         /*
 121          * Shortcut for the stolen region. This points to either
 122          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 123          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 124          * support stolen.
 125          */
 126         struct intel_memory_region *stolen_region;
 127         /** Memory allocator for GTT stolen memory */
 128         struct drm_mm stolen;
 129         /** Protects the usage of the GTT stolen memory allocator. This is
 130          * always the inner lock when overlapping with struct_mutex. */
 131         struct mutex stolen_lock;
 132
 133         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 134         spinlock_t obj_lock;
 135
 136         /**
 137          * List of objects which are purgeable.
 138          */
 139         struct list_head purge_list;
 140
 141         /**
 142          * List of objects which have allocated pages and are shrinkable.
 143          */
 144         struct list_head shrink_list;
 145
 146         /**
 147          * List of objects which are pending destruction.
 148          */
 149         struct llist_head free_list;
 150         struct work_struct free_work;
 151         /**
 152          * Count of objects pending destructions. Used to skip needlessly
 153          * waiting on an RCU barrier if no objects are waiting to be freed.
 154          */
 155         atomic_t free_count;
 156
 157         /**
 158          * tmpfs instance used for shmem backed objects
 159          */
 160         struct vfsmount *gemfs;
 161
 162         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 163
 164         struct notifier_block oom_notifier;
 165         struct notifier_block vmap_notifier;
 166         struct shrinker shrinker;
 167
 168 #ifdef CONFIG_MMU_NOTIFIER
 169         /**
 170          * notifier_lock for mmu notifiers, memory may not be allocated
 171          * while holding this lock.
 172          */
 173         rwlock_t notifier_lock;
 174 #endif
 175
 176         /* shrinker accounting, also useful for userland debugging */
 177         u64 shrink_memory;
 178         u32 shrink_count;
 179 };
 180
 181 struct i915_virtual_gpu {
 182         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 183         bool active;
 184         u32 caps;
 185         u32 *initial_mmio;
 186         u8 *initial_cfg_space;
 187         struct list_head entry;
 188 };
 189
 190 struct i915_selftest_stash {
 191         atomic_t counter;
 192         struct ida mock_region_instances;
 193 };
 194
 195 struct drm_i915_private {
 196         struct drm_device drm;
 197
 198         struct intel_display display;
 199
 200         /* FIXME: Device release actions should all be moved to drmm_ */
 201         bool do_release;
 202
 203         /* i915 device parameters */
 204         struct i915_params params;
 205
 206         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 207         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 208         struct intel_driver_caps caps;
 209
 210         struct i915_dsm dsm;
 211
 212         struct intel_uncore uncore;
 213         struct intel_uncore_mmio_debug mmio_debug;
 214
 215         struct i915_virtual_gpu vgpu;
 216
 217         struct intel_gvt *gvt;
 218
 219         struct {
 220                 struct pci_dev *pdev;
 221                 struct resource mch_res;
 222                 bool mchbar_need_disable;
 223         } gmch;
 224
 225         struct rb_root uabi_engines;
 226         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 227
 228         /* protects the irq masks */
 229         spinlock_t irq_lock;
 230
 231         bool display_irqs_enabled;
 232
 233         /* Sideband mailbox protection */
 234         struct mutex sb_lock;
 235         struct pm_qos_request sb_qos;
 236
 237         /** Cached value of IMR to avoid reads in updating the bitfield */
 238         union {
 239                 u32 irq_mask;
 240                 u32 de_irq_mask[I915_MAX_PIPES];
 241         };
 242         u32 pipestat_irq_mask[I915_MAX_PIPES];
 243
 244         bool preserve_bios_swizzle;
 245
 246         unsigned int fsb_freq, mem_freq, is_ddr3;
 247         unsigned int skl_preferred_vco_freq;
 248
 249         unsigned int max_dotclk_freq;
 250         unsigned int hpll_freq;
 251         unsigned int czclk_freq;
 252
 253         /**
 254          * wq - Driver workqueue for GEM.
 255          *
 256          * NOTE: Work items scheduled here are not allowed to grab any modeset
 257          * locks, for otherwise the flushing done in the pageflip code will
 258          * result in deadlocks.
 259          */
 260         struct workqueue_struct *wq;
 261
 262         /* pm private clock gating functions */
 263         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 264
 265         /* PCH chipset type */
 266         enum intel_pch pch_type;
 267         unsigned short pch_id;
 268
 269         unsigned long gem_quirks;
 270
 271         struct i915_gem_mm mm;
 272
 273         struct intel_l3_parity l3_parity;
 274
 275         /*
 276          * edram size in MB.
 277          * Cannot be determined by PCIID. You must always read a register.
 278          */
 279         u32 edram_size_mb;
 280
 281         struct i915_gpu_error gpu_error;
 282
 283         u32 suspend_count;
 284         struct i915_suspend_saved_registers regfile;
 285         struct vlv_s0ix_state *vlv_s0ix_state;
 286
 287         struct dram_info {
 288                 bool wm_lv_0_adjust_needed;
 289                 u8 num_channels;
 290                 bool symmetric_memory;
 291                 enum intel_dram_type {
 292                         INTEL_DRAM_UNKNOWN,
 293                         INTEL_DRAM_DDR3,
 294                         INTEL_DRAM_DDR4,
 295                         INTEL_DRAM_LPDDR3,
 296                         INTEL_DRAM_LPDDR4,
 297                         INTEL_DRAM_DDR5,
 298                         INTEL_DRAM_LPDDR5,
 299                 } type;
 300                 u8 num_qgv_points;
 301                 u8 num_psf_gv_points;
 302         } dram_info;
 303
 304         struct intel_runtime_pm runtime_pm;
 305
 306         struct i915_perf perf;
 307
 308         struct i915_hwmon *hwmon;
 309
 310         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 311         struct intel_gt gt0;
 312
 313         /*
 314          * i915->gt[0] == &i915->gt0
 315          */
 316 #define I915_MAX_GT 4
 317         struct intel_gt *gt[I915_MAX_GT];
 318
 319         struct kobject *sysfs_gt;
 320
 321         /* Quick lookup of media GT (current platforms only have one) */
 322         struct intel_gt *media_gt;
 323
 324         struct {
 325                 struct i915_gem_contexts {
 326                         spinlock_t lock; /* locks list */
 327                         struct list_head list;
 328                 } contexts;
 329
 330                 /*
 331                  * We replace the local file with a global mappings as the
 332                  * backing storage for the mmap is on the device and not
 333                  * on the struct file, and we do not want to prolong the
 334                  * lifetime of the local fd. To minimise the number of
 335                  * anonymous inodes we create, we use a global singleton to
 336                  * share the global mapping.
 337                  */
 338                 struct file *mmap_singleton;
 339         } gem;
 340
 341         struct intel_pxp *pxp;
 342
 343         /* For i915gm/i945gm vblank irq workaround */
 344         u8 vblank_enabled;
 345
 346         bool irq_enabled;
 347
 348         struct i915_pmu pmu;
 349
 350         struct i915_drm_clients clients;
 351
 352         /* The TTM device structure. */
 353         struct ttm_device bdev;
 354
 355         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 356
 357         /*
 358          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 359          * will be rejected. Instead look for a better place.
 360          */
 361 };
 362
 363 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 364 {
 365         return container_of(dev, struct drm_i915_private, drm);
 366 }
 367
 368 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 369 {
 370         return dev_get_drvdata(kdev);
 371 }
 372
 373 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 374 {
 375         return pci_get_drvdata(pdev);
 376 }
 377
 378 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 379 {
 380         return &i915->gt0;
 381 }
 382
 383 /* Simple iterator over all initialised engines */
 384 #define for_each_engine(engine__, dev_priv__, id__) \
 385         for ((id__) = 0; \
 386              (id__) < I915_NUM_ENGINES; \
 387              (id__)++) \
 388                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 389
 390 /* Iterator over subset of engines selected by mask */
 391 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 392         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 393              (tmp__) ? \
 394              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 395              0;)
 396
 397 #define rb_to_uabi_engine(rb) \
 398         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 399
 400 #define for_each_uabi_engine(engine__, i915__) \
 401         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 402              (engine__); \
 403              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 404
 405 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 406         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 407              (engine__) && (engine__)->uabi_class == (class__); \
 408              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 409
 410 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 411 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 412 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 413
 414 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 415
 416 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 417
 418 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 419 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 420                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 421 #define IS_GRAPHICS_VER(i915, from, until) \
 422         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 423
 424 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 425 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 426                                                RUNTIME_INFO(i915)->media.ip.rel)
 427 #define IS_MEDIA_VER(i915, from, until) \
 428         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 429
 430 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 431 #define IS_DISPLAY_VER(i915, from, until) \
 432         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 433
 434 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 435
 436 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 437 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 438 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 439 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 440
 441 #define IS_DISPLAY_STEP(__i915, since, until) \
 442         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 443          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 444
 445 #define IS_GRAPHICS_STEP(__i915, since, until) \
 446         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 447          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 448
 449 #define IS_MEDIA_STEP(__i915, since, until) \
 450         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 451          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 452
 453 #define IS_BASEDIE_STEP(__i915, since, until) \
 454         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 455          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 456
 457 static __always_inline unsigned int
 458 __platform_mask_index(const struct intel_runtime_info *info,
 459                       enum intel_platform p)
 460 {
 461         const unsigned int pbits =
 462                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 463
 464         /* Expand the platform_mask array if this fails. */
 465         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 466                      pbits * ARRAY_SIZE(info->platform_mask));
 467
 468         return p / pbits;
 469 }
 470
 471 static __always_inline unsigned int
 472 __platform_mask_bit(const struct intel_runtime_info *info,
 473                     enum intel_platform p)
 474 {
 475         const unsigned int pbits =
 476                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 477
 478         return p % pbits + INTEL_SUBPLATFORM_BITS;
 479 }
 480
 481 static inline u32
 482 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 483 {
 484         const unsigned int pi = __platform_mask_index(info, p);
 485
 486         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 487 }
 488
 489 static __always_inline bool
 490 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 491 {
 492         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 493         const unsigned int pi = __platform_mask_index(info, p);
 494         const unsigned int pb = __platform_mask_bit(info, p);
 495
 496         BUILD_BUG_ON(!__builtin_constant_p(p));
 497
 498         return info->platform_mask[pi] & BIT(pb);
 499 }
 500
 501 static __always_inline bool
 502 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 503                enum intel_platform p, unsigned int s)
 504 {
 505         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 506         const unsigned int pi = __platform_mask_index(info, p);
 507         const unsigned int pb = __platform_mask_bit(info, p);
 508         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 509         const u32 mask = info->platform_mask[pi];
 510
 511         BUILD_BUG_ON(!__builtin_constant_p(p));
 512         BUILD_BUG_ON(!__builtin_constant_p(s));
 513         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 514
 515         /* Shift and test on the MSB position so sign flag can be used. */
 516         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 517 }
 518
 519 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 520 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 521
 522 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 523 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 524 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 525 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 526 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 527 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 528 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 529 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 530 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 531 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 532 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 533 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 534 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 535 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 536 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 537 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 538 #define IS_IRONLAKE_M(dev_priv) \
 539         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 540 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 541 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 542 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 543                                  INTEL_INFO(dev_priv)->gt == 1)
 544 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 545 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 546 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 547 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 548 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 549 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 550 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 551 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 552 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 553 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 554 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 555 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 556                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 557 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 558 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 559 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 560 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 561 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 562 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 563 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 564 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 565 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 566
 567 #define IS_METEORLAKE_M(dev_priv) \
 568         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 569 #define IS_METEORLAKE_P(dev_priv) \
 570         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 571 #define IS_DG2_G10(dev_priv) \
 572         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 573 #define IS_DG2_G11(dev_priv) \
 574         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 575 #define IS_DG2_G12(dev_priv) \
 576         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 577 #define IS_ADLS_RPLS(dev_priv) \
 578         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 579 #define IS_ADLP_N(dev_priv) \
 580         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 581 #define IS_ADLP_RPLP(dev_priv) \
 582         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 583 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 584                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 585 #define IS_BDW_ULT(dev_priv) \
 586         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 587 #define IS_BDW_ULX(dev_priv) \
 588         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 589 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 590                                  INTEL_INFO(dev_priv)->gt == 3)
 591 #define IS_HSW_ULT(dev_priv) \
 592         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 593 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 594                                  INTEL_INFO(dev_priv)->gt == 3)
 595 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 596                                  INTEL_INFO(dev_priv)->gt == 1)
 597 /* ULX machines are also considered ULT. */
 598 #define IS_HSW_ULX(dev_priv) \
 599         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 600 #define IS_SKL_ULT(dev_priv) \
 601         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 602 #define IS_SKL_ULX(dev_priv) \
 603         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 604 #define IS_KBL_ULT(dev_priv) \
 605         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 606 #define IS_KBL_ULX(dev_priv) \
 607         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 608 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 609                                  INTEL_INFO(dev_priv)->gt == 2)
 610 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 611                                  INTEL_INFO(dev_priv)->gt == 3)
 612 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 613                                  INTEL_INFO(dev_priv)->gt == 4)
 614 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 615                                  INTEL_INFO(dev_priv)->gt == 2)
 616 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 617                                  INTEL_INFO(dev_priv)->gt == 3)
 618 #define IS_CFL_ULT(dev_priv) \
 619         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 620 #define IS_CFL_ULX(dev_priv) \
 621         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 622 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 623                                  INTEL_INFO(dev_priv)->gt == 2)
 624 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 625                                  INTEL_INFO(dev_priv)->gt == 3)
 626
 627 #define IS_CML_ULT(dev_priv) \
 628         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 629 #define IS_CML_ULX(dev_priv) \
 630         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 631 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 632                                  INTEL_INFO(dev_priv)->gt == 2)
 633
 634 #define IS_ICL_WITH_PORT_F(dev_priv) \
 635         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 636
 637 #define IS_TGL_UY(dev_priv) \
 638         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 639
 640 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 641
 642 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 643         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 644 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 645         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 646
 647 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 648         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 649 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 650         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 651
 652 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 653         (IS_TIGERLAKE(__i915) && \
 654          IS_DISPLAY_STEP(__i915, since, until))
 655
 656 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 657         (IS_TGL_UY(__i915) && \
 658          IS_GRAPHICS_STEP(__i915, since, until))
 659
 660 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 661         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 662          IS_GRAPHICS_STEP(__i915, since, until))
 663
 664 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 665         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 666
 667 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 668         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 669 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 670         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 671
 672 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 673         (IS_ALDERLAKE_S(__i915) && \
 674          IS_DISPLAY_STEP(__i915, since, until))
 675
 676 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 677         (IS_ALDERLAKE_S(__i915) && \
 678          IS_GRAPHICS_STEP(__i915, since, until))
 679
 680 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 681         (IS_ALDERLAKE_P(__i915) && \
 682          IS_DISPLAY_STEP(__i915, since, until))
 683
 684 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 685         (IS_ALDERLAKE_P(__i915) && \
 686          IS_GRAPHICS_STEP(__i915, since, until))
 687
 688 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 689         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 690
 691 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
 692         (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 693          IS_GRAPHICS_STEP(__i915, since, until))
 694
 695 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
 696         (IS_METEORLAKE(__i915) && \
 697          IS_DISPLAY_STEP(__i915, since, until))
 698
 699 #define IS_MTL_MEDIA_STEP(__i915, since, until) \
 700         (IS_METEORLAKE(__i915) && \
 701          IS_MEDIA_STEP(__i915, since, until))
 702
 703 /*
 704  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 705  * create three variants (G10, G11, and G12) which each have distinct
 706  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 707  * stepping back to "A0" for their first iterations, even though they're more
 708  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 709  * functionality and workarounds.  However the display stepping does not reset
 710  * in the same manner --- a specific stepping like "B0" has a consistent
 711  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 712  *
 713  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 714  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 715  * and stepping-specific logic will be applied with a general DG2-wide stepping
 716  * number.
 717  */
 718 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 719         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 720          IS_GRAPHICS_STEP(__i915, since, until))
 721
 722 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 723         (IS_DG2(__i915) && \
 724          IS_DISPLAY_STEP(__i915, since, until))
 725
 726 #define IS_PVC_BD_STEP(__i915, since, until) \
 727         (IS_PONTEVECCHIO(__i915) && \
 728          IS_BASEDIE_STEP(__i915, since, until))
 729
 730 #define IS_PVC_CT_STEP(__i915, since, until) \
 731         (IS_PONTEVECCHIO(__i915) && \
 732          IS_GRAPHICS_STEP(__i915, since, until))
 733
 734 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 735 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 736 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 737
 738 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 739 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 740
 741 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({                  \
 742         unsigned int first__ = (first);                                 \
 743         unsigned int count__ = (count);                                 \
 744         ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;  \
 745 })
 746
 747 #define ENGINE_INSTANCES_MASK(gt, first, count) \
 748         __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
 749
 750 #define RCS_MASK(gt) \
 751         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 752 #define BCS_MASK(gt) \
 753         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 754 #define VDBOX_MASK(gt) \
 755         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 756 #define VEBOX_MASK(gt) \
 757         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 758 #define CCS_MASK(gt) \
 759         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 760
 761 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 762
 763 /*
 764  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 765  * All later gens can run the final buffer from the ppgtt
 766  */
 767 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 768
 769 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 770 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 771 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 772 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 773 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 774 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 775
 776 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 777
 778 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 779                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 780 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 781                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 782
 783 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 784
 785 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 786 #define HAS_PPGTT(dev_priv) \
 787         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 788 #define HAS_FULL_PPGTT(dev_priv) \
 789         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 790
 791 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 792         GEM_BUG_ON((sizes) == 0); \
 793         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 794 })
 795
 796 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 797 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 798                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 799
 800 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 801 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 802
 803 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 804         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 805
 806 /* WaRsDisableCoarsePowerGating:skl,cnl */
 807 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 808         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 809
 810 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 811 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 812                                         IS_GEMINILAKE(dev_priv) || \
 813                                         IS_KABYLAKE(dev_priv))
 814
 815 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 816  * rows, which changed the alignment requirements and fence programming.
 817  */
 818 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 819                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 820 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 821 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 822
 823 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 824 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 825 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 826
 827 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 828
 829 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 830 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 831
 832 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 833
 834 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 835 #define HAS_CDCLK_SQUASH(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 836 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 837 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 838 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 839 #define HAS_PSR_HW_TRACKING(dev_priv) \
 840         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 841 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 842 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 843
 844 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 845 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 846 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 847
 848 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 849
 850 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 851 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 852 #define HAS_DSC(__i915)         (RUNTIME_INFO(__i915)->has_dsc)
 853 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 854
 855 #define HAS_HECI_PXP(dev_priv) \
 856         (INTEL_INFO(dev_priv)->has_heci_pxp)
 857
 858 #define HAS_HECI_GSCFI(dev_priv) \
 859         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 860
 861 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 862
 863 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 864
 865 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 866 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 867
 868 #define HAS_OA_BPC_REPORTING(dev_priv) \
 869         (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
 870 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
 871         (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 872
 873 /*
 874  * Set this flag, when platform requires 64K GTT page sizes or larger for
 875  * device local memory access.
 876  */
 877 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 878
 879 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 880
 881 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 882 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 883
 884 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 885
 886 /*
 887  * Platform has the dedicated compression control state for each lmem surfaces
 888  * stored in lmem to support the 3D and media compression formats.
 889  */
 890 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 891
 892 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 893
 894 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 895
 896 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 897
 898 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 899
 900 #define HAS_GMD_ID(i915)        (INTEL_INFO(i915)->has_gmd_id)
 901
 902 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 903
 904 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 905
 906 /* DPF == dynamic parity feature */
 907 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 908 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 909                                  2 : HAS_L3_DPF(dev_priv))
 910
 911 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 912
 913 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 914
 915 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 916
 917 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 918
 919 /* Only valid when HAS_DISPLAY() is true */
 920 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 921         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 922          !(dev_priv)->params.disable_display &&                         \
 923          !intel_opregion_headless_sku(dev_priv))
 924
 925 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 926         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 927
 928 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 929                                               IS_ALDERLAKE_S(dev_priv))
 930
 931 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 932
 933 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 934
 935 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 936
 937 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
 938                                        GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 939
 940 /* intel_device_info.c */
 941 static inline struct intel_device_info *
 942 mkwrite_device_info(struct drm_i915_private *dev_priv)
 943 {
 944         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 945 }
 946
 947 #endif