1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
35 #include <linux/pm_qos.h>
37 #include <drm/ttm/ttm_device.h>
39 #include "display/intel_display.h"
40 #include "display/intel_display_core.h"
42 #include "gem/i915_gem_context_types.h"
43 #include "gem/i915_gem_shrinker.h"
44 #include "gem/i915_gem_stolen.h"
46 #include "gt/intel_engine.h"
47 #include "gt/intel_gt_types.h"
48 #include "gt/intel_region_lmem.h"
49 #include "gt/intel_workarounds.h"
50 #include "gt/uc/intel_uc.h"
52 #include "soc/intel_pch.h"
54 #include "i915_drm_client.h"
56 #include "i915_gpu_error.h"
57 #include "i915_params.h"
58 #include "i915_perf_types.h"
59 #include "i915_scheduler.h"
60 #include "i915_utils.h"
61 #include "intel_device_info.h"
62 #include "intel_memory_region.h"
63 #include "intel_runtime_pm.h"
64 #include "intel_step.h"
65 #include "intel_uncore.h"
67 struct drm_i915_clock_gating_funcs;
68 struct drm_i915_gem_object;
69 struct drm_i915_private;
70 struct intel_connector;
74 struct intel_overlay_error_state;
75 struct vlv_s0ix_state;
77 #define I915_GEM_GPU_DOMAINS \
78 (I915_GEM_DOMAIN_RENDER | \
79 I915_GEM_DOMAIN_SAMPLER | \
80 I915_GEM_DOMAIN_COMMAND | \
81 I915_GEM_DOMAIN_INSTRUCTION | \
82 I915_GEM_DOMAIN_VERTEX)
84 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
86 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
88 struct i915_suspend_saved_registers {
96 #define MAX_L3_SLICES 2
97 struct intel_l3_parity {
98 u32 *remap_info[MAX_L3_SLICES];
99 struct work_struct error_work;
105 * Shortcut for the stolen region. This points to either
106 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
107 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
110 struct intel_memory_region *stolen_region;
111 /** Memory allocator for GTT stolen memory */
112 struct drm_mm stolen;
113 /** Protects the usage of the GTT stolen memory allocator. This is
114 * always the inner lock when overlapping with struct_mutex. */
115 struct mutex stolen_lock;
117 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
121 * List of objects which are purgeable.
123 struct list_head purge_list;
126 * List of objects which have allocated pages and are shrinkable.
128 struct list_head shrink_list;
131 * List of objects which are pending destruction.
133 struct llist_head free_list;
134 struct work_struct free_work;
136 * Count of objects pending destructions. Used to skip needlessly
137 * waiting on an RCU barrier if no objects are waiting to be freed.
142 * tmpfs instance used for shmem backed objects
144 struct vfsmount *gemfs;
146 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
148 struct notifier_block oom_notifier;
149 struct notifier_block vmap_notifier;
150 struct shrinker shrinker;
152 #ifdef CONFIG_MMU_NOTIFIER
154 * notifier_lock for mmu notifiers, memory may not be allocated
155 * while holding this lock.
157 rwlock_t notifier_lock;
160 /* shrinker accounting, also useful for userland debugging */
165 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
167 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
170 static inline unsigned long
171 i915_fence_timeout(const struct drm_i915_private *i915)
173 return i915_fence_context_timeout(i915, U64_MAX);
176 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
178 struct i915_virtual_gpu {
179 struct mutex lock; /* serialises sending of g2v_notify command pkts */
183 u8 *initial_cfg_space;
184 struct list_head entry;
187 struct i915_selftest_stash {
189 struct ida mock_region_instances;
192 struct drm_i915_private {
193 struct drm_device drm;
195 struct intel_display display;
197 /* FIXME: Device release actions should all be moved to drmm_ */
200 /* i915 device parameters */
201 struct i915_params params;
203 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
204 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
205 struct intel_driver_caps caps;
208 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
209 * end of stolen which we can optionally use to create GEM objects
210 * backed by stolen memory. Note that stolen_usable_size tells us
211 * exactly how much of this we are actually allowed to use, given that
212 * some portion of it is in fact reserved for use by hardware functions.
216 * Reseved portion of Data Stolen Memory
218 struct resource dsm_reserved;
221 * Stolen memory is segmented in hardware with different portions
222 * offlimits to certain functions.
224 * The drm_mm is initialised to the total accessible range, as found
225 * from the PCI config. On Broadwell+, this is further restricted to
226 * avoid the first page! The upper end of stolen memory is reserved for
227 * hardware functions and similarly removed from the accessible range.
229 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
231 struct intel_uncore uncore;
232 struct intel_uncore_mmio_debug mmio_debug;
234 struct i915_virtual_gpu vgpu;
236 struct intel_gvt *gvt;
238 struct pci_dev *bridge_dev;
240 struct rb_root uabi_engines;
241 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
243 struct resource mch_res;
245 /* protects the irq masks */
248 bool display_irqs_enabled;
250 /* Sideband mailbox protection */
251 struct mutex sb_lock;
252 struct pm_qos_request sb_qos;
254 /** Cached value of IMR to avoid reads in updating the bitfield */
257 u32 de_irq_mask[I915_MAX_PIPES];
259 u32 pipestat_irq_mask[I915_MAX_PIPES];
261 bool preserve_bios_swizzle;
263 unsigned int fsb_freq, mem_freq, is_ddr3;
264 unsigned int skl_preferred_vco_freq;
266 unsigned int max_dotclk_freq;
267 unsigned int hpll_freq;
268 unsigned int czclk_freq;
271 * wq - Driver workqueue for GEM.
273 * NOTE: Work items scheduled here are not allowed to grab any modeset
274 * locks, for otherwise the flushing done in the pageflip code will
275 * result in deadlocks.
277 struct workqueue_struct *wq;
279 /* pm private clock gating functions */
280 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
282 /* PCH chipset type */
283 enum intel_pch pch_type;
284 unsigned short pch_id;
286 unsigned long gem_quirks;
288 struct i915_gem_mm mm;
290 bool mchbar_need_disable;
292 struct intel_l3_parity l3_parity;
296 * Cannot be determined by PCIID. You must always read a register.
300 struct i915_gpu_error gpu_error;
303 * Shadows for CHV DPLL_MD regs to keep the state
304 * checker somewhat working in the presence hardware
305 * crappiness (can't read out DPLL_MD for pipes B & C).
307 u32 chv_dpll_md[I915_MAX_PIPES];
311 struct i915_suspend_saved_registers regfile;
312 struct vlv_s0ix_state *vlv_s0ix_state;
315 bool wm_lv_0_adjust_needed;
317 bool symmetric_memory;
318 enum intel_dram_type {
328 u8 num_psf_gv_points;
331 struct intel_runtime_pm runtime_pm;
333 struct i915_perf perf;
335 struct i915_hwmon *hwmon;
337 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
341 * i915->gt[0] == &i915->gt0
343 #define I915_MAX_GT 4
344 struct intel_gt *gt[I915_MAX_GT];
346 struct kobject *sysfs_gt;
348 /* Quick lookup of media GT (current platforms only have one) */
349 struct intel_gt *media_gt;
352 struct i915_gem_contexts {
353 spinlock_t lock; /* locks list */
354 struct list_head list;
358 * We replace the local file with a global mappings as the
359 * backing storage for the mmap is on the device and not
360 * on the struct file, and we do not want to prolong the
361 * lifetime of the local fd. To minimise the number of
362 * anonymous inodes we create, we use a global singleton to
363 * share the global mapping.
365 struct file *mmap_singleton;
370 /* For i915gm/i945gm vblank irq workaround */
376 * DG2: Mask of PHYs that were not calibrated by the firmware
377 * and should not be used.
379 u8 snps_phy_failed_calibration;
383 struct i915_drm_clients clients;
385 /* The TTM device structure. */
386 struct ttm_device bdev;
388 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
391 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
392 * will be rejected. Instead look for a better place.
396 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
398 return container_of(dev, struct drm_i915_private, drm);
401 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
403 return dev_get_drvdata(kdev);
406 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
408 return pci_get_drvdata(pdev);
411 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
416 /* Simple iterator over all initialised engines */
417 #define for_each_engine(engine__, dev_priv__, id__) \
419 (id__) < I915_NUM_ENGINES; \
421 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
423 /* Iterator over subset of engines selected by mask */
424 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
425 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
427 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
430 #define rb_to_uabi_engine(rb) \
431 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
433 #define for_each_uabi_engine(engine__, i915__) \
434 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
436 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
438 #define for_each_uabi_class_engine(engine__, class__, i915__) \
439 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
440 (engine__) && (engine__)->uabi_class == (class__); \
441 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
443 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
444 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
445 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
447 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
449 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
451 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
452 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
453 RUNTIME_INFO(i915)->graphics.ip.rel)
454 #define IS_GRAPHICS_VER(i915, from, until) \
455 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
457 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
458 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
459 RUNTIME_INFO(i915)->media.ip.rel)
460 #define IS_MEDIA_VER(i915, from, until) \
461 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
463 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
464 #define IS_DISPLAY_VER(i915, from, until) \
465 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
467 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
469 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
470 #define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
472 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
473 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
474 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
475 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
477 #define IS_DISPLAY_STEP(__i915, since, until) \
478 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
479 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
481 #define IS_GRAPHICS_STEP(__i915, since, until) \
482 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
483 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
485 #define IS_MEDIA_STEP(__i915, since, until) \
486 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
487 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
489 #define IS_BASEDIE_STEP(__i915, since, until) \
490 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
491 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
493 static __always_inline unsigned int
494 __platform_mask_index(const struct intel_runtime_info *info,
495 enum intel_platform p)
497 const unsigned int pbits =
498 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
500 /* Expand the platform_mask array if this fails. */
501 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
502 pbits * ARRAY_SIZE(info->platform_mask));
507 static __always_inline unsigned int
508 __platform_mask_bit(const struct intel_runtime_info *info,
509 enum intel_platform p)
511 const unsigned int pbits =
512 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
514 return p % pbits + INTEL_SUBPLATFORM_BITS;
518 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
520 const unsigned int pi = __platform_mask_index(info, p);
522 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
525 static __always_inline bool
526 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
528 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
529 const unsigned int pi = __platform_mask_index(info, p);
530 const unsigned int pb = __platform_mask_bit(info, p);
532 BUILD_BUG_ON(!__builtin_constant_p(p));
534 return info->platform_mask[pi] & BIT(pb);
537 static __always_inline bool
538 IS_SUBPLATFORM(const struct drm_i915_private *i915,
539 enum intel_platform p, unsigned int s)
541 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
542 const unsigned int pi = __platform_mask_index(info, p);
543 const unsigned int pb = __platform_mask_bit(info, p);
544 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
545 const u32 mask = info->platform_mask[pi];
547 BUILD_BUG_ON(!__builtin_constant_p(p));
548 BUILD_BUG_ON(!__builtin_constant_p(s));
549 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
551 /* Shift and test on the MSB position so sign flag can be used. */
552 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
555 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
556 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
558 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
559 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
560 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
561 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
562 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
563 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
564 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
565 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
566 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
567 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
568 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
569 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
570 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
571 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
572 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
573 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
574 #define IS_IRONLAKE_M(dev_priv) \
575 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
576 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
577 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
578 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
579 INTEL_INFO(dev_priv)->gt == 1)
580 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
581 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
582 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
583 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
584 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
585 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
586 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
587 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
588 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
589 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
590 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
591 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
592 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
593 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
594 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
595 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
596 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
597 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
598 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
599 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
600 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
601 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
603 #define IS_METEORLAKE_M(dev_priv) \
604 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
605 #define IS_METEORLAKE_P(dev_priv) \
606 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
607 #define IS_DG2_G10(dev_priv) \
608 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
609 #define IS_DG2_G11(dev_priv) \
610 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
611 #define IS_DG2_G12(dev_priv) \
612 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
613 #define IS_ADLS_RPLS(dev_priv) \
614 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
615 #define IS_ADLP_N(dev_priv) \
616 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
617 #define IS_ADLP_RPLP(dev_priv) \
618 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
619 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
620 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
621 #define IS_BDW_ULT(dev_priv) \
622 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
623 #define IS_BDW_ULX(dev_priv) \
624 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
625 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
626 INTEL_INFO(dev_priv)->gt == 3)
627 #define IS_HSW_ULT(dev_priv) \
628 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
629 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
630 INTEL_INFO(dev_priv)->gt == 3)
631 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
632 INTEL_INFO(dev_priv)->gt == 1)
633 /* ULX machines are also considered ULT. */
634 #define IS_HSW_ULX(dev_priv) \
635 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
636 #define IS_SKL_ULT(dev_priv) \
637 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
638 #define IS_SKL_ULX(dev_priv) \
639 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
640 #define IS_KBL_ULT(dev_priv) \
641 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
642 #define IS_KBL_ULX(dev_priv) \
643 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
644 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
645 INTEL_INFO(dev_priv)->gt == 2)
646 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
647 INTEL_INFO(dev_priv)->gt == 3)
648 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
649 INTEL_INFO(dev_priv)->gt == 4)
650 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
651 INTEL_INFO(dev_priv)->gt == 2)
652 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
653 INTEL_INFO(dev_priv)->gt == 3)
654 #define IS_CFL_ULT(dev_priv) \
655 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
656 #define IS_CFL_ULX(dev_priv) \
657 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
658 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
659 INTEL_INFO(dev_priv)->gt == 2)
660 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
661 INTEL_INFO(dev_priv)->gt == 3)
663 #define IS_CML_ULT(dev_priv) \
664 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
665 #define IS_CML_ULX(dev_priv) \
666 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
667 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
668 INTEL_INFO(dev_priv)->gt == 2)
670 #define IS_ICL_WITH_PORT_F(dev_priv) \
671 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
673 #define IS_TGL_UY(dev_priv) \
674 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
676 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
678 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
679 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
680 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
681 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
683 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
684 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
685 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
686 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
688 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
689 (IS_TIGERLAKE(__i915) && \
690 IS_DISPLAY_STEP(__i915, since, until))
692 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
693 (IS_TGL_UY(__i915) && \
694 IS_GRAPHICS_STEP(__i915, since, until))
696 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
697 (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
698 IS_GRAPHICS_STEP(__i915, since, until))
700 #define IS_RKL_DISPLAY_STEP(p, since, until) \
701 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
703 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
704 (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
705 #define IS_DG1_DISPLAY_STEP(p, since, until) \
706 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
708 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
709 (IS_ALDERLAKE_S(__i915) && \
710 IS_DISPLAY_STEP(__i915, since, until))
712 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
713 (IS_ALDERLAKE_S(__i915) && \
714 IS_GRAPHICS_STEP(__i915, since, until))
716 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
717 (IS_ALDERLAKE_P(__i915) && \
718 IS_DISPLAY_STEP(__i915, since, until))
720 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
721 (IS_ALDERLAKE_P(__i915) && \
722 IS_GRAPHICS_STEP(__i915, since, until))
724 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
725 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
727 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
728 (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
729 IS_GRAPHICS_STEP(__i915, since, until))
731 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
732 (IS_METEORLAKE(__i915) && \
733 IS_DISPLAY_STEP(__i915, since, until))
736 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
737 * create three variants (G10, G11, and G12) which each have distinct
738 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
739 * stepping back to "A0" for their first iterations, even though they're more
740 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
741 * functionality and workarounds. However the display stepping does not reset
742 * in the same manner --- a specific stepping like "B0" has a consistent
743 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
745 * TLDR: All GT workarounds and stepping-specific logic must be applied in
746 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
747 * and stepping-specific logic will be applied with a general DG2-wide stepping
750 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
751 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
752 IS_GRAPHICS_STEP(__i915, since, until))
754 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
756 IS_DISPLAY_STEP(__i915, since, until))
758 #define IS_PVC_BD_STEP(__i915, since, until) \
759 (IS_PONTEVECCHIO(__i915) && \
760 IS_BASEDIE_STEP(__i915, since, until))
762 #define IS_PVC_CT_STEP(__i915, since, until) \
763 (IS_PONTEVECCHIO(__i915) && \
764 IS_GRAPHICS_STEP(__i915, since, until))
766 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
767 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
768 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
770 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
771 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
773 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
774 unsigned int first__ = (first); \
775 unsigned int count__ = (count); \
776 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
779 #define ENGINE_INSTANCES_MASK(gt, first, count) \
780 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
782 #define RCS_MASK(gt) \
783 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
784 #define BCS_MASK(gt) \
785 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
786 #define VDBOX_MASK(gt) \
787 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
788 #define VEBOX_MASK(gt) \
789 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
790 #define CCS_MASK(gt) \
791 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
793 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
796 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
797 * All later gens can run the final buffer from the ppgtt
799 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
801 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
802 #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
803 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
804 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
805 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
806 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
808 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
810 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
811 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
812 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
813 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
815 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
817 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
818 #define HAS_PPGTT(dev_priv) \
819 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
820 #define HAS_FULL_PPGTT(dev_priv) \
821 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
823 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
824 GEM_BUG_ON((sizes) == 0); \
825 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
828 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
829 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
830 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
832 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
833 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
835 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
836 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
838 /* WaRsDisableCoarsePowerGating:skl,cnl */
839 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
840 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
842 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
843 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
844 IS_GEMINILAKE(dev_priv) || \
845 IS_KABYLAKE(dev_priv))
847 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
848 * rows, which changed the alignment requirements and fence programming.
850 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
851 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
852 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
853 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
855 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
856 #define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
857 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
859 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
861 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
862 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
864 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
866 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
867 #define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
868 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
869 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
870 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
871 #define HAS_PSR_HW_TRACKING(dev_priv) \
872 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
873 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
874 #define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
876 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
877 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
878 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
880 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
882 #define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
884 #define HAS_HECI_PXP(dev_priv) \
885 (INTEL_INFO(dev_priv)->has_heci_pxp)
887 #define HAS_HECI_GSCFI(dev_priv) \
888 (INTEL_INFO(dev_priv)->has_heci_gscfi)
890 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
892 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
894 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
895 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
897 #define HAS_OA_BPC_REPORTING(dev_priv) \
898 (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
899 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
900 (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
903 * Set this flag, when platform requires 64K GTT page sizes or larger for
904 * device local memory access.
906 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
908 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
910 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
911 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
913 #define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
916 * Platform has the dedicated compression control state for each lmem surfaces
917 * stored in lmem to support the 3D and media compression formats.
919 #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
921 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
923 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
925 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
927 #define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
928 INTEL_INFO(dev_priv)->has_pxp) && \
929 VDBOX_MASK(to_gt(dev_priv)))
931 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
933 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
935 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
937 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
939 /* DPF == dynamic parity feature */
940 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
941 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
942 2 : HAS_L3_DPF(dev_priv))
944 #define GT_FREQUENCY_MULTIPLIER 50
945 #define GEN9_FREQ_SCALER 3
947 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
949 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
951 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
953 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
955 /* Only valid when HAS_DISPLAY() is true */
956 #define INTEL_DISPLAY_ENABLED(dev_priv) \
957 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
958 !(dev_priv)->params.disable_display && \
959 !intel_opregion_headless_sku(dev_priv))
961 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
962 (INTEL_INFO(dev_priv)->has_guc_deprivilege)
964 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
965 IS_ALDERLAKE_S(dev_priv))
967 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
969 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
971 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
973 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
974 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
976 /* intel_device_info.c */
977 static inline struct intel_device_info *
978 mkwrite_device_info(struct drm_i915_private *dev_priv)
980 return (struct intel_device_info *)INTEL_INFO(dev_priv);