drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_lmem.h"
  44 #include "gem/i915_gem_shrinker.h"
  45 #include "gem/i915_gem_stolen.h"
  46
  47 #include "gt/intel_engine.h"
  48 #include "gt/intel_gt_types.h"
  49 #include "gt/intel_region_lmem.h"
  50 #include "gt/intel_workarounds.h"
  51 #include "gt/uc/intel_uc.h"
  52
  53 #include "i915_drm_client.h"
  54 #include "i915_gem.h"
  55 #include "i915_gpu_error.h"
  56 #include "i915_params.h"
  57 #include "i915_perf_types.h"
  58 #include "i915_scheduler.h"
  59 #include "i915_utils.h"
  60 #include "intel_device_info.h"
  61 #include "intel_memory_region.h"
  62 #include "intel_pch.h"
  63 #include "intel_runtime_pm.h"
  64 #include "intel_step.h"
  65 #include "intel_uncore.h"
  66 #include "intel_wopcm.h"
  67
  68 struct drm_i915_clock_gating_funcs;
  69 struct drm_i915_gem_object;
  70 struct drm_i915_private;
  71 struct intel_connector;
  72 struct intel_dp;
  73 struct intel_encoder;
  74 struct intel_limit;
  75 struct intel_overlay_error_state;
  76 struct vlv_s0ix_state;
  77
  78 #define I915_GEM_GPU_DOMAINS \
  79         (I915_GEM_DOMAIN_RENDER | \
  80          I915_GEM_DOMAIN_SAMPLER | \
  81          I915_GEM_DOMAIN_COMMAND | \
  82          I915_GEM_DOMAIN_INSTRUCTION | \
  83          I915_GEM_DOMAIN_VERTEX)
  84
  85 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
  86
  87 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  88
  89 struct i915_suspend_saved_registers {
  90         u32 saveDSPARB;
  91         u32 saveSWF0[16];
  92         u32 saveSWF1[16];
  93         u32 saveSWF3[3];
  94         u16 saveGCDGMBUS;
  95 };
  96
  97 #define MAX_L3_SLICES 2
  98 struct intel_l3_parity {
  99         u32 *remap_info[MAX_L3_SLICES];
 100         struct work_struct error_work;
 101         int which_slice;
 102 };
 103
 104 struct i915_gem_mm {
 105         /*
 106          * Shortcut for the stolen region. This points to either
 107          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 108          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 109          * support stolen.
 110          */
 111         struct intel_memory_region *stolen_region;
 112         /** Memory allocator for GTT stolen memory */
 113         struct drm_mm stolen;
 114         /** Protects the usage of the GTT stolen memory allocator. This is
 115          * always the inner lock when overlapping with struct_mutex. */
 116         struct mutex stolen_lock;
 117
 118         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 119         spinlock_t obj_lock;
 120
 121         /**
 122          * List of objects which are purgeable.
 123          */
 124         struct list_head purge_list;
 125
 126         /**
 127          * List of objects which have allocated pages and are shrinkable.
 128          */
 129         struct list_head shrink_list;
 130
 131         /**
 132          * List of objects which are pending destruction.
 133          */
 134         struct llist_head free_list;
 135         struct work_struct free_work;
 136         /**
 137          * Count of objects pending destructions. Used to skip needlessly
 138          * waiting on an RCU barrier if no objects are waiting to be freed.
 139          */
 140         atomic_t free_count;
 141
 142         /**
 143          * tmpfs instance used for shmem backed objects
 144          */
 145         struct vfsmount *gemfs;
 146
 147         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 148
 149         struct notifier_block oom_notifier;
 150         struct notifier_block vmap_notifier;
 151         struct shrinker shrinker;
 152
 153 #ifdef CONFIG_MMU_NOTIFIER
 154         /**
 155          * notifier_lock for mmu notifiers, memory may not be allocated
 156          * while holding this lock.
 157          */
 158         rwlock_t notifier_lock;
 159 #endif
 160
 161         /* shrinker accounting, also useful for userland debugging */
 162         u64 shrink_memory;
 163         u32 shrink_count;
 164 };
 165
 166 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 167
 168 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 169                                          u64 context);
 170
 171 static inline unsigned long
 172 i915_fence_timeout(const struct drm_i915_private *i915)
 173 {
 174         return i915_fence_context_timeout(i915, U64_MAX);
 175 }
 176
 177 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 178
 179 struct i915_virtual_gpu {
 180         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 181         bool active;
 182         u32 caps;
 183         u32 *initial_mmio;
 184         u8 *initial_cfg_space;
 185         struct list_head entry;
 186 };
 187
 188 struct i915_selftest_stash {
 189         atomic_t counter;
 190         struct ida mock_region_instances;
 191 };
 192
 193 struct drm_i915_private {
 194         struct drm_device drm;
 195
 196         struct intel_display display;
 197
 198         /* FIXME: Device release actions should all be moved to drmm_ */
 199         bool do_release;
 200
 201         /* i915 device parameters */
 202         struct i915_params params;
 203
 204         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 205         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 206         struct intel_driver_caps caps;
 207
 208         /**
 209          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 210          * end of stolen which we can optionally use to create GEM objects
 211          * backed by stolen memory. Note that stolen_usable_size tells us
 212          * exactly how much of this we are actually allowed to use, given that
 213          * some portion of it is in fact reserved for use by hardware functions.
 214          */
 215         struct resource dsm;
 216         /**
 217          * Reseved portion of Data Stolen Memory
 218          */
 219         struct resource dsm_reserved;
 220
 221         /*
 222          * Stolen memory is segmented in hardware with different portions
 223          * offlimits to certain functions.
 224          *
 225          * The drm_mm is initialised to the total accessible range, as found
 226          * from the PCI config. On Broadwell+, this is further restricted to
 227          * avoid the first page! The upper end of stolen memory is reserved for
 228          * hardware functions and similarly removed from the accessible range.
 229          */
 230         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 231
 232         struct intel_uncore uncore;
 233         struct intel_uncore_mmio_debug mmio_debug;
 234
 235         struct i915_virtual_gpu vgpu;
 236
 237         struct intel_gvt *gvt;
 238
 239         struct intel_wopcm wopcm;
 240
 241         struct pci_dev *bridge_dev;
 242
 243         struct rb_root uabi_engines;
 244         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 245
 246         struct resource mch_res;
 247
 248         /* protects the irq masks */
 249         spinlock_t irq_lock;
 250
 251         bool display_irqs_enabled;
 252
 253         /* Sideband mailbox protection */
 254         struct mutex sb_lock;
 255         struct pm_qos_request sb_qos;
 256
 257         /** Cached value of IMR to avoid reads in updating the bitfield */
 258         union {
 259                 u32 irq_mask;
 260                 u32 de_irq_mask[I915_MAX_PIPES];
 261         };
 262         u32 pipestat_irq_mask[I915_MAX_PIPES];
 263
 264         bool preserve_bios_swizzle;
 265
 266         unsigned int fsb_freq, mem_freq, is_ddr3;
 267         unsigned int skl_preferred_vco_freq;
 268
 269         unsigned int max_dotclk_freq;
 270         unsigned int hpll_freq;
 271         unsigned int czclk_freq;
 272
 273         /**
 274          * wq - Driver workqueue for GEM.
 275          *
 276          * NOTE: Work items scheduled here are not allowed to grab any modeset
 277          * locks, for otherwise the flushing done in the pageflip code will
 278          * result in deadlocks.
 279          */
 280         struct workqueue_struct *wq;
 281
 282         /* pm private clock gating functions */
 283         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 284
 285         /* PCH chipset type */
 286         enum intel_pch pch_type;
 287         unsigned short pch_id;
 288
 289         unsigned long gem_quirks;
 290
 291         struct drm_atomic_state *modeset_restore_state;
 292         struct drm_modeset_acquire_ctx reset_ctx;
 293
 294         struct i915_gem_mm mm;
 295
 296         /* Kernel Modesetting */
 297
 298         struct list_head global_obj_list;
 299
 300         bool mchbar_need_disable;
 301
 302         struct intel_l3_parity l3_parity;
 303
 304         /*
 305          * HTI (aka HDPORT) state read during initial hw readout.  Most
 306          * platforms don't have HTI, so this will just stay 0.  Those that do
 307          * will use this later to figure out which PLLs and PHYs are unavailable
 308          * for driver usage.
 309          */
 310         u32 hti_state;
 311
 312         /*
 313          * edram size in MB.
 314          * Cannot be determined by PCIID. You must always read a register.
 315          */
 316         u32 edram_size_mb;
 317
 318         struct i915_gpu_error gpu_error;
 319
 320         /*
 321          * Shadows for CHV DPLL_MD regs to keep the state
 322          * checker somewhat working in the presence hardware
 323          * crappiness (can't read out DPLL_MD for pipes B & C).
 324          */
 325         u32 chv_dpll_md[I915_MAX_PIPES];
 326         u32 bxt_phy_grc;
 327
 328         u32 suspend_count;
 329         struct i915_suspend_saved_registers regfile;
 330         struct vlv_s0ix_state *vlv_s0ix_state;
 331
 332         struct dram_info {
 333                 bool wm_lv_0_adjust_needed;
 334                 u8 num_channels;
 335                 bool symmetric_memory;
 336                 enum intel_dram_type {
 337                         INTEL_DRAM_UNKNOWN,
 338                         INTEL_DRAM_DDR3,
 339                         INTEL_DRAM_DDR4,
 340                         INTEL_DRAM_LPDDR3,
 341                         INTEL_DRAM_LPDDR4,
 342                         INTEL_DRAM_DDR5,
 343                         INTEL_DRAM_LPDDR5,
 344                 } type;
 345                 u8 num_qgv_points;
 346                 u8 num_psf_gv_points;
 347         } dram_info;
 348
 349         struct intel_runtime_pm runtime_pm;
 350
 351         struct i915_perf perf;
 352
 353         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 354         struct intel_gt gt0;
 355
 356         /*
 357          * i915->gt[0] == &i915->gt0
 358          */
 359 #define I915_MAX_GT 4
 360         struct intel_gt *gt[I915_MAX_GT];
 361
 362         struct kobject *sysfs_gt;
 363
 364         /* Quick lookup of media GT (current platforms only have one) */
 365         struct intel_gt *media_gt;
 366
 367         struct {
 368                 struct i915_gem_contexts {
 369                         spinlock_t lock; /* locks list */
 370                         struct list_head list;
 371                 } contexts;
 372
 373                 /*
 374                  * We replace the local file with a global mappings as the
 375                  * backing storage for the mmap is on the device and not
 376                  * on the struct file, and we do not want to prolong the
 377                  * lifetime of the local fd. To minimise the number of
 378                  * anonymous inodes we create, we use a global singleton to
 379                  * share the global mapping.
 380                  */
 381                 struct file *mmap_singleton;
 382         } gem;
 383
 384         u8 pch_ssc_use;
 385
 386         /* For i915gm/i945gm vblank irq workaround */
 387         u8 vblank_enabled;
 388
 389         bool irq_enabled;
 390
 391         /*
 392          * DG2: Mask of PHYs that were not calibrated by the firmware
 393          * and should not be used.
 394          */
 395         u8 snps_phy_failed_calibration;
 396
 397         struct i915_pmu pmu;
 398
 399         struct i915_drm_clients clients;
 400
 401         /* The TTM device structure. */
 402         struct ttm_device bdev;
 403
 404         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 405
 406         /*
 407          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 408          * will be rejected. Instead look for a better place.
 409          */
 410 };
 411
 412 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 413 {
 414         return container_of(dev, struct drm_i915_private, drm);
 415 }
 416
 417 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 418 {
 419         return dev_get_drvdata(kdev);
 420 }
 421
 422 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 423 {
 424         return pci_get_drvdata(pdev);
 425 }
 426
 427 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 428 {
 429         return &i915->gt0;
 430 }
 431
 432 /* Simple iterator over all initialised engines */
 433 #define for_each_engine(engine__, dev_priv__, id__) \
 434         for ((id__) = 0; \
 435              (id__) < I915_NUM_ENGINES; \
 436              (id__)++) \
 437                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 438
 439 /* Iterator over subset of engines selected by mask */
 440 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 441         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 442              (tmp__) ? \
 443              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 444              0;)
 445
 446 #define rb_to_uabi_engine(rb) \
 447         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 448
 449 #define for_each_uabi_engine(engine__, i915__) \
 450         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 451              (engine__); \
 452              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 453
 454 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 455         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 456              (engine__) && (engine__)->uabi_class == (class__); \
 457              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 458
 459 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 460 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 461 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 462
 463 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 464
 465 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 466
 467 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 468 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 469                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 470 #define IS_GRAPHICS_VER(i915, from, until) \
 471         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 472
 473 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 474 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 475                                                RUNTIME_INFO(i915)->media.ip.rel)
 476 #define IS_MEDIA_VER(i915, from, until) \
 477         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 478
 479 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 480 #define IS_DISPLAY_VER(i915, from, until) \
 481         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 482
 483 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 484
 485 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 486
 487 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 488 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 489 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 490 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 491
 492 #define IS_DISPLAY_STEP(__i915, since, until) \
 493         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 494          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 495
 496 #define IS_GRAPHICS_STEP(__i915, since, until) \
 497         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 498          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 499
 500 #define IS_MEDIA_STEP(__i915, since, until) \
 501         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 502          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 503
 504 #define IS_BASEDIE_STEP(__i915, since, until) \
 505         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 506          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 507
 508 static __always_inline unsigned int
 509 __platform_mask_index(const struct intel_runtime_info *info,
 510                       enum intel_platform p)
 511 {
 512         const unsigned int pbits =
 513                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 514
 515         /* Expand the platform_mask array if this fails. */
 516         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 517                      pbits * ARRAY_SIZE(info->platform_mask));
 518
 519         return p / pbits;
 520 }
 521
 522 static __always_inline unsigned int
 523 __platform_mask_bit(const struct intel_runtime_info *info,
 524                     enum intel_platform p)
 525 {
 526         const unsigned int pbits =
 527                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 528
 529         return p % pbits + INTEL_SUBPLATFORM_BITS;
 530 }
 531
 532 static inline u32
 533 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 534 {
 535         const unsigned int pi = __platform_mask_index(info, p);
 536
 537         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 538 }
 539
 540 static __always_inline bool
 541 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 542 {
 543         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 544         const unsigned int pi = __platform_mask_index(info, p);
 545         const unsigned int pb = __platform_mask_bit(info, p);
 546
 547         BUILD_BUG_ON(!__builtin_constant_p(p));
 548
 549         return info->platform_mask[pi] & BIT(pb);
 550 }
 551
 552 static __always_inline bool
 553 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 554                enum intel_platform p, unsigned int s)
 555 {
 556         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 557         const unsigned int pi = __platform_mask_index(info, p);
 558         const unsigned int pb = __platform_mask_bit(info, p);
 559         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 560         const u32 mask = info->platform_mask[pi];
 561
 562         BUILD_BUG_ON(!__builtin_constant_p(p));
 563         BUILD_BUG_ON(!__builtin_constant_p(s));
 564         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 565
 566         /* Shift and test on the MSB position so sign flag can be used. */
 567         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 568 }
 569
 570 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 571 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 572
 573 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 574 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 575 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 576 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 577 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 578 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 579 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 580 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 581 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 582 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 583 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 584 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 585 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 586 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 587 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 588 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 589 #define IS_IRONLAKE_M(dev_priv) \
 590         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 591 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 592 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 593 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 594                                  INTEL_INFO(dev_priv)->gt == 1)
 595 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 596 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 597 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 598 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 599 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 600 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 601 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 602 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 603 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 604 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 605 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 606 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 607                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 608 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 609 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 610 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 611 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 612 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 613 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 614 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 615 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 616 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 617
 618 #define IS_METEORLAKE_M(dev_priv) \
 619         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 620 #define IS_METEORLAKE_P(dev_priv) \
 621         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 622 #define IS_DG2_G10(dev_priv) \
 623         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 624 #define IS_DG2_G11(dev_priv) \
 625         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 626 #define IS_DG2_G12(dev_priv) \
 627         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 628 #define IS_ADLS_RPLS(dev_priv) \
 629         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 630 #define IS_ADLP_N(dev_priv) \
 631         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 632 #define IS_ADLP_RPLP(dev_priv) \
 633         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 634 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 635                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 636 #define IS_BDW_ULT(dev_priv) \
 637         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 638 #define IS_BDW_ULX(dev_priv) \
 639         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 640 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 641                                  INTEL_INFO(dev_priv)->gt == 3)
 642 #define IS_HSW_ULT(dev_priv) \
 643         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 644 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 645                                  INTEL_INFO(dev_priv)->gt == 3)
 646 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 647                                  INTEL_INFO(dev_priv)->gt == 1)
 648 /* ULX machines are also considered ULT. */
 649 #define IS_HSW_ULX(dev_priv) \
 650         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 651 #define IS_SKL_ULT(dev_priv) \
 652         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 653 #define IS_SKL_ULX(dev_priv) \
 654         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 655 #define IS_KBL_ULT(dev_priv) \
 656         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 657 #define IS_KBL_ULX(dev_priv) \
 658         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 659 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 660                                  INTEL_INFO(dev_priv)->gt == 2)
 661 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 662                                  INTEL_INFO(dev_priv)->gt == 3)
 663 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 664                                  INTEL_INFO(dev_priv)->gt == 4)
 665 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 666                                  INTEL_INFO(dev_priv)->gt == 2)
 667 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 668                                  INTEL_INFO(dev_priv)->gt == 3)
 669 #define IS_CFL_ULT(dev_priv) \
 670         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 671 #define IS_CFL_ULX(dev_priv) \
 672         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 673 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 674                                  INTEL_INFO(dev_priv)->gt == 2)
 675 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 676                                  INTEL_INFO(dev_priv)->gt == 3)
 677
 678 #define IS_CML_ULT(dev_priv) \
 679         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 680 #define IS_CML_ULX(dev_priv) \
 681         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 682 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 683                                  INTEL_INFO(dev_priv)->gt == 2)
 684
 685 #define IS_ICL_WITH_PORT_F(dev_priv) \
 686         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 687
 688 #define IS_TGL_UY(dev_priv) \
 689         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 690
 691 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 692
 693 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 694         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 695 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 696         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 697
 698 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 699         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 700 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 701         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 702
 703 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 704         (IS_TIGERLAKE(__i915) && \
 705          IS_DISPLAY_STEP(__i915, since, until))
 706
 707 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 708         (IS_TGL_UY(__i915) && \
 709          IS_GRAPHICS_STEP(__i915, since, until))
 710
 711 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 712         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 713          IS_GRAPHICS_STEP(__i915, since, until))
 714
 715 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 716         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 717
 718 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 719         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 720 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 721         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 722
 723 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 724         (IS_ALDERLAKE_S(__i915) && \
 725          IS_DISPLAY_STEP(__i915, since, until))
 726
 727 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 728         (IS_ALDERLAKE_S(__i915) && \
 729          IS_GRAPHICS_STEP(__i915, since, until))
 730
 731 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 732         (IS_ALDERLAKE_P(__i915) && \
 733          IS_DISPLAY_STEP(__i915, since, until))
 734
 735 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 736         (IS_ALDERLAKE_P(__i915) && \
 737          IS_GRAPHICS_STEP(__i915, since, until))
 738
 739 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 740         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 741
 742 /*
 743  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 744  * create three variants (G10, G11, and G12) which each have distinct
 745  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 746  * stepping back to "A0" for their first iterations, even though they're more
 747  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 748  * functionality and workarounds.  However the display stepping does not reset
 749  * in the same manner --- a specific stepping like "B0" has a consistent
 750  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 751  *
 752  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 753  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 754  * and stepping-specific logic will be applied with a general DG2-wide stepping
 755  * number.
 756  */
 757 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 758         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 759          IS_GRAPHICS_STEP(__i915, since, until))
 760
 761 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 762         (IS_DG2(__i915) && \
 763          IS_DISPLAY_STEP(__i915, since, until))
 764
 765 #define IS_PVC_BD_STEP(__i915, since, until) \
 766         (IS_PONTEVECCHIO(__i915) && \
 767          IS_BASEDIE_STEP(__i915, since, until))
 768
 769 #define IS_PVC_CT_STEP(__i915, since, until) \
 770         (IS_PONTEVECCHIO(__i915) && \
 771          IS_GRAPHICS_STEP(__i915, since, until))
 772
 773 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 774 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 775 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 776
 777 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 778 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 779
 780 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
 781         unsigned int first__ = (first);                                 \
 782         unsigned int count__ = (count);                                 \
 783         ((gt)->info.engine_mask &                                               \
 784          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
 785 })
 786 #define RCS_MASK(gt) \
 787         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 788 #define BCS_MASK(gt) \
 789         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 790 #define VDBOX_MASK(gt) \
 791         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 792 #define VEBOX_MASK(gt) \
 793         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 794 #define CCS_MASK(gt) \
 795         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 796
 797 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 798
 799 /*
 800  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 801  * All later gens can run the final buffer from the ppgtt
 802  */
 803 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 804
 805 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 806 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 807 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 808 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 809 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 810 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 811
 812 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 813
 814 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 815                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 816 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 817                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 818
 819 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 820
 821 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 822 #define HAS_PPGTT(dev_priv) \
 823         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 824 #define HAS_FULL_PPGTT(dev_priv) \
 825         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 826
 827 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 828         GEM_BUG_ON((sizes) == 0); \
 829         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 830 })
 831
 832 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 833 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 834                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 835
 836 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 837 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 838
 839 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 840         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 841
 842 /* WaRsDisableCoarsePowerGating:skl,cnl */
 843 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 844         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 845
 846 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 847 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 848                                         IS_GEMINILAKE(dev_priv) || \
 849                                         IS_KABYLAKE(dev_priv))
 850
 851 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 852  * rows, which changed the alignment requirements and fence programming.
 853  */
 854 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 855                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 856 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 857 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 858
 859 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 860 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 861 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 862
 863 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 864
 865 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 866 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 867
 868 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 869
 870 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 871 #define HAS_CDCLK_SQUASH(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 872 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 873 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 874 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 875 #define HAS_PSR_HW_TRACKING(dev_priv) \
 876         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 877 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 878 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 879
 880 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 881 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 882 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 883
 884 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 885
 886 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 887
 888 #define HAS_HECI_PXP(dev_priv) \
 889         (INTEL_INFO(dev_priv)->has_heci_pxp)
 890
 891 #define HAS_HECI_GSCFI(dev_priv) \
 892         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 893
 894 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 895
 896 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 897
 898 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 899 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 900
 901 /*
 902  * Set this flag, when platform requires 64K GTT page sizes or larger for
 903  * device local memory access.
 904  */
 905 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 906
 907 /*
 908  * Set this flag when platform doesn't allow both 64k pages and 4k pages in
 909  * the same PT. this flag means we need to support compact PT layout for the
 910  * ppGTT when using the 64K GTT pages.
 911  */
 912 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
 913
 914 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 915
 916 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 917 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 918
 919 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 920
 921 /*
 922  * Platform has the dedicated compression control state for each lmem surfaces
 923  * stored in lmem to support the 3D and media compression formats.
 924  */
 925 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 926
 927 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 928
 929 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 930
 931 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 932
 933 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
 934                             INTEL_INFO(dev_priv)->has_pxp) && \
 935                             VDBOX_MASK(to_gt(dev_priv)))
 936
 937 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 938
 939 #define HAS_GMD_ID(i915)        (INTEL_INFO(i915)->has_gmd_id)
 940
 941 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 942
 943 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 944
 945 /* DPF == dynamic parity feature */
 946 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 947 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 948                                  2 : HAS_L3_DPF(dev_priv))
 949
 950 #define GT_FREQUENCY_MULTIPLIER 50
 951 #define GEN9_FREQ_SCALER 3
 952
 953 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 954
 955 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 956
 957 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 958
 959 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 960
 961 /* Only valid when HAS_DISPLAY() is true */
 962 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 963         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 964          !(dev_priv)->params.disable_display &&                         \
 965          !intel_opregion_headless_sku(dev_priv))
 966
 967 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 968         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 969
 970 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 971                                               IS_ALDERLAKE_S(dev_priv))
 972
 973 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 974
 975 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 976
 977 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 978
 979 /* intel_device_info.c */
 980 static inline struct intel_device_info *
 981 mkwrite_device_info(struct drm_i915_private *dev_priv)
 982 {
 983         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 984 }
 985
 986 static inline enum i915_map_type
 987 i915_coherent_map_type(struct drm_i915_private *i915,
 988                        struct drm_i915_gem_object *obj, bool always_coherent)
 989 {
 990         if (i915_gem_object_is_lmem(obj))
 991                 return I915_MAP_WC;
 992         if (HAS_LLC(i915) || always_coherent)
 993                 return I915_MAP_WB;
 994         else
 995                 return I915_MAP_WC;
 996 }
 997
 998 #endif