drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/string_helpers.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42
  43 #include <drm/drm_aperture.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_bw.h"
  51 #include "display/intel_cdclk.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64 #include "display/skl_watermark.h"
  65
  66 #include "gem/i915_gem_context.h"
  67 #include "gem/i915_gem_create.h"
  68 #include "gem/i915_gem_dmabuf.h"
  69 #include "gem/i915_gem_ioctls.h"
  70 #include "gem/i915_gem_mman.h"
  71 #include "gem/i915_gem_pm.h"
  72 #include "gt/intel_gt.h"
  73 #include "gt/intel_gt_pm.h"
  74 #include "gt/intel_rc6.h"
  75
  76 #include "pxp/intel_pxp_pm.h"
  77
  78 #include "i915_file_private.h"
  79 #include "i915_debugfs.h"
  80 #include "i915_driver.h"
  81 #include "i915_drm_client.h"
  82 #include "i915_drv.h"
  83 #include "i915_getparam.h"
  84 #include "i915_ioc32.h"
  85 #include "i915_ioctl.h"
  86 #include "i915_irq.h"
  87 #include "i915_memcpy.h"
  88 #include "i915_perf.h"
  89 #include "i915_query.h"
  90 #include "i915_suspend.h"
  91 #include "i915_switcheroo.h"
  92 #include "i915_sysfs.h"
  93 #include "i915_utils.h"
  94 #include "i915_vgpu.h"
  95 #include "intel_dram.h"
  96 #include "intel_gvt.h"
  97 #include "intel_memory_region.h"
  98 #include "intel_pci_config.h"
  99 #include "intel_pcode.h"
 100 #include "intel_pm.h"
 101 #include "intel_region_ttm.h"
 102 #include "vlv_suspend.h"
 103
 104 /* Intel Rapid Start Technology ACPI device name */
 105 static const char irst_name[] = "INT3392";
 106
 107 static const struct drm_driver i915_drm_driver;
 108
 109 static void i915_release_bridge_dev(struct drm_device *dev,
 110                                     void *bridge)
 111 {
 112         pci_dev_put(bridge);
 113 }
 114
 115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 116 {
 117         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 118
 119         dev_priv->bridge_dev =
 120                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 121         if (!dev_priv->bridge_dev) {
 122                 drm_err(&dev_priv->drm, "bridge device not found\n");
 123                 return -EIO;
 124         }
 125
 126         return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
 127                                         dev_priv->bridge_dev);
 128 }
 129
 130 /* Allocate space for the MCH regs if needed, return nonzero on error */
 131 static int
 132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 133 {
 134         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 135         u32 temp_lo, temp_hi = 0;
 136         u64 mchbar_addr;
 137         int ret;
 138
 139         if (GRAPHICS_VER(dev_priv) >= 4)
 140                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 141         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 142         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 143
 144         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 145 #ifdef CONFIG_PNP
 146         if (mchbar_addr &&
 147             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 148                 return 0;
 149 #endif
 150
 151         /* Get some space for it */
 152         dev_priv->mch_res.name = "i915 MCHBAR";
 153         dev_priv->mch_res.flags = IORESOURCE_MEM;
 154         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 155                                      &dev_priv->mch_res,
 156                                      MCHBAR_SIZE, MCHBAR_SIZE,
 157                                      PCIBIOS_MIN_MEM,
 158                                      0, pcibios_align_resource,
 159                                      dev_priv->bridge_dev);
 160         if (ret) {
 161                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 162                 dev_priv->mch_res.start = 0;
 163                 return ret;
 164         }
 165
 166         if (GRAPHICS_VER(dev_priv) >= 4)
 167                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 168                                        upper_32_bits(dev_priv->mch_res.start));
 169
 170         pci_write_config_dword(dev_priv->bridge_dev, reg,
 171                                lower_32_bits(dev_priv->mch_res.start));
 172         return 0;
 173 }
 174
 175 /* Setup MCHBAR if possible, return true if we should disable it again */
 176 static void
 177 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 178 {
 179         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 180         u32 temp;
 181         bool enabled;
 182
 183         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 184                 return;
 185
 186         dev_priv->mchbar_need_disable = false;
 187
 188         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 189                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 190                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 191         } else {
 192                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 193                 enabled = temp & 1;
 194         }
 195
 196         /* If it's already enabled, don't have to do anything */
 197         if (enabled)
 198                 return;
 199
 200         if (intel_alloc_mchbar_resource(dev_priv))
 201                 return;
 202
 203         dev_priv->mchbar_need_disable = true;
 204
 205         /* Space is allocated or reserved, so enable it. */
 206         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 207                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 208                                        temp | DEVEN_MCHBAR_EN);
 209         } else {
 210                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 211                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 212         }
 213 }
 214
 215 static void
 216 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 217 {
 218         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 219
 220         if (dev_priv->mchbar_need_disable) {
 221                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 222                         u32 deven_val;
 223
 224                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 225                                               &deven_val);
 226                         deven_val &= ~DEVEN_MCHBAR_EN;
 227                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 228                                                deven_val);
 229                 } else {
 230                         u32 mchbar_val;
 231
 232                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 233                                               &mchbar_val);
 234                         mchbar_val &= ~1;
 235                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 236                                                mchbar_val);
 237                 }
 238         }
 239
 240         if (dev_priv->mch_res.start)
 241                 release_resource(&dev_priv->mch_res);
 242 }
 243
 244 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 245 {
 246         /*
 247          * The i915 workqueue is primarily used for batched retirement of
 248          * requests (and thus managing bo) once the task has been completed
 249          * by the GPU. i915_retire_requests() is called directly when we
 250          * need high-priority retirement, such as waiting for an explicit
 251          * bo.
 252          *
 253          * It is also used for periodic low-priority events, such as
 254          * idle-timers and recording error state.
 255          *
 256          * All tasks on the workqueue are expected to acquire the dev mutex
 257          * so there is no point in running more than one instance of the
 258          * workqueue at any time.  Use an ordered one.
 259          */
 260         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 261         if (dev_priv->wq == NULL)
 262                 goto out_err;
 263
 264         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 265         if (dev_priv->display.hotplug.dp_wq == NULL)
 266                 goto out_free_wq;
 267
 268         return 0;
 269
 270 out_free_wq:
 271         destroy_workqueue(dev_priv->wq);
 272 out_err:
 273         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 274
 275         return -ENOMEM;
 276 }
 277
 278 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 279 {
 280         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 281         destroy_workqueue(dev_priv->wq);
 282 }
 283
 284 /*
 285  * We don't keep the workarounds for pre-production hardware, so we expect our
 286  * driver to fail on these machines in one way or another. A little warning on
 287  * dmesg may help both the user and the bug triagers.
 288  *
 289  * Our policy for removing pre-production workarounds is to keep the
 290  * current gen workarounds as a guide to the bring-up of the next gen
 291  * (workarounds have a habit of persisting!). Anything older than that
 292  * should be removed along with the complications they introduce.
 293  */
 294 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 295 {
 296         bool pre = false;
 297
 298         pre |= IS_HSW_EARLY_SDV(dev_priv);
 299         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 300         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 301         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 302         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 303         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 304
 305         if (pre) {
 306                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 307                           "It may not be fully functional.\n");
 308                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 309         }
 310 }
 311
 312 static void sanitize_gpu(struct drm_i915_private *i915)
 313 {
 314         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 315                 struct intel_gt *gt;
 316                 unsigned int i;
 317
 318                 for_each_gt(gt, i915, i)
 319                         __intel_gt_reset(gt, ALL_ENGINES);
 320         }
 321 }
 322
 323 /**
 324  * i915_driver_early_probe - setup state not requiring device access
 325  * @dev_priv: device private
 326  *
 327  * Initialize everything that is a "SW-only" state, that is state not
 328  * requiring accessing the device or exposing the driver via kernel internal
 329  * or userspace interfaces. Example steps belonging here: lock initialization,
 330  * system memory allocation, setting up device specific attributes and
 331  * function hooks not requiring accessing the device.
 332  */
 333 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 334 {
 335         int ret = 0;
 336
 337         if (i915_inject_probe_failure(dev_priv))
 338                 return -ENODEV;
 339
 340         intel_device_info_runtime_init_early(dev_priv);
 341
 342         intel_step_init(dev_priv);
 343
 344         intel_uncore_mmio_debug_init_early(dev_priv);
 345
 346         spin_lock_init(&dev_priv->irq_lock);
 347         spin_lock_init(&dev_priv->gpu_error.lock);
 348         mutex_init(&dev_priv->display.backlight.lock);
 349
 350         mutex_init(&dev_priv->sb_lock);
 351         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 352
 353         mutex_init(&dev_priv->display.audio.mutex);
 354         mutex_init(&dev_priv->display.wm.wm_mutex);
 355         mutex_init(&dev_priv->display.pps.mutex);
 356         mutex_init(&dev_priv->display.hdcp.comp_mutex);
 357         spin_lock_init(&dev_priv->display.dkl.phy_lock);
 358
 359         i915_memcpy_init_early(dev_priv);
 360         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 361
 362         ret = i915_workqueues_init(dev_priv);
 363         if (ret < 0)
 364                 return ret;
 365
 366         ret = vlv_suspend_init(dev_priv);
 367         if (ret < 0)
 368                 goto err_workqueues;
 369
 370         ret = intel_region_ttm_device_init(dev_priv);
 371         if (ret)
 372                 goto err_ttm;
 373
 374         intel_wopcm_init_early(&dev_priv->wopcm);
 375
 376         ret = intel_root_gt_init_early(dev_priv);
 377         if (ret < 0)
 378                 goto err_rootgt;
 379
 380         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 381
 382         i915_gem_init_early(dev_priv);
 383
 384         /* This must be called before any calls to HAS_PCH_* */
 385         intel_detect_pch(dev_priv);
 386
 387         intel_pm_setup(dev_priv);
 388         ret = intel_power_domains_init(dev_priv);
 389         if (ret < 0)
 390                 goto err_gem;
 391         intel_irq_init(dev_priv);
 392         intel_init_display_hooks(dev_priv);
 393         intel_init_clock_gating_hooks(dev_priv);
 394
 395         intel_detect_preproduction_hw(dev_priv);
 396
 397         return 0;
 398
 399 err_gem:
 400         i915_gem_cleanup_early(dev_priv);
 401         intel_gt_driver_late_release_all(dev_priv);
 402         i915_drm_clients_fini(&dev_priv->clients);
 403 err_rootgt:
 404         intel_region_ttm_device_fini(dev_priv);
 405 err_ttm:
 406         vlv_suspend_cleanup(dev_priv);
 407 err_workqueues:
 408         i915_workqueues_cleanup(dev_priv);
 409         return ret;
 410 }
 411
 412 /**
 413  * i915_driver_late_release - cleanup the setup done in
 414  *                             i915_driver_early_probe()
 415  * @dev_priv: device private
 416  */
 417 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 418 {
 419         intel_irq_fini(dev_priv);
 420         intel_power_domains_cleanup(dev_priv);
 421         i915_gem_cleanup_early(dev_priv);
 422         intel_gt_driver_late_release_all(dev_priv);
 423         i915_drm_clients_fini(&dev_priv->clients);
 424         intel_region_ttm_device_fini(dev_priv);
 425         vlv_suspend_cleanup(dev_priv);
 426         i915_workqueues_cleanup(dev_priv);
 427
 428         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 429         mutex_destroy(&dev_priv->sb_lock);
 430
 431         i915_params_free(&dev_priv->params);
 432 }
 433
 434 /**
 435  * i915_driver_mmio_probe - setup device MMIO
 436  * @dev_priv: device private
 437  *
 438  * Setup minimal device state necessary for MMIO accesses later in the
 439  * initialization sequence. The setup here should avoid any other device-wide
 440  * side effects or exposing the driver via kernel internal or user space
 441  * interfaces.
 442  */
 443 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 444 {
 445         struct intel_gt *gt;
 446         int ret, i;
 447
 448         if (i915_inject_probe_failure(dev_priv))
 449                 return -ENODEV;
 450
 451         ret = i915_get_bridge_dev(dev_priv);
 452         if (ret < 0)
 453                 return ret;
 454
 455         for_each_gt(gt, dev_priv, i) {
 456                 ret = intel_uncore_init_mmio(gt->uncore);
 457                 if (ret)
 458                         return ret;
 459
 460                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 461                                                intel_uncore_fini_mmio,
 462                                                gt->uncore);
 463                 if (ret)
 464                         return ret;
 465         }
 466
 467         /* Try to make sure MCHBAR is enabled before poking at it */
 468         intel_setup_mchbar(dev_priv);
 469         intel_device_info_runtime_init(dev_priv);
 470
 471         for_each_gt(gt, dev_priv, i) {
 472                 ret = intel_gt_init_mmio(gt);
 473                 if (ret)
 474                         goto err_uncore;
 475         }
 476
 477         /* As early as possible, scrub existing GPU state before clobbering */
 478         sanitize_gpu(dev_priv);
 479
 480         return 0;
 481
 482 err_uncore:
 483         intel_teardown_mchbar(dev_priv);
 484
 485         return ret;
 486 }
 487
 488 /**
 489  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 490  * @dev_priv: device private
 491  */
 492 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 493 {
 494         intel_teardown_mchbar(dev_priv);
 495 }
 496
 497 /**
 498  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 499  * platform
 500  * @i915: valid i915 instance
 501  *
 502  * Set the dma max segment size, device and coherent masks.  The dma mask set
 503  * needs to occur before i915_ggtt_probe_hw.
 504  *
 505  * A couple of platforms have special needs.  Address them as well.
 506  *
 507  */
 508 static int i915_set_dma_info(struct drm_i915_private *i915)
 509 {
 510         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 511         int ret;
 512
 513         GEM_BUG_ON(!mask_size);
 514
 515         /*
 516          * We don't have a max segment size, so set it to the max so sg's
 517          * debugging layer doesn't complain
 518          */
 519         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 520
 521         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 522         if (ret)
 523                 goto mask_err;
 524
 525         /* overlay on gen2 is broken and can't address above 1G */
 526         if (GRAPHICS_VER(i915) == 2)
 527                 mask_size = 30;
 528
 529         /*
 530          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 531          * using 32bit addressing, overwriting memory if HWS is located
 532          * above 4GB.
 533          *
 534          * The documentation also mentions an issue with undefined
 535          * behaviour if any general state is accessed within a page above 4GB,
 536          * which also needs to be handled carefully.
 537          */
 538         if (IS_I965G(i915) || IS_I965GM(i915))
 539                 mask_size = 32;
 540
 541         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 542         if (ret)
 543                 goto mask_err;
 544
 545         return 0;
 546
 547 mask_err:
 548         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 549         return ret;
 550 }
 551
 552 static int i915_pcode_init(struct drm_i915_private *i915)
 553 {
 554         struct intel_gt *gt;
 555         int id, ret;
 556
 557         for_each_gt(gt, i915, id) {
 558                 ret = intel_pcode_init(gt->uncore);
 559                 if (ret) {
 560                         drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
 561                         return ret;
 562                 }
 563         }
 564
 565         return 0;
 566 }
 567
 568 /**
 569  * i915_driver_hw_probe - setup state requiring device access
 570  * @dev_priv: device private
 571  *
 572  * Setup state that requires accessing the device, but doesn't require
 573  * exposing the driver via kernel internal or userspace interfaces.
 574  */
 575 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 576 {
 577         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 578         struct pci_dev *root_pdev;
 579         int ret;
 580
 581         if (i915_inject_probe_failure(dev_priv))
 582                 return -ENODEV;
 583
 584         if (HAS_PPGTT(dev_priv)) {
 585                 if (intel_vgpu_active(dev_priv) &&
 586                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 587                         i915_report_error(dev_priv,
 588                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 589                         return -ENXIO;
 590                 }
 591         }
 592
 593         if (HAS_EXECLISTS(dev_priv)) {
 594                 /*
 595                  * Older GVT emulation depends upon intercepting CSB mmio,
 596                  * which we no longer use, preferring to use the HWSP cache
 597                  * instead.
 598                  */
 599                 if (intel_vgpu_active(dev_priv) &&
 600                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 601                         i915_report_error(dev_priv,
 602                                           "old vGPU host found, support for HWSP emulation required\n");
 603                         return -ENXIO;
 604                 }
 605         }
 606
 607         /* needs to be done before ggtt probe */
 608         intel_dram_edram_detect(dev_priv);
 609
 610         ret = i915_set_dma_info(dev_priv);
 611         if (ret)
 612                 return ret;
 613
 614         i915_perf_init(dev_priv);
 615
 616         ret = intel_gt_assign_ggtt(to_gt(dev_priv));
 617         if (ret)
 618                 goto err_perf;
 619
 620         ret = i915_ggtt_probe_hw(dev_priv);
 621         if (ret)
 622                 goto err_perf;
 623
 624         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 625         if (ret)
 626                 goto err_ggtt;
 627
 628         ret = i915_ggtt_init_hw(dev_priv);
 629         if (ret)
 630                 goto err_ggtt;
 631
 632         ret = intel_memory_regions_hw_probe(dev_priv);
 633         if (ret)
 634                 goto err_ggtt;
 635
 636         ret = intel_gt_tiles_init(dev_priv);
 637         if (ret)
 638                 goto err_mem_regions;
 639
 640         ret = i915_ggtt_enable_hw(dev_priv);
 641         if (ret) {
 642                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 643                 goto err_mem_regions;
 644         }
 645
 646         pci_set_master(pdev);
 647
 648         /* On the 945G/GM, the chipset reports the MSI capability on the
 649          * integrated graphics even though the support isn't actually there
 650          * according to the published specs.  It doesn't appear to function
 651          * correctly in testing on 945G.
 652          * This may be a side effect of MSI having been made available for PEG
 653          * and the registers being closely associated.
 654          *
 655          * According to chipset errata, on the 965GM, MSI interrupts may
 656          * be lost or delayed, and was defeatured. MSI interrupts seem to
 657          * get lost on g4x as well, and interrupt delivery seems to stay
 658          * properly dead afterwards. So we'll just disable them for all
 659          * pre-gen5 chipsets.
 660          *
 661          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 662          * interrupts even when in MSI mode. This results in spurious
 663          * interrupt warnings if the legacy irq no. is shared with another
 664          * device. The kernel then disables that interrupt source and so
 665          * prevents the other device from working properly.
 666          */
 667         if (GRAPHICS_VER(dev_priv) >= 5) {
 668                 if (pci_enable_msi(pdev) < 0)
 669                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 670         }
 671
 672         ret = intel_gvt_init(dev_priv);
 673         if (ret)
 674                 goto err_msi;
 675
 676         intel_opregion_setup(dev_priv);
 677
 678         ret = i915_pcode_init(dev_priv);
 679         if (ret)
 680                 goto err_msi;
 681
 682         /*
 683          * Fill the dram structure to get the system dram info. This will be
 684          * used for memory latency calculation.
 685          */
 686         intel_dram_detect(dev_priv);
 687
 688         intel_bw_init_hw(dev_priv);
 689
 690         /*
 691          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
 692          * This should be totally removed when we handle the pci states properly
 693          * on runtime PM and on s2idle cases.
 694          */
 695         root_pdev = pcie_find_root_port(pdev);
 696         if (root_pdev)
 697                 pci_d3cold_disable(root_pdev);
 698
 699         return 0;
 700
 701 err_msi:
 702         if (pdev->msi_enabled)
 703                 pci_disable_msi(pdev);
 704 err_mem_regions:
 705         intel_memory_regions_driver_release(dev_priv);
 706 err_ggtt:
 707         i915_ggtt_driver_release(dev_priv);
 708         i915_gem_drain_freed_objects(dev_priv);
 709         i915_ggtt_driver_late_release(dev_priv);
 710 err_perf:
 711         i915_perf_fini(dev_priv);
 712         return ret;
 713 }
 714
 715 /**
 716  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 717  * @dev_priv: device private
 718  */
 719 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 720 {
 721         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 722         struct pci_dev *root_pdev;
 723
 724         i915_perf_fini(dev_priv);
 725
 726         if (pdev->msi_enabled)
 727                 pci_disable_msi(pdev);
 728
 729         root_pdev = pcie_find_root_port(pdev);
 730         if (root_pdev)
 731                 pci_d3cold_enable(root_pdev);
 732 }
 733
 734 /**
 735  * i915_driver_register - register the driver with the rest of the system
 736  * @dev_priv: device private
 737  *
 738  * Perform any steps necessary to make the driver available via kernel
 739  * internal or userspace interfaces.
 740  */
 741 static void i915_driver_register(struct drm_i915_private *dev_priv)
 742 {
 743         struct intel_gt *gt;
 744         unsigned int i;
 745
 746         i915_gem_driver_register(dev_priv);
 747         i915_pmu_register(dev_priv);
 748
 749         intel_vgpu_register(dev_priv);
 750
 751         /* Reveal our presence to userspace */
 752         if (drm_dev_register(&dev_priv->drm, 0)) {
 753                 drm_err(&dev_priv->drm,
 754                         "Failed to register driver for userspace access!\n");
 755                 return;
 756         }
 757
 758         i915_debugfs_register(dev_priv);
 759         i915_setup_sysfs(dev_priv);
 760
 761         /* Depends on sysfs having been initialized */
 762         i915_perf_register(dev_priv);
 763
 764         for_each_gt(gt, dev_priv, i)
 765                 intel_gt_driver_register(gt);
 766
 767         intel_display_driver_register(dev_priv);
 768
 769         intel_power_domains_enable(dev_priv);
 770         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 771
 772         intel_register_dsm_handler();
 773
 774         if (i915_switcheroo_register(dev_priv))
 775                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 776 }
 777
 778 /**
 779  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 780  * @dev_priv: device private
 781  */
 782 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 783 {
 784         struct intel_gt *gt;
 785         unsigned int i;
 786
 787         i915_switcheroo_unregister(dev_priv);
 788
 789         intel_unregister_dsm_handler();
 790
 791         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 792         intel_power_domains_disable(dev_priv);
 793
 794         intel_display_driver_unregister(dev_priv);
 795
 796         for_each_gt(gt, dev_priv, i)
 797                 intel_gt_driver_unregister(gt);
 798
 799         i915_perf_unregister(dev_priv);
 800         i915_pmu_unregister(dev_priv);
 801
 802         i915_teardown_sysfs(dev_priv);
 803         drm_dev_unplug(&dev_priv->drm);
 804
 805         i915_gem_driver_unregister(dev_priv);
 806 }
 807
 808 void
 809 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 810 {
 811         drm_printf(p, "iommu: %s\n",
 812                    str_enabled_disabled(i915_vtd_active(i915)));
 813 }
 814
 815 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 816 {
 817         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 818                 struct drm_printer p = drm_debug_printer("i915 device info:");
 819                 struct intel_gt *gt;
 820                 unsigned int i;
 821
 822                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 823                            INTEL_DEVID(dev_priv),
 824                            INTEL_REVID(dev_priv),
 825                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 826                            intel_subplatform(RUNTIME_INFO(dev_priv),
 827                                              INTEL_INFO(dev_priv)->platform),
 828                            GRAPHICS_VER(dev_priv));
 829
 830                 intel_device_info_print(INTEL_INFO(dev_priv),
 831                                         RUNTIME_INFO(dev_priv), &p);
 832                 i915_print_iommu_status(dev_priv, &p);
 833                 for_each_gt(gt, dev_priv, i)
 834                         intel_gt_info_print(&gt->info, &p);
 835         }
 836
 837         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 838                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 839         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 840                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 841         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 842                 drm_info(&dev_priv->drm,
 843                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 844 }
 845
 846 static struct drm_i915_private *
 847 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 848 {
 849         const struct intel_device_info *match_info =
 850                 (struct intel_device_info *)ent->driver_data;
 851         struct intel_device_info *device_info;
 852         struct intel_runtime_info *runtime;
 853         struct drm_i915_private *i915;
 854
 855         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 856                                   struct drm_i915_private, drm);
 857         if (IS_ERR(i915))
 858                 return i915;
 859
 860         pci_set_drvdata(pdev, i915);
 861
 862         /* Device parameters start as a copy of module parameters. */
 863         i915_params_copy(&i915->params, &i915_modparams);
 864
 865         /* Setup the write-once "constant" device info */
 866         device_info = mkwrite_device_info(i915);
 867         memcpy(device_info, match_info, sizeof(*device_info));
 868
 869         /* Initialize initial runtime info from static const data and pdev. */
 870         runtime = RUNTIME_INFO(i915);
 871         memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
 872         runtime->device_id = pdev->device;
 873
 874         return i915;
 875 }
 876
 877 /**
 878  * i915_driver_probe - setup chip and create an initial config
 879  * @pdev: PCI device
 880  * @ent: matching PCI ID entry
 881  *
 882  * The driver probe routine has to do several things:
 883  *   - drive output discovery via intel_modeset_init()
 884  *   - initialize the memory manager
 885  *   - allocate initial config memory
 886  *   - setup the DRM framebuffer with the allocated memory
 887  */
 888 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 889 {
 890         struct drm_i915_private *i915;
 891         int ret;
 892
 893         i915 = i915_driver_create(pdev, ent);
 894         if (IS_ERR(i915))
 895                 return PTR_ERR(i915);
 896
 897         ret = pci_enable_device(pdev);
 898         if (ret)
 899                 goto out_fini;
 900
 901         ret = i915_driver_early_probe(i915);
 902         if (ret < 0)
 903                 goto out_pci_disable;
 904
 905         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 906
 907         intel_vgpu_detect(i915);
 908
 909         ret = intel_gt_probe_all(i915);
 910         if (ret < 0)
 911                 goto out_runtime_pm_put;
 912
 913         ret = i915_driver_mmio_probe(i915);
 914         if (ret < 0)
 915                 goto out_tiles_cleanup;
 916
 917         ret = i915_driver_hw_probe(i915);
 918         if (ret < 0)
 919                 goto out_cleanup_mmio;
 920
 921         ret = intel_modeset_init_noirq(i915);
 922         if (ret < 0)
 923                 goto out_cleanup_hw;
 924
 925         ret = intel_irq_install(i915);
 926         if (ret)
 927                 goto out_cleanup_modeset;
 928
 929         ret = intel_modeset_init_nogem(i915);
 930         if (ret)
 931                 goto out_cleanup_irq;
 932
 933         ret = i915_gem_init(i915);
 934         if (ret)
 935                 goto out_cleanup_modeset2;
 936
 937         ret = intel_modeset_init(i915);
 938         if (ret)
 939                 goto out_cleanup_gem;
 940
 941         i915_driver_register(i915);
 942
 943         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 944
 945         i915_welcome_messages(i915);
 946
 947         i915->do_release = true;
 948
 949         return 0;
 950
 951 out_cleanup_gem:
 952         i915_gem_suspend(i915);
 953         i915_gem_driver_remove(i915);
 954         i915_gem_driver_release(i915);
 955 out_cleanup_modeset2:
 956         /* FIXME clean up the error path */
 957         intel_modeset_driver_remove(i915);
 958         intel_irq_uninstall(i915);
 959         intel_modeset_driver_remove_noirq(i915);
 960         goto out_cleanup_modeset;
 961 out_cleanup_irq:
 962         intel_irq_uninstall(i915);
 963 out_cleanup_modeset:
 964         intel_modeset_driver_remove_nogem(i915);
 965 out_cleanup_hw:
 966         i915_driver_hw_remove(i915);
 967         intel_memory_regions_driver_release(i915);
 968         i915_ggtt_driver_release(i915);
 969         i915_gem_drain_freed_objects(i915);
 970         i915_ggtt_driver_late_release(i915);
 971 out_cleanup_mmio:
 972         i915_driver_mmio_release(i915);
 973 out_tiles_cleanup:
 974         intel_gt_release_all(i915);
 975 out_runtime_pm_put:
 976         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 977         i915_driver_late_release(i915);
 978 out_pci_disable:
 979         pci_disable_device(pdev);
 980 out_fini:
 981         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 982         return ret;
 983 }
 984
 985 void i915_driver_remove(struct drm_i915_private *i915)
 986 {
 987         intel_wakeref_t wakeref;
 988
 989         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 990
 991         i915_driver_unregister(i915);
 992
 993         /* Flush any external code that still may be under the RCU lock */
 994         synchronize_rcu();
 995
 996         i915_gem_suspend(i915);
 997
 998         intel_gvt_driver_remove(i915);
 999
1000         intel_modeset_driver_remove(i915);
1001
1002         intel_irq_uninstall(i915);
1003
1004         intel_modeset_driver_remove_noirq(i915);
1005
1006         i915_reset_error_state(i915);
1007         i915_gem_driver_remove(i915);
1008
1009         intel_modeset_driver_remove_nogem(i915);
1010
1011         i915_driver_hw_remove(i915);
1012
1013         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1014 }
1015
1016 static void i915_driver_release(struct drm_device *dev)
1017 {
1018         struct drm_i915_private *dev_priv = to_i915(dev);
1019         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1020         intel_wakeref_t wakeref;
1021
1022         if (!dev_priv->do_release)
1023                 return;
1024
1025         wakeref = intel_runtime_pm_get(rpm);
1026
1027         i915_gem_driver_release(dev_priv);
1028
1029         intel_memory_regions_driver_release(dev_priv);
1030         i915_ggtt_driver_release(dev_priv);
1031         i915_gem_drain_freed_objects(dev_priv);
1032         i915_ggtt_driver_late_release(dev_priv);
1033
1034         i915_driver_mmio_release(dev_priv);
1035
1036         intel_runtime_pm_put(rpm, wakeref);
1037
1038         intel_runtime_pm_driver_release(rpm);
1039
1040         i915_driver_late_release(dev_priv);
1041 }
1042
1043 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1044 {
1045         struct drm_i915_private *i915 = to_i915(dev);
1046         int ret;
1047
1048         ret = i915_gem_open(i915, file);
1049         if (ret)
1050                 return ret;
1051
1052         return 0;
1053 }
1054
1055 /**
1056  * i915_driver_lastclose - clean up after all DRM clients have exited
1057  * @dev: DRM device
1058  *
1059  * Take care of cleaning up after all DRM clients have exited.  In the
1060  * mode setting case, we want to restore the kernel's initial mode (just
1061  * in case the last client left us in a bad state).
1062  *
1063  * Additionally, in the non-mode setting case, we'll tear down the GTT
1064  * and DMA structures, since the kernel won't be using them, and clea
1065  * up any GEM state.
1066  */
1067 static void i915_driver_lastclose(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *i915 = to_i915(dev);
1070
1071         intel_fbdev_restore_mode(dev);
1072
1073         if (HAS_DISPLAY(i915))
1074                 vga_switcheroo_process_delayed_switch();
1075 }
1076
1077 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1078 {
1079         struct drm_i915_file_private *file_priv = file->driver_priv;
1080
1081         i915_gem_context_close(file);
1082         i915_drm_client_put(file_priv->client);
1083
1084         kfree_rcu(file_priv, rcu);
1085
1086         /* Catch up with all the deferred frees from "this" client */
1087         i915_gem_flush_free_objects(to_i915(dev));
1088 }
1089
1090 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1091 {
1092         struct intel_encoder *encoder;
1093
1094         if (!HAS_DISPLAY(dev_priv))
1095                 return;
1096
1097         drm_modeset_lock_all(&dev_priv->drm);
1098         for_each_intel_encoder(&dev_priv->drm, encoder)
1099                 if (encoder->suspend)
1100                         encoder->suspend(encoder);
1101         drm_modeset_unlock_all(&dev_priv->drm);
1102 }
1103
1104 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1105 {
1106         struct intel_encoder *encoder;
1107
1108         if (!HAS_DISPLAY(dev_priv))
1109                 return;
1110
1111         drm_modeset_lock_all(&dev_priv->drm);
1112         for_each_intel_encoder(&dev_priv->drm, encoder)
1113                 if (encoder->shutdown)
1114                         encoder->shutdown(encoder);
1115         drm_modeset_unlock_all(&dev_priv->drm);
1116 }
1117
1118 void i915_driver_shutdown(struct drm_i915_private *i915)
1119 {
1120         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1121         intel_runtime_pm_disable(&i915->runtime_pm);
1122         intel_power_domains_disable(i915);
1123
1124         if (HAS_DISPLAY(i915)) {
1125                 drm_kms_helper_poll_disable(&i915->drm);
1126
1127                 drm_atomic_helper_shutdown(&i915->drm);
1128         }
1129
1130         intel_dp_mst_suspend(i915);
1131
1132         intel_runtime_pm_disable_interrupts(i915);
1133         intel_hpd_cancel_work(i915);
1134
1135         intel_suspend_encoders(i915);
1136         intel_shutdown_encoders(i915);
1137
1138         intel_dmc_ucode_suspend(i915);
1139
1140         i915_gem_suspend(i915);
1141
1142         /*
1143          * The only requirement is to reboot with display DC states disabled,
1144          * for now leaving all display power wells in the INIT power domain
1145          * enabled.
1146          *
1147          * TODO:
1148          * - unify the pci_driver::shutdown sequence here with the
1149          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1150          * - unify the driver remove and system/runtime suspend sequences with
1151          *   the above unified shutdown/poweroff sequence.
1152          */
1153         intel_power_domains_driver_remove(i915);
1154         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1155
1156         intel_runtime_pm_driver_release(&i915->runtime_pm);
1157 }
1158
1159 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1160 {
1161 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1162         if (acpi_target_system_state() < ACPI_STATE_S3)
1163                 return true;
1164 #endif
1165         return false;
1166 }
1167
1168 static int i915_drm_prepare(struct drm_device *dev)
1169 {
1170         struct drm_i915_private *i915 = to_i915(dev);
1171
1172         /*
1173          * NB intel_display_suspend() may issue new requests after we've
1174          * ostensibly marked the GPU as ready-to-sleep here. We need to
1175          * split out that work and pull it forward so that after point,
1176          * the GPU is not woken again.
1177          */
1178         return i915_gem_backup_suspend(i915);
1179 }
1180
1181 static int i915_drm_suspend(struct drm_device *dev)
1182 {
1183         struct drm_i915_private *dev_priv = to_i915(dev);
1184         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1185         pci_power_t opregion_target_state;
1186
1187         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1188
1189         /* We do a lot of poking in a lot of registers, make sure they work
1190          * properly. */
1191         intel_power_domains_disable(dev_priv);
1192         if (HAS_DISPLAY(dev_priv))
1193                 drm_kms_helper_poll_disable(dev);
1194
1195         pci_save_state(pdev);
1196
1197         intel_display_suspend(dev);
1198
1199         intel_dp_mst_suspend(dev_priv);
1200
1201         intel_runtime_pm_disable_interrupts(dev_priv);
1202         intel_hpd_cancel_work(dev_priv);
1203
1204         intel_suspend_encoders(dev_priv);
1205
1206         intel_suspend_hw(dev_priv);
1207
1208         /* Must be called before GGTT is suspended. */
1209         intel_dpt_suspend(dev_priv);
1210         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1211
1212         i915_save_display(dev_priv);
1213
1214         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1215         intel_opregion_suspend(dev_priv, opregion_target_state);
1216
1217         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1218
1219         dev_priv->suspend_count++;
1220
1221         intel_dmc_ucode_suspend(dev_priv);
1222
1223         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1224
1225         i915_gem_drain_freed_objects(dev_priv);
1226
1227         return 0;
1228 }
1229
1230 static enum i915_drm_suspend_mode
1231 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1232 {
1233         if (hibernate)
1234                 return I915_DRM_SUSPEND_HIBERNATE;
1235
1236         if (suspend_to_idle(dev_priv))
1237                 return I915_DRM_SUSPEND_IDLE;
1238
1239         return I915_DRM_SUSPEND_MEM;
1240 }
1241
1242 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1243 {
1244         struct drm_i915_private *dev_priv = to_i915(dev);
1245         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1246         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1247         struct intel_gt *gt;
1248         int ret, i;
1249
1250         disable_rpm_wakeref_asserts(rpm);
1251
1252         i915_gem_suspend_late(dev_priv);
1253
1254         for_each_gt(gt, dev_priv, i)
1255                 intel_uncore_suspend(gt->uncore);
1256
1257         intel_power_domains_suspend(dev_priv,
1258                                     get_suspend_mode(dev_priv, hibernation));
1259
1260         intel_display_power_suspend_late(dev_priv);
1261
1262         ret = vlv_suspend_complete(dev_priv);
1263         if (ret) {
1264                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1265                 intel_power_domains_resume(dev_priv);
1266
1267                 goto out;
1268         }
1269
1270         pci_disable_device(pdev);
1271         /*
1272          * During hibernation on some platforms the BIOS may try to access
1273          * the device even though it's already in D3 and hang the machine. So
1274          * leave the device in D0 on those platforms and hope the BIOS will
1275          * power down the device properly. The issue was seen on multiple old
1276          * GENs with different BIOS vendors, so having an explicit blacklist
1277          * is inpractical; apply the workaround on everything pre GEN6. The
1278          * platforms where the issue was seen:
1279          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1280          * Fujitsu FSC S7110
1281          * Acer Aspire 1830T
1282          */
1283         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1284                 pci_set_power_state(pdev, PCI_D3hot);
1285
1286 out:
1287         enable_rpm_wakeref_asserts(rpm);
1288         if (!dev_priv->uncore.user_forcewake_count)
1289                 intel_runtime_pm_driver_release(rpm);
1290
1291         return ret;
1292 }
1293
1294 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1295                                    pm_message_t state)
1296 {
1297         int error;
1298
1299         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1300                              state.event != PM_EVENT_FREEZE))
1301                 return -EINVAL;
1302
1303         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1304                 return 0;
1305
1306         error = i915_drm_suspend(&i915->drm);
1307         if (error)
1308                 return error;
1309
1310         return i915_drm_suspend_late(&i915->drm, false);
1311 }
1312
1313 static int i915_drm_resume(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = to_i915(dev);
1316         int ret;
1317
1318         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1319
1320         ret = i915_pcode_init(dev_priv);
1321         if (ret)
1322                 return ret;
1323
1324         sanitize_gpu(dev_priv);
1325
1326         ret = i915_ggtt_enable_hw(dev_priv);
1327         if (ret)
1328                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1329
1330         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1331         /* Must be called after GGTT is resumed. */
1332         intel_dpt_resume(dev_priv);
1333
1334         intel_dmc_ucode_resume(dev_priv);
1335
1336         i915_restore_display(dev_priv);
1337         intel_pps_unlock_regs_wa(dev_priv);
1338
1339         intel_init_pch_refclk(dev_priv);
1340
1341         /*
1342          * Interrupts have to be enabled before any batches are run. If not the
1343          * GPU will hang. i915_gem_init_hw() will initiate batches to
1344          * update/restore the context.
1345          *
1346          * drm_mode_config_reset() needs AUX interrupts.
1347          *
1348          * Modeset enabling in intel_modeset_init_hw() also needs working
1349          * interrupts.
1350          */
1351         intel_runtime_pm_enable_interrupts(dev_priv);
1352
1353         if (HAS_DISPLAY(dev_priv))
1354                 drm_mode_config_reset(dev);
1355
1356         i915_gem_resume(dev_priv);
1357
1358         intel_modeset_init_hw(dev_priv);
1359         intel_init_clock_gating(dev_priv);
1360         intel_hpd_init(dev_priv);
1361
1362         /* MST sideband requires HPD interrupts enabled */
1363         intel_dp_mst_resume(dev_priv);
1364         intel_display_resume(dev);
1365
1366         intel_hpd_poll_disable(dev_priv);
1367         if (HAS_DISPLAY(dev_priv))
1368                 drm_kms_helper_poll_enable(dev);
1369
1370         intel_opregion_resume(dev_priv);
1371
1372         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1373
1374         intel_power_domains_enable(dev_priv);
1375
1376         intel_gvt_resume(dev_priv);
1377
1378         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1379
1380         return 0;
1381 }
1382
1383 static int i915_drm_resume_early(struct drm_device *dev)
1384 {
1385         struct drm_i915_private *dev_priv = to_i915(dev);
1386         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1387         struct intel_gt *gt;
1388         int ret, i;
1389
1390         /*
1391          * We have a resume ordering issue with the snd-hda driver also
1392          * requiring our device to be power up. Due to the lack of a
1393          * parent/child relationship we currently solve this with an early
1394          * resume hook.
1395          *
1396          * FIXME: This should be solved with a special hdmi sink device or
1397          * similar so that power domains can be employed.
1398          */
1399
1400         /*
1401          * Note that we need to set the power state explicitly, since we
1402          * powered off the device during freeze and the PCI core won't power
1403          * it back up for us during thaw. Powering off the device during
1404          * freeze is not a hard requirement though, and during the
1405          * suspend/resume phases the PCI core makes sure we get here with the
1406          * device powered on. So in case we change our freeze logic and keep
1407          * the device powered we can also remove the following set power state
1408          * call.
1409          */
1410         ret = pci_set_power_state(pdev, PCI_D0);
1411         if (ret) {
1412                 drm_err(&dev_priv->drm,
1413                         "failed to set PCI D0 power state (%d)\n", ret);
1414                 return ret;
1415         }
1416
1417         /*
1418          * Note that pci_enable_device() first enables any parent bridge
1419          * device and only then sets the power state for this device. The
1420          * bridge enabling is a nop though, since bridge devices are resumed
1421          * first. The order of enabling power and enabling the device is
1422          * imposed by the PCI core as described above, so here we preserve the
1423          * same order for the freeze/thaw phases.
1424          *
1425          * TODO: eventually we should remove pci_disable_device() /
1426          * pci_enable_enable_device() from suspend/resume. Due to how they
1427          * depend on the device enable refcount we can't anyway depend on them
1428          * disabling/enabling the device.
1429          */
1430         if (pci_enable_device(pdev))
1431                 return -EIO;
1432
1433         pci_set_master(pdev);
1434
1435         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1436
1437         ret = vlv_resume_prepare(dev_priv, false);
1438         if (ret)
1439                 drm_err(&dev_priv->drm,
1440                         "Resume prepare failed: %d, continuing anyway\n", ret);
1441
1442         for_each_gt(gt, dev_priv, i) {
1443                 intel_uncore_resume_early(gt->uncore);
1444                 intel_gt_check_and_clear_faults(gt);
1445         }
1446
1447         intel_display_power_resume_early(dev_priv);
1448
1449         intel_power_domains_resume(dev_priv);
1450
1451         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1452
1453         return ret;
1454 }
1455
1456 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1457 {
1458         int ret;
1459
1460         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1461                 return 0;
1462
1463         ret = i915_drm_resume_early(&i915->drm);
1464         if (ret)
1465                 return ret;
1466
1467         return i915_drm_resume(&i915->drm);
1468 }
1469
1470 static int i915_pm_prepare(struct device *kdev)
1471 {
1472         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1473
1474         if (!i915) {
1475                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1476                 return -ENODEV;
1477         }
1478
1479         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1480                 return 0;
1481
1482         return i915_drm_prepare(&i915->drm);
1483 }
1484
1485 static int i915_pm_suspend(struct device *kdev)
1486 {
1487         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1488
1489         if (!i915) {
1490                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1491                 return -ENODEV;
1492         }
1493
1494         i915_ggtt_mark_pte_lost(i915, false);
1495
1496         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1497                 return 0;
1498
1499         return i915_drm_suspend(&i915->drm);
1500 }
1501
1502 static int i915_pm_suspend_late(struct device *kdev)
1503 {
1504         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1505
1506         /*
1507          * We have a suspend ordering issue with the snd-hda driver also
1508          * requiring our device to be power up. Due to the lack of a
1509          * parent/child relationship we currently solve this with an late
1510          * suspend hook.
1511          *
1512          * FIXME: This should be solved with a special hdmi sink device or
1513          * similar so that power domains can be employed.
1514          */
1515         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1516                 return 0;
1517
1518         return i915_drm_suspend_late(&i915->drm, false);
1519 }
1520
1521 static int i915_pm_poweroff_late(struct device *kdev)
1522 {
1523         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1524
1525         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1526                 return 0;
1527
1528         return i915_drm_suspend_late(&i915->drm, true);
1529 }
1530
1531 static int i915_pm_resume_early(struct device *kdev)
1532 {
1533         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1534
1535         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1536                 return 0;
1537
1538         return i915_drm_resume_early(&i915->drm);
1539 }
1540
1541 static int i915_pm_resume(struct device *kdev)
1542 {
1543         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1544
1545         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1546                 return 0;
1547
1548         /*
1549          * If IRST is enabled, or if we can't detect whether it's enabled,
1550          * then we must assume we lost the GGTT page table entries, since
1551          * they are not retained if IRST decided to enter S4.
1552          */
1553         if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1))
1554                 i915_ggtt_mark_pte_lost(i915, true);
1555
1556         return i915_drm_resume(&i915->drm);
1557 }
1558
1559 /* freeze: before creating the hibernation_image */
1560 static int i915_pm_freeze(struct device *kdev)
1561 {
1562         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1563         int ret;
1564
1565         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1566                 ret = i915_drm_suspend(&i915->drm);
1567                 if (ret)
1568                         return ret;
1569         }
1570
1571         ret = i915_gem_freeze(i915);
1572         if (ret)
1573                 return ret;
1574
1575         return 0;
1576 }
1577
1578 static int i915_pm_freeze_late(struct device *kdev)
1579 {
1580         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1581         int ret;
1582
1583         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1584                 ret = i915_drm_suspend_late(&i915->drm, true);
1585                 if (ret)
1586                         return ret;
1587         }
1588
1589         ret = i915_gem_freeze_late(i915);
1590         if (ret)
1591                 return ret;
1592
1593         return 0;
1594 }
1595
1596 /* thaw: called after creating the hibernation image, but before turning off. */
1597 static int i915_pm_thaw_early(struct device *kdev)
1598 {
1599         return i915_pm_resume_early(kdev);
1600 }
1601
1602 static int i915_pm_thaw(struct device *kdev)
1603 {
1604         return i915_pm_resume(kdev);
1605 }
1606
1607 /* restore: called after loading the hibernation image. */
1608 static int i915_pm_restore_early(struct device *kdev)
1609 {
1610         return i915_pm_resume_early(kdev);
1611 }
1612
1613 static int i915_pm_restore(struct device *kdev)
1614 {
1615         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1616
1617         i915_ggtt_mark_pte_lost(i915, true);
1618         return i915_pm_resume(kdev);
1619 }
1620
1621 static int intel_runtime_suspend(struct device *kdev)
1622 {
1623         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1624         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1625         struct intel_gt *gt;
1626         int ret, i;
1627
1628         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1629                 return -ENODEV;
1630
1631         drm_dbg(&dev_priv->drm, "Suspending device\n");
1632
1633         disable_rpm_wakeref_asserts(rpm);
1634
1635         /*
1636          * We are safe here against re-faults, since the fault handler takes
1637          * an RPM reference.
1638          */
1639         i915_gem_runtime_suspend(dev_priv);
1640
1641         for_each_gt(gt, dev_priv, i)
1642                 intel_gt_runtime_suspend(gt);
1643
1644         intel_runtime_pm_disable_interrupts(dev_priv);
1645
1646         for_each_gt(gt, dev_priv, i)
1647                 intel_uncore_suspend(gt->uncore);
1648
1649         intel_display_power_suspend(dev_priv);
1650
1651         ret = vlv_suspend_complete(dev_priv);
1652         if (ret) {
1653                 drm_err(&dev_priv->drm,
1654                         "Runtime suspend failed, disabling it (%d)\n", ret);
1655                 intel_uncore_runtime_resume(&dev_priv->uncore);
1656
1657                 intel_runtime_pm_enable_interrupts(dev_priv);
1658
1659                 intel_gt_runtime_resume(to_gt(dev_priv));
1660
1661                 enable_rpm_wakeref_asserts(rpm);
1662
1663                 return ret;
1664         }
1665
1666         enable_rpm_wakeref_asserts(rpm);
1667         intel_runtime_pm_driver_release(rpm);
1668
1669         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1670                 drm_err(&dev_priv->drm,
1671                         "Unclaimed access detected prior to suspending\n");
1672
1673         rpm->suspended = true;
1674
1675         /*
1676          * FIXME: We really should find a document that references the arguments
1677          * used below!
1678          */
1679         if (IS_BROADWELL(dev_priv)) {
1680                 /*
1681                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1682                  * being detected, and the call we do at intel_runtime_resume()
1683                  * won't be able to restore them. Since PCI_D3hot matches the
1684                  * actual specification and appears to be working, use it.
1685                  */
1686                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1687         } else {
1688                 /*
1689                  * current versions of firmware which depend on this opregion
1690                  * notification have repurposed the D1 definition to mean
1691                  * "runtime suspended" vs. what you would normally expect (D3)
1692                  * to distinguish it from notifications that might be sent via
1693                  * the suspend path.
1694                  */
1695                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1696         }
1697
1698         assert_forcewakes_inactive(&dev_priv->uncore);
1699
1700         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1701                 intel_hpd_poll_enable(dev_priv);
1702
1703         drm_dbg(&dev_priv->drm, "Device suspended\n");
1704         return 0;
1705 }
1706
1707 static int intel_runtime_resume(struct device *kdev)
1708 {
1709         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1710         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1711         struct intel_gt *gt;
1712         int ret, i;
1713
1714         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1715                 return -ENODEV;
1716
1717         drm_dbg(&dev_priv->drm, "Resuming device\n");
1718
1719         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1720         disable_rpm_wakeref_asserts(rpm);
1721
1722         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1723         rpm->suspended = false;
1724         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1725                 drm_dbg(&dev_priv->drm,
1726                         "Unclaimed access during suspend, bios?\n");
1727
1728         intel_display_power_resume(dev_priv);
1729
1730         ret = vlv_resume_prepare(dev_priv, true);
1731
1732         for_each_gt(gt, dev_priv, i)
1733                 intel_uncore_runtime_resume(gt->uncore);
1734
1735         intel_runtime_pm_enable_interrupts(dev_priv);
1736
1737         /*
1738          * No point of rolling back things in case of an error, as the best
1739          * we can do is to hope that things will still work (and disable RPM).
1740          */
1741         for_each_gt(gt, dev_priv, i)
1742                 intel_gt_runtime_resume(gt);
1743
1744         /*
1745          * On VLV/CHV display interrupts are part of the display
1746          * power well, so hpd is reinitialized from there. For
1747          * everyone else do it here.
1748          */
1749         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1750                 intel_hpd_init(dev_priv);
1751                 intel_hpd_poll_disable(dev_priv);
1752         }
1753
1754         skl_watermark_ipc_update(dev_priv);
1755
1756         enable_rpm_wakeref_asserts(rpm);
1757
1758         if (ret)
1759                 drm_err(&dev_priv->drm,
1760                         "Runtime resume failed, disabling it (%d)\n", ret);
1761         else
1762                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1763
1764         return ret;
1765 }
1766
1767 const struct dev_pm_ops i915_pm_ops = {
1768         /*
1769          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1770          * PMSG_RESUME]
1771          */
1772         .prepare = i915_pm_prepare,
1773         .suspend = i915_pm_suspend,
1774         .suspend_late = i915_pm_suspend_late,
1775         .resume_early = i915_pm_resume_early,
1776         .resume = i915_pm_resume,
1777
1778         /*
1779          * S4 event handlers
1780          * @freeze, @freeze_late    : called (1) before creating the
1781          *                            hibernation image [PMSG_FREEZE] and
1782          *                            (2) after rebooting, before restoring
1783          *                            the image [PMSG_QUIESCE]
1784          * @thaw, @thaw_early       : called (1) after creating the hibernation
1785          *                            image, before writing it [PMSG_THAW]
1786          *                            and (2) after failing to create or
1787          *                            restore the image [PMSG_RECOVER]
1788          * @poweroff, @poweroff_late: called after writing the hibernation
1789          *                            image, before rebooting [PMSG_HIBERNATE]
1790          * @restore, @restore_early : called after rebooting and restoring the
1791          *                            hibernation image [PMSG_RESTORE]
1792          */
1793         .freeze = i915_pm_freeze,
1794         .freeze_late = i915_pm_freeze_late,
1795         .thaw_early = i915_pm_thaw_early,
1796         .thaw = i915_pm_thaw,
1797         .poweroff = i915_pm_suspend,
1798         .poweroff_late = i915_pm_poweroff_late,
1799         .restore_early = i915_pm_restore_early,
1800         .restore = i915_pm_restore,
1801
1802         /* S0ix (via runtime suspend) event handlers */
1803         .runtime_suspend = intel_runtime_suspend,
1804         .runtime_resume = intel_runtime_resume,
1805 };
1806
1807 static const struct file_operations i915_driver_fops = {
1808         .owner = THIS_MODULE,
1809         .open = drm_open,
1810         .release = drm_release_noglobal,
1811         .unlocked_ioctl = drm_ioctl,
1812         .mmap = i915_gem_mmap,
1813         .poll = drm_poll,
1814         .read = drm_read,
1815         .compat_ioctl = i915_ioc32_compat_ioctl,
1816         .llseek = noop_llseek,
1817 #ifdef CONFIG_PROC_FS
1818         .show_fdinfo = i915_drm_client_fdinfo,
1819 #endif
1820 };
1821
1822 static int
1823 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1824                           struct drm_file *file)
1825 {
1826         return -ENODEV;
1827 }
1828
1829 static const struct drm_ioctl_desc i915_ioctls[] = {
1830         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1831         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1832         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1833         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1834         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1835         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1836         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1837         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1838         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1839         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1840         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1841         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1842         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1843         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1844         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1845         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1846         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1847         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1848         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1849         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1850         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1851         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1852         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1853         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1854         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1855         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1856         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1857         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1858         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1859         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1860         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1861         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1862         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1863         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1864         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1865         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1866         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1867         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1868         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1869         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1870         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1871         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1872         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1873         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1874         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1875         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1876         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1877         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1878         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1879         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1880         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1881         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1882         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1883         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1884         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1885         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1886         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1887         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1888         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1889 };
1890
1891 /*
1892  * Interface history:
1893  *
1894  * 1.1: Original.
1895  * 1.2: Add Power Management
1896  * 1.3: Add vblank support
1897  * 1.4: Fix cmdbuffer path, add heap destroy
1898  * 1.5: Add vblank pipe configuration
1899  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1900  *      - Support vertical blank on secondary display pipe
1901  */
1902 #define DRIVER_MAJOR            1
1903 #define DRIVER_MINOR            6
1904 #define DRIVER_PATCHLEVEL       0
1905
1906 static const struct drm_driver i915_drm_driver = {
1907         /* Don't use MTRRs here; the Xserver or userspace app should
1908          * deal with them for Intel hardware.
1909          */
1910         .driver_features =
1911             DRIVER_GEM |
1912             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1913             DRIVER_SYNCOBJ_TIMELINE,
1914         .release = i915_driver_release,
1915         .open = i915_driver_open,
1916         .lastclose = i915_driver_lastclose,
1917         .postclose = i915_driver_postclose,
1918
1919         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1920         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1921         .gem_prime_import = i915_gem_prime_import,
1922
1923         .dumb_create = i915_gem_dumb_create,
1924         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1925
1926         .ioctls = i915_ioctls,
1927         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1928         .fops = &i915_driver_fops,
1929         .name = DRIVER_NAME,
1930         .desc = DRIVER_DESC,
1931         .date = DRIVER_DATE,
1932         .major = DRIVER_MAJOR,
1933         .minor = DRIVER_MINOR,
1934         .patchlevel = DRIVER_PATCHLEVEL,
1935 };