drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33
  34 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  35 {
  36         return to_i915(node->minor->dev);
  37 }
  38
  39 static __always_inline void seq_print_param(struct seq_file *m,
  40                                             const char *name,
  41                                             const char *type,
  42                                             const void *x)
  43 {
  44         if (!__builtin_strcmp(type, "bool"))
  45                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  46         else if (!__builtin_strcmp(type, "int"))
  47                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  48         else if (!__builtin_strcmp(type, "unsigned int"))
  49                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  50         else if (!__builtin_strcmp(type, "char *"))
  51                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  52         else
  53                 BUILD_BUG();
  54 }
  55
  56 static int i915_capabilities(struct seq_file *m, void *data)
  57 {
  58         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  59         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  60
  61         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  62         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  63         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  64
  65 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  66         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  67 #undef PRINT_FLAG
  68
  69         kernel_param_lock(THIS_MODULE);
  70 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
  71         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  72 #undef PRINT_PARAM
  73         kernel_param_unlock(THIS_MODULE);
  74
  75         return 0;
  76 }
  77
  78 static char get_active_flag(struct drm_i915_gem_object *obj)
  79 {
  80         return i915_gem_object_is_active(obj) ? '*' : ' ';
  81 }
  82
  83 static char get_pin_flag(struct drm_i915_gem_object *obj)
  84 {
  85         return obj->pin_display ? 'p' : ' ';
  86 }
  87
  88 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  89 {
  90         switch (i915_gem_object_get_tiling(obj)) {
  91         default:
  92         case I915_TILING_NONE: return ' ';
  93         case I915_TILING_X: return 'X';
  94         case I915_TILING_Y: return 'Y';
  95         }
  96 }
  97
  98 static char get_global_flag(struct drm_i915_gem_object *obj)
  99 {
 100         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 101 }
 102
 103 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 104 {
 105         return obj->mm.mapping ? 'M' : ' ';
 106 }
 107
 108 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 109 {
 110         u64 size = 0;
 111         struct i915_vma *vma;
 112
 113         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 114                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 115                         size += vma->node.size;
 116         }
 117
 118         return size;
 119 }
 120
 121 static void
 122 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 125         struct intel_engine_cs *engine;
 126         struct i915_vma *vma;
 127         unsigned int frontbuffer_bits;
 128         int pin_count = 0;
 129
 130         lockdep_assert_held(&obj->base.dev->struct_mutex);
 131
 132         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 133                    &obj->base,
 134                    get_active_flag(obj),
 135                    get_pin_flag(obj),
 136                    get_tiling_flag(obj),
 137                    get_global_flag(obj),
 138                    get_pin_mapped_flag(obj),
 139                    obj->base.size / 1024,
 140                    obj->base.read_domains,
 141                    obj->base.write_domain,
 142                    i915_cache_level_str(dev_priv, obj->cache_level),
 143                    obj->mm.dirty ? " dirty" : "",
 144                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 145         if (obj->base.name)
 146                 seq_printf(m, " (name: %d)", obj->base.name);
 147         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 148                 if (i915_vma_is_pinned(vma))
 149                         pin_count++;
 150         }
 151         seq_printf(m, " (pinned x %d)", pin_count);
 152         if (obj->pin_display)
 153                 seq_printf(m, " (display)");
 154         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 155                 if (!drm_mm_node_allocated(&vma->node))
 156                         continue;
 157
 158                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 159                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 160                            vma->node.start, vma->node.size);
 161                 if (i915_vma_is_ggtt(vma)) {
 162                         switch (vma->ggtt_view.type) {
 163                         case I915_GGTT_VIEW_NORMAL:
 164                                 seq_puts(m, ", normal");
 165                                 break;
 166
 167                         case I915_GGTT_VIEW_PARTIAL:
 168                                 seq_printf(m, ", partial [%08llx+%x]",
 169                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 170                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 171                                 break;
 172
 173                         case I915_GGTT_VIEW_ROTATED:
 174                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 175                                            vma->ggtt_view.rotated.plane[0].width,
 176                                            vma->ggtt_view.rotated.plane[0].height,
 177                                            vma->ggtt_view.rotated.plane[0].stride,
 178                                            vma->ggtt_view.rotated.plane[0].offset,
 179                                            vma->ggtt_view.rotated.plane[1].width,
 180                                            vma->ggtt_view.rotated.plane[1].height,
 181                                            vma->ggtt_view.rotated.plane[1].stride,
 182                                            vma->ggtt_view.rotated.plane[1].offset);
 183                                 break;
 184
 185                         default:
 186                                 MISSING_CASE(vma->ggtt_view.type);
 187                                 break;
 188                         }
 189                 }
 190                 if (vma->fence)
 191                         seq_printf(m, " , fence: %d%s",
 192                                    vma->fence->id,
 193                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 194                 seq_puts(m, ")");
 195         }
 196         if (obj->stolen)
 197                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 198
 199         engine = i915_gem_object_last_write_engine(obj);
 200         if (engine)
 201                 seq_printf(m, " (%s)", engine->name);
 202
 203         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 204         if (frontbuffer_bits)
 205                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 206 }
 207
 208 static int obj_rank_by_stolen(const void *A, const void *B)
 209 {
 210         const struct drm_i915_gem_object *a =
 211                 *(const struct drm_i915_gem_object **)A;
 212         const struct drm_i915_gem_object *b =
 213                 *(const struct drm_i915_gem_object **)B;
 214
 215         if (a->stolen->start < b->stolen->start)
 216                 return -1;
 217         if (a->stolen->start > b->stolen->start)
 218                 return 1;
 219         return 0;
 220 }
 221
 222 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 223 {
 224         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 225         struct drm_device *dev = &dev_priv->drm;
 226         struct drm_i915_gem_object **objects;
 227         struct drm_i915_gem_object *obj;
 228         u64 total_obj_size, total_gtt_size;
 229         unsigned long total, count, n;
 230         int ret;
 231
 232         total = READ_ONCE(dev_priv->mm.object_count);
 233         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 234         if (!objects)
 235                 return -ENOMEM;
 236
 237         ret = mutex_lock_interruptible(&dev->struct_mutex);
 238         if (ret)
 239                 goto out;
 240
 241         total_obj_size = total_gtt_size = count = 0;
 242         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 243                 if (count == total)
 244                         break;
 245
 246                 if (obj->stolen == NULL)
 247                         continue;
 248
 249                 objects[count++] = obj;
 250                 total_obj_size += obj->base.size;
 251                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 252
 253         }
 254         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 255                 if (count == total)
 256                         break;
 257
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 objects[count++] = obj;
 262                 total_obj_size += obj->base.size;
 263         }
 264
 265         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 266
 267         seq_puts(m, "Stolen:\n");
 268         for (n = 0; n < count; n++) {
 269                 seq_puts(m, "   ");
 270                 describe_obj(m, objects[n]);
 271                 seq_putc(m, '\n');
 272         }
 273         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 274                    count, total_obj_size, total_gtt_size);
 275
 276         mutex_unlock(&dev->struct_mutex);
 277 out:
 278         kvfree(objects);
 279         return ret;
 280 }
 281
 282 struct file_stats {
 283         struct drm_i915_file_private *file_priv;
 284         unsigned long count;
 285         u64 total, unbound;
 286         u64 global, shared;
 287         u64 active, inactive;
 288 };
 289
 290 static int per_file_stats(int id, void *ptr, void *data)
 291 {
 292         struct drm_i915_gem_object *obj = ptr;
 293         struct file_stats *stats = data;
 294         struct i915_vma *vma;
 295
 296         lockdep_assert_held(&obj->base.dev->struct_mutex);
 297
 298         stats->count++;
 299         stats->total += obj->base.size;
 300         if (!obj->bind_count)
 301                 stats->unbound += obj->base.size;
 302         if (obj->base.name || obj->base.dma_buf)
 303                 stats->shared += obj->base.size;
 304
 305         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 306                 if (!drm_mm_node_allocated(&vma->node))
 307                         continue;
 308
 309                 if (i915_vma_is_ggtt(vma)) {
 310                         stats->global += vma->node.size;
 311                 } else {
 312                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 313
 314                         if (ppgtt->base.file != stats->file_priv)
 315                                 continue;
 316                 }
 317
 318                 if (i915_vma_is_active(vma))
 319                         stats->active += vma->node.size;
 320                 else
 321                         stats->inactive += vma->node.size;
 322         }
 323
 324         return 0;
 325 }
 326
 327 #define print_file_stats(m, name, stats) do { \
 328         if (stats.count) \
 329                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 330                            name, \
 331                            stats.count, \
 332                            stats.total, \
 333                            stats.active, \
 334                            stats.inactive, \
 335                            stats.global, \
 336                            stats.shared, \
 337                            stats.unbound); \
 338 } while (0)
 339
 340 static void print_batch_pool_stats(struct seq_file *m,
 341                                    struct drm_i915_private *dev_priv)
 342 {
 343         struct drm_i915_gem_object *obj;
 344         struct file_stats stats;
 345         struct intel_engine_cs *engine;
 346         enum intel_engine_id id;
 347         int j;
 348
 349         memset(&stats, 0, sizeof(stats));
 350
 351         for_each_engine(engine, dev_priv, id) {
 352                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 353                         list_for_each_entry(obj,
 354                                             &engine->batch_pool.cache_list[j],
 355                                             batch_pool_link)
 356                                 per_file_stats(0, obj, &stats);
 357                 }
 358         }
 359
 360         print_file_stats(m, "[k]batch pool", stats);
 361 }
 362
 363 static int per_file_ctx_stats(int id, void *ptr, void *data)
 364 {
 365         struct i915_gem_context *ctx = ptr;
 366         int n;
 367
 368         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 369                 if (ctx->engine[n].state)
 370                         per_file_stats(0, ctx->engine[n].state->obj, data);
 371                 if (ctx->engine[n].ring)
 372                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 373         }
 374
 375         return 0;
 376 }
 377
 378 static void print_context_stats(struct seq_file *m,
 379                                 struct drm_i915_private *dev_priv)
 380 {
 381         struct drm_device *dev = &dev_priv->drm;
 382         struct file_stats stats;
 383         struct drm_file *file;
 384
 385         memset(&stats, 0, sizeof(stats));
 386
 387         mutex_lock(&dev->struct_mutex);
 388         if (dev_priv->kernel_context)
 389                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 390
 391         list_for_each_entry(file, &dev->filelist, lhead) {
 392                 struct drm_i915_file_private *fpriv = file->driver_priv;
 393                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 394         }
 395         mutex_unlock(&dev->struct_mutex);
 396
 397         print_file_stats(m, "[k]contexts", stats);
 398 }
 399
 400 static int i915_gem_object_info(struct seq_file *m, void *data)
 401 {
 402         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 403         struct drm_device *dev = &dev_priv->drm;
 404         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 405         u32 count, mapped_count, purgeable_count, dpy_count;
 406         u64 size, mapped_size, purgeable_size, dpy_size;
 407         struct drm_i915_gem_object *obj;
 408         struct drm_file *file;
 409         int ret;
 410
 411         ret = mutex_lock_interruptible(&dev->struct_mutex);
 412         if (ret)
 413                 return ret;
 414
 415         seq_printf(m, "%u objects, %llu bytes\n",
 416                    dev_priv->mm.object_count,
 417                    dev_priv->mm.object_memory);
 418
 419         size = count = 0;
 420         mapped_size = mapped_count = 0;
 421         purgeable_size = purgeable_count = 0;
 422         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 423                 size += obj->base.size;
 424                 ++count;
 425
 426                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 427                         purgeable_size += obj->base.size;
 428                         ++purgeable_count;
 429                 }
 430
 431                 if (obj->mm.mapping) {
 432                         mapped_count++;
 433                         mapped_size += obj->base.size;
 434                 }
 435         }
 436         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 437
 438         size = count = dpy_size = dpy_count = 0;
 439         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 440                 size += obj->base.size;
 441                 ++count;
 442
 443                 if (obj->pin_display) {
 444                         dpy_size += obj->base.size;
 445                         ++dpy_count;
 446                 }
 447
 448                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 449                         purgeable_size += obj->base.size;
 450                         ++purgeable_count;
 451                 }
 452
 453                 if (obj->mm.mapping) {
 454                         mapped_count++;
 455                         mapped_size += obj->base.size;
 456                 }
 457         }
 458         seq_printf(m, "%u bound objects, %llu bytes\n",
 459                    count, size);
 460         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u mapped objects, %llu bytes\n",
 463                    mapped_count, mapped_size);
 464         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 465                    dpy_count, dpy_size);
 466
 467         seq_printf(m, "%llu [%llu] gtt total\n",
 468                    ggtt->base.total, ggtt->mappable_end);
 469
 470         seq_putc(m, '\n');
 471         print_batch_pool_stats(m, dev_priv);
 472         mutex_unlock(&dev->struct_mutex);
 473
 474         mutex_lock(&dev->filelist_mutex);
 475         print_context_stats(m, dev_priv);
 476         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 477                 struct file_stats stats;
 478                 struct drm_i915_file_private *file_priv = file->driver_priv;
 479                 struct drm_i915_gem_request *request;
 480                 struct task_struct *task;
 481
 482                 mutex_lock(&dev->struct_mutex);
 483
 484                 memset(&stats, 0, sizeof(stats));
 485                 stats.file_priv = file->driver_priv;
 486                 spin_lock(&file->table_lock);
 487                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 488                 spin_unlock(&file->table_lock);
 489                 /*
 490                  * Although we have a valid reference on file->pid, that does
 491                  * not guarantee that the task_struct who called get_pid() is
 492                  * still alive (e.g. get_pid(current) => fork() => exit()).
 493                  * Therefore, we need to protect this ->comm access using RCU.
 494                  */
 495                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 496                                                    struct drm_i915_gem_request,
 497                                                    client_link);
 498                 rcu_read_lock();
 499                 task = pid_task(request && request->ctx->pid ?
 500                                 request->ctx->pid : file->pid,
 501                                 PIDTYPE_PID);
 502                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 503                 rcu_read_unlock();
 504
 505                 mutex_unlock(&dev->struct_mutex);
 506         }
 507         mutex_unlock(&dev->filelist_mutex);
 508
 509         return 0;
 510 }
 511
 512 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 513 {
 514         struct drm_info_node *node = m->private;
 515         struct drm_i915_private *dev_priv = node_to_i915(node);
 516         struct drm_device *dev = &dev_priv->drm;
 517         bool show_pin_display_only = !!node->info_ent->data;
 518         struct drm_i915_gem_object *obj;
 519         u64 total_obj_size, total_gtt_size;
 520         int count, ret;
 521
 522         ret = mutex_lock_interruptible(&dev->struct_mutex);
 523         if (ret)
 524                 return ret;
 525
 526         total_obj_size = total_gtt_size = count = 0;
 527         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 528                 if (show_pin_display_only && !obj->pin_display)
 529                         continue;
 530
 531                 seq_puts(m, "   ");
 532                 describe_obj(m, obj);
 533                 seq_putc(m, '\n');
 534                 total_obj_size += obj->base.size;
 535                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 536                 count++;
 537         }
 538
 539         mutex_unlock(&dev->struct_mutex);
 540
 541         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 542                    count, total_obj_size, total_gtt_size);
 543
 544         return 0;
 545 }
 546
 547 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 548 {
 549         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 550         struct drm_device *dev = &dev_priv->drm;
 551         struct drm_i915_gem_object *obj;
 552         struct intel_engine_cs *engine;
 553         enum intel_engine_id id;
 554         int total = 0;
 555         int ret, j;
 556
 557         ret = mutex_lock_interruptible(&dev->struct_mutex);
 558         if (ret)
 559                 return ret;
 560
 561         for_each_engine(engine, dev_priv, id) {
 562                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 563                         int count;
 564
 565                         count = 0;
 566                         list_for_each_entry(obj,
 567                                             &engine->batch_pool.cache_list[j],
 568                                             batch_pool_link)
 569                                 count++;
 570                         seq_printf(m, "%s cache[%d]: %d objects\n",
 571                                    engine->name, j, count);
 572
 573                         list_for_each_entry(obj,
 574                                             &engine->batch_pool.cache_list[j],
 575                                             batch_pool_link) {
 576                                 seq_puts(m, "   ");
 577                                 describe_obj(m, obj);
 578                                 seq_putc(m, '\n');
 579                         }
 580
 581                         total += count;
 582                 }
 583         }
 584
 585         seq_printf(m, "total: %d\n", total);
 586
 587         mutex_unlock(&dev->struct_mutex);
 588
 589         return 0;
 590 }
 591
 592 static void print_request(struct seq_file *m,
 593                           struct drm_i915_gem_request *rq,
 594                           const char *prefix)
 595 {
 596         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 597                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 598                    rq->priotree.priority,
 599                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 600                    rq->timeline->common->name);
 601 }
 602
 603 static int i915_gem_request_info(struct seq_file *m, void *data)
 604 {
 605         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 606         struct drm_device *dev = &dev_priv->drm;
 607         struct drm_i915_gem_request *req;
 608         struct intel_engine_cs *engine;
 609         enum intel_engine_id id;
 610         int ret, any;
 611
 612         ret = mutex_lock_interruptible(&dev->struct_mutex);
 613         if (ret)
 614                 return ret;
 615
 616         any = 0;
 617         for_each_engine(engine, dev_priv, id) {
 618                 int count;
 619
 620                 count = 0;
 621                 list_for_each_entry(req, &engine->timeline->requests, link)
 622                         count++;
 623                 if (count == 0)
 624                         continue;
 625
 626                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 627                 list_for_each_entry(req, &engine->timeline->requests, link)
 628                         print_request(m, req, "    ");
 629
 630                 any++;
 631         }
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         if (any == 0)
 635                 seq_puts(m, "No requests\n");
 636
 637         return 0;
 638 }
 639
 640 static void i915_ring_seqno_info(struct seq_file *m,
 641                                  struct intel_engine_cs *engine)
 642 {
 643         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 644         struct rb_node *rb;
 645
 646         seq_printf(m, "Current sequence (%s): %x\n",
 647                    engine->name, intel_engine_get_seqno(engine));
 648
 649         spin_lock_irq(&b->rb_lock);
 650         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 651                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 652
 653                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 654                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 655         }
 656         spin_unlock_irq(&b->rb_lock);
 657 }
 658
 659 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 660 {
 661         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 662         struct intel_engine_cs *engine;
 663         enum intel_engine_id id;
 664
 665         for_each_engine(engine, dev_priv, id)
 666                 i915_ring_seqno_info(m, engine);
 667
 668         return 0;
 669 }
 670
 671
 672 static int i915_interrupt_info(struct seq_file *m, void *data)
 673 {
 674         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 675         struct intel_engine_cs *engine;
 676         enum intel_engine_id id;
 677         int i, pipe;
 678
 679         intel_runtime_pm_get(dev_priv);
 680
 681         if (IS_CHERRYVIEW(dev_priv)) {
 682                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 683                            I915_READ(GEN8_MASTER_IRQ));
 684
 685                 seq_printf(m, "Display IER:\t%08x\n",
 686                            I915_READ(VLV_IER));
 687                 seq_printf(m, "Display IIR:\t%08x\n",
 688                            I915_READ(VLV_IIR));
 689                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 690                            I915_READ(VLV_IIR_RW));
 691                 seq_printf(m, "Display IMR:\t%08x\n",
 692                            I915_READ(VLV_IMR));
 693                 for_each_pipe(dev_priv, pipe) {
 694                         enum intel_display_power_domain power_domain;
 695
 696                         power_domain = POWER_DOMAIN_PIPE(pipe);
 697                         if (!intel_display_power_get_if_enabled(dev_priv,
 698                                                                 power_domain)) {
 699                                 seq_printf(m, "Pipe %c power disabled\n",
 700                                            pipe_name(pipe));
 701                                 continue;
 702                         }
 703
 704                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 705                                    pipe_name(pipe),
 706                                    I915_READ(PIPESTAT(pipe)));
 707
 708                         intel_display_power_put(dev_priv, power_domain);
 709                 }
 710
 711                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 712                 seq_printf(m, "Port hotplug:\t%08x\n",
 713                            I915_READ(PORT_HOTPLUG_EN));
 714                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 715                            I915_READ(VLV_DPFLIPSTAT));
 716                 seq_printf(m, "DPINVGTT:\t%08x\n",
 717                            I915_READ(DPINVGTT));
 718                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 719
 720                 for (i = 0; i < 4; i++) {
 721                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 722                                    i, I915_READ(GEN8_GT_IMR(i)));
 723                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 724                                    i, I915_READ(GEN8_GT_IIR(i)));
 725                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 726                                    i, I915_READ(GEN8_GT_IER(i)));
 727                 }
 728
 729                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 730                            I915_READ(GEN8_PCU_IMR));
 731                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 732                            I915_READ(GEN8_PCU_IIR));
 733                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 734                            I915_READ(GEN8_PCU_IER));
 735         } else if (INTEL_GEN(dev_priv) >= 8) {
 736                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 737                            I915_READ(GEN8_MASTER_IRQ));
 738
 739                 for (i = 0; i < 4; i++) {
 740                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 741                                    i, I915_READ(GEN8_GT_IMR(i)));
 742                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 743                                    i, I915_READ(GEN8_GT_IIR(i)));
 744                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 745                                    i, I915_READ(GEN8_GT_IER(i)));
 746                 }
 747
 748                 for_each_pipe(dev_priv, pipe) {
 749                         enum intel_display_power_domain power_domain;
 750
 751                         power_domain = POWER_DOMAIN_PIPE(pipe);
 752                         if (!intel_display_power_get_if_enabled(dev_priv,
 753                                                                 power_domain)) {
 754                                 seq_printf(m, "Pipe %c power disabled\n",
 755                                            pipe_name(pipe));
 756                                 continue;
 757                         }
 758                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 759                                    pipe_name(pipe),
 760                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 761                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 762                                    pipe_name(pipe),
 763                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 764                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 765                                    pipe_name(pipe),
 766                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 767
 768                         intel_display_power_put(dev_priv, power_domain);
 769                 }
 770
 771                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 772                            I915_READ(GEN8_DE_PORT_IMR));
 773                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 774                            I915_READ(GEN8_DE_PORT_IIR));
 775                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 776                            I915_READ(GEN8_DE_PORT_IER));
 777
 778                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 779                            I915_READ(GEN8_DE_MISC_IMR));
 780                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 781                            I915_READ(GEN8_DE_MISC_IIR));
 782                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 783                            I915_READ(GEN8_DE_MISC_IER));
 784
 785                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 786                            I915_READ(GEN8_PCU_IMR));
 787                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 788                            I915_READ(GEN8_PCU_IIR));
 789                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 790                            I915_READ(GEN8_PCU_IER));
 791         } else if (IS_VALLEYVIEW(dev_priv)) {
 792                 seq_printf(m, "Display IER:\t%08x\n",
 793                            I915_READ(VLV_IER));
 794                 seq_printf(m, "Display IIR:\t%08x\n",
 795                            I915_READ(VLV_IIR));
 796                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 797                            I915_READ(VLV_IIR_RW));
 798                 seq_printf(m, "Display IMR:\t%08x\n",
 799                            I915_READ(VLV_IMR));
 800                 for_each_pipe(dev_priv, pipe) {
 801                         enum intel_display_power_domain power_domain;
 802
 803                         power_domain = POWER_DOMAIN_PIPE(pipe);
 804                         if (!intel_display_power_get_if_enabled(dev_priv,
 805                                                                 power_domain)) {
 806                                 seq_printf(m, "Pipe %c power disabled\n",
 807                                            pipe_name(pipe));
 808                                 continue;
 809                         }
 810
 811                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 812                                    pipe_name(pipe),
 813                                    I915_READ(PIPESTAT(pipe)));
 814                         intel_display_power_put(dev_priv, power_domain);
 815                 }
 816
 817                 seq_printf(m, "Master IER:\t%08x\n",
 818                            I915_READ(VLV_MASTER_IER));
 819
 820                 seq_printf(m, "Render IER:\t%08x\n",
 821                            I915_READ(GTIER));
 822                 seq_printf(m, "Render IIR:\t%08x\n",
 823                            I915_READ(GTIIR));
 824                 seq_printf(m, "Render IMR:\t%08x\n",
 825                            I915_READ(GTIMR));
 826
 827                 seq_printf(m, "PM IER:\t\t%08x\n",
 828                            I915_READ(GEN6_PMIER));
 829                 seq_printf(m, "PM IIR:\t\t%08x\n",
 830                            I915_READ(GEN6_PMIIR));
 831                 seq_printf(m, "PM IMR:\t\t%08x\n",
 832                            I915_READ(GEN6_PMIMR));
 833
 834                 seq_printf(m, "Port hotplug:\t%08x\n",
 835                            I915_READ(PORT_HOTPLUG_EN));
 836                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 837                            I915_READ(VLV_DPFLIPSTAT));
 838                 seq_printf(m, "DPINVGTT:\t%08x\n",
 839                            I915_READ(DPINVGTT));
 840
 841         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 842                 seq_printf(m, "Interrupt enable:    %08x\n",
 843                            I915_READ(IER));
 844                 seq_printf(m, "Interrupt identity:  %08x\n",
 845                            I915_READ(IIR));
 846                 seq_printf(m, "Interrupt mask:      %08x\n",
 847                            I915_READ(IMR));
 848                 for_each_pipe(dev_priv, pipe)
 849                         seq_printf(m, "Pipe %c stat:         %08x\n",
 850                                    pipe_name(pipe),
 851                                    I915_READ(PIPESTAT(pipe)));
 852         } else {
 853                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 854                            I915_READ(DEIER));
 855                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 856                            I915_READ(DEIIR));
 857                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 858                            I915_READ(DEIMR));
 859                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 860                            I915_READ(SDEIER));
 861                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 862                            I915_READ(SDEIIR));
 863                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 864                            I915_READ(SDEIMR));
 865                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 866                            I915_READ(GTIER));
 867                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 868                            I915_READ(GTIIR));
 869                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 870                            I915_READ(GTIMR));
 871         }
 872         for_each_engine(engine, dev_priv, id) {
 873                 if (INTEL_GEN(dev_priv) >= 6) {
 874                         seq_printf(m,
 875                                    "Graphics Interrupt mask (%s):       %08x\n",
 876                                    engine->name, I915_READ_IMR(engine));
 877                 }
 878                 i915_ring_seqno_info(m, engine);
 879         }
 880         intel_runtime_pm_put(dev_priv);
 881
 882         return 0;
 883 }
 884
 885 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 886 {
 887         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 888         struct drm_device *dev = &dev_priv->drm;
 889         int i, ret;
 890
 891         ret = mutex_lock_interruptible(&dev->struct_mutex);
 892         if (ret)
 893                 return ret;
 894
 895         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 896         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 897                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 898
 899                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 900                            i, dev_priv->fence_regs[i].pin_count);
 901                 if (!vma)
 902                         seq_puts(m, "unused");
 903                 else
 904                         describe_obj(m, vma->obj);
 905                 seq_putc(m, '\n');
 906         }
 907
 908         mutex_unlock(&dev->struct_mutex);
 909         return 0;
 910 }
 911
 912 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 913 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 914                               size_t count, loff_t *pos)
 915 {
 916         struct i915_gpu_state *error = file->private_data;
 917         struct drm_i915_error_state_buf str;
 918         ssize_t ret;
 919         loff_t tmp;
 920
 921         if (!error)
 922                 return 0;
 923
 924         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 925         if (ret)
 926                 return ret;
 927
 928         ret = i915_error_state_to_str(&str, error);
 929         if (ret)
 930                 goto out;
 931
 932         tmp = 0;
 933         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 934         if (ret < 0)
 935                 goto out;
 936
 937         *pos = str.start + ret;
 938 out:
 939         i915_error_state_buf_release(&str);
 940         return ret;
 941 }
 942
 943 static int gpu_state_release(struct inode *inode, struct file *file)
 944 {
 945         i915_gpu_state_put(file->private_data);
 946         return 0;
 947 }
 948
 949 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 950 {
 951         struct drm_i915_private *i915 = inode->i_private;
 952         struct i915_gpu_state *gpu;
 953
 954         intel_runtime_pm_get(i915);
 955         gpu = i915_capture_gpu_state(i915);
 956         intel_runtime_pm_put(i915);
 957         if (!gpu)
 958                 return -ENOMEM;
 959
 960         file->private_data = gpu;
 961         return 0;
 962 }
 963
 964 static const struct file_operations i915_gpu_info_fops = {
 965         .owner = THIS_MODULE,
 966         .open = i915_gpu_info_open,
 967         .read = gpu_state_read,
 968         .llseek = default_llseek,
 969         .release = gpu_state_release,
 970 };
 971
 972 static ssize_t
 973 i915_error_state_write(struct file *filp,
 974                        const char __user *ubuf,
 975                        size_t cnt,
 976                        loff_t *ppos)
 977 {
 978         struct i915_gpu_state *error = filp->private_data;
 979
 980         if (!error)
 981                 return 0;
 982
 983         DRM_DEBUG_DRIVER("Resetting error state\n");
 984         i915_reset_error_state(error->i915);
 985
 986         return cnt;
 987 }
 988
 989 static int i915_error_state_open(struct inode *inode, struct file *file)
 990 {
 991         file->private_data = i915_first_error_state(inode->i_private);
 992         return 0;
 993 }
 994
 995 static const struct file_operations i915_error_state_fops = {
 996         .owner = THIS_MODULE,
 997         .open = i915_error_state_open,
 998         .read = gpu_state_read,
 999         .write = i915_error_state_write,
1000         .llseek = default_llseek,
1001         .release = gpu_state_release,
1002 };
1003 #endif
1004
1005 static int
1006 i915_next_seqno_set(void *data, u64 val)
1007 {
1008         struct drm_i915_private *dev_priv = data;
1009         struct drm_device *dev = &dev_priv->drm;
1010         int ret;
1011
1012         ret = mutex_lock_interruptible(&dev->struct_mutex);
1013         if (ret)
1014                 return ret;
1015
1016         ret = i915_gem_set_global_seqno(dev, val);
1017         mutex_unlock(&dev->struct_mutex);
1018
1019         return ret;
1020 }
1021
1022 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1023                         NULL, i915_next_seqno_set,
1024                         "0x%llx\n");
1025
1026 static int i915_frequency_info(struct seq_file *m, void *unused)
1027 {
1028         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1029         int ret = 0;
1030
1031         intel_runtime_pm_get(dev_priv);
1032
1033         if (IS_GEN5(dev_priv)) {
1034                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1035                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1036
1037                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1038                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1039                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1040                            MEMSTAT_VID_SHIFT);
1041                 seq_printf(m, "Current P-state: %d\n",
1042                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1043         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1044                 u32 freq_sts;
1045
1046                 mutex_lock(&dev_priv->rps.hw_lock);
1047                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1048                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1049                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1050
1051                 seq_printf(m, "actual GPU freq: %d MHz\n",
1052                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1053
1054                 seq_printf(m, "current GPU freq: %d MHz\n",
1055                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1056
1057                 seq_printf(m, "max GPU freq: %d MHz\n",
1058                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1059
1060                 seq_printf(m, "min GPU freq: %d MHz\n",
1061                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1062
1063                 seq_printf(m, "idle GPU freq: %d MHz\n",
1064                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1065
1066                 seq_printf(m,
1067                            "efficient (RPe) frequency: %d MHz\n",
1068                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1069                 mutex_unlock(&dev_priv->rps.hw_lock);
1070         } else if (INTEL_GEN(dev_priv) >= 6) {
1071                 u32 rp_state_limits;
1072                 u32 gt_perf_status;
1073                 u32 rp_state_cap;
1074                 u32 rpmodectl, rpinclimit, rpdeclimit;
1075                 u32 rpstat, cagf, reqf;
1076                 u32 rpupei, rpcurup, rpprevup;
1077                 u32 rpdownei, rpcurdown, rpprevdown;
1078                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1079                 int max_freq;
1080
1081                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1082                 if (IS_GEN9_LP(dev_priv)) {
1083                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1084                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1085                 } else {
1086                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1087                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1088                 }
1089
1090                 /* RPSTAT1 is in the GT power well */
1091                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1092
1093                 reqf = I915_READ(GEN6_RPNSWREQ);
1094                 if (INTEL_GEN(dev_priv) >= 9)
1095                         reqf >>= 23;
1096                 else {
1097                         reqf &= ~GEN6_TURBO_DISABLE;
1098                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1099                                 reqf >>= 24;
1100                         else
1101                                 reqf >>= 25;
1102                 }
1103                 reqf = intel_gpu_freq(dev_priv, reqf);
1104
1105                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1106                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1107                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1108
1109                 rpstat = I915_READ(GEN6_RPSTAT1);
1110                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1111                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1112                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1113                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1114                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1115                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1116                 if (INTEL_GEN(dev_priv) >= 9)
1117                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1118                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1119                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1120                 else
1121                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1122                 cagf = intel_gpu_freq(dev_priv, cagf);
1123
1124                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1125
1126                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1127                         pm_ier = I915_READ(GEN6_PMIER);
1128                         pm_imr = I915_READ(GEN6_PMIMR);
1129                         pm_isr = I915_READ(GEN6_PMISR);
1130                         pm_iir = I915_READ(GEN6_PMIIR);
1131                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1132                 } else {
1133                         pm_ier = I915_READ(GEN8_GT_IER(2));
1134                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1135                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1136                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1137                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1138                 }
1139                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1140                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1141                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1142                            dev_priv->rps.pm_intrmsk_mbz);
1143                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1144                 seq_printf(m, "Render p-state ratio: %d\n",
1145                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1146                 seq_printf(m, "Render p-state VID: %d\n",
1147                            gt_perf_status & 0xff);
1148                 seq_printf(m, "Render p-state limit: %d\n",
1149                            rp_state_limits & 0xff);
1150                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1151                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1152                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1153                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1154                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1155                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1156                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1157                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1158                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1159                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1160                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1161                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1162                 seq_printf(m, "Up threshold: %d%%\n",
1163                            dev_priv->rps.up_threshold);
1164
1165                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1166                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1167                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1168                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1169                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1170                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1171                 seq_printf(m, "Down threshold: %d%%\n",
1172                            dev_priv->rps.down_threshold);
1173
1174                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1175                             rp_state_cap >> 16) & 0xff;
1176                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1177                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1178                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1179                            intel_gpu_freq(dev_priv, max_freq));
1180
1181                 max_freq = (rp_state_cap & 0xff00) >> 8;
1182                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1183                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            intel_gpu_freq(dev_priv, max_freq));
1186
1187                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1188                             rp_state_cap >> 0) & 0xff;
1189                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1190                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1191                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1192                            intel_gpu_freq(dev_priv, max_freq));
1193                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1194                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1195
1196                 seq_printf(m, "Current freq: %d MHz\n",
1197                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1198                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1199                 seq_printf(m, "Idle freq: %d MHz\n",
1200                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1201                 seq_printf(m, "Min freq: %d MHz\n",
1202                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1203                 seq_printf(m, "Boost freq: %d MHz\n",
1204                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1205                 seq_printf(m, "Max freq: %d MHz\n",
1206                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1207                 seq_printf(m,
1208                            "efficient (RPe) frequency: %d MHz\n",
1209                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1210         } else {
1211                 seq_puts(m, "no P-state info available\n");
1212         }
1213
1214         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1215         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1216         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1217
1218         intel_runtime_pm_put(dev_priv);
1219         return ret;
1220 }
1221
1222 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1223                                struct seq_file *m,
1224                                struct intel_instdone *instdone)
1225 {
1226         int slice;
1227         int subslice;
1228
1229         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1230                    instdone->instdone);
1231
1232         if (INTEL_GEN(dev_priv) <= 3)
1233                 return;
1234
1235         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1236                    instdone->slice_common);
1237
1238         if (INTEL_GEN(dev_priv) <= 6)
1239                 return;
1240
1241         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1242                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1243                            slice, subslice, instdone->sampler[slice][subslice]);
1244
1245         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1246                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1247                            slice, subslice, instdone->row[slice][subslice]);
1248 }
1249
1250 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1251 {
1252         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1253         struct intel_engine_cs *engine;
1254         u64 acthd[I915_NUM_ENGINES];
1255         u32 seqno[I915_NUM_ENGINES];
1256         struct intel_instdone instdone;
1257         enum intel_engine_id id;
1258
1259         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1260                 seq_puts(m, "Wedged\n");
1261         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1262                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1263         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1264                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1265         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1266                 seq_puts(m, "Waiter holding struct mutex\n");
1267         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1268                 seq_puts(m, "struct_mutex blocked for reset\n");
1269
1270         if (!i915_modparams.enable_hangcheck) {
1271                 seq_puts(m, "Hangcheck disabled\n");
1272                 return 0;
1273         }
1274
1275         intel_runtime_pm_get(dev_priv);
1276
1277         for_each_engine(engine, dev_priv, id) {
1278                 acthd[id] = intel_engine_get_active_head(engine);
1279                 seqno[id] = intel_engine_get_seqno(engine);
1280         }
1281
1282         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1283
1284         intel_runtime_pm_put(dev_priv);
1285
1286         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1287                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1288                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1289                                             jiffies));
1290         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1291                 seq_puts(m, "Hangcheck active, work pending\n");
1292         else
1293                 seq_puts(m, "Hangcheck inactive\n");
1294
1295         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1296
1297         for_each_engine(engine, dev_priv, id) {
1298                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1299                 struct rb_node *rb;
1300
1301                 seq_printf(m, "%s:\n", engine->name);
1302                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1303                            engine->hangcheck.seqno, seqno[id],
1304                            intel_engine_last_submit(engine),
1305                            engine->timeline->inflight_seqnos);
1306                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1307                            yesno(intel_engine_has_waiter(engine)),
1308                            yesno(test_bit(engine->id,
1309                                           &dev_priv->gpu_error.missed_irq_rings)),
1310                            yesno(engine->hangcheck.stalled));
1311
1312                 spin_lock_irq(&b->rb_lock);
1313                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1314                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1315
1316                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1317                                    w->tsk->comm, w->tsk->pid, w->seqno);
1318                 }
1319                 spin_unlock_irq(&b->rb_lock);
1320
1321                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1322                            (long long)engine->hangcheck.acthd,
1323                            (long long)acthd[id]);
1324                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1325                            hangcheck_action_to_str(engine->hangcheck.action),
1326                            engine->hangcheck.action,
1327                            jiffies_to_msecs(jiffies -
1328                                             engine->hangcheck.action_timestamp));
1329
1330                 if (engine->id == RCS) {
1331                         seq_puts(m, "\tinstdone read =\n");
1332
1333                         i915_instdone_info(dev_priv, m, &instdone);
1334
1335                         seq_puts(m, "\tinstdone accu =\n");
1336
1337                         i915_instdone_info(dev_priv, m,
1338                                            &engine->hangcheck.instdone);
1339                 }
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int i915_reset_info(struct seq_file *m, void *unused)
1346 {
1347         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1348         struct i915_gpu_error *error = &dev_priv->gpu_error;
1349         struct intel_engine_cs *engine;
1350         enum intel_engine_id id;
1351
1352         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1353
1354         for_each_engine(engine, dev_priv, id) {
1355                 seq_printf(m, "%s = %u\n", engine->name,
1356                            i915_reset_engine_count(error, engine));
1357         }
1358
1359         return 0;
1360 }
1361
1362 static int ironlake_drpc_info(struct seq_file *m)
1363 {
1364         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1365         u32 rgvmodectl, rstdbyctl;
1366         u16 crstandvid;
1367
1368         rgvmodectl = I915_READ(MEMMODECTL);
1369         rstdbyctl = I915_READ(RSTDBYCTL);
1370         crstandvid = I915_READ16(CRSTANDVID);
1371
1372         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1373         seq_printf(m, "Boost freq: %d\n",
1374                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1375                    MEMMODE_BOOST_FREQ_SHIFT);
1376         seq_printf(m, "HW control enabled: %s\n",
1377                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1378         seq_printf(m, "SW control enabled: %s\n",
1379                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1380         seq_printf(m, "Gated voltage change: %s\n",
1381                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1382         seq_printf(m, "Starting frequency: P%d\n",
1383                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1384         seq_printf(m, "Max P-state: P%d\n",
1385                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1386         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1387         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1388         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1389         seq_printf(m, "Render standby enabled: %s\n",
1390                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1391         seq_puts(m, "Current RS state: ");
1392         switch (rstdbyctl & RSX_STATUS_MASK) {
1393         case RSX_STATUS_ON:
1394                 seq_puts(m, "on\n");
1395                 break;
1396         case RSX_STATUS_RC1:
1397                 seq_puts(m, "RC1\n");
1398                 break;
1399         case RSX_STATUS_RC1E:
1400                 seq_puts(m, "RC1E\n");
1401                 break;
1402         case RSX_STATUS_RS1:
1403                 seq_puts(m, "RS1\n");
1404                 break;
1405         case RSX_STATUS_RS2:
1406                 seq_puts(m, "RS2 (RC6)\n");
1407                 break;
1408         case RSX_STATUS_RS3:
1409                 seq_puts(m, "RC3 (RC6+)\n");
1410                 break;
1411         default:
1412                 seq_puts(m, "unknown\n");
1413                 break;
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int i915_forcewake_domains(struct seq_file *m, void *data)
1420 {
1421         struct drm_i915_private *i915 = node_to_i915(m->private);
1422         struct intel_uncore_forcewake_domain *fw_domain;
1423         unsigned int tmp;
1424
1425         seq_printf(m, "user.bypass_count = %u\n",
1426                    i915->uncore.user_forcewake.count);
1427
1428         for_each_fw_domain(fw_domain, i915, tmp)
1429                 seq_printf(m, "%s.wake_count = %u\n",
1430                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1431                            READ_ONCE(fw_domain->wake_count));
1432
1433         return 0;
1434 }
1435
1436 static void print_rc6_res(struct seq_file *m,
1437                           const char *title,
1438                           const i915_reg_t reg)
1439 {
1440         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1441
1442         seq_printf(m, "%s %u (%llu us)\n",
1443                    title, I915_READ(reg),
1444                    intel_rc6_residency_us(dev_priv, reg));
1445 }
1446
1447 static int vlv_drpc_info(struct seq_file *m)
1448 {
1449         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1450         u32 rpmodectl1, rcctl1, pw_status;
1451
1452         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1453         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1454         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1455
1456         seq_printf(m, "Video Turbo Mode: %s\n",
1457                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1458         seq_printf(m, "Turbo enabled: %s\n",
1459                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1460         seq_printf(m, "HW control enabled: %s\n",
1461                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1462         seq_printf(m, "SW control enabled: %s\n",
1463                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1464                           GEN6_RP_MEDIA_SW_MODE));
1465         seq_printf(m, "RC6 Enabled: %s\n",
1466                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1467                                         GEN6_RC_CTL_EI_MODE(1))));
1468         seq_printf(m, "Render Power Well: %s\n",
1469                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1470         seq_printf(m, "Media Power Well: %s\n",
1471                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1472
1473         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1474         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1475
1476         return i915_forcewake_domains(m, NULL);
1477 }
1478
1479 static int gen6_drpc_info(struct seq_file *m)
1480 {
1481         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1482         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1483         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1484         unsigned forcewake_count;
1485         int count = 0;
1486
1487         forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1488         if (forcewake_count) {
1489                 seq_puts(m, "RC information inaccurate because somebody "
1490                             "holds a forcewake reference \n");
1491         } else {
1492                 /* NB: we cannot use forcewake, else we read the wrong values */
1493                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1494                         udelay(10);
1495                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1496         }
1497
1498         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1499         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1500
1501         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1502         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1503         if (INTEL_GEN(dev_priv) >= 9) {
1504                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1505                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1506         }
1507
1508         mutex_lock(&dev_priv->rps.hw_lock);
1509         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1510         mutex_unlock(&dev_priv->rps.hw_lock);
1511
1512         seq_printf(m, "Video Turbo Mode: %s\n",
1513                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1514         seq_printf(m, "HW control enabled: %s\n",
1515                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1516         seq_printf(m, "SW control enabled: %s\n",
1517                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1518                           GEN6_RP_MEDIA_SW_MODE));
1519         seq_printf(m, "RC1e Enabled: %s\n",
1520                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1521         seq_printf(m, "RC6 Enabled: %s\n",
1522                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1523         if (INTEL_GEN(dev_priv) >= 9) {
1524                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1525                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1526                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1527                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1528         }
1529         seq_printf(m, "Deep RC6 Enabled: %s\n",
1530                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1531         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1532                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1533         seq_puts(m, "Current RC state: ");
1534         switch (gt_core_status & GEN6_RCn_MASK) {
1535         case GEN6_RC0:
1536                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1537                         seq_puts(m, "Core Power Down\n");
1538                 else
1539                         seq_puts(m, "on\n");
1540                 break;
1541         case GEN6_RC3:
1542                 seq_puts(m, "RC3\n");
1543                 break;
1544         case GEN6_RC6:
1545                 seq_puts(m, "RC6\n");
1546                 break;
1547         case GEN6_RC7:
1548                 seq_puts(m, "RC7\n");
1549                 break;
1550         default:
1551                 seq_puts(m, "Unknown\n");
1552                 break;
1553         }
1554
1555         seq_printf(m, "Core Power Down: %s\n",
1556                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1557         if (INTEL_GEN(dev_priv) >= 9) {
1558                 seq_printf(m, "Render Power Well: %s\n",
1559                         (gen9_powergate_status &
1560                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1561                 seq_printf(m, "Media Power Well: %s\n",
1562                         (gen9_powergate_status &
1563                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1564         }
1565
1566         /* Not exactly sure what this is */
1567         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1568                       GEN6_GT_GFX_RC6_LOCKED);
1569         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1570         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1571         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1572
1573         seq_printf(m, "RC6   voltage: %dmV\n",
1574                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1575         seq_printf(m, "RC6+  voltage: %dmV\n",
1576                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1577         seq_printf(m, "RC6++ voltage: %dmV\n",
1578                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1579         return i915_forcewake_domains(m, NULL);
1580 }
1581
1582 static int i915_drpc_info(struct seq_file *m, void *unused)
1583 {
1584         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1585         int err;
1586
1587         intel_runtime_pm_get(dev_priv);
1588
1589         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1590                 err = vlv_drpc_info(m);
1591         else if (INTEL_GEN(dev_priv) >= 6)
1592                 err = gen6_drpc_info(m);
1593         else
1594                 err = ironlake_drpc_info(m);
1595
1596         intel_runtime_pm_put(dev_priv);
1597
1598         return err;
1599 }
1600
1601 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1602 {
1603         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1604
1605         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1606                    dev_priv->fb_tracking.busy_bits);
1607
1608         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1609                    dev_priv->fb_tracking.flip_bits);
1610
1611         return 0;
1612 }
1613
1614 static int i915_fbc_status(struct seq_file *m, void *unused)
1615 {
1616         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1617
1618         if (!HAS_FBC(dev_priv)) {
1619                 seq_puts(m, "FBC unsupported on this chipset\n");
1620                 return 0;
1621         }
1622
1623         intel_runtime_pm_get(dev_priv);
1624         mutex_lock(&dev_priv->fbc.lock);
1625
1626         if (intel_fbc_is_active(dev_priv))
1627                 seq_puts(m, "FBC enabled\n");
1628         else
1629                 seq_printf(m, "FBC disabled: %s\n",
1630                            dev_priv->fbc.no_fbc_reason);
1631
1632         if (intel_fbc_is_active(dev_priv)) {
1633                 u32 mask;
1634
1635                 if (INTEL_GEN(dev_priv) >= 8)
1636                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1637                 else if (INTEL_GEN(dev_priv) >= 7)
1638                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1639                 else if (INTEL_GEN(dev_priv) >= 5)
1640                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1641                 else if (IS_G4X(dev_priv))
1642                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1643                 else
1644                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1645                                                         FBC_STAT_COMPRESSED);
1646
1647                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1648         }
1649
1650         mutex_unlock(&dev_priv->fbc.lock);
1651         intel_runtime_pm_put(dev_priv);
1652
1653         return 0;
1654 }
1655
1656 static int i915_fbc_false_color_get(void *data, u64 *val)
1657 {
1658         struct drm_i915_private *dev_priv = data;
1659
1660         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1661                 return -ENODEV;
1662
1663         *val = dev_priv->fbc.false_color;
1664
1665         return 0;
1666 }
1667
1668 static int i915_fbc_false_color_set(void *data, u64 val)
1669 {
1670         struct drm_i915_private *dev_priv = data;
1671         u32 reg;
1672
1673         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1674                 return -ENODEV;
1675
1676         mutex_lock(&dev_priv->fbc.lock);
1677
1678         reg = I915_READ(ILK_DPFC_CONTROL);
1679         dev_priv->fbc.false_color = val;
1680
1681         I915_WRITE(ILK_DPFC_CONTROL, val ?
1682                    (reg | FBC_CTL_FALSE_COLOR) :
1683                    (reg & ~FBC_CTL_FALSE_COLOR));
1684
1685         mutex_unlock(&dev_priv->fbc.lock);
1686         return 0;
1687 }
1688
1689 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1690                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1691                         "%llu\n");
1692
1693 static int i915_ips_status(struct seq_file *m, void *unused)
1694 {
1695         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1696
1697         if (!HAS_IPS(dev_priv)) {
1698                 seq_puts(m, "not supported\n");
1699                 return 0;
1700         }
1701
1702         intel_runtime_pm_get(dev_priv);
1703
1704         seq_printf(m, "Enabled by kernel parameter: %s\n",
1705                    yesno(i915_modparams.enable_ips));
1706
1707         if (INTEL_GEN(dev_priv) >= 8) {
1708                 seq_puts(m, "Currently: unknown\n");
1709         } else {
1710                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1711                         seq_puts(m, "Currently: enabled\n");
1712                 else
1713                         seq_puts(m, "Currently: disabled\n");
1714         }
1715
1716         intel_runtime_pm_put(dev_priv);
1717
1718         return 0;
1719 }
1720
1721 static int i915_sr_status(struct seq_file *m, void *unused)
1722 {
1723         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1724         bool sr_enabled = false;
1725
1726         intel_runtime_pm_get(dev_priv);
1727         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1728
1729         if (INTEL_GEN(dev_priv) >= 9)
1730                 /* no global SR status; inspect per-plane WM */;
1731         else if (HAS_PCH_SPLIT(dev_priv))
1732                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1733         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1734                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1735                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1736         else if (IS_I915GM(dev_priv))
1737                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1738         else if (IS_PINEVIEW(dev_priv))
1739                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1740         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1741                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1742
1743         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1744         intel_runtime_pm_put(dev_priv);
1745
1746         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1747
1748         return 0;
1749 }
1750
1751 static int i915_emon_status(struct seq_file *m, void *unused)
1752 {
1753         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1754         struct drm_device *dev = &dev_priv->drm;
1755         unsigned long temp, chipset, gfx;
1756         int ret;
1757
1758         if (!IS_GEN5(dev_priv))
1759                 return -ENODEV;
1760
1761         ret = mutex_lock_interruptible(&dev->struct_mutex);
1762         if (ret)
1763                 return ret;
1764
1765         temp = i915_mch_val(dev_priv);
1766         chipset = i915_chipset_val(dev_priv);
1767         gfx = i915_gfx_val(dev_priv);
1768         mutex_unlock(&dev->struct_mutex);
1769
1770         seq_printf(m, "GMCH temp: %ld\n", temp);
1771         seq_printf(m, "Chipset power: %ld\n", chipset);
1772         seq_printf(m, "GFX power: %ld\n", gfx);
1773         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1774
1775         return 0;
1776 }
1777
1778 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1779 {
1780         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1781         int ret = 0;
1782         int gpu_freq, ia_freq;
1783         unsigned int max_gpu_freq, min_gpu_freq;
1784
1785         if (!HAS_LLC(dev_priv)) {
1786                 seq_puts(m, "unsupported on this chipset\n");
1787                 return 0;
1788         }
1789
1790         intel_runtime_pm_get(dev_priv);
1791
1792         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1793         if (ret)
1794                 goto out;
1795
1796         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1797                 /* Convert GT frequency to 50 HZ units */
1798                 min_gpu_freq =
1799                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1800                 max_gpu_freq =
1801                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1802         } else {
1803                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1804                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1805         }
1806
1807         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1808
1809         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1810                 ia_freq = gpu_freq;
1811                 sandybridge_pcode_read(dev_priv,
1812                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1813                                        &ia_freq);
1814                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1815                            intel_gpu_freq(dev_priv, (gpu_freq *
1816                                                      (IS_GEN9_BC(dev_priv) ||
1817                                                       IS_CANNONLAKE(dev_priv) ?
1818                                                       GEN9_FREQ_SCALER : 1))),
1819                            ((ia_freq >> 0) & 0xff) * 100,
1820                            ((ia_freq >> 8) & 0xff) * 100);
1821         }
1822
1823         mutex_unlock(&dev_priv->rps.hw_lock);
1824
1825 out:
1826         intel_runtime_pm_put(dev_priv);
1827         return ret;
1828 }
1829
1830 static int i915_opregion(struct seq_file *m, void *unused)
1831 {
1832         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1833         struct drm_device *dev = &dev_priv->drm;
1834         struct intel_opregion *opregion = &dev_priv->opregion;
1835         int ret;
1836
1837         ret = mutex_lock_interruptible(&dev->struct_mutex);
1838         if (ret)
1839                 goto out;
1840
1841         if (opregion->header)
1842                 seq_write(m, opregion->header, OPREGION_SIZE);
1843
1844         mutex_unlock(&dev->struct_mutex);
1845
1846 out:
1847         return 0;
1848 }
1849
1850 static int i915_vbt(struct seq_file *m, void *unused)
1851 {
1852         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1853
1854         if (opregion->vbt)
1855                 seq_write(m, opregion->vbt, opregion->vbt_size);
1856
1857         return 0;
1858 }
1859
1860 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1861 {
1862         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1863         struct drm_device *dev = &dev_priv->drm;
1864         struct intel_framebuffer *fbdev_fb = NULL;
1865         struct drm_framebuffer *drm_fb;
1866         int ret;
1867
1868         ret = mutex_lock_interruptible(&dev->struct_mutex);
1869         if (ret)
1870                 return ret;
1871
1872 #ifdef CONFIG_DRM_FBDEV_EMULATION
1873         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1874                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1875
1876                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1877                            fbdev_fb->base.width,
1878                            fbdev_fb->base.height,
1879                            fbdev_fb->base.format->depth,
1880                            fbdev_fb->base.format->cpp[0] * 8,
1881                            fbdev_fb->base.modifier,
1882                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1883                 describe_obj(m, fbdev_fb->obj);
1884                 seq_putc(m, '\n');
1885         }
1886 #endif
1887
1888         mutex_lock(&dev->mode_config.fb_lock);
1889         drm_for_each_fb(drm_fb, dev) {
1890                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1891                 if (fb == fbdev_fb)
1892                         continue;
1893
1894                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1895                            fb->base.width,
1896                            fb->base.height,
1897                            fb->base.format->depth,
1898                            fb->base.format->cpp[0] * 8,
1899                            fb->base.modifier,
1900                            drm_framebuffer_read_refcount(&fb->base));
1901                 describe_obj(m, fb->obj);
1902                 seq_putc(m, '\n');
1903         }
1904         mutex_unlock(&dev->mode_config.fb_lock);
1905         mutex_unlock(&dev->struct_mutex);
1906
1907         return 0;
1908 }
1909
1910 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1911 {
1912         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1913                    ring->space, ring->head, ring->tail);
1914 }
1915
1916 static int i915_context_status(struct seq_file *m, void *unused)
1917 {
1918         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1919         struct drm_device *dev = &dev_priv->drm;
1920         struct intel_engine_cs *engine;
1921         struct i915_gem_context *ctx;
1922         enum intel_engine_id id;
1923         int ret;
1924
1925         ret = mutex_lock_interruptible(&dev->struct_mutex);
1926         if (ret)
1927                 return ret;
1928
1929         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1930                 seq_printf(m, "HW context %u ", ctx->hw_id);
1931                 if (ctx->pid) {
1932                         struct task_struct *task;
1933
1934                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1935                         if (task) {
1936                                 seq_printf(m, "(%s [%d]) ",
1937                                            task->comm, task->pid);
1938                                 put_task_struct(task);
1939                         }
1940                 } else if (IS_ERR(ctx->file_priv)) {
1941                         seq_puts(m, "(deleted) ");
1942                 } else {
1943                         seq_puts(m, "(kernel) ");
1944                 }
1945
1946                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1947                 seq_putc(m, '\n');
1948
1949                 for_each_engine(engine, dev_priv, id) {
1950                         struct intel_context *ce = &ctx->engine[engine->id];
1951
1952                         seq_printf(m, "%s: ", engine->name);
1953                         seq_putc(m, ce->initialised ? 'I' : 'i');
1954                         if (ce->state)
1955                                 describe_obj(m, ce->state->obj);
1956                         if (ce->ring)
1957                                 describe_ctx_ring(m, ce->ring);
1958                         seq_putc(m, '\n');
1959                 }
1960
1961                 seq_putc(m, '\n');
1962         }
1963
1964         mutex_unlock(&dev->struct_mutex);
1965
1966         return 0;
1967 }
1968
1969 static void i915_dump_lrc_obj(struct seq_file *m,
1970                               struct i915_gem_context *ctx,
1971                               struct intel_engine_cs *engine)
1972 {
1973         struct i915_vma *vma = ctx->engine[engine->id].state;
1974         struct page *page;
1975         int j;
1976
1977         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1978
1979         if (!vma) {
1980                 seq_puts(m, "\tFake context\n");
1981                 return;
1982         }
1983
1984         if (vma->flags & I915_VMA_GLOBAL_BIND)
1985                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1986                            i915_ggtt_offset(vma));
1987
1988         if (i915_gem_object_pin_pages(vma->obj)) {
1989                 seq_puts(m, "\tFailed to get pages for context object\n\n");
1990                 return;
1991         }
1992
1993         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1994         if (page) {
1995                 u32 *reg_state = kmap_atomic(page);
1996
1997                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1998                         seq_printf(m,
1999                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2000                                    j * 4,
2001                                    reg_state[j], reg_state[j + 1],
2002                                    reg_state[j + 2], reg_state[j + 3]);
2003                 }
2004                 kunmap_atomic(reg_state);
2005         }
2006
2007         i915_gem_object_unpin_pages(vma->obj);
2008         seq_putc(m, '\n');
2009 }
2010
2011 static int i915_dump_lrc(struct seq_file *m, void *unused)
2012 {
2013         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2014         struct drm_device *dev = &dev_priv->drm;
2015         struct intel_engine_cs *engine;
2016         struct i915_gem_context *ctx;
2017         enum intel_engine_id id;
2018         int ret;
2019
2020         if (!i915_modparams.enable_execlists) {
2021                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2022                 return 0;
2023         }
2024
2025         ret = mutex_lock_interruptible(&dev->struct_mutex);
2026         if (ret)
2027                 return ret;
2028
2029         list_for_each_entry(ctx, &dev_priv->contexts.list, link)
2030                 for_each_engine(engine, dev_priv, id)
2031                         i915_dump_lrc_obj(m, ctx, engine);
2032
2033         mutex_unlock(&dev->struct_mutex);
2034
2035         return 0;
2036 }
2037
2038 static const char *swizzle_string(unsigned swizzle)
2039 {
2040         switch (swizzle) {
2041         case I915_BIT_6_SWIZZLE_NONE:
2042                 return "none";
2043         case I915_BIT_6_SWIZZLE_9:
2044                 return "bit9";
2045         case I915_BIT_6_SWIZZLE_9_10:
2046                 return "bit9/bit10";
2047         case I915_BIT_6_SWIZZLE_9_11:
2048                 return "bit9/bit11";
2049         case I915_BIT_6_SWIZZLE_9_10_11:
2050                 return "bit9/bit10/bit11";
2051         case I915_BIT_6_SWIZZLE_9_17:
2052                 return "bit9/bit17";
2053         case I915_BIT_6_SWIZZLE_9_10_17:
2054                 return "bit9/bit10/bit17";
2055         case I915_BIT_6_SWIZZLE_UNKNOWN:
2056                 return "unknown";
2057         }
2058
2059         return "bug";
2060 }
2061
2062 static int i915_swizzle_info(struct seq_file *m, void *data)
2063 {
2064         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2065
2066         intel_runtime_pm_get(dev_priv);
2067
2068         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2069                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2070         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2071                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2072
2073         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2074                 seq_printf(m, "DDC = 0x%08x\n",
2075                            I915_READ(DCC));
2076                 seq_printf(m, "DDC2 = 0x%08x\n",
2077                            I915_READ(DCC2));
2078                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2079                            I915_READ16(C0DRB3));
2080                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2081                            I915_READ16(C1DRB3));
2082         } else if (INTEL_GEN(dev_priv) >= 6) {
2083                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2084                            I915_READ(MAD_DIMM_C0));
2085                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2086                            I915_READ(MAD_DIMM_C1));
2087                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2088                            I915_READ(MAD_DIMM_C2));
2089                 seq_printf(m, "TILECTL = 0x%08x\n",
2090                            I915_READ(TILECTL));
2091                 if (INTEL_GEN(dev_priv) >= 8)
2092                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2093                                    I915_READ(GAMTARBMODE));
2094                 else
2095                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2096                                    I915_READ(ARB_MODE));
2097                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2098                            I915_READ(DISP_ARB_CTL));
2099         }
2100
2101         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2102                 seq_puts(m, "L-shaped memory detected\n");
2103
2104         intel_runtime_pm_put(dev_priv);
2105
2106         return 0;
2107 }
2108
2109 static int per_file_ctx(int id, void *ptr, void *data)
2110 {
2111         struct i915_gem_context *ctx = ptr;
2112         struct seq_file *m = data;
2113         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2114
2115         if (!ppgtt) {
2116                 seq_printf(m, "  no ppgtt for context %d\n",
2117                            ctx->user_handle);
2118                 return 0;
2119         }
2120
2121         if (i915_gem_context_is_default(ctx))
2122                 seq_puts(m, "  default context:\n");
2123         else
2124                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2125         ppgtt->debug_dump(ppgtt, m);
2126
2127         return 0;
2128 }
2129
2130 static void gen8_ppgtt_info(struct seq_file *m,
2131                             struct drm_i915_private *dev_priv)
2132 {
2133         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2134         struct intel_engine_cs *engine;
2135         enum intel_engine_id id;
2136         int i;
2137
2138         if (!ppgtt)
2139                 return;
2140
2141         for_each_engine(engine, dev_priv, id) {
2142                 seq_printf(m, "%s\n", engine->name);
2143                 for (i = 0; i < 4; i++) {
2144                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2145                         pdp <<= 32;
2146                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2147                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2148                 }
2149         }
2150 }
2151
2152 static void gen6_ppgtt_info(struct seq_file *m,
2153                             struct drm_i915_private *dev_priv)
2154 {
2155         struct intel_engine_cs *engine;
2156         enum intel_engine_id id;
2157
2158         if (IS_GEN6(dev_priv))
2159                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2160
2161         for_each_engine(engine, dev_priv, id) {
2162                 seq_printf(m, "%s\n", engine->name);
2163                 if (IS_GEN7(dev_priv))
2164                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2165                                    I915_READ(RING_MODE_GEN7(engine)));
2166                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2167                            I915_READ(RING_PP_DIR_BASE(engine)));
2168                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2169                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2170                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2171                            I915_READ(RING_PP_DIR_DCLV(engine)));
2172         }
2173         if (dev_priv->mm.aliasing_ppgtt) {
2174                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2175
2176                 seq_puts(m, "aliasing PPGTT:\n");
2177                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2178
2179                 ppgtt->debug_dump(ppgtt, m);
2180         }
2181
2182         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2183 }
2184
2185 static int i915_ppgtt_info(struct seq_file *m, void *data)
2186 {
2187         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2188         struct drm_device *dev = &dev_priv->drm;
2189         struct drm_file *file;
2190         int ret;
2191
2192         mutex_lock(&dev->filelist_mutex);
2193         ret = mutex_lock_interruptible(&dev->struct_mutex);
2194         if (ret)
2195                 goto out_unlock;
2196
2197         intel_runtime_pm_get(dev_priv);
2198
2199         if (INTEL_GEN(dev_priv) >= 8)
2200                 gen8_ppgtt_info(m, dev_priv);
2201         else if (INTEL_GEN(dev_priv) >= 6)
2202                 gen6_ppgtt_info(m, dev_priv);
2203
2204         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2205                 struct drm_i915_file_private *file_priv = file->driver_priv;
2206                 struct task_struct *task;
2207
2208                 task = get_pid_task(file->pid, PIDTYPE_PID);
2209                 if (!task) {
2210                         ret = -ESRCH;
2211                         goto out_rpm;
2212                 }
2213                 seq_printf(m, "\nproc: %s\n", task->comm);
2214                 put_task_struct(task);
2215                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2216                              (void *)(unsigned long)m);
2217         }
2218
2219 out_rpm:
2220         intel_runtime_pm_put(dev_priv);
2221         mutex_unlock(&dev->struct_mutex);
2222 out_unlock:
2223         mutex_unlock(&dev->filelist_mutex);
2224         return ret;
2225 }
2226
2227 static int count_irq_waiters(struct drm_i915_private *i915)
2228 {
2229         struct intel_engine_cs *engine;
2230         enum intel_engine_id id;
2231         int count = 0;
2232
2233         for_each_engine(engine, i915, id)
2234                 count += intel_engine_has_waiter(engine);
2235
2236         return count;
2237 }
2238
2239 static const char *rps_power_to_str(unsigned int power)
2240 {
2241         static const char * const strings[] = {
2242                 [LOW_POWER] = "low power",
2243                 [BETWEEN] = "mixed",
2244                 [HIGH_POWER] = "high power",
2245         };
2246
2247         if (power >= ARRAY_SIZE(strings) || !strings[power])
2248                 return "unknown";
2249
2250         return strings[power];
2251 }
2252
2253 static int i915_rps_boost_info(struct seq_file *m, void *data)
2254 {
2255         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2256         struct drm_device *dev = &dev_priv->drm;
2257         struct drm_file *file;
2258
2259         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2260         seq_printf(m, "GPU busy? %s [%d requests]\n",
2261                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2262         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2263         seq_printf(m, "Boosts outstanding? %d\n",
2264                    atomic_read(&dev_priv->rps.num_waiters));
2265         seq_printf(m, "Frequency requested %d\n",
2266                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2267         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2268                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2269                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2270                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2271                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2272         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2273                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2274                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2275                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2276
2277         mutex_lock(&dev->filelist_mutex);
2278         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2279                 struct drm_i915_file_private *file_priv = file->driver_priv;
2280                 struct task_struct *task;
2281
2282                 rcu_read_lock();
2283                 task = pid_task(file->pid, PIDTYPE_PID);
2284                 seq_printf(m, "%s [%d]: %d boosts\n",
2285                            task ? task->comm : "<unknown>",
2286                            task ? task->pid : -1,
2287                            atomic_read(&file_priv->rps.boosts));
2288                 rcu_read_unlock();
2289         }
2290         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2291                    atomic_read(&dev_priv->rps.boosts));
2292         mutex_unlock(&dev->filelist_mutex);
2293
2294         if (INTEL_GEN(dev_priv) >= 6 &&
2295             dev_priv->rps.enabled &&
2296             dev_priv->gt.active_requests) {
2297                 u32 rpup, rpupei;
2298                 u32 rpdown, rpdownei;
2299
2300                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2301                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2302                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2303                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2304                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2305                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2306
2307                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2308                            rps_power_to_str(dev_priv->rps.power));
2309                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2310                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2311                            dev_priv->rps.up_threshold);
2312                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2313                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2314                            dev_priv->rps.down_threshold);
2315         } else {
2316                 seq_puts(m, "\nRPS Autotuning inactive\n");
2317         }
2318
2319         return 0;
2320 }
2321
2322 static int i915_llc(struct seq_file *m, void *data)
2323 {
2324         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2325         const bool edram = INTEL_GEN(dev_priv) > 8;
2326
2327         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2328         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2329                    intel_uncore_edram_size(dev_priv)/1024/1024);
2330
2331         return 0;
2332 }
2333
2334 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2335 {
2336         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2337         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2338
2339         if (!HAS_HUC_UCODE(dev_priv))
2340                 return 0;
2341
2342         seq_puts(m, "HuC firmware status:\n");
2343         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2344         seq_printf(m, "\tfetch: %s\n",
2345                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2346         seq_printf(m, "\tload: %s\n",
2347                 intel_uc_fw_status_repr(huc_fw->load_status));
2348         seq_printf(m, "\tversion wanted: %d.%d\n",
2349                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2350         seq_printf(m, "\tversion found: %d.%d\n",
2351                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2352         seq_printf(m, "\theader: offset is %d; size = %d\n",
2353                 huc_fw->header_offset, huc_fw->header_size);
2354         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2355                 huc_fw->ucode_offset, huc_fw->ucode_size);
2356         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2357                 huc_fw->rsa_offset, huc_fw->rsa_size);
2358
2359         intel_runtime_pm_get(dev_priv);
2360         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2361         intel_runtime_pm_put(dev_priv);
2362
2363         return 0;
2364 }
2365
2366 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2367 {
2368         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2369         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2370         u32 tmp, i;
2371
2372         if (!HAS_GUC_UCODE(dev_priv))
2373                 return 0;
2374
2375         seq_printf(m, "GuC firmware status:\n");
2376         seq_printf(m, "\tpath: %s\n",
2377                 guc_fw->path);
2378         seq_printf(m, "\tfetch: %s\n",
2379                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2380         seq_printf(m, "\tload: %s\n",
2381                 intel_uc_fw_status_repr(guc_fw->load_status));
2382         seq_printf(m, "\tversion wanted: %d.%d\n",
2383                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2384         seq_printf(m, "\tversion found: %d.%d\n",
2385                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2386         seq_printf(m, "\theader: offset is %d; size = %d\n",
2387                 guc_fw->header_offset, guc_fw->header_size);
2388         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2389                 guc_fw->ucode_offset, guc_fw->ucode_size);
2390         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2391                 guc_fw->rsa_offset, guc_fw->rsa_size);
2392
2393         intel_runtime_pm_get(dev_priv);
2394
2395         tmp = I915_READ(GUC_STATUS);
2396
2397         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2398         seq_printf(m, "\tBootrom status = 0x%x\n",
2399                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2400         seq_printf(m, "\tuKernel status = 0x%x\n",
2401                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2402         seq_printf(m, "\tMIA Core status = 0x%x\n",
2403                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2404         seq_puts(m, "\nScratch registers:\n");
2405         for (i = 0; i < 16; i++)
2406                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2407
2408         intel_runtime_pm_put(dev_priv);
2409
2410         return 0;
2411 }
2412
2413 static void i915_guc_log_info(struct seq_file *m,
2414                               struct drm_i915_private *dev_priv)
2415 {
2416         struct intel_guc *guc = &dev_priv->guc;
2417
2418         seq_puts(m, "\nGuC logging stats:\n");
2419
2420         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2421                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2422                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2423
2424         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2425                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2426                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2427
2428         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2429                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2430                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2431
2432         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2433                    guc->log.flush_interrupt_count);
2434
2435         seq_printf(m, "\tCapture miss count: %u\n",
2436                    guc->log.capture_miss_count);
2437 }
2438
2439 static void i915_guc_client_info(struct seq_file *m,
2440                                  struct drm_i915_private *dev_priv,
2441                                  struct i915_guc_client *client)
2442 {
2443         struct intel_engine_cs *engine;
2444         enum intel_engine_id id;
2445         uint64_t tot = 0;
2446
2447         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2448                 client->priority, client->stage_id, client->proc_desc_offset);
2449         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2450                 client->doorbell_id, client->doorbell_offset);
2451
2452         for_each_engine(engine, dev_priv, id) {
2453                 u64 submissions = client->submissions[id];
2454                 tot += submissions;
2455                 seq_printf(m, "\tSubmissions: %llu %s\n",
2456                                 submissions, engine->name);
2457         }
2458         seq_printf(m, "\tTotal: %llu\n", tot);
2459 }
2460
2461 static bool check_guc_submission(struct seq_file *m)
2462 {
2463         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2464         const struct intel_guc *guc = &dev_priv->guc;
2465
2466         if (!guc->execbuf_client) {
2467                 seq_printf(m, "GuC submission %s\n",
2468                            HAS_GUC_SCHED(dev_priv) ?
2469                            "disabled" :
2470                            "not supported");
2471                 return false;
2472         }
2473
2474         return true;
2475 }
2476
2477 static int i915_guc_info(struct seq_file *m, void *data)
2478 {
2479         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2480         const struct intel_guc *guc = &dev_priv->guc;
2481
2482         if (!check_guc_submission(m))
2483                 return 0;
2484
2485         seq_printf(m, "Doorbell map:\n");
2486         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2487         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2488
2489         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2490         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2491
2492         i915_guc_log_info(m, dev_priv);
2493
2494         /* Add more as required ... */
2495
2496         return 0;
2497 }
2498
2499 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2500 {
2501         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2502         const struct intel_guc *guc = &dev_priv->guc;
2503         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2504         struct i915_guc_client *client = guc->execbuf_client;
2505         unsigned int tmp;
2506         int index;
2507
2508         if (!check_guc_submission(m))
2509                 return 0;
2510
2511         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2512                 struct intel_engine_cs *engine;
2513
2514                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2515                         continue;
2516
2517                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2518                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2519                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2520                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2521                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2522                 seq_printf(m, "\tEngines used: 0x%x\n",
2523                            desc->engines_used);
2524                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2525                            desc->db_trigger_phy,
2526                            desc->db_trigger_cpu,
2527                            desc->db_trigger_uk);
2528                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2529                            desc->process_desc);
2530                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2531                            desc->wq_addr, desc->wq_size);
2532                 seq_putc(m, '\n');
2533
2534                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2535                         u32 guc_engine_id = engine->guc_id;
2536                         struct guc_execlist_context *lrc =
2537                                                 &desc->lrc[guc_engine_id];
2538
2539                         seq_printf(m, "\t%s LRC:\n", engine->name);
2540                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2541                                    lrc->context_desc);
2542                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2543                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2544                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2545                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2546                         seq_putc(m, '\n');
2547                 }
2548         }
2549
2550         return 0;
2551 }
2552
2553 static int i915_guc_log_dump(struct seq_file *m, void *data)
2554 {
2555         struct drm_info_node *node = m->private;
2556         struct drm_i915_private *dev_priv = node_to_i915(node);
2557         bool dump_load_err = !!node->info_ent->data;
2558         struct drm_i915_gem_object *obj = NULL;
2559         u32 *log;
2560         int i = 0;
2561
2562         if (dump_load_err)
2563                 obj = dev_priv->guc.load_err_log;
2564         else if (dev_priv->guc.log.vma)
2565                 obj = dev_priv->guc.log.vma->obj;
2566
2567         if (!obj)
2568                 return 0;
2569
2570         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2571         if (IS_ERR(log)) {
2572                 DRM_DEBUG("Failed to pin object\n");
2573                 seq_puts(m, "(log data unaccessible)\n");
2574                 return PTR_ERR(log);
2575         }
2576
2577         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2578                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2579                            *(log + i), *(log + i + 1),
2580                            *(log + i + 2), *(log + i + 3));
2581
2582         seq_putc(m, '\n');
2583
2584         i915_gem_object_unpin_map(obj);
2585
2586         return 0;
2587 }
2588
2589 static int i915_guc_log_control_get(void *data, u64 *val)
2590 {
2591         struct drm_i915_private *dev_priv = data;
2592
2593         if (!dev_priv->guc.log.vma)
2594                 return -EINVAL;
2595
2596         *val = i915_modparams.guc_log_level;
2597
2598         return 0;
2599 }
2600
2601 static int i915_guc_log_control_set(void *data, u64 val)
2602 {
2603         struct drm_i915_private *dev_priv = data;
2604         int ret;
2605
2606         if (!dev_priv->guc.log.vma)
2607                 return -EINVAL;
2608
2609         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2610         if (ret)
2611                 return ret;
2612
2613         intel_runtime_pm_get(dev_priv);
2614         ret = i915_guc_log_control(dev_priv, val);
2615         intel_runtime_pm_put(dev_priv);
2616
2617         mutex_unlock(&dev_priv->drm.struct_mutex);
2618         return ret;
2619 }
2620
2621 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2622                         i915_guc_log_control_get, i915_guc_log_control_set,
2623                         "%lld\n");
2624
2625 static const char *psr2_live_status(u32 val)
2626 {
2627         static const char * const live_status[] = {
2628                 "IDLE",
2629                 "CAPTURE",
2630                 "CAPTURE_FS",
2631                 "SLEEP",
2632                 "BUFON_FW",
2633                 "ML_UP",
2634                 "SU_STANDBY",
2635                 "FAST_SLEEP",
2636                 "DEEP_SLEEP",
2637                 "BUF_ON",
2638                 "TG_ON"
2639         };
2640
2641         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2642         if (val < ARRAY_SIZE(live_status))
2643                 return live_status[val];
2644
2645         return "unknown";
2646 }
2647
2648 static int i915_edp_psr_status(struct seq_file *m, void *data)
2649 {
2650         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2651         u32 psrperf = 0;
2652         u32 stat[3];
2653         enum pipe pipe;
2654         bool enabled = false;
2655
2656         if (!HAS_PSR(dev_priv)) {
2657                 seq_puts(m, "PSR not supported\n");
2658                 return 0;
2659         }
2660
2661         intel_runtime_pm_get(dev_priv);
2662
2663         mutex_lock(&dev_priv->psr.lock);
2664         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2665         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2666         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2667         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2668         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2669                    dev_priv->psr.busy_frontbuffer_bits);
2670         seq_printf(m, "Re-enable work scheduled: %s\n",
2671                    yesno(work_busy(&dev_priv->psr.work.work)));
2672
2673         if (HAS_DDI(dev_priv)) {
2674                 if (dev_priv->psr.psr2_support)
2675                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2676                 else
2677                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2678         } else {
2679                 for_each_pipe(dev_priv, pipe) {
2680                         enum transcoder cpu_transcoder =
2681                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2682                         enum intel_display_power_domain power_domain;
2683
2684                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2685                         if (!intel_display_power_get_if_enabled(dev_priv,
2686                                                                 power_domain))
2687                                 continue;
2688
2689                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2690                                 VLV_EDP_PSR_CURR_STATE_MASK;
2691                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2692                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2693                                 enabled = true;
2694
2695                         intel_display_power_put(dev_priv, power_domain);
2696                 }
2697         }
2698
2699         seq_printf(m, "Main link in standby mode: %s\n",
2700                    yesno(dev_priv->psr.link_standby));
2701
2702         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2703
2704         if (!HAS_DDI(dev_priv))
2705                 for_each_pipe(dev_priv, pipe) {
2706                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2707                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2708                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2709                 }
2710         seq_puts(m, "\n");
2711
2712         /*
2713          * VLV/CHV PSR has no kind of performance counter
2714          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2715          */
2716         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2717                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2718                         EDP_PSR_PERF_CNT_MASK;
2719
2720                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2721         }
2722         if (dev_priv->psr.psr2_support) {
2723                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2724
2725                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2726                            psr2, psr2_live_status(psr2));
2727         }
2728         mutex_unlock(&dev_priv->psr.lock);
2729
2730         intel_runtime_pm_put(dev_priv);
2731         return 0;
2732 }
2733
2734 static int i915_sink_crc(struct seq_file *m, void *data)
2735 {
2736         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2737         struct drm_device *dev = &dev_priv->drm;
2738         struct intel_connector *connector;
2739         struct drm_connector_list_iter conn_iter;
2740         struct intel_dp *intel_dp = NULL;
2741         int ret;
2742         u8 crc[6];
2743
2744         drm_modeset_lock_all(dev);
2745         drm_connector_list_iter_begin(dev, &conn_iter);
2746         for_each_intel_connector_iter(connector, &conn_iter) {
2747                 struct drm_crtc *crtc;
2748
2749                 if (!connector->base.state->best_encoder)
2750                         continue;
2751
2752                 crtc = connector->base.state->crtc;
2753                 if (!crtc->state->active)
2754                         continue;
2755
2756                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2757                         continue;
2758
2759                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2760
2761                 ret = intel_dp_sink_crc(intel_dp, crc);
2762                 if (ret)
2763                         goto out;
2764
2765                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2766                            crc[0], crc[1], crc[2],
2767                            crc[3], crc[4], crc[5]);
2768                 goto out;
2769         }
2770         ret = -ENODEV;
2771 out:
2772         drm_connector_list_iter_end(&conn_iter);
2773         drm_modeset_unlock_all(dev);
2774         return ret;
2775 }
2776
2777 static int i915_energy_uJ(struct seq_file *m, void *data)
2778 {
2779         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2780         unsigned long long power;
2781         u32 units;
2782
2783         if (INTEL_GEN(dev_priv) < 6)
2784                 return -ENODEV;
2785
2786         intel_runtime_pm_get(dev_priv);
2787
2788         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2789                 intel_runtime_pm_put(dev_priv);
2790                 return -ENODEV;
2791         }
2792
2793         units = (power & 0x1f00) >> 8;
2794         power = I915_READ(MCH_SECP_NRG_STTS);
2795         power = (1000000 * power) >> units; /* convert to uJ */
2796
2797         intel_runtime_pm_put(dev_priv);
2798
2799         seq_printf(m, "%llu", power);
2800
2801         return 0;
2802 }
2803
2804 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2805 {
2806         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2807         struct pci_dev *pdev = dev_priv->drm.pdev;
2808
2809         if (!HAS_RUNTIME_PM(dev_priv))
2810                 seq_puts(m, "Runtime power management not supported\n");
2811
2812         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2813         seq_printf(m, "IRQs disabled: %s\n",
2814                    yesno(!intel_irqs_enabled(dev_priv)));
2815 #ifdef CONFIG_PM
2816         seq_printf(m, "Usage count: %d\n",
2817                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2818 #else
2819         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2820 #endif
2821         seq_printf(m, "PCI device power state: %s [%d]\n",
2822                    pci_power_name(pdev->current_state),
2823                    pdev->current_state);
2824
2825         return 0;
2826 }
2827
2828 static int i915_power_domain_info(struct seq_file *m, void *unused)
2829 {
2830         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2831         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2832         int i;
2833
2834         mutex_lock(&power_domains->lock);
2835
2836         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2837         for (i = 0; i < power_domains->power_well_count; i++) {
2838                 struct i915_power_well *power_well;
2839                 enum intel_display_power_domain power_domain;
2840
2841                 power_well = &power_domains->power_wells[i];
2842                 seq_printf(m, "%-25s %d\n", power_well->name,
2843                            power_well->count);
2844
2845                 for_each_power_domain(power_domain, power_well->domains)
2846                         seq_printf(m, "  %-23s %d\n",
2847                                  intel_display_power_domain_str(power_domain),
2848                                  power_domains->domain_use_count[power_domain]);
2849         }
2850
2851         mutex_unlock(&power_domains->lock);
2852
2853         return 0;
2854 }
2855
2856 static int i915_dmc_info(struct seq_file *m, void *unused)
2857 {
2858         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2859         struct intel_csr *csr;
2860
2861         if (!HAS_CSR(dev_priv)) {
2862                 seq_puts(m, "not supported\n");
2863                 return 0;
2864         }
2865
2866         csr = &dev_priv->csr;
2867
2868         intel_runtime_pm_get(dev_priv);
2869
2870         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2871         seq_printf(m, "path: %s\n", csr->fw_path);
2872
2873         if (!csr->dmc_payload)
2874                 goto out;
2875
2876         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2877                    CSR_VERSION_MINOR(csr->version));
2878
2879         if (IS_KABYLAKE(dev_priv) ||
2880             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2881                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2882                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2883                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2884                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2885         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2886                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2887                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2888         }
2889
2890 out:
2891         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2892         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2893         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2894
2895         intel_runtime_pm_put(dev_priv);
2896
2897         return 0;
2898 }
2899
2900 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2901                                  struct drm_display_mode *mode)
2902 {
2903         int i;
2904
2905         for (i = 0; i < tabs; i++)
2906                 seq_putc(m, '\t');
2907
2908         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2909                    mode->base.id, mode->name,
2910                    mode->vrefresh, mode->clock,
2911                    mode->hdisplay, mode->hsync_start,
2912                    mode->hsync_end, mode->htotal,
2913                    mode->vdisplay, mode->vsync_start,
2914                    mode->vsync_end, mode->vtotal,
2915                    mode->type, mode->flags);
2916 }
2917
2918 static void intel_encoder_info(struct seq_file *m,
2919                                struct intel_crtc *intel_crtc,
2920                                struct intel_encoder *intel_encoder)
2921 {
2922         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2923         struct drm_device *dev = &dev_priv->drm;
2924         struct drm_crtc *crtc = &intel_crtc->base;
2925         struct intel_connector *intel_connector;
2926         struct drm_encoder *encoder;
2927
2928         encoder = &intel_encoder->base;
2929         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2930                    encoder->base.id, encoder->name);
2931         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2932                 struct drm_connector *connector = &intel_connector->base;
2933                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2934                            connector->base.id,
2935                            connector->name,
2936                            drm_get_connector_status_name(connector->status));
2937                 if (connector->status == connector_status_connected) {
2938                         struct drm_display_mode *mode = &crtc->mode;
2939                         seq_printf(m, ", mode:\n");
2940                         intel_seq_print_mode(m, 2, mode);
2941                 } else {
2942                         seq_putc(m, '\n');
2943                 }
2944         }
2945 }
2946
2947 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2948 {
2949         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2950         struct drm_device *dev = &dev_priv->drm;
2951         struct drm_crtc *crtc = &intel_crtc->base;
2952         struct intel_encoder *intel_encoder;
2953         struct drm_plane_state *plane_state = crtc->primary->state;
2954         struct drm_framebuffer *fb = plane_state->fb;
2955
2956         if (fb)
2957                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2958                            fb->base.id, plane_state->src_x >> 16,
2959                            plane_state->src_y >> 16, fb->width, fb->height);
2960         else
2961                 seq_puts(m, "\tprimary plane disabled\n");
2962         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2963                 intel_encoder_info(m, intel_crtc, intel_encoder);
2964 }
2965
2966 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2967 {
2968         struct drm_display_mode *mode = panel->fixed_mode;
2969
2970         seq_printf(m, "\tfixed mode:\n");
2971         intel_seq_print_mode(m, 2, mode);
2972 }
2973
2974 static void intel_dp_info(struct seq_file *m,
2975                           struct intel_connector *intel_connector)
2976 {
2977         struct intel_encoder *intel_encoder = intel_connector->encoder;
2978         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2979
2980         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2981         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2982         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2983                 intel_panel_info(m, &intel_connector->panel);
2984
2985         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2986                                 &intel_dp->aux);
2987 }
2988
2989 static void intel_dp_mst_info(struct seq_file *m,
2990                           struct intel_connector *intel_connector)
2991 {
2992         struct intel_encoder *intel_encoder = intel_connector->encoder;
2993         struct intel_dp_mst_encoder *intel_mst =
2994                 enc_to_mst(&intel_encoder->base);
2995         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2996         struct intel_dp *intel_dp = &intel_dig_port->dp;
2997         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2998                                         intel_connector->port);
2999
3000         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
3001 }
3002
3003 static void intel_hdmi_info(struct seq_file *m,
3004                             struct intel_connector *intel_connector)
3005 {
3006         struct intel_encoder *intel_encoder = intel_connector->encoder;
3007         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3008
3009         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3010 }
3011
3012 static void intel_lvds_info(struct seq_file *m,
3013                             struct intel_connector *intel_connector)
3014 {
3015         intel_panel_info(m, &intel_connector->panel);
3016 }
3017
3018 static void intel_connector_info(struct seq_file *m,
3019                                  struct drm_connector *connector)
3020 {
3021         struct intel_connector *intel_connector = to_intel_connector(connector);
3022         struct intel_encoder *intel_encoder = intel_connector->encoder;
3023         struct drm_display_mode *mode;
3024
3025         seq_printf(m, "connector %d: type %s, status: %s\n",
3026                    connector->base.id, connector->name,
3027                    drm_get_connector_status_name(connector->status));
3028         if (connector->status == connector_status_connected) {
3029                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3030                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3031                            connector->display_info.width_mm,
3032                            connector->display_info.height_mm);
3033                 seq_printf(m, "\tsubpixel order: %s\n",
3034                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3035                 seq_printf(m, "\tCEA rev: %d\n",
3036                            connector->display_info.cea_rev);
3037         }
3038
3039         if (!intel_encoder)
3040                 return;
3041
3042         switch (connector->connector_type) {
3043         case DRM_MODE_CONNECTOR_DisplayPort:
3044         case DRM_MODE_CONNECTOR_eDP:
3045                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3046                         intel_dp_mst_info(m, intel_connector);
3047                 else
3048                         intel_dp_info(m, intel_connector);
3049                 break;
3050         case DRM_MODE_CONNECTOR_LVDS:
3051                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3052                         intel_lvds_info(m, intel_connector);
3053                 break;
3054         case DRM_MODE_CONNECTOR_HDMIA:
3055                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3056                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3057                         intel_hdmi_info(m, intel_connector);
3058                 break;
3059         default:
3060                 break;
3061         }
3062
3063         seq_printf(m, "\tmodes:\n");
3064         list_for_each_entry(mode, &connector->modes, head)
3065                 intel_seq_print_mode(m, 2, mode);
3066 }
3067
3068 static const char *plane_type(enum drm_plane_type type)
3069 {
3070         switch (type) {
3071         case DRM_PLANE_TYPE_OVERLAY:
3072                 return "OVL";
3073         case DRM_PLANE_TYPE_PRIMARY:
3074                 return "PRI";
3075         case DRM_PLANE_TYPE_CURSOR:
3076                 return "CUR";
3077         /*
3078          * Deliberately omitting default: to generate compiler warnings
3079          * when a new drm_plane_type gets added.
3080          */
3081         }
3082
3083         return "unknown";
3084 }
3085
3086 static const char *plane_rotation(unsigned int rotation)
3087 {
3088         static char buf[48];
3089         /*
3090          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3091          * will print them all to visualize if the values are misused
3092          */
3093         snprintf(buf, sizeof(buf),
3094                  "%s%s%s%s%s%s(0x%08x)",
3095                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3096                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3097                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3098                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3099                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3100                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3101                  rotation);
3102
3103         return buf;
3104 }
3105
3106 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3107 {
3108         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3109         struct drm_device *dev = &dev_priv->drm;
3110         struct intel_plane *intel_plane;
3111
3112         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3113                 struct drm_plane_state *state;
3114                 struct drm_plane *plane = &intel_plane->base;
3115                 struct drm_format_name_buf format_name;
3116
3117                 if (!plane->state) {
3118                         seq_puts(m, "plane->state is NULL!\n");
3119                         continue;
3120                 }
3121
3122                 state = plane->state;
3123
3124                 if (state->fb) {
3125                         drm_get_format_name(state->fb->format->format,
3126                                             &format_name);
3127                 } else {
3128                         sprintf(format_name.str, "N/A");
3129                 }
3130
3131                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3132                            plane->base.id,
3133                            plane_type(intel_plane->base.type),
3134                            state->crtc_x, state->crtc_y,
3135                            state->crtc_w, state->crtc_h,
3136                            (state->src_x >> 16),
3137                            ((state->src_x & 0xffff) * 15625) >> 10,
3138                            (state->src_y >> 16),
3139                            ((state->src_y & 0xffff) * 15625) >> 10,
3140                            (state->src_w >> 16),
3141                            ((state->src_w & 0xffff) * 15625) >> 10,
3142                            (state->src_h >> 16),
3143                            ((state->src_h & 0xffff) * 15625) >> 10,
3144                            format_name.str,
3145                            plane_rotation(state->rotation));
3146         }
3147 }
3148
3149 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3150 {
3151         struct intel_crtc_state *pipe_config;
3152         int num_scalers = intel_crtc->num_scalers;
3153         int i;
3154
3155         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3156
3157         /* Not all platformas have a scaler */
3158         if (num_scalers) {
3159                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3160                            num_scalers,
3161                            pipe_config->scaler_state.scaler_users,
3162                            pipe_config->scaler_state.scaler_id);
3163
3164                 for (i = 0; i < num_scalers; i++) {
3165                         struct intel_scaler *sc =
3166                                         &pipe_config->scaler_state.scalers[i];
3167
3168                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3169                                    i, yesno(sc->in_use), sc->mode);
3170                 }
3171                 seq_puts(m, "\n");
3172         } else {
3173                 seq_puts(m, "\tNo scalers available on this platform\n");
3174         }
3175 }
3176
3177 static int i915_display_info(struct seq_file *m, void *unused)
3178 {
3179         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3180         struct drm_device *dev = &dev_priv->drm;
3181         struct intel_crtc *crtc;
3182         struct drm_connector *connector;
3183         struct drm_connector_list_iter conn_iter;
3184
3185         intel_runtime_pm_get(dev_priv);
3186         seq_printf(m, "CRTC info\n");
3187         seq_printf(m, "---------\n");
3188         for_each_intel_crtc(dev, crtc) {
3189                 struct intel_crtc_state *pipe_config;
3190
3191                 drm_modeset_lock(&crtc->base.mutex, NULL);
3192                 pipe_config = to_intel_crtc_state(crtc->base.state);
3193
3194                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3195                            crtc->base.base.id, pipe_name(crtc->pipe),
3196                            yesno(pipe_config->base.active),
3197                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3198                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3199
3200                 if (pipe_config->base.active) {
3201                         struct intel_plane *cursor =
3202                                 to_intel_plane(crtc->base.cursor);
3203
3204                         intel_crtc_info(m, crtc);
3205
3206                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3207                                    yesno(cursor->base.state->visible),
3208                                    cursor->base.state->crtc_x,
3209                                    cursor->base.state->crtc_y,
3210                                    cursor->base.state->crtc_w,
3211                                    cursor->base.state->crtc_h,
3212                                    cursor->cursor.base);
3213                         intel_scaler_info(m, crtc);
3214                         intel_plane_info(m, crtc);
3215                 }
3216
3217                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3218                            yesno(!crtc->cpu_fifo_underrun_disabled),
3219                            yesno(!crtc->pch_fifo_underrun_disabled));
3220                 drm_modeset_unlock(&crtc->base.mutex);
3221         }
3222
3223         seq_printf(m, "\n");
3224         seq_printf(m, "Connector info\n");
3225         seq_printf(m, "--------------\n");
3226         mutex_lock(&dev->mode_config.mutex);
3227         drm_connector_list_iter_begin(dev, &conn_iter);
3228         drm_for_each_connector_iter(connector, &conn_iter)
3229                 intel_connector_info(m, connector);
3230         drm_connector_list_iter_end(&conn_iter);
3231         mutex_unlock(&dev->mode_config.mutex);
3232
3233         intel_runtime_pm_put(dev_priv);
3234
3235         return 0;
3236 }
3237
3238 static int i915_engine_info(struct seq_file *m, void *unused)
3239 {
3240         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3241         struct i915_gpu_error *error = &dev_priv->gpu_error;
3242         struct intel_engine_cs *engine;
3243         enum intel_engine_id id;
3244
3245         intel_runtime_pm_get(dev_priv);
3246
3247         seq_printf(m, "GT awake? %s\n",
3248                    yesno(dev_priv->gt.awake));
3249         seq_printf(m, "Global active requests: %d\n",
3250                    dev_priv->gt.active_requests);
3251
3252         for_each_engine(engine, dev_priv, id) {
3253                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3254                 struct drm_i915_gem_request *rq;
3255                 struct rb_node *rb;
3256                 u64 addr;
3257
3258                 seq_printf(m, "%s\n", engine->name);
3259                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
3260                            intel_engine_get_seqno(engine),
3261                            intel_engine_last_submit(engine),
3262                            engine->hangcheck.seqno,
3263                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
3264                            engine->timeline->inflight_seqnos);
3265                 seq_printf(m, "\tReset count: %d\n",
3266                            i915_reset_engine_count(error, engine));
3267
3268                 rcu_read_lock();
3269
3270                 seq_printf(m, "\tRequests:\n");
3271
3272                 rq = list_first_entry(&engine->timeline->requests,
3273                                       struct drm_i915_gem_request, link);
3274                 if (&rq->link != &engine->timeline->requests)
3275                         print_request(m, rq, "\t\tfirst  ");
3276
3277                 rq = list_last_entry(&engine->timeline->requests,
3278                                      struct drm_i915_gem_request, link);
3279                 if (&rq->link != &engine->timeline->requests)
3280                         print_request(m, rq, "\t\tlast   ");
3281
3282                 rq = i915_gem_find_active_request(engine);
3283                 if (rq) {
3284                         print_request(m, rq, "\t\tactive ");
3285                         seq_printf(m,
3286                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3287                                    rq->head, rq->postfix, rq->tail,
3288                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3289                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3290                 }
3291
3292                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3293                            I915_READ(RING_START(engine->mmio_base)),
3294                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3295                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3296                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3297                            rq ? rq->ring->head : 0);
3298                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3299                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3300                            rq ? rq->ring->tail : 0);
3301                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3302                            I915_READ(RING_CTL(engine->mmio_base)),
3303                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3304
3305                 rcu_read_unlock();
3306
3307                 addr = intel_engine_get_active_head(engine);
3308                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3309                            upper_32_bits(addr), lower_32_bits(addr));
3310                 addr = intel_engine_get_last_batch_head(engine);
3311                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3312                            upper_32_bits(addr), lower_32_bits(addr));
3313
3314                 if (i915_modparams.enable_execlists) {
3315                         const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
3316                         struct intel_engine_execlists * const execlists = &engine->execlists;
3317                         u32 ptr, read, write;
3318                         unsigned int idx;
3319
3320                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3321                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3322                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3323
3324                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3325                         read = GEN8_CSB_READ_PTR(ptr);
3326                         write = GEN8_CSB_WRITE_PTR(ptr);
3327                         seq_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
3328                                    read, execlists->csb_head,
3329                                    write,
3330                                    intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
3331                                    yesno(test_bit(ENGINE_IRQ_EXECLIST,
3332                                                   &engine->irq_posted)));
3333                         if (read >= GEN8_CSB_ENTRIES)
3334                                 read = 0;
3335                         if (write >= GEN8_CSB_ENTRIES)
3336                                 write = 0;
3337                         if (read > write)
3338                                 write += GEN8_CSB_ENTRIES;
3339                         while (read < write) {
3340                                 idx = ++read % GEN8_CSB_ENTRIES;
3341                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
3342                                            idx,
3343                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3344                                            hws[idx * 2],
3345                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
3346                                            hws[idx * 2 + 1]);
3347                         }
3348
3349                         rcu_read_lock();
3350                         for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
3351                                 unsigned int count;
3352
3353                                 rq = port_unpack(&execlists->port[idx], &count);
3354                                 if (rq) {
3355                                         seq_printf(m, "\t\tELSP[%d] count=%d, ",
3356                                                    idx, count);
3357                                         print_request(m, rq, "rq: ");
3358                                 } else {
3359                                         seq_printf(m, "\t\tELSP[%d] idle\n",
3360                                                    idx);
3361                                 }
3362                         }
3363                         rcu_read_unlock();
3364
3365                         spin_lock_irq(&engine->timeline->lock);
3366                         for (rb = execlists->first; rb; rb = rb_next(rb)) {
3367                                 struct i915_priolist *p =
3368                                         rb_entry(rb, typeof(*p), node);
3369
3370                                 list_for_each_entry(rq, &p->requests,
3371                                                     priotree.link)
3372                                         print_request(m, rq, "\t\tQ ");
3373                         }
3374                         spin_unlock_irq(&engine->timeline->lock);
3375                 } else if (INTEL_GEN(dev_priv) > 6) {
3376                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3377                                    I915_READ(RING_PP_DIR_BASE(engine)));
3378                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3379                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3380                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3381                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3382                 }
3383
3384                 spin_lock_irq(&b->rb_lock);
3385                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3386                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
3387
3388                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3389                                    w->tsk->comm, w->tsk->pid, w->seqno);
3390                 }
3391                 spin_unlock_irq(&b->rb_lock);
3392
3393                 seq_puts(m, "\n");
3394         }
3395
3396         intel_runtime_pm_put(dev_priv);
3397
3398         return 0;
3399 }
3400
3401 static int i915_semaphore_status(struct seq_file *m, void *unused)
3402 {
3403         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3404         struct drm_device *dev = &dev_priv->drm;
3405         struct intel_engine_cs *engine;
3406         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3407         enum intel_engine_id id;
3408         int j, ret;
3409
3410         if (!i915_modparams.semaphores) {
3411                 seq_puts(m, "Semaphores are disabled\n");
3412                 return 0;
3413         }
3414
3415         ret = mutex_lock_interruptible(&dev->struct_mutex);
3416         if (ret)
3417                 return ret;
3418         intel_runtime_pm_get(dev_priv);
3419
3420         if (IS_BROADWELL(dev_priv)) {
3421                 struct page *page;
3422                 uint64_t *seqno;
3423
3424                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3425
3426                 seqno = (uint64_t *)kmap_atomic(page);
3427                 for_each_engine(engine, dev_priv, id) {
3428                         uint64_t offset;
3429
3430                         seq_printf(m, "%s\n", engine->name);
3431
3432                         seq_puts(m, "  Last signal:");
3433                         for (j = 0; j < num_rings; j++) {
3434                                 offset = id * I915_NUM_ENGINES + j;
3435                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3436                                            seqno[offset], offset * 8);
3437                         }
3438                         seq_putc(m, '\n');
3439
3440                         seq_puts(m, "  Last wait:  ");
3441                         for (j = 0; j < num_rings; j++) {
3442                                 offset = id + (j * I915_NUM_ENGINES);
3443                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3444                                            seqno[offset], offset * 8);
3445                         }
3446                         seq_putc(m, '\n');
3447
3448                 }
3449                 kunmap_atomic(seqno);
3450         } else {
3451                 seq_puts(m, "  Last signal:");
3452                 for_each_engine(engine, dev_priv, id)
3453                         for (j = 0; j < num_rings; j++)
3454                                 seq_printf(m, "0x%08x\n",
3455                                            I915_READ(engine->semaphore.mbox.signal[j]));
3456                 seq_putc(m, '\n');
3457         }
3458
3459         intel_runtime_pm_put(dev_priv);
3460         mutex_unlock(&dev->struct_mutex);
3461         return 0;
3462 }
3463
3464 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3465 {
3466         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3467         struct drm_device *dev = &dev_priv->drm;
3468         int i;
3469
3470         drm_modeset_lock_all(dev);
3471         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3472                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3473
3474                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3475                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3476                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3477                 seq_printf(m, " tracked hardware state:\n");
3478                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3479                 seq_printf(m, " dpll_md: 0x%08x\n",
3480                            pll->state.hw_state.dpll_md);
3481                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3482                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3483                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3484         }
3485         drm_modeset_unlock_all(dev);
3486
3487         return 0;
3488 }
3489
3490 static int i915_wa_registers(struct seq_file *m, void *unused)
3491 {
3492         int i;
3493         int ret;
3494         struct intel_engine_cs *engine;
3495         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3496         struct drm_device *dev = &dev_priv->drm;
3497         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3498         enum intel_engine_id id;
3499
3500         ret = mutex_lock_interruptible(&dev->struct_mutex);
3501         if (ret)
3502                 return ret;
3503
3504         intel_runtime_pm_get(dev_priv);
3505
3506         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3507         for_each_engine(engine, dev_priv, id)
3508                 seq_printf(m, "HW whitelist count for %s: %d\n",
3509                            engine->name, workarounds->hw_whitelist_count[id]);
3510         for (i = 0; i < workarounds->count; ++i) {
3511                 i915_reg_t addr;
3512                 u32 mask, value, read;
3513                 bool ok;
3514
3515                 addr = workarounds->reg[i].addr;
3516                 mask = workarounds->reg[i].mask;
3517                 value = workarounds->reg[i].value;
3518                 read = I915_READ(addr);
3519                 ok = (value & mask) == (read & mask);
3520                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3521                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3522         }
3523
3524         intel_runtime_pm_put(dev_priv);
3525         mutex_unlock(&dev->struct_mutex);
3526
3527         return 0;
3528 }
3529
3530 static int i915_ipc_status_show(struct seq_file *m, void *data)
3531 {
3532         struct drm_i915_private *dev_priv = m->private;
3533
3534         seq_printf(m, "Isochronous Priority Control: %s\n",
3535                         yesno(dev_priv->ipc_enabled));
3536         return 0;
3537 }
3538
3539 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3540 {
3541         struct drm_i915_private *dev_priv = inode->i_private;
3542
3543         if (!HAS_IPC(dev_priv))
3544                 return -ENODEV;
3545
3546         return single_open(file, i915_ipc_status_show, dev_priv);
3547 }
3548
3549 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3550                                      size_t len, loff_t *offp)
3551 {
3552         struct seq_file *m = file->private_data;
3553         struct drm_i915_private *dev_priv = m->private;
3554         int ret;
3555         bool enable;
3556
3557         ret = kstrtobool_from_user(ubuf, len, &enable);
3558         if (ret < 0)
3559                 return ret;
3560
3561         intel_runtime_pm_get(dev_priv);
3562         if (!dev_priv->ipc_enabled && enable)
3563                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3564         dev_priv->wm.distrust_bios_wm = true;
3565         dev_priv->ipc_enabled = enable;
3566         intel_enable_ipc(dev_priv);
3567         intel_runtime_pm_put(dev_priv);
3568
3569         return len;
3570 }
3571
3572 static const struct file_operations i915_ipc_status_fops = {
3573         .owner = THIS_MODULE,
3574         .open = i915_ipc_status_open,
3575         .read = seq_read,
3576         .llseek = seq_lseek,
3577         .release = single_release,
3578         .write = i915_ipc_status_write
3579 };
3580
3581 static int i915_ddb_info(struct seq_file *m, void *unused)
3582 {
3583         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3584         struct drm_device *dev = &dev_priv->drm;
3585         struct skl_ddb_allocation *ddb;
3586         struct skl_ddb_entry *entry;
3587         enum pipe pipe;
3588         int plane;
3589
3590         if (INTEL_GEN(dev_priv) < 9)
3591                 return 0;
3592
3593         drm_modeset_lock_all(dev);
3594
3595         ddb = &dev_priv->wm.skl_hw.ddb;
3596
3597         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3598
3599         for_each_pipe(dev_priv, pipe) {
3600                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3601
3602                 for_each_universal_plane(dev_priv, pipe, plane) {
3603                         entry = &ddb->plane[pipe][plane];
3604                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3605                                    entry->start, entry->end,
3606                                    skl_ddb_entry_size(entry));
3607                 }
3608
3609                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3610                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3611                            entry->end, skl_ddb_entry_size(entry));
3612         }
3613
3614         drm_modeset_unlock_all(dev);
3615
3616         return 0;
3617 }
3618
3619 static void drrs_status_per_crtc(struct seq_file *m,
3620                                  struct drm_device *dev,
3621                                  struct intel_crtc *intel_crtc)
3622 {
3623         struct drm_i915_private *dev_priv = to_i915(dev);
3624         struct i915_drrs *drrs = &dev_priv->drrs;
3625         int vrefresh = 0;
3626         struct drm_connector *connector;
3627         struct drm_connector_list_iter conn_iter;
3628
3629         drm_connector_list_iter_begin(dev, &conn_iter);
3630         drm_for_each_connector_iter(connector, &conn_iter) {
3631                 if (connector->state->crtc != &intel_crtc->base)
3632                         continue;
3633
3634                 seq_printf(m, "%s:\n", connector->name);
3635         }
3636         drm_connector_list_iter_end(&conn_iter);
3637
3638         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3639                 seq_puts(m, "\tVBT: DRRS_type: Static");
3640         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3641                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3642         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3643                 seq_puts(m, "\tVBT: DRRS_type: None");
3644         else
3645                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3646
3647         seq_puts(m, "\n\n");
3648
3649         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3650                 struct intel_panel *panel;
3651
3652                 mutex_lock(&drrs->mutex);
3653                 /* DRRS Supported */
3654                 seq_puts(m, "\tDRRS Supported: Yes\n");
3655
3656                 /* disable_drrs() will make drrs->dp NULL */
3657                 if (!drrs->dp) {
3658                         seq_puts(m, "Idleness DRRS: Disabled");
3659                         mutex_unlock(&drrs->mutex);
3660                         return;
3661                 }
3662
3663                 panel = &drrs->dp->attached_connector->panel;
3664                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3665                                         drrs->busy_frontbuffer_bits);
3666
3667                 seq_puts(m, "\n\t\t");
3668                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3669                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3670                         vrefresh = panel->fixed_mode->vrefresh;
3671                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3672                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3673                         vrefresh = panel->downclock_mode->vrefresh;
3674                 } else {
3675                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3676                                                 drrs->refresh_rate_type);
3677                         mutex_unlock(&drrs->mutex);
3678                         return;
3679                 }
3680                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3681
3682                 seq_puts(m, "\n\t\t");
3683                 mutex_unlock(&drrs->mutex);
3684         } else {
3685                 /* DRRS not supported. Print the VBT parameter*/
3686                 seq_puts(m, "\tDRRS Supported : No");
3687         }
3688         seq_puts(m, "\n");
3689 }
3690
3691 static int i915_drrs_status(struct seq_file *m, void *unused)
3692 {
3693         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3694         struct drm_device *dev = &dev_priv->drm;
3695         struct intel_crtc *intel_crtc;
3696         int active_crtc_cnt = 0;
3697
3698         drm_modeset_lock_all(dev);
3699         for_each_intel_crtc(dev, intel_crtc) {
3700                 if (intel_crtc->base.state->active) {
3701                         active_crtc_cnt++;
3702                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3703
3704                         drrs_status_per_crtc(m, dev, intel_crtc);
3705                 }
3706         }
3707         drm_modeset_unlock_all(dev);
3708
3709         if (!active_crtc_cnt)
3710                 seq_puts(m, "No active crtc found\n");
3711
3712         return 0;
3713 }
3714
3715 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3716 {
3717         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3718         struct drm_device *dev = &dev_priv->drm;
3719         struct intel_encoder *intel_encoder;
3720         struct intel_digital_port *intel_dig_port;
3721         struct drm_connector *connector;
3722         struct drm_connector_list_iter conn_iter;
3723
3724         drm_connector_list_iter_begin(dev, &conn_iter);
3725         drm_for_each_connector_iter(connector, &conn_iter) {
3726                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3727                         continue;
3728
3729                 intel_encoder = intel_attached_encoder(connector);
3730                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3731                         continue;
3732
3733                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3734                 if (!intel_dig_port->dp.can_mst)
3735                         continue;
3736
3737                 seq_printf(m, "MST Source Port %c\n",
3738                            port_name(intel_dig_port->port));
3739                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3740         }
3741         drm_connector_list_iter_end(&conn_iter);
3742
3743         return 0;
3744 }
3745
3746 static ssize_t i915_displayport_test_active_write(struct file *file,
3747                                                   const char __user *ubuf,
3748                                                   size_t len, loff_t *offp)
3749 {
3750         char *input_buffer;
3751         int status = 0;
3752         struct drm_device *dev;
3753         struct drm_connector *connector;
3754         struct drm_connector_list_iter conn_iter;
3755         struct intel_dp *intel_dp;
3756         int val = 0;
3757
3758         dev = ((struct seq_file *)file->private_data)->private;
3759
3760         if (len == 0)
3761                 return 0;
3762
3763         input_buffer = memdup_user_nul(ubuf, len);
3764         if (IS_ERR(input_buffer))
3765                 return PTR_ERR(input_buffer);
3766
3767         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3768
3769         drm_connector_list_iter_begin(dev, &conn_iter);
3770         drm_for_each_connector_iter(connector, &conn_iter) {
3771                 struct intel_encoder *encoder;
3772
3773                 if (connector->connector_type !=
3774                     DRM_MODE_CONNECTOR_DisplayPort)
3775                         continue;
3776
3777                 encoder = to_intel_encoder(connector->encoder);
3778                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3779                         continue;
3780
3781                 if (encoder && connector->status == connector_status_connected) {
3782                         intel_dp = enc_to_intel_dp(&encoder->base);
3783                         status = kstrtoint(input_buffer, 10, &val);
3784                         if (status < 0)
3785                                 break;
3786                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3787                         /* To prevent erroneous activation of the compliance
3788                          * testing code, only accept an actual value of 1 here
3789                          */
3790                         if (val == 1)
3791                                 intel_dp->compliance.test_active = 1;
3792                         else
3793                                 intel_dp->compliance.test_active = 0;
3794                 }
3795         }
3796         drm_connector_list_iter_end(&conn_iter);
3797         kfree(input_buffer);
3798         if (status < 0)
3799                 return status;
3800
3801         *offp += len;
3802         return len;
3803 }
3804
3805 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3806 {
3807         struct drm_device *dev = m->private;
3808         struct drm_connector *connector;
3809         struct drm_connector_list_iter conn_iter;
3810         struct intel_dp *intel_dp;
3811
3812         drm_connector_list_iter_begin(dev, &conn_iter);
3813         drm_for_each_connector_iter(connector, &conn_iter) {
3814                 struct intel_encoder *encoder;
3815
3816                 if (connector->connector_type !=
3817                     DRM_MODE_CONNECTOR_DisplayPort)
3818                         continue;
3819
3820                 encoder = to_intel_encoder(connector->encoder);
3821                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3822                         continue;
3823
3824                 if (encoder && connector->status == connector_status_connected) {
3825                         intel_dp = enc_to_intel_dp(&encoder->base);
3826                         if (intel_dp->compliance.test_active)
3827                                 seq_puts(m, "1");
3828                         else
3829                                 seq_puts(m, "0");
3830                 } else
3831                         seq_puts(m, "0");
3832         }
3833         drm_connector_list_iter_end(&conn_iter);
3834
3835         return 0;
3836 }
3837
3838 static int i915_displayport_test_active_open(struct inode *inode,
3839                                              struct file *file)
3840 {
3841         struct drm_i915_private *dev_priv = inode->i_private;
3842
3843         return single_open(file, i915_displayport_test_active_show,
3844                            &dev_priv->drm);
3845 }
3846
3847 static const struct file_operations i915_displayport_test_active_fops = {
3848         .owner = THIS_MODULE,
3849         .open = i915_displayport_test_active_open,
3850         .read = seq_read,
3851         .llseek = seq_lseek,
3852         .release = single_release,
3853         .write = i915_displayport_test_active_write
3854 };
3855
3856 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3857 {
3858         struct drm_device *dev = m->private;
3859         struct drm_connector *connector;
3860         struct drm_connector_list_iter conn_iter;
3861         struct intel_dp *intel_dp;
3862
3863         drm_connector_list_iter_begin(dev, &conn_iter);
3864         drm_for_each_connector_iter(connector, &conn_iter) {
3865                 struct intel_encoder *encoder;
3866
3867                 if (connector->connector_type !=
3868                     DRM_MODE_CONNECTOR_DisplayPort)
3869                         continue;
3870
3871                 encoder = to_intel_encoder(connector->encoder);
3872                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3873                         continue;
3874
3875                 if (encoder && connector->status == connector_status_connected) {
3876                         intel_dp = enc_to_intel_dp(&encoder->base);
3877                         if (intel_dp->compliance.test_type ==
3878                             DP_TEST_LINK_EDID_READ)
3879                                 seq_printf(m, "%lx",
3880                                            intel_dp->compliance.test_data.edid);
3881                         else if (intel_dp->compliance.test_type ==
3882                                  DP_TEST_LINK_VIDEO_PATTERN) {
3883                                 seq_printf(m, "hdisplay: %d\n",
3884                                            intel_dp->compliance.test_data.hdisplay);
3885                                 seq_printf(m, "vdisplay: %d\n",
3886                                            intel_dp->compliance.test_data.vdisplay);
3887                                 seq_printf(m, "bpc: %u\n",
3888                                            intel_dp->compliance.test_data.bpc);
3889                         }
3890                 } else
3891                         seq_puts(m, "0");
3892         }
3893         drm_connector_list_iter_end(&conn_iter);
3894
3895         return 0;
3896 }
3897 static int i915_displayport_test_data_open(struct inode *inode,
3898                                            struct file *file)
3899 {
3900         struct drm_i915_private *dev_priv = inode->i_private;
3901
3902         return single_open(file, i915_displayport_test_data_show,
3903                            &dev_priv->drm);
3904 }
3905
3906 static const struct file_operations i915_displayport_test_data_fops = {
3907         .owner = THIS_MODULE,
3908         .open = i915_displayport_test_data_open,
3909         .read = seq_read,
3910         .llseek = seq_lseek,
3911         .release = single_release
3912 };
3913
3914 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3915 {
3916         struct drm_device *dev = m->private;
3917         struct drm_connector *connector;
3918         struct drm_connector_list_iter conn_iter;
3919         struct intel_dp *intel_dp;
3920
3921         drm_connector_list_iter_begin(dev, &conn_iter);
3922         drm_for_each_connector_iter(connector, &conn_iter) {
3923                 struct intel_encoder *encoder;
3924
3925                 if (connector->connector_type !=
3926                     DRM_MODE_CONNECTOR_DisplayPort)
3927                         continue;
3928
3929                 encoder = to_intel_encoder(connector->encoder);
3930                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3931                         continue;
3932
3933                 if (encoder && connector->status == connector_status_connected) {
3934                         intel_dp = enc_to_intel_dp(&encoder->base);
3935                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3936                 } else
3937                         seq_puts(m, "0");
3938         }
3939         drm_connector_list_iter_end(&conn_iter);
3940
3941         return 0;
3942 }
3943
3944 static int i915_displayport_test_type_open(struct inode *inode,
3945                                        struct file *file)
3946 {
3947         struct drm_i915_private *dev_priv = inode->i_private;
3948
3949         return single_open(file, i915_displayport_test_type_show,
3950                            &dev_priv->drm);
3951 }
3952
3953 static const struct file_operations i915_displayport_test_type_fops = {
3954         .owner = THIS_MODULE,
3955         .open = i915_displayport_test_type_open,
3956         .read = seq_read,
3957         .llseek = seq_lseek,
3958         .release = single_release
3959 };
3960
3961 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3962 {
3963         struct drm_i915_private *dev_priv = m->private;
3964         struct drm_device *dev = &dev_priv->drm;
3965         int level;
3966         int num_levels;
3967
3968         if (IS_CHERRYVIEW(dev_priv))
3969                 num_levels = 3;
3970         else if (IS_VALLEYVIEW(dev_priv))
3971                 num_levels = 1;
3972         else if (IS_G4X(dev_priv))
3973                 num_levels = 3;
3974         else
3975                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3976
3977         drm_modeset_lock_all(dev);
3978
3979         for (level = 0; level < num_levels; level++) {
3980                 unsigned int latency = wm[level];
3981
3982                 /*
3983                  * - WM1+ latency values in 0.5us units
3984                  * - latencies are in us on gen9/vlv/chv
3985                  */
3986                 if (INTEL_GEN(dev_priv) >= 9 ||
3987                     IS_VALLEYVIEW(dev_priv) ||
3988                     IS_CHERRYVIEW(dev_priv) ||
3989                     IS_G4X(dev_priv))
3990                         latency *= 10;
3991                 else if (level > 0)
3992                         latency *= 5;
3993
3994                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3995                            level, wm[level], latency / 10, latency % 10);
3996         }
3997
3998         drm_modeset_unlock_all(dev);
3999 }
4000
4001 static int pri_wm_latency_show(struct seq_file *m, void *data)
4002 {
4003         struct drm_i915_private *dev_priv = m->private;
4004         const uint16_t *latencies;
4005
4006         if (INTEL_GEN(dev_priv) >= 9)
4007                 latencies = dev_priv->wm.skl_latency;
4008         else
4009                 latencies = dev_priv->wm.pri_latency;
4010
4011         wm_latency_show(m, latencies);
4012
4013         return 0;
4014 }
4015
4016 static int spr_wm_latency_show(struct seq_file *m, void *data)
4017 {
4018         struct drm_i915_private *dev_priv = m->private;
4019         const uint16_t *latencies;
4020
4021         if (INTEL_GEN(dev_priv) >= 9)
4022                 latencies = dev_priv->wm.skl_latency;
4023         else
4024                 latencies = dev_priv->wm.spr_latency;
4025
4026         wm_latency_show(m, latencies);
4027
4028         return 0;
4029 }
4030
4031 static int cur_wm_latency_show(struct seq_file *m, void *data)
4032 {
4033         struct drm_i915_private *dev_priv = m->private;
4034         const uint16_t *latencies;
4035
4036         if (INTEL_GEN(dev_priv) >= 9)
4037                 latencies = dev_priv->wm.skl_latency;
4038         else
4039                 latencies = dev_priv->wm.cur_latency;
4040
4041         wm_latency_show(m, latencies);
4042
4043         return 0;
4044 }
4045
4046 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4047 {
4048         struct drm_i915_private *dev_priv = inode->i_private;
4049
4050         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
4051                 return -ENODEV;
4052
4053         return single_open(file, pri_wm_latency_show, dev_priv);
4054 }
4055
4056 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4057 {
4058         struct drm_i915_private *dev_priv = inode->i_private;
4059
4060         if (HAS_GMCH_DISPLAY(dev_priv))
4061                 return -ENODEV;
4062
4063         return single_open(file, spr_wm_latency_show, dev_priv);
4064 }
4065
4066 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4067 {
4068         struct drm_i915_private *dev_priv = inode->i_private;
4069
4070         if (HAS_GMCH_DISPLAY(dev_priv))
4071                 return -ENODEV;
4072
4073         return single_open(file, cur_wm_latency_show, dev_priv);
4074 }
4075
4076 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4077                                 size_t len, loff_t *offp, uint16_t wm[8])
4078 {
4079         struct seq_file *m = file->private_data;
4080         struct drm_i915_private *dev_priv = m->private;
4081         struct drm_device *dev = &dev_priv->drm;
4082         uint16_t new[8] = { 0 };
4083         int num_levels;
4084         int level;
4085         int ret;
4086         char tmp[32];
4087
4088         if (IS_CHERRYVIEW(dev_priv))
4089                 num_levels = 3;
4090         else if (IS_VALLEYVIEW(dev_priv))
4091                 num_levels = 1;
4092         else if (IS_G4X(dev_priv))
4093                 num_levels = 3;
4094         else
4095                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4096
4097         if (len >= sizeof(tmp))
4098                 return -EINVAL;
4099
4100         if (copy_from_user(tmp, ubuf, len))
4101                 return -EFAULT;
4102
4103         tmp[len] = '\0';
4104
4105         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4106                      &new[0], &new[1], &new[2], &new[3],
4107                      &new[4], &new[5], &new[6], &new[7]);
4108         if (ret != num_levels)
4109                 return -EINVAL;
4110
4111         drm_modeset_lock_all(dev);
4112
4113         for (level = 0; level < num_levels; level++)
4114                 wm[level] = new[level];
4115
4116         drm_modeset_unlock_all(dev);
4117
4118         return len;
4119 }
4120
4121
4122 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4123                                     size_t len, loff_t *offp)
4124 {
4125         struct seq_file *m = file->private_data;
4126         struct drm_i915_private *dev_priv = m->private;
4127         uint16_t *latencies;
4128
4129         if (INTEL_GEN(dev_priv) >= 9)
4130                 latencies = dev_priv->wm.skl_latency;
4131         else
4132                 latencies = dev_priv->wm.pri_latency;
4133
4134         return wm_latency_write(file, ubuf, len, offp, latencies);
4135 }
4136
4137 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4138                                     size_t len, loff_t *offp)
4139 {
4140         struct seq_file *m = file->private_data;
4141         struct drm_i915_private *dev_priv = m->private;
4142         uint16_t *latencies;
4143
4144         if (INTEL_GEN(dev_priv) >= 9)
4145                 latencies = dev_priv->wm.skl_latency;
4146         else
4147                 latencies = dev_priv->wm.spr_latency;
4148
4149         return wm_latency_write(file, ubuf, len, offp, latencies);
4150 }
4151
4152 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4153                                     size_t len, loff_t *offp)
4154 {
4155         struct seq_file *m = file->private_data;
4156         struct drm_i915_private *dev_priv = m->private;
4157         uint16_t *latencies;
4158
4159         if (INTEL_GEN(dev_priv) >= 9)
4160                 latencies = dev_priv->wm.skl_latency;
4161         else
4162                 latencies = dev_priv->wm.cur_latency;
4163
4164         return wm_latency_write(file, ubuf, len, offp, latencies);
4165 }
4166
4167 static const struct file_operations i915_pri_wm_latency_fops = {
4168         .owner = THIS_MODULE,
4169         .open = pri_wm_latency_open,
4170         .read = seq_read,
4171         .llseek = seq_lseek,
4172         .release = single_release,
4173         .write = pri_wm_latency_write
4174 };
4175
4176 static const struct file_operations i915_spr_wm_latency_fops = {
4177         .owner = THIS_MODULE,
4178         .open = spr_wm_latency_open,
4179         .read = seq_read,
4180         .llseek = seq_lseek,
4181         .release = single_release,
4182         .write = spr_wm_latency_write
4183 };
4184
4185 static const struct file_operations i915_cur_wm_latency_fops = {
4186         .owner = THIS_MODULE,
4187         .open = cur_wm_latency_open,
4188         .read = seq_read,
4189         .llseek = seq_lseek,
4190         .release = single_release,
4191         .write = cur_wm_latency_write
4192 };
4193
4194 static int
4195 i915_wedged_get(void *data, u64 *val)
4196 {
4197         struct drm_i915_private *dev_priv = data;
4198
4199         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4200
4201         return 0;
4202 }
4203
4204 static int
4205 i915_wedged_set(void *data, u64 val)
4206 {
4207         struct drm_i915_private *i915 = data;
4208         struct intel_engine_cs *engine;
4209         unsigned int tmp;
4210
4211         /*
4212          * There is no safeguard against this debugfs entry colliding
4213          * with the hangcheck calling same i915_handle_error() in
4214          * parallel, causing an explosion. For now we assume that the
4215          * test harness is responsible enough not to inject gpu hangs
4216          * while it is writing to 'i915_wedged'
4217          */
4218
4219         if (i915_reset_backoff(&i915->gpu_error))
4220                 return -EAGAIN;
4221
4222         for_each_engine_masked(engine, i915, val, tmp) {
4223                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4224                 engine->hangcheck.stalled = true;
4225         }
4226
4227         i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4228
4229         wait_on_bit(&i915->gpu_error.flags,
4230                     I915_RESET_HANDOFF,
4231                     TASK_UNINTERRUPTIBLE);
4232
4233         return 0;
4234 }
4235
4236 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4237                         i915_wedged_get, i915_wedged_set,
4238                         "%llu\n");
4239
4240 static int
4241 fault_irq_set(struct drm_i915_private *i915,
4242               unsigned long *irq,
4243               unsigned long val)
4244 {
4245         int err;
4246
4247         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4248         if (err)
4249                 return err;
4250
4251         err = i915_gem_wait_for_idle(i915,
4252                                      I915_WAIT_LOCKED |
4253                                      I915_WAIT_INTERRUPTIBLE);
4254         if (err)
4255                 goto err_unlock;
4256
4257         *irq = val;
4258         mutex_unlock(&i915->drm.struct_mutex);
4259
4260         /* Flush idle worker to disarm irq */
4261         while (flush_delayed_work(&i915->gt.idle_work))
4262                 ;
4263
4264         return 0;
4265
4266 err_unlock:
4267         mutex_unlock(&i915->drm.struct_mutex);
4268         return err;
4269 }
4270
4271 static int
4272 i915_ring_missed_irq_get(void *data, u64 *val)
4273 {
4274         struct drm_i915_private *dev_priv = data;
4275
4276         *val = dev_priv->gpu_error.missed_irq_rings;
4277         return 0;
4278 }
4279
4280 static int
4281 i915_ring_missed_irq_set(void *data, u64 val)
4282 {
4283         struct drm_i915_private *i915 = data;
4284
4285         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4286 }
4287
4288 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4289                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4290                         "0x%08llx\n");
4291
4292 static int
4293 i915_ring_test_irq_get(void *data, u64 *val)
4294 {
4295         struct drm_i915_private *dev_priv = data;
4296
4297         *val = dev_priv->gpu_error.test_irq_rings;
4298
4299         return 0;
4300 }
4301
4302 static int
4303 i915_ring_test_irq_set(void *data, u64 val)
4304 {
4305         struct drm_i915_private *i915 = data;
4306
4307         val &= INTEL_INFO(i915)->ring_mask;
4308         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4309
4310         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4311 }
4312
4313 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4314                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4315                         "0x%08llx\n");
4316
4317 #define DROP_UNBOUND 0x1
4318 #define DROP_BOUND 0x2
4319 #define DROP_RETIRE 0x4
4320 #define DROP_ACTIVE 0x8
4321 #define DROP_FREED 0x10
4322 #define DROP_SHRINK_ALL 0x20
4323 #define DROP_ALL (DROP_UNBOUND  | \
4324                   DROP_BOUND    | \
4325                   DROP_RETIRE   | \
4326                   DROP_ACTIVE   | \
4327                   DROP_FREED    | \
4328                   DROP_SHRINK_ALL)
4329 static int
4330 i915_drop_caches_get(void *data, u64 *val)
4331 {
4332         *val = DROP_ALL;
4333
4334         return 0;
4335 }
4336
4337 static int
4338 i915_drop_caches_set(void *data, u64 val)
4339 {
4340         struct drm_i915_private *dev_priv = data;
4341         struct drm_device *dev = &dev_priv->drm;
4342         int ret = 0;
4343
4344         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4345
4346         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4347          * on ioctls on -EAGAIN. */
4348         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4349                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4350                 if (ret)
4351                         return ret;
4352
4353                 if (val & DROP_ACTIVE)
4354                         ret = i915_gem_wait_for_idle(dev_priv,
4355                                                      I915_WAIT_INTERRUPTIBLE |
4356                                                      I915_WAIT_LOCKED);
4357
4358                 if (val & DROP_RETIRE)
4359                         i915_gem_retire_requests(dev_priv);
4360
4361                 mutex_unlock(&dev->struct_mutex);
4362         }
4363
4364         fs_reclaim_acquire(GFP_KERNEL);
4365         if (val & DROP_BOUND)
4366                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4367
4368         if (val & DROP_UNBOUND)
4369                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4370
4371         if (val & DROP_SHRINK_ALL)
4372                 i915_gem_shrink_all(dev_priv);
4373         fs_reclaim_release(GFP_KERNEL);
4374
4375         if (val & DROP_FREED) {
4376                 synchronize_rcu();
4377                 i915_gem_drain_freed_objects(dev_priv);
4378         }
4379
4380         return ret;
4381 }
4382
4383 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4384                         i915_drop_caches_get, i915_drop_caches_set,
4385                         "0x%08llx\n");
4386
4387 static int
4388 i915_max_freq_get(void *data, u64 *val)
4389 {
4390         struct drm_i915_private *dev_priv = data;
4391
4392         if (INTEL_GEN(dev_priv) < 6)
4393                 return -ENODEV;
4394
4395         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4396         return 0;
4397 }
4398
4399 static int
4400 i915_max_freq_set(void *data, u64 val)
4401 {
4402         struct drm_i915_private *dev_priv = data;
4403         u32 hw_max, hw_min;
4404         int ret;
4405
4406         if (INTEL_GEN(dev_priv) < 6)
4407                 return -ENODEV;
4408
4409         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4410
4411         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4412         if (ret)
4413                 return ret;
4414
4415         /*
4416          * Turbo will still be enabled, but won't go above the set value.
4417          */
4418         val = intel_freq_opcode(dev_priv, val);
4419
4420         hw_max = dev_priv->rps.max_freq;
4421         hw_min = dev_priv->rps.min_freq;
4422
4423         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4424                 mutex_unlock(&dev_priv->rps.hw_lock);
4425                 return -EINVAL;
4426         }
4427
4428         dev_priv->rps.max_freq_softlimit = val;
4429
4430         if (intel_set_rps(dev_priv, val))
4431                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4432
4433         mutex_unlock(&dev_priv->rps.hw_lock);
4434
4435         return 0;
4436 }
4437
4438 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4439                         i915_max_freq_get, i915_max_freq_set,
4440                         "%llu\n");
4441
4442 static int
4443 i915_min_freq_get(void *data, u64 *val)
4444 {
4445         struct drm_i915_private *dev_priv = data;
4446
4447         if (INTEL_GEN(dev_priv) < 6)
4448                 return -ENODEV;
4449
4450         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4451         return 0;
4452 }
4453
4454 static int
4455 i915_min_freq_set(void *data, u64 val)
4456 {
4457         struct drm_i915_private *dev_priv = data;
4458         u32 hw_max, hw_min;
4459         int ret;
4460
4461         if (INTEL_GEN(dev_priv) < 6)
4462                 return -ENODEV;
4463
4464         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4465
4466         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4467         if (ret)
4468                 return ret;
4469
4470         /*
4471          * Turbo will still be enabled, but won't go below the set value.
4472          */
4473         val = intel_freq_opcode(dev_priv, val);
4474
4475         hw_max = dev_priv->rps.max_freq;
4476         hw_min = dev_priv->rps.min_freq;
4477
4478         if (val < hw_min ||
4479             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4480                 mutex_unlock(&dev_priv->rps.hw_lock);
4481                 return -EINVAL;
4482         }
4483
4484         dev_priv->rps.min_freq_softlimit = val;
4485
4486         if (intel_set_rps(dev_priv, val))
4487                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4488
4489         mutex_unlock(&dev_priv->rps.hw_lock);
4490
4491         return 0;
4492 }
4493
4494 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4495                         i915_min_freq_get, i915_min_freq_set,
4496                         "%llu\n");
4497
4498 static int
4499 i915_cache_sharing_get(void *data, u64 *val)
4500 {
4501         struct drm_i915_private *dev_priv = data;
4502         u32 snpcr;
4503
4504         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4505                 return -ENODEV;
4506
4507         intel_runtime_pm_get(dev_priv);
4508
4509         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4510
4511         intel_runtime_pm_put(dev_priv);
4512
4513         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4514
4515         return 0;
4516 }
4517
4518 static int
4519 i915_cache_sharing_set(void *data, u64 val)
4520 {
4521         struct drm_i915_private *dev_priv = data;
4522         u32 snpcr;
4523
4524         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4525                 return -ENODEV;
4526
4527         if (val > 3)
4528                 return -EINVAL;
4529
4530         intel_runtime_pm_get(dev_priv);
4531         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4532
4533         /* Update the cache sharing policy here as well */
4534         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4535         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4536         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4537         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4538
4539         intel_runtime_pm_put(dev_priv);
4540         return 0;
4541 }
4542
4543 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4544                         i915_cache_sharing_get, i915_cache_sharing_set,
4545                         "%llu\n");
4546
4547 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4548                                           struct sseu_dev_info *sseu)
4549 {
4550         int ss_max = 2;
4551         int ss;
4552         u32 sig1[ss_max], sig2[ss_max];
4553
4554         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4555         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4556         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4557         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4558
4559         for (ss = 0; ss < ss_max; ss++) {
4560                 unsigned int eu_cnt;
4561
4562                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4563                         /* skip disabled subslice */
4564                         continue;
4565
4566                 sseu->slice_mask = BIT(0);
4567                 sseu->subslice_mask |= BIT(ss);
4568                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4569                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4570                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4571                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4572                 sseu->eu_total += eu_cnt;
4573                 sseu->eu_per_subslice = max_t(unsigned int,
4574                                               sseu->eu_per_subslice, eu_cnt);
4575         }
4576 }
4577
4578 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4579                                     struct sseu_dev_info *sseu)
4580 {
4581         int s_max = 3, ss_max = 4;
4582         int s, ss;
4583         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4584
4585         /* BXT has a single slice and at most 3 subslices. */
4586         if (IS_GEN9_LP(dev_priv)) {
4587                 s_max = 1;
4588                 ss_max = 3;
4589         }
4590
4591         for (s = 0; s < s_max; s++) {
4592                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4593                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4594                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4595         }
4596
4597         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4598                      GEN9_PGCTL_SSA_EU19_ACK |
4599                      GEN9_PGCTL_SSA_EU210_ACK |
4600                      GEN9_PGCTL_SSA_EU311_ACK;
4601         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4602                      GEN9_PGCTL_SSB_EU19_ACK |
4603                      GEN9_PGCTL_SSB_EU210_ACK |
4604                      GEN9_PGCTL_SSB_EU311_ACK;
4605
4606         for (s = 0; s < s_max; s++) {
4607                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4608                         /* skip disabled slice */
4609                         continue;
4610
4611                 sseu->slice_mask |= BIT(s);
4612
4613                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
4614                         sseu->subslice_mask =
4615                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4616
4617                 for (ss = 0; ss < ss_max; ss++) {
4618                         unsigned int eu_cnt;
4619
4620                         if (IS_GEN9_LP(dev_priv)) {
4621                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4622                                         /* skip disabled subslice */
4623                                         continue;
4624
4625                                 sseu->subslice_mask |= BIT(ss);
4626                         }
4627
4628                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4629                                                eu_mask[ss%2]);
4630                         sseu->eu_total += eu_cnt;
4631                         sseu->eu_per_subslice = max_t(unsigned int,
4632                                                       sseu->eu_per_subslice,
4633                                                       eu_cnt);
4634                 }
4635         }
4636 }
4637
4638 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4639                                          struct sseu_dev_info *sseu)
4640 {
4641         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4642         int s;
4643
4644         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4645
4646         if (sseu->slice_mask) {
4647                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4648                 sseu->eu_per_subslice =
4649                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4650                 sseu->eu_total = sseu->eu_per_subslice *
4651                                  sseu_subslice_total(sseu);
4652
4653                 /* subtract fused off EU(s) from enabled slice(s) */
4654                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4655                         u8 subslice_7eu =
4656                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4657
4658                         sseu->eu_total -= hweight8(subslice_7eu);
4659                 }
4660         }
4661 }
4662
4663 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4664                                  const struct sseu_dev_info *sseu)
4665 {
4666         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4667         const char *type = is_available_info ? "Available" : "Enabled";
4668
4669         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4670                    sseu->slice_mask);
4671         seq_printf(m, "  %s Slice Total: %u\n", type,
4672                    hweight8(sseu->slice_mask));
4673         seq_printf(m, "  %s Subslice Total: %u\n", type,
4674                    sseu_subslice_total(sseu));
4675         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4676                    sseu->subslice_mask);
4677         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4678                    hweight8(sseu->subslice_mask));
4679         seq_printf(m, "  %s EU Total: %u\n", type,
4680                    sseu->eu_total);
4681         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4682                    sseu->eu_per_subslice);
4683
4684         if (!is_available_info)
4685                 return;
4686
4687         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4688         if (HAS_POOLED_EU(dev_priv))
4689                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4690
4691         seq_printf(m, "  Has Slice Power Gating: %s\n",
4692                    yesno(sseu->has_slice_pg));
4693         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4694                    yesno(sseu->has_subslice_pg));
4695         seq_printf(m, "  Has EU Power Gating: %s\n",
4696                    yesno(sseu->has_eu_pg));
4697 }
4698
4699 static int i915_sseu_status(struct seq_file *m, void *unused)
4700 {
4701         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4702         struct sseu_dev_info sseu;
4703
4704         if (INTEL_GEN(dev_priv) < 8)
4705                 return -ENODEV;
4706
4707         seq_puts(m, "SSEU Device Info\n");
4708         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4709
4710         seq_puts(m, "SSEU Device Status\n");
4711         memset(&sseu, 0, sizeof(sseu));
4712
4713         intel_runtime_pm_get(dev_priv);
4714
4715         if (IS_CHERRYVIEW(dev_priv)) {
4716                 cherryview_sseu_device_status(dev_priv, &sseu);
4717         } else if (IS_BROADWELL(dev_priv)) {
4718                 broadwell_sseu_device_status(dev_priv, &sseu);
4719         } else if (INTEL_GEN(dev_priv) >= 9) {
4720                 gen9_sseu_device_status(dev_priv, &sseu);
4721         }
4722
4723         intel_runtime_pm_put(dev_priv);
4724
4725         i915_print_sseu_info(m, false, &sseu);
4726
4727         return 0;
4728 }
4729
4730 static int i915_forcewake_open(struct inode *inode, struct file *file)
4731 {
4732         struct drm_i915_private *i915 = inode->i_private;
4733
4734         if (INTEL_GEN(i915) < 6)
4735                 return 0;
4736
4737         intel_runtime_pm_get(i915);
4738         intel_uncore_forcewake_user_get(i915);
4739
4740         return 0;
4741 }
4742
4743 static int i915_forcewake_release(struct inode *inode, struct file *file)
4744 {
4745         struct drm_i915_private *i915 = inode->i_private;
4746
4747         if (INTEL_GEN(i915) < 6)
4748                 return 0;
4749
4750         intel_uncore_forcewake_user_put(i915);
4751         intel_runtime_pm_put(i915);
4752
4753         return 0;
4754 }
4755
4756 static const struct file_operations i915_forcewake_fops = {
4757         .owner = THIS_MODULE,
4758         .open = i915_forcewake_open,
4759         .release = i915_forcewake_release,
4760 };
4761
4762 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4763 {
4764         struct drm_i915_private *dev_priv = m->private;
4765         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4766
4767         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4768         seq_printf(m, "Detected: %s\n",
4769                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4770
4771         return 0;
4772 }
4773
4774 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4775                                         const char __user *ubuf, size_t len,
4776                                         loff_t *offp)
4777 {
4778         struct seq_file *m = file->private_data;
4779         struct drm_i915_private *dev_priv = m->private;
4780         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4781         unsigned int new_threshold;
4782         int i;
4783         char *newline;
4784         char tmp[16];
4785
4786         if (len >= sizeof(tmp))
4787                 return -EINVAL;
4788
4789         if (copy_from_user(tmp, ubuf, len))
4790                 return -EFAULT;
4791
4792         tmp[len] = '\0';
4793
4794         /* Strip newline, if any */
4795         newline = strchr(tmp, '\n');
4796         if (newline)
4797                 *newline = '\0';
4798
4799         if (strcmp(tmp, "reset") == 0)
4800                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4801         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4802                 return -EINVAL;
4803
4804         if (new_threshold > 0)
4805                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4806                               new_threshold);
4807         else
4808                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4809
4810         spin_lock_irq(&dev_priv->irq_lock);
4811         hotplug->hpd_storm_threshold = new_threshold;
4812         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4813         for_each_hpd_pin(i)
4814                 hotplug->stats[i].count = 0;
4815         spin_unlock_irq(&dev_priv->irq_lock);
4816
4817         /* Re-enable hpd immediately if we were in an irq storm */
4818         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4819
4820         return len;
4821 }
4822
4823 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4824 {
4825         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4826 }
4827
4828 static const struct file_operations i915_hpd_storm_ctl_fops = {
4829         .owner = THIS_MODULE,
4830         .open = i915_hpd_storm_ctl_open,
4831         .read = seq_read,
4832         .llseek = seq_lseek,
4833         .release = single_release,
4834         .write = i915_hpd_storm_ctl_write
4835 };
4836
4837 static const struct drm_info_list i915_debugfs_list[] = {
4838         {"i915_capabilities", i915_capabilities, 0},
4839         {"i915_gem_objects", i915_gem_object_info, 0},
4840         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4841         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4842         {"i915_gem_stolen", i915_gem_stolen_list_info },
4843         {"i915_gem_request", i915_gem_request_info, 0},
4844         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4845         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4846         {"i915_gem_interrupt", i915_interrupt_info, 0},
4847         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4848         {"i915_guc_info", i915_guc_info, 0},
4849         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4850         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4851         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4852         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4853         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4854         {"i915_frequency_info", i915_frequency_info, 0},
4855         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4856         {"i915_reset_info", i915_reset_info, 0},
4857         {"i915_drpc_info", i915_drpc_info, 0},
4858         {"i915_emon_status", i915_emon_status, 0},
4859         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4860         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4861         {"i915_fbc_status", i915_fbc_status, 0},
4862         {"i915_ips_status", i915_ips_status, 0},
4863         {"i915_sr_status", i915_sr_status, 0},
4864         {"i915_opregion", i915_opregion, 0},
4865         {"i915_vbt", i915_vbt, 0},
4866         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4867         {"i915_context_status", i915_context_status, 0},
4868         {"i915_dump_lrc", i915_dump_lrc, 0},
4869         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4870         {"i915_swizzle_info", i915_swizzle_info, 0},
4871         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4872         {"i915_llc", i915_llc, 0},
4873         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4874         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4875         {"i915_energy_uJ", i915_energy_uJ, 0},
4876         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4877         {"i915_power_domain_info", i915_power_domain_info, 0},
4878         {"i915_dmc_info", i915_dmc_info, 0},
4879         {"i915_display_info", i915_display_info, 0},
4880         {"i915_engine_info", i915_engine_info, 0},
4881         {"i915_semaphore_status", i915_semaphore_status, 0},
4882         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4883         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4884         {"i915_wa_registers", i915_wa_registers, 0},
4885         {"i915_ddb_info", i915_ddb_info, 0},
4886         {"i915_sseu_status", i915_sseu_status, 0},
4887         {"i915_drrs_status", i915_drrs_status, 0},
4888         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4889 };
4890 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4891
4892 static const struct i915_debugfs_files {
4893         const char *name;
4894         const struct file_operations *fops;
4895 } i915_debugfs_files[] = {
4896         {"i915_wedged", &i915_wedged_fops},
4897         {"i915_max_freq", &i915_max_freq_fops},
4898         {"i915_min_freq", &i915_min_freq_fops},
4899         {"i915_cache_sharing", &i915_cache_sharing_fops},
4900         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4901         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4902         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4903 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4904         {"i915_error_state", &i915_error_state_fops},
4905         {"i915_gpu_info", &i915_gpu_info_fops},
4906 #endif
4907         {"i915_next_seqno", &i915_next_seqno_fops},
4908         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4909         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4910         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4911         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4912         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4913         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4914         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4915         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4916         {"i915_guc_log_control", &i915_guc_log_control_fops},
4917         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4918         {"i915_ipc_status", &i915_ipc_status_fops}
4919 };
4920
4921 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4922 {
4923         struct drm_minor *minor = dev_priv->drm.primary;
4924         struct dentry *ent;
4925         int ret, i;
4926
4927         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4928                                   minor->debugfs_root, to_i915(minor->dev),
4929                                   &i915_forcewake_fops);
4930         if (!ent)
4931                 return -ENOMEM;
4932
4933         ret = intel_pipe_crc_create(minor);
4934         if (ret)
4935                 return ret;
4936
4937         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4938                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4939                                           S_IRUGO | S_IWUSR,
4940                                           minor->debugfs_root,
4941                                           to_i915(minor->dev),
4942                                           i915_debugfs_files[i].fops);
4943                 if (!ent)
4944                         return -ENOMEM;
4945         }
4946
4947         return drm_debugfs_create_files(i915_debugfs_list,
4948                                         I915_DEBUGFS_ENTRIES,
4949                                         minor->debugfs_root, minor);
4950 }
4951
4952 struct dpcd_block {
4953         /* DPCD dump start address. */
4954         unsigned int offset;
4955         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4956         unsigned int end;
4957         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4958         size_t size;
4959         /* Only valid for eDP. */
4960         bool edp;
4961 };
4962
4963 static const struct dpcd_block i915_dpcd_debug[] = {
4964         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4965         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4966         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4967         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4968         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4969         { .offset = DP_SET_POWER },
4970         { .offset = DP_EDP_DPCD_REV },
4971         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4972         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4973         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4974 };
4975
4976 static int i915_dpcd_show(struct seq_file *m, void *data)
4977 {
4978         struct drm_connector *connector = m->private;
4979         struct intel_dp *intel_dp =
4980                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4981         uint8_t buf[16];
4982         ssize_t err;
4983         int i;
4984
4985         if (connector->status != connector_status_connected)
4986                 return -ENODEV;
4987
4988         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4989                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4990                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4991
4992                 if (b->edp &&
4993                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4994                         continue;
4995
4996                 /* low tech for now */
4997                 if (WARN_ON(size > sizeof(buf)))
4998                         continue;
4999
5000                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5001                 if (err <= 0) {
5002                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5003                                   size, b->offset, err);
5004                         continue;
5005                 }
5006
5007                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5008         }
5009
5010         return 0;
5011 }
5012
5013 static int i915_dpcd_open(struct inode *inode, struct file *file)
5014 {
5015         return single_open(file, i915_dpcd_show, inode->i_private);
5016 }
5017
5018 static const struct file_operations i915_dpcd_fops = {
5019         .owner = THIS_MODULE,
5020         .open = i915_dpcd_open,
5021         .read = seq_read,
5022         .llseek = seq_lseek,
5023         .release = single_release,
5024 };
5025
5026 static int i915_panel_show(struct seq_file *m, void *data)
5027 {
5028         struct drm_connector *connector = m->private;
5029         struct intel_dp *intel_dp =
5030                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5031
5032         if (connector->status != connector_status_connected)
5033                 return -ENODEV;
5034
5035         seq_printf(m, "Panel power up delay: %d\n",
5036                    intel_dp->panel_power_up_delay);
5037         seq_printf(m, "Panel power down delay: %d\n",
5038                    intel_dp->panel_power_down_delay);
5039         seq_printf(m, "Backlight on delay: %d\n",
5040                    intel_dp->backlight_on_delay);
5041         seq_printf(m, "Backlight off delay: %d\n",
5042                    intel_dp->backlight_off_delay);
5043
5044         return 0;
5045 }
5046
5047 static int i915_panel_open(struct inode *inode, struct file *file)
5048 {
5049         return single_open(file, i915_panel_show, inode->i_private);
5050 }
5051
5052 static const struct file_operations i915_panel_fops = {
5053         .owner = THIS_MODULE,
5054         .open = i915_panel_open,
5055         .read = seq_read,
5056         .llseek = seq_lseek,
5057         .release = single_release,
5058 };
5059
5060 /**
5061  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5062  * @connector: pointer to a registered drm_connector
5063  *
5064  * Cleanup will be done by drm_connector_unregister() through a call to
5065  * drm_debugfs_connector_remove().
5066  *
5067  * Returns 0 on success, negative error codes on error.
5068  */
5069 int i915_debugfs_connector_add(struct drm_connector *connector)
5070 {
5071         struct dentry *root = connector->debugfs_entry;
5072
5073         /* The connector must have been registered beforehands. */
5074         if (!root)
5075                 return -ENODEV;
5076
5077         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5078             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5079                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5080                                     connector, &i915_dpcd_fops);
5081
5082         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5083                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5084                                     connector, &i915_panel_fops);
5085
5086         return 0;
5087 }