2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
37 #include "hypercall.h"
40 #include "interrupt.h"
45 #include "scheduler.h"
46 #include "sched_policy.h"
47 #include "mmio_context.h"
48 #include "cmd_parser.h"
49 #include "fb_decoder.h"
51 #include "page_track.h"
53 #define GVT_MAX_VGPU 8
55 struct intel_gvt_host {
59 struct intel_gvt_mpt *mpt;
62 extern struct intel_gvt_host intel_gvt_host;
64 /* Describe per-platform limitations. */
65 struct intel_gvt_device_info {
66 u32 max_support_vgpus;
70 unsigned long msi_cap_offset;
73 u32 gtt_entry_size_shift;
74 int gmadr_bytes_in_cmd;
78 /* GM resources owned by a vGPU */
79 struct intel_vgpu_gm {
82 struct drm_mm_node low_gm_node;
83 struct drm_mm_node high_gm_node;
86 #define INTEL_GVT_MAX_NUM_FENCES 32
88 /* Fences owned by a vGPU */
89 struct intel_vgpu_fence {
90 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
95 struct intel_vgpu_mmio {
99 #define INTEL_GVT_MAX_BAR_NUM 4
101 struct intel_vgpu_pci_bar {
106 struct intel_vgpu_cfg_space {
107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
111 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
113 struct intel_vgpu_irq {
114 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
115 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
116 INTEL_GVT_EVENT_MAX);
119 struct intel_vgpu_opregion {
122 u32 gfn[INTEL_GVT_OPREGION_PAGES];
125 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
127 struct intel_vgpu_display {
128 struct intel_vgpu_i2c_edid i2c_edid;
129 struct intel_vgpu_port ports[I915_MAX_PORTS];
130 struct intel_vgpu_sbi sbi;
133 struct vgpu_sched_ctl {
138 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
139 INTEL_VGPU_GUC_SUBMISSION,
142 struct intel_vgpu_submission_ops {
144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
149 struct intel_vgpu_submission {
150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
151 struct list_head workload_q_head[I915_NUM_ENGINES];
152 struct kmem_cache *workloads;
153 atomic_t running_workload_num;
154 struct i915_gem_context *shadow_ctx;
156 u64 i915_context_pml4;
157 u64 i915_context_pdps[GEN8_3LVL_PDPES];
159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
161 void *ring_scan_buffer[I915_NUM_ENGINES];
162 int ring_scan_buffer_size[I915_NUM_ENGINES];
163 const struct intel_vgpu_submission_ops *ops;
164 int virtual_submission_interface;
169 struct intel_gvt *gvt;
170 struct mutex vgpu_lock;
172 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
176 unsigned int resetting_eng;
178 /* Both sched_data and sched_ctl can be seen a part of the global gvt
179 * scheduler structure. So below 2 vgpu data are protected
180 * by sched_lock, not vgpu_lock.
183 struct vgpu_sched_ctl sched_ctl;
185 struct intel_vgpu_fence fence;
186 struct intel_vgpu_gm gm;
187 struct intel_vgpu_cfg_space cfg_space;
188 struct intel_vgpu_mmio mmio;
189 struct intel_vgpu_irq irq;
190 struct intel_vgpu_gtt gtt;
191 struct intel_vgpu_opregion opregion;
192 struct intel_vgpu_display display;
193 struct intel_vgpu_submission submission;
194 struct radix_tree_root page_track_tree;
195 u32 hws_pga[I915_NUM_ENGINES];
197 struct dentry *debugfs;
199 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
201 struct mdev_device *mdev;
202 struct vfio_region *region;
204 struct eventfd_ctx *intx_trigger;
205 struct eventfd_ctx *msi_trigger;
208 * Two caches are used to avoid mapping duplicated pages (eg.
209 * scratch pages). This help to reduce dma setup overhead.
211 struct rb_root gfn_cache;
212 struct rb_root dma_addr_cache;
213 unsigned long nr_cache_entries;
214 struct mutex cache_lock;
216 struct notifier_block iommu_notifier;
217 struct notifier_block group_notifier;
219 struct work_struct release_work;
221 struct vfio_device *vfio_device;
225 struct list_head dmabuf_obj_list_head;
226 struct mutex dmabuf_lock;
227 struct idr object_idr;
229 struct completion vblank_done;
234 /* validating GM healthy status*/
235 #define vgpu_is_vm_unhealthy(ret_val) \
236 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
238 struct intel_gvt_gm {
239 unsigned long vgpu_allocated_low_gm_size;
240 unsigned long vgpu_allocated_high_gm_size;
243 struct intel_gvt_fence {
244 unsigned long vgpu_allocated_fence_num;
247 /* Special MMIO blocks. */
248 struct gvt_mmio_block {
256 #define INTEL_GVT_MMIO_HASH_BITS 11
258 struct intel_gvt_mmio {
260 /* Register contains RO bits */
261 #define F_RO (1 << 0)
262 /* Register contains graphics address */
263 #define F_GMADR (1 << 1)
264 /* Mode mask registers with high 16 bits as the mask bits */
265 #define F_MODE_MASK (1 << 2)
266 /* This reg can be accessed by GPU commands */
267 #define F_CMD_ACCESS (1 << 3)
268 /* This reg has been accessed by a VM */
269 #define F_ACCESSED (1 << 4)
270 /* This reg has been accessed through GPU commands */
271 #define F_CMD_ACCESSED (1 << 5)
272 /* This reg could be accessed by unaligned address */
273 #define F_UNALIGN (1 << 6)
274 /* This reg is saved/restored in context */
275 #define F_IN_CTX (1 << 7)
277 struct gvt_mmio_block *mmio_block;
278 unsigned int num_mmio_block;
280 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
281 unsigned long num_tracked_mmio;
284 struct intel_gvt_firmware {
287 bool firmware_loaded;
290 #define NR_MAX_INTEL_VGPU_TYPES 20
291 struct intel_vgpu_type {
293 unsigned int avail_instance;
294 unsigned int low_gm_size;
295 unsigned int high_gm_size;
298 enum intel_vgpu_edid resolution;
302 /* GVT scope lock, protect GVT itself, and all resource currently
303 * not yet protected by special locks(vgpu and scheduler lock).
306 /* scheduler scope lock, protect gvt and vgpu schedule related data */
307 struct mutex sched_lock;
309 struct drm_i915_private *dev_priv;
310 struct idr vgpu_idr; /* vGPU IDR pool */
312 struct intel_gvt_device_info device_info;
313 struct intel_gvt_gm gm;
314 struct intel_gvt_fence fence;
315 struct intel_gvt_mmio mmio;
316 struct intel_gvt_firmware firmware;
317 struct intel_gvt_irq irq;
318 struct intel_gvt_gtt gtt;
319 struct intel_gvt_workload_scheduler scheduler;
320 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
321 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
322 struct intel_vgpu_type *types;
323 unsigned int num_types;
324 struct intel_vgpu *idle_vgpu;
326 struct task_struct *service_thread;
327 wait_queue_head_t service_thread_wq;
329 /* service_request is always used in bit operation, we should always
330 * use it with atomic bit ops so that no need to use gvt big lock.
332 unsigned long service_request;
335 struct engine_mmio *mmio;
336 int ctx_mmio_count[I915_NUM_ENGINES];
339 struct dentry *debugfs_root;
342 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
348 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
350 /* Scheduling trigger by timer */
351 INTEL_GVT_REQUEST_SCHED = 1,
353 /* Scheduling trigger by event */
354 INTEL_GVT_REQUEST_EVENT_SCHED = 2,
357 static inline void intel_gvt_request_service(struct intel_gvt *gvt,
360 set_bit(service, (void *)&gvt->service_request);
361 wake_up(&gvt->service_thread_wq);
364 void intel_gvt_free_firmware(struct intel_gvt *gvt);
365 int intel_gvt_load_firmware(struct intel_gvt *gvt);
367 /* Aperture/GM space definitions for GVT device */
368 #define MB_TO_BYTES(mb) ((mb) << 20ULL)
369 #define BYTES_TO_MB(b) ((b) >> 20ULL)
371 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
372 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
375 /* Aperture/GM space definitions for GVT device */
376 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
377 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)
379 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total)
380 #define gvt_ggtt_sz(gvt) \
381 ((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3)
382 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
384 #define gvt_aperture_gmadr_base(gvt) (0)
385 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
386 + gvt_aperture_sz(gvt) - 1)
388 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
389 + gvt_aperture_sz(gvt))
390 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
391 + gvt_hidden_sz(gvt) - 1)
393 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
395 /* Aperture/GM space definitions for vGPU */
396 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
397 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
398 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
399 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
401 #define vgpu_aperture_pa_base(vgpu) \
402 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
404 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
406 #define vgpu_aperture_pa_end(vgpu) \
407 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
409 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
410 #define vgpu_aperture_gmadr_end(vgpu) \
411 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
413 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
414 #define vgpu_hidden_gmadr_end(vgpu) \
415 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
417 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
418 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
420 struct intel_vgpu_creation_params {
422 __u64 low_gm_sz; /* in MB */
423 __u64 high_gm_sz; /* in MB */
432 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
433 struct intel_vgpu_creation_params *param);
434 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
435 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
436 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
437 u32 fence, u64 value);
439 /* Macros for easily accessing vGPU virtual/shadow register.
440 Explicitly seperate use for typed MMIO reg or real offset.*/
441 #define vgpu_vreg_t(vgpu, reg) \
442 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
443 #define vgpu_vreg(vgpu, offset) \
444 (*(u32 *)(vgpu->mmio.vreg + (offset)))
445 #define vgpu_vreg64_t(vgpu, reg) \
446 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
447 #define vgpu_vreg64(vgpu, offset) \
448 (*(u64 *)(vgpu->mmio.vreg + (offset)))
450 #define for_each_active_vgpu(gvt, vgpu, id) \
451 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
452 for_each_if(vgpu->active)
454 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
455 u32 offset, u32 val, bool low)
459 /* BAR offset should be 32 bits algiend */
460 offset = rounddown(offset, 4);
461 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
465 * only update bit 31 - bit 4,
466 * leave the bit 3 - bit 0 unchanged.
468 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
474 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
475 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
477 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
478 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
479 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
480 struct intel_vgpu_type *type);
481 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
482 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
483 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
484 intel_engine_mask_t engine_mask);
485 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
486 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
487 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
489 /* validating GM functions */
490 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \
491 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
492 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
494 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \
495 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
496 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
498 #define vgpu_gmadr_is_valid(vgpu, gmadr) \
499 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
500 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
502 #define gvt_gmadr_is_aperture(gvt, gmadr) \
503 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
504 (gmadr <= gvt_aperture_gmadr_end(gvt)))
506 #define gvt_gmadr_is_hidden(gvt, gmadr) \
507 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
508 (gmadr <= gvt_hidden_gmadr_end(gvt)))
510 #define gvt_gmadr_is_valid(gvt, gmadr) \
511 (gvt_gmadr_is_aperture(gvt, gmadr) || \
512 gvt_gmadr_is_hidden(gvt, gmadr))
514 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
515 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
516 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
517 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
518 unsigned long *h_index);
519 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
520 unsigned long *g_index);
522 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
524 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
526 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
527 void *p_data, unsigned int bytes);
529 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
530 void *p_data, unsigned int bytes);
532 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
534 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
536 /* We are 64bit bar. */
537 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
538 PCI_BASE_ADDRESS_MEM_MASK;
541 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
542 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
543 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
545 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
546 void populate_pvinfo_page(struct intel_vgpu *vgpu);
548 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
549 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
551 struct intel_gvt_ops {
552 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
554 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *,
556 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,
558 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,
560 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *,
561 struct intel_vgpu_type *);
562 void (*vgpu_destroy)(struct intel_vgpu *vgpu);
563 void (*vgpu_release)(struct intel_vgpu *vgpu);
564 void (*vgpu_reset)(struct intel_vgpu *);
565 void (*vgpu_activate)(struct intel_vgpu *);
566 void (*vgpu_deactivate)(struct intel_vgpu *);
567 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt,
569 bool (*get_gvt_attrs)(struct attribute ***type_attrs,
570 struct attribute_group ***intel_vgpu_type_groups);
571 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
572 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
573 int (*write_protect_handler)(struct intel_vgpu *, u64, void *,
575 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected);
580 GVT_FAILSAFE_UNSUPPORTED_GUEST,
581 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
582 GVT_FAILSAFE_GUEST_ERR,
585 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv)
587 intel_runtime_pm_get(dev_priv);
590 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv)
592 intel_runtime_pm_put_unchecked(dev_priv);
596 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
598 * @offset: register offset
601 static inline void intel_gvt_mmio_set_accessed(
602 struct intel_gvt *gvt, unsigned int offset)
604 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
608 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
610 * @offset: register offset
613 static inline bool intel_gvt_mmio_is_cmd_access(
614 struct intel_gvt *gvt, unsigned int offset)
616 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
620 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
622 * @offset: register offset
625 static inline bool intel_gvt_mmio_is_unalign(
626 struct intel_gvt *gvt, unsigned int offset)
628 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
632 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
634 * @offset: register offset
637 static inline void intel_gvt_mmio_set_cmd_accessed(
638 struct intel_gvt *gvt, unsigned int offset)
640 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED;
644 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
646 * @offset: register offset
649 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
652 static inline bool intel_gvt_mmio_has_mode_mask(
653 struct intel_gvt *gvt, unsigned int offset)
655 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
659 * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask
661 * @offset: register offset
664 * True if a MMIO has a in-context mask, false if it isn't.
667 static inline bool intel_gvt_mmio_is_in_ctx(
668 struct intel_gvt *gvt, unsigned int offset)
670 return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX;
674 * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context
676 * @offset: register offset
679 static inline void intel_gvt_mmio_set_in_ctx(
680 struct intel_gvt *gvt, unsigned int offset)
682 gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
685 int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
686 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
687 int intel_gvt_debugfs_init(struct intel_gvt *gvt);
688 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);